avr32_eth.h

00001 /**
00002  * @file avr32_eth.h
00003  * @brief AVR32 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _AVR32_ETH_H
00030 #define _AVR32_ETH_H
00031 
00032 //Number of TX buffers
00033 #ifndef AVR32_ETH_TX_BUFFER_COUNT
00034    #define AVR32_ETH_TX_BUFFER_COUNT 2
00035 #elif (AVR32_ETH_TX_BUFFER_COUNT < 1)
00036    #error AVR32_ETH_TX_BUFFER_COUNT parameter is not valid
00037 #endif
00038 
00039 //TX buffer size
00040 #ifndef AVR32_ETH_TX_BUFFER_SIZE
00041    #define AVR32_ETH_TX_BUFFER_SIZE 1536
00042 #elif (AVR32_ETH_TX_BUFFER_SIZE != 1536)
00043    #error AVR32_ETH_TX_BUFFER_SIZE parameter is not valid
00044 #endif
00045 
00046 //Number of RX buffers
00047 #ifndef AVR32_ETH_RX_BUFFER_COUNT
00048    #define AVR32_ETH_RX_BUFFER_COUNT 48
00049 #elif (AVR32_ETH_RX_BUFFER_COUNT < 12)
00050    #error AVR32_ETH_RX_BUFFER_COUNT parameter is not valid
00051 #endif
00052 
00053 //RX buffer size
00054 #ifndef AVR32_ETH_RX_BUFFER_SIZE
00055    #define AVR32_ETH_RX_BUFFER_SIZE 128
00056 #elif (AVR32_ETH_RX_BUFFER_SIZE != 128)
00057    #error AVR32_ETH_RX_BUFFER_SIZE parameter is not valid
00058 #endif
00059 
00060 //Ethernet interrupt priority
00061 #ifndef AVR32_ETH_IRQ_PRIORITY
00062    #define AVR32_ETH_IRQ_PRIORITY 2
00063 #elif (AVR32_ETH_IRQ_PRIORITY < 0 || AVR32_ETH_IRQ_PRIORITY > 3)
00064    #error AVR32_ETH_IRQ_PRIORITY parameter is not valid
00065 #endif
00066 
00067 //RMII pin definition
00068 #define MACB_RMII_EREFCK_MASK (1 << (AVR32_MACB_TX_CLK_0_PIN - 32))
00069 #define MACB_RMII_ETXEN_MASK  (1 << (AVR32_MACB_TX_EN_0_PIN - 32))
00070 #define MACB_RMII_ETX0_MASK   (1 << (AVR32_MACB_TXD_0_PIN - 32))
00071 #define MACB_RMII_ETX1_MASK   (1 << (AVR32_MACB_TXD_1_PIN - 32))
00072 #define MACB_RMII_ERX0_MASK   (1 << (AVR32_MACB_RXD_0_PIN - 32))
00073 #define MACB_RMII_ERX1_MASK   (1 << (AVR32_MACB_RXD_1_PIN - 32))
00074 #define MACB_RMII_ERXER_MASK  (1 << (AVR32_MACB_RX_ER_0_PIN - 32))
00075 #define MACB_RMII_ECRSDV_MASK (1 << (AVR32_MACB_RX_DV_0_PIN - 32))
00076 #define MACB_RMII_MDC_MASK    (1 << (AVR32_MACB_MDC_0_PIN - 32))
00077 #define MACB_RMII_MDIO_MASK   (1 << (AVR32_MACB_MDIO_0_PIN - 32))
00078 
00079 //RMII signals
00080 #define MACB_RMII_MASK (MACB_RMII_EREFCK_MASK | MACB_RMII_ETXEN_MASK | \
00081    MACB_RMII_ETX0_MASK | MACB_RMII_ETX1_MASK | MACB_RMII_ERX0_MASK | MACB_RMII_ERX1_MASK | \
00082    MACB_RMII_ERXER_MASK | MACB_RMII_ECRSDV_MASK | MACB_RMII_MDC_MASK | MACB_RMII_MDIO_MASK)
00083 
00084 //PHY maintenance register (MAN)
00085 #define MACB_MAN_SOF_01  (1 << AVR32_MACB_MAN_SOF_OFFSET)
00086 #define MACB_MAN_RW_01   (1 << AVR32_MACB_MAN_RW_OFFSET)
00087 #define MACB_MAN_RW_10   (2 << AVR32_MACB_MAN_RW_OFFSET)
00088 #define MACB_MAN_CODE_10 (2 << AVR32_MACB_MAN_CODE_OFFSET)
00089 
00090 //TX buffer descriptor flags
00091 #define MACB_TX_USED           0x80000000
00092 #define MACB_TX_WRAP           0x40000000
00093 #define MACB_TX_ERROR          0x20000000
00094 #define MACB_TX_UNDERRUN       0x10000000
00095 #define MACB_TX_EXHAUSTED      0x08000000
00096 #define MACB_TX_NO_CRC         0x00010000
00097 #define MACB_TX_LAST           0x00008000
00098 #define MACB_TX_LENGTH         0x000007FF
00099 
00100 //RX buffer descriptor flags
00101 #define MACB_RX_ADDRESS        0xFFFFFFFC
00102 #define MACB_RX_WRAP           0x00000002
00103 #define MACB_RX_OWNERSHIP      0x00000001
00104 #define MACB_RX_BROADCAST      0x80000000
00105 #define MACB_RX_MULTICAST_HASH 0x40000000
00106 #define MACB_RX_UNICAST_HASH   0x20000000
00107 #define MACB_RX_EXT_ADDR       0x10000000
00108 #define MACB_RX_SAR1           0x04000000
00109 #define MACB_RX_SAR2           0x02000000
00110 #define MACB_RX_SAR3           0x01000000
00111 #define MACB_RX_SAR4           0x00800000
00112 #define MACB_RX_TYPE_ID        0x00400000
00113 #define MACB_RX_VLAN_TAG       0x00200000
00114 #define MACB_RX_PRIORITY_TAG   0x00100000
00115 #define MACB_RX_VLAN_PRIORITY  0x000E0000
00116 #define MACB_RX_CFI            0x00010000
00117 #define MACB_RX_EOF            0x00008000
00118 #define MACB_RX_SOF            0x00004000
00119 #define MACB_RX_OFFSET         0x00003000
00120 #define MACB_RX_LENGTH         0x00000FFF
00121 
00122 
00123 /**
00124  * @brief Transmit buffer descriptor
00125  **/
00126 
00127 typedef struct
00128 {
00129    uint32_t address;
00130    uint32_t status;
00131 } Avr32TxBufferDesc;
00132 
00133 
00134 /**
00135  * @brief Receive buffer descriptor
00136  **/
00137 
00138 typedef struct
00139 {
00140    uint32_t address;
00141    uint32_t status;
00142 } Avr32RxBufferDesc;
00143 
00144 
00145 //AVR32 Ethernet MAC driver
00146 extern const NicDriver avr32EthDriver;
00147 
00148 //AVR32 Ethernet MAC related functions
00149 error_t avr32EthInit(NetInterface *interface);
00150 void avr32EthInitGpio(NetInterface *interface);
00151 void avr32EthInitBufferDesc(NetInterface *interface);
00152 
00153 void avr32EthTick(NetInterface *interface);
00154 
00155 void avr32EthEnableIrq(NetInterface *interface);
00156 void avr32EthDisableIrq(NetInterface *interface);
00157 void avr32EthIrqWrapper(void);
00158 bool_t avr32EthIrqHandler(void);
00159 void avr32EthEventHandler(NetInterface *interface);
00160 
00161 error_t avr32EthSendPacket(NetInterface *interface,
00162    const NetBuffer *buffer, size_t offset);
00163 
00164 error_t avr32EthReceivePacket(NetInterface *interface);
00165 
00166 error_t avr32EthSetMulticastFilter(NetInterface *interface);
00167 error_t avr32EthUpdateMacConfig(NetInterface *interface);
00168 
00169 void avr32EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00170 uint16_t avr32EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00171 
00172 #endif
00173