ar8031.h

00001 /**
00002  * @file ar8031.h
00003  * @brief AR8031 Gigabit Ethernet PHY transceiver
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _AR8031_H
00030 #define _AR8031_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //PHY address
00036 #ifndef AR8031_PHY_ADDR
00037    #define AR8031_PHY_ADDR 0
00038 #elif (AR8031_PHY_ADDR < 0 || AR8031_PHY_ADDR > 31)
00039    #error AR8031_PHY_ADDR parameter is not valid
00040 #endif
00041 
00042 //AR8031 registers
00043 #define AR8031_PHY_REG_BMCR              0x00
00044 #define AR8031_PHY_REG_BMSR              0x01
00045 #define AR8031_PHY_REG_PHYIDR1           0x02
00046 #define AR8031_PHY_REG_PHYIDR2           0x03
00047 #define AR8031_PHY_REG_ANAR              0x04
00048 #define AR8031_PHY_REG_ANLPAR            0x05
00049 #define AR8031_PHY_REG_ANER              0x06
00050 #define AR8031_PHY_REG_ANNPTR            0x07
00051 #define AR8031_PHY_REG_LPNPAR            0x08
00052 #define AR8031_PHY_REG_1000BT_CTRL       0x09
00053 #define AR8031_PHY_REG_1000BT_STATUS     0x0A
00054 #define AR8031_PHY_REG_MMD_CTRL          0x0D
00055 #define AR8031_PHY_REG_MMD_DATA          0x0E
00056 #define AR8031_PHY_REG_EXT_STATUS        0x0F
00057 #define AR8031_PHY_REG_FUNCTION_CTRL     0x10
00058 #define AR8031_PHY_REG_PHY_STATUS        0x11
00059 #define AR8031_PHY_REG_INT_EN            0x12
00060 #define AR8031_PHY_REG_INT_STATUS        0x13
00061 #define AR8031_PHY_REG_SMART_SPEED       0x14
00062 #define AR8031_PHY_REG_CDT_CTRL          0x16
00063 #define AR8031_PHY_REG_LED_CTRL          0x18
00064 #define AR8031_PHY_REG_MAN_LED_OVERRIDE  0x19
00065 #define AR8031_PHY_REG_CDT_STATUS        0x1C
00066 #define AR8031_PHY_REG_DBG_PORT          0x1D
00067 #define AR8031_PHY_REG_DBG_PORT2         0x1E
00068 #define AR8031_PHY_REG_CHIP_CONFIG       0x1F
00069 
00070 //BMCR register
00071 #define BMCR_RESET                       (1 << 15)
00072 #define BMCR_LOOPBACK                    (1 << 14)
00073 #define BMCR_SPEED_SEL_LSB               (1 << 13)
00074 #define BMCR_AN_EN                       (1 << 12)
00075 #define BMCR_POWER_DOWN                  (1 << 11)
00076 #define BMCR_ISOLATE                     (1 << 10)
00077 #define BMCR_RESTART_AN                  (1 << 9)
00078 #define BMCR_DUPLEX_MODE                 (1 << 8)
00079 #define BMCR_COL_TEST                    (1 << 7)
00080 #define BMCR_SPEED_SEL_MSB               (1 << 6)
00081 
00082 //BMSR register
00083 #define BMSR_100BT4                      (1 << 15)
00084 #define BMSR_100BTX_FD                   (1 << 14)
00085 #define BMSR_100BTX_HD                   (1 << 13)
00086 #define BMSR_10BT_FD                     (1 << 12)
00087 #define BMSR_10BT_HD                     (1 << 11)
00088 #define BMSR_100BT2_FD                   (1 << 10)
00089 #define BMSR_100BT2_HD                   (1 << 9)
00090 #define BMSR_EXTENDED_STATUS             (1 << 8)
00091 #define BMSR_NO_PREAMBLE                 (1 << 6)
00092 #define BMSR_AN_COMPLETE                 (1 << 5)
00093 #define BMSR_REMOTE_FAULT                (1 << 4)
00094 #define BMSR_AN_ABLE                     (1 << 3)
00095 #define BMSR_LINK_STATUS                 (1 << 2)
00096 #define BMSR_JABBER_DETECT               (1 << 1)
00097 #define BMSR_EXTENDED_CAP                (1 << 0)
00098 
00099 //ANAR register
00100 #define ANAR_NEXT_PAGE                   (1 << 15)
00101 #define ANAR_ACK                         (1 << 14)
00102 #define ANAR_REMOTE_FAULT                (1 << 13)
00103 #define ANAR_XNP_ABLE                    (1 << 12)
00104 #define ANAR_ASYMMETRIC_PAUSE            (1 << 11)
00105 #define ANAR_PAUSE                       (1 << 10)
00106 #define ANAR_100BT4                      (1 << 9)
00107 #define ANAR_100BTX_FD                   (1 << 8)
00108 #define ANAR_100BTX_HD                   (1 << 7)
00109 #define ANAR_10BT_FD                     (1 << 6)
00110 #define ANAR_10BT_HD                     (1 << 5)
00111 #define ANAR_SELECTOR4                   (1 << 4)
00112 #define ANAR_SELECTOR3                   (1 << 3)
00113 #define ANAR_SELECTOR2                   (1 << 2)
00114 #define ANAR_SELECTOR1                   (1 << 1)
00115 #define ANAR_SELECTOR0                   (1 << 0)
00116 
00117 //ANLPAR register
00118 #define ANLPAR_NEXT_PAGE                 (1 << 15)
00119 #define ANLPAR_ACK                       (1 << 14)
00120 #define ANLPAR_REMOTE_FAULT              (1 << 13)
00121 #define ANLPAR_ASYMMETRIC_PAUSE          (1 << 11)
00122 #define ANLPAR_PAUSE                     (1 << 10)
00123 #define ANLPAR_100BT4                    (1 << 9)
00124 #define ANLPAR_100BTX_FD                 (1 << 8)
00125 #define ANLPAR_100BTX_HD                 (1 << 7)
00126 #define ANLPAR_10BT_FD                   (1 << 6)
00127 #define ANLPAR_10BT_HD                   (1 << 5)
00128 #define ANLPAR_SELECTOR4                 (1 << 4)
00129 #define ANLPAR_SELECTOR3                 (1 << 3)
00130 #define ANLPAR_SELECTOR2                 (1 << 2)
00131 #define ANLPAR_SELECTOR1                 (1 << 1)
00132 #define ANLPAR_SELECTOR0                 (1 << 0)
00133 
00134 //ANER register
00135 #define ANER_PAR_DET_FAULT               (1 << 4)
00136 #define ANER_LP_NEXT_PAGE_ABLE           (1 << 3)
00137 #define ANER_NEXT_PAGE_ABLE              (1 << 2)
00138 #define ANER_PAGE_RECEIVED               (1 << 1)
00139 #define ANER_LP_AN_ABLE                  (1 << 0)
00140 
00141 //ANNPTR register
00142 #define ANNPTR_NEXT_PAGE                 (1 << 15)
00143 #define ANNPTR_MSG_PAGE                  (1 << 13)
00144 #define ANNPTR_ACK2                      (1 << 12)
00145 #define ANNPTR_TOGGLE                    (1 << 11)
00146 #define ANNPTR_MESSAGE10                 (1 << 10)
00147 #define ANNPTR_MESSAGE9                  (1 << 9)
00148 #define ANNPTR_MESSAGE8                  (1 << 8)
00149 #define ANNPTR_MESSAGE7                  (1 << 7)
00150 #define ANNPTR_MESSAGE6                  (1 << 6)
00151 #define ANNPTR_MESSAGE5                  (1 << 5)
00152 #define ANNPTR_MESSAGE4                  (1 << 4)
00153 #define ANNPTR_MESSAGE3                  (1 << 3)
00154 #define ANNPTR_MESSAGE2                  (1 << 2)
00155 #define ANNPTR_MESSAGE1                  (1 << 1)
00156 #define ANNPTR_MESSAGE0                  (1 << 0)
00157 
00158 //LPNPAR register
00159 #define LPNPAR_NEXT_PAGE                 (1 << 15)
00160 #define LPNPAR_MSG_PAGE                  (1 << 13)
00161 #define LPNPAR_ACK2                      (1 << 12)
00162 #define LPNPAR_TOGGLE                    (1 << 11)
00163 #define LPNPAR_MESSAGE10                 (1 << 10)
00164 #define LPNPAR_MESSAGE9                  (1 << 9)
00165 #define LPNPAR_MESSAGE8                  (1 << 8)
00166 #define LPNPAR_MESSAGE7                  (1 << 7)
00167 #define LPNPAR_MESSAGE6                  (1 << 6)
00168 #define LPNPAR_MESSAGE5                  (1 << 5)
00169 #define LPNPAR_MESSAGE4                  (1 << 4)
00170 #define LPNPAR_MESSAGE3                  (1 << 3)
00171 #define LPNPAR_MESSAGE2                  (1 << 2)
00172 #define LPNPAR_MESSAGE1                  (1 << 1)
00173 #define LPNPAR_MESSAGE0                  (1 << 0)
00174 
00175 //1000BT_CTRL register
00176 #define _1000BT_CTRL_TEST_MODE2          (1 << 15)
00177 #define _1000BT_CTRL_TEST_MODE1          (1 << 14)
00178 #define _1000BT_CTRL_TEST_MODE0          (1 << 13)
00179 #define _1000BT_CTRL_MS_MAN_CONF_EN      (1 << 12)
00180 #define _1000BT_CTRL_MS_MAN_CONF_VAL     (1 << 11)
00181 #define _1000BT_CTRL_PORT_TYPE           (1 << 10)
00182 #define _1000BT_CTRL_1000BT_FD           (1 << 9)
00183 #define _1000BT_CTRL_1000BT_HD           (1 << 8)
00184 
00185 //1000BT_STATUS register
00186 #define _1000BT_STATUS_MS_CONF_FAULT     (1 << 15)
00187 #define _1000BT_STATUS_MS_CONF_RES       (1 << 14)
00188 #define _1000BT_STATUS_LOC_REC_STATUS    (1 << 13)
00189 #define _1000BT_STATUS_REM_REC_STATUS    (1 << 12)
00190 #define _1000BT_STATUS_LP_1000BT_FD      (1 << 11)
00191 #define _1000BT_STATUS_LP_1000BT_HD      (1 << 10)
00192 #define _1000BT_STATUS_IDLE_ERR_CTR7     (1 << 7)
00193 #define _1000BT_STATUS_IDLE_ERR_CTR6     (1 << 6)
00194 #define _1000BT_STATUS_IDLE_ERR_CTR5     (1 << 5)
00195 #define _1000BT_STATUS_IDLE_ERR_CTR4     (1 << 4)
00196 #define _1000BT_STATUS_IDLE_ERR_CTR3     (1 << 3)
00197 #define _1000BT_STATUS_IDLE_ERR_CTR2     (1 << 2)
00198 #define _1000BT_STATUS_IDLE_ERR_CTR1     (1 << 1)
00199 #define _1000BT_STATUS_IDLE_ERR_CTR0     (1 << 0)
00200 
00201 //MMD_CTRL register
00202 #define MMD_CTRL_FUNCTION1               (1 << 15)
00203 #define MMD_CTRL_FUNCTION0               (1 << 14)
00204 #define MMD_CTRL_DEVAD4                  (1 << 4)
00205 #define MMD_CTRL_DEVAD3                  (1 << 3)
00206 #define MMD_CTRL_DEVAD2                  (1 << 2)
00207 #define MMD_CTRL_DEVAD1                  (1 << 1)
00208 #define MMD_CTRL_DEVAD0                  (1 << 0)
00209 
00210 //EXT_STATUS register
00211 #define EXT_STATUS_1000BX_FD             (1 << 15)
00212 #define EXT_STATUS_1000BX_HD             (1 << 14)
00213 #define EXT_STATUS_1000BT_FD             (1 << 13)
00214 #define EXT_STATUS_1000BT_HD             (1 << 12)
00215 
00216 //FUNCTION register
00217 #define FUNCTION_ASSERT_CRS_ON_TX        (1 << 11)
00218 #define FUNCTION_FORCE_LINK              (1 << 10)
00219 #define FUNCTION_MDI_CROSSOVER_MODE1     (1 << 6)
00220 #define FUNCTION_MDI_CROSSOVER_MODE0     (1 << 5)
00221 #define FUNCTION_SQE_TEST                (1 << 2)
00222 #define FUNCTION_POLARITY_REVERSAL       (1 << 1)
00223 #define FUNCTION_DISABLE_JABBER          (1 << 0)
00224 
00225 //PHY_STATUS register
00226 #define PHY_STATUS_SPEED1                (1 << 15)
00227 #define PHY_STATUS_SPEED0                (1 << 14)
00228 #define PHY_STATUS_DUPLEX                (1 << 13)
00229 #define PHY_STATUS_PAGE_RECEIVED         (1 << 12)
00230 #define PHY_STATUS_SPEED_DUPLEX_RESOLVED (1 << 11)
00231 #define PHY_STATUS_LINK                  (1 << 10)
00232 #define PHY_STATUS_MDI_CROSSOVER_STATUS  (1 << 6)
00233 #define PHY_STATUS_WIRESPEED_DOWNGRADE   (1 << 5)
00234 #define PHY_STATUS_TX_PAUSE_ENABLED      (1 << 3)
00235 #define PHY_STATUS_RX_PAUSE_ENABLED      (1 << 2)
00236 #define PHY_STATUS_POLARITY              (1 << 1)
00237 #define PHY_STATUS_JABBER                (1 << 0)
00238 
00239 //Speed
00240 #define PHY_STATUS_SPEED_MASK            (3 << 14)
00241 #define PHY_STATUS_SPEED_10              (0 << 14)
00242 #define PHY_STATUS_SPEED_100             (1 << 14)
00243 #define PHY_STATUS_SPEED_1000            (2 << 14)
00244 
00245 //INT_EN register
00246 #define INT_EN_AN_ERROR                  (1 << 15)
00247 #define INT_EN_SPEED_CHANGED             (1 << 14)
00248 #define INT_EN_PAGE_RECEIVED             (1 << 12)
00249 #define INT_EN_LINK_FAIL                 (1 << 11)
00250 #define INT_EN_LINK_SUCCESS              (1 << 10)
00251 #define INT_EN_FAST_LINK_DOWN1           (1 << 9)
00252 #define INT_EN_LINK_FAIL_BX              (1 << 8)
00253 #define INT_EN_LINK_SUCCESS_BX           (1 << 7)
00254 #define INT_EN_FAST_LINK_DOWN0           (1 << 6)
00255 #define INT_EN_WIRESPEED_DOWNGRADE       (1 << 5)
00256 #define INT_EN_10MS_PTP                  (1 << 4)
00257 #define INT_EN_RX_PTP                    (1 << 3)
00258 #define INT_EN_TX_PTP                    (1 << 2)
00259 #define INT_EN_POLARITY_CHANGED          (1 << 1)
00260 #define INT_EN_WOL_PTP                   (1 << 0)
00261 
00262 //INT_STATUS register
00263 #define INT_STATUS_AN_ERROR              (1 << 15)
00264 #define INT_STATUS_SPEED_CHANGED         (1 << 14)
00265 #define INT_STATUS_PAGE_RECEIVED         (1 << 12)
00266 #define INT_STATUS_LINK_FAIL             (1 << 11)
00267 #define INT_STATUS_LINK_SUCCESS          (1 << 10)
00268 #define INT_STATUS_FAST_LINK_DOWN1       (1 << 9)
00269 #define INT_STATUS_LINK_FAIL_BX          (1 << 8)
00270 #define INT_STATUS_LINK_SUCCESS_BX       (1 << 7)
00271 #define INT_STATUS_FAST_LINK_DOWN0       (1 << 6)
00272 #define INT_STATUS_WIRESPEED_DOWNGRADE   (1 << 5)
00273 #define INT_STATUS_10MS_PTP              (1 << 4)
00274 #define INT_STATUS_RX_PTP                (1 << 3)
00275 #define INT_STATUS_TX_PTP                (1 << 2)
00276 #define INT_STATUS_POLARITY_CHANGED      (1 << 1)
00277 #define INT_STATUS_WOL_PTP               (1 << 0)
00278 
00279 //SMART_SPEED register
00280 #define SMART_SPEED_EN                   (1 << 5)
00281 #define SMART_SPEED_RETRY_LIMIT2         (1 << 4)
00282 #define SMART_SPEED_RETRY_LIMIT1         (1 << 3)
00283 #define SMART_SPEED_RETRY_LIMIT0         (1 << 2)
00284 #define SMART_SPEED_TIMER                (1 << 1)
00285 
00286 //CDT_CTRL register
00287 #define CDT_CTRL_MDI_PAIR_SELECT1        (1 << 9)
00288 #define CDT_CTRL_MDI_PAIR_SELECT0        (1 << 8)
00289 #define CDT_CTRL_ENABLE_TEST             (1 << 0)
00290 
00291 //LED_CTRL register
00292 #define LED_CTRL_DISABLE_LED             (1 << 15)
00293 #define LED_CTRL_LED_ON_TIME2            (1 << 14)
00294 #define LED_CTRL_LED_ON_TIME1            (1 << 13)
00295 #define LED_CTRL_LED_ON_TIME0            (1 << 12)
00296 #define LED_CTRL_LED_OFF_TIME2           (1 << 10)
00297 #define LED_CTRL_LED_OFF_TIME1           (1 << 9)
00298 #define LED_CTRL_LED_OFF_TIME0           (1 << 8)
00299 #define LED_CTRL_LED_LINK_CTRL1          (1 << 4)
00300 #define LED_CTRL_LED_LINK_CTRL0          (1 << 3)
00301 #define LED_CTRL_LED_ACT_CTRL            (1 << 1)
00302 
00303 //MAN_LED_OVERRIDE register
00304 #define MAN_LED_OVERRIDE_LED_ACT_CTRL    (1 << 12)
00305 #define MAN_LED_OVERRIDE_LED_LINK_CTRL1  (1 << 7)
00306 #define MAN_LED_OVERRIDE_LED_LINK_CTRL0  (1 << 6)
00307 #define MAN_LED_OVERRIDE_LED_RX_CTRL1    (1 << 3)
00308 #define MAN_LED_OVERRIDE_LED_RX_CTRL0    (1 << 2)
00309 #define MAN_LED_OVERRIDE_LED_TX_CTRL1    (1 << 1)
00310 #define MAN_LED_OVERRIDE_LED_TX_CTRL0    (1 << 0)
00311 
00312 //CDT_STATUS register
00313 #define CDT_STATUS_STATUS1               (1 << 9)
00314 #define CDT_STATUS_STATUS0               (1 << 8)
00315 #define CDT_STATUS_DELTA_TIME7           (1 << 7)
00316 #define CDT_STATUS_DELTA_TIME6           (1 << 6)
00317 #define CDT_STATUS_DELTA_TIME5           (1 << 5)
00318 #define CDT_STATUS_DELTA_TIME4           (1 << 4)
00319 #define CDT_STATUS_DELTA_TIME3           (1 << 3)
00320 #define CDT_STATUS_DELTA_TIME2           (1 << 2)
00321 #define CDT_STATUS_DELTA_TIME1           (1 << 1)
00322 #define CDT_STATUS_DELTA_TIME0           (1 << 0)
00323 
00324 //CHIP_CONF register
00325 #define CHIP_CONFIG_BT_BX_REG_SEL        (1 << 15)
00326 #define CHIP_CONFIG_SMII_IMP_50_75_AUTO  (1 << 14)
00327 #define CHIP_CONFIG_SGMII_RXIMP_50_75    (1 << 13)
00328 #define CHIP_CONFIG_SGMII_TXIMP_50_75    (1 << 12)
00329 #define CHIP_CONFIG_PRIORITY_SEL         (1 << 10)
00330 #define CHIP_CONFIG_FIBER_MODE_AUTO      (1 << 8)
00331 #define CHIP_CONFIG_MODE_CFG_QUAL3       (1 << 7)
00332 #define CHIP_CONFIG_MODE_CFG_QUAL2       (1 << 6)
00333 #define CHIP_CONFIG_MODE_CFG_QUAL1       (1 << 5)
00334 #define CHIP_CONFIG_MODE_CFG_QUAL0       (1 << 4)
00335 #define CHIP_CONFIG_MODE_CFG3            (1 << 3)
00336 #define CHIP_CONFIG_MODE_CFG2            (1 << 2)
00337 #define CHIP_CONFIG_MODE_CFG1            (1 << 1)
00338 #define CHIP_CONFIG_MODE_CFG0            (1 << 0)
00339 
00340 //AR8031 Ethernet PHY driver
00341 extern const PhyDriver ar8031PhyDriver;
00342 
00343 //AR8031 related functions
00344 error_t ar8031Init(NetInterface *interface);
00345 
00346 void ar8031Tick(NetInterface *interface);
00347 
00348 void ar8031EnableIrq(NetInterface *interface);
00349 void ar8031DisableIrq(NetInterface *interface);
00350 
00351 void ar8031EventHandler(NetInterface *interface);
00352 
00353 void ar8031WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
00354 uint16_t ar8031ReadPhyReg(NetInterface *interface, uint8_t address);
00355 
00356 void ar8031DumpPhyReg(NetInterface *interface);
00357 
00358 #endif
00359