aps3_eth.h

00001 /**
00002  * @file aps3_eth.h
00003  * @brief Cortus APS3 Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _APS3_ETH_H
00030 #define _APS3_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef APS3_ETH_TX_BUFFER_COUNT
00037    #define APS3_ETH_TX_BUFFER_COUNT 4
00038 #elif (APS3_ETH_TX_BUFFER_COUNT < 1)
00039    #error APS3_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef APS3_ETH_TX_BUFFER_SIZE
00044    #define APS3_ETH_TX_BUFFER_SIZE 1536
00045 #elif (APS3_ETH_TX_BUFFER_SIZE != 1536)
00046    #error APS3_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef APS3_ETH_RX_BUFFER_COUNT
00051    #define APS3_ETH_RX_BUFFER_COUNT 4
00052 #elif (APS3_ETH_RX_BUFFER_COUNT < 1)
00053    #error APS3_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef APS3_ETH_RX_BUFFER_SIZE
00058    #define APS3_ETH_RX_BUFFER_SIZE 1536
00059 #elif (APS3_ETH_RX_BUFFER_SIZE != 1536)
00060    #error APS3_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Ethernet interrupt priority
00064 #ifndef APS3_ETH_IRQ_PRIORITY
00065    #define APS3_ETH_IRQ_PRIORITY 0
00066 #elif (APS3_ETH_IRQ_PRIORITY < 0)
00067    #error APS3_ETH_IRQ_PRIORITY parameter is not valid
00068 #endif
00069 
00070 //tx_irq_mask register
00071 #define TX_IRQ_MASK_TRANSMIT_ERROR      0x0001
00072 #define TX_IRQ_MASK_EXCESSIVE_DEFERRAL  0x0002
00073 #define TX_IRQ_MASK_EXCESSIVE_COLLISION 0x0004
00074 #define TX_IRQ_MASK_LATE_COLLISION      0x0008
00075 #define TX_IRQ_MASK_FRAME_TOO_LONG      0x0010
00076 #define TX_IRQ_MASK_MEMORY_ERROR        0x0020
00077 #define TX_IRQ_MASK_FRAME_SENT          0x0040
00078 #define TX_IRQ_MASK_MEMORY_AVAILABLE    0x0080
00079 #define TX_IRQ_MASK_THRESHOLD_REACHED   0x0100
00080 #define TX_IRQ_MASK_MEMORY_EMPTY        0x0200
00081 
00082 //rx_irq_mask register
00083 #define RX_IRQ_MASK_RECEIVE_ERROR       0x0001
00084 #define RX_IRQ_MASK_LENGTH_FIELD_ERROR  0x0002
00085 #define RX_IRQ_MASK_FRAME_TOO_LONG      0x0004
00086 #define RX_IRQ_MASK_SHORT_FRAME         0x0008
00087 #define RX_IRQ_MASK_ODD_NIBBLE_COUNT    0x0010
00088 #define RX_IRQ_MASK_INVALID_ADDRESS     0x0020
00089 #define RX_IRQ_MASK_PHY_ERROR           0x0040
00090 #define RX_IRQ_MASK_CRC_ERROR           0x0080
00091 #define RX_IRQ_MASK_MEMORY_ERROR        0x0100
00092 #define RX_IRQ_MASK_WAKEUP_ON_LAN       0x0200
00093 #define RX_IRQ_MASK_FRAME_READY         0x0400
00094 #define RX_IRQ_MASK_THRESHOLD_REACHED   0x0800
00095 #define RX_IRQ_MASK_FRAME_OVERFLOW      0x1000
00096 
00097 //Transmit DMA descriptor flags
00098 #define TX_DESC_TRANSMIT_ERROR          0x0001
00099 #define TX_DESC_EXCESSIVE_DEFERRAL      0x0002
00100 #define TX_DESC_EXCESSIVE_COLLISION     0x0003
00101 #define TX_DESC_LATE_COLLISION          0x0004
00102 #define TX_DESC_FRAME_TOO_LONG          0x0010
00103 #define TX_DESC_MEMORY_ERROR            0x0020
00104 
00105 //Receive DMA descriptor flags
00106 #define RX_DESC_RECEIVE_ERROR           0x0001
00107 #define RX_DESC_LENGTH_FIELD_ERROR      0x0002
00108 #define RX_DESC_FRAME_TOO_LONG          0x0003
00109 #define RX_DESC_SHORT_FRAME             0x0004
00110 #define RX_DESC_ODD_NIBBLE_COUNT        0x0010
00111 #define RX_DESC_INVALID_ADDRESS         0x0020
00112 #define RX_DESC_PHY_ERROR               0x0040
00113 #define RX_DESC_CRC_ERROR               0x0080
00114 #define RX_DESC_MEMORY_ERROR            0x0100
00115 
00116 
00117 /**
00118  * @brief TX DMA descriptor
00119  **/
00120 
00121 typedef struct
00122 {
00123    uint32_t addr;
00124    uint32_t size : 16;
00125    uint32_t status : 16;
00126 } Aps3TxDmaDesc;
00127 
00128 
00129 /**
00130  * @brief RX DMA descriptor
00131  **/
00132 
00133 typedef struct
00134 {
00135    uint32_t addr;
00136    uint32_t size : 16;
00137    uint32_t status : 16;
00138 } Aps3RxDmaDesc;
00139 
00140 
00141 //Cortus APS3 Ethernet MAC driver
00142 extern const NicDriver aps3EthDriver;
00143 
00144 //Cortus APS3 Ethernet MAC related functions
00145 error_t aps3EthInit(NetInterface *interface);
00146 void aps3EthInitDmaDesc(NetInterface *interface);
00147 
00148 void aps3EthTick(NetInterface *interface);
00149 
00150 void aps3EthEnableIrq(NetInterface *interface);
00151 void aps3EthDisableIrq(NetInterface *interface);
00152 
00153 void aps3EthTxIrqHandler(void) __attribute__((noinline));
00154 void aps3EthRxIrqHandler(void) __attribute__((noinline));
00155 
00156 void aps3EthEventHandler(NetInterface *interface);
00157 
00158 error_t aps3EthSendPacket(NetInterface *interface,
00159    const NetBuffer *buffer, size_t offset);
00160 
00161 error_t aps3EthReceivePacket(NetInterface *interface);
00162 
00163 error_t aps3EthSetMulticastFilter(NetInterface *interface);
00164 error_t aps3EthUpdateMacConfig(NetInterface *interface);
00165 
00166 void aps3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00167 uint16_t aps3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00168 
00169 uint32_t aps3EthCalcCrc(const void *data, size_t length);
00170 
00171 #endif
00172