am335x_eth.h

00001 /**
00002  * @file am335x_eth.h
00003  * @brief Sitara AM335x Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _AM335X_ETH_H
00030 #define _AM335X_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef AM335X_ETH_TX_BUFFER_COUNT
00037    #define AM335X_ETH_TX_BUFFER_COUNT 16
00038 #elif (AM335X_ETH_TX_BUFFER_COUNT < 1)
00039    #error AM335X_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef AM335X_ETH_TX_BUFFER_SIZE
00044    #define AM335X_ETH_TX_BUFFER_SIZE 1536
00045 #elif (AM335X_ETH_TX_BUFFER_SIZE != 1536)
00046    #error AM335X_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef AM335X_ETH_RX_BUFFER_COUNT
00051    #define AM335X_ETH_RX_BUFFER_COUNT 16
00052 #elif (AM335X_ETH_RX_BUFFER_COUNT < 1)
00053    #error AM335X_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef AM335X_ETH_RX_BUFFER_SIZE
00058    #define AM335X_ETH_RX_BUFFER_SIZE 1536
00059 #elif (AM335X_ETH_RX_BUFFER_SIZE != 1536)
00060    #error AM335X_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Ethernet interrupt priority
00064 #ifndef AM335X_ETH_IRQ_PRIORITY
00065    #define AM335X_ETH_IRQ_PRIORITY 1
00066 #elif (AM335X_ETH_IRQ_PRIORITY < 0)
00067    #error AM335X_ETH_IRQ_PRIORITY parameter is not valid
00068 #endif
00069 
00070 //CPSW cores
00071 #define CPSW_CORE0 0
00072 #define CPSW_CORE1 1
00073 #define CPSW_CORE2 2
00074 
00075 //CPSW ports
00076 #define CPSW_PORT0 0
00077 #define CPSW_PORT1 1
00078 #define CPSW_PORT2 2
00079 
00080 //CPSW channels
00081 #define CPSW_CH0 0
00082 #define CPSW_CH1 1
00083 #define CPSW_CH2 2
00084 #define CPSW_CH3 3
00085 #define CPSW_CH4 4
00086 #define CPSW_CH5 5
00087 #define CPSW_CH6 6
00088 #define CPSW_CH7 7
00089 
00090 //PRCM registers
00091 #define CM_PER_CPGMAC0_CLKCTRL_R          HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL)
00092 #define CM_PER_CPSW_CLKSTCTRL_R           HWREG(SOC_PRCM_REGS + CM_PER_CPSW_CLKSTCTRL)
00093 
00094 //CONTROL registers
00095 #define CONTROL_MAC_ID_LO_R(n)            HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_LO(n))
00096 #define CONTROL_MAC_ID_HI_R(n)            HWREG(SOC_CONTROL_REGS + CONTROL_MAC_ID_HI(n))
00097 #define CONTROL_GMII_SEL_R                HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL)
00098 #define CONTROL_CONF_GPMC_A_R(n)          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(n))
00099 #define CONTROL_CONF_MII1_COL_R           HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL)
00100 #define CONTROL_CONF_MII1_CRS_R           HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS)
00101 #define CONTROL_CONF_MII1_RXERR_R         HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR)
00102 #define CONTROL_CONF_MII1_TXEN_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN)
00103 #define CONTROL_CONF_MII1_RXDV_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV)
00104 #define CONTROL_CONF_MII1_TXD3_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3)
00105 #define CONTROL_CONF_MII1_TXD2_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2)
00106 #define CONTROL_CONF_MII1_TXD1_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1)
00107 #define CONTROL_CONF_MII1_TXD0_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0)
00108 #define CONTROL_CONF_MII1_TXCLK_R         HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK)
00109 #define CONTROL_CONF_MII1_RXCLK_R         HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK)
00110 #define CONTROL_CONF_MII1_RXD3_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3)
00111 #define CONTROL_CONF_MII1_RXD2_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2)
00112 #define CONTROL_CONF_MII1_RXD1_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1)
00113 #define CONTROL_CONF_MII1_RXD0_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0)
00114 #define CONTROL_CONF_RMII1_REFCLK_R       HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK)
00115 #define CONTROL_CONF_MDIO_DATA_R          HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA)
00116 #define CONTROL_CONF_MDIO_CLK_R           HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK)
00117 
00118 //CPSW_ALE registers
00119 #define CPSW_ALE_IDVER_R                  HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_IDVER)
00120 #define CPSW_ALE_CONTROL_R                HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_CONTROL)
00121 #define CPSW_ALE_PRESCALE_R               HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PRESCALE)
00122 #define CPSW_ALE_UNKNOWN_VLAN_R           HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_UNKNOWN_VLAN)
00123 #define CPSW_ALE_TBLCTL_R                 HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLCTL)
00124 #define CPSW_ALE_TBLW_R(n)                HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_TBLW(n))
00125 #define CPSW_ALE_PORTCTL_R(n)             HWREG(SOC_CPSW_ALE_REGS + CPSW_ALE_PORTCTL(n))
00126 
00127 //CPSW_CPDMA registers
00128 #define CPSW_CPDMA_TX_IDVER_R             HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_IDVER)
00129 #define CPSW_CPDMA_TX_CONTROL_R           HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CONTROL)
00130 #define CPSW_CPDMA_TX_TEARDOWN_R          HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_TEARDOWN)
00131 #define CPSW_CPDMA_RX_IDVER_R             HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_IDVER)
00132 #define CPSW_CPDMA_RX_CONTROL_R           HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CONTROL)
00133 #define CPSW_CPDMA_RX_TEARDOWN_R          HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_TEARDOWN)
00134 #define CPSW_CPDMA_CPDMA_SOFT_RESET_R     HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_SOFT_RESET)
00135 #define CPSW_CPDMA_DMACONTROL_R           HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMACONTROL)
00136 #define CPSW_CPDMA_DMASTATUS_R            HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMASTATUS)
00137 #define CPSW_CPDMA_RX_BUFFER_OFFSET_R     HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_BUFFER_OFFSET)
00138 #define CPSW_CPDMA_EMCONTROL_R            HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_EMCONTROL)
00139 #define CPSW_CPDMA_TX_PRI_RATE_R(n)       HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_PRI_RATE(n))
00140 #define CPSW_CPDMA_TX_INTSTAT_RAW_R       HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_RAW)
00141 #define CPSW_CPDMA_TX_INTSTAT_MASKED_R    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTSTAT_MASKED)
00142 #define CPSW_CPDMA_TX_INTMASK_SET_R       HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_SET)
00143 #define CPSW_CPDMA_TX_INTMASK_CLEAR_R     HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_INTMASK_CLEAR)
00144 #define CPSW_CPDMA_CPDMA_IN_VECTOR_R      HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_IN_VECTOR)
00145 #define CPSW_CPDMA_CPDMA_EOI_VECTOR_R     HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_CPDMA_EOI_VECTOR)
00146 #define CPSW_CPDMA_RX_INTSTAT_RAW_R       HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_RAW)
00147 #define CPSW_CPDMA_RX_INTSTAT_MASKED_R    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTSTAT_MASKED)
00148 #define CPSW_CPDMA_RX_INTMASK_SET_R       HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_SET)
00149 #define CPSW_CPDMA_RX_INTMASK_CLEAR_R     HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_INTMASK_CLEAR)
00150 #define CPSW_CPDMA_DMA_INTSTAT_RAW_R      HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_RAW)
00151 #define CPSW_CPDMA_DMA_INTSTAT_MASKED_R   HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTSTAT_MASKED)
00152 #define CPSW_CPDMA_DMA_INTMASK_SET_R      HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_SET)
00153 #define CPSW_CPDMA_DMA_INTMASK_CLEAR_R    HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_DMA_INTMASK_CLEAR)
00154 #define CPSW_CPDMA_RX_PENDTHRESH_R(n)     HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_PENDTHRESH(n))
00155 #define CPSW_CPDMA_RX_FREEBUFFER_R(n)     HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_FREEBUFFER(n))
00156 #define CPSW_CPDMA_TX_HDP_R(n)            HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_HDP(n))
00157 #define CPSW_CPDMA_RX_HDP_R(n)            HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_HDP(n))
00158 #define CPSW_CPDMA_TX_CP_R(n)             HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_TX_CP(n))
00159 #define CPSW_CPDMA_RX_CP_R(n)             HWREG(SOC_CPSW_CPDMA_REGS + CPSW_CPDMA_RX_CP(n))
00160 
00161 //CPSW_PORT registers
00162 #define CPSW_PORT0_CONTROL_R              HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CONTROL)
00163 #define CPSW_PORT0_MAX_BLKS_R             HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_MAX_BLKS)
00164 #define CPSW_PORT0_BLK_CNT_R              HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_BLK_CNT)
00165 #define CPSW_PORT0_TX_IN_CTL_R            HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TX_IN_CTL)
00166 #define CPSW_PORT0_PORT_VLAN_R            HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_PORT_VLAN)
00167 #define CPSW_PORT0_TX_PRI_MAP_R           HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TX_PRI_MAP)
00168 #define CPSW_PORT0_CPDMA_TX_PRI_MAP0_R    HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
00169 #define CPSW_PORT0_CPDMA_RX_CH_MAP0_R     HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
00170 #define CPSW_PORT0_RX_DSCP_PRI_MAP_R(n)   HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
00171 #define CPSW_PORT0_TS_SEQ_MTYPE_R         HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_TS_SEQ_MTYPE)
00172 #define CPSW_PORT0_SA_LO_R                HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SA_LO)
00173 #define CPSW_PORT0_SA_HI_R                HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SA_HI)
00174 #define CPSW_PORT0_SEND_PERCENT_R         HWREG(SOC_CPSW_PORT_0_REGS + CPSW_PORT_SEND_PERCENT)
00175 
00176 #define CPSW_PORT1_CONTROL_R              HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CONTROL)
00177 #define CPSW_PORT1_MAX_BLKS_R             HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_MAX_BLKS)
00178 #define CPSW_PORT1_BLK_CNT_R              HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_BLK_CNT)
00179 #define CPSW_PORT1_TX_IN_CTL_R            HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TX_IN_CTL)
00180 #define CPSW_PORT1_PORT_VLAN_R            HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_PORT_VLAN)
00181 #define CPSW_PORT1_TX_PRI_MAP_R           HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TX_PRI_MAP)
00182 #define CPSW_PORT1_CPDMA_TX_PRI_MAP0_R    HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
00183 #define CPSW_PORT1_CPDMA_RX_CH_MAP0_R     HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
00184 #define CPSW_PORT1_RX_DSCP_PRI_MAP_R(n)   HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
00185 #define CPSW_PORT1_TS_SEQ_MTYPE_R         HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_TS_SEQ_MTYPE)
00186 #define CPSW_PORT1_SA_LO_R                HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SA_LO)
00187 #define CPSW_PORT1_SA_HI_R                HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SA_HI)
00188 #define CPSW_PORT1_SEND_PERCENT_R         HWREG(SOC_CPSW_PORT_1_REGS + CPSW_PORT_SEND_PERCENT)
00189 
00190 #define CPSW_PORT2_CONTROL_R              HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CONTROL)
00191 #define CPSW_PORT2_MAX_BLKS_R             HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_MAX_BLKS)
00192 #define CPSW_PORT2_BLK_CNT_R              HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_BLK_CNT)
00193 #define CPSW_PORT2_TX_IN_CTL_R            HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TX_IN_CTL)
00194 #define CPSW_PORT2_PORT_VLAN_R            HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_PORT_VLAN)
00195 #define CPSW_PORT2_TX_PRI_MAP_R           HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TX_PRI_MAP)
00196 #define CPSW_PORT2_CPDMA_TX_PRI_MAP0_R    HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CPDMA_TX_PRI_MAP0)
00197 #define CPSW_PORT2_CPDMA_RX_CH_MAP0_R     HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_CPDMA_RX_CH_MAP0)
00198 #define CPSW_PORT2_RX_DSCP_PRI_MAP_R(n)   HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_RX_DSCP_PRI_MAP(n))
00199 #define CPSW_PORT2_TS_SEQ_MTYPE_R         HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_TS_SEQ_MTYPE)
00200 #define CPSW_PORT2_SA_LO_R                HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SA_LO)
00201 #define CPSW_PORT2_SA_HI_R                HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SA_HI)
00202 #define CPSW_PORT2_SEND_PERCENT_R         HWREG(SOC_CPSW_PORT_2_REGS + CPSW_PORT_SEND_PERCENT)
00203 
00204 //CPSW_SL registers
00205 #define CPSW_SL1_IDVER_R                  HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_IDVER)
00206 #define CPSW_SL1_MACCONTROL_R             HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACCONTROL)
00207 #define CPSW_SL1_MACSTATUS_R              HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_MACSTATUS)
00208 #define CPSW_SL1_SOFT_RESET_R             HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_SOFT_RESET)
00209 #define CPSW_SL1_RX_MAXLEN_R              HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_MAXLEN)
00210 #define CPSW_SL1_BOFFTEST_R               HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_BOFFTEST)
00211 #define CPSW_SL1_RX_PAUSE_R               HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PAUSE)
00212 #define CPSW_SL1_TX_PAUSE_R               HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_PAUSE)
00213 #define CPSW_SL1_EMCONTROL_R              HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_EMCONTROL)
00214 #define CPSW_SL1_RX_PRI_MAP_R             HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_RX_PRI_MAP)
00215 #define CPSW_SL1_TX_GAP_R                 HWREG(SOC_CPSW_SLIVER_1_REGS + CPSW_SL_TX_GAP)
00216 
00217 #define CPSW_SL2_IDVER_R                  HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_IDVER)
00218 #define CPSW_SL2_MACCONTROL_R             HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACCONTROL)
00219 #define CPSW_SL2_MACSTATUS_R              HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_MACSTATUS)
00220 #define CPSW_SL2_SOFT_RESET_R             HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_SOFT_RESET)
00221 #define CPSW_SL2_RX_MAXLEN_R              HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_MAXLEN)
00222 #define CPSW_SL2_BOFFTEST_R               HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_BOFFTEST)
00223 #define CPSW_SL2_RX_PAUSE_R               HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PAUSE)
00224 #define CPSW_SL2_TX_PAUSE_R               HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_PAUSE)
00225 #define CPSW_SL2_EMCONTROL_R              HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_EMCONTROL)
00226 #define CPSW_SL2_RX_PRI_MAP_R             HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_RX_PRI_MAP)
00227 #define CPSW_SL2_TX_GAP_R                 HWREG(SOC_CPSW_SLIVER_2_REGS + CPSW_SL_TX_GAP)
00228 
00229 //CPSW_SS registers
00230 #define CPSW_SS_ID_VER_R                  HWREG(SOC_CPSW_SS_REGS + CPSW_SS_ID_VER)
00231 #define CPSW_SS_CONTROL_R                 HWREG(SOC_CPSW_SS_REGS + CPSW_SS_CONTROL)
00232 #define CPSW_SS_SOFT_RESET_R              HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_RESET)
00233 #define CPSW_SS_STAT_PORT_EN_R            HWREG(SOC_CPSW_SS_REGS + CPSW_SS_STAT_PORT_EN)
00234 #define CPSW_SS_PTYPE_R                   HWREG(SOC_CPSW_SS_REGS + CPSW_SS_PTYPE)
00235 #define CPSW_SS_SOFT_IDLE_R               HWREG(SOC_CPSW_SS_REGS + CPSW_SS_SOFT_IDLE)
00236 #define CPSW_SS_THRU_RATE_R               HWREG(SOC_CPSW_SS_REGS + CPSW_SS_THRU_RATE)
00237 #define CPSW_SS_GAP_THRESH_R              HWREG(SOC_CPSW_SS_REGS + CPSW_SS_GAP_THRESH)
00238 #define CPSW_SS_TX_START_WDS_R            HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TX_START_WDS)
00239 #define CPSW_SS_FLOW_CONTROL_R            HWREG(SOC_CPSW_SS_REGS + CPSW_SS_FLOW_CONTROL)
00240 #define CPSW_SS_VLAN_LTYPE_R              HWREG(SOC_CPSW_SS_REGS + CPSW_SS_VLAN_LTYPE)
00241 #define CPSW_SS_TS_LTYPE_R                HWREG(SOC_CPSW_SS_REGS + CPSW_SS_TS_LTYPE)
00242 #define CPSW_SS_DLR_LTYPE_R               HWREG(SOC_CPSW_SS_REGS + CPSW_SS_DLR_LTYPE)
00243 
00244 //CPSW_WR registers
00245 #define CPSW_WR_IDVER_R                   HWREG(SOC_CPSW_WR_REGS + CPSW_WR_IDVER)
00246 #define CPSW_WR_SOFT_RESET_R              HWREG(SOC_CPSW_WR_REGS + CPSW_WR_SOFT_RESET)
00247 #define CPSW_WR_CONTROL_R                 HWREG(SOC_CPSW_WR_REGS + CPSW_WR_CONTROL)
00248 #define CPSW_WR_INT_CONTROL_R             HWREG(SOC_CPSW_WR_REGS + CPSW_WR_INT_CONTROL)
00249 #define CPSW_WR_C_RX_THRESH_EN_R(n)       HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_THRESH_EN(n))
00250 #define CPSW_WR_C_RX_EN_R(n)              HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_EN(n))
00251 #define CPSW_WR_C_TX_EN_R(n)              HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_EN(n))
00252 #define CPSW_WR_C_MISC_EN_R(n)            HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_EN(n))
00253 #define CPSW_WR_C_RX_THRESH_STAT_R(n)     HWREG(SOC_CPSW_WR_REGS +CPSW_WR_C_RX_THRESH_STAT(n))
00254 #define CPSW_WR_C_RX_STAT_R(n)            HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_STAT(n))
00255 #define CPSW_WR_C_TX_STAT_R(n)            HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_STAT(n))
00256 #define CPSW_WR_C_MISC_STAT_R(n)          HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_MISC_STAT(n))
00257 #define CPSW_WR_C_RX_IMAX_R(n)            HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_RX_IMAX(n))
00258 #define CPSW_WR_C_TX_IMAX_R(n)            HWREG(SOC_CPSW_WR_REGS + CPSW_WR_C_TX_IMAX(n))
00259 #define CPSW_WR_RGMII_CTL_R               HWREG(SOC_CPSW_WR_REGS + CPSW_WR_RGMII_CTL)
00260 
00261 //MDIO registers
00262 #define MDIO_REVID_R                      HWREG(SOC_CPSW_MDIO_REGS + MDIO_REVID)
00263 #define MDIO_CONTROL_R                    HWREG(SOC_CPSW_MDIO_REGS + MDIO_CONTROL)
00264 #define MDIO_ALIVE_R                      HWREG(SOC_CPSW_MDIO_REGS + MDIO_ALIVE)
00265 #define MDIO_LINK_R                       HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINK)
00266 #define MDIO_LINKINTRAW_R                 HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTRAW)
00267 #define MDIO_LINKINTMASKED_R              HWREG(SOC_CPSW_MDIO_REGS + MDIO_LINKINTMASKED)
00268 #define MDIO_USERINTRAW_R                 HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTRAW)
00269 #define MDIO_USERINTMASKED_R              HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKED)
00270 #define MDIO_USERINTMASKSET_R             HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKSET)
00271 #define MDIO_USERINTMASKCLEAR_R           HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERINTMASKCLEAR)
00272 #define MDIO_USERACCESS0_R                HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS0)
00273 #define MDIO_USERPHYSEL0_R                HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL0)
00274 #define MDIO_USERACCESS1_R                HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERACCESS1)
00275 #define MDIO_USERPHYSEL1_R                HWREG(SOC_CPSW_MDIO_REGS + MDIO_USERPHYSEL1)
00276 
00277 //GMII_SEL register
00278 #define CONTROL_GMII_SEL_GMII2_SEL_MII        0x00000000
00279 #define CONTROL_GMII_SEL_GMII2_SEL_RMII       0x00000004
00280 #define CONTROL_GMII_SEL_GMII2_SEL_RGMII      0x00000008
00281 #define CONTROL_GMII_SEL_GMII1_SEL_MII        0x00000000
00282 #define CONTROL_GMII_SEL_GMII1_SEL_RMII       0x00000001
00283 #define CONTROL_GMII_SEL_GMII1_SEL_RGMII      0x00000002
00284 
00285 //ALE_PORTCTL register
00286 #define CPSW_ALE_PORTCTL_PORT_STATE_DISABLED  0x00000000
00287 #define CPSW_ALE_PORTCTL_PORT_STATE_BLOCKED   0x00000001
00288 #define CPSW_ALE_PORTCTL_PORT_STATE_LEARN     0x00000002
00289 #define CPSW_ALE_PORTCTL_PORT_STATE_FORWARD   0x00000003
00290 
00291 //CPDMA_EOI_VECTOR register
00292 #define CPSW_CPDMA_EOI_VECTOR_RX_THRESH_PULSE 0x00000000
00293 #define CPSW_CPDMA_EOI_VECTOR_RX_PULSE        0x00000001
00294 #define CPSW_CPDMA_EOI_VECTOR_TX_PULSE        0x00000002
00295 #define CPSW_CPDMA_EOI_VECTOR_MISC_PULSE      0x00000003
00296 
00297 //TX buffer descriptor flags
00298 #define CPSW_TX_WORD0_NEXT_DESC_POINTER       0xFFFFFFFF
00299 #define CPSW_TX_WORD1_BUFFER_POINTER          0xFFFFFFFF
00300 #define CPSW_TX_WORD2_BUFFER_OFFSET           0xFFFF0000
00301 #define CPSW_TX_WORD2_BUFFER_LENGTH           0x0000FFFF
00302 #define CPSW_TX_WORD3_SOP                     0x80000000
00303 #define CPSW_TX_WORD3_EOP                     0x40000000
00304 #define CPSW_TX_WORD3_OWNER                   0x20000000
00305 #define CPSW_TX_WORD3_EOQ                     0x10000000
00306 #define CPSW_TX_WORD3_TDOWN_CMPLT             0x08000000
00307 #define CPSW_TX_WORD3_PASS_CRC                0x04000000
00308 #define CPSW_TX_WORD3_TO_PORT_EN              0x00100000
00309 #define CPSW_TX_WORD3_TO_PORT                 0x00030000
00310 #define CPSW_TX_WORD3_TO_PORT_1               0x00010000
00311 #define CPSW_TX_WORD3_TO_PORT_2               0x00020000
00312 #define CPSW_TX_WORD3_PACKET_LENGTH           0x000007FF
00313 
00314 //RX buffer descriptor flags
00315 #define CPSW_RX_WORD0_NEXT_DESC_POINTER       0xFFFFFFFF
00316 #define CPSW_RX_WORD1_BUFFER_POINTER          0xFFFFFFFF
00317 #define CPSW_RX_WORD2_BUFFER_OFFSET           0x07FF0000
00318 #define CPSW_RX_WORD2_BUFFER_LENGTH           0x000007FF
00319 #define CPSW_RX_WORD3_SOP                     0x80000000
00320 #define CPSW_RX_WORD3_EOP                     0x40000000
00321 #define CPSW_RX_WORD3_OWNER                   0x20000000
00322 #define CPSW_RX_WORD3_EOQ                     0x10000000
00323 #define CPSW_RX_WORD3_TDOWN_CMPLT             0x08000000
00324 #define CPSW_RX_WORD3_PASS_CRC                0x04000000
00325 #define CPSW_RX_WORD3_LONG                    0x02000000
00326 #define CPSW_RX_WORD3_SHORT                   0x01000000
00327 #define CPSW_RX_WORD3_CONTROL                 0x00800000
00328 #define CPSW_RX_WORD3_OVERRUN                 0x00400000
00329 #define CPSW_RX_WORD3_PKT_ERROR               0x00300000
00330 #define CPSW_RX_WORD3_RX_VLAN_ENCAP           0x000C0000
00331 #define CPSW_RX_WORD3_FROM_PORT               0x00030000
00332 #define CPSW_RX_WORD3_FROM_PORT_1             0x00010000
00333 #define CPSW_RX_WORD3_FROM_PORT_2             0x00020000
00334 #define CPSW_RX_WORD3_PACKET_LENGTH           0x000007FF
00335 
00336 //Number of entries in the ALE table
00337 #define CPSW_ALE_MAX_ENTRIES                   1024
00338 
00339 //ALE table entry
00340 #define CPSW_ALE_WORD1_ENTRY_TYPE_MASK         (3 << 28)
00341 #define CPSW_ALE_WORD1_ENTRY_TYPE_FREE         (0 << 28)
00342 #define CPSW_ALE_WORD1_ENTRY_TYPE_ADDR         (1 << 28)
00343 #define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN         (2 << 28)
00344 #define CPSW_ALE_WORD1_ENTRY_TYPE_VLAN_ADDR    (3 << 28)
00345 #define CPSW_ALE_WORD1_MULTICAST               (1 << 8)
00346 
00347 //Unicast address table entry
00348 #define CPSW_ALE_WORD2_DLR_UNICAST             (1 << 5)
00349 #define CPSW_ALE_WORD2_PORT_NUMBER_MASK        (3 << 2)
00350 #define CPSW_ALE_WORD2_PORT_NUMBER(n)          ((n) << 2)
00351 #define CPSW_ALE_WORD2_BLOCK                   (1 << 1)
00352 #define CPSW_ALE_WORD2_SECURE                  (1 << 0)
00353 #define CPSW_ALE_WORD1_UNICAST_TYPE_MASK       (3 << 30)
00354 #define CPSW_ALE_WORD1_UNICAST_TYPE(n)         ((n) << 30)
00355 
00356 //Multicast address table entry
00357 #define CPSW_ALE_WORD2_PORT_LIST_MASK          (3 << 2)
00358 #define CPSW_ALE_WORD2_PORT_LIST(n)            ((n) << 2)
00359 #define CPSW_ALE_WORD2_SUPER                   (1 << 1)
00360 #define CPSW_ALE_WORD1_MCAST_FWD_STATE_MASK    (3 << 30)
00361 #define CPSW_ALE_WORD1_MCAST_FWD_STATE(n)      ((n) << 30)
00362 
00363 //VLAN table entry
00364 #define CPSW_ALE_WORD1_VLAN_ID_MASK            (4095 << 16)
00365 #define CPSW_ALE_WORD1_VLAN_ID(n)              ((n) << 16)
00366 #define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS_MASK (7 << 24)
00367 #define CPSW_ALE_WORD0_FORCE_UNTAG_EGRESS(n)   ((n) << 24)
00368 #define CPSW_ALE_WORD0_REG_MCAST_FLOOD_MASK    (7 << 16)
00369 #define CPSW_ALE_WORD0_REG_MCAST_FLOOD(n)      ((n) << 16)
00370 #define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD_MASK  (7 << 8)
00371 #define CPSW_ALE_WORD0_UNREG_MCAST_FLOOD(n)    ((n) << 8)
00372 #define CPSW_ALE_WORD0_VLAN_MEMBER_LIST_MASK   (7 << 0)
00373 #define CPSW_ALE_WORD0_VLAN_MEMBER_LIST(n)     ((n) << 0)
00374 
00375 
00376 /**
00377  * @brief ALE table entry
00378  **/
00379 
00380 typedef struct
00381 {
00382    uint32_t word2;
00383    uint32_t word1;
00384    uint32_t word0;
00385 } Am335xAleEntry;
00386 
00387 
00388 /**
00389  * @brief TX buffer descriptor
00390  **/
00391 
00392 typedef struct _Am335xTxBufferDesc
00393 {
00394    uint32_t word0;
00395    uint32_t word1;
00396    uint32_t word2;
00397    uint32_t word3;
00398    struct _Am335xTxBufferDesc *next;
00399    struct _Am335xTxBufferDesc *prev;
00400 } Am335xTxBufferDesc;
00401 
00402 
00403 /**
00404  * @brief RX buffer descriptor
00405  **/
00406 
00407 typedef struct _Am335xRxBufferDesc
00408 {
00409    uint32_t word0;
00410    uint32_t word1;
00411    uint32_t word2;
00412    uint32_t word3;
00413    struct _Am335xRxBufferDesc *next;
00414    struct _Am335xRxBufferDesc *prev;
00415 } Am335xRxBufferDesc;
00416 
00417 
00418 //AM335x Ethernet MAC driver
00419 extern const NicDriver am335xEthPort1Driver;
00420 extern const NicDriver am335xEthPort2Driver;
00421 
00422 //AM335x Ethernet MAC related functions
00423 error_t am335xEthInitPort1(NetInterface *interface);
00424 error_t am335xEthInitPort2(NetInterface *interface);
00425 void am335xEthInitInstance(NetInterface *interface);
00426 void am335xEthInitGpio(NetInterface *interface);
00427 void am335xEthInitBufferDesc(NetInterface *interface);
00428 
00429 void am335xEthTick(NetInterface *interface);
00430 
00431 void am335xEthEnableIrq(NetInterface *interface);
00432 void am335xEthDisableIrq(NetInterface *interface);
00433 void am335xEthTxIrqHandler(void);
00434 void am335xEthRxIrqHandler(void);
00435 void am335xEthEventHandler(NetInterface *interface);
00436 
00437 error_t am335xEthSendPacketPort1(NetInterface *interface,
00438    const NetBuffer *buffer, size_t offset);
00439 
00440 error_t am335xEthSendPacketPort2(NetInterface *interface,
00441    const NetBuffer *buffer, size_t offset);
00442 
00443 error_t am335xEthSetMulticastFilter(NetInterface *interface);
00444 error_t am335xEthUpdateMacConfig(NetInterface *interface);
00445 
00446 void am335xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00447 uint16_t am335xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00448 
00449 void am335xEthWriteEntry(uint_t index, const Am335xAleEntry *entry);
00450 void am335xEthReadEntry(uint_t index, Am335xAleEntry *entry);
00451 
00452 uint_t am335xEthFindFreeEntry(void);
00453 uint_t am335xEthFindVlanEntry(uint_t vlanId);
00454 uint_t am335xEthFindVlanAddrEntry(uint_t vlanId, MacAddr *macAddr);
00455 
00456 error_t am335xEthAddVlanEntry(uint_t port, uint_t vlanId);
00457 error_t am335xEthAddVlanAddrEntry(uint_t port, uint_t vlanId, MacAddr *macAddr);
00458 error_t am335xEthDeleteVlanAddrEntry(uint_t port, uint_t vlanId, MacAddr *macAddr);
00459 
00460 #endif
00461