a2fxxxm3_eth.h

00001 /**
00002  * @file a2fxxxm3_eth.h
00003  * @brief SmartFusion (A2FxxxM3) Ethernet MAC controller
00004  *
00005  * @section License
00006  *
00007  * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
00008  *
00009  * This file is part of CycloneTCP Open.
00010  *
00011  * This program is free software; you can redistribute it and/or
00012  * modify it under the terms of the GNU General Public License
00013  * as published by the Free Software Foundation; either version 2
00014  * of the License, or (at your option) any later version.
00015  *
00016  * This program is distributed in the hope that it will be useful,
00017  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00018  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019  * GNU General Public License for more details.
00020  *
00021  * You should have received a copy of the GNU General Public License
00022  * along with this program; if not, write to the Free Software Foundation,
00023  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
00024  *
00025  * @author Oryx Embedded SARL (www.oryx-embedded.com)
00026  * @version 1.7.6
00027  **/
00028 
00029 #ifndef _A2FXXXM3_ETH_H
00030 #define _A2FXXXM3_ETH_H
00031 
00032 //Dependencies
00033 #include "core/nic.h"
00034 
00035 //Number of TX buffers
00036 #ifndef A2FXXXM3_ETH_TX_BUFFER_COUNT
00037    #define A2FXXXM3_ETH_TX_BUFFER_COUNT 2
00038 #elif (A2FXXXM3_ETH_TX_BUFFER_COUNT < 1)
00039    #error A2FXXXM3_ETH_TX_BUFFER_COUNT parameter is not valid
00040 #endif
00041 
00042 //TX buffer size
00043 #ifndef A2FXXXM3_ETH_TX_BUFFER_SIZE
00044    #define A2FXXXM3_ETH_TX_BUFFER_SIZE 1536
00045 #elif (A2FXXXM3_ETH_TX_BUFFER_SIZE != 1536)
00046    #error A2FXXXM3_ETH_TX_BUFFER_SIZE parameter is not valid
00047 #endif
00048 
00049 //Number of RX buffers
00050 #ifndef A2FXXXM3_ETH_RX_BUFFER_COUNT
00051    #define A2FXXXM3_ETH_RX_BUFFER_COUNT 4
00052 #elif (A2FXXXM3_ETH_RX_BUFFER_COUNT < 1)
00053    #error A2FXXXM3_ETH_RX_BUFFER_COUNT parameter is not valid
00054 #endif
00055 
00056 //RX buffer size
00057 #ifndef A2FXXXM3_ETH_RX_BUFFER_SIZE
00058    #define A2FXXXM3_ETH_RX_BUFFER_SIZE 1536
00059 #elif (A2FXXXM3_ETH_RX_BUFFER_SIZE != 1536)
00060    #error A2FXXXM3_ETH_RX_BUFFER_SIZE parameter is not valid
00061 #endif
00062 
00063 //Interrupt priority grouping
00064 #ifndef A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING
00065    #define A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING 2
00066 #elif (A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING < 0)
00067    #error A2FXXXM3_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
00068 #endif
00069 
00070 //Ethernet interrupt group priority
00071 #ifndef A2FXXXM3_ETH_IRQ_GROUP_PRIORITY
00072    #define A2FXXXM3_ETH_IRQ_GROUP_PRIORITY 24
00073 #elif (A2FXXXM3_ETH_IRQ_GROUP_PRIORITY < 0)
00074    #error A2FXXXM3_ETH_IRQ_GROUP_PRIORITY parameter is not valid
00075 #endif
00076 
00077 //Ethernet interrupt subpriority
00078 #ifndef A2FXXXM3_ETH_IRQ_SUB_PRIORITY
00079    #define A2FXXXM3_ETH_IRQ_SUB_PRIORITY 0
00080 #elif (A2FXXXM3_ETH_IRQ_SUB_PRIORITY < 0)
00081    #error A2FXXXM3_ETH_IRQ_SUB_PRIORITY parameter is not valid
00082 #endif
00083 
00084 //MDEN bit definition
00085 #ifndef CSR9_MDEN_MASK
00086    #define CSR9_MDEN_MASK CSR9_MII_MASK
00087 #endif
00088 
00089 //Serial Management Interface
00090 #define SMI_SYNC  0xFFFFFFFF
00091 #define SMI_START 0x00000001
00092 #define SMI_WRITE 0x00000001
00093 #define SMI_READ  0x00000002
00094 #define SMI_TA    0x00000002
00095 
00096 
00097 /**
00098  * @brief Transmit DMA descriptor
00099  **/
00100 
00101 typedef struct
00102 {
00103    uint32_t tdes0;
00104    uint32_t tdes1;
00105    uint32_t tdes2;
00106    uint32_t tdes3;
00107 } A2fxxxm3TxDmaDesc;
00108 
00109 
00110 /**
00111  * @brief Receive DMA descriptor
00112  **/
00113 
00114 typedef struct
00115 {
00116    uint32_t rdes0;
00117    uint32_t rdes1;
00118    uint32_t rdes2;
00119    uint32_t rdes3;
00120 } A2fxxxm3RxDmaDesc;
00121 
00122 
00123 /**
00124  * @brief Hash table setup frame
00125  **/
00126 
00127 typedef struct
00128 {
00129    uint32_t hashFilter[32];  //0-127
00130    uint32_t reserved1[7];    //128-155
00131    uint32_t physicalAddr[3]; //156-167
00132    uint32_t reserved2[6];    //168-191
00133 } A2fxxxm3HashTableSetupFrame;
00134 
00135 
00136 //A2FxxxM3 Ethernet MAC driver
00137 extern const NicDriver a2fxxxm3EthDriver;
00138 
00139 //A2FxxxM3 Ethernet MAC related functions
00140 error_t a2fxxxm3EthInit(NetInterface *interface);
00141 void a2fxxxm3EthInitDmaDesc(NetInterface *interface);
00142 
00143 void a2fxxxm3EthTick(NetInterface *interface);
00144 
00145 void a2fxxxm3EthEnableIrq(NetInterface *interface);
00146 void a2fxxxm3EthDisableIrq(NetInterface *interface);
00147 void a2fxxxm3EthEventHandler(NetInterface *interface);
00148 
00149 error_t a2fxxxm3EthSendSetup(NetInterface *interface);
00150 
00151 error_t a2fxxxm3EthSendPacket(NetInterface *interface,
00152    const NetBuffer *buffer, size_t offset);
00153 
00154 error_t a2fxxxm3EthReceivePacket(NetInterface *interface);
00155 
00156 error_t a2fxxxm3EthSetMulticastFilter(NetInterface *interface);
00157 error_t a2fxxxm3EthUpdateMacConfig(NetInterface *interface);
00158 
00159 void a2fxxxm3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
00160 uint16_t a2fxxxm3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
00161 
00162 void a2fxxxm3EthWriteSmi(uint32_t data, uint_t length);
00163 uint32_t a2fxxxm3EthReadSmi(uint_t length);
00164 
00165 uint32_t a2fxxxm3EthCalcCrc(const void *data, size_t length);
00166 
00167 #endif
00168