bluenrg_shield_bsp.h

00001 #ifndef __BLUENRG_SHIELD_BRP_H_
00002 #define __BLUENRG_SHIELD_BRP_H_
00003 
00004 #ifdef __cplusplus
00005  extern "C" {
00006 #endif
00007 
00008 /* Includes ------------------------------------------------------------------*/
00009 #include "cube_hal.h"
00010 #include "gp_timer.h"
00011 
00012 /* SPI communication details between Nucleo F4 and BlueNRG shield */
00013 
00014 // SPI Instance
00015 #define BNRG_SPI_INSTANCE               SPI1
00016 #define BNRG_SPI_CLK_ENABLE()               __SPI1_CLK_ENABLE()
00017 
00018 // SPI Configuration
00019 #define BNRG_SPI_MODE                   SPI_MODE_MASTER
00020 #define BNRG_SPI_DIRECTION              SPI_DIRECTION_2LINES
00021 #define BNRG_SPI_DATASIZE               SPI_DATASIZE_8BIT
00022 #define BNRG_SPI_CLKPOLARITY                SPI_POLARITY_LOW
00023 #define BNRG_SPI_CLKPHASE               SPI_PHASE_1EDGE
00024 #define BNRG_SPI_NSS                    SPI_NSS_SOFT
00025 #define BNRG_SPI_FIRSTBIT               SPI_FIRSTBIT_MSB
00026 #define BNRG_SPI_TIMODE                 SPI_TIMODE_DISABLED
00027 #define BNRG_SPI_CRCPOLYNOMIAL              7
00028 #define BNRG_SPI_BAUDRATEPRESCALER          SPI_BAUDRATEPRESCALER_4
00029 #define BNRG_SPI_CRCCALCULATION             SPI_CRCCALCULATION_DISABLED
00030 
00031 // SPI Reset Pin: PA.8
00032 #define BNRG_SPI_RESET_PIN              GPIO_PIN_8
00033 #define BNRG_SPI_RESET_MODE             GPIO_MODE_OUTPUT_PP
00034 #define BNRG_SPI_RESET_PULL             GPIO_NOPULL
00035 #define BNRG_SPI_RESET_SPEED                GPIO_SPEED_LOW
00036 #define BNRG_SPI_RESET_ALTERNATE            0
00037 #define BNRG_SPI_RESET_PORT             GPIOA
00038 #define BNRG_SPI_RESET_CLK_ENABLE()         __GPIOA_CLK_ENABLE()
00039 
00040 
00041 #ifdef USE_PA5
00042 // SPI Clock (SCLK): PA.5
00043 #define BNRG_SPI_SCLK_PIN               GPIO_PIN_5
00044 #define BNRG_SPI_SCLK_MODE              GPIO_MODE_AF_PP
00045 #define BNRG_SPI_SCLK_PULL              GPIO_PULLDOWN
00046 #define BNRG_SPI_SCLK_SPEED             GPIO_SPEED_HIGH
00047 #define BNRG_SPI_SCLK_ALTERNATE             GPIO_AF5_SPI1
00048 #define BNRG_SPI_SCLK_PORT              GPIOA
00049 #define BNRG_SPI_SCLK_CLK_ENABLE()          __GPIOA_CLK_ENABLE()
00050 
00051 #else //USE_PA5
00052 
00053 // Alternative setting for SCLK: PB.3
00054 #define BNRG_SPI_SCLK_PIN               GPIO_PIN_3
00055 #define BNRG_SPI_SCLK_MODE              GPIO_MODE_AF_PP
00056 #define BNRG_SPI_SCLK_PULL              GPIO_PULLUP // or GPIO_PULLDOWN?
00057 #define BNRG_SPI_SCLK_SPEED             GPIO_SPEED_HIGH
00058 #define BNRG_SPI_SCLK_ALTERNATE             GPIO_AF5_SPI1
00059 #define BNRG_SPI_SCLK_PORT              GPIOB
00060 #define BNRG_SPI_SCLK_CLK_ENABLE()          __GPIOB_CLK_ENABLE()
00061 
00062 #endif //USE_PA5
00063 
00064 // MISO (Master Input Slave Output): PA.6
00065 #define BNRG_SPI_MISO_PIN               GPIO_PIN_6
00066 #define BNRG_SPI_MISO_MODE              GPIO_MODE_AF_PP
00067 #define BNRG_SPI_MISO_PULL              GPIO_PULLDOWN
00068 #define BNRG_SPI_MISO_SPEED             GPIO_SPEED_HIGH
00069 #define BNRG_SPI_MISO_ALTERNATE             GPIO_AF5_SPI1
00070 #define BNRG_SPI_MISO_PORT              GPIOA
00071 #define BNRG_SPI_MISO_CLK_ENABLE()          __GPIOA_CLK_ENABLE()
00072 
00073 
00074 // MOSI (Master Output Slave Input): PA.7
00075 #define BNRG_SPI_MOSI_PIN           GPIO_PIN_7
00076 #define BNRG_SPI_MOSI_MODE          GPIO_MODE_AF_PP
00077 #define BNRG_SPI_MOSI_PULL          GPIO_PULLUP
00078 #define BNRG_SPI_MOSI_SPEED         GPIO_SPEED_HIGH
00079 #define BNRG_SPI_MOSI_ALTERNATE             GPIO_AF5_SPI1
00080 #define BNRG_SPI_MOSI_PORT          GPIOA
00081 #define BNRG_SPI_MOSI_CLK_ENABLE()          __GPIOA_CLK_ENABLE()
00082 
00083 // NSS/CSN/CS: PA.1
00084 #define BNRG_SPI_CS_PIN             GPIO_PIN_1
00085 #define BNRG_SPI_CS_MODE            GPIO_MODE_OUTPUT_PP
00086 #define BNRG_SPI_CS_PULL            GPIO_NOPULL
00087 #define BNRG_SPI_CS_SPEED           GPIO_SPEED_HIGH
00088 #define BNRG_SPI_CS_ALTERNATE               0
00089 #define BNRG_SPI_CS_PORT            GPIOA
00090 #define BNRG_SPI_CS_CLK_ENABLE()            __GPIOA_CLK_ENABLE()
00091 
00092 // IRQ: PA.0
00093 #define BNRG_SPI_IRQ_PIN            GPIO_PIN_0
00094 #define BNRG_SPI_IRQ_MODE           GPIO_MODE_IT_RISING
00095 #define BNRG_SPI_IRQ_PULL           GPIO_NOPULL
00096 #define BNRG_SPI_IRQ_SPEED          GPIO_SPEED_HIGH
00097 #define BNRG_SPI_IRQ_ALTERNATE              0
00098 #define BNRG_SPI_IRQ_PORT           GPIOA
00099 #define BNRG_SPI_IRQ_CLK_ENABLE()           __GPIOA_CLK_ENABLE()
00100 
00101 // EXTI External Interrupt for SPI
00102 // NOTE: if you change the IRQ pin remember to implement a corresponding handler
00103 // function like EXTI0_IRQHandler() in the user project
00104 #define BNRG_SPI_EXTI_IRQn          EXTI0_IRQn
00105 #define BNRG_SPI_EXTI_PIN           BNRG_SPI_IRQ_PIN
00106 #define BNRG_SPI_EXTI_PORT          BNRG_SPI_IRQ_PORT
00107 
00108 /* Exported functions --------------------------------------------------------*/
00109 void BNRG_SPI_Init(void);
00110 void BlueNRG_RST(void);
00111 int32_t BlueNRG_SPI_Read_All(SPI_HandleTypeDef *hspi,
00112                              uint8_t *buffer,
00113                              uint8_t buff_size);
00114 int32_t BlueNRG_SPI_Write(SPI_HandleTypeDef *hspi,
00115                           uint8_t* data1,
00116                           uint8_t* data2,
00117                           uint8_t Nb_bytes1,
00118                           uint8_t Nb_bytes2);
00119 void Hal_Write_Serial(const void* data1, const void* data2, tHalInt32 n_bytes1, tHalInt32 n_bytes2);
00120 void Enable_SPI_IRQ(void);
00121 void Disable_SPI_IRQ(void);
00122 void Clear_SPI_IRQ(void);
00123 void Clear_SPI_EXTI_Flag(void);
00124 
00125 #ifdef __cplusplus
00126 }
00127 #endif
00128 
00129 #endif //_BLUENRG_SHIELD_BRP_H_