max32600.h

00001 /*******************************************************************************
00002 * Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
00003 *
00004 * Permission is hereby granted, free of charge, to any person obtaining a
00005 * copy of this software and associated documentation files (the "Software"),
00006 * to deal in the Software without restriction, including without limitation
00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00008 * and/or sell copies of the Software, and to permit persons to whom the
00009 * Software is furnished to do so, subject to the following conditions:
00010 *
00011 * The above copyright notice and this permission notice shall be included
00012 * in all copies or substantial portions of the Software.
00013 *
00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020 * OTHER DEALINGS IN THE SOFTWARE.
00021 *
00022 * Except as contained in this notice, the name of Maxim Integrated 
00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 
00024 * Products, Inc. Branding Policy.
00025 *
00026 * The mere transfer of this software does not imply any licenses
00027 * of trade secrets, proprietary technology, copyrights, patents,
00028 * trademarks, maskwork rights, or any other form of intellectual
00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 
00030 * ownership rights.
00031 *******************************************************************************
00032 */
00033 
00034 /* $Revision: 4395 $ $Date: 2015-02-17 15:52:32 -0600 (Tue, 17 Feb 2015) $ */
00035 
00036 #include <stdint.h>
00037 
00038 #ifndef _MAX32600_H_
00039 #define _MAX32600_H_
00040 
00041 #ifndef  FALSE
00042 #define  FALSE      (0)
00043 #endif
00044 
00045 #ifndef  TRUE
00046 #define  TRUE       (1)
00047 #endif
00048 
00049 #define __NVIC_PRIO_BITS 3
00050 
00051 typedef enum IRQn_Type { 
00052     NonMaskableInt_IRQn = -14, 
00053     HardFault_IRQn = -13, 
00054     MemoryManagement_IRQn = -12, 
00055     BusFault_IRQn = -11, 
00056     UsageFault_IRQn = -10, 
00057     SVCall_IRQn = -5, 
00058     DebugMonitor_IRQn = -4, 
00059     PendSV_IRQn = -2, 
00060     SysTick_IRQn = -1, 
00061 
00062     /* Maxim 32600 Externals interrupts */
00063     UART0_IRQn = 0,      /* 16:01 UART0 */
00064     UART1_IRQn,          /* 17: 2 UART1 */
00065     I2CM0_IRQn,          /* 18: 3 I2C Master 0 */
00066     I2CS_IRQn,           /* 19: 4 I2C Slave */
00067     USB_IRQn,            /* 20: 5 USB */
00068     PMU_IRQn,            /* 21: 6 DMA */
00069     AFE_IRQn,            /* 22: 7 AFE */
00070     MAA_IRQn,            /* 23: 8 MAA */
00071     AES_IRQn,            /* 24: 9 AES */
00072     SPI0_IRQn,           /* 25:10 SPI0 */
00073     SPI1_IRQn,           /* 26:11 SPI1 */
00074     SPI2_IRQn,           /* 27:12 SPI2 */
00075     TMR0_IRQn,           /* 28:13 Timer32-0 */
00076     TMR1_IRQn,           /* 29:14 Timer32-1 */
00077     TMR2_IRQn,           /* 30:15 Timer32-1 */
00078     TMR3_IRQn,           /* 31:16 Timer32-2 */
00079     RSVD0_IRQn,          /* 32:17 RSVD */
00080     RSVD1_IRQn,          /* 33:18 RSVD */
00081     DAC0_IRQn,           /* 34:19 DAC0  (12-bit DAC) */  
00082     DAC1_IRQn,           /* 35:20 DAC1  (12-bit DAC) */  
00083     DAC2_IRQn,           /* 36:21 DAC2  (8-bit DAC) */
00084     DAC3_IRQn,           /* 37:22 DAC3  (8-bit DAC) */
00085     ADC_IRQn,            /* 38:23 ADC */
00086     FLC_IRQn,            /* 39:24 Flash Controller */
00087     PWRMAN_IRQn,         /* 40:25 PWRMAN */
00088     CLKMAN_IRQn,         /* 41:26 CLKMAN */
00089     RTC0_IRQn,           /* 42:27 RTC INT0 */
00090     RTC1_IRQn,           /* 43:28 RTC INT1 */
00091     RTC2_IRQn,           /* 44:29 RTC INT2 */
00092     RTC3_IRQn,           /* 45:30 RTC INT3 */
00093     WDT0_IRQn,           /* 46:31 WATCHDOG0 */
00094     WDT0_P_IRQn,         /* 47:32 WATCHDOG0 PRE-WINDOW */
00095     WDT1_IRQn,           /* 48:33 WATCHDOG1 */
00096     WDT1_P_IRQn,         /* 49:34 WATCHDOG1 PRE-WINDOW */
00097     GPIO_P0_IRQn,        /* 50:35 GPIO Port 0  */
00098     GPIO_P1_IRQn,        /* 51:36 GPIO Port 1  */
00099     GPIO_P2_IRQn,        /* 52:37 GPIO Port 2  */
00100     GPIO_P3_IRQn,        /* 53:38 GPIO Port 3  */
00101     GPIO_P4_IRQn,        /* 54:39 GPIO Port 4  */
00102     GPIO_P5_IRQn,        /* 55:40 GPIO Port 5  */
00103     GPIO_P6_IRQn,        /* 56:41 GPIO Port 6  */
00104     GPIO_P7_IRQn,        /* 57:42 GPIO Port 7  */
00105     TMR16_0_IRQn,        /* 58:43 Timer16-s0 */
00106     TMR16_1_IRQn,        /* 59:44 Timer16-s1 */
00107     TMR16_2_IRQn,        /* 60:45 Timer16-s2 */
00108     TMR16_3_IRQn,        /* 61:46 Timer16-s3 */
00109     I2CM1_IRQn,          /* 62:47 I2C Master 1 */
00110     MXC_IRQ_EXT_COUNT,
00111 } IRQn_Type;
00112 
00113 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
00114 
00115 #include "core_cm3.h"
00116 #include "system_max32600.h"
00117 
00118 /*
00119    Base addresses and configuration settings for all MAX32600 peripheral modules.
00120 */
00121 
00122 /*******************************************************************************/
00123 /*                                            General Purpose I/O Ports (GPIO) */
00124 
00125 
00126 #define MXC_BASE_GPIO                   ((uint32_t)0x40000000UL)
00127 #define MXC_GPIO                        ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
00128 #define MXC_BASE_GPIO_BITBAND           ((uint32_t)0x42000000UL)
00129 
00130 
00131 /*******************************************************************************/
00132 /*                                                      Pulse Train Generation */
00133 
00134 #define MXC_CFG_PT_INSTANCES             (13)
00135 
00136 #define MXC_BASE_PTG                     ((uint32_t)0x40001000UL)
00137 #define MXC_PTG                          ((mxc_ptg_regs_t *)MXC_BASE_PTG)
00138 #define MXC_BASE_PT                      ((uint32_t)0x40001008UL)
00139 #define MXC_PT                           ((mxc_pt_regs_t *)MXC_BASE_PT)
00140 #define MXC_BASE_PT0                     ((uint32_t)0x40001008UL)
00141 #define MXC_PT0                          ((mxc_pt_regs_t *)MXC_BASE_PT0)
00142 #define MXC_BASE_PT1                     ((uint32_t)0x40001010UL)
00143 #define MXC_PT1                          ((mxc_pt_regs_t *)MXC_BASE_PT1)
00144 #define MXC_BASE_PT2                     ((uint32_t)0x40001018UL)
00145 #define MXC_PT2                          ((mxc_pt_regs_t *)MXC_BASE_PT2)
00146 #define MXC_BASE_PT3                     ((uint32_t)0x40001020UL)
00147 #define MXC_PT3                          ((mxc_pt_regs_t *)MXC_BASE_PT3)
00148 #define MXC_BASE_PT4                     ((uint32_t)0x40001028UL)
00149 #define MXC_PT4                          ((mxc_pt_regs_t *)MXC_BASE_PT4)
00150 #define MXC_BASE_PT5                     ((uint32_t)0x40001030UL)
00151 #define MXC_PT5                          ((mxc_pt_regs_t *)MXC_BASE_PT5)
00152 #define MXC_BASE_PT6                     ((uint32_t)0x40001038UL)
00153 #define MXC_PT6                          ((mxc_pt_regs_t *)MXC_BASE_PT6)
00154 #define MXC_BASE_PT7                     ((uint32_t)0x40001040UL)
00155 #define MXC_PT7                          ((mxc_pt_regs_t *)MXC_BASE_PT7)
00156 #define MXC_BASE_PT8                     ((uint32_t)0x40001048UL)
00157 #define MXC_PT8                          ((mxc_pt_regs_t *)MXC_BASE_PT8)
00158 #define MXC_BASE_PT9                     ((uint32_t)0x40001050UL)
00159 #define MXC_PT9                          ((mxc_pt_regs_t *)MXC_BASE_PT9)
00160 #define MXC_BASE_PT10                    ((uint32_t)0x40001058UL)
00161 #define MXC_PT10                         ((mxc_pt_regs_t *)MXC_BASE_PT10)
00162 #define MXC_BASE_PT11                    ((uint32_t)0x40001060UL)
00163 #define MXC_PT11                         ((mxc_pt_regs_t *)MXC_BASE_PT11)
00164 
00165 /*                                       PT12, PT13, PT14 are not used         */
00166 
00167 /*******************************************************************************/
00168 /*                                                        CRC-16/CRC-32 Engine */
00169 
00170 #define MXC_BASE_CRC                    ((uint32_t)0x40010000UL)
00171 #define MXC_CRC_REGS                    ((mxc_crc_regs_t *)MXC_BASE_CRC)
00172 
00173 #define MXC_BASE_CRC_DATA               ((uint32_t)0x4010B000UL)
00174 #define MXC_CRC_DATA                    ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
00175 
00176 /*******************************************************************************/
00177 /*                                                 Trust Protection Unit (TPU) */
00178 
00179 #define MXC_BASE_TPU                     ((uint32_t)0x40011000UL)
00180 #define MXC_TPU                          ((mxc_tpu_regs_t *)MXC_BASE_TPU)
00181 
00182 #define MXC_BASE_TPU_TSR                 ((uint32_t)0x40011C00UL)
00183 #define MXC_TPU_TSR                      ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
00184 
00185 /*******************************************************************************/
00186 /*                                                    AES Cryptographic Engine */
00187 
00188 #define MXC_BASE_AES                     ((uint32_t)0x40011400UL)
00189 #define MXC_AES                          ((mxc_aes_regs_t *)MXC_BASE_AES)
00190 
00191 #define MXC_BASE_AES_MEM                 ((uint32_t)0x4010A000UL)
00192 #define MXC_AES_MEM                      ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
00193 
00194 
00195 /*******************************************************************************/
00196 /*                                                    MAA Cryptographic Engine */
00197 
00198 #define MXC_BASE_MAA                     ((uint32_t)0x40011800UL)
00199 #define MXC_MAA                          ((mxc_maa_regs_t *)MXC_BASE_MAA)
00200 
00201 #define MXC_BASE_MAA_MEM                 ((uint32_t)0x4010A800UL)
00202 #define MXC_MAA_MEM                      ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
00203 
00204 /*******************************************************************************/
00205 /*                                                    32-Bit PWM Timer/Counter */
00206 
00207 #define MXC_CFG_TMR_INSTANCES            (4)
00208 
00209 #define MXC_BASE_TMR0                    ((uint32_t)0x40012000UL)
00210 #define MXC_BASE_TMR0_BITBAND            ((uint32_t)0x42240000UL)
00211 #define MXC_TMR0                         ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
00212 
00213 #define MXC_BASE_TMR1                    ((uint32_t)0x40013000UL)
00214 #define MXC_BASE_TMR1_BITBAND            ((uint32_t)0x42260000UL)
00215 #define MXC_TMR1                         ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
00216 
00217 #define MXC_BASE_TMR2                    ((uint32_t)0x40014000UL)
00218 #define MXC_BASE_TMR2_BITBAND            ((uint32_t)0x42280000UL)
00219 #define MXC_TMR2                         ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
00220 
00221 #define MXC_BASE_TMR3                    ((uint32_t)0x40015000UL)
00222 #define MXC_BASE_TMR3_BITBAND            ((uint32_t)0x422A0000UL)
00223 #define MXC_TMR3                         ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
00224 
00225 
00226 #define MXC_TMR_GET_IRQ_32(i)            ((i) == 0 ? TMR0_IRQn :    \
00227                                           (i) == 1 ? TMR1_IRQn :    \
00228                                           (i) == 2 ? TMR2_IRQn :    \
00229                                           (i) == 3 ? TMR3_IRQn : 0)
00230 
00231 #define MXC_TMR_GET_IRQ_16(i)            ((i) == 0 ? TMR0_IRQn :    \
00232                                           (i) == 1 ? TMR1_IRQn :    \
00233                                           (i) == 2 ? TMR2_IRQn :    \
00234                                           (i) == 3 ? TMR3_IRQn :    \
00235                                           (i) == 4 ? TMR16_0_IRQn :    \
00236                                           (i) == 5 ? TMR16_1_IRQn :    \
00237                                           (i) == 6 ? TMR16_2_IRQn :    \
00238                                           (i) == 7 ? TMR16_3_IRQn : 0)
00239 
00240 #define MXC_TMR_GET_BASE(i)              ((i) == 0 ? MXC_BASE_TMR0 : \
00241                                           (i) == 1 ? MXC_BASE_TMR1 : \
00242                                           (i) == 2 ? MXC_BASE_TMR2 : \
00243                                           (i) == 3 ? MXC_BASE_TMR3 : 0)
00244 
00245 #define MXC_TMR_GET_TMR(i)               ((i) == 0 ? MXC_TMR0 : \
00246                                           (i) == 1 ? MXC_TMR1 : \
00247                                           (i) == 2 ? MXC_TMR2 : \
00248                                           (i) == 3 ? MXC_TMR3 : 0)
00249 /*******************************************************************************/
00250 /*                                                              Watchdog Timer */
00251 
00252 #define MXC_CFG_WDT_INSTANCES            (2)
00253 
00254 #define MXC_BASE_WDT0                    ((uint32_t)0x40021000UL)
00255 #define MXC_BASE_WDT0_BITBAND            ((uint32_t)0x42420000UL)
00256 #define MXC_WDT0                         ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
00257 
00258 #define MXC_BASE_WDT1                    ((uint32_t)0x40022000UL)
00259 #define MXC_BASE_WDT1_BITBAND            ((uint32_t)0x42440000UL)
00260 #define MXC_WDT1                         ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
00261 
00262 #define MXC_WDT_GET_IRQ(i)               ((i) == 0 ? WDT0_IRQn : \
00263                                           (i) == 1 ? WDT1_IRQn : 0)
00264 
00265 #define MXC_WDT_GET_IRQ_P(i)             ((i) == 0 ? WDT0_P_IRQn : \
00266                                           (i) == 1 ? WDT1_P_IRQn : 0)
00267 
00268 #define MXC_WDT_GET_BASE(i)              ((i) == 0 ? MXC_BASE_WDT0 : \
00269                                           (i) == 1 ? MXC_BASE_WDT1 : 0)
00270 
00271 #define MXC_WDT_GET_WDT(i)               ((i) == 0 ? MXC_WDT0 : \
00272                                           (i) == 1 ? MXC_WDT1 : 0)
00273 
00274 /*******************************************************************************/
00275 /*                                                               SPI Interface */
00276 
00277 #define MXC_CFG_SPI_INSTANCES            (3)
00278 #define MXC_CFG_SPI_FIFO_DEPTH           (16)
00279 
00280 
00281 #define MXC_BASE_SPI0                    ((uint32_t)0x40030000UL)
00282 #define MXC_SPI0                         ((mxc_spi_regs_t *)MXC_BASE_SPI0)
00283 
00284 #define MXC_BASE_SPI0_FIFO               ((uint32_t)0x40100000UL)
00285 #define MXC_SPI0_FIFO                    ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI0_FIFO)
00286 
00287 #define MXC_BASE_SPI1                    ((uint32_t)0x40031000UL)
00288 #define MXC_SPI1                         ((mxc_spi_regs_t *)MXC_BASE_SPI1)
00289 
00290 #define MXC_BASE_SPI1_FIFO               ((uint32_t)0x40101000UL)
00291 #define MXC_SPI1_FIFO                    ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI1_FIFO)
00292 
00293 #define MXC_BASE_SPI2                    ((uint32_t)0x40032000UL)
00294 #define MXC_SPI2                         ((mxc_spi_regs_t *)MXC_BASE_SPI2)
00295 
00296 #define MXC_BASE_SPI2_FIFO               ((uint32_t)0x40102000UL)
00297 #define MXC_SPI2_FIFO                    ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI2_FIFO)
00298 
00299 
00300 #define MXC_SPI_GET_IRQ(i)               ((i) == 0 ? SPI0_IRQn :       \
00301                                           (i) == 1 ? SPI1_IRQn :       \
00302                                           (i) == 2 ? SPI2_IRQn : 0)
00303 
00304 #define MXC_SPI_GET_BASE(i)              ((i) == 0 ? MXC_BASE_SPI0 :      \
00305                                           (i) == 1 ? MXC_BASE_SPI1 :      \
00306                                           (i) == 2 ? MXC_BASE_SPI2 : 0)
00307 
00308 #define MXC_SPI_GET_SPI(i)               ((i) == 0 ? MXC_SPI0 :      \
00309                                           (i) == 1 ? MXC_SPI1 :      \
00310                                           (i) == 2 ? MXC_SPI2 : 0)
00311 
00312 #define MXC_SPI_GET_BASE_FIFO(i)         ((i) == 0 ? MXC_BASE_SPI0_FIFO :     \
00313                                           (i) == 1 ? MXC_BASE_SPI1_FIFO :     \
00314                                           (i) == 2 ? MXC_BASE_SPI2_FIFO : 0)
00315 
00316 #define MXC_SPI_GET_SPI_FIFO(i)          ((i) == 0 ? MXC_SPI0_FIFO :      \
00317                                           (i) == 1 ? MXC_SPI1_FIFO :      \
00318                                           (i) == 2 ? MXC_SPI2_FIFO : 0)
00319 
00320 
00321 /*******************************************************************************/
00322 /*                                                              UART Interface */
00323 
00324 #define MXC_CFG_UART_INSTANCES           (2)
00325 
00326 #define MXC_BASE_UART0                   ((uint32_t)0x40038000UL)
00327 #define MXC_BASE_UART0_BITBAND           ((uint32_t)0x42700000UL)
00328 #define MXC_UART0                        ((mxc_uart_regs_t *)MXC_BASE_UART0)
00329 
00330 #define MXC_BASE_UART1                   ((uint32_t)0x40039000UL)
00331 #define MXC_BASE_UART1_BITBAND           ((uint32_t)0x42720000UL)
00332 #define MXC_UART1                        ((mxc_uart_regs_t *)MXC_BASE_UART1)
00333 
00334 
00335 #define MXC_UART_GET_IRQ(i)              ((i) == 0 ? UART0_IRQn :      \
00336                                           (i) == 1 ? UART1_IRQn : 0)
00337 
00338 #define MXC_UART_GET_BASE(i)             ((i) == 0 ? MXC_BASE_UART0 :     \
00339                                           (i) == 1 ? MXC_BASE_UART1 : 0)
00340 
00341 #define MXC_UART_GET_UART(i)             ((i) == 0 ? MXC_UART0 :     \
00342                                           (i) == 1 ? MXC_UART1 : 0)
00343 
00344 #define MXC_CFG_UART_FIFO_DEPTH           (8)
00345 
00346 
00347 /*******************************************************************************/
00348 /*                                                        I2C Master Interface */
00349 
00350 #define MXC_CFG_I2CM_INSTANCES           (2)
00351 
00352 #define MXC_BASE_I2CM0                   ((uint32_t)0x40040000UL)
00353 #define MXC_BASE_I2CM0_BITBAND           ((uint32_t)0x42800000UL)
00354 #define MXC_I2CM0                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
00355 
00356 #define MXC_BASE_I2CM0_FIFO              ((uint32_t)0x40103000UL)
00357 
00358 #define MXC_BASE_I2CM1                   ((uint32_t)0x40042000UL)
00359 #define MXC_BASE_I2CM1_BITBAND           ((uint32_t)0x42840000UL)
00360 #define MXC_I2CM1                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
00361 
00362 #define MXC_BASE_I2CM1_FIFO              ((uint32_t)0x4010D000UL)
00363 
00364 
00365 #define MXC_I2CM_GET_IRQ(i)              ((i) == 0 ? I2CM0_IRQn :      \
00366                                           (i) == 1 ? I2CM1_IRQn : 0)
00367 
00368 #define MXC_I2CM_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2CM0 :     \
00369                                           (i) == 1 ? MXC_BASE_I2CM1 : 0)
00370 
00371 #define MXC_I2CM_GET_I2CM(i)             ((i) == 0 ? MXC_I2CM0 :     \
00372                                           (i) == 1 ? MXC_I2CM1 : 0)
00373 
00374 #define MXC_I2CM_GET_BASE_FIFO(i)        ((i) == 0 ? MXC_BASE_I2CM0_FIFO :       \
00375                                           (i) == 1 ? MXC_BASE_I2CM1_FIFO : 0)
00376 
00377 
00378 /*******************************************************************************/
00379 /*                                                         I2C Slave Interface */
00380 
00381 #define MXC_CFG_I2CS_INSTANCES           (1)
00382 
00383 #define MXC_BASE_I2CS0                   ((uint32_t)0x40041000UL)
00384 #define MXC_BASE_I2CS0_BITBAND           ((uint32_t)0x42820000UL)
00385 #define MXC_I2CS0                        ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
00386 
00387 #define MXC_BASE_I2CS0_FIFO              ((uint32_t)0x40104000UL)
00388 #define MXC_I2CS0_FIFO                   ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
00389 
00390 
00391 
00392 /*******************************************************************************/
00393 /*                                                                        DACs */
00394 
00395 #define MXC_CFG_DAC_INSTANCES            (4)
00396 #define MXC_CFG_DAC_FIFO_DEPTH           (32)
00397 
00398 #define MXC_BASE_DAC0                    ((uint32_t)0x40050000UL)
00399 #define MXC_DAC0                         ((mxc_dac_regs_t *)MXC_BASE_DAC0)
00400 #define MXC_BASE_DAC0_FIFO               ((uint32_t)0x40105000UL)
00401 #define MXC_DAC0_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
00402 #define MXC_DAC0_WIDTH                   ((uint8_t)(2))
00403 
00404 #define MXC_BASE_DAC1                    ((uint32_t)0x40051000UL)
00405 #define MXC_DAC1                         ((mxc_dac_regs_t *)MXC_BASE_DAC1)
00406 #define MXC_BASE_DAC1_FIFO               ((uint32_t)0x40106000UL)
00407 #define MXC_DAC1_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
00408 #define MXC_DAC1_WIDTH                   ((uint8_t)(2))
00409 
00410 #define MXC_BASE_DAC2                    ((uint32_t)0x40052000UL)
00411 #define MXC_DAC2                         ((mxc_dac_regs_t *)MXC_BASE_DAC2)
00412 #define MXC_BASE_DAC2_FIFO               ((uint32_t)0x40107000UL)
00413 #define MXC_DAC2_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
00414 #define MXC_DAC2_WIDTH                   ((uint8_t)(1))
00415 
00416 #define MXC_BASE_DAC3                    ((uint32_t)0x40053000UL)
00417 #define MXC_DAC3                         ((mxc_dac_regs_t *)MXC_BASE_DAC3)
00418 #define MXC_BASE_DAC3_FIFO               ((uint32_t)0x40108000UL)
00419 #define MXC_DAC3_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
00420 #define MXC_DAC3_WIDTH                   ((uint8_t)(1))
00421 
00422 
00423 #define MXC_DAC_GET_IRQ(i)               ((i) == 0 ? DAC0_IRQn :     \
00424                                           (i) == 1 ? DAC1_IRQn :     \
00425                                           (i) == 2 ? DAC2_IRQn :     \
00426                                           (i) == 3 ? DAC3_IRQn : 0)
00427 
00428 
00429 #define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
00430                              i == 1 ? MXC_BASE_DAC1 : \
00431                              i == 2 ? MXC_BASE_DAC2 : \
00432                              i == 3 ? MXC_BASE_DAC3 : 0)
00433 
00434 #define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
00435                              i == 1 ? MXC_BASE_DAC1_FIFO : \
00436                              i == 2 ? MXC_BASE_DAC2_FIFO  : \
00437                              i == 3 ? MXC_BASE_DAC3_FIFO  : 0)
00438 
00439 #define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
00440                                      i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
00441                                      i == 2 ? PMU_IRQ_DAC2_FIFO_AE  : \
00442                                      i == 3 ? PMU_IRQ_DAC3_FIFO_AE  : 0)
00443 
00444 #define MXC_DAC_GET_DAC(i)  (i == 0 ? MXC_DAC0 : \
00445                              i == 1 ? MXC_DAC1 : \
00446                              i == 2 ? MXC_DAC2 : \
00447                              i == 3 ? MXC_DAC3 : 0)
00448 
00449 #define MXC_DAC_GET_WIDTH(i)  (i == 0 ? MXC_DAC0_WIDTH : \
00450                                i == 1 ? MXC_DAC1_WIDTH : \
00451                                i == 2 ? MXC_DAC2_WIDTH : \
00452                                i == 3 ? MXC_DAC3_WIDTH : 0)
00453 
00454 
00455 /*******************************************************************************/
00456 /*                                                            Analog Front End */
00457 
00458 #define MXC_BASE_AFE                     ((uint32_t)0x4005401CUL)
00459 #define MXC_AFE                          ((mxc_afe_regs_t *)MXC_BASE_AFE)
00460 
00461 
00462 
00463 /*******************************************************************************/
00464 /*                                                                         ADC */
00465 
00466 #define MXC_CFG_ADC_FIFO_DEPTH           ((uint32_t)(32))
00467 
00468 #define MXC_BASE_ADC                     ((uint32_t)0x40054000UL)
00469 #define MXC_ADC                          ((mxc_adc_regs_t *)MXC_BASE_ADC)
00470 
00471 #define MXC_BASE_ADCCFG                  ((uint32_t)0x40054038UL)
00472 #define MXC_ADCCFG                       ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
00473 
00474 #define MXC_BASE_ADC_FIFO                ((uint32_t)0x40109000UL)
00475 
00476 
00477 
00478 /*******************************************************************************/
00479 /*                                                                         LCD */
00480 #define MXC_BASE_LCD                     ((uint32_t)0x40060000)
00481 #define MXC_LCD                          ((mxc_lcd_regs_t *)MXC_BASE_LCD)
00482 
00483 /*******************************************************************************/
00484 /*                  Peripheral Management Unit (PMU) - formerly DMA Controller */
00485 
00486 #define MXC_CFG_PMU_CHANNELS             (6)
00487 
00488 #define MXC_BASE_PMU0                    ((uint32_t)0x40070000UL)
00489 #define MXC_PMU0                         ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
00490 #define MXC_BASE_PMU1                    ((uint32_t)0x40070020UL)
00491 #define MXC_PMU1                         ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
00492 #define MXC_BASE_PMU2                    ((uint32_t)0x40070040UL)
00493 #define MXC_PMU2                         ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
00494 #define MXC_BASE_PMU3                    ((uint32_t)0x40070060UL)
00495 #define MXC_PMU3                         ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
00496 #define MXC_BASE_PMU4                    ((uint32_t)0x40070080UL)
00497 #define MXC_PMU4                         ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
00498 #define MXC_BASE_PMU5                    ((uint32_t)0x400700A0UL)
00499 #define MXC_PMU5                         ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
00500 
00501 #define MXC_BASE_PMU_BITBAND            ((uint32_t)0x42E00000UL)
00502 #define MXC_BASE_PMU_BITBAND_CHOFFSET   ((uint32_t)0x00000400UL)
00503 /*******************************************************************************/
00504 
00505 typedef enum {
00506     PMU_IRQ_DAC0_FIFO_AE,
00507     PMU_IRQ_DAC1_FIFO_AE,
00508     PMU_IRQ_DAC2_FIFO_AE,
00509     PMU_IRQ_DAC3_FIFO_AE,
00510     PMU_IRQ_DAC0_DONE,
00511     PMU_IRQ_DAC1_DONE,
00512     PMU_IRQ_DAC2_DONE,
00513     PMU_IRQ_DAC3_DONE,
00514     PMU_IRQ_ADC_FIFO_AF,
00515     PMU_IRQ_ADC_DONE,
00516     PMU_IRQ_I2C_MST0_DONE,
00517     PMU_IRQ_I2C_MST1_DONE,
00518     PMU_IRQ_SPI0_RSLTS_DONE,
00519     PMU_IRQ_SPI1_RSLTS_DONE,
00520     PMU_IRQ_SPI2_RSLTS_DONE,
00521     PMU_IRQ_MAA_DONE,
00522     PMU_IRQ_SPI0_TX_FIFO_AE,
00523     PMU_IRQ_SPI0_RSLTS_FIFO_AF,
00524     PMU_IRQ_SPI1_TX_FIFO_AE,
00525     PMU_IRQ_SPI1_RSLTS_FIFO_AF,
00526     PMU_IRQ_SPI2_TX_FIFO_AE,
00527     PMU_IRQ_SPI3_RSLTS_FIFO_AF,
00528     PMU_IRQ_I2C_MST0_TRANS_FIFO,
00529     PMU_IRQ_I2C_MST0_RSLT_FIFO,
00530     PMU_IRQ_I2C_MST1_TRANS_FIFO,
00531     PMU_IRQ_I2C_MST2_RSLT_FIFO,
00532     PMU_IRQ_I2C_SLV_TRANS_FIFO,
00533     PMU_IRQ_I2C_SLV_RSLT_FIFO,
00534     PMU_IRQ_UART0_TX_FIFO,
00535     PMU_IRQ_UART0_RX_FIFO,
00536     PMU_IRQ_UART1_TX_FIFO,
00537     PMU_IRQ_UART1_RX_FIFO,
00538     PMU_IRQ_SPI0_EXCP,
00539     PMU_IRQ_SPI1_EXCP,
00540     PMU_IRQ_SPI2_EXCP,
00541     PMU_IRQ_RSVD0,
00542     PMU_IRQ_I2C_MST0_EXCP,
00543     PMU_IRQ_I2C_MST1_EXCP,
00544     PMU_IRQ_I2C_SLV_EXCP,
00545     PMU_IRQ_RSVD1,
00546     PMU_IRQ_GPIO0,
00547     PMU_IRQ_GPIO1,
00548     PMU_IRQ_GPIO2,
00549     PMU_IRQ_GPIO3,
00550     PMU_IRQ_GPIO4,
00551     PMU_IRQ_GPIO5,
00552     PMU_IRQ_GPIO6,
00553     PMU_IRQ_GPIO7,
00554     PMU_IRQ_GPIO8,
00555     PMU_IRQ_AFE_COMP_NMI,
00556     PMU_IRQ_AES_ENGINE,
00557 } pmu_int_mask_t;
00558 
00559 /*******************************************************************************/
00560 /*                                                                         USB */
00561 
00562 #define MXC_BASE_USB                     ((uint32_t)0x4010C000UL)
00563 #define MXC_USB                          ((mxc_usb_regs_t *)MXC_BASE_USB)
00564 
00565 #define MXC_USB_MAX_PACKET               (64)
00566 #define MXC_USB_NUM_EP                   (8)
00567 
00568 
00569 /*******************************************************************************/
00570 /*                                                Instruction Cache Controller */
00571 
00572 #define MXC_BASE_ICC                     ((uint32_t)0x40080000UL)
00573 #define MXC_ICC                          ((mxc_icc_regs_t *)MXC_BASE_ICC)
00574 
00575 /*                                                              System Manager */
00576 
00577 #define MXC_BASE_SYSMAN                 ((uint32_t)0x40090000UL)
00578 
00579 /*******************************************************************************/
00580 /*                                                               Clock Manager */
00581 
00582 #define MXC_BASE_CLKMAN                  ((uint32_t)0x40090400UL)
00583 #define MXC_CLKMAN                       ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
00584 
00585 
00586 /*******************************************************************************/
00587 /*                                                               Power Manager */
00588 
00589 #define MXC_BASE_PWRMAN                  ((uint32_t)0x40090800UL)
00590 #define MXC_PWRMAN                       ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
00591 
00592 /*******************************************************************************/
00593 /*                                                                 I/O Manager */
00594 
00595 #define MXC_BASE_IOMAN                   ((uint32_t)0x40090C00UL)
00596 #define MXC_IOMAN                        ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
00597 
00598 
00599 /*******************************************************************************/
00600 /*                                                           RTC: Timer/Alarms */
00601 
00602 #define MXC_BASE_RTCTMR                 ((uint32_t)0x40090A00UL)
00603 #define MXC_RTCTMR                       ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
00604 
00605 #define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn :    \
00606                                i == 1 ? RTC1_IRQn :    \
00607                                i == 2 ? RTC2_IRQn :    \
00608                                i == 3 ? RTC3_IRQn : 0)
00609 
00610 #define MXC_BASE_RTCCFG                  ((uint32_t)0x40090A70UL)
00611 #define MXC_RTCCFG                       ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
00612 /*******************************************************************************/
00613 /*                                                        RTC: Power Sequencer */
00614 
00615 #define MXC_BASE_PWRSEQ                  ((uint32_t)0x40090A30UL)
00616 #define MXC_PWRSEQ                       ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
00617 
00618 /*******************************************************************************/
00619 
00620 /*                                                       Trim Shadow Registers */
00621 
00622 #define MXC_BASE_TRIM                    ((uint32_t)0x400E0000UL)
00623 #define MXC_TRIM                         ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
00624 
00625 
00626 /*******************************************************************************/
00627 /*                                          Flash Memory Controller / Security */
00628 
00629 #define MXC_BASE_FLC                     ((uint32_t)0x400F0000UL)
00630 #define MXC_FLC                          ((mxc_flc_regs_t *)MXC_BASE_FLC)
00631 #define MXC_BASE_FLC_BITBAND             ((uint32_t)0x43E00000UL)
00632 #define MXC_FLC_PAGE_SIZE_SHIFT          11
00633 #define MXC_FLC_PAGE_SIZE                (1 << MXC_FLC_PAGE_SIZE_SHIFT)
00634 #define MXC_FLC_PAGE_ERASE_MSK           ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
00635 
00636 
00637 /*******************************************************************************/
00638 
00639 #define BITBAND(reg, bit)        ((0xf0000000 & reg) + 0x2000000 + ((reg & 0x0fffffff) << 5) + (bit << 2))
00640 #define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0;
00641 #define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1;
00642 #define BITBAND_GetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit)
00643 
00644 /*******************************************************************************/
00645 #endif  /* _MAX32600_H_ */
00646