Sam Shi / Mbed 2 deprecated unytelogo_animation

growing leaf (6 frames) and reverse

Dependencies:   Adafruit_GFX_i2c BLE_API USBDevice mbed

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

flc_regs.h@32:114e947a916b, 2017-07-18 (annotated)

Committer:
SamShiSS
Date:
Tue Jul 18 16:39:46 2017 +0000
Revision:
32:114e947a916b
unyte logo animation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
SamShiSS 32:114e947a916b 1 /*******************************************************************************
SamShiSS 32:114e947a916b 2 * Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
SamShiSS 32:114e947a916b 3 *
SamShiSS 32:114e947a916b 4 * Permission is hereby granted, free of charge, to any person obtaining a
SamShiSS 32:114e947a916b 5 * copy of this software and associated documentation files (the "Software"),
SamShiSS 32:114e947a916b 6 * to deal in the Software without restriction, including without limitation
SamShiSS 32:114e947a916b 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
SamShiSS 32:114e947a916b 8 * and/or sell copies of the Software, and to permit persons to whom the
SamShiSS 32:114e947a916b 9 * Software is furnished to do so, subject to the following conditions:
SamShiSS 32:114e947a916b 10 *
SamShiSS 32:114e947a916b 11 * The above copyright notice and this permission notice shall be included
SamShiSS 32:114e947a916b 12 * in all copies or substantial portions of the Software.
SamShiSS 32:114e947a916b 13 *
SamShiSS 32:114e947a916b 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
SamShiSS 32:114e947a916b 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
SamShiSS 32:114e947a916b 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
SamShiSS 32:114e947a916b 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
SamShiSS 32:114e947a916b 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
SamShiSS 32:114e947a916b 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
SamShiSS 32:114e947a916b 20 * OTHER DEALINGS IN THE SOFTWARE.
SamShiSS 32:114e947a916b 21 *
SamShiSS 32:114e947a916b 22 * Except as contained in this notice, the name of Maxim Integrated
SamShiSS 32:114e947a916b 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
SamShiSS 32:114e947a916b 24 * Products, Inc. Branding Policy.
SamShiSS 32:114e947a916b 25 *
SamShiSS 32:114e947a916b 26 * The mere transfer of this software does not imply any licenses
SamShiSS 32:114e947a916b 27 * of trade secrets, proprietary technology, copyrights, patents,
SamShiSS 32:114e947a916b 28 * trademarks, maskwork rights, or any other form of intellectual
SamShiSS 32:114e947a916b 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
SamShiSS 32:114e947a916b 30 * ownership rights.
SamShiSS 32:114e947a916b 31 *******************************************************************************
SamShiSS 32:114e947a916b 32 */
SamShiSS 32:114e947a916b 33
SamShiSS 32:114e947a916b 34 /* $Revision: 3550 $ $Date: 2014-11-12 11:45:23 -0600 (Wed, 12 Nov 2014) $ */
SamShiSS 32:114e947a916b 35
SamShiSS 32:114e947a916b 36 #ifndef _MXC_FLC_REGS_H
SamShiSS 32:114e947a916b 37 #define _MXC_FLC_REGS_H
SamShiSS 32:114e947a916b 38
SamShiSS 32:114e947a916b 39 #ifdef __cplusplus
SamShiSS 32:114e947a916b 40 extern "C" {
SamShiSS 32:114e947a916b 41 #endif
SamShiSS 32:114e947a916b 42
SamShiSS 32:114e947a916b 43 #include <stdint.h>
SamShiSS 32:114e947a916b 44
SamShiSS 32:114e947a916b 45 /*
SamShiSS 32:114e947a916b 46 If types are not defined elsewhere (CMSIS) define them here
SamShiSS 32:114e947a916b 47 */
SamShiSS 32:114e947a916b 48 #ifndef __IO
SamShiSS 32:114e947a916b 49 #define __IO volatile
SamShiSS 32:114e947a916b 50 #endif
SamShiSS 32:114e947a916b 51 #ifndef __I
SamShiSS 32:114e947a916b 52 #define __I volatile const
SamShiSS 32:114e947a916b 53 #endif
SamShiSS 32:114e947a916b 54 #ifndef __O
SamShiSS 32:114e947a916b 55 #define __O volatile
SamShiSS 32:114e947a916b 56 #endif
SamShiSS 32:114e947a916b 57 #ifndef __R
SamShiSS 32:114e947a916b 58 #define __R volatile const
SamShiSS 32:114e947a916b 59 #endif
SamShiSS 32:114e947a916b 60
SamShiSS 32:114e947a916b 61
SamShiSS 32:114e947a916b 62 /*
SamShiSS 32:114e947a916b 63 Bitfield structs for registers in this module
SamShiSS 32:114e947a916b 64 */
SamShiSS 32:114e947a916b 65
SamShiSS 32:114e947a916b 66
SamShiSS 32:114e947a916b 67 typedef struct
SamShiSS 32:114e947a916b 68 {
SamShiSS 32:114e947a916b 69 uint32_t faddr : 18;
SamShiSS 32:114e947a916b 70 uint32_t : 14;
SamShiSS 32:114e947a916b 71 } mxc_flc_faddr_t;
SamShiSS 32:114e947a916b 72
SamShiSS 32:114e947a916b 73 typedef struct
SamShiSS 32:114e947a916b 74 {
SamShiSS 32:114e947a916b 75 uint32_t fckdiv : 5;
SamShiSS 32:114e947a916b 76 uint32_t : 27;
SamShiSS 32:114e947a916b 77 } mxc_flc_fckdiv_t;
SamShiSS 32:114e947a916b 78
SamShiSS 32:114e947a916b 79 typedef struct
SamShiSS 32:114e947a916b 80 {
SamShiSS 32:114e947a916b 81 uint32_t write : 1;
SamShiSS 32:114e947a916b 82 uint32_t mass_erase : 1;
SamShiSS 32:114e947a916b 83 uint32_t page_erase : 1;
SamShiSS 32:114e947a916b 84 uint32_t : 5;
SamShiSS 32:114e947a916b 85 uint32_t erase_code : 8;
SamShiSS 32:114e947a916b 86 uint32_t info_block_unlock : 1;
SamShiSS 32:114e947a916b 87 uint32_t write_enable : 1;
SamShiSS 32:114e947a916b 88 uint32_t : 6;
SamShiSS 32:114e947a916b 89 uint32_t pending : 1;
SamShiSS 32:114e947a916b 90 uint32_t info_block_valid : 1;
SamShiSS 32:114e947a916b 91 uint32_t : 1;
SamShiSS 32:114e947a916b 92 uint32_t auto_incre_mode : 1;
SamShiSS 32:114e947a916b 93 uint32_t flsh_unlock : 4;
SamShiSS 32:114e947a916b 94 } mxc_flc_ctrl_t;
SamShiSS 32:114e947a916b 95
SamShiSS 32:114e947a916b 96 typedef struct
SamShiSS 32:114e947a916b 97 {
SamShiSS 32:114e947a916b 98 uint32_t write_erase : 1;
SamShiSS 32:114e947a916b 99 uint32_t flsh_fail : 1;
SamShiSS 32:114e947a916b 100 uint32_t : 6;
SamShiSS 32:114e947a916b 101 uint32_t done : 1;
SamShiSS 32:114e947a916b 102 uint32_t failed : 1;
SamShiSS 32:114e947a916b 103 uint32_t : 22;
SamShiSS 32:114e947a916b 104 } mxc_flc_intr_t;
SamShiSS 32:114e947a916b 105
SamShiSS 32:114e947a916b 106 typedef struct
SamShiSS 32:114e947a916b 107 {
SamShiSS 32:114e947a916b 108 uint32_t delay_se_en : 1;
SamShiSS 32:114e947a916b 109 uint32_t : 7;
SamShiSS 32:114e947a916b 110 uint32_t fast_read_mode_en : 1;
SamShiSS 32:114e947a916b 111 uint32_t : 23;
SamShiSS 32:114e947a916b 112 } mxc_flc_perform_t;
SamShiSS 32:114e947a916b 113
SamShiSS 32:114e947a916b 114 typedef struct
SamShiSS 32:114e947a916b 115 {
SamShiSS 32:114e947a916b 116 uint32_t jtag_lock_window : 1;
SamShiSS 32:114e947a916b 117 uint32_t jtag_lock_static : 1;
SamShiSS 32:114e947a916b 118 uint32_t : 1;
SamShiSS 32:114e947a916b 119 uint32_t auto_lock : 1;
SamShiSS 32:114e947a916b 120 uint32_t : 25;
SamShiSS 32:114e947a916b 121 uint32_t trim_update_done : 1;
SamShiSS 32:114e947a916b 122 uint32_t info_block_valid : 1;
SamShiSS 32:114e947a916b 123 uint32_t : 1;
SamShiSS 32:114e947a916b 124 } mxc_flc_status_t;
SamShiSS 32:114e947a916b 125
SamShiSS 32:114e947a916b 126 typedef struct
SamShiSS 32:114e947a916b 127 {
SamShiSS 32:114e947a916b 128 uint32_t debug_disable : 1;
SamShiSS 32:114e947a916b 129 uint32_t : 7;
SamShiSS 32:114e947a916b 130 uint32_t mass_erase_lock : 1;
SamShiSS 32:114e947a916b 131 uint32_t : 22;
SamShiSS 32:114e947a916b 132 uint32_t security_lock : 1;
SamShiSS 32:114e947a916b 133 } mxc_flc_security_t;
SamShiSS 32:114e947a916b 134
SamShiSS 32:114e947a916b 135 typedef struct
SamShiSS 32:114e947a916b 136 {
SamShiSS 32:114e947a916b 137 uint32_t destruct_bypass_erase : 1;
SamShiSS 32:114e947a916b 138 uint32_t superwipe_erase : 1;
SamShiSS 32:114e947a916b 139 uint32_t destruct_bypass_complete : 1;
SamShiSS 32:114e947a916b 140 uint32_t superwipe_complete : 1;
SamShiSS 32:114e947a916b 141 uint32_t : 28;
SamShiSS 32:114e947a916b 142 } mxc_flc_bypass_t;
SamShiSS 32:114e947a916b 143
SamShiSS 32:114e947a916b 144 typedef struct
SamShiSS 32:114e947a916b 145 {
SamShiSS 32:114e947a916b 146 uint32_t flash_lve : 1;
SamShiSS 32:114e947a916b 147 uint32_t : 7;
SamShiSS 32:114e947a916b 148 uint32_t bypass_ahb_fail : 1;
SamShiSS 32:114e947a916b 149 uint32_t : 23;
SamShiSS 32:114e947a916b 150 } mxc_flc_ctrl2_t;
SamShiSS 32:114e947a916b 151
SamShiSS 32:114e947a916b 152 typedef struct
SamShiSS 32:114e947a916b 153 {
SamShiSS 32:114e947a916b 154 uint32_t sram_addr_wrapped : 1;
SamShiSS 32:114e947a916b 155 uint32_t invalid_flash_addr : 1;
SamShiSS 32:114e947a916b 156 uint32_t flash_read_locked : 1;
SamShiSS 32:114e947a916b 157 uint32_t trim_update_done : 1;
SamShiSS 32:114e947a916b 158 uint32_t : 28;
SamShiSS 32:114e947a916b 159 } mxc_flc_intfl1_t;
SamShiSS 32:114e947a916b 160
SamShiSS 32:114e947a916b 161 typedef struct
SamShiSS 32:114e947a916b 162 {
SamShiSS 32:114e947a916b 163 uint32_t sram_addr_wrapped : 1;
SamShiSS 32:114e947a916b 164 uint32_t invalid_flash_addr : 1;
SamShiSS 32:114e947a916b 165 uint32_t flash_read_locked : 1;
SamShiSS 32:114e947a916b 166 uint32_t trim_update_done : 1;
SamShiSS 32:114e947a916b 167 uint32_t : 28;
SamShiSS 32:114e947a916b 168 } mxc_flc_inten1_t;
SamShiSS 32:114e947a916b 169
SamShiSS 32:114e947a916b 170
SamShiSS 32:114e947a916b 171 /*
SamShiSS 32:114e947a916b 172 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
SamShiSS 32:114e947a916b 173 register access along with union access to bit/bitfield struct (where defined).
SamShiSS 32:114e947a916b 174 */
SamShiSS 32:114e947a916b 175
SamShiSS 32:114e947a916b 176 /* Offset Register Description
SamShiSS 32:114e947a916b 177 ====== ======================================================= */
SamShiSS 32:114e947a916b 178 typedef struct {
SamShiSS 32:114e947a916b 179 union {
SamShiSS 32:114e947a916b 180 __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
SamShiSS 32:114e947a916b 181 __IO mxc_flc_faddr_t faddr_f;
SamShiSS 32:114e947a916b 182 };
SamShiSS 32:114e947a916b 183 union {
SamShiSS 32:114e947a916b 184 __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */
SamShiSS 32:114e947a916b 185 __IO mxc_flc_fckdiv_t fckdiv_f;
SamShiSS 32:114e947a916b 186 };
SamShiSS 32:114e947a916b 187 union {
SamShiSS 32:114e947a916b 188 __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
SamShiSS 32:114e947a916b 189 __IO mxc_flc_ctrl_t ctrl_f;
SamShiSS 32:114e947a916b 190 };
SamShiSS 32:114e947a916b 191 __R uint32_t rsv000C[6]; /* 0x000C */
SamShiSS 32:114e947a916b 192 union {
SamShiSS 32:114e947a916b 193 __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
SamShiSS 32:114e947a916b 194 __IO mxc_flc_intr_t intr_f;
SamShiSS 32:114e947a916b 195 };
SamShiSS 32:114e947a916b 196 __R uint32_t rsv0028[2]; /* 0x0028 */
SamShiSS 32:114e947a916b 197
SamShiSS 32:114e947a916b 198 __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
SamShiSS 32:114e947a916b 199
SamShiSS 32:114e947a916b 200 __R uint32_t rsv0034[7]; /* 0x0034 */
SamShiSS 32:114e947a916b 201 union {
SamShiSS 32:114e947a916b 202 __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
SamShiSS 32:114e947a916b 203 __IO mxc_flc_perform_t perform_f;
SamShiSS 32:114e947a916b 204 };
SamShiSS 32:114e947a916b 205 __R uint32_t rsv0054[11]; /* 0x0054 */
SamShiSS 32:114e947a916b 206 union {
SamShiSS 32:114e947a916b 207 __IO uint32_t status; /* 0x0080 Security Status Flags */
SamShiSS 32:114e947a916b 208 __IO mxc_flc_status_t status_f;
SamShiSS 32:114e947a916b 209 };
SamShiSS 32:114e947a916b 210 __R uint32_t rsv0084; /* 0x0084 */
SamShiSS 32:114e947a916b 211 union {
SamShiSS 32:114e947a916b 212 __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
SamShiSS 32:114e947a916b 213 __IO mxc_flc_security_t security_f;
SamShiSS 32:114e947a916b 214 };
SamShiSS 32:114e947a916b 215 __R uint32_t rsv008C[4]; /* 0x008C */
SamShiSS 32:114e947a916b 216 union {
SamShiSS 32:114e947a916b 217 __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
SamShiSS 32:114e947a916b 218 __IO mxc_flc_bypass_t bypass_f;
SamShiSS 32:114e947a916b 219 };
SamShiSS 32:114e947a916b 220
SamShiSS 32:114e947a916b 221 __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
SamShiSS 32:114e947a916b 222 __R uint32_t rsv0104[15]; /* 0x0104 */
SamShiSS 32:114e947a916b 223 union {
SamShiSS 32:114e947a916b 224 __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
SamShiSS 32:114e947a916b 225 __IO mxc_flc_ctrl2_t ctrl2_f;
SamShiSS 32:114e947a916b 226 };
SamShiSS 32:114e947a916b 227 union {
SamShiSS 32:114e947a916b 228 __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
SamShiSS 32:114e947a916b 229 __IO mxc_flc_intfl1_t intfl1_f;
SamShiSS 32:114e947a916b 230 };
SamShiSS 32:114e947a916b 231 union {
SamShiSS 32:114e947a916b 232 __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
SamShiSS 32:114e947a916b 233 __IO mxc_flc_inten1_t inten1_f;
SamShiSS 32:114e947a916b 234 };
SamShiSS 32:114e947a916b 235 __R uint32_t rsv014C; /* 0x014C */
SamShiSS 32:114e947a916b 236 __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */
SamShiSS 32:114e947a916b 237 __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */
SamShiSS 32:114e947a916b 238 __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */
SamShiSS 32:114e947a916b 239 __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */
SamShiSS 32:114e947a916b 240 __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */
SamShiSS 32:114e947a916b 241 __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */
SamShiSS 32:114e947a916b 242 __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */
SamShiSS 32:114e947a916b 243 __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */
SamShiSS 32:114e947a916b 244 } mxc_flc_regs_t;
SamShiSS 32:114e947a916b 245
SamShiSS 32:114e947a916b 246
SamShiSS 32:114e947a916b 247 /*
SamShiSS 32:114e947a916b 248 Register offsets for module FLC.
SamShiSS 32:114e947a916b 249 */
SamShiSS 32:114e947a916b 250 #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
SamShiSS 32:114e947a916b 251 #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
SamShiSS 32:114e947a916b 252 #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
SamShiSS 32:114e947a916b 253 #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
SamShiSS 32:114e947a916b 254 #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
SamShiSS 32:114e947a916b 255 #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
SamShiSS 32:114e947a916b 256 #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
SamShiSS 32:114e947a916b 257 #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
SamShiSS 32:114e947a916b 258 #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
SamShiSS 32:114e947a916b 259 #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
SamShiSS 32:114e947a916b 260 #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
SamShiSS 32:114e947a916b 261 #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
SamShiSS 32:114e947a916b 262 #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
SamShiSS 32:114e947a916b 263 #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL)
SamShiSS 32:114e947a916b 264 #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL)
SamShiSS 32:114e947a916b 265 #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL)
SamShiSS 32:114e947a916b 266 #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL)
SamShiSS 32:114e947a916b 267 #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL)
SamShiSS 32:114e947a916b 268 #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL)
SamShiSS 32:114e947a916b 269 #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL)
SamShiSS 32:114e947a916b 270 #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL)
SamShiSS 32:114e947a916b 271
SamShiSS 32:114e947a916b 272 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
SamShiSS 32:114e947a916b 273 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
SamShiSS 32:114e947a916b 274
SamShiSS 32:114e947a916b 275 #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
SamShiSS 32:114e947a916b 276
SamShiSS 32:114e947a916b 277 #ifdef __cplusplus
SamShiSS 32:114e947a916b 278 }
SamShiSS 32:114e947a916b 279 #endif
SamShiSS 32:114e947a916b 280
SamShiSS 32:114e947a916b 281 #endif /* _MXC_FLC_REGS_H_ */
SamShiSS 32:114e947a916b 282