flc_regs.h

00001 /*******************************************************************************
00002 * Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
00003 *
00004 * Permission is hereby granted, free of charge, to any person obtaining a
00005 * copy of this software and associated documentation files (the "Software"),
00006 * to deal in the Software without restriction, including without limitation
00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00008 * and/or sell copies of the Software, and to permit persons to whom the
00009 * Software is furnished to do so, subject to the following conditions:
00010 *
00011 * The above copyright notice and this permission notice shall be included
00012 * in all copies or substantial portions of the Software.
00013 *
00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020 * OTHER DEALINGS IN THE SOFTWARE.
00021 *
00022 * Except as contained in this notice, the name of Maxim Integrated 
00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 
00024 * Products, Inc. Branding Policy.
00025 *
00026 * The mere transfer of this software does not imply any licenses
00027 * of trade secrets, proprietary technology, copyrights, patents,
00028 * trademarks, maskwork rights, or any other form of intellectual
00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 
00030 * ownership rights.
00031 *******************************************************************************
00032 */
00033 
00034 /* $Revision: 3550 $ $Date: 2014-11-12 11:45:23 -0600 (Wed, 12 Nov 2014) $ */
00035 
00036 #ifndef _MXC_FLC_REGS_H
00037 #define _MXC_FLC_REGS_H
00038 
00039 #ifdef __cplusplus
00040 extern "C" {
00041 #endif
00042 
00043 #include <stdint.h>
00044 
00045 /*
00046     If types are not defined elsewhere (CMSIS) define them here
00047 */
00048 #ifndef __IO
00049 #define __IO volatile
00050 #endif
00051 #ifndef __I
00052 #define __I  volatile const
00053 #endif
00054 #ifndef __O
00055 #define __O  volatile
00056 #endif
00057 #ifndef __R
00058 #define __R  volatile const
00059 #endif
00060 
00061 
00062 /*
00063     Bitfield structs for registers in this module
00064 */
00065 
00066 
00067 typedef struct
00068 {
00069     uint32_t faddr                     : 18;
00070     uint32_t                           : 14;
00071 } mxc_flc_faddr_t;
00072 
00073 typedef struct
00074 {
00075     uint32_t fckdiv                    : 5;
00076     uint32_t                           : 27;
00077 } mxc_flc_fckdiv_t;
00078 
00079 typedef struct
00080 {
00081     uint32_t write                     : 1;
00082     uint32_t mass_erase                : 1;
00083     uint32_t page_erase                : 1;
00084     uint32_t                           : 5;
00085     uint32_t erase_code                : 8;
00086     uint32_t info_block_unlock         : 1;
00087     uint32_t write_enable              : 1;
00088     uint32_t                           : 6;
00089     uint32_t pending                   : 1;
00090     uint32_t info_block_valid          : 1;
00091     uint32_t                           : 1;
00092     uint32_t auto_incre_mode           : 1;
00093     uint32_t flsh_unlock               : 4;
00094 } mxc_flc_ctrl_t;
00095 
00096 typedef struct
00097 {
00098     uint32_t write_erase               : 1;
00099     uint32_t flsh_fail                 : 1;
00100     uint32_t                           : 6;
00101     uint32_t done                      : 1;
00102     uint32_t failed                    : 1;
00103     uint32_t                           : 22;
00104 } mxc_flc_intr_t;
00105 
00106 typedef struct
00107 {
00108     uint32_t delay_se_en               : 1;
00109     uint32_t                           : 7;
00110     uint32_t fast_read_mode_en         : 1;
00111     uint32_t                           : 23;
00112 } mxc_flc_perform_t;
00113 
00114 typedef struct
00115 {
00116     uint32_t jtag_lock_window          : 1;
00117     uint32_t jtag_lock_static          : 1;
00118     uint32_t                           : 1;
00119     uint32_t auto_lock                 : 1;
00120     uint32_t                           : 25;
00121     uint32_t trim_update_done          : 1;
00122     uint32_t info_block_valid          : 1;
00123     uint32_t                           : 1;
00124 } mxc_flc_status_t;
00125 
00126 typedef struct
00127 {
00128     uint32_t debug_disable             : 1;
00129     uint32_t                           : 7;
00130     uint32_t mass_erase_lock           : 1;
00131     uint32_t                           : 22;
00132     uint32_t security_lock             : 1;
00133 } mxc_flc_security_t;
00134 
00135 typedef struct
00136 {
00137     uint32_t destruct_bypass_erase     : 1;
00138     uint32_t superwipe_erase           : 1;
00139     uint32_t destruct_bypass_complete  : 1;
00140     uint32_t superwipe_complete        : 1;
00141     uint32_t                           : 28;
00142 } mxc_flc_bypass_t;
00143 
00144 typedef struct
00145 {
00146     uint32_t flash_lve                 : 1;
00147     uint32_t                           : 7;
00148     uint32_t bypass_ahb_fail           : 1;
00149     uint32_t                           : 23;
00150 } mxc_flc_ctrl2_t;
00151 
00152 typedef struct
00153 {
00154     uint32_t sram_addr_wrapped         : 1;
00155     uint32_t invalid_flash_addr        : 1;
00156     uint32_t flash_read_locked         : 1;
00157     uint32_t trim_update_done          : 1;
00158     uint32_t                           : 28;
00159 } mxc_flc_intfl1_t;
00160 
00161 typedef struct
00162 {
00163     uint32_t sram_addr_wrapped         : 1;
00164     uint32_t invalid_flash_addr        : 1;
00165     uint32_t flash_read_locked         : 1;
00166     uint32_t trim_update_done          : 1;
00167     uint32_t                           : 28;
00168 } mxc_flc_inten1_t;
00169 
00170 
00171 /*
00172    Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
00173    register access along with union access to bit/bitfield struct (where defined).
00174 */
00175 
00176 /*                                              Offset   Register Description
00177                                                 ======   ======================================================= */
00178 typedef struct {
00179     union {
00180         __IO uint32_t faddr;                /*  0x0000   Flash Operation Address                                 */
00181         __IO mxc_flc_faddr_t faddr_f;
00182     };
00183     union {
00184         __IO uint32_t fckdiv;               /*  0x0004   Flash Clock Rate Divisor                                */
00185         __IO mxc_flc_fckdiv_t fckdiv_f;
00186     };
00187     union {
00188         __IO uint32_t ctrl;                 /*  0x0008   Flash Control Register                                  */
00189         __IO mxc_flc_ctrl_t ctrl_f;
00190     };
00191     __R uint32_t rsv000C[6];                /*  0x000C                                                           */
00192     union {
00193         __IO uint32_t intr;                 /*  0x0024   Flash Controller Interrupt Flags and Enable/Disable 0   */
00194         __IO mxc_flc_intr_t intr_f;
00195     };
00196     __R uint32_t rsv0028[2];                /*  0x0028                                                           */
00197 
00198     __IO uint32_t fdata;                    /*  0x0030   Flash Operation Data Register                           */
00199 
00200     __R uint32_t rsv0034[7];                /*  0x0034                                                           */
00201     union {
00202         __IO uint32_t perform;              /*  0x0050   Flash Performance Settings                              */
00203         __IO mxc_flc_perform_t perform_f;
00204     };
00205     __R uint32_t rsv0054[11];               /*  0x0054                                                           */
00206     union {
00207         __IO uint32_t status;               /*  0x0080   Security Status Flags                                   */
00208         __IO mxc_flc_status_t status_f;
00209     };
00210     __R uint32_t rsv0084;                   /*  0x0084                                                           */
00211     union {
00212         __IO uint32_t security;             /*  0x0088   Flash Controller Security Settings                      */
00213         __IO mxc_flc_security_t security_f;
00214     };
00215     __R uint32_t rsv008C[4];                /*  0x008C                                                           */
00216     union {
00217         __IO uint32_t bypass;               /*  0x009C   Status Flags for DSB Operations                         */
00218         __IO mxc_flc_bypass_t bypass_f;
00219     };
00220 
00221     __IO uint32_t user_option;              /*  0x0100   Used to set DSB Access code and Auto-Lock in info block */
00222     __R uint32_t rsv0104[15];               /*  0x0104                                                           */
00223     union {
00224         __IO uint32_t ctrl2;                /*  0x0140   Flash Control Register 2                                */
00225         __IO mxc_flc_ctrl2_t ctrl2_f;
00226     };
00227     union {
00228         __IO uint32_t intfl1;               /*  0x0144   Interrupt Flags Register 1                              */
00229         __IO mxc_flc_intfl1_t intfl1_f;
00230     };
00231     union {
00232         __IO uint32_t inten1;               /*  0x0148   Interrupt Enable/Disable Register 1                     */
00233         __IO mxc_flc_inten1_t inten1_f;
00234     };
00235     __R uint32_t rsv014C;                   /*  0x014C                                                           */
00236     __IO uint32_t disable_xr0;              /*  0x0150   Disable Flash Page Exec/Read Register 0                 */
00237     __IO uint32_t disable_xr1;              /*  0x0154   Disable Flash Page Exec/Read Register 1                 */
00238     __IO uint32_t disable_xr2;              /*  0x0158   Disable Flash Page Exec/Read Register 2                 */
00239     __IO uint32_t disable_xr3;              /*  0x015C   Disable Flash Page Exec/Read Register 3                 */
00240     __IO uint32_t disable_we0;              /*  0x0160   Disable Flash Page Write/Erase Register 0               */
00241     __IO uint32_t disable_we1;              /*  0x0164   Disable Flash Page Write/Erase Register 1               */
00242     __IO uint32_t disable_we2;              /*  0x0168   Disable Flash Page Write/Erase Register 2               */
00243     __IO uint32_t disable_we3;              /*  0x016C   Disable Flash Page Write/Erase Register 3               */
00244 } mxc_flc_regs_t;
00245 
00246 
00247 /*
00248    Register offsets for module FLC.
00249 */
00250 #define MXC_R_FLC_OFFS_FADDR                      ((uint32_t)0x00000000UL)
00251 #define MXC_R_FLC_OFFS_FCKDIV                     ((uint32_t)0x00000004UL)
00252 #define MXC_R_FLC_OFFS_CTRL                       ((uint32_t)0x00000008UL)
00253 #define MXC_R_FLC_OFFS_INTR                       ((uint32_t)0x00000024UL)
00254 #define MXC_R_FLC_OFFS_FDATA                      ((uint32_t)0x00000030UL)
00255 #define MXC_R_FLC_OFFS_PERFORM                    ((uint32_t)0x00000050UL)
00256 #define MXC_R_FLC_OFFS_STATUS                     ((uint32_t)0x00000080UL)
00257 #define MXC_R_FLC_OFFS_SECURITY                   ((uint32_t)0x00000088UL)
00258 #define MXC_R_FLC_OFFS_BYPASS                     ((uint32_t)0x0000009CUL)
00259 #define MXC_R_FLC_OFFS_USER_OPTION                ((uint32_t)0x00000100UL)
00260 #define MXC_R_FLC_OFFS_CTRL2                      ((uint32_t)0x00000140UL)
00261 #define MXC_R_FLC_OFFS_INTFL1                     ((uint32_t)0x00000144UL)
00262 #define MXC_R_FLC_OFFS_INTEN1                     ((uint32_t)0x00000148UL)
00263 #define MXC_R_FLC_OFFS_DISABLE_XR0                ((uint32_t)0x00000150UL)
00264 #define MXC_R_FLC_OFFS_DISABLE_XR1                ((uint32_t)0x00000154UL)
00265 #define MXC_R_FLC_OFFS_DISABLE_XR2                ((uint32_t)0x00000158UL)
00266 #define MXC_R_FLC_OFFS_DISABLE_XR3                ((uint32_t)0x0000015CUL)
00267 #define MXC_R_FLC_OFFS_DISABLE_WE0                ((uint32_t)0x00000160UL)
00268 #define MXC_R_FLC_OFFS_DISABLE_WE1                ((uint32_t)0x00000164UL)
00269 #define MXC_R_FLC_OFFS_DISABLE_WE2                ((uint32_t)0x00000168UL)
00270 #define MXC_R_FLC_OFFS_DISABLE_WE3                ((uint32_t)0x0000016CUL)
00271 
00272 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE   ((uint8_t)0x55)
00273 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE   ((uint8_t)0xAA)
00274 
00275 #define MXC_V_FLC_FLSH_UNLOCK_KEY         ((uint8_t)0x2)
00276 
00277 #ifdef __cplusplus
00278 }
00279 #endif
00280 
00281 #endif   /* _MXC_FLC_REGS_H_ */
00282