timer_11xx.h

00001 /*
00002  * @brief LPC11xx 16/32-bit Timer/PWM control functions
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2012
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 #ifndef __TIMER_11XX_H_
00033 #define __TIMER_11XX_H_
00034 
00035 #ifdef __cplusplus
00036 extern "C" {
00037 #endif
00038 
00039 /** @defgroup TIMER_11XX CHIP: LPC11xx 16/32-bit Timer driver
00040  * @ingroup CHIP_11XX_Drivers
00041  * @{
00042  */
00043 
00044 /**
00045  * @brief 32-bit Standard timer register block structure
00046  */
00047 typedef struct {                    /*!< TIMERn Structure       */
00048     __IO uint32_t IR ;               /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
00049     __IO uint32_t TCR ;              /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
00050     __IO uint32_t TC ;               /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
00051     __IO uint32_t PR ;               /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
00052     __IO uint32_t PC ;               /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
00053     __IO uint32_t MCR ;              /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
00054     __IO uint32_t MR[4];            /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
00055     __IO uint32_t CCR ;              /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
00056     __IO uint32_t CR[4];            /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
00057     __IO uint32_t EMR ;              /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
00058     __I  uint32_t RESERVED0[12];
00059     __IO uint32_t CTCR ;             /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
00060     __IO uint32_t PWMC;
00061 } LPC_TIMER_T;
00062 
00063 /** Macro to clear interrupt pending */
00064 #define TIMER_IR_CLR(n)         _BIT(n)
00065 
00066 /** Macro for getting a timer match interrupt bit */
00067 #define TIMER_MATCH_INT(n)      (_BIT((n) & 0x0F))
00068 /** Macro for getting a capture event interrupt bit */
00069 #define TIMER_CAP_INT(n)        (_BIT((((n) & 0x0F) + 4)))
00070 
00071 /** Timer/counter enable bit */
00072 #define TIMER_ENABLE            ((uint32_t) (1 << 0))
00073 /** Timer/counter reset bit */
00074 #define TIMER_RESET             ((uint32_t) (1 << 1))
00075 
00076 /** Bit location for interrupt on MRx match, n = 0 to 3 */
00077 #define TIMER_INT_ON_MATCH(n)   (_BIT(((n) * 3)))
00078 /** Bit location for reset on MRx match, n = 0 to 3 */
00079 #define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
00080 /** Bit location for stop on MRx match, n = 0 to 3 */
00081 #define TIMER_STOP_ON_MATCH(n)  (_BIT((((n) * 3) + 2)))
00082 
00083 /** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
00084 #define TIMER_CAP_RISING(n)     (_BIT(((n) * 3)))
00085 /** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
00086 #define TIMER_CAP_FALLING(n)    (_BIT((((n) * 3) + 1)))
00087 /** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
00088 #define TIMER_INT_ON_CAP(n)     (_BIT((((n) * 3) + 2)))
00089 
00090 /**
00091  * @brief   Initialize a timer
00092  * @param   pTMR    : Pointer to timer IP register address
00093  * @return  Nothing
00094  */
00095 void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
00096 
00097 /**
00098  * @brief   Shutdown a timer
00099  * @param   pTMR    : Pointer to timer IP register address
00100  * @return  Nothing
00101  */
00102 void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
00103 
00104 /**
00105  * @brief   Determine if a match interrupt is pending
00106  * @param   pTMR        : Pointer to timer IP register address
00107  * @param   matchnum    : Match interrupt number to check
00108  * @return  false if the interrupt is not pending, otherwise true
00109  * @note    Determine if the match interrupt for the passed timer and match
00110  * counter is pending.
00111  */
00112 STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
00113 {
00114     return (bool) ((pTMR->IR  & TIMER_MATCH_INT(matchnum)) != 0);
00115 }
00116 
00117 /**
00118  * @brief   Determine if a capture interrupt is pending
00119  * @param   pTMR    : Pointer to timer IP register address
00120  * @param   capnum  : Capture interrupt number to check
00121  * @return  false if the interrupt is not pending, otherwise true
00122  * @note    Determine if the capture interrupt for the passed capture pin is
00123  * pending.
00124  */
00125 STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
00126 {
00127     return (bool) ((pTMR->IR  & TIMER_CAP_INT(capnum)) != 0);
00128 }
00129 
00130 /**
00131  * @brief   Clears a (pending) match interrupt
00132  * @param   pTMR        : Pointer to timer IP register address
00133  * @param   matchnum    : Match interrupt number to clear
00134  * @return  Nothing
00135  * @note    Clears a pending timer match interrupt.
00136  */
00137 STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
00138 {
00139     pTMR->IR  = TIMER_IR_CLR(matchnum);
00140 }
00141 
00142 /**
00143  * @brief   Clears a (pending) capture interrupt
00144  * @param   pTMR    : Pointer to timer IP register address
00145  * @param   capnum  : Capture interrupt number to clear
00146  * @return  Nothing
00147  * @note    Clears a pending timer capture interrupt.
00148  */
00149 STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
00150 {
00151     pTMR->IR  = (0x10 << capnum);
00152 }
00153 
00154 /**
00155  * @brief   Enables the timer (starts count)
00156  * @param   pTMR    : Pointer to timer IP register address
00157  * @return  Nothing
00158  * @note    Enables the timer to start counting.
00159  */
00160 STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
00161 {
00162     pTMR->TCR  |= TIMER_ENABLE;
00163 }
00164 
00165 /**
00166  * @brief   Disables the timer (stops count)
00167  * @param   pTMR    : Pointer to timer IP register address
00168  * @return  Nothing
00169  * @note    Disables the timer to stop counting.
00170  */
00171 STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
00172 {
00173     pTMR->TCR  &= ~TIMER_ENABLE;
00174 }
00175 
00176 /**
00177  * @brief   Returns the current timer count
00178  * @param   pTMR    : Pointer to timer IP register address
00179  * @return  Current timer terminal count value
00180  * @note    Returns the current timer terminal count.
00181  */
00182 STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
00183 {
00184     return pTMR->TC ;
00185 }
00186 
00187 /**
00188  * @brief   Returns the current prescale count
00189  * @param   pTMR    : Pointer to timer IP register address
00190  * @return  Current timer prescale count value
00191  * @note    Returns the current prescale count.
00192  */
00193 STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
00194 {
00195     return pTMR->PC ;
00196 }
00197 
00198 /**
00199  * @brief   Sets the prescaler value
00200  * @param   pTMR        : Pointer to timer IP register address
00201  * @param   prescale    : Prescale value to set the prescale register to
00202  * @return  Nothing
00203  * @note    Sets the prescale count value.
00204  */
00205 STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
00206 {
00207     pTMR->PR  = prescale;
00208 }
00209 
00210 /**
00211  * @brief   Sets a timer match value
00212  * @param   pTMR        : Pointer to timer IP register address
00213  * @param   matchnum    : Match timer to set match count for
00214  * @param   matchval    : Match value for the selected match count
00215  * @return  Nothing
00216  * @note    Sets one of the timer match values.
00217  */
00218 STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
00219 {
00220     pTMR->MR [matchnum] = matchval;
00221 }
00222 
00223 /**
00224  * @brief   Reads a capture register
00225  * @param   pTMR    : Pointer to timer IP register address
00226  * @param   capnum  : Capture register to read
00227  * @return  The selected capture register value
00228  * @note    Returns the selected capture register value.
00229  */
00230 STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
00231 {
00232     return pTMR->CR [capnum];
00233 }
00234 
00235 /**
00236  * @brief   Resets the timer terminal and prescale counts to 0
00237  * @param   pTMR    : Pointer to timer IP register address
00238  * @return  Nothing
00239  */
00240 void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
00241 
00242 /**
00243  * @brief   Enables a match interrupt that fires when the terminal count
00244  *          matches the match counter value.
00245  * @param   pTMR        : Pointer to timer IP register address
00246  * @param   matchnum    : Match timer, 0 to 3
00247  * @return  Nothing
00248  */
00249 STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
00250 {
00251     pTMR->MCR  |= TIMER_INT_ON_MATCH(matchnum);
00252 }
00253 
00254 /**
00255  * @brief   Disables a match interrupt for a match counter.
00256  * @param   pTMR        : Pointer to timer IP register address
00257  * @param   matchnum    : Match timer, 0 to 3
00258  * @return  Nothing
00259  */
00260 STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
00261 {
00262     pTMR->MCR  &= ~TIMER_INT_ON_MATCH(matchnum);
00263 }
00264 
00265 /**
00266  * @brief   For the specific match counter, enables reset of the terminal count register when a match occurs
00267  * @param   pTMR        : Pointer to timer IP register address
00268  * @param   matchnum    : Match timer, 0 to 3
00269  * @return  Nothing
00270  */
00271 STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
00272 {
00273     pTMR->MCR  |= TIMER_RESET_ON_MATCH(matchnum);
00274 }
00275 
00276 /**
00277  * @brief   For the specific match counter, disables reset of the terminal count register when a match occurs
00278  * @param   pTMR        : Pointer to timer IP register address
00279  * @param   matchnum    : Match timer, 0 to 3
00280  * @return  Nothing
00281  */
00282 STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
00283 {
00284     pTMR->MCR  &= ~TIMER_RESET_ON_MATCH(matchnum);
00285 }
00286 
00287 /**
00288  * @brief   Enable a match timer to stop the terminal count when a
00289  *          match count equals the terminal count.
00290  * @param   pTMR        : Pointer to timer IP register address
00291  * @param   matchnum    : Match timer, 0 to 3
00292  * @return  Nothing
00293  */
00294 STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
00295 {
00296     pTMR->MCR  |= TIMER_STOP_ON_MATCH(matchnum);
00297 }
00298 
00299 /**
00300  * @brief   Disable stop on match for a match timer. Disables a match timer
00301  *          to stop the terminal count when a match count equals the terminal count.
00302  * @param   pTMR        : Pointer to timer IP register address
00303  * @param   matchnum    : Match timer, 0 to 3
00304  * @return  Nothing
00305  */
00306 STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
00307 {
00308     pTMR->MCR  &= ~TIMER_STOP_ON_MATCH(matchnum);
00309 }
00310 
00311 /**
00312  * @brief   Enables capture on on rising edge of selected CAP signal for the
00313  *          selected capture register, enables the selected CAPn.capnum signal to load
00314  *          the capture register with the terminal coount on a rising edge.
00315  * @param   pTMR    : Pointer to timer IP register address
00316  * @param   capnum  : Capture signal/register to use
00317  * @return  Nothing
00318  */
00319 STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
00320 {
00321     pTMR->CCR  |= TIMER_CAP_RISING(capnum);
00322 }
00323 
00324 /**
00325  * @brief   Disables capture on on rising edge of selected CAP signal. For the
00326  *          selected capture register, disables the selected CAPn.capnum signal to load
00327  *          the capture register with the terminal coount on a rising edge.
00328  * @param   pTMR    : Pointer to timer IP register address
00329  * @param   capnum  : Capture signal/register to use
00330  * @return  Nothing
00331  */
00332 STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
00333 {
00334     pTMR->CCR  &= ~TIMER_CAP_RISING(capnum);
00335 }
00336 
00337 /**
00338  * @brief   Enables capture on on falling edge of selected CAP signal. For the
00339  *          selected capture register, enables the selected CAPn.capnum signal to load
00340  *          the capture register with the terminal coount on a falling edge.
00341  * @param   pTMR    : Pointer to timer IP register address
00342  * @param   capnum  : Capture signal/register to use
00343  * @return  Nothing
00344  */
00345 STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
00346 {
00347     pTMR->CCR  |= TIMER_CAP_FALLING(capnum);
00348 }
00349 
00350 /**
00351  * @brief   Disables capture on on falling edge of selected CAP signal. For the
00352  *          selected capture register, disables the selected CAPn.capnum signal to load
00353  *          the capture register with the terminal coount on a falling edge.
00354  * @param   pTMR    : Pointer to timer IP register address
00355  * @param   capnum  : Capture signal/register to use
00356  * @return  Nothing
00357  */
00358 STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
00359 {
00360     pTMR->CCR  &= ~TIMER_CAP_FALLING(capnum);
00361 }
00362 
00363 /**
00364  * @brief   Enables interrupt on capture of selected CAP signal. For the
00365  *          selected capture register, an interrupt will be generated when the enabled
00366  *          rising or falling edge on CAPn.capnum is detected.
00367  * @param   pTMR    : Pointer to timer IP register address
00368  * @param   capnum  : Capture signal/register to use
00369  * @return  Nothing
00370  */
00371 STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
00372 {
00373     pTMR->CCR  |= TIMER_INT_ON_CAP(capnum);
00374 }
00375 
00376 /**
00377  * @brief   Disables interrupt on capture of selected CAP signal
00378  * @param   pTMR    : Pointer to timer IP register address
00379  * @param   capnum  : Capture signal/register to use
00380  * @return  Nothing
00381  */
00382 STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
00383 {
00384     pTMR->CCR  &= ~TIMER_INT_ON_CAP(capnum);
00385 }
00386 
00387 /**
00388  * @brief Standard timer initial match pin state and change state
00389  */
00390 typedef enum IP_TIMER_PIN_MATCH_STATE {
00391     TIMER_EXTMATCH_DO_NOTHING  = 0,  /*!< Timer match state does nothing on match pin */
00392     TIMER_EXTMATCH_CLEAR       = 1,  /*!< Timer match state sets match pin low */
00393     TIMER_EXTMATCH_SET         = 2,  /*!< Timer match state sets match pin high */
00394     TIMER_EXTMATCH_TOGGLE      = 3   /*!< Timer match state toggles match pin */
00395 } TIMER_PIN_MATCH_STATE_T;
00396 
00397 /**
00398  * @brief   Sets external match control (MATn.matchnum) pin control. For the pin
00399  *          selected with matchnum, sets the function of the pin that occurs on
00400  *          a terminal count match for the match count.
00401  * @param   pTMR            : Pointer to timer IP register address
00402  * @param   initial_state   : Initial state of the pin, high(1) or low(0)
00403  * @param   matchState      : Selects the match state for the pin
00404  * @param   matchnum        : MATn.matchnum signal to use
00405  * @return  Nothing
00406  * @note    For the pin selected with matchnum, sets the function of the pin that occurs on
00407  * a terminal count match for the match count.
00408  */
00409 void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
00410                                    TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
00411 
00412 /**
00413  * @brief Standard timer clock and edge for count source
00414  */
00415 typedef enum IP_TIMER_CAP_SRC_STATE {
00416     TIMER_CAPSRC_RISING_PCLK   = 0,  /*!< Timer ticks on PCLK rising edge */
00417     TIMER_CAPSRC_RISING_CAPN   = 1,  /*!< Timer ticks on CAPn.x rising edge */
00418     TIMER_CAPSRC_FALLING_CAPN  = 2,  /*!< Timer ticks on CAPn.x falling edge */
00419     TIMER_CAPSRC_BOTH_CAPN     = 3   /*!< Timer ticks on CAPn.x both edges */
00420 } TIMER_CAP_SRC_STATE_T;
00421 
00422 /**
00423  * @brief   Sets timer count source and edge with the selected passed from CapSrc.
00424  *          If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
00425  * @param   pTMR    : Pointer to timer IP register address
00426  * @param   capSrc  : timer clock source and edge
00427  * @param   capnum  : CAPn.capnum pin to use (if used)
00428  * @return  Nothing
00429  * @note    If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
00430  */
00431 STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
00432                                                      TIMER_CAP_SRC_STATE_T capSrc,
00433                                                      int8_t capnum)
00434 {
00435     pTMR->CTCR  = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
00436 }
00437 
00438 /**
00439  * @}
00440  */
00441 
00442 #ifdef __cplusplus
00443 }
00444 #endif
00445 
00446 #endif /* __TIMER_11XX_H_ */