sysctl_11xx.h

00001 /*
00002  * @brief LPC11XX System Control registers and control functions
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2012
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 #ifndef __SYSCTL_11XX_H_
00033 #define __SYSCTL_11XX_H_
00034 
00035 #ifdef __cplusplus
00036 extern "C" {
00037 #endif
00038 
00039 /** @defgroup SYSCTL_11XX CHIP: LPC11xx System Control block driver
00040  * @ingroup CHIP_11XX_Drivers
00041  * @{
00042  */
00043 
00044 /**
00045  * @brief LPC11XX System Control block structure
00046  */
00047 typedef struct {            /*!< SYSCTL Structure */
00048     __IO uint32_t  SYSMEMREMAP ;     /*!< System Memory remap register */
00049     __IO uint32_t  PRESETCTRL ;      /*!< Peripheral reset Control register */
00050     __IO uint32_t  SYSPLLCTRL ;      /*!< System PLL control register */
00051     __I  uint32_t  SYSPLLSTAT ;      /*!< System PLL status register */
00052     __IO uint32_t  USBPLLCTRL ;      /*!< USB PLL control register, LPC11UXX only*/
00053     __I  uint32_t  USBPLLSTAT ;      /*!< USB PLL status register, LPC11UXX only */
00054     __I  uint32_t  RESERVED1[2];
00055     __IO uint32_t  SYSOSCCTRL ;      /*!< System Oscillator control register */
00056     __IO uint32_t  WDTOSCCTRL ;      /*!< Watchdog Oscillator control register */
00057     __IO uint32_t  IRCCTRL ;         /*!< IRC control register, not on LPC11UXX and LPC11EXX */
00058     __IO uint32_t  LFOSCCTRL ;       /*!< LF oscillator control, LPC11AXX only */
00059     __IO uint32_t  SYSRSTSTAT ;      /*!< System Reset Status register           */
00060     __I  uint32_t  RESERVED2[3];
00061     __IO uint32_t  SYSPLLCLKSEL ;    /*!< System PLL clock source select register */
00062     __IO uint32_t  SYSPLLCLKUEN ;    /*!< System PLL clock source update enable register*/
00063     __IO uint32_t  USBPLLCLKSEL ;    /*!< USB PLL clock source select register, LPC11UXX only */
00064     __IO uint32_t  USBPLLCLKUEN ;    /*!< USB PLL clock source update enable register, LPC11UXX only */
00065     __I  uint32_t  RESERVED3[8];
00066     __IO uint32_t  MAINCLKSEL ;  /*!< Main clock source select register      */
00067     __IO uint32_t  MAINCLKUEN ;  /*!< Main clock source update enable register   */
00068     __IO uint32_t  SYSAHBCLKDIV ;    /*!< System Clock divider register */
00069     __I  uint32_t  RESERVED4;
00070     __IO uint32_t  SYSAHBCLKCTRL ;   /*!< System clock control register */
00071     __I  uint32_t  RESERVED5[4];
00072     __IO uint32_t  SSP0CLKDIV ;  /*!< SSP0 clock divider register   */
00073     __IO uint32_t  USARTCLKDIV ; /*!< UART clock divider register   */
00074     __IO uint32_t  SSP1CLKDIV ;  /*!< SSP1 clock divider register, not on CHIP_LPC110X, CHIP_LPC11XXLV */
00075     __I  uint32_t  RESERVED6[8];
00076     __IO uint32_t  USBCLKSEL ;   /*!< USB clock source select register, LPC11UXX only */
00077     __IO uint32_t  USBCLKUEN ;   /*!< USB clock source update enable register, LPC11UXX only */
00078     __IO uint32_t  USBCLKDIV ;   /*!< USB clock source divider register, LPC11UXX only */
00079     __I  uint32_t  RESERVED7;
00080     __IO uint32_t  WDTCLKSEL ;   /*!< WDT clock source select register, some parts only */
00081     __IO uint32_t  WDTCLKUEN ;   /*!< WDT clock source update enable register, some parts only */
00082     __IO uint32_t  WDTCLKDIV ;   /*!< WDT clock divider register, some parts only */
00083     __I  uint32_t  RESERVED8;
00084     __IO uint32_t  CLKOUTSEL ;   /*!< Clock out source select register, not on LPC1102/04 */
00085     __IO uint32_t  CLKOUTUEN ;   /*!< Clock out source update enable register, not on LPC1102/04 */
00086     __IO uint32_t  CLKOUTDIV ;   /*!< Clock out divider register, not on LPC1102/04 */
00087     __I  uint32_t  RESERVED9[5];
00088     __I  uint32_t  PIOPORCAP[2];/*!< POR captured PIO status registers, index 1 on LPC1102/04 */
00089     __I  uint32_t  RESERVED10[18];
00090     __IO uint32_t  BODCTRL ;     /*!< Brown Out Detect register */
00091     __IO uint32_t  SYSTCKCAL ;   /*!< System tick counter calibration register */
00092     __I  uint32_t  RESERVED11[6];
00093     __IO uint32_t  IRQLATENCY ;  /*!< IRQ delay register, on LPC11UXX and LPC11EXX only */
00094     __IO uint32_t  NMISRC ;      /*!< NMI source control register,some parts only */
00095     __IO uint32_t  PINTSEL[8];  /*!< GPIO pin interrupt select register 0-7, not on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */
00096     __IO uint32_t  USBCLKCTRL ;  /*!< USB clock control register, LPC11UXX only */
00097     __I  uint32_t  USBCLKST ;    /*!< USB clock status register, LPC11UXX only */
00098     __I  uint32_t  RESERVED12[24];
00099     __IO uint32_t  STARTAPRP0 ;  /*!< Start loigc 0 interrupt wake up enable register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */
00100     __IO uint32_t  STARTERP0 ;   /*!< Start loigc signal enable register 0, not on LPC11AXX */
00101     __IO uint32_t  STARTRSRP0CLR ;   /*!< Start loigc reset register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */
00102     __IO uint32_t  STARTSRP0 ;       /*!< Start loigc status register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */
00103     __I  uint32_t  RESERVED13;
00104     __IO uint32_t  STARTERP1 ;   /*!< Start logic 1 interrupt wake up enable register 1, on LPC11UXX and LPC11EXX only */
00105     __I  uint32_t  RESERVED14[6];
00106     __IO uint32_t  PDSLEEPCFG ;  /*!< Power down states in deep sleep mode register, not on LPC11AXX */
00107     __IO uint32_t  PDWAKECFG ;   /*!< Power down states in wake up from deep sleep register, not on LPC11AXX */
00108     __IO uint32_t  PDRUNCFG ;    /*!< Power configuration register*/
00109     __I  uint32_t  RESERVED15[110];
00110     __I  uint32_t  DEVICEID ;    /*!< Device ID register */
00111 } LPC_SYSCTL_T;
00112 
00113 /**
00114  * System memory remap modes used to remap interrupt vectors
00115  */
00116 typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
00117     REMAP_BOOT_LOADER_MODE , /*!< Interrupt vectors are re-mapped to Boot ROM */
00118     REMAP_USER_RAM_MODE ,    /*!< Interrupt vectors are re-mapped to Static RAM */
00119     REMAP_USER_FLASH_MODE    /*!< Interrupt vectors are not re-mapped and reside in Flash */
00120 } CHIP_SYSCTL_BOOT_MODE_REMAP_T;
00121 
00122 /**
00123  * @brief   Re-map interrupt vectors
00124  * @param   remap   : system memory map value
00125  * @return  Nothing
00126  */
00127 STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
00128 {
00129     LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
00130 }
00131 
00132 /**
00133  * Peripheral reset identifiers, not available on all devices
00134  */
00135 typedef enum {
00136     RESET_SSP0 ,         /*!< SSP0 reset control */
00137     RESET_I2C0 ,         /*!< I2C0 reset control */
00138     RESET_SSP1 ,         /*!< SSP1 reset control */
00139 #if !defined(CHIP_LPC1125)
00140     RESET_CAN0 ,         /*!< CAN0 reset control */
00141     RESET_UART0 ,        /*!< UART0 reset control */
00142     RESET_TIMER0_16 ,    /*!< 16-bit Timer 0 reset control */
00143     RESET_TIMER1_16 ,    /*!< 16-bit Timer 1 reset control */
00144     RESET_TIMER0_32 ,    /*!< 32-bit Timer 0 reset control */
00145     RESET_TIMER1_32 ,    /*!< 32-bit Timer 1 reset control */
00146     RESET_ACMP ,         /*!< Analog comparator reset control */
00147     RESET_DAC0 ,         /*!< DAC reset control */
00148     RESET_ADC0           /*!< ADC reset control */
00149 #endif
00150 } CHIP_SYSCTL_PERIPH_RESET_T;
00151 
00152 /**
00153  * @brief   Assert reset for a peripheral
00154  * @param   periph  : Peripheral to assert reset for
00155  * @return  Nothing
00156  * @note    The peripheral will stay in reset until reset is de-asserted. Call
00157  * Chip_SYSCTL_DeassertPeriphReset() to de-assert the reset.
00158  */
00159 STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
00160 {
00161     LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
00162 }
00163 
00164 /**
00165  * @brief   De-assert reset for a peripheral
00166  * @param   periph  : Peripheral to de-assert reset for
00167  * @return  Nothing
00168  */
00169 STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
00170 {
00171     LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
00172 }
00173 
00174 /**
00175  * @brief   Resets a peripheral
00176  * @param   periph  :   Peripheral to reset
00177  * @return  Nothing
00178  */
00179 STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
00180 {
00181     Chip_SYSCTL_AssertPeriphReset(periph);
00182     Chip_SYSCTL_DeassertPeriphReset(periph);
00183 }
00184 
00185 /**
00186  * System reset status
00187  */
00188 #define SYSCTL_RST_POR    (1 << 0)  /*!< POR reset status */
00189 #define SYSCTL_RST_EXTRST (1 << 1)  /*!< External reset status */
00190 #define SYSCTL_RST_WDT    (1 << 2)  /*!< Watchdog reset status */
00191 #define SYSCTL_RST_BOD    (1 << 3)  /*!< Brown-out detect reset status */
00192 #define SYSCTL_RST_SYSRST (1 << 4)  /*!< software system reset status */
00193 
00194 /**
00195  * Non-Maskable Interrupt Enable/Disable value
00196  */
00197 #define SYSCTL_NMISRC_ENABLE   ((uint32_t) 1 << 31) /*!< Enable the Non-Maskable Interrupt (NMI) source */
00198 
00199 /**
00200  * @brief   Get system reset status
00201  * @return  An Or'ed value of SYSCTL_RST_*
00202  * @note    This function returns the detected reset source(s).
00203  */
00204 STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
00205 {
00206     return LPC_SYSCTL->SYSRSTSTAT;
00207 }
00208 
00209 /**
00210  * @brief   Clear system reset status
00211  * @param   reset   : An Or'ed value of SYSCTL_RST_* status to clear
00212  * @return  Nothing
00213  * @note    This function returns the detected reset source(s).
00214  */
00215 STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
00216 {
00217     LPC_SYSCTL->SYSRSTSTAT = reset;
00218 }
00219 
00220 /**
00221  * @brief   Read POR captured PIO status
00222  * @param   index   : POR register index, 0 or 1
00223  * @return  captured POR PIO status
00224  * @note    Some devices only support index 0.
00225  */
00226 STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
00227 {
00228     return LPC_SYSCTL->PIOPORCAP[index];
00229 }
00230 
00231 /**
00232  * Brown-out detector reset level
00233  */
00234 typedef enum CHIP_SYSCTL_BODRSTLVL {
00235 #if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC1125)
00236     SYSCTL_BODRSTLVL_1_46V , /*!< Brown-out reset at 1.46v */
00237 #else
00238     SYSCTL_BODRSTLVL_RESERVED1 , /*!< Only possible value for LPC11A/02/XXLV */
00239 #endif
00240 #if defined(CHIP_LPC11XXLV)
00241     SYSCTL_BODRSTLVL_RESERVED1 ,
00242     SYSCTL_BODRSTLVL_RESERVED2,
00243     SYSCTL_BODRSTLVL_RESERVED3,
00244 #elif defined(CHIP_LPC11AXX)
00245     SYSCTL_BODRSTLVL_RESERVED2,
00246     SYSCTL_BODRSTLVL_2_52V , /*!< Brown-out reset at 2.52v */
00247     SYSCTL_BODRSTLVL_2_80V , /*!< Brown-out reset at 2.80v */
00248 #else
00249     SYSCTL_BODRSTLVL_2_06V , /*!< Brown-out reset at 2.06v */
00250     SYSCTL_BODRSTLVL_2_35V , /*!< Brown-out reset at 2.35v */
00251     SYSCTL_BODRSTLVL_2_63V , /*!< Brown-out reset at 2.63v */
00252 #endif
00253 } CHIP_SYSCTL_BODRSTLVL_T;
00254 
00255 /**
00256  * Brown-out detector interrupt level
00257  */
00258 typedef enum CHIP_SYSCTL_BODRINTVAL {
00259     SYSCTL_BODINTVAL_RESERVED1,
00260 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)
00261     SYSCTL_BODINTVAL_2_22V , /*!< Brown-out interrupt at 2.22v */
00262     SYSCTL_BODINTVAL_2_52V , /*!< Brown-out interrupt at 2.52v */
00263     SYSCTL_BODINTVAL_2_80V , /*!< Brown-out interrupt at 2.8v */
00264 #endif
00265 } CHIP_SYSCTL_BODRINTVAL_T;
00266 
00267 /**
00268  * @brief   Set brown-out detection interrupt and reset levels
00269  * @param   rstlvl  : Brown-out detector reset level
00270  * @param   intlvl  : Brown-out interrupt level
00271  * @return  Nothing
00272  * @note    Brown-out detection reset will be disabled upon exiting this function.
00273  * Use Chip_SYSCTL_EnableBODReset() to re-enable.
00274  */
00275 STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
00276                                             CHIP_SYSCTL_BODRINTVAL_T intlvl)
00277 {
00278     LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
00279 }
00280 
00281 #if defined(CHIP_LPC11AXX)
00282 /**
00283  * @brief   Returns brown-out detection interrupt status
00284  * @return  true if the BOD interrupt is pending, otherwise false
00285  */
00286 STATIC INLINE bool Chip_SYSCTL_GetBODIntStatus(void)
00287 {
00288     return (bool) ((LPC_SYSCTL->BODCTRL & (1 << 6)) != 0);
00289 }
00290 
00291 #else
00292 /**
00293  * @brief   Enable brown-out detection reset
00294  * @return  Nothing
00295  */
00296 STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
00297 {
00298     LPC_SYSCTL->BODCTRL |= (1 << 4);
00299 }
00300 
00301 /**
00302  * @brief   Disable brown-out detection reset
00303  * @return  Nothing
00304  */
00305 STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
00306 {
00307     LPC_SYSCTL->BODCTRL &= ~(1 << 4);
00308 }
00309 
00310 #endif
00311 
00312 /**
00313  * @brief   Set System tick timer calibration value
00314  * @param   sysCalVal   : System tick timer calibration value
00315  * @return  Nothing
00316  */
00317 STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
00318 {
00319     LPC_SYSCTL->SYSTCKCAL = sysCalVal;
00320 }
00321 
00322 #if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)
00323 /**
00324  * @brief   Set System IRQ latency
00325  * @param   latency : Latency in clock ticks
00326  * @return  Nothing
00327  * @note    Sets the IRQ latency, a value between 0 and 255 clocks. Lower
00328  * values allow better latency.
00329  */
00330 STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
00331 {
00332     LPC_SYSCTL->IRQLATENCY = latency;
00333 }
00334 
00335 /**
00336  * @brief   Get System IRQ latency
00337  * @return  Latency in clock ticks
00338  */
00339 STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
00340 {
00341     return LPC_SYSCTL->IRQLATENCY;
00342 }
00343 
00344 #endif
00345 
00346 #if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)
00347 /**
00348  * @brief   Set source for non-maskable interrupt (NMI)
00349  * @param   intsrc  : IRQ number to assign to the NMI
00350  * @return  Nothing
00351  * @note    The NMI source will be disabled upon exiting this function. use the
00352  * Chip_SYSCTL_EnableNMISource() function to enable the NMI source.
00353  */
00354 STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
00355 {
00356     LPC_SYSCTL->NMISRC = intsrc;
00357 }
00358 
00359 /**
00360  * @brief   Enable interrupt used for NMI source
00361  * @return  Nothing
00362  */
00363 STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
00364 {
00365     LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
00366 }
00367 
00368 /**
00369  * @brief   Disable interrupt used for NMI source
00370  * @return  Nothing
00371  */
00372 STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
00373 {
00374     LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
00375 }
00376 
00377 #endif
00378 
00379 #if defined(CHIP_LPC11AXX)
00380 /**
00381  * @brief   Setup a pin source for the pin interrupts (0-7)
00382  * @param   intno   : IRQ number
00383  * @param   port        : port number 0/1)
00384  * @param   pin     : pin number (0->31)
00385  * @return  Nothing
00386  */
00387 STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
00388 {
00389     LPC_SYSCTL->PINTSEL[intno] = (uint32_t) ((port << 5) | pin);
00390 }
00391 
00392 #elif defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
00393 /**
00394  * @brief   Setup a pin source for the pin interrupts (0-7)
00395  * @param   intno   : IRQ number
00396  * @param   port        : port number 0/1)
00397  * @param   pin     : pin number (0->23 for GPIO Port 0 and 0->31 for GPIO Port 1)
00398  * @return  Nothing
00399  */
00400 STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
00401 {
00402     LPC_SYSCTL->PINTSEL[intno] = (uint32_t) (port * 24 + pin);
00403 }
00404 
00405 #endif
00406 
00407 #if defined(CHIP_LPC11UXX)
00408 /**
00409  * @brief   Setup USB clock control
00410  * @param   ap_clk  : USB need_clock signal control (0 or 1)
00411  * @param   pol_clk : USB need_clock polarity for triggering the USB wake-up interrupt (0 or 1)
00412  * @return  Nothing
00413  * @note    See the USBCLKCTRL register in the user manual for these settings.
00414  */
00415 STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
00416 {
00417     LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
00418 }
00419 
00420 /**
00421  * @brief   Returns the status of the USB need_clock signal
00422  * @return  true if USB need_clock statis is high, otherwise false
00423  */
00424 STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
00425 {
00426     return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
00427 }
00428 
00429 #endif
00430 
00431 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC1125)
00432 /**
00433  * @brief   Set edge for PIO start logic
00434  * @param   pin     : PIO pin number
00435  * @param   edge    : 0 for falling edge, 1 for rising edge
00436  * @return  Nothing
00437  * @note    Different devices support different pins, see the user manual for supported pins.
00438  */
00439 STATIC INLINE void Chip_SYSCTL_SetStartPin(uint32_t pin, uint32_t edge)
00440 {
00441     if (edge) {
00442         LPC_SYSCTL->STARTAPRP0 |= (1 << pin);
00443     }
00444     else {
00445         LPC_SYSCTL->STARTAPRP0 &= ~(1 << pin);
00446     }
00447 }
00448 
00449 /**
00450  * @brief   Enable PIO start logic for a pin
00451  * @param   pin : PIO pin number
00452  * @return  Nothing
00453  * @note    Different devices support different pins, see the user manual for supported pins.
00454  */
00455 STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint32_t pin)
00456 {
00457     LPC_SYSCTL->STARTERP0 |= (1 << pin);
00458 }
00459 
00460 /**
00461  * @brief   Disable PIO start logic for a pin
00462  * @param   pin : PIO pin number
00463  * @return  Nothing
00464  * @note    Different devices support different pins, see the user manual for supported pins.
00465  */
00466 STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint32_t pin)
00467 {
00468     LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
00469 }
00470 
00471 /**
00472  * @brief   Clear PIO start logic state
00473  * @param   pin : PIO pin number
00474  * @return  Nothing
00475  * @note    Different devices support different pins, see the user manual for supported pins.
00476  */
00477 STATIC INLINE void Chip_SYSCTL_ResetStartPin(uint32_t pin)
00478 {
00479     LPC_SYSCTL->STARTRSRP0CLR = (1 << pin);
00480 }
00481 
00482 /**
00483  * @brief   Returns status of pin wakeup
00484  * @param   pin : PIO pin number
00485  * @return  true if a pin start signal is pending, otherwise false
00486  * @note    Different devices support different pins, see the user manual for supported pins.
00487  */
00488 STATIC INLINE bool Chip_SYSCTL_GetStartPinStatus(uint32_t pin)
00489 {
00490     return (bool) ((LPC_SYSCTL->STARTSRP0 & (1 << pin)) != 0);
00491 }
00492 
00493 #endif
00494 
00495 #if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
00496 /**
00497  * @brief   Enables a pin's (PINT) wakeup logic
00498  * @param   pin : pin number
00499  * @return  Nothing
00500  * @note    Different devices support different pins, see the user manual for supported pins.
00501  */
00502 STATIC INLINE void Chip_SYSCTL_EnablePINTWakeup(uint32_t pin)
00503 {
00504     LPC_SYSCTL->STARTERP0 |= (1 << pin);
00505 }
00506 
00507 /**
00508  * @brief   Disables a pin's (PINT) wakeup logic
00509  * @param   pin : pin number
00510  * @return  Nothing
00511  * @note    Different devices support different pins, see the user manual for supported pins.
00512  */
00513 STATIC INLINE void Chip_SYSCTL_DisablePINTWakeup(uint32_t pin)
00514 {
00515     LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
00516 }
00517 
00518 /**
00519  * Peripheral interrupt wakeup events, LPC11E/Uxx only
00520  */
00521 #define SYSCTL_WAKEUP_WWDTINT    (1 << 12)  /*!< WWDT interrupt wake-up */
00522 #define SYSCTL_WAKEUP_BODINT     (1 << 13)  /*!< Brown Out Detect (BOD) interrupt wake-up */
00523 #define SYSCTL_WAKEUP_USB_WAKEUP (1 << 19)  /*!< USB need_clock signal wake-up, LPC11Uxx only */
00524 #define SYSCTL_WAKEUP_GPIOINT0   (1 << 20)  /*!< GPIO GROUP0 interrupt wake-up */
00525 #define SYSCTL_WAKEUP_GPIOINT1   (1 << 21)  /*!< GPIO GROUP1 interrupt wake-up */
00526 
00527 /**
00528  * @brief   Enables a peripheral's wakeup logic
00529  * @param   periphmask  : OR'ed values of SYSCTL_WAKEUP_* for wakeup
00530  * @return  Nothing
00531  */
00532 STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
00533 {
00534     LPC_SYSCTL->STARTERP1 |= periphmask;
00535 }
00536 
00537 /**
00538  * @brief   Disables a peripheral's wakeup logic
00539  * @param   periphmask  : OR'ed values of SYSCTL_WAKEUP_* for wakeup
00540  * @return  Nothing
00541  */
00542 STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
00543 {
00544     LPC_SYSCTL->STARTERP1 &= ~periphmask;
00545 }
00546 
00547 #endif
00548 
00549 #if !defined(LPC11AXX)
00550 /**
00551  * Deep sleep setup values
00552  */
00553 #define SYSCTL_DEEPSLP_BOD_PD    (1 << 3)   /*!< BOD power-down control in Deep-sleep mode, powered down */
00554 #define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6)   /*!< Watchdog oscillator power control in Deep-sleep, powered down */
00555 #if defined(CHIP_LPC11XXLV)
00556 #define SYSCTL_DEEPSLP_IRCOUT_PD (1 << 0)   /*!< IRC oscillator output in Deep-sleep mode, powered down */
00557 #define SYSCTL_DEEPSLP_IRC_PD    (1 << 1)   /*!< IRC oscillator in Deep-sleep, powered down */
00558 #endif
00559 
00560 /**
00561  * @brief   Setup deep sleep behaviour for power down
00562  * @param   sleepmask   : OR'ed values of SYSCTL_DEEPSLP_* values (high to powerdown on deepsleep)
00563  * @return  Nothing
00564  * @note    This must be setup prior to using deep sleep. See the user manual
00565  ***(PDSLEEPCFG register) for more info on setting this up. This function selects
00566  * which peripherals are powered down on deep sleep.
00567  * This function should only be called once with all options for power-down
00568  * in that call.
00569  */
00570 void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);
00571 
00572 /**
00573  * @brief   Returns current deep sleep mask
00574  * @return  OR'ed values of SYSCTL_DEEPSLP_* values
00575  * @note    A high bit indicates the peripheral will power down on deep sleep.
00576  */
00577 STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
00578 {
00579     return LPC_SYSCTL->PDSLEEPCFG;
00580 }
00581 
00582 /**
00583  * Deep sleep to wakeup setup values
00584  */
00585 #define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0)   /*!< IRC oscillator output wake-up configuration */
00586 #define SYSCTL_SLPWAKE_IRC_PD    (1 << 1)   /*!< IRC oscillator power-down wake-up configuration */
00587 #define SYSCTL_SLPWAKE_FLASH_PD  (1 << 2)   /*!< Flash wake-up configuration */
00588 #define SYSCTL_SLPWAKE_BOD_PD    (1 << 3)   /*!< BOD wake-up configuration */
00589 #define SYSCTL_SLPWAKE_ADC_PD    (1 << 4)   /*!< ADC wake-up configuration */
00590 #define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5)   /*!< System oscillator wake-up configuration */
00591 #define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6)   /*!< Watchdog oscillator wake-up configuration */
00592 #define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7)   /*!< System PLL wake-up configuration */
00593 #if defined(CHIP_LPC11UXX)
00594 #define SYSCTL_SLPWAKE_USBPLL_PD (1 << 8)   /*!< USB PLL wake-up configuration */
00595 #define SYSCTL_SLPWAKE_USBPAD_PD (1 << 10)  /*!< USB transceiver wake-up configuration */
00596 #endif
00597 
00598 /**
00599  * @brief   Setup wakeup behaviour from deep sleep
00600  * @param   wakeupmask  : OR'ed values of SYSCTL_SLPWAKE_* values (high is powered down)
00601  * @return  Nothing
00602  * @note    This must be setup prior to using deep sleep. See the user manual
00603  * (PDWAKECFG register) for more info on setting this up. This function selects
00604  * which peripherals are powered up on exit from deep sleep.
00605  * This function should only be called once with all options for wakeup
00606  * in that call.
00607  */
00608 void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
00609 
00610 /**
00611  * @brief   Return current wakeup mask
00612  * @return  OR'ed values of SYSCTL_SLPWAKE_* values
00613  * @note    A high state indicates the peripehral will powerup on wakeup.
00614  */
00615 STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
00616 {
00617     return LPC_SYSCTL->PDWAKECFG;
00618 }
00619 
00620 #endif
00621 
00622 /**
00623  * Power down configuration values
00624  */
00625 #define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 0) /*!< IRC oscillator output power down */
00626 #define SYSCTL_POWERDOWN_IRC_PD    (1 << 1) /*!< IRC oscillator power-down */
00627 #define SYSCTL_POWERDOWN_FLASH_PD  (1 << 2) /*!< Flash power down */
00628 #if !defined(CHIP_LPC11AXX)
00629 #define SYSCTL_POWERDOWN_BOD_PD    (1 << 3) /*!< BOD power down */
00630 #endif
00631 #define SYSCTL_POWERDOWN_ADC_PD    (1 << 4) /*!< ADC power down */
00632 #define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 5) /*!< System oscillator power down */
00633 #define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator power down */
00634 #define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 7) /*!< System PLL power down */
00635 #if defined(CHIP_LPC11UXX)
00636 #define SYSCTL_POWERDOWN_USBPLL_PD (1 << 8) /*!< USB PLL power-down */
00637 #define SYSCTL_POWERDOWN_USBPAD_PD (1 << 10)/*!< USB transceiver power-down */
00638 #endif
00639 #if defined(CHIP_LPC11AXX)
00640 #define SYSCTL_POWERDOWN_LFOSC_PD (1 << 13) /*!< Low frequency oscillator power-down */
00641 #define SYSCTL_POWERDOWN_DAC_PD   (1 << 14) /*!< DAC power-down */
00642 #define SYSCTL_POWERDOWN_TS_PD    (1 << 15) /*!< Temperature Sensor power-down */
00643 #define SYSCTL_POWERDOWN_ACOMP_PD (1 << 16) /*!< Analog Comparator power-down */
00644 #endif
00645 
00646 /**
00647  * @brief   Power down one or more blocks or peripherals
00648  * @param   powerdownmask   : OR'ed values of SYSCTL_POWERDOWN_* values
00649  * @return  Nothing
00650  */
00651 void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
00652 
00653 /**
00654  * @brief   Power up one or more blocks or peripherals
00655  * @param   powerupmask : OR'ed values of SYSCTL_POWERDOWN_* values
00656  * @return  Nothing
00657  */
00658 void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
00659 
00660 /**
00661  * @brief   Get power status
00662  * @return  OR'ed values of SYSCTL_POWERDOWN_* values
00663  * @note    A high state indicates the peripheral is powered down.
00664  */
00665 STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
00666 {
00667     return LPC_SYSCTL->PDRUNCFG;
00668 }
00669 
00670 /**
00671  * @brief   Return the device ID
00672  * @return  the device ID
00673  */
00674 STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
00675 {
00676     return LPC_SYSCTL->DEVICEID;
00677 }
00678 
00679 /**
00680  * @}
00681  */
00682 
00683 #ifdef __cplusplus
00684 }
00685 #endif
00686 
00687 #endif /*!< __SYSCTL_11XX_H_ */