clock_11xx.h

00001 /*
00002  * @brief LPC11XX Clock control functions
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2012
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 #ifndef __CLOCK_11XX_H_
00033 #define __CLOCK_11XX_H_
00034 
00035 #ifdef __cplusplus
00036 extern "C" {
00037 #endif
00038 
00039 /** @defgroup CLOCK_11XX CHIP: LPC11xx Clock Control block driver
00040  * @ingroup CHIP_11XX_Drivers
00041  * @{
00042  */
00043 
00044 /** Internal oscillator frequency */
00045 #define SYSCTL_IRC_FREQ (12000000)
00046 
00047 /**
00048  * @brief   Set System PLL divider values
00049  * @param   msel    : PLL feedback divider value. M = msel + 1.
00050  * @param   psel    : PLL post divider value. P =  (1<<psel).
00051  * @return  Nothing
00052  * @note    See the user manual for how to setup the PLL.
00053  */
00054 STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
00055 {
00056     LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
00057 }
00058 
00059 /**
00060  * @brief   Read System PLL lock status
00061  * @return  true of the PLL is locked. false if not locked
00062  */
00063 STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
00064 {
00065     return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
00066 }
00067 
00068 /**
00069  * Clock sources for system and USB PLLs
00070  */
00071 typedef enum CHIP_SYSCTL_PLLCLKSRC {
00072     SYSCTL_PLLCLKSRC_IRC  = 0,       /*!< Internal oscillator in */
00073     SYSCTL_PLLCLKSRC_MAINOSC ,       /*!< Crystal (main) oscillator in */
00074 #if defined(CHIP_LPC11AXX)
00075     SYSCTL_PLLCLKSRC_EXT_CLKIN , /*!< External clock in (11Axx only) */
00076 #else
00077     SYSCTL_PLLCLKSRC_RESERVED1 , /*!< Reserved */
00078 #endif
00079     SYSCTL_PLLCLKSRC_RESERVED2 , /*!< Reserved */
00080 } CHIP_SYSCTL_PLLCLKSRC_T;
00081 
00082 /**
00083  * @brief   Set System PLL clock source
00084  * @param   src : Clock source for system PLL
00085  * @return  Nothing
00086  * @note    This function will also toggle the clock source update register
00087  * to update the clock source.
00088  */
00089 void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
00090 
00091 #if defined(CHIP_LPC11UXX)
00092 /**
00093  * @brief   Set USB PLL divider values
00094  * @param   msel    : PLL feedback divider value. M = msel + 1.
00095  * @param   psel    : PLL post divider value. P = (1<<psel).
00096  * @return  Nothing
00097  * @note    See the user manual for how to setup the PLL.
00098  */
00099 STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
00100 {
00101     LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
00102 }
00103 
00104 /**
00105  * @brief   Read USB PLL lock status
00106  * @return  true of the PLL is locked. false if not locked
00107  */
00108 STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
00109 {
00110     return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
00111 }
00112 
00113 /**
00114  * @brief   Set USB PLL clock source
00115  * @param   src : Clock source for USB PLL
00116  * @return  Nothing
00117  * @note    This function will also toggle the clock source update register
00118  * to update the clock source.
00119  */
00120 void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
00121 
00122 #endif /*defined(CHIP_LPC11UXX)*/
00123 
00124 /**
00125  * @brief   Bypass System Oscillator and set oscillator frequency range
00126  * @param   bypass  : Flag to bypass oscillator
00127  * @param   highfr  : Flag to set oscillator range from 15-25 MHz
00128  * @return  Nothing
00129  * @note    Sets the PLL input to bypass the oscillator. This would be
00130  * used if an external clock that is not an oscillator is attached
00131  * to the XTALIN pin.
00132  */
00133 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
00134 
00135 /**
00136  * Watchdog and low frequency oscillator frequencies plus or minus 40%
00137  */
00138 typedef enum CHIP_WDTLFO_OSC {
00139     WDTLFO_OSC_ILLEGAL,
00140     WDTLFO_OSC_0_60 ,    /*!< 0.6 MHz watchdog/LFO rate */
00141     WDTLFO_OSC_1_05 ,    /*!< 1.05 MHz watchdog/LFO rate */
00142     WDTLFO_OSC_1_40 ,    /*!< 1.4 MHz watchdog/LFO rate */
00143     WDTLFO_OSC_1_75 ,    /*!< 1.75 MHz watchdog/LFO rate */
00144     WDTLFO_OSC_2_10 ,    /*!< 2.1 MHz watchdog/LFO rate */
00145     WDTLFO_OSC_2_40 ,    /*!< 2.4 MHz watchdog/LFO rate */
00146     WDTLFO_OSC_2_70 ,    /*!< 2.7 MHz watchdog/LFO rate */
00147     WDTLFO_OSC_3_00 ,    /*!< 3.0 MHz watchdog/LFO rate */
00148     WDTLFO_OSC_3_25 ,    /*!< 3.25 MHz watchdog/LFO rate */
00149     WDTLFO_OSC_3_50 ,    /*!< 3.5 MHz watchdog/LFO rate */
00150     WDTLFO_OSC_3_75 ,    /*!< 3.75 MHz watchdog/LFO rate */
00151     WDTLFO_OSC_4_00 ,    /*!< 4.0 MHz watchdog/LFO rate */
00152     WDTLFO_OSC_4_20 ,    /*!< 4.2 MHz watchdog/LFO rate */
00153     WDTLFO_OSC_4_40 ,    /*!< 4.4 MHz watchdog/LFO rate */
00154     WDTLFO_OSC_4_60      /*!< 4.6 MHz watchdog/LFO rate */
00155 } CHIP_WDTLFO_OSC_T;
00156 
00157 /**
00158  * @brief   Setup Watchdog oscillator rate and divider
00159  * @param   wdtclk  : Selected watchdog clock rate
00160  * @param   div     : Watchdog divider value, even value between 2 and 64
00161  * @return  Nothing
00162  * @note    Watchdog rate = selected rate divided by divider rate
00163  */
00164 STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
00165 {
00166     LPC_SYSCTL->WDTOSCCTRL  = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
00167 }
00168 
00169 #if defined(CHIP_LPC11AXX)
00170 /**
00171  * @brief   Setup low frequency oscillator rate and divider
00172  * @param   lfoclk  : Selected low frequency clock rate
00173  * @param   div     : Low frequency divider value, even value between 2 and 64
00174  * @return  Nothing
00175  * @note    Low frequency oscillator rate = selected rate divided by divider rate
00176  */
00177 STATIC INLINE void Chip_Clock_SetLFOSC(CHIP_WDTLFO_OSC_T lfoclk, uint8_t div)
00178 {
00179     LPC_SYSCTL->LFOSCCTRL  = (((uint32_t) lfoclk) << 5) | ((div >> 1) - 1);
00180 }
00181 
00182 #endif /*CHIP_LPC11AXX*/
00183 
00184 /**
00185  * Clock sources for main system clock
00186  */
00187 typedef enum CHIP_SYSCTL_MAINCLKSRC {
00188     SYSCTL_MAINCLKSRC_IRC  = 0,      /*!< Internal oscillator */
00189     SYSCTL_MAINCLKSRC_PLLIN ,        /*!< System PLL input */
00190     SYSCTL_MAINCLKSRC_LFOSC ,        /*!< LF oscillator rate (11Axx only) */
00191     SYSCTL_MAINCLKSRC_WDTOSC  = SYSCTL_MAINCLKSRC_LFOSC , /*!< Watchdog oscillator rate */
00192     SYSCTL_MAINCLKSRC_PLLOUT ,       /*!< System PLL output */
00193 } CHIP_SYSCTL_MAINCLKSRC_T;
00194 
00195 /**
00196  * @brief   Set main system clock source
00197  * @param   src : Clock source for main system
00198  * @return  Nothing
00199  * @note    This function will also toggle the clock source update register
00200  * to update the clock source.
00201  */
00202 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
00203 
00204 /**
00205  * @brief   Returns the main clock source
00206  * @return  Which clock is used for the core clock source?
00207  */
00208 STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
00209 {
00210     return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
00211 }
00212 
00213 /**
00214  * @brief   Set system clock divider
00215  * @param   div : divider for system clock
00216  * @return  Nothing
00217  * @note    Use 0 to disable, or a divider value of 1 to 255. The system clock
00218  * rate is the main system clock divided by this value.
00219  */
00220 STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
00221 {
00222     LPC_SYSCTL->SYSAHBCLKDIV  = div;
00223 }
00224 
00225 /**
00226  * System and peripheral clocks
00227  */
00228 typedef enum CHIP_SYSCTL_CLOCK {
00229     SYSCTL_CLOCK_SYS  = 0,               /*!< 0: System clock */
00230     SYSCTL_CLOCK_ROM ,                   /*!<1:  ROM clock */
00231     SYSCTL_CLOCK_RAM ,                   /*!< 2: RAM clock */
00232     SYSCTL_CLOCK_FLASHREG ,              /*!< 3: FLASH register interface clock */
00233     SYSCTL_CLOCK_FLASHARRAY ,            /*!< 4: FLASH array access clock */
00234 #if defined(CHIP_LPC110X)
00235     SYSCTL_CLOCK_RESERVED5 ,             /*!< 5: Reserved */
00236 #else
00237     SYSCTL_CLOCK_I2C ,                   /*!< 5: I2C clock, not on LPC110x */
00238 #endif
00239     SYSCTL_CLOCK_GPIO ,                  /*!< 6: GPIO clock */
00240     SYSCTL_CLOCK_CT16B0 ,                /*!< 7: 16-bit Counter/timer 0 clock */
00241     SYSCTL_CLOCK_CT16B1 ,                /*!< 8: 16-bit Counter/timer 1 clock */
00242     SYSCTL_CLOCK_CT32B0 ,                /*!< 9: 32-bit Counter/timer 0 clock */
00243     SYSCTL_CLOCK_CT32B1 ,                /*!< 10: 32-bit Counter/timer 1 clock */
00244     SYSCTL_CLOCK_SSP0 ,                  /*!< 11: SSP0 clock */
00245     SYSCTL_CLOCK_UART0 ,                 /*!< 12: UART0 clock */
00246     SYSCTL_CLOCK_ADC ,                   /*!< 13: ADC clock */
00247 #if defined(CHIP_LPC11UXX)
00248     SYSCTL_CLOCK_USB ,                   /*!< 14: USB clock, LPC11Uxx only */
00249 #else
00250     SYSCTL_CLOCK_RESERVED14 ,            /*!< 14: Reserved */
00251 #endif
00252     SYSCTL_CLOCK_WDT ,                   /*!< 15: Watchdog timer clock */
00253     SYSCTL_CLOCK_IOCON ,                 /*!< 16: IOCON block clock */
00254 #if defined(CHIP_LPC11CXX)
00255     SYSCTL_CLOCK_CAN ,                   /*!< 17: CAN clock, LPC11Cxx only */
00256 #else
00257     SYSCTL_CLOCK_RESERVED17 ,            /*!< 17: Reserved */
00258 #endif
00259 #if !(defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV))  
00260     SYSCTL_CLOCK_SSP1 ,                  /*!< 18: SSP1 clock, LPC11A/C/E/Uxx//1125 only */
00261 #if !defined(CHIP_LPC11CXX)
00262     SYSCTL_CLOCK_PINT ,                  /*!< 19: GPIO Pin int register interface clock, LPC11A/E/Uxx only */
00263 #if defined(CHIP_LPC11AXX)
00264     SYSCTL_CLOCK_ACOMP ,                 /*!< 20: Analog comparator clock, LPC11Axx only */
00265     SYSCTL_CLOCK_DAC ,                   /*!< 21: DAC clock, LPC11Axx only */
00266 #else
00267     SYSCTL_CLOCK_RESERVED20 ,            /*!< 20: Reserved */
00268     SYSCTL_CLOCK_RESERVED21 ,            /*!< 21: Reserved */
00269 #endif
00270     SYSCTL_CLOCK_RESERVED22 ,            /*!< 22: Reserved */
00271     SYSCTL_CLOCK_P0INT ,                 /*!< 23: GPIO GROUP1 interrupt register clock, LPC11Axx only */
00272     SYSCTL_CLOCK_GROUP0INT  = SYSCTL_CLOCK_P0INT ,/*!< 23: GPIO GROUP0 interrupt register interface clock, LPC11E/Uxx only */
00273     SYSCTL_CLOCK_P1INT ,                 /*!< 24: GPIO GROUP1 interrupt register clock, LPC11Axx only */
00274     SYSCTL_CLOCK_GROUP1INT  = SYSCTL_CLOCK_P1INT ,/*!< 24: GPIO GROUP1 interrupt register interface clock, LPC11E/Uxx only */
00275     SYSCTL_CLOCK_RESERVED25 ,            /*!< 25: Reserved */
00276 #if defined(CHIP_LPC11EXX)  || defined(CHIP_LPC11UXX)
00277     SYSCTL_CLOCK_RAM1 ,                  /*!< 26: SRAM block (0x20000000) clock, LPC11E/Uxx only */
00278 #else
00279     SYSCTL_CLOCK_RESERVED26 ,            /*!< 26: Reserved */
00280 #endif
00281 #if defined(CHIP_LPC11UXX)
00282     SYSCTL_CLOCK_USBRAM ,                /*!< 27: USB SRAM block clock, LPC11Uxx only */
00283 #else
00284     SYSCTL_CLOCK_RESERVED27 ,            /*!< 27: Reserved */
00285 #endif
00286 #endif /* !defined(CHIP_LPC11CXX) */
00287 #endif /* !(defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV)) */
00288 } CHIP_SYSCTL_CLOCK_T;
00289 
00290 /**
00291  * @brief   Enable a system or peripheral clock
00292  * @param   clk : Clock to enable
00293  * @return  Nothing
00294  */
00295 STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
00296 {
00297     LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
00298 }
00299 
00300 /**
00301  * @brief   Disable a system or peripheral clock
00302  * @param   clk : Clock to disable
00303  * @return  Nothing
00304  */
00305 STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
00306 {
00307     LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
00308 }
00309 
00310 /**
00311  * @brief   Set SSP0 divider
00312  * @param   div : divider for SSP0 clock
00313  * @return  Nothing
00314  * @note    Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock
00315  * rate is the main system clock divided by this value.
00316  */
00317 STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
00318 {
00319     LPC_SYSCTL->SSP0CLKDIV  = div;
00320 }
00321 
00322 /**
00323  * @brief   Return SSP0 divider
00324  * @return  divider for SSP0 clock
00325  * @note    A value of 0 means the clock is disabled.
00326  */
00327 STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
00328 {
00329     return LPC_SYSCTL->SSP0CLKDIV;
00330 }
00331 
00332 /**
00333  * @brief   Set UART divider clock
00334  * @param   div : divider for UART clock
00335  * @return  Nothing
00336  * @note    Use 0 to disable, or a divider value of 1 to 255. The UART clock
00337  * rate is the main system clock divided by this value.
00338  */
00339 STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
00340 {
00341     LPC_SYSCTL->USARTCLKDIV  = div;
00342 }
00343 
00344 /**
00345  * @brief   Return UART divider
00346  * @return  divider for UART clock
00347  * @note    A value of 0 means the clock is disabled.
00348  */
00349 STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
00350 {
00351     return LPC_SYSCTL->USARTCLKDIV;
00352 }
00353 
00354 #if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)
00355 /**
00356  * @brief   Set SSP1 divider clock
00357  * @param   div : divider for SSP1 clock
00358  * @return  Nothing
00359  * @note    Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock
00360  * rate is the main system clock divided by this value.
00361  */
00362 STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
00363 {
00364     LPC_SYSCTL->SSP1CLKDIV  = div;
00365 }
00366 
00367 /**
00368  * @brief   Return SSP1 divider
00369  * @return  divider for SSP1 clock
00370  * @note    A value of 0 means the clock is disabled.
00371  */
00372 STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
00373 {
00374     return LPC_SYSCTL->SSP1CLKDIV;
00375 }
00376 
00377 #endif /*defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX)*/
00378 
00379 #if defined(CHIP_LPC11UXX)
00380 /**
00381  * Clock sources for USB
00382  */
00383 typedef enum CHIP_SYSCTL_USBCLKSRC {
00384     SYSCTL_USBCLKSRC_PLLOUT  = 0,    /*!< USB PLL out */
00385     SYSCTL_USBCLKSRC_MAINSYSCLK ,    /*!< Main system clock */
00386 } CHIP_SYSCTL_USBCLKSRC_T;
00387 
00388 /**
00389  * @brief   Set USB clock source and divider
00390  * @param   src : Clock source for USB
00391  * @param   div : divider for USB clock
00392  * @return  Nothing
00393  * @note    Use 0 to disable, or a divider value of 1 to 255. The USB clock
00394  * rate is either the main system clock or USB PLL output clock divided
00395  * by this value. This function will also toggle the clock source
00396  * update register to update the clock source.
00397  */
00398 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
00399 
00400 #endif /*CHIP_LPC11UXX*/
00401 
00402 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC1125)
00403 /**
00404  * Clock sources for WDT
00405  */
00406 typedef enum CHIP_SYSCTL_WDTCLKSRC {
00407     SYSCTL_WDTCLKSRC_IRC  = 0,       /*!< Internal oscillator for watchdog clock */
00408     SYSCTL_WDTCLKSRC_MAINSYSCLK ,    /*!< Main system clock for watchdog clock */
00409     SYSCTL_WDTCLKSRC_WDTOSC ,        /*!< Watchdog oscillator for watchdog clock */
00410 } CHIP_SYSCTL_WDTCLKSRC_T;
00411 
00412 /**
00413  * @brief   Set WDT clock source and divider
00414  * @param   src : Clock source for WDT
00415  * @param   div : divider for WDT clock
00416  * @return  Nothing
00417  * @note    Use 0 to disable, or a divider value of 1 to 255. The WDT clock
00418  * rate is the clock source divided by the divider. This function will
00419  * also toggle the clock source update register to update the clock
00420  * source.
00421  */
00422 void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div);
00423 
00424 #endif
00425 
00426 #if !defined(CHIP_LPC110X)
00427 /**
00428  * Clock sources for CLKOUT
00429  */
00430 typedef enum CHIP_SYSCTL_CLKOUTSRC {
00431     SYSCTL_CLKOUTSRC_IRC  = 0,       /*!< Internal oscillator for CLKOUT */
00432     SYSCTL_CLKOUTSRC_MAINOSC ,       /*!< Main oscillator for CLKOUT */
00433     SYSCTL_CLKOUTSRC_WDTOSC ,        /*!< Watchdog oscillator for CLKOUT */
00434     SYSCTL_CLKOUTSRC_LFOSC  = SYSCTL_CLKOUTSRC_WDTOSC ,   /*!< LF oscillator rate (LPC11A/Exx only) for CLKOUT */
00435     SYSCTL_CLKOUTSRC_MAINSYSCLK ,    /*!< Main system clock for CLKOUT */
00436 } CHIP_SYSCTL_CLKOUTSRC_T;
00437 
00438 /**
00439  * @brief   Set CLKOUT clock source and divider
00440  * @param   src : Clock source for CLKOUT
00441  * @param   div : divider for CLKOUT clock
00442  * @return  Nothing
00443  * @note    Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
00444  * rate is the clock source divided by the divider. This function will
00445  * also toggle the clock source update register to update the clock
00446  * source.
00447  */
00448 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
00449 
00450 #endif
00451 
00452 /**
00453  * @brief   Returns the main oscillator clock rate
00454  * @return  main oscillator clock rate
00455  */
00456 STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
00457 {
00458     return OscRateIn;
00459 }
00460 
00461 /**
00462  * @brief   Returns the internal oscillator (IRC) clock rate
00463  * @return  internal oscillator (IRC) clock rate
00464  */
00465 STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
00466 {
00467     return SYSCTL_IRC_FREQ;
00468 }
00469 
00470 #if defined(CHIP_LPC11AXX)
00471 /**
00472  * @brief   Returns the external clock input rate
00473  * @return  internal external clock input rate
00474  * @note    LPC11Axx devices only
00475  */
00476 STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void)
00477 {
00478     return ExtRateIn;
00479 }
00480 
00481 #endif
00482 
00483 /**
00484  * @brief   Return estimated watchdog oscillator rate
00485  * @return  Estimated watchdog oscillator rate
00486  * @note    This rate is accurate to plus or minus 40%.
00487  */
00488 uint32_t Chip_Clock_GetWDTOSCRate(void);
00489 
00490 #if defined(CHIP_LPC11AXX)
00491 /**
00492  * @brief   Return estimated low frequency oscillator rate
00493  * @return  Estimated low frequency oscillator rate
00494  * @note    This rate is accurate to plus or minus 40%.
00495  */
00496 uint32_t Chip_Clock_GetLFOOSCRate(void);
00497 
00498 #endif
00499 
00500 /**
00501  * @brief   Return System PLL input clock rate
00502  * @return  System PLL input clock rate
00503  */
00504 uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
00505 
00506 /**
00507  * @brief   Return System PLL output clock rate
00508  * @return  System PLL output clock rate
00509  */
00510 uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
00511 
00512 #if defined(CHIP_LPC11UXX)
00513 /**
00514  * @brief   Return USB PLL input clock rate
00515  * @return  USB PLL input clock rate
00516  */
00517 uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
00518 
00519 /**
00520  * @brief   Return USB PLL output clock rate
00521  * @return  USB PLL output clock rate
00522  */
00523 uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
00524 
00525 #endif
00526 
00527 /**
00528  * @brief   Return main clock rate
00529  * @return  main clock rate
00530  */
00531 uint32_t Chip_Clock_GetMainClockRate(void);
00532 
00533 /**
00534  * @brief   Return system clock rate
00535  * @return  system clock rate
00536  */
00537 uint32_t Chip_Clock_GetSystemClockRate(void);
00538 
00539 /**
00540  * @}
00541  */
00542 
00543 #ifdef __cplusplus
00544 }
00545 #endif
00546 
00547 #endif /* __CLOCK_11XX_H_ */