clock_11xx.c

00001 /*
00002  * @brief LPC11XX System clock control functions
00003  *
00004  * Copyright(C) NXP Semiconductors, 2012
00005  * All rights reserved.
00006  *
00007  * Software that is described herein is for illustrative purposes only
00008  * which provides customers with programming information regarding the
00009  * LPC products.  This software is supplied "AS IS" without any warranties of
00010  * any kind, and NXP Semiconductors and its licensor disclaim any and
00011  * all warranties, express or implied, including all implied warranties of
00012  * merchantability, fitness for a particular purpose and non-infringement of
00013  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00014  * or liability for the use of the software, conveys no license or rights under any
00015  * patent, copyright, mask work right, or any other intellectual property rights in
00016  * or to any products. NXP Semiconductors reserves the right to make changes
00017  * in the software without notification. NXP Semiconductors also makes no
00018  * representation or warranty that such application will be suitable for the
00019  * specified use without further testing or modification.
00020  *
00021  * Permission to use, copy, modify, and distribute this software and its
00022  * documentation is hereby granted, under NXP Semiconductors' and its
00023  * licensor's relevant copyrights in the software, without fee, provided that it
00024  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00025  * copyright, permission, and disclaimer notice must appear in all copies of
00026  * this code.
00027  */
00028 
00029 #include "chip.h"
00030 
00031 /*****************************************************************************
00032  * Private types/enumerations/variables
00033  ****************************************************************************/
00034 
00035 /* Inprecise clock rates for the watchdog oscillator */
00036 STATIC const uint32_t wdtOSCRate[WDTLFO_OSC_4_60  + 1] = {
00037     0,                  /* WDT_OSC_ILLEGAL */
00038     600000,             /* WDT_OSC_0_60 */
00039     1050000,            /* WDT_OSC_1_05 */
00040     1400000,            /* WDT_OSC_1_40 */
00041     1750000,            /* WDT_OSC_1_75 */
00042     2100000,            /* WDT_OSC_2_10 */
00043     2400000,            /* WDT_OSC_2_40 */
00044     2700000,            /* WDT_OSC_2_70 */
00045     3000000,            /* WDT_OSC_3_00 */
00046     3250000,            /* WDT_OSC_3_25 */
00047     3500000,            /* WDT_OSC_3_50 */
00048     3750000,            /* WDT_OSC_3_75 */
00049     4000000,            /* WDT_OSC_4_00 */
00050     4200000,            /* WDT_OSC_4_20 */
00051     4400000,            /* WDT_OSC_4_40 */
00052     4600000             /* WDT_OSC_4_60 */
00053 };
00054 
00055 /*****************************************************************************
00056  * Public types/enumerations/variables
00057  ****************************************************************************/
00058 
00059 /*****************************************************************************
00060  * Private functions
00061  ****************************************************************************/
00062 
00063 /* Compute a WDT or LFO rate */
00064 STATIC uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
00065 {
00066     uint32_t div;
00067     CHIP_WDTLFO_OSC_T clk;
00068 
00069     /* Get WDT oscillator settings */
00070     clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
00071     div = reg & 0x1F;
00072 
00073     /* Compute clock rate and divided by divde value */
00074     return wdtOSCRate[clk] / ((div + 1) << 1);
00075 }
00076 
00077 /* Compute a PLL frequency */
00078 STATIC uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
00079 {
00080     uint32_t msel = ((PLLReg & 0x1F) + 1);
00081 
00082     return inputRate * msel;
00083 }
00084 
00085 /*****************************************************************************
00086  * Public functions
00087  ****************************************************************************/
00088 
00089 /* Set System PLL clock source */
00090 void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
00091 {
00092     LPC_SYSCTL->SYSPLLCLKSEL  = (uint32_t) src;
00093     LPC_SYSCTL->SYSPLLCLKUEN  = 0;
00094     LPC_SYSCTL->SYSPLLCLKUEN  = 1;
00095 }
00096 
00097 /* Bypass System Oscillator and set oscillator frequency range */
00098 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
00099 {
00100     uint32_t ctrl = 0;
00101 
00102     if (bypass) {
00103         ctrl |= (1 << 0);
00104     }
00105     if (highfr) {
00106         ctrl |= (1 << 1);
00107     }
00108 
00109     LPC_SYSCTL->SYSOSCCTRL = ctrl;
00110 }
00111 
00112 #if defined(CHIP_LPC11UXX)
00113 /* Set USB PLL clock source */
00114 void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
00115 {
00116     LPC_SYSCTL->USBPLLCLKSEL  = (uint32_t) src;
00117     LPC_SYSCTL->USBPLLCLKUEN  = 0;
00118     LPC_SYSCTL->USBPLLCLKUEN  = 1;
00119 }
00120 
00121 #endif
00122 
00123 /* Set main system clock source */
00124 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
00125 {
00126     LPC_SYSCTL->MAINCLKSEL  = (uint32_t) src;
00127     LPC_SYSCTL->MAINCLKUEN  = 0;
00128     LPC_SYSCTL->MAINCLKUEN  = 1;
00129 }
00130 
00131 #if defined(CHIP_LPC11UXX)
00132 /* Set USB clock source and divider */
00133 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
00134 {
00135     LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
00136     LPC_SYSCTL->USBCLKUEN = 0;
00137     LPC_SYSCTL->USBCLKUEN = 1;
00138     LPC_SYSCTL->USBCLKDIV = div;
00139 }
00140 
00141 #endif /*CHIP_LPC11UXX*/
00142 
00143 #if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC1125)
00144 /* Set WDT clock source and divider */
00145 void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div)
00146 {
00147     LPC_SYSCTL->WDTCLKSEL = (uint32_t) src;
00148     LPC_SYSCTL->WDTCLKUEN = 0;
00149     LPC_SYSCTL->WDTCLKUEN = 1;
00150     LPC_SYSCTL->WDTCLKDIV = div;
00151 }
00152 
00153 #endif
00154 
00155 #if !defined(CHIP_LPC110X)
00156 /* Set CLKOUT clock source and divider */
00157 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
00158 {
00159     LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
00160     LPC_SYSCTL->CLKOUTUEN = 0;
00161     LPC_SYSCTL->CLKOUTUEN = 1;
00162     LPC_SYSCTL->CLKOUTDIV = div;
00163 }
00164 
00165 #endif
00166 
00167 /* Return estimated watchdog oscillator rate */
00168 uint32_t Chip_Clock_GetWDTOSCRate(void)
00169 {
00170     return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL);
00171 }
00172 
00173 #if defined(CHIP_LPC11AXX)
00174 /* Return estimated low frequency oscillator rate */
00175 uint32_t Chip_Clock_GetLFOOSCRate(void)
00176 {
00177     return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->LFOSCCTRL);
00178 }
00179 
00180 #endif
00181 
00182 /* Return System PLL input clock rate */
00183 uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
00184 {
00185     uint32_t clkRate;
00186 
00187     switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
00188     case SYSCTL_PLLCLKSRC_IRC :
00189         clkRate = Chip_Clock_GetIntOscRate();
00190         break;
00191 
00192     case SYSCTL_PLLCLKSRC_MAINOSC :
00193         clkRate = Chip_Clock_GetMainOscRate();
00194         break;
00195 
00196 #if defined(CHIP_LPC11AXX)
00197     case SYSCTL_PLLCLKSRC_EXT_CLKIN :
00198         clkRate = Chip_Clock_GetExtClockInRate();
00199         break;
00200 #endif
00201 
00202     default:
00203         clkRate = 0;
00204     }
00205 
00206     return clkRate;
00207 }
00208 
00209 /* Return System PLL output clock rate */
00210 uint32_t Chip_Clock_GetSystemPLLOutClockRate(void)
00211 {
00212     return Chip_Clock_GetPLLFreq(LPC_SYSCTL->SYSPLLCTRL,
00213                                  Chip_Clock_GetSystemPLLInClockRate());
00214 }
00215 
00216 #if defined(CHIP_LPC11UXX)
00217 /* Return USB PLL input clock rate */
00218 uint32_t Chip_Clock_GetUSBPLLInClockRate(void)
00219 {
00220     uint32_t clkRate;
00221 
00222     switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->USBPLLCLKSEL & 0x3)) {
00223     case SYSCTL_PLLCLKSRC_IRC :
00224         clkRate = Chip_Clock_GetIntOscRate();
00225         break;
00226 
00227     case SYSCTL_PLLCLKSRC_MAINOSC :
00228         clkRate = Chip_Clock_GetMainOscRate();
00229         break;
00230 
00231     default:
00232         clkRate = 0;
00233     }
00234 
00235     return clkRate;
00236 }
00237 
00238 /* Return USB PLL output clock rate */
00239 uint32_t Chip_Clock_GetUSBPLLOutClockRate(void)
00240 {
00241     return Chip_Clock_GetPLLFreq(LPC_SYSCTL->USBPLLCTRL,
00242                                  Chip_Clock_GetUSBPLLInClockRate());
00243 }
00244 
00245 #endif
00246 
00247 /* Return main clock rate */
00248 uint32_t Chip_Clock_GetMainClockRate(void)
00249 {
00250     uint32_t clkRate = 0;
00251 
00252     switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
00253     case SYSCTL_MAINCLKSRC_IRC :
00254         clkRate = Chip_Clock_GetIntOscRate();
00255         break;
00256 
00257     case SYSCTL_MAINCLKSRC_PLLIN :
00258         clkRate = Chip_Clock_GetSystemPLLInClockRate();
00259         break;
00260 
00261 #if defined(CHIP_LPC11AXX)
00262     case SYSCTL_MAINCLKSRC_LFOSC :
00263         clkRate = Chip_Clock_GetLFOOSCRate();
00264         break;
00265 
00266 #else
00267     case SYSCTL_MAINCLKSRC_WDTOSC :
00268         clkRate = Chip_Clock_GetWDTOSCRate();
00269         break;
00270 #endif
00271 
00272     case SYSCTL_MAINCLKSRC_PLLOUT :
00273         clkRate = Chip_Clock_GetSystemPLLOutClockRate();
00274         break;
00275     }
00276 
00277     return clkRate;
00278 }
00279 
00280 /* Return system clock rate */
00281 uint32_t Chip_Clock_GetSystemClockRate(void)
00282 {
00283     /* No point in checking for divide by 0 */
00284     return Chip_Clock_GetMainClockRate() / LPC_SYSCTL->SYSAHBCLKDIV;
00285 }