bxcan.hpp

00001 /*
00002  * Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com>
00003  * Bit definitions were copied from NuttX STM32 CAN driver.
00004  */
00005 
00006 #pragma once
00007 
00008 #include <uavcan_stm32/build_config.hpp>
00009 
00010 #include <uavcan/uavcan.hpp>
00011 #include <stdint.h>
00012 
00013 #ifndef UAVCAN_CPP_VERSION
00014 # error UAVCAN_CPP_VERSION
00015 #endif
00016 
00017 #if UAVCAN_CPP_VERSION < UAVCAN_CPP11
00018 // #undef'ed at the end of this file
00019 # define constexpr const
00020 #endif
00021 
00022 namespace uavcan_stm32
00023 {
00024 namespace bxcan
00025 {
00026 
00027 struct TxMailboxType
00028 {
00029     volatile uint32_t TIR;
00030     volatile uint32_t TDTR;
00031     volatile uint32_t TDLR;
00032     volatile uint32_t TDHR;
00033 };
00034 
00035 struct RxMailboxType
00036 {
00037     volatile uint32_t RIR;
00038     volatile uint32_t RDTR;
00039     volatile uint32_t RDLR;
00040     volatile uint32_t RDHR;
00041 };
00042 
00043 struct FilterRegisterType
00044 {
00045     volatile uint32_t FR1;
00046     volatile uint32_t FR2;
00047 };
00048 
00049 struct CanType
00050 {
00051     volatile uint32_t  MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
00052     volatile uint32_t  MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
00053     volatile uint32_t  TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
00054     volatile uint32_t  RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
00055     volatile uint32_t  RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
00056     volatile uint32_t  IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
00057     volatile uint32_t  ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
00058     volatile uint32_t  BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
00059     uint32_t           RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
00060     TxMailboxType      TxMailbox[3];        /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
00061     RxMailboxType      RxMailbox[2];        /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
00062     uint32_t           RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
00063     volatile uint32_t  FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
00064     volatile uint32_t  FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
00065     uint32_t           RESERVED2;           /*!< Reserved, 0x208                                                    */
00066     volatile uint32_t  FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
00067     uint32_t           RESERVED3;           /*!< Reserved, 0x210                                                    */
00068     volatile uint32_t  FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
00069     uint32_t           RESERVED4;           /*!< Reserved, 0x218                                                    */
00070     volatile uint32_t  FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
00071     uint32_t           RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
00072     FilterRegisterType FilterRegister[28];  /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
00073 };
00074 
00075 /**
00076  * CANx register sets
00077  */
00078 CanType* const Can[UAVCAN_STM32_NUM_IFACES] =
00079 {
00080     reinterpret_cast<CanType*>(0x40006400)
00081 #if UAVCAN_STM32_NUM_IFACES > 1
00082     ,
00083     reinterpret_cast<CanType*>(0x40006800)
00084 #endif
00085 };
00086 
00087 /* CAN master control register */
00088 
00089 constexpr unsigned long MCR_INRQ =            (1U << 0); /* Bit 0: Initialization Request */
00090 constexpr unsigned long MCR_SLEEP =           (1U << 1); /* Bit 1: Sleep Mode Request */
00091 constexpr unsigned long MCR_TXFP =            (1U << 2); /* Bit 2: Transmit FIFO Priority */
00092 constexpr unsigned long MCR_RFLM =            (1U << 3); /* Bit 3: Receive FIFO Locked Mode */
00093 constexpr unsigned long MCR_NART =            (1U << 4); /* Bit 4: No Automatic Retransmission */
00094 constexpr unsigned long MCR_AWUM =            (1U << 5); /* Bit 5: Automatic Wakeup Mode */
00095 constexpr unsigned long MCR_ABOM =            (1U << 6); /* Bit 6: Automatic Bus-Off Management */
00096 constexpr unsigned long MCR_TTCM =            (1U << 7); /* Bit 7: Time Triggered Communication Mode Enable */
00097 constexpr unsigned long MCR_RESET =           (1U << 15);/* Bit 15: bxCAN software master reset */
00098 constexpr unsigned long MCR_DBF =             (1U << 16);/* Bit 16: Debug freeze */
00099 
00100 /* CAN master status register */
00101 
00102 constexpr unsigned long MSR_INAK =            (1U << 0); /* Bit 0: Initialization Acknowledge */
00103 constexpr unsigned long MSR_SLAK =            (1U << 1); /* Bit 1: Sleep Acknowledge */
00104 constexpr unsigned long MSR_ERRI =            (1U << 2); /* Bit 2: Error Interrupt */
00105 constexpr unsigned long MSR_WKUI =            (1U << 3); /* Bit 3: Wakeup Interrupt */
00106 constexpr unsigned long MSR_SLAKI =           (1U << 4); /* Bit 4: Sleep acknowledge interrupt */
00107 constexpr unsigned long MSR_TXM =             (1U << 8); /* Bit 8: Transmit Mode */
00108 constexpr unsigned long MSR_RXM =             (1U << 9); /* Bit 9: Receive Mode */
00109 constexpr unsigned long MSR_SAMP =            (1U << 10);/* Bit 10: Last Sample Point */
00110 constexpr unsigned long MSR_RX =              (1U << 11);/* Bit 11: CAN Rx Signal */
00111 
00112 /* CAN transmit status register */
00113 
00114 constexpr unsigned long TSR_RQCP0 =           (1U << 0); /* Bit 0: Request Completed Mailbox 0 */
00115 constexpr unsigned long TSR_TXOK0 =           (1U << 1); /* Bit 1 : Transmission OK of Mailbox 0 */
00116 constexpr unsigned long TSR_ALST0 =           (1U << 2); /* Bit 2 : Arbitration Lost for Mailbox 0 */
00117 constexpr unsigned long TSR_TERR0 =           (1U << 3); /* Bit 3 : Transmission Error of Mailbox 0 */
00118 constexpr unsigned long TSR_ABRQ0 =           (1U << 7); /* Bit 7 : Abort Request for Mailbox 0 */
00119 constexpr unsigned long TSR_RQCP1 =           (1U << 8); /* Bit 8 : Request Completed Mailbox 1 */
00120 constexpr unsigned long TSR_TXOK1 =           (1U << 9); /* Bit 9 : Transmission OK of Mailbox 1 */
00121 constexpr unsigned long TSR_ALST1 =           (1U << 10);/* Bit 10 : Arbitration Lost for Mailbox 1 */
00122 constexpr unsigned long TSR_TERR1 =           (1U << 11);/* Bit 11 : Transmission Error of Mailbox 1 */
00123 constexpr unsigned long TSR_ABRQ1 =           (1U << 15);/* Bit 15 : Abort Request for Mailbox 1 */
00124 constexpr unsigned long TSR_RQCP2 =           (1U << 16);/* Bit 16 : Request Completed Mailbox 2 */
00125 constexpr unsigned long TSR_TXOK2 =           (1U << 17);/* Bit 17 : Transmission OK of Mailbox 2 */
00126 constexpr unsigned long TSR_ALST2 =           (1U << 18);/* Bit 18: Arbitration Lost for Mailbox 2 */
00127 constexpr unsigned long TSR_TERR2 =           (1U << 19);/* Bit 19: Transmission Error of Mailbox 2 */
00128 constexpr unsigned long TSR_ABRQ2 =           (1U << 23);/* Bit 23: Abort Request for Mailbox 2 */
00129 constexpr unsigned long TSR_CODE_SHIFT =      (24U);     /* Bits 25-24: Mailbox Code */
00130 constexpr unsigned long TSR_CODE_MASK =       (3U << TSR_CODE_SHIFT);
00131 constexpr unsigned long TSR_TME0 =            (1U << 26);/* Bit 26: Transmit Mailbox 0 Empty */
00132 constexpr unsigned long TSR_TME1 =            (1U << 27);/* Bit 27: Transmit Mailbox 1 Empty */
00133 constexpr unsigned long TSR_TME2 =            (1U << 28);/* Bit 28: Transmit Mailbox 2 Empty */
00134 constexpr unsigned long TSR_LOW0 =            (1U << 29);/* Bit 29: Lowest Priority Flag for Mailbox 0 */
00135 constexpr unsigned long TSR_LOW1 =            (1U << 30);/* Bit 30: Lowest Priority Flag for Mailbox 1 */
00136 constexpr unsigned long TSR_LOW2 =            (1U << 31);/* Bit 31: Lowest Priority Flag for Mailbox 2 */
00137 
00138 /* CAN receive FIFO 0/1 registers */
00139 
00140 constexpr unsigned long RFR_FMP_SHIFT =       (0U);      /* Bits 1-0: FIFO Message Pending */
00141 constexpr unsigned long RFR_FMP_MASK =        (3U << RFR_FMP_SHIFT);
00142 constexpr unsigned long RFR_FULL =            (1U << 3); /* Bit 3: FIFO 0 Full */
00143 constexpr unsigned long RFR_FOVR =            (1U << 4); /* Bit 4: FIFO 0 Overrun */
00144 constexpr unsigned long RFR_RFOM =            (1U << 5); /* Bit 5: Release FIFO 0 Output Mailbox */
00145 
00146 /* CAN interrupt enable register */
00147 
00148 constexpr unsigned long IER_TMEIE =           (1U << 0); /* Bit 0: Transmit Mailbox Empty Interrupt Enable */
00149 constexpr unsigned long IER_FMPIE0 =          (1U << 1); /* Bit 1: FIFO Message Pending Interrupt Enable */
00150 constexpr unsigned long IER_FFIE0 =           (1U << 2); /* Bit 2: FIFO Full Interrupt Enable */
00151 constexpr unsigned long IER_FOVIE0 =          (1U << 3); /* Bit 3: FIFO Overrun Interrupt Enable */
00152 constexpr unsigned long IER_FMPIE1 =          (1U << 4); /* Bit 4: FIFO Message Pending Interrupt Enable */
00153 constexpr unsigned long IER_FFIE1 =           (1U << 5); /* Bit 5: FIFO Full Interrupt Enable */
00154 constexpr unsigned long IER_FOVIE1 =          (1U << 6); /* Bit 6: FIFO Overrun Interrupt Enable */
00155 constexpr unsigned long IER_EWGIE =           (1U << 8); /* Bit 8: Error Warning Interrupt Enable */
00156 constexpr unsigned long IER_EPVIE =           (1U << 9); /* Bit 9: Error Passive Interrupt Enable */
00157 constexpr unsigned long IER_BOFIE =           (1U << 10);/* Bit 10: Bus-Off Interrupt Enable */
00158 constexpr unsigned long IER_LECIE =           (1U << 11);/* Bit 11: Last Error Code Interrupt Enable */
00159 constexpr unsigned long IER_ERRIE =           (1U << 15);/* Bit 15: Error Interrupt Enable */
00160 constexpr unsigned long IER_WKUIE =           (1U << 16);/* Bit 16: Wakeup Interrupt Enable */
00161 constexpr unsigned long IER_SLKIE =           (1U << 17);/* Bit 17: Sleep Interrupt Enable */
00162 
00163 /* CAN error status register */
00164 
00165 constexpr unsigned long ESR_EWGF =            (1U << 0); /* Bit 0: Error Warning Flag */
00166 constexpr unsigned long ESR_EPVF =            (1U << 1); /* Bit 1: Error Passive Flag */
00167 constexpr unsigned long ESR_BOFF =            (1U << 2); /* Bit 2: Bus-Off Flag */
00168 constexpr unsigned long ESR_LEC_SHIFT =       (4U);      /* Bits 6-4: Last Error Code */
00169 constexpr unsigned long ESR_LEC_MASK =        (7U << ESR_LEC_SHIFT);
00170 constexpr unsigned long ESR_NOERROR =         (0U << ESR_LEC_SHIFT);/* 000: No Error */
00171 constexpr unsigned long ESR_STUFFERROR =      (1U << ESR_LEC_SHIFT);/* 001: Stuff Error */
00172 constexpr unsigned long ESR_FORMERROR =       (2U << ESR_LEC_SHIFT);/* 010: Form Error */
00173 constexpr unsigned long ESR_ACKERROR =        (3U << ESR_LEC_SHIFT);/* 011: Acknowledgment Error */
00174 constexpr unsigned long ESR_BRECERROR =       (4U << ESR_LEC_SHIFT);/* 100: Bit recessive Error */
00175 constexpr unsigned long ESR_BDOMERROR =       (5U << ESR_LEC_SHIFT);/* 101: Bit dominant Error */
00176 constexpr unsigned long ESR_CRCERRPR =        (6U << ESR_LEC_SHIFT);/* 110: CRC Error */
00177 constexpr unsigned long ESR_SWERROR =         (7U << ESR_LEC_SHIFT);/* 111: Set by software */
00178 constexpr unsigned long ESR_TEC_SHIFT =       (16U);     /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */
00179 constexpr unsigned long ESR_TEC_MASK =        (0xFFU << ESR_TEC_SHIFT);
00180 constexpr unsigned long ESR_REC_SHIFT =       (24U);     /* Bits 31-24: Receive Error Counter */
00181 constexpr unsigned long ESR_REC_MASK =        (0xFFU << ESR_REC_SHIFT);
00182 
00183 /* CAN bit timing register */
00184 
00185 constexpr unsigned long BTR_BRP_SHIFT =       (0U);      /* Bits 9-0: Baud Rate Prescaler */
00186 constexpr unsigned long BTR_BRP_MASK =        (0x03FFU << BTR_BRP_SHIFT);
00187 constexpr unsigned long BTR_TS1_SHIFT =       (16U);     /* Bits 19-16: Time Segment 1 */
00188 constexpr unsigned long BTR_TS1_MASK =        (0x0FU <<  BTR_TS1_SHIFT);
00189 constexpr unsigned long BTR_TS2_SHIFT =       (20U);     /* Bits 22-20: Time Segment 2 */
00190 constexpr unsigned long BTR_TS2_MASK =        (7U << BTR_TS2_SHIFT);
00191 constexpr unsigned long BTR_SJW_SHIFT =       (24U);     /* Bits 25-24: Resynchronization Jump Width */
00192 constexpr unsigned long BTR_SJW_MASK =        (3U << BTR_SJW_SHIFT);
00193 constexpr unsigned long BTR_LBKM =            (1U << 30);/* Bit 30: Loop Back Mode (Debug);*/
00194 constexpr unsigned long BTR_SILM =            (1U << 31);/* Bit 31: Silent Mode (Debug);*/
00195 
00196 constexpr unsigned long BTR_BRP_MAX =         (1024U);   /* Maximum BTR value (without decrement);*/
00197 constexpr unsigned long BTR_TSEG1_MAX =       (16U);     /* Maximum TSEG1 value (without decrement);*/
00198 constexpr unsigned long BTR_TSEG2_MAX =       (8U);      /* Maximum TSEG2 value (without decrement);*/
00199 
00200 /* TX mailbox identifier register */
00201 
00202 constexpr unsigned long TIR_TXRQ =            (1U << 0); /* Bit 0: Transmit Mailbox Request */
00203 constexpr unsigned long TIR_RTR =             (1U << 1); /* Bit 1: Remote Transmission Request */
00204 constexpr unsigned long TIR_IDE =             (1U << 2); /* Bit 2: Identifier Extension */
00205 constexpr unsigned long TIR_EXID_SHIFT =      (3U);      /* Bit 3-31: Extended Identifier */
00206 constexpr unsigned long TIR_EXID_MASK =       (0x1FFFFFFFU << TIR_EXID_SHIFT);
00207 constexpr unsigned long TIR_STID_SHIFT =      (21U);     /* Bits 21-31: Standard Identifier */
00208 constexpr unsigned long TIR_STID_MASK =       (0x07FFU << TIR_STID_SHIFT);
00209 
00210 /* Mailbox data length control and time stamp register */
00211 
00212 constexpr unsigned long TDTR_DLC_SHIFT =      (0U);      /* Bits 3:0: Data Length Code */
00213 constexpr unsigned long TDTR_DLC_MASK =       (0x0FU << TDTR_DLC_SHIFT);
00214 constexpr unsigned long TDTR_TGT =            (1U << 8); /* Bit 8: Transmit Global Time */
00215 constexpr unsigned long TDTR_TIME_SHIFT =     (16U);     /* Bits 31:16: Message Time Stamp */
00216 constexpr unsigned long TDTR_TIME_MASK =      (0xFFFFU << TDTR_TIME_SHIFT);
00217 
00218 /* Mailbox data low register */
00219 
00220 constexpr unsigned long TDLR_DATA0_SHIFT =    (0U);      /* Bits 7-0: Data Byte 0 */
00221 constexpr unsigned long TDLR_DATA0_MASK =     (0xFFU << TDLR_DATA0_SHIFT);
00222 constexpr unsigned long TDLR_DATA1_SHIFT =    (8U);      /* Bits 15-8: Data Byte 1 */
00223 constexpr unsigned long TDLR_DATA1_MASK =     (0xFFU << TDLR_DATA1_SHIFT);
00224 constexpr unsigned long TDLR_DATA2_SHIFT =    (16U);     /* Bits 23-16: Data Byte 2 */
00225 constexpr unsigned long TDLR_DATA2_MASK =     (0xFFU << TDLR_DATA2_SHIFT);
00226 constexpr unsigned long TDLR_DATA3_SHIFT =    (24U);     /* Bits 31-24: Data Byte 3 */
00227 constexpr unsigned long TDLR_DATA3_MASK =     (0xFFU << TDLR_DATA3_SHIFT);
00228 
00229 /* Mailbox data high register */
00230 
00231 constexpr unsigned long TDHR_DATA4_SHIFT =    (0U);      /* Bits 7-0: Data Byte 4 */
00232 constexpr unsigned long TDHR_DATA4_MASK =     (0xFFU << TDHR_DATA4_SHIFT);
00233 constexpr unsigned long TDHR_DATA5_SHIFT =    (8U);      /* Bits 15-8: Data Byte 5 */
00234 constexpr unsigned long TDHR_DATA5_MASK =     (0xFFU << TDHR_DATA5_SHIFT);
00235 constexpr unsigned long TDHR_DATA6_SHIFT =    (16U);     /* Bits 23-16: Data Byte 6 */
00236 constexpr unsigned long TDHR_DATA6_MASK =     (0xFFU << TDHR_DATA6_SHIFT);
00237 constexpr unsigned long TDHR_DATA7_SHIFT =    (24U);     /* Bits 31-24: Data Byte 7 */
00238 constexpr unsigned long TDHR_DATA7_MASK =     (0xFFU << TDHR_DATA7_SHIFT);
00239 
00240 /* Rx FIFO mailbox identifier register */
00241 
00242 constexpr unsigned long RIR_RTR =             (1U << 1); /* Bit 1: Remote Transmission Request */
00243 constexpr unsigned long RIR_IDE =             (1U << 2); /* Bit 2: Identifier Extension */
00244 constexpr unsigned long RIR_EXID_SHIFT =      (3U);      /* Bit 3-31: Extended Identifier */
00245 constexpr unsigned long RIR_EXID_MASK =       (0x1FFFFFFFU << RIR_EXID_SHIFT);
00246 constexpr unsigned long RIR_STID_SHIFT =      (21U);     /* Bits 21-31: Standard Identifier */
00247 constexpr unsigned long RIR_STID_MASK =       (0x07FFU << RIR_STID_SHIFT);
00248 
00249 /* Receive FIFO mailbox data length control and time stamp register */
00250 
00251 constexpr unsigned long RDTR_DLC_SHIFT =      (0U);      /* Bits 3:0: Data Length Code */
00252 constexpr unsigned long RDTR_DLC_MASK =       (0x0FU << RDTR_DLC_SHIFT);
00253 constexpr unsigned long RDTR_FM_SHIFT =       (8U);      /* Bits 15-8: Filter Match Index */
00254 constexpr unsigned long RDTR_FM_MASK =        (0xFFU << RDTR_FM_SHIFT);
00255 constexpr unsigned long RDTR_TIME_SHIFT =     (16U);     /* Bits 31:16: Message Time Stamp */
00256 constexpr unsigned long RDTR_TIME_MASK =      (0xFFFFU << RDTR_TIME_SHIFT);
00257 
00258 /* Receive FIFO mailbox data low register */
00259 
00260 constexpr unsigned long RDLR_DATA0_SHIFT =    (0U);      /* Bits 7-0: Data Byte 0 */
00261 constexpr unsigned long RDLR_DATA0_MASK =     (0xFFU << RDLR_DATA0_SHIFT);
00262 constexpr unsigned long RDLR_DATA1_SHIFT =    (8U);      /* Bits 15-8: Data Byte 1 */
00263 constexpr unsigned long RDLR_DATA1_MASK =     (0xFFU << RDLR_DATA1_SHIFT);
00264 constexpr unsigned long RDLR_DATA2_SHIFT =    (16U);     /* Bits 23-16: Data Byte 2 */
00265 constexpr unsigned long RDLR_DATA2_MASK =     (0xFFU << RDLR_DATA2_SHIFT);
00266 constexpr unsigned long RDLR_DATA3_SHIFT =    (24U);     /* Bits 31-24: Data Byte 3 */
00267 constexpr unsigned long RDLR_DATA3_MASK =     (0xFFU << RDLR_DATA3_SHIFT);
00268 
00269 /* Receive FIFO mailbox data high register */
00270 
00271 constexpr unsigned long RDHR_DATA4_SHIFT =    (0U);      /* Bits 7-0: Data Byte 4 */
00272 constexpr unsigned long RDHR_DATA4_MASK =     (0xFFU << RDHR_DATA4_SHIFT);
00273 constexpr unsigned long RDHR_DATA5_SHIFT =    (8U);      /* Bits 15-8: Data Byte 5 */
00274 constexpr unsigned long RDHR_DATA5_MASK =     (0xFFU << RDHR_DATA5_SHIFT);
00275 constexpr unsigned long RDHR_DATA6_SHIFT =    (16U);     /* Bits 23-16: Data Byte 6 */
00276 constexpr unsigned long RDHR_DATA6_MASK =     (0xFFU << RDHR_DATA6_SHIFT);
00277 constexpr unsigned long RDHR_DATA7_SHIFT =    (24U);     /* Bits 31-24: Data Byte 7 */
00278 constexpr unsigned long RDHR_DATA7_MASK =     (0xFFU << RDHR_DATA7_SHIFT);
00279 
00280 /* CAN filter master register */
00281 
00282 constexpr unsigned long FMR_FINIT =           (1U << 0); /* Bit 0:  Filter Init Mode */
00283 
00284 }
00285 }
00286 
00287 #if UAVCAN_CPP_VERSION < UAVCAN_CPP11
00288 # undef constexpr
00289 #endif