adc_11xx.h

00001 /*
00002  * @brief  LPC11xx A/D conversion driver (except LPC1125)
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2012
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 #ifndef __ADC_11XX_H_
00033 #define __ADC_11XX_H_
00034 
00035 #if !defined(CHIP_LPC1125)
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /** @defgroup ADC_11XX CHIP:  LPC11xx A/D conversion driver
00042  * @ingroup CHIP_11XX_Drivers
00043  * This ADC driver is for LPC11xx variants except for LPC1125.
00044  * @{
00045  */
00046 
00047 #define ADC_MAX_SAMPLE_RATE 400000
00048 
00049 /**
00050  * @brief 10 or 12-bit ADC register block structure
00051  */
00052 typedef struct {                    /*!< ADCn Structure */
00053     __IO uint32_t CR ;               /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
00054     __I  uint32_t GDR ;              /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
00055     __I  uint32_t RESERVED0;
00056     __IO uint32_t INTEN ;            /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
00057     __I  uint32_t DR[8];            /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
00058     __I  uint32_t STAT ;             /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
00059 } LPC_ADC_T;
00060 
00061 /**
00062  * @brief ADC register support bitfields and mask
00063  */
00064  #define ADC_DR_RESULT(n)        ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */
00065  #define ADC_CR_BITACC(n)        ((((n) & 0x7) << 17))  /*!< Number of ADC accuracy bits */
00066 
00067 #define ADC_DR_DONE(n)          (((n) >> 31))           /*!< Mask for reading the ADC done status */
00068 #define ADC_DR_OVERRUN(n)       ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */
00069 #define ADC_CR_CH_SEL(n)        ((1UL << (n)))          /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
00070 #define ADC_CR_CLKDIV(n)        ((((n) & 0xFF) << 8))   /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
00071 #define ADC_CR_BURST            ((1UL << 16))           /*!< Repeated conversions A/D enable bit */
00072 #define ADC_CR_PDN              ((1UL << 21))           /*!< ADC convert is operational */
00073 #define ADC_CR_START_MASK       ((7UL << 24))           /*!< ADC start mask bits */
00074 #define ADC_CR_START_MODE_SEL(SEL)  ((SEL << 24))       /*!< Select Start Mode */
00075 #define ADC_CR_START_NOW        ((1UL << 24))           /*!< Start conversion now */
00076 #define ADC_CR_START_CTOUT15    ((2UL << 24))           /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
00077 #define ADC_CR_START_CTOUT8     ((3UL << 24))           /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
00078 #define ADC_CR_START_ADCTRIG0   ((4UL << 24))           /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
00079 #define ADC_CR_START_ADCTRIG1   ((5UL << 24))           /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
00080 #define ADC_CR_START_MCOA2      ((6UL << 24))           /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
00081 #define ADC_CR_EDGE             ((1UL << 27))           /*!< Start conversion on a falling edge on the selected CAP/MAT signal */
00082 #define ADC_SAMPLE_RATE_CONFIG_MASK         (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))
00083 
00084 /**
00085  * @brief   ADC status register used for IP drivers
00086  */
00087 typedef enum IP_ADC_STATUS {
00088     ADC_DR_DONE_STAT ,   /*!< ADC data register staus */
00089     ADC_DR_OVERRUN_STAT ,/*!< ADC data overrun staus */
00090     ADC_DR_ADINT_STAT    /*!< ADC interrupt status */
00091 } ADC_STATUS_T;
00092 
00093 /** The channels on one ADC peripheral*/
00094 typedef enum CHIP_ADC_CHANNEL {
00095     ADC_CH0 = 0,    /**< ADC channel 0 */
00096     ADC_CH1,        /**< ADC channel 1 */
00097     ADC_CH2,        /**< ADC channel 2 */
00098     ADC_CH3,        /**< ADC channel 3 */
00099     ADC_CH4,        /**< ADC channel 4 */
00100     ADC_CH5,        /**< ADC channel 5 */
00101     ADC_CH6,        /**< ADC channel 6 */
00102     ADC_CH7,        /**< ADC channel 7 */
00103 } ADC_CHANNEL_T;
00104 
00105 /** The number of bits of accuracy of the result in the LS bits of ADDR*/
00106 typedef enum CHIP_ADC_RESOLUTION {
00107     ADC_10BITS = 0,     /**< ADC 10 bits */
00108     ADC_9BITS,          /**< ADC 9 bits  */
00109     ADC_8BITS,          /**< ADC 8 bits  */
00110     ADC_7BITS,          /**< ADC 7 bits  */
00111     ADC_6BITS,          /**< ADC 6 bits  */
00112     ADC_5BITS,          /**< ADC 5 bits  */
00113     ADC_4BITS,          /**< ADC 4 bits  */
00114     ADC_3BITS,          /**< ADC 3 bits  */
00115 } ADC_RESOLUTION_T;
00116 
00117 /** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
00118 typedef enum CHIP_ADC_EDGE_CFG {
00119     ADC_TRIGGERMODE_RISING = 0,     /**< Trigger event: rising edge */
00120     ADC_TRIGGERMODE_FALLING,        /**< Trigger event: falling edge */
00121 } ADC_EDGE_CFG_T;
00122 
00123 /** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
00124 typedef enum CHIP_ADC_START_MODE {
00125     ADC_NO_START = 0,
00126     ADC_START_NOW ,          /*!< Start conversion now */
00127     ADC_START_ON_CTOUT15 ,   /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
00128     ADC_START_ON_CTOUT8 ,    /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
00129     ADC_START_ON_ADCTRIG0 ,  /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
00130     ADC_START_ON_ADCTRIG1 ,  /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
00131     ADC_START_ON_MCOA2       /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
00132 } ADC_START_MODE_T;
00133 
00134 /** Clock setup structure for ADC controller passed to the initialize function */
00135 typedef struct {
00136     uint32_t adcRate ;       /*!< ADC rate */
00137     uint8_t  bitsAccuracy ;  /*!< ADC bit accuracy */
00138     bool     burstMode ;     /*!< ADC Burt Mode */
00139 } ADC_CLOCK_SETUP_T;
00140 
00141 /**
00142  * @brief   Initialize the ADC peripheral and the ADC setup structure to default value
00143  * @param   pADC        : The base of ADC peripheral on the chip
00144  * @param   ADCSetup    : ADC setup structure to be set
00145  * @return  Nothing
00146  * @note    Default setting for ADC is 400kHz - 10bits
00147  */
00148 void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup);
00149 
00150 /**
00151  * @brief   Shutdown ADC
00152  * @param   pADC    : The base of ADC peripheral on the chip
00153  * @return  Nothing
00154  */
00155 void Chip_ADC_DeInit(LPC_ADC_T *pADC);
00156 
00157 /**
00158  * @brief   Read the ADC value from a channel
00159  * @param   pADC        : The base of ADC peripheral on the chip
00160  * @param   channel     : ADC channel to read
00161  * @param   data        : Pointer to where to put data
00162  * @return  SUCCESS or ERROR if no conversion is ready
00163  */
00164 Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data);
00165 
00166 /**
00167  * @brief   Read the ADC value and convert it to 8bits value
00168  * @param   pADC        : The base of ADC peripheral on the chip
00169  * @param   channel:    selected channel
00170  * @param   data        : Storage for data
00171  * @return  Status  : ERROR or SUCCESS
00172  */
00173 Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data);
00174 
00175 /**
00176  * @brief   Read the ADC channel status
00177  * @param   pADC        : The base of ADC peripheral on the chip
00178  * @param   channel     : ADC channel to read
00179  * @param   StatusType  : Status type of ADC_DR_*
00180  * @return  SET or RESET
00181  */
00182 FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType);
00183 
00184 /**
00185  * @brief   Enable/Disable interrupt for ADC channel
00186  * @param   pADC        : The base of ADC peripheral on the chip
00187  * @param   channel     : ADC channel to read
00188  * @param   NewState    : New state, ENABLE or DISABLE
00189  * @return  SET or RESET
00190  */
00191 void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState);
00192 
00193 /**
00194  * @brief   Enable/Disable global interrupt for ADC channel
00195  * @param   pADC        : The base of ADC peripheral on the chip
00196  * @param   NewState    : New state, ENABLE or DISABLE
00197  * @return  Nothing
00198  */
00199 STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState)
00200 {
00201     Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState);
00202 }
00203 
00204 /**
00205  * @brief   Select the mode starting the AD conversion
00206  * @param   pADC        : The base of ADC peripheral on the chip
00207  * @param   mode        : Stating mode, should be :
00208  *                          - ADC_NO_START              : Must be set for Burst mode
00209  *                          - ADC_START_NOW             : Start conversion now
00210  *                          - ADC_START_ON_CTOUT15      : Start conversion when the edge selected by bit 27 occurs on CTOUT_15
00211  *                          - ADC_START_ON_CTOUT8       : Start conversion when the edge selected by bit 27 occurs on CTOUT_8
00212  *                          - ADC_START_ON_ADCTRIG0     : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
00213  *                          - ADC_START_ON_ADCTRIG1     : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
00214  *                          - ADC_START_ON_MCOA2        : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
00215  * @param   EdgeOption  : Stating Edge Condition, should be :
00216  *                          - ADC_TRIGGERMODE_RISING    : Trigger event on rising edge
00217  *                          - ADC_TRIGGERMODE_FALLING   : Trigger event on falling edge
00218  * @return  Nothing
00219  */
00220 void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption);
00221 
00222 /**
00223  * @brief   Set the ADC Sample rate
00224  * @param   pADC        : The base of ADC peripheral on the chip
00225  * @param   ADCSetup    : ADC setup structure to be modified
00226  * @param   rate        : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
00227  * @return  Nothing
00228  */
00229 void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate);
00230 
00231 /**
00232  * @brief   Set the ADC accuracy bits
00233  * @param   pADC        : The base of ADC peripheral on the chip
00234  * @param   ADCSetup    : ADC setup structure to be modified
00235  * @param   resolution  : The resolution, should be ADC_10BITS -> ADC_3BITS
00236  * @return  Nothing
00237  */
00238 void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution);
00239 
00240 /**
00241  * @brief   Enable or disable the ADC channel on ADC peripheral
00242  * @param   pADC        : The base of ADC peripheral on the chip
00243  * @param   channel     : Channel to be enable or disable
00244  * @param   NewState    : New state, should be:
00245  *                              - ENABLE
00246  *                              - DISABLE
00247  * @return  Nothing
00248  */
00249 void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState);
00250 
00251 /**
00252  * @brief   Enable burst mode
00253  * @param   pADC        : The base of ADC peripheral on the chip
00254  * @param   NewState    : New state, should be:
00255  *                          - ENABLE
00256  *                          - DISABLE
00257  * @return  Nothing
00258  */
00259 void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState);
00260 
00261 /**
00262  * @}
00263  */
00264 
00265 #ifdef __cplusplus
00266 }
00267 #endif
00268 
00269 #endif /* !defined(CHIP_LPC1125) */
00270 
00271 #endif /* __ADC_11XX_H_ */