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targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL27Z/drivers/fsl_clock.h@0:f269e3021894, 2016-10-23 (annotated)
- Committer:
- elessair
- Date:
- Sun Oct 23 15:10:02 2016 +0000
- Revision:
- 0:f269e3021894
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| elessair | 0:f269e3021894 | 1 | /* |
| elessair | 0:f269e3021894 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| elessair | 0:f269e3021894 | 3 | * All rights reserved. |
| elessair | 0:f269e3021894 | 4 | * |
| elessair | 0:f269e3021894 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| elessair | 0:f269e3021894 | 6 | * are permitted provided that the following conditions are met: |
| elessair | 0:f269e3021894 | 7 | * |
| elessair | 0:f269e3021894 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| elessair | 0:f269e3021894 | 9 | * of conditions and the following disclaimer. |
| elessair | 0:f269e3021894 | 10 | * |
| elessair | 0:f269e3021894 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| elessair | 0:f269e3021894 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| elessair | 0:f269e3021894 | 13 | * other materials provided with the distribution. |
| elessair | 0:f269e3021894 | 14 | * |
| elessair | 0:f269e3021894 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| elessair | 0:f269e3021894 | 16 | * contributors may be used to endorse or promote products derived from this |
| elessair | 0:f269e3021894 | 17 | * software without specific prior written permission. |
| elessair | 0:f269e3021894 | 18 | * |
| elessair | 0:f269e3021894 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| elessair | 0:f269e3021894 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| elessair | 0:f269e3021894 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| elessair | 0:f269e3021894 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| elessair | 0:f269e3021894 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| elessair | 0:f269e3021894 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| elessair | 0:f269e3021894 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| elessair | 0:f269e3021894 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| elessair | 0:f269e3021894 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| elessair | 0:f269e3021894 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| elessair | 0:f269e3021894 | 29 | */ |
| elessair | 0:f269e3021894 | 30 | |
| elessair | 0:f269e3021894 | 31 | #ifndef _FSL_CLOCK_H_ |
| elessair | 0:f269e3021894 | 32 | #define _FSL_CLOCK_H_ |
| elessair | 0:f269e3021894 | 33 | |
| elessair | 0:f269e3021894 | 34 | #include "fsl_device_registers.h" |
| elessair | 0:f269e3021894 | 35 | #include <stdint.h> |
| elessair | 0:f269e3021894 | 36 | #include <stdbool.h> |
| elessair | 0:f269e3021894 | 37 | #include <assert.h> |
| elessair | 0:f269e3021894 | 38 | |
| elessair | 0:f269e3021894 | 39 | /*! @addtogroup clock */ |
| elessair | 0:f269e3021894 | 40 | /*! @{ */ |
| elessair | 0:f269e3021894 | 41 | |
| elessair | 0:f269e3021894 | 42 | /******************************************************************************* |
| elessair | 0:f269e3021894 | 43 | * Definitions |
| elessair | 0:f269e3021894 | 44 | ******************************************************************************/ |
| elessair | 0:f269e3021894 | 45 | |
| elessair | 0:f269e3021894 | 46 | /*! @brief Clock driver version. */ |
| elessair | 0:f269e3021894 | 47 | #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ |
| elessair | 0:f269e3021894 | 48 | |
| elessair | 0:f269e3021894 | 49 | /*! @brief External XTAL0 (OSC0) clock frequency. |
| elessair | 0:f269e3021894 | 50 | * |
| elessair | 0:f269e3021894 | 51 | * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the |
| elessair | 0:f269e3021894 | 52 | * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example, |
| elessair | 0:f269e3021894 | 53 | * if XTAL0 is 8MHz, |
| elessair | 0:f269e3021894 | 54 | * @code |
| elessair | 0:f269e3021894 | 55 | * CLOCK_InitOsc0(...); // Setup the OSC0 |
| elessair | 0:f269e3021894 | 56 | * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver. |
| elessair | 0:f269e3021894 | 57 | * @endcode |
| elessair | 0:f269e3021894 | 58 | * |
| elessair | 0:f269e3021894 | 59 | * This is important for the multicore platforms, only one core needs to setup |
| elessair | 0:f269e3021894 | 60 | * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq |
| elessair | 0:f269e3021894 | 61 | * to get valid clock frequency. |
| elessair | 0:f269e3021894 | 62 | */ |
| elessair | 0:f269e3021894 | 63 | extern uint32_t g_xtal0Freq; |
| elessair | 0:f269e3021894 | 64 | |
| elessair | 0:f269e3021894 | 65 | /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. |
| elessair | 0:f269e3021894 | 66 | * |
| elessair | 0:f269e3021894 | 67 | * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the |
| elessair | 0:f269e3021894 | 68 | * function CLOCK_SetXtal32Freq to set the value in to clock driver. |
| elessair | 0:f269e3021894 | 69 | * |
| elessair | 0:f269e3021894 | 70 | * This is important for the multicore platforms, only one core needs to setup |
| elessair | 0:f269e3021894 | 71 | * the clock, all other cores need to call CLOCK_SetXtal32Freq |
| elessair | 0:f269e3021894 | 72 | * to get valid clock frequency. |
| elessair | 0:f269e3021894 | 73 | */ |
| elessair | 0:f269e3021894 | 74 | extern uint32_t g_xtal32Freq; |
| elessair | 0:f269e3021894 | 75 | |
| elessair | 0:f269e3021894 | 76 | /*! @brief Clock ip name array for DMAMUX. */ |
| elessair | 0:f269e3021894 | 77 | #define DMAMUX_CLOCKS \ |
| elessair | 0:f269e3021894 | 78 | { \ |
| elessair | 0:f269e3021894 | 79 | kCLOCK_Dmamux0 \ |
| elessair | 0:f269e3021894 | 80 | } |
| elessair | 0:f269e3021894 | 81 | |
| elessair | 0:f269e3021894 | 82 | /*! @brief Clock ip name array for RTC. */ |
| elessair | 0:f269e3021894 | 83 | #define RTC_CLOCKS \ |
| elessair | 0:f269e3021894 | 84 | { \ |
| elessair | 0:f269e3021894 | 85 | kCLOCK_Rtc0 \ |
| elessair | 0:f269e3021894 | 86 | } |
| elessair | 0:f269e3021894 | 87 | |
| elessair | 0:f269e3021894 | 88 | /*! @brief Clock ip name array for SPI. */ |
| elessair | 0:f269e3021894 | 89 | #define SPI_CLOCKS \ |
| elessair | 0:f269e3021894 | 90 | { \ |
| elessair | 0:f269e3021894 | 91 | kCLOCK_Spi0, kCLOCK_Spi1 \ |
| elessair | 0:f269e3021894 | 92 | } |
| elessair | 0:f269e3021894 | 93 | |
| elessair | 0:f269e3021894 | 94 | /*! @brief Clock ip name array for PIT. */ |
| elessair | 0:f269e3021894 | 95 | #define PIT_CLOCKS \ |
| elessair | 0:f269e3021894 | 96 | { \ |
| elessair | 0:f269e3021894 | 97 | kCLOCK_Pit0 \ |
| elessair | 0:f269e3021894 | 98 | } |
| elessair | 0:f269e3021894 | 99 | |
| elessair | 0:f269e3021894 | 100 | /*! @brief Clock ip name array for PORT. */ |
| elessair | 0:f269e3021894 | 101 | #define PORT_CLOCKS \ |
| elessair | 0:f269e3021894 | 102 | { \ |
| elessair | 0:f269e3021894 | 103 | kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ |
| elessair | 0:f269e3021894 | 104 | } |
| elessair | 0:f269e3021894 | 105 | |
| elessair | 0:f269e3021894 | 106 | /*! @brief Clock ip name array for LPUART. */ |
| elessair | 0:f269e3021894 | 107 | #define LPUART_CLOCKS \ |
| elessair | 0:f269e3021894 | 108 | { \ |
| elessair | 0:f269e3021894 | 109 | kCLOCK_Lpuart0, kCLOCK_Lpuart1 \ |
| elessair | 0:f269e3021894 | 110 | } |
| elessair | 0:f269e3021894 | 111 | |
| elessair | 0:f269e3021894 | 112 | /*! @brief Clock ip name array for LPTMR. */ |
| elessair | 0:f269e3021894 | 113 | #define LPTMR_CLOCKS \ |
| elessair | 0:f269e3021894 | 114 | { \ |
| elessair | 0:f269e3021894 | 115 | kCLOCK_Lptmr0 \ |
| elessair | 0:f269e3021894 | 116 | } |
| elessair | 0:f269e3021894 | 117 | |
| elessair | 0:f269e3021894 | 118 | /*! @brief Clock ip name array for ADC16. */ |
| elessair | 0:f269e3021894 | 119 | #define ADC16_CLOCKS \ |
| elessair | 0:f269e3021894 | 120 | { \ |
| elessair | 0:f269e3021894 | 121 | kCLOCK_Adc0 \ |
| elessair | 0:f269e3021894 | 122 | } |
| elessair | 0:f269e3021894 | 123 | |
| elessair | 0:f269e3021894 | 124 | /*! @brief Clock ip name array for FLEXIO. */ |
| elessair | 0:f269e3021894 | 125 | #define FLEXIO_CLOCKS \ |
| elessair | 0:f269e3021894 | 126 | { \ |
| elessair | 0:f269e3021894 | 127 | kCLOCK_Flexio0 \ |
| elessair | 0:f269e3021894 | 128 | } |
| elessair | 0:f269e3021894 | 129 | |
| elessair | 0:f269e3021894 | 130 | /*! @brief Clock ip name array for VREF. */ |
| elessair | 0:f269e3021894 | 131 | #define VREF_CLOCKS \ |
| elessair | 0:f269e3021894 | 132 | { \ |
| elessair | 0:f269e3021894 | 133 | kCLOCK_Vref0 \ |
| elessair | 0:f269e3021894 | 134 | } |
| elessair | 0:f269e3021894 | 135 | |
| elessair | 0:f269e3021894 | 136 | /*! @brief Clock ip name array for DMA. */ |
| elessair | 0:f269e3021894 | 137 | #define DMA_CLOCKS \ |
| elessair | 0:f269e3021894 | 138 | { \ |
| elessair | 0:f269e3021894 | 139 | kCLOCK_Dma0 \ |
| elessair | 0:f269e3021894 | 140 | } |
| elessair | 0:f269e3021894 | 141 | |
| elessair | 0:f269e3021894 | 142 | /*! @brief Clock ip name array for UART. */ |
| elessair | 0:f269e3021894 | 143 | #define UART_CLOCKS \ |
| elessair | 0:f269e3021894 | 144 | { \ |
| elessair | 0:f269e3021894 | 145 | kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Uart2 \ |
| elessair | 0:f269e3021894 | 146 | } |
| elessair | 0:f269e3021894 | 147 | |
| elessair | 0:f269e3021894 | 148 | /*! @brief Clock ip name array for TPM. */ |
| elessair | 0:f269e3021894 | 149 | #define TPM_CLOCKS \ |
| elessair | 0:f269e3021894 | 150 | { \ |
| elessair | 0:f269e3021894 | 151 | kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \ |
| elessair | 0:f269e3021894 | 152 | } |
| elessair | 0:f269e3021894 | 153 | |
| elessair | 0:f269e3021894 | 154 | /*! @brief Clock ip name array for CRC. */ |
| elessair | 0:f269e3021894 | 155 | #define CRC_CLOCKS \ |
| elessair | 0:f269e3021894 | 156 | { \ |
| elessair | 0:f269e3021894 | 157 | kCLOCK_Crc0 \ |
| elessair | 0:f269e3021894 | 158 | } |
| elessair | 0:f269e3021894 | 159 | |
| elessair | 0:f269e3021894 | 160 | /*! @brief Clock ip name array for I2C. */ |
| elessair | 0:f269e3021894 | 161 | #define I2C_CLOCKS \ |
| elessair | 0:f269e3021894 | 162 | { \ |
| elessair | 0:f269e3021894 | 163 | kCLOCK_I2c0, kCLOCK_I2c1 \ |
| elessair | 0:f269e3021894 | 164 | } |
| elessair | 0:f269e3021894 | 165 | |
| elessair | 0:f269e3021894 | 166 | /*! @brief Clock ip name array for FTF. */ |
| elessair | 0:f269e3021894 | 167 | #define FTF_CLOCKS \ |
| elessair | 0:f269e3021894 | 168 | { \ |
| elessair | 0:f269e3021894 | 169 | kCLOCK_Ftf0 \ |
| elessair | 0:f269e3021894 | 170 | } |
| elessair | 0:f269e3021894 | 171 | |
| elessair | 0:f269e3021894 | 172 | /*! @brief Clock ip name array for CMP. */ |
| elessair | 0:f269e3021894 | 173 | #define CMP_CLOCKS \ |
| elessair | 0:f269e3021894 | 174 | { \ |
| elessair | 0:f269e3021894 | 175 | kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \ |
| elessair | 0:f269e3021894 | 176 | } |
| elessair | 0:f269e3021894 | 177 | |
| elessair | 0:f269e3021894 | 178 | /*! |
| elessair | 0:f269e3021894 | 179 | * @brief LPO clock frequency. |
| elessair | 0:f269e3021894 | 180 | */ |
| elessair | 0:f269e3021894 | 181 | #define LPO_CLK_FREQ 1000U |
| elessair | 0:f269e3021894 | 182 | |
| elessair | 0:f269e3021894 | 183 | /*! @brief Peripherals clock source definition. */ |
| elessair | 0:f269e3021894 | 184 | #define SYS_CLK kCLOCK_CoreSysClk |
| elessair | 0:f269e3021894 | 185 | #define BUS_CLK kCLOCK_BusClk |
| elessair | 0:f269e3021894 | 186 | |
| elessair | 0:f269e3021894 | 187 | #define I2C0_CLK_SRC SYS_CLK |
| elessair | 0:f269e3021894 | 188 | #define I2C1_CLK_SRC SYS_CLK |
| elessair | 0:f269e3021894 | 189 | #define SPI0_CLK_SRC BUS_CLK |
| elessair | 0:f269e3021894 | 190 | #define SPI1_CLK_SRC SYS_CLK |
| elessair | 0:f269e3021894 | 191 | #define UART2_CLK_SRC BUS_CLK |
| elessair | 0:f269e3021894 | 192 | |
| elessair | 0:f269e3021894 | 193 | /*! @brief Clock name used to get clock frequency. */ |
| elessair | 0:f269e3021894 | 194 | typedef enum _clock_name |
| elessair | 0:f269e3021894 | 195 | { |
| elessair | 0:f269e3021894 | 196 | |
| elessair | 0:f269e3021894 | 197 | /* ----------------------------- System layer clock -------------------------------*/ |
| elessair | 0:f269e3021894 | 198 | kCLOCK_CoreSysClk, /*!< Core/system clock */ |
| elessair | 0:f269e3021894 | 199 | kCLOCK_PlatClk, /*!< Platform clock */ |
| elessair | 0:f269e3021894 | 200 | kCLOCK_BusClk, /*!< Bus clock */ |
| elessair | 0:f269e3021894 | 201 | kCLOCK_FlexBusClk, /*!< FlexBus clock */ |
| elessair | 0:f269e3021894 | 202 | kCLOCK_FlashClk, /*!< Flash clock */ |
| elessair | 0:f269e3021894 | 203 | kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */ |
| elessair | 0:f269e3021894 | 204 | kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */ |
| elessair | 0:f269e3021894 | 205 | |
| elessair | 0:f269e3021894 | 206 | /* ---------------------------------- OSC clock -----------------------------------*/ |
| elessair | 0:f269e3021894 | 207 | kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ |
| elessair | 0:f269e3021894 | 208 | kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ |
| elessair | 0:f269e3021894 | 209 | kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */ |
| elessair | 0:f269e3021894 | 210 | kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */ |
| elessair | 0:f269e3021894 | 211 | |
| elessair | 0:f269e3021894 | 212 | /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ |
| elessair | 0:f269e3021894 | 213 | kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ |
| elessair | 0:f269e3021894 | 214 | kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ |
| elessair | 0:f269e3021894 | 215 | kCLOCK_McgFllClk, /*!< MCGFLLCLK */ |
| elessair | 0:f269e3021894 | 216 | kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */ |
| elessair | 0:f269e3021894 | 217 | kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */ |
| elessair | 0:f269e3021894 | 218 | kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */ |
| elessair | 0:f269e3021894 | 219 | kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ |
| elessair | 0:f269e3021894 | 220 | kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */ |
| elessair | 0:f269e3021894 | 221 | |
| elessair | 0:f269e3021894 | 222 | /* --------------------------------- Other clock ----------------------------------*/ |
| elessair | 0:f269e3021894 | 223 | kCLOCK_LpoClk, /*!< LPO clock */ |
| elessair | 0:f269e3021894 | 224 | |
| elessair | 0:f269e3021894 | 225 | } clock_name_t; |
| elessair | 0:f269e3021894 | 226 | |
| elessair | 0:f269e3021894 | 227 | /*! @brief USB clock source definition. */ |
| elessair | 0:f269e3021894 | 228 | typedef enum _clock_usb_src |
| elessair | 0:f269e3021894 | 229 | { |
| elessair | 0:f269e3021894 | 230 | kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U), /*!< Use IRC48M. */ |
| elessair | 0:f269e3021894 | 231 | kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ |
| elessair | 0:f269e3021894 | 232 | } clock_usb_src_t; |
| elessair | 0:f269e3021894 | 233 | /*------------------------------------------------------------------------------ |
| elessair | 0:f269e3021894 | 234 | |
| elessair | 0:f269e3021894 | 235 | clock_gate_t definition: |
| elessair | 0:f269e3021894 | 236 | |
| elessair | 0:f269e3021894 | 237 | 31 16 0 |
| elessair | 0:f269e3021894 | 238 | ----------------------------------------------------------------- |
| elessair | 0:f269e3021894 | 239 | | SIM_SCGC register offset | control bit offset in SCGC | |
| elessair | 0:f269e3021894 | 240 | ----------------------------------------------------------------- |
| elessair | 0:f269e3021894 | 241 | |
| elessair | 0:f269e3021894 | 242 | For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the |
| elessair | 0:f269e3021894 | 243 | SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as |
| elessair | 0:f269e3021894 | 244 | |
| elessair | 0:f269e3021894 | 245 | kCLOCK_GateSdhc0 = (0x1030 << 16) | 17; |
| elessair | 0:f269e3021894 | 246 | |
| elessair | 0:f269e3021894 | 247 | ------------------------------------------------------------------------------*/ |
| elessair | 0:f269e3021894 | 248 | |
| elessair | 0:f269e3021894 | 249 | #define CLK_GATE_REG_OFFSET_SHIFT 16U |
| elessair | 0:f269e3021894 | 250 | #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U |
| elessair | 0:f269e3021894 | 251 | #define CLK_GATE_BIT_SHIFT_SHIFT 0U |
| elessair | 0:f269e3021894 | 252 | #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU |
| elessair | 0:f269e3021894 | 253 | |
| elessair | 0:f269e3021894 | 254 | #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ |
| elessair | 0:f269e3021894 | 255 | ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ |
| elessair | 0:f269e3021894 | 256 | (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) |
| elessair | 0:f269e3021894 | 257 | |
| elessair | 0:f269e3021894 | 258 | #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) |
| elessair | 0:f269e3021894 | 259 | #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) |
| elessair | 0:f269e3021894 | 260 | |
| elessair | 0:f269e3021894 | 261 | /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ |
| elessair | 0:f269e3021894 | 262 | typedef enum _clock_ip_name |
| elessair | 0:f269e3021894 | 263 | { |
| elessair | 0:f269e3021894 | 264 | kCLOCK_IpInvalid = 0U, |
| elessair | 0:f269e3021894 | 265 | kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), |
| elessair | 0:f269e3021894 | 266 | kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), |
| elessair | 0:f269e3021894 | 267 | kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U), |
| elessair | 0:f269e3021894 | 268 | kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), |
| elessair | 0:f269e3021894 | 269 | kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), |
| elessair | 0:f269e3021894 | 270 | kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), |
| elessair | 0:f269e3021894 | 271 | kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U), |
| elessair | 0:f269e3021894 | 272 | kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), |
| elessair | 0:f269e3021894 | 273 | kCLOCK_Spi0 = CLK_GATE_DEFINE(0x1034U, 22U), |
| elessair | 0:f269e3021894 | 274 | kCLOCK_Spi1 = CLK_GATE_DEFINE(0x1034U, 23U), |
| elessair | 0:f269e3021894 | 275 | |
| elessair | 0:f269e3021894 | 276 | kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), |
| elessair | 0:f269e3021894 | 277 | kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), |
| elessair | 0:f269e3021894 | 278 | kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), |
| elessair | 0:f269e3021894 | 279 | kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), |
| elessair | 0:f269e3021894 | 280 | kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), |
| elessair | 0:f269e3021894 | 281 | kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), |
| elessair | 0:f269e3021894 | 282 | kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U), |
| elessair | 0:f269e3021894 | 283 | kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x1038U, 21U), |
| elessair | 0:f269e3021894 | 284 | kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x1038U, 31U), |
| elessair | 0:f269e3021894 | 285 | |
| elessair | 0:f269e3021894 | 286 | kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), |
| elessair | 0:f269e3021894 | 287 | kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), |
| elessair | 0:f269e3021894 | 288 | kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), |
| elessair | 0:f269e3021894 | 289 | kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), |
| elessair | 0:f269e3021894 | 290 | kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U), |
| elessair | 0:f269e3021894 | 291 | kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U), |
| elessair | 0:f269e3021894 | 292 | kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U), |
| elessair | 0:f269e3021894 | 293 | kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), |
| elessair | 0:f269e3021894 | 294 | kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), |
| elessair | 0:f269e3021894 | 295 | |
| elessair | 0:f269e3021894 | 296 | kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U), |
| elessair | 0:f269e3021894 | 297 | } clock_ip_name_t; |
| elessair | 0:f269e3021894 | 298 | |
| elessair | 0:f269e3021894 | 299 | /*!@brief SIM configuration structure for clock setting. */ |
| elessair | 0:f269e3021894 | 300 | typedef struct _sim_clock_config |
| elessair | 0:f269e3021894 | 301 | { |
| elessair | 0:f269e3021894 | 302 | uint8_t er32kSrc; /*!< ERCLK32K source selection. */ |
| elessair | 0:f269e3021894 | 303 | uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ |
| elessair | 0:f269e3021894 | 304 | } sim_clock_config_t; |
| elessair | 0:f269e3021894 | 305 | |
| elessair | 0:f269e3021894 | 306 | /*! @brief Oscillator capacitor load setting.*/ |
| elessair | 0:f269e3021894 | 307 | enum _osc_cap_load |
| elessair | 0:f269e3021894 | 308 | { |
| elessair | 0:f269e3021894 | 309 | kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ |
| elessair | 0:f269e3021894 | 310 | kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ |
| elessair | 0:f269e3021894 | 311 | kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ |
| elessair | 0:f269e3021894 | 312 | kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ |
| elessair | 0:f269e3021894 | 313 | }; |
| elessair | 0:f269e3021894 | 314 | |
| elessair | 0:f269e3021894 | 315 | /*! @brief OSCERCLK enable mode. */ |
| elessair | 0:f269e3021894 | 316 | enum _oscer_enable_mode |
| elessair | 0:f269e3021894 | 317 | { |
| elessair | 0:f269e3021894 | 318 | kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ |
| elessair | 0:f269e3021894 | 319 | kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ |
| elessair | 0:f269e3021894 | 320 | }; |
| elessair | 0:f269e3021894 | 321 | |
| elessair | 0:f269e3021894 | 322 | /*! @brief OSC configuration for OSCERCLK. */ |
| elessair | 0:f269e3021894 | 323 | typedef struct _oscer_config |
| elessair | 0:f269e3021894 | 324 | { |
| elessair | 0:f269e3021894 | 325 | uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of \ref _oscer_enable_mode. */ |
| elessair | 0:f269e3021894 | 326 | |
| elessair | 0:f269e3021894 | 327 | } oscer_config_t; |
| elessair | 0:f269e3021894 | 328 | |
| elessair | 0:f269e3021894 | 329 | /*! @brief OSC work mode. */ |
| elessair | 0:f269e3021894 | 330 | typedef enum _osc_mode |
| elessair | 0:f269e3021894 | 331 | { |
| elessair | 0:f269e3021894 | 332 | kOSC_ModeExt = 0U, /*!< Use external clock. */ |
| elessair | 0:f269e3021894 | 333 | kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ |
| elessair | 0:f269e3021894 | 334 | kOSC_ModeOscHighGain = MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ |
| elessair | 0:f269e3021894 | 335 | } osc_mode_t; |
| elessair | 0:f269e3021894 | 336 | |
| elessair | 0:f269e3021894 | 337 | /*! |
| elessair | 0:f269e3021894 | 338 | * @brief OSC Initialization Configuration Structure |
| elessair | 0:f269e3021894 | 339 | * |
| elessair | 0:f269e3021894 | 340 | * Defines the configuration data structure to initialize the OSC. |
| elessair | 0:f269e3021894 | 341 | * When porting to a new board, set the following members |
| elessair | 0:f269e3021894 | 342 | * according to board settings: |
| elessair | 0:f269e3021894 | 343 | * 1. freq: The external frequency. |
| elessair | 0:f269e3021894 | 344 | * 2. workMode: The OSC module mode. |
| elessair | 0:f269e3021894 | 345 | */ |
| elessair | 0:f269e3021894 | 346 | typedef struct _osc_config |
| elessair | 0:f269e3021894 | 347 | { |
| elessair | 0:f269e3021894 | 348 | uint32_t freq; /*!< External clock frequency. */ |
| elessair | 0:f269e3021894 | 349 | uint8_t capLoad; /*!< Capacitor load setting. */ |
| elessair | 0:f269e3021894 | 350 | osc_mode_t workMode; /*!< OSC work mode setting. */ |
| elessair | 0:f269e3021894 | 351 | oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */ |
| elessair | 0:f269e3021894 | 352 | } osc_config_t; |
| elessair | 0:f269e3021894 | 353 | |
| elessair | 0:f269e3021894 | 354 | /*! @brief MCG_Lite clock source selection. */ |
| elessair | 0:f269e3021894 | 355 | typedef enum _mcglite_clkout_src |
| elessair | 0:f269e3021894 | 356 | { |
| elessair | 0:f269e3021894 | 357 | kMCGLITE_ClkSrcHirc, /*!< MCGOUTCLK source is HIRC */ |
| elessair | 0:f269e3021894 | 358 | kMCGLITE_ClkSrcLirc, /*!< MCGOUTCLK source is LIRC */ |
| elessair | 0:f269e3021894 | 359 | kMCGLITE_ClkSrcExt, /*!< MCGOUTCLK source is external clock source */ |
| elessair | 0:f269e3021894 | 360 | kMCGLITE_ClkSrcReserved |
| elessair | 0:f269e3021894 | 361 | } mcglite_clkout_src_t; |
| elessair | 0:f269e3021894 | 362 | |
| elessair | 0:f269e3021894 | 363 | /*! @brief MCG_Lite LIRC select. */ |
| elessair | 0:f269e3021894 | 364 | typedef enum _mcglite_lirc_mode |
| elessair | 0:f269e3021894 | 365 | { |
| elessair | 0:f269e3021894 | 366 | kMCGLITE_Lirc2M, /*!< Slow internal reference(LIRC) 2MHz clock selected */ |
| elessair | 0:f269e3021894 | 367 | kMCGLITE_Lirc8M, /*!< Slow internal reference(LIRC) 8MHz clock selected */ |
| elessair | 0:f269e3021894 | 368 | } mcglite_lirc_mode_t; |
| elessair | 0:f269e3021894 | 369 | |
| elessair | 0:f269e3021894 | 370 | /*! @brief MCG_Lite divider factor selection for clock source*/ |
| elessair | 0:f269e3021894 | 371 | typedef enum _mcglite_lirc_div |
| elessair | 0:f269e3021894 | 372 | { |
| elessair | 0:f269e3021894 | 373 | kMCGLITE_LircDivBy1 = 0U, /*!< Divider is 1 */ |
| elessair | 0:f269e3021894 | 374 | kMCGLITE_LircDivBy2, /*!< Divider is 2 */ |
| elessair | 0:f269e3021894 | 375 | kMCGLITE_LircDivBy4, /*!< Divider is 4 */ |
| elessair | 0:f269e3021894 | 376 | kMCGLITE_LircDivBy8, /*!< Divider is 8 */ |
| elessair | 0:f269e3021894 | 377 | kMCGLITE_LircDivBy16, /*!< Divider is 16 */ |
| elessair | 0:f269e3021894 | 378 | kMCGLITE_LircDivBy32, /*!< Divider is 32 */ |
| elessair | 0:f269e3021894 | 379 | kMCGLITE_LircDivBy64, /*!< Divider is 64 */ |
| elessair | 0:f269e3021894 | 380 | kMCGLITE_LircDivBy128 /*!< Divider is 128 */ |
| elessair | 0:f269e3021894 | 381 | } mcglite_lirc_div_t; |
| elessair | 0:f269e3021894 | 382 | |
| elessair | 0:f269e3021894 | 383 | /*! @brief MCG_Lite clock mode definitions */ |
| elessair | 0:f269e3021894 | 384 | typedef enum _mcglite_mode |
| elessair | 0:f269e3021894 | 385 | { |
| elessair | 0:f269e3021894 | 386 | kMCGLITE_ModeHirc48M, /*!< Clock mode is HIRC 48 M */ |
| elessair | 0:f269e3021894 | 387 | kMCGLITE_ModeLirc8M, /*!< Clock mode is LIRC 8 M */ |
| elessair | 0:f269e3021894 | 388 | kMCGLITE_ModeLirc2M, /*!< Clock mode is LIRC 2 M */ |
| elessair | 0:f269e3021894 | 389 | kMCGLITE_ModeExt, /*!< Clock mode is EXT */ |
| elessair | 0:f269e3021894 | 390 | kMCGLITE_ModeError /*!< Unknown mode */ |
| elessair | 0:f269e3021894 | 391 | } mcglite_mode_t; |
| elessair | 0:f269e3021894 | 392 | |
| elessair | 0:f269e3021894 | 393 | /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ |
| elessair | 0:f269e3021894 | 394 | enum _mcglite_irclk_enable_mode |
| elessair | 0:f269e3021894 | 395 | { |
| elessair | 0:f269e3021894 | 396 | kMCGLITE_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ |
| elessair | 0:f269e3021894 | 397 | kMCGLITE_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ |
| elessair | 0:f269e3021894 | 398 | }; |
| elessair | 0:f269e3021894 | 399 | |
| elessair | 0:f269e3021894 | 400 | /*! @brief MCG_Lite configure structure for mode change. */ |
| elessair | 0:f269e3021894 | 401 | typedef struct _mcglite_config |
| elessair | 0:f269e3021894 | 402 | { |
| elessair | 0:f269e3021894 | 403 | mcglite_clkout_src_t outSrc; /*!< MCGOUT clock select. */ |
| elessair | 0:f269e3021894 | 404 | uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode, OR'ed value of _mcglite_irclk_enable_mode. */ |
| elessair | 0:f269e3021894 | 405 | mcglite_lirc_mode_t ircs; /*!< MCG_C2[IRCS]. */ |
| elessair | 0:f269e3021894 | 406 | mcglite_lirc_div_t fcrdiv; /*!< MCG_SC[FCRDIV]. */ |
| elessair | 0:f269e3021894 | 407 | mcglite_lirc_div_t lircDiv2; /*!< MCG_MC[LIRC_DIV2]. */ |
| elessair | 0:f269e3021894 | 408 | bool hircEnableInNotHircMode; /*!< HIRC enable when not in HIRC mode. */ |
| elessair | 0:f269e3021894 | 409 | } mcglite_config_t; |
| elessair | 0:f269e3021894 | 410 | |
| elessair | 0:f269e3021894 | 411 | /******************************************************************************* |
| elessair | 0:f269e3021894 | 412 | * API |
| elessair | 0:f269e3021894 | 413 | ******************************************************************************/ |
| elessair | 0:f269e3021894 | 414 | |
| elessair | 0:f269e3021894 | 415 | #if defined(__cplusplus) |
| elessair | 0:f269e3021894 | 416 | extern "C" { |
| elessair | 0:f269e3021894 | 417 | #endif /* __cplusplus */ |
| elessair | 0:f269e3021894 | 418 | |
| elessair | 0:f269e3021894 | 419 | /*! |
| elessair | 0:f269e3021894 | 420 | * @brief Set the XTAL0 frequency based on board setting. |
| elessair | 0:f269e3021894 | 421 | * |
| elessair | 0:f269e3021894 | 422 | * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. |
| elessair | 0:f269e3021894 | 423 | */ |
| elessair | 0:f269e3021894 | 424 | static inline void CLOCK_SetXtal0Freq(uint32_t freq) |
| elessair | 0:f269e3021894 | 425 | { |
| elessair | 0:f269e3021894 | 426 | g_xtal0Freq = freq; |
| elessair | 0:f269e3021894 | 427 | } |
| elessair | 0:f269e3021894 | 428 | |
| elessair | 0:f269e3021894 | 429 | /*! |
| elessair | 0:f269e3021894 | 430 | * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting. |
| elessair | 0:f269e3021894 | 431 | * |
| elessair | 0:f269e3021894 | 432 | * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. |
| elessair | 0:f269e3021894 | 433 | */ |
| elessair | 0:f269e3021894 | 434 | static inline void CLOCK_SetXtal32Freq(uint32_t freq) |
| elessair | 0:f269e3021894 | 435 | { |
| elessair | 0:f269e3021894 | 436 | g_xtal32Freq = freq; |
| elessair | 0:f269e3021894 | 437 | } |
| elessair | 0:f269e3021894 | 438 | |
| elessair | 0:f269e3021894 | 439 | /*! |
| elessair | 0:f269e3021894 | 440 | * @brief Enable the clock for specific IP. |
| elessair | 0:f269e3021894 | 441 | * |
| elessair | 0:f269e3021894 | 442 | * @param name Which clock to enable, see \ref clock_ip_name_t. |
| elessair | 0:f269e3021894 | 443 | */ |
| elessair | 0:f269e3021894 | 444 | static inline void CLOCK_EnableClock(clock_ip_name_t name) |
| elessair | 0:f269e3021894 | 445 | { |
| elessair | 0:f269e3021894 | 446 | uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); |
| elessair | 0:f269e3021894 | 447 | (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); |
| elessair | 0:f269e3021894 | 448 | } |
| elessair | 0:f269e3021894 | 449 | |
| elessair | 0:f269e3021894 | 450 | /*! |
| elessair | 0:f269e3021894 | 451 | * @brief Disable the clock for specific IP. |
| elessair | 0:f269e3021894 | 452 | * |
| elessair | 0:f269e3021894 | 453 | * @param name Which clock to disable, see \ref clock_ip_name_t. |
| elessair | 0:f269e3021894 | 454 | */ |
| elessair | 0:f269e3021894 | 455 | static inline void CLOCK_DisableClock(clock_ip_name_t name) |
| elessair | 0:f269e3021894 | 456 | { |
| elessair | 0:f269e3021894 | 457 | uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); |
| elessair | 0:f269e3021894 | 458 | (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); |
| elessair | 0:f269e3021894 | 459 | } |
| elessair | 0:f269e3021894 | 460 | |
| elessair | 0:f269e3021894 | 461 | /*! |
| elessair | 0:f269e3021894 | 462 | * @brief Set ERCLK32K source. |
| elessair | 0:f269e3021894 | 463 | * |
| elessair | 0:f269e3021894 | 464 | * @param src The value to set ERCLK32K clock source. |
| elessair | 0:f269e3021894 | 465 | */ |
| elessair | 0:f269e3021894 | 466 | static inline void CLOCK_SetEr32kClock(uint32_t src) |
| elessair | 0:f269e3021894 | 467 | { |
| elessair | 0:f269e3021894 | 468 | SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); |
| elessair | 0:f269e3021894 | 469 | } |
| elessair | 0:f269e3021894 | 470 | |
| elessair | 0:f269e3021894 | 471 | /*! |
| elessair | 0:f269e3021894 | 472 | * @brief Set LPUART0 clock source. |
| elessair | 0:f269e3021894 | 473 | * |
| elessair | 0:f269e3021894 | 474 | * @param src The value to set LPUART0 clock source. |
| elessair | 0:f269e3021894 | 475 | */ |
| elessair | 0:f269e3021894 | 476 | static inline void CLOCK_SetLpuart0Clock(uint32_t src) |
| elessair | 0:f269e3021894 | 477 | { |
| elessair | 0:f269e3021894 | 478 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src)); |
| elessair | 0:f269e3021894 | 479 | } |
| elessair | 0:f269e3021894 | 480 | |
| elessair | 0:f269e3021894 | 481 | /*! |
| elessair | 0:f269e3021894 | 482 | * @brief Set LPUART1 clock source. |
| elessair | 0:f269e3021894 | 483 | * |
| elessair | 0:f269e3021894 | 484 | * @param src The value to set LPUART1 clock source. |
| elessair | 0:f269e3021894 | 485 | */ |
| elessair | 0:f269e3021894 | 486 | static inline void CLOCK_SetLpuart1Clock(uint32_t src) |
| elessair | 0:f269e3021894 | 487 | { |
| elessair | 0:f269e3021894 | 488 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) | SIM_SOPT2_LPUART1SRC(src)); |
| elessair | 0:f269e3021894 | 489 | } |
| elessair | 0:f269e3021894 | 490 | |
| elessair | 0:f269e3021894 | 491 | /*! |
| elessair | 0:f269e3021894 | 492 | * @brief Set TPM clock source. |
| elessair | 0:f269e3021894 | 493 | * |
| elessair | 0:f269e3021894 | 494 | * @param src The value to set TPM clock source. |
| elessair | 0:f269e3021894 | 495 | */ |
| elessair | 0:f269e3021894 | 496 | static inline void CLOCK_SetTpmClock(uint32_t src) |
| elessair | 0:f269e3021894 | 497 | { |
| elessair | 0:f269e3021894 | 498 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src)); |
| elessair | 0:f269e3021894 | 499 | } |
| elessair | 0:f269e3021894 | 500 | |
| elessair | 0:f269e3021894 | 501 | /*! |
| elessair | 0:f269e3021894 | 502 | * @brief Set FLEXIO clock source. |
| elessair | 0:f269e3021894 | 503 | * |
| elessair | 0:f269e3021894 | 504 | * @param src The value to set FLEXIO clock source. |
| elessair | 0:f269e3021894 | 505 | */ |
| elessair | 0:f269e3021894 | 506 | static inline void CLOCK_SetFlexio0Clock(uint32_t src) |
| elessair | 0:f269e3021894 | 507 | { |
| elessair | 0:f269e3021894 | 508 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) | SIM_SOPT2_FLEXIOSRC(src)); |
| elessair | 0:f269e3021894 | 509 | } |
| elessair | 0:f269e3021894 | 510 | |
| elessair | 0:f269e3021894 | 511 | /*! @brief Enable USB FS clock. |
| elessair | 0:f269e3021894 | 512 | * |
| elessair | 0:f269e3021894 | 513 | * @param src USB FS clock source. |
| elessair | 0:f269e3021894 | 514 | * @param freq The frequency specified by src. |
| elessair | 0:f269e3021894 | 515 | * @retval true The clock is set successfully. |
| elessair | 0:f269e3021894 | 516 | * @retval false The clock source is invalid to get proper USB FS clock. |
| elessair | 0:f269e3021894 | 517 | */ |
| elessair | 0:f269e3021894 | 518 | bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); |
| elessair | 0:f269e3021894 | 519 | |
| elessair | 0:f269e3021894 | 520 | /*! @brief Disable USB FS clock. |
| elessair | 0:f269e3021894 | 521 | * |
| elessair | 0:f269e3021894 | 522 | * Disable USB FS clock. |
| elessair | 0:f269e3021894 | 523 | */ |
| elessair | 0:f269e3021894 | 524 | static inline void CLOCK_DisableUsbfs0Clock(void) |
| elessair | 0:f269e3021894 | 525 | { |
| elessair | 0:f269e3021894 | 526 | CLOCK_DisableClock(kCLOCK_Usbfs0); |
| elessair | 0:f269e3021894 | 527 | } |
| elessair | 0:f269e3021894 | 528 | |
| elessair | 0:f269e3021894 | 529 | /*! |
| elessair | 0:f269e3021894 | 530 | * @brief Set CLKOUT source. |
| elessair | 0:f269e3021894 | 531 | * |
| elessair | 0:f269e3021894 | 532 | * @param src The value to set CLKOUT source. |
| elessair | 0:f269e3021894 | 533 | */ |
| elessair | 0:f269e3021894 | 534 | static inline void CLOCK_SetClkOutClock(uint32_t src) |
| elessair | 0:f269e3021894 | 535 | { |
| elessair | 0:f269e3021894 | 536 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); |
| elessair | 0:f269e3021894 | 537 | } |
| elessair | 0:f269e3021894 | 538 | |
| elessair | 0:f269e3021894 | 539 | /*! |
| elessair | 0:f269e3021894 | 540 | * @brief Set RTC_CLKOUT source. |
| elessair | 0:f269e3021894 | 541 | * |
| elessair | 0:f269e3021894 | 542 | * @param src The value to set RTC_CLKOUT source. |
| elessair | 0:f269e3021894 | 543 | */ |
| elessair | 0:f269e3021894 | 544 | static inline void CLOCK_SetRtcClkOutClock(uint32_t src) |
| elessair | 0:f269e3021894 | 545 | { |
| elessair | 0:f269e3021894 | 546 | SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); |
| elessair | 0:f269e3021894 | 547 | } |
| elessair | 0:f269e3021894 | 548 | |
| elessair | 0:f269e3021894 | 549 | /*! |
| elessair | 0:f269e3021894 | 550 | * @brief System clock divider |
| elessair | 0:f269e3021894 | 551 | * |
| elessair | 0:f269e3021894 | 552 | * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4]. |
| elessair | 0:f269e3021894 | 553 | * |
| elessair | 0:f269e3021894 | 554 | * @param outdiv1 Clock 1 output divider value. |
| elessair | 0:f269e3021894 | 555 | * |
| elessair | 0:f269e3021894 | 556 | * @param outdiv4 Clock 4 output divider value. |
| elessair | 0:f269e3021894 | 557 | */ |
| elessair | 0:f269e3021894 | 558 | static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4) |
| elessair | 0:f269e3021894 | 559 | { |
| elessair | 0:f269e3021894 | 560 | SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4); |
| elessair | 0:f269e3021894 | 561 | } |
| elessair | 0:f269e3021894 | 562 | |
| elessair | 0:f269e3021894 | 563 | /*! |
| elessair | 0:f269e3021894 | 564 | * @brief Gets the clock frequency for a specific clock name. |
| elessair | 0:f269e3021894 | 565 | * |
| elessair | 0:f269e3021894 | 566 | * This function checks the current clock configurations and then calculates |
| elessair | 0:f269e3021894 | 567 | * the clock frequency for a specific clock name defined in clock_name_t. |
| elessair | 0:f269e3021894 | 568 | * The MCG must be properly configured before using this function. |
| elessair | 0:f269e3021894 | 569 | * |
| elessair | 0:f269e3021894 | 570 | * @param clockName Clock names defined in clock_name_t |
| elessair | 0:f269e3021894 | 571 | * @return Clock frequency value in Hertz |
| elessair | 0:f269e3021894 | 572 | */ |
| elessair | 0:f269e3021894 | 573 | uint32_t CLOCK_GetFreq(clock_name_t clockName); |
| elessair | 0:f269e3021894 | 574 | |
| elessair | 0:f269e3021894 | 575 | /*! |
| elessair | 0:f269e3021894 | 576 | * @brief Get the core clock or system clock frequency. |
| elessair | 0:f269e3021894 | 577 | * |
| elessair | 0:f269e3021894 | 578 | * @return Clock frequency in Hz. |
| elessair | 0:f269e3021894 | 579 | */ |
| elessair | 0:f269e3021894 | 580 | uint32_t CLOCK_GetCoreSysClkFreq(void); |
| elessair | 0:f269e3021894 | 581 | |
| elessair | 0:f269e3021894 | 582 | /*! |
| elessair | 0:f269e3021894 | 583 | * @brief Get the platform clock frequency. |
| elessair | 0:f269e3021894 | 584 | * |
| elessair | 0:f269e3021894 | 585 | * @return Clock frequency in Hz. |
| elessair | 0:f269e3021894 | 586 | */ |
| elessair | 0:f269e3021894 | 587 | uint32_t CLOCK_GetPlatClkFreq(void); |
| elessair | 0:f269e3021894 | 588 | |
| elessair | 0:f269e3021894 | 589 | /*! |
| elessair | 0:f269e3021894 | 590 | * @brief Get the bus clock frequency. |
| elessair | 0:f269e3021894 | 591 | * |
| elessair | 0:f269e3021894 | 592 | * @return Clock frequency in Hz. |
| elessair | 0:f269e3021894 | 593 | */ |
| elessair | 0:f269e3021894 | 594 | uint32_t CLOCK_GetBusClkFreq(void); |
| elessair | 0:f269e3021894 | 595 | |
| elessair | 0:f269e3021894 | 596 | /*! |
| elessair | 0:f269e3021894 | 597 | * @brief Get the flash clock frequency. |
| elessair | 0:f269e3021894 | 598 | * |
| elessair | 0:f269e3021894 | 599 | * @return Clock frequency in Hz. |
| elessair | 0:f269e3021894 | 600 | */ |
| elessair | 0:f269e3021894 | 601 | uint32_t CLOCK_GetFlashClkFreq(void); |
| elessair | 0:f269e3021894 | 602 | |
| elessair | 0:f269e3021894 | 603 | /*! |
| elessair | 0:f269e3021894 | 604 | * @brief Get the external reference 32K clock frequency (ERCLK32K). |
| elessair | 0:f269e3021894 | 605 | * |
| elessair | 0:f269e3021894 | 606 | * @return Clock frequency in Hz. |
| elessair | 0:f269e3021894 | 607 | */ |
| elessair | 0:f269e3021894 | 608 | uint32_t CLOCK_GetEr32kClkFreq(void); |
| elessair | 0:f269e3021894 | 609 | |
| elessair | 0:f269e3021894 | 610 | /*! |
| elessair | 0:f269e3021894 | 611 | * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). |
| elessair | 0:f269e3021894 | 612 | * |
| elessair | 0:f269e3021894 | 613 | * @return Clock frequency in Hz. |
| elessair | 0:f269e3021894 | 614 | */ |
| elessair | 0:f269e3021894 | 615 | uint32_t CLOCK_GetOsc0ErClkFreq(void); |
| elessair | 0:f269e3021894 | 616 | |
| elessair | 0:f269e3021894 | 617 | /*! |
| elessair | 0:f269e3021894 | 618 | * @brief Set the clock configure in SIM module. |
| elessair | 0:f269e3021894 | 619 | * |
| elessair | 0:f269e3021894 | 620 | * This function sets system layer clock settings in SIM module. |
| elessair | 0:f269e3021894 | 621 | * |
| elessair | 0:f269e3021894 | 622 | * @param config Pointer to the configure structure. |
| elessair | 0:f269e3021894 | 623 | */ |
| elessair | 0:f269e3021894 | 624 | void CLOCK_SetSimConfig(sim_clock_config_t const *config); |
| elessair | 0:f269e3021894 | 625 | |
| elessair | 0:f269e3021894 | 626 | /*! |
| elessair | 0:f269e3021894 | 627 | * @brief Set the system clock dividers in SIM to safe value. |
| elessair | 0:f269e3021894 | 628 | * |
| elessair | 0:f269e3021894 | 629 | * The system level clocks (core clock, bus clock, flexbus clock and flash clock) |
| elessair | 0:f269e3021894 | 630 | * must be in allowed ranges. During MCG clock mode switch, the MCG output clock |
| elessair | 0:f269e3021894 | 631 | * changes then the system level clocks may be out of range. This function could |
| elessair | 0:f269e3021894 | 632 | * be used before MCG mode change, to make sure system level clocks are in allowed |
| elessair | 0:f269e3021894 | 633 | * range. |
| elessair | 0:f269e3021894 | 634 | * |
| elessair | 0:f269e3021894 | 635 | * @param config Pointer to the configure structure. |
| elessair | 0:f269e3021894 | 636 | */ |
| elessair | 0:f269e3021894 | 637 | static inline void CLOCK_SetSimSafeDivs(void) |
| elessair | 0:f269e3021894 | 638 | { |
| elessair | 0:f269e3021894 | 639 | SIM->CLKDIV1 = 0x10030000U; |
| elessair | 0:f269e3021894 | 640 | } |
| elessair | 0:f269e3021894 | 641 | |
| elessair | 0:f269e3021894 | 642 | /*! |
| elessair | 0:f269e3021894 | 643 | * @name MCG_Lite clock frequency |
| elessair | 0:f269e3021894 | 644 | * @{ |
| elessair | 0:f269e3021894 | 645 | */ |
| elessair | 0:f269e3021894 | 646 | |
| elessair | 0:f269e3021894 | 647 | /*! |
| elessair | 0:f269e3021894 | 648 | * @brief Gets the MCG_Lite output clock (MCGOUTCLK) frequency. |
| elessair | 0:f269e3021894 | 649 | * |
| elessair | 0:f269e3021894 | 650 | * This function gets the MCG_Lite output clock frequency (Hz) based on the current |
| elessair | 0:f269e3021894 | 651 | * MCG_Lite register value. |
| elessair | 0:f269e3021894 | 652 | * |
| elessair | 0:f269e3021894 | 653 | * @return The frequency of MCGOUTCLK. |
| elessair | 0:f269e3021894 | 654 | */ |
| elessair | 0:f269e3021894 | 655 | uint32_t CLOCK_GetOutClkFreq(void); |
| elessair | 0:f269e3021894 | 656 | |
| elessair | 0:f269e3021894 | 657 | /*! |
| elessair | 0:f269e3021894 | 658 | * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency. |
| elessair | 0:f269e3021894 | 659 | * |
| elessair | 0:f269e3021894 | 660 | * This function gets the MCG_Lite internal reference clock frequency (Hz) based |
| elessair | 0:f269e3021894 | 661 | * on the current MCG register value. |
| elessair | 0:f269e3021894 | 662 | * |
| elessair | 0:f269e3021894 | 663 | * @return The frequency of MCGIRCLK. |
| elessair | 0:f269e3021894 | 664 | */ |
| elessair | 0:f269e3021894 | 665 | uint32_t CLOCK_GetInternalRefClkFreq(void); |
| elessair | 0:f269e3021894 | 666 | |
| elessair | 0:f269e3021894 | 667 | /*! |
| elessair | 0:f269e3021894 | 668 | * @brief Gets the current MCGPCLK frequency. |
| elessair | 0:f269e3021894 | 669 | * |
| elessair | 0:f269e3021894 | 670 | * This function gets the MCGPCLK frequency (Hertz) based on the current MCG_Lite |
| elessair | 0:f269e3021894 | 671 | * register settings. |
| elessair | 0:f269e3021894 | 672 | * |
| elessair | 0:f269e3021894 | 673 | * @return The frequency of MCGPCLK. |
| elessair | 0:f269e3021894 | 674 | */ |
| elessair | 0:f269e3021894 | 675 | uint32_t CLOCK_GetPeriphClkFreq(void); |
| elessair | 0:f269e3021894 | 676 | |
| elessair | 0:f269e3021894 | 677 | /*! @}*/ |
| elessair | 0:f269e3021894 | 678 | |
| elessair | 0:f269e3021894 | 679 | /*! |
| elessair | 0:f269e3021894 | 680 | * @name MCG_Lite mode. |
| elessair | 0:f269e3021894 | 681 | * @{ |
| elessair | 0:f269e3021894 | 682 | */ |
| elessair | 0:f269e3021894 | 683 | |
| elessair | 0:f269e3021894 | 684 | /*! |
| elessair | 0:f269e3021894 | 685 | * @brief Gets the current MCG_Lite mode. |
| elessair | 0:f269e3021894 | 686 | * |
| elessair | 0:f269e3021894 | 687 | * This function checks the MCG_Lite registers and determines the current MCG_Lite mode. |
| elessair | 0:f269e3021894 | 688 | * |
| elessair | 0:f269e3021894 | 689 | * @return Current MCG_Lite mode or error code. |
| elessair | 0:f269e3021894 | 690 | */ |
| elessair | 0:f269e3021894 | 691 | mcglite_mode_t CLOCK_GetMode(void); |
| elessair | 0:f269e3021894 | 692 | |
| elessair | 0:f269e3021894 | 693 | /*! |
| elessair | 0:f269e3021894 | 694 | * @brief Sets the MCG_Lite configuration. |
| elessair | 0:f269e3021894 | 695 | * |
| elessair | 0:f269e3021894 | 696 | * This function configures the MCG_Lite, include output clock source, MCGIRCLK |
| elessair | 0:f269e3021894 | 697 | * setting, HIRC setting and so on, see @ref mcglite_config_t for details. |
| elessair | 0:f269e3021894 | 698 | * |
| elessair | 0:f269e3021894 | 699 | * @param targetConfig Pointer to the target MCG_Lite mode configuration structure. |
| elessair | 0:f269e3021894 | 700 | * @return Error code. |
| elessair | 0:f269e3021894 | 701 | */ |
| elessair | 0:f269e3021894 | 702 | status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig); |
| elessair | 0:f269e3021894 | 703 | |
| elessair | 0:f269e3021894 | 704 | /*! @}*/ |
| elessair | 0:f269e3021894 | 705 | |
| elessair | 0:f269e3021894 | 706 | /*! |
| elessair | 0:f269e3021894 | 707 | * @name OSC configuration |
| elessair | 0:f269e3021894 | 708 | * @{ |
| elessair | 0:f269e3021894 | 709 | */ |
| elessair | 0:f269e3021894 | 710 | |
| elessair | 0:f269e3021894 | 711 | /*! |
| elessair | 0:f269e3021894 | 712 | * @brief Configures the OSC external reference clock (OSCERCLK). |
| elessair | 0:f269e3021894 | 713 | * |
| elessair | 0:f269e3021894 | 714 | * This function configures the OSC external reference clock (OSCERCLK). |
| elessair | 0:f269e3021894 | 715 | * For example, to enable the OSCERCLK in normal mode and stop mode, and also set |
| elessair | 0:f269e3021894 | 716 | * the output divider to 1, as follows: |
| elessair | 0:f269e3021894 | 717 | * |
| elessair | 0:f269e3021894 | 718 | @code |
| elessair | 0:f269e3021894 | 719 | oscer_config_t config = |
| elessair | 0:f269e3021894 | 720 | { |
| elessair | 0:f269e3021894 | 721 | .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, |
| elessair | 0:f269e3021894 | 722 | .erclkDiv = 1U, |
| elessair | 0:f269e3021894 | 723 | }; |
| elessair | 0:f269e3021894 | 724 | |
| elessair | 0:f269e3021894 | 725 | OSC_SetExtRefClkConfig(OSC, &config); |
| elessair | 0:f269e3021894 | 726 | @endcode |
| elessair | 0:f269e3021894 | 727 | * |
| elessair | 0:f269e3021894 | 728 | * @param base OSC peripheral address. |
| elessair | 0:f269e3021894 | 729 | * @param config Pointer to the configuration structure. |
| elessair | 0:f269e3021894 | 730 | */ |
| elessair | 0:f269e3021894 | 731 | static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) |
| elessair | 0:f269e3021894 | 732 | { |
| elessair | 0:f269e3021894 | 733 | uint8_t reg = base->CR; |
| elessair | 0:f269e3021894 | 734 | |
| elessair | 0:f269e3021894 | 735 | reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); |
| elessair | 0:f269e3021894 | 736 | reg |= config->enableMode; |
| elessair | 0:f269e3021894 | 737 | |
| elessair | 0:f269e3021894 | 738 | base->CR = reg; |
| elessair | 0:f269e3021894 | 739 | } |
| elessair | 0:f269e3021894 | 740 | |
| elessair | 0:f269e3021894 | 741 | /*! |
| elessair | 0:f269e3021894 | 742 | * @brief Sets the capacitor load configuration for the oscillator. |
| elessair | 0:f269e3021894 | 743 | * |
| elessair | 0:f269e3021894 | 744 | * This function sets the specified capacitors configuration for the oscillator. |
| elessair | 0:f269e3021894 | 745 | * This should be done in the early system level initialization function call |
| elessair | 0:f269e3021894 | 746 | * based on the system configuration. |
| elessair | 0:f269e3021894 | 747 | * |
| elessair | 0:f269e3021894 | 748 | * @param base OSC peripheral address. |
| elessair | 0:f269e3021894 | 749 | * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. |
| elessair | 0:f269e3021894 | 750 | * |
| elessair | 0:f269e3021894 | 751 | * Example: |
| elessair | 0:f269e3021894 | 752 | @code |
| elessair | 0:f269e3021894 | 753 | // To enable only 2 pF and 8 pF capacitor load, please use like this. |
| elessair | 0:f269e3021894 | 754 | OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); |
| elessair | 0:f269e3021894 | 755 | @endcode |
| elessair | 0:f269e3021894 | 756 | */ |
| elessair | 0:f269e3021894 | 757 | |
| elessair | 0:f269e3021894 | 758 | static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) |
| elessair | 0:f269e3021894 | 759 | { |
| elessair | 0:f269e3021894 | 760 | uint8_t reg = base->CR; |
| elessair | 0:f269e3021894 | 761 | |
| elessair | 0:f269e3021894 | 762 | reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); |
| elessair | 0:f269e3021894 | 763 | reg |= capLoad; |
| elessair | 0:f269e3021894 | 764 | |
| elessair | 0:f269e3021894 | 765 | base->CR = reg; |
| elessair | 0:f269e3021894 | 766 | } |
| elessair | 0:f269e3021894 | 767 | |
| elessair | 0:f269e3021894 | 768 | /*! |
| elessair | 0:f269e3021894 | 769 | * @brief Initialize OSC0. |
| elessair | 0:f269e3021894 | 770 | * |
| elessair | 0:f269e3021894 | 771 | * This function initializes the OSC0 according to the board configuration. |
| elessair | 0:f269e3021894 | 772 | * |
| elessair | 0:f269e3021894 | 773 | * @param config Pointer to the OSC0 configuration structure. |
| elessair | 0:f269e3021894 | 774 | */ |
| elessair | 0:f269e3021894 | 775 | void CLOCK_InitOsc0(osc_config_t const *config); |
| elessair | 0:f269e3021894 | 776 | |
| elessair | 0:f269e3021894 | 777 | /*! |
| elessair | 0:f269e3021894 | 778 | * @brief Deinitializes the OSC0. |
| elessair | 0:f269e3021894 | 779 | * |
| elessair | 0:f269e3021894 | 780 | * This function deinitializes the OSC0. |
| elessair | 0:f269e3021894 | 781 | */ |
| elessair | 0:f269e3021894 | 782 | void CLOCK_DeinitOsc0(void); |
| elessair | 0:f269e3021894 | 783 | |
| elessair | 0:f269e3021894 | 784 | /*! @}*/ |
| elessair | 0:f269e3021894 | 785 | |
| elessair | 0:f269e3021894 | 786 | #if defined(__cplusplus) |
| elessair | 0:f269e3021894 | 787 | } |
| elessair | 0:f269e3021894 | 788 | #endif /* __cplusplus */ |
| elessair | 0:f269e3021894 | 789 | |
| elessair | 0:f269e3021894 | 790 | /*! @} */ |
| elessair | 0:f269e3021894 | 791 | |
| elessair | 0:f269e3021894 | 792 | #endif /* _FSL_CLOCK_H_ */ |