Rizky Ardi Maulana / mbed-os

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targets/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/drivers/fsl_smc.c@1:2b6e8130a0ac, 2018-02-22 (annotated)

Committer:
calmantara186
Date:
Thu Feb 22 14:05:19 2018 +0000
Revision:
1:2b6e8130a0ac
Parent:
0:f269e3021894 
mbed os

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /*
elessair 0:f269e3021894 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
elessair 0:f269e3021894 3 * All rights reserved.
elessair 0:f269e3021894 4 *
elessair 0:f269e3021894 5 * Redistribution and use in source and binary forms, with or without modification,
elessair 0:f269e3021894 6 * are permitted provided that the following conditions are met:
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * o Redistributions of source code must retain the above copyright notice, this list
elessair 0:f269e3021894 9 * of conditions and the following disclaimer.
elessair 0:f269e3021894 10 *
elessair 0:f269e3021894 11 * o Redistributions in binary form must reproduce the above copyright notice, this
elessair 0:f269e3021894 12 * list of conditions and the following disclaimer in the documentation and/or
elessair 0:f269e3021894 13 * other materials provided with the distribution.
elessair 0:f269e3021894 14 *
elessair 0:f269e3021894 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
elessair 0:f269e3021894 16 * contributors may be used to endorse or promote products derived from this
elessair 0:f269e3021894 17 * software without specific prior written permission.
elessair 0:f269e3021894 18 *
elessair 0:f269e3021894 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
elessair 0:f269e3021894 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
elessair 0:f269e3021894 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elessair 0:f269e3021894 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
elessair 0:f269e3021894 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
elessair 0:f269e3021894 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
elessair 0:f269e3021894 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
elessair 0:f269e3021894 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
elessair 0:f269e3021894 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
elessair 0:f269e3021894 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elessair 0:f269e3021894 29 */
elessair 0:f269e3021894 30
elessair 0:f269e3021894 31 #include "fsl_smc.h"
elessair 0:f269e3021894 32
elessair 0:f269e3021894 33 #if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
elessair 0:f269e3021894 34 void SMC_GetParam(SMC_Type *base, smc_param_t *param)
elessair 0:f269e3021894 35 {
elessair 0:f269e3021894 36 uint32_t reg = base->PARAM;
elessair 0:f269e3021894 37 param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK);
elessair 0:f269e3021894 38 param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK);
elessair 0:f269e3021894 39 param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK);
elessair 0:f269e3021894 40 param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK);
elessair 0:f269e3021894 41 }
elessair 0:f269e3021894 42 #endif /* FSL_FEATURE_SMC_HAS_PARAM */
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 status_t SMC_SetPowerModeRun(SMC_Type *base)
elessair 0:f269e3021894 45 {
elessair 0:f269e3021894 46 uint8_t reg;
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 reg = base->PMCTRL;
elessair 0:f269e3021894 49 /* configure Normal RUN mode */
elessair 0:f269e3021894 50 reg &= ~SMC_PMCTRL_RUNM_MASK;
elessair 0:f269e3021894 51 reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
elessair 0:f269e3021894 52 base->PMCTRL = reg;
elessair 0:f269e3021894 53
elessair 0:f269e3021894 54 return kStatus_Success;
elessair 0:f269e3021894 55 }
elessair 0:f269e3021894 56
elessair 0:f269e3021894 57 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
elessair 0:f269e3021894 58 status_t SMC_SetPowerModeHsrun(SMC_Type *base)
elessair 0:f269e3021894 59 {
elessair 0:f269e3021894 60 uint8_t reg;
elessair 0:f269e3021894 61
elessair 0:f269e3021894 62 reg = base->PMCTRL;
elessair 0:f269e3021894 63 /* configure High Speed RUN mode */
elessair 0:f269e3021894 64 reg &= ~SMC_PMCTRL_RUNM_MASK;
elessair 0:f269e3021894 65 reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
elessair 0:f269e3021894 66 base->PMCTRL = reg;
elessair 0:f269e3021894 67
elessair 0:f269e3021894 68 return kStatus_Success;
elessair 0:f269e3021894 69 }
elessair 0:f269e3021894 70 #endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
elessair 0:f269e3021894 71
elessair 0:f269e3021894 72 status_t SMC_SetPowerModeWait(SMC_Type *base)
elessair 0:f269e3021894 73 {
elessair 0:f269e3021894 74 /* configure Normal Wait mode */
elessair 0:f269e3021894 75 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 76 __WFI();
elessair 0:f269e3021894 77
elessair 0:f269e3021894 78 return kStatus_Success;
elessair 0:f269e3021894 79 }
elessair 0:f269e3021894 80
elessair 0:f269e3021894 81 status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
elessair 0:f269e3021894 82 {
elessair 0:f269e3021894 83 uint8_t reg;
elessair 0:f269e3021894 84
elessair 0:f269e3021894 85 #if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO)
elessair 0:f269e3021894 86 /* configure the Partial Stop mode in Noraml Stop mode */
elessair 0:f269e3021894 87 reg = base->STOPCTRL;
elessair 0:f269e3021894 88 reg &= ~SMC_STOPCTRL_PSTOPO_MASK;
elessair 0:f269e3021894 89 reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT);
elessair 0:f269e3021894 90 base->STOPCTRL = reg;
elessair 0:f269e3021894 91 #endif
elessair 0:f269e3021894 92
elessair 0:f269e3021894 93 /* configure Normal Stop mode */
elessair 0:f269e3021894 94 reg = base->PMCTRL;
elessair 0:f269e3021894 95 reg &= ~SMC_PMCTRL_STOPM_MASK;
elessair 0:f269e3021894 96 reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
elessair 0:f269e3021894 97 base->PMCTRL = reg;
elessair 0:f269e3021894 98
elessair 0:f269e3021894 99 /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
elessair 0:f269e3021894 100 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 101
elessair 0:f269e3021894 102 /* read back to make sure the configuration valid before enter stop mode */
elessair 0:f269e3021894 103 (void)base->PMCTRL;
elessair 0:f269e3021894 104 __WFI();
elessair 0:f269e3021894 105
elessair 0:f269e3021894 106 /* check whether the power mode enter Stop mode succeed */
elessair 0:f269e3021894 107 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
elessair 0:f269e3021894 108 {
elessair 0:f269e3021894 109 return kStatus_SMC_StopAbort;
elessair 0:f269e3021894 110 }
elessair 0:f269e3021894 111 else
elessair 0:f269e3021894 112 {
elessair 0:f269e3021894 113 return kStatus_Success;
elessair 0:f269e3021894 114 }
elessair 0:f269e3021894 115 }
elessair 0:f269e3021894 116
elessair 0:f269e3021894 117 status_t SMC_SetPowerModeVlpr(SMC_Type *base
elessair 0:f269e3021894 118 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
elessair 0:f269e3021894 119 ,
elessair 0:f269e3021894 120 bool wakeupMode
elessair 0:f269e3021894 121 #endif
elessair 0:f269e3021894 122 )
elessair 0:f269e3021894 123 {
elessair 0:f269e3021894 124 uint8_t reg;
elessair 0:f269e3021894 125
elessair 0:f269e3021894 126 reg = base->PMCTRL;
elessair 0:f269e3021894 127 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
elessair 0:f269e3021894 128 /* configure whether the system remains in VLP mode on an interrupt */
elessair 0:f269e3021894 129 if (wakeupMode)
elessair 0:f269e3021894 130 {
elessair 0:f269e3021894 131 /* exits to RUN mode on an interrupt */
elessair 0:f269e3021894 132 reg |= SMC_PMCTRL_LPWUI_MASK;
elessair 0:f269e3021894 133 }
elessair 0:f269e3021894 134 else
elessair 0:f269e3021894 135 {
elessair 0:f269e3021894 136 /* remains in VLP mode on an interrupt */
elessair 0:f269e3021894 137 reg &= ~SMC_PMCTRL_LPWUI_MASK;
elessair 0:f269e3021894 138 }
elessair 0:f269e3021894 139 #endif /* FSL_FEATURE_SMC_HAS_LPWUI */
elessair 0:f269e3021894 140
elessair 0:f269e3021894 141 /* configure VLPR mode */
elessair 0:f269e3021894 142 reg &= ~SMC_PMCTRL_RUNM_MASK;
elessair 0:f269e3021894 143 reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
elessair 0:f269e3021894 144 base->PMCTRL = reg;
elessair 0:f269e3021894 145
elessair 0:f269e3021894 146 return kStatus_Success;
elessair 0:f269e3021894 147 }
elessair 0:f269e3021894 148
elessair 0:f269e3021894 149 status_t SMC_SetPowerModeVlpw(SMC_Type *base)
elessair 0:f269e3021894 150 {
elessair 0:f269e3021894 151 /* Power mode transaction to VLPW can only happen in VLPR mode */
elessair 0:f269e3021894 152 if (kSMC_PowerStateVlpr != SMC_GetPowerModeState(base))
elessair 0:f269e3021894 153 {
elessair 0:f269e3021894 154 return kStatus_Fail;
elessair 0:f269e3021894 155 }
elessair 0:f269e3021894 156
elessair 0:f269e3021894 157 /* configure VLPW mode */
elessair 0:f269e3021894 158 /* Set the SLEEPDEEP bit to enable deep sleep mode */
elessair 0:f269e3021894 159 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 160 __WFI();
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 return kStatus_Success;
elessair 0:f269e3021894 163 }
elessair 0:f269e3021894 164
elessair 0:f269e3021894 165 status_t SMC_SetPowerModeVlps(SMC_Type *base)
elessair 0:f269e3021894 166 {
elessair 0:f269e3021894 167 uint8_t reg;
elessair 0:f269e3021894 168
elessair 0:f269e3021894 169 /* configure VLPS mode */
elessair 0:f269e3021894 170 reg = base->PMCTRL;
elessair 0:f269e3021894 171 reg &= ~SMC_PMCTRL_STOPM_MASK;
elessair 0:f269e3021894 172 reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
elessair 0:f269e3021894 173 base->PMCTRL = reg;
elessair 0:f269e3021894 174
elessair 0:f269e3021894 175 /* Set the SLEEPDEEP bit to enable deep sleep mode */
elessair 0:f269e3021894 176 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 177
elessair 0:f269e3021894 178 /* read back to make sure the configuration valid before enter stop mode */
elessair 0:f269e3021894 179 (void)base->PMCTRL;
elessair 0:f269e3021894 180 __WFI();
elessair 0:f269e3021894 181
elessair 0:f269e3021894 182 /* check whether the power mode enter VLPS mode succeed */
elessair 0:f269e3021894 183 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
elessair 0:f269e3021894 184 {
elessair 0:f269e3021894 185 return kStatus_SMC_StopAbort;
elessair 0:f269e3021894 186 }
elessair 0:f269e3021894 187 else
elessair 0:f269e3021894 188 {
elessair 0:f269e3021894 189 return kStatus_Success;
elessair 0:f269e3021894 190 }
elessair 0:f269e3021894 191 }
elessair 0:f269e3021894 192
elessair 0:f269e3021894 193 #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
elessair 0:f269e3021894 194 status_t SMC_SetPowerModeLls(SMC_Type *base
elessair 0:f269e3021894 195 #if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
elessair 0:f269e3021894 196 (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
elessair 0:f269e3021894 197 ,
elessair 0:f269e3021894 198 const smc_power_mode_lls_config_t *config
elessair 0:f269e3021894 199 #endif
elessair 0:f269e3021894 200 )
elessair 0:f269e3021894 201 {
elessair 0:f269e3021894 202 uint8_t reg;
elessair 0:f269e3021894 203
elessair 0:f269e3021894 204 /* configure to LLS mode */
elessair 0:f269e3021894 205 reg = base->PMCTRL;
elessair 0:f269e3021894 206 reg &= ~SMC_PMCTRL_STOPM_MASK;
elessair 0:f269e3021894 207 reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
elessair 0:f269e3021894 208 base->PMCTRL = reg;
elessair 0:f269e3021894 209
elessair 0:f269e3021894 210 /* configure LLS sub-mode*/
elessair 0:f269e3021894 211 #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
elessair 0:f269e3021894 212 reg = base->STOPCTRL;
elessair 0:f269e3021894 213 reg &= ~SMC_STOPCTRL_LLSM_MASK;
elessair 0:f269e3021894 214 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
elessair 0:f269e3021894 215 base->STOPCTRL = reg;
elessair 0:f269e3021894 216 #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
elessair 0:f269e3021894 217
elessair 0:f269e3021894 218 #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
elessair 0:f269e3021894 219 if (config->enableLpoClock)
elessair 0:f269e3021894 220 {
elessair 0:f269e3021894 221 base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
elessair 0:f269e3021894 222 }
elessair 0:f269e3021894 223 else
elessair 0:f269e3021894 224 {
elessair 0:f269e3021894 225 base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
elessair 0:f269e3021894 226 }
elessair 0:f269e3021894 227 #endif /* FSL_FEATURE_SMC_HAS_LPOPO */
elessair 0:f269e3021894 228
elessair 0:f269e3021894 229 /* Set the SLEEPDEEP bit to enable deep sleep mode */
elessair 0:f269e3021894 230 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 231
elessair 0:f269e3021894 232 /* read back to make sure the configuration valid before enter stop mode */
elessair 0:f269e3021894 233 (void)base->PMCTRL;
elessair 0:f269e3021894 234 __WFI();
elessair 0:f269e3021894 235
elessair 0:f269e3021894 236 /* check whether the power mode enter LLS mode succeed */
elessair 0:f269e3021894 237 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
elessair 0:f269e3021894 238 {
elessair 0:f269e3021894 239 return kStatus_SMC_StopAbort;
elessair 0:f269e3021894 240 }
elessair 0:f269e3021894 241 else
elessair 0:f269e3021894 242 {
elessair 0:f269e3021894 243 return kStatus_Success;
elessair 0:f269e3021894 244 }
elessair 0:f269e3021894 245 }
elessair 0:f269e3021894 246 #endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
elessair 0:f269e3021894 247
elessair 0:f269e3021894 248 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
elessair 0:f269e3021894 249 status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config)
elessair 0:f269e3021894 250 {
elessair 0:f269e3021894 251 uint8_t reg;
elessair 0:f269e3021894 252
elessair 0:f269e3021894 253 #if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO)
elessair 0:f269e3021894 254 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \
elessair 0:f269e3021894 255 (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \
elessair 0:f269e3021894 256 (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
elessair 0:f269e3021894 257 if (config->subMode == kSMC_StopSub0)
elessair 0:f269e3021894 258 #endif
elessair 0:f269e3021894 259 {
elessair 0:f269e3021894 260 /* configure whether the Por Detect work in Vlls0 mode */
elessair 0:f269e3021894 261 if (config->enablePorDetectInVlls0)
elessair 0:f269e3021894 262 {
elessair 0:f269e3021894 263 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
elessair 0:f269e3021894 264 base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK;
elessair 0:f269e3021894 265 #else
elessair 0:f269e3021894 266 base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK;
elessair 0:f269e3021894 267 #endif
elessair 0:f269e3021894 268 }
elessair 0:f269e3021894 269 else
elessair 0:f269e3021894 270 {
elessair 0:f269e3021894 271 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
elessair 0:f269e3021894 272 base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK;
elessair 0:f269e3021894 273 #else
elessair 0:f269e3021894 274 base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK;
elessair 0:f269e3021894 275 #endif
elessair 0:f269e3021894 276 }
elessair 0:f269e3021894 277 }
elessair 0:f269e3021894 278 #endif /* FSL_FEATURE_SMC_HAS_PORPO */
elessair 0:f269e3021894 279
elessair 0:f269e3021894 280 #if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION)
elessair 0:f269e3021894 281 else if (config->subMode == kSMC_StopSub2)
elessair 0:f269e3021894 282 {
elessair 0:f269e3021894 283 /* configure whether the Por Detect work in Vlls0 mode */
elessair 0:f269e3021894 284 if (config->enableRam2InVlls2)
elessair 0:f269e3021894 285 {
elessair 0:f269e3021894 286 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
elessair 0:f269e3021894 287 base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK;
elessair 0:f269e3021894 288 #else
elessair 0:f269e3021894 289 base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK;
elessair 0:f269e3021894 290 #endif
elessair 0:f269e3021894 291 }
elessair 0:f269e3021894 292 else
elessair 0:f269e3021894 293 {
elessair 0:f269e3021894 294 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
elessair 0:f269e3021894 295 base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK;
elessair 0:f269e3021894 296 #else
elessair 0:f269e3021894 297 base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK;
elessair 0:f269e3021894 298 #endif
elessair 0:f269e3021894 299 }
elessair 0:f269e3021894 300 }
elessair 0:f269e3021894 301 else
elessair 0:f269e3021894 302 {
elessair 0:f269e3021894 303 }
elessair 0:f269e3021894 304 #endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */
elessair 0:f269e3021894 305
elessair 0:f269e3021894 306 /* configure to VLLS mode */
elessair 0:f269e3021894 307 reg = base->PMCTRL;
elessair 0:f269e3021894 308 reg &= ~SMC_PMCTRL_STOPM_MASK;
elessair 0:f269e3021894 309 reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
elessair 0:f269e3021894 310 base->PMCTRL = reg;
elessair 0:f269e3021894 311
elessair 0:f269e3021894 312 /* configure the VLLS sub-mode */
elessair 0:f269e3021894 313 #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG)
elessair 0:f269e3021894 314 reg = base->VLLSCTRL;
elessair 0:f269e3021894 315 reg &= ~SMC_VLLSCTRL_VLLSM_MASK;
elessair 0:f269e3021894 316 reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT);
elessair 0:f269e3021894 317 base->VLLSCTRL = reg;
elessair 0:f269e3021894 318 #else
elessair 0:f269e3021894 319 #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE)
elessair 0:f269e3021894 320 reg = base->STOPCTRL;
elessair 0:f269e3021894 321 reg &= ~SMC_STOPCTRL_LLSM_MASK;
elessair 0:f269e3021894 322 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT);
elessair 0:f269e3021894 323 base->STOPCTRL = reg;
elessair 0:f269e3021894 324 #else
elessair 0:f269e3021894 325 reg = base->STOPCTRL;
elessair 0:f269e3021894 326 reg &= ~SMC_STOPCTRL_VLLSM_MASK;
elessair 0:f269e3021894 327 reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT);
elessair 0:f269e3021894 328 base->STOPCTRL = reg;
elessair 0:f269e3021894 329 #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */
elessair 0:f269e3021894 330 #endif
elessair 0:f269e3021894 331
elessair 0:f269e3021894 332 #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
elessair 0:f269e3021894 333 if (config->enableLpoClock)
elessair 0:f269e3021894 334 {
elessair 0:f269e3021894 335 base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK;
elessair 0:f269e3021894 336 }
elessair 0:f269e3021894 337 else
elessair 0:f269e3021894 338 {
elessair 0:f269e3021894 339 base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK;
elessair 0:f269e3021894 340 }
elessair 0:f269e3021894 341 #endif /* FSL_FEATURE_SMC_HAS_LPOPO */
elessair 0:f269e3021894 342
elessair 0:f269e3021894 343 /* Set the SLEEPDEEP bit to enable deep sleep mode */
elessair 0:f269e3021894 344 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 345
elessair 0:f269e3021894 346 /* read back to make sure the configuration valid before enter stop mode */
elessair 0:f269e3021894 347 (void)base->PMCTRL;
elessair 0:f269e3021894 348 __WFI();
elessair 0:f269e3021894 349
elessair 0:f269e3021894 350 /* check whether the power mode enter LLS mode succeed */
elessair 0:f269e3021894 351 if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
elessair 0:f269e3021894 352 {
elessair 0:f269e3021894 353 return kStatus_SMC_StopAbort;
elessair 0:f269e3021894 354 }
elessair 0:f269e3021894 355 else
elessair 0:f269e3021894 356 {
elessair 0:f269e3021894 357 return kStatus_Success;
elessair 0:f269e3021894 358 }
elessair 0:f269e3021894 359 }
elessair 0:f269e3021894 360 #endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */