Haoyu Xiong / Mbed 2 deprecated SerialTesting

Testing

Dependencies:   mbed FatFileSystemCpp

USBHostLite/usbhost_lpc17xx.h@0:1855e9b8c2a2, 2020-04-24 (annotated)

Committer:
Richard_Xiong
Date:
Fri Apr 24 01:49:33 2020 +0000
Revision:
0:1855e9b8c2a2
USBTesting

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Richard_Xiong 0:1855e9b8c2a2 1 /*
Richard_Xiong 0:1855e9b8c2a2 2 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 3 * NXP USB Host Stack
Richard_Xiong 0:1855e9b8c2a2 4 *
Richard_Xiong 0:1855e9b8c2a2 5 * (c) Copyright 2008, NXP SemiConductors
Richard_Xiong 0:1855e9b8c2a2 6 * (c) Copyright 2008, OnChip Technologies LLC
Richard_Xiong 0:1855e9b8c2a2 7 * All Rights Reserved
Richard_Xiong 0:1855e9b8c2a2 8 *
Richard_Xiong 0:1855e9b8c2a2 9 * www.nxp.com
Richard_Xiong 0:1855e9b8c2a2 10 * www.onchiptech.com
Richard_Xiong 0:1855e9b8c2a2 11 *
Richard_Xiong 0:1855e9b8c2a2 12 * File : usbhost_lpc17xx.h
Richard_Xiong 0:1855e9b8c2a2 13 * Programmer(s) : Ravikanth.P
Richard_Xiong 0:1855e9b8c2a2 14 * Version :
Richard_Xiong 0:1855e9b8c2a2 15 *
Richard_Xiong 0:1855e9b8c2a2 16 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 17 */
Richard_Xiong 0:1855e9b8c2a2 18
Richard_Xiong 0:1855e9b8c2a2 19 #ifndef USBHOST_LPC17xx_H
Richard_Xiong 0:1855e9b8c2a2 20 #define USBHOST_LPC17xx_H
Richard_Xiong 0:1855e9b8c2a2 21
Richard_Xiong 0:1855e9b8c2a2 22 /*
Richard_Xiong 0:1855e9b8c2a2 23 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 24 * INCLUDE HEADER FILES
Richard_Xiong 0:1855e9b8c2a2 25 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 26 */
Richard_Xiong 0:1855e9b8c2a2 27
Richard_Xiong 0:1855e9b8c2a2 28 #include "usbhost_inc.h"
Richard_Xiong 0:1855e9b8c2a2 29
Richard_Xiong 0:1855e9b8c2a2 30 /*
Richard_Xiong 0:1855e9b8c2a2 31 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 32 * PRINT CONFIGURATION
Richard_Xiong 0:1855e9b8c2a2 33 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 34 */
Richard_Xiong 0:1855e9b8c2a2 35
Richard_Xiong 0:1855e9b8c2a2 36 #define PRINT_ENABLE 1
Richard_Xiong 0:1855e9b8c2a2 37
Richard_Xiong 0:1855e9b8c2a2 38 #if PRINT_ENABLE
Richard_Xiong 0:1855e9b8c2a2 39 #define PRINT_Log(...) printf(__VA_ARGS__)
Richard_Xiong 0:1855e9b8c2a2 40 #define PRINT_Err(rc) printf("ERROR: In %s at Line %u - rc = %d\n", __FUNCTION__, __LINE__, rc)
Richard_Xiong 0:1855e9b8c2a2 41
Richard_Xiong 0:1855e9b8c2a2 42 #else
Richard_Xiong 0:1855e9b8c2a2 43 #define PRINT_Log(...) do {} while(0)
Richard_Xiong 0:1855e9b8c2a2 44 #define PRINT_Err(rc) do {} while(0)
Richard_Xiong 0:1855e9b8c2a2 45
Richard_Xiong 0:1855e9b8c2a2 46 #endif
Richard_Xiong 0:1855e9b8c2a2 47
Richard_Xiong 0:1855e9b8c2a2 48 /*
Richard_Xiong 0:1855e9b8c2a2 49 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 50 * GENERAL DEFINITIONS
Richard_Xiong 0:1855e9b8c2a2 51 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 52 */
Richard_Xiong 0:1855e9b8c2a2 53
Richard_Xiong 0:1855e9b8c2a2 54 #define DESC_LENGTH(x) x[0]
Richard_Xiong 0:1855e9b8c2a2 55 #define DESC_TYPE(x) x[1]
Richard_Xiong 0:1855e9b8c2a2 56
Richard_Xiong 0:1855e9b8c2a2 57
Richard_Xiong 0:1855e9b8c2a2 58 #define HOST_GET_DESCRIPTOR(descType, descIndex, data, length) \
Richard_Xiong 0:1855e9b8c2a2 59 Host_CtrlRecv(USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE, GET_DESCRIPTOR, \
Richard_Xiong 0:1855e9b8c2a2 60 (descType << 8)|(descIndex), 0, length, data)
Richard_Xiong 0:1855e9b8c2a2 61
Richard_Xiong 0:1855e9b8c2a2 62 #define HOST_SET_ADDRESS(new_addr) \
Richard_Xiong 0:1855e9b8c2a2 63 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_ADDRESS, \
Richard_Xiong 0:1855e9b8c2a2 64 new_addr, 0, 0, NULL)
Richard_Xiong 0:1855e9b8c2a2 65
Richard_Xiong 0:1855e9b8c2a2 66 #define USBH_SET_CONFIGURATION(configNum) \
Richard_Xiong 0:1855e9b8c2a2 67 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE, SET_CONFIGURATION, \
Richard_Xiong 0:1855e9b8c2a2 68 configNum, 0, 0, NULL)
Richard_Xiong 0:1855e9b8c2a2 69
Richard_Xiong 0:1855e9b8c2a2 70 #define USBH_SET_INTERFACE(ifNum, altNum) \
Richard_Xiong 0:1855e9b8c2a2 71 Host_CtrlSend(USB_HOST_TO_DEVICE | USB_RECIPIENT_INTERFACE, SET_INTERFACE, \
Richard_Xiong 0:1855e9b8c2a2 72 altNum, ifNum, 0, NULL)
Richard_Xiong 0:1855e9b8c2a2 73
Richard_Xiong 0:1855e9b8c2a2 74 /*
Richard_Xiong 0:1855e9b8c2a2 75 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 76 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
Richard_Xiong 0:1855e9b8c2a2 77 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 78 */
Richard_Xiong 0:1855e9b8c2a2 79
Richard_Xiong 0:1855e9b8c2a2 80 /* ------------------ HcControl Register --------------------- */
Richard_Xiong 0:1855e9b8c2a2 81 #define OR_CONTROL_CLE 0x00000010
Richard_Xiong 0:1855e9b8c2a2 82 #define OR_CONTROL_BLE 0x00000020
Richard_Xiong 0:1855e9b8c2a2 83 #define OR_CONTROL_HCFS 0x000000C0
Richard_Xiong 0:1855e9b8c2a2 84 #define OR_CONTROL_HC_OPER 0x00000080
Richard_Xiong 0:1855e9b8c2a2 85 /* ----------------- HcCommandStatus Register ----------------- */
Richard_Xiong 0:1855e9b8c2a2 86 #define OR_CMD_STATUS_HCR 0x00000001
Richard_Xiong 0:1855e9b8c2a2 87 #define OR_CMD_STATUS_CLF 0x00000002
Richard_Xiong 0:1855e9b8c2a2 88 #define OR_CMD_STATUS_BLF 0x00000004
Richard_Xiong 0:1855e9b8c2a2 89 /* --------------- HcInterruptStatus Register ----------------- */
Richard_Xiong 0:1855e9b8c2a2 90 #define OR_INTR_STATUS_WDH 0x00000002
Richard_Xiong 0:1855e9b8c2a2 91 #define OR_INTR_STATUS_RHSC 0x00000040
Richard_Xiong 0:1855e9b8c2a2 92 /* --------------- HcInterruptEnable Register ----------------- */
Richard_Xiong 0:1855e9b8c2a2 93 #define OR_INTR_ENABLE_WDH 0x00000002
Richard_Xiong 0:1855e9b8c2a2 94 #define OR_INTR_ENABLE_RHSC 0x00000040
Richard_Xiong 0:1855e9b8c2a2 95 #define OR_INTR_ENABLE_MIE 0x80000000
Richard_Xiong 0:1855e9b8c2a2 96 /* ---------------- HcRhDescriptorA Register ------------------ */
Richard_Xiong 0:1855e9b8c2a2 97 #define OR_RH_STATUS_LPSC 0x00010000
Richard_Xiong 0:1855e9b8c2a2 98 #define OR_RH_STATUS_DRWE 0x00008000
Richard_Xiong 0:1855e9b8c2a2 99 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
Richard_Xiong 0:1855e9b8c2a2 100 #define OR_RH_PORT_CCS 0x00000001
Richard_Xiong 0:1855e9b8c2a2 101 #define OR_RH_PORT_PRS 0x00000010
Richard_Xiong 0:1855e9b8c2a2 102 #define OR_RH_PORT_CSC 0x00010000
Richard_Xiong 0:1855e9b8c2a2 103 #define OR_RH_PORT_PRSC 0x00100000
Richard_Xiong 0:1855e9b8c2a2 104
Richard_Xiong 0:1855e9b8c2a2 105
Richard_Xiong 0:1855e9b8c2a2 106 /*
Richard_Xiong 0:1855e9b8c2a2 107 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 108 * FRAME INTERVAL
Richard_Xiong 0:1855e9b8c2a2 109 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 110 */
Richard_Xiong 0:1855e9b8c2a2 111
Richard_Xiong 0:1855e9b8c2a2 112 #define FI 0x2EDF /* 12000 bits per frame (-1) */
Richard_Xiong 0:1855e9b8c2a2 113 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
Richard_Xiong 0:1855e9b8c2a2 114
Richard_Xiong 0:1855e9b8c2a2 115 /*
Richard_Xiong 0:1855e9b8c2a2 116 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 117 * TRANSFER DESCRIPTOR CONTROL FIELDS
Richard_Xiong 0:1855e9b8c2a2 118 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 119 */
Richard_Xiong 0:1855e9b8c2a2 120
Richard_Xiong 0:1855e9b8c2a2 121 #define TD_ROUNDING (USB_INT32U) (0x00040000) /* Buffer Rounding */
Richard_Xiong 0:1855e9b8c2a2 122 #define TD_SETUP (USB_INT32U)(0) /* Direction of Setup Packet */
Richard_Xiong 0:1855e9b8c2a2 123 #define TD_IN (USB_INT32U)(0x00100000) /* Direction In */
Richard_Xiong 0:1855e9b8c2a2 124 #define TD_OUT (USB_INT32U)(0x00080000) /* Direction Out */
Richard_Xiong 0:1855e9b8c2a2 125 #define TD_DELAY_INT(x) (USB_INT32U)((x) << 21) /* Delay Interrupt */
Richard_Xiong 0:1855e9b8c2a2 126 #define TD_TOGGLE_0 (USB_INT32U)(0x02000000) /* Toggle 0 */
Richard_Xiong 0:1855e9b8c2a2 127 #define TD_TOGGLE_1 (USB_INT32U)(0x03000000) /* Toggle 1 */
Richard_Xiong 0:1855e9b8c2a2 128 #define TD_CC (USB_INT32U)(0xF0000000) /* Completion Code */
Richard_Xiong 0:1855e9b8c2a2 129
Richard_Xiong 0:1855e9b8c2a2 130 /*
Richard_Xiong 0:1855e9b8c2a2 131 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 132 * USB STANDARD REQUEST DEFINITIONS
Richard_Xiong 0:1855e9b8c2a2 133 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 134 */
Richard_Xiong 0:1855e9b8c2a2 135
Richard_Xiong 0:1855e9b8c2a2 136 #define USB_DESCRIPTOR_TYPE_DEVICE 1
Richard_Xiong 0:1855e9b8c2a2 137 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
Richard_Xiong 0:1855e9b8c2a2 138 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
Richard_Xiong 0:1855e9b8c2a2 139 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
Richard_Xiong 0:1855e9b8c2a2 140 /* ----------- Control RequestType Fields ----------- */
Richard_Xiong 0:1855e9b8c2a2 141 #define USB_DEVICE_TO_HOST 0x80
Richard_Xiong 0:1855e9b8c2a2 142 #define USB_HOST_TO_DEVICE 0x00
Richard_Xiong 0:1855e9b8c2a2 143 #define USB_REQUEST_TYPE_CLASS 0x20
Richard_Xiong 0:1855e9b8c2a2 144 #define USB_RECIPIENT_DEVICE 0x00
Richard_Xiong 0:1855e9b8c2a2 145 #define USB_RECIPIENT_INTERFACE 0x01
Richard_Xiong 0:1855e9b8c2a2 146 /* -------------- USB Standard Requests -------------- */
Richard_Xiong 0:1855e9b8c2a2 147 #define SET_ADDRESS 5
Richard_Xiong 0:1855e9b8c2a2 148 #define GET_DESCRIPTOR 6
Richard_Xiong 0:1855e9b8c2a2 149 #define SET_CONFIGURATION 9
Richard_Xiong 0:1855e9b8c2a2 150 #define SET_INTERFACE 11
Richard_Xiong 0:1855e9b8c2a2 151
Richard_Xiong 0:1855e9b8c2a2 152 /*
Richard_Xiong 0:1855e9b8c2a2 153 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 154 * TYPE DEFINITIONS
Richard_Xiong 0:1855e9b8c2a2 155 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 156 */
Richard_Xiong 0:1855e9b8c2a2 157
Richard_Xiong 0:1855e9b8c2a2 158 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
Richard_Xiong 0:1855e9b8c2a2 159 volatile USB_INT32U Control; /* Endpoint descriptor control */
Richard_Xiong 0:1855e9b8c2a2 160 volatile USB_INT32U TailTd; /* Physical address of tail in Transfer descriptor list */
Richard_Xiong 0:1855e9b8c2a2 161 volatile USB_INT32U HeadTd; /* Physcial address of head in Transfer descriptor list */
Richard_Xiong 0:1855e9b8c2a2 162 volatile USB_INT32U Next; /* Physical address of next Endpoint descriptor */
Richard_Xiong 0:1855e9b8c2a2 163 } HCED;
Richard_Xiong 0:1855e9b8c2a2 164
Richard_Xiong 0:1855e9b8c2a2 165 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
Richard_Xiong 0:1855e9b8c2a2 166 volatile USB_INT32U Control; /* Transfer descriptor control */
Richard_Xiong 0:1855e9b8c2a2 167 volatile USB_INT32U CurrBufPtr; /* Physical address of current buffer pointer */
Richard_Xiong 0:1855e9b8c2a2 168 volatile USB_INT32U Next; /* Physical pointer to next Transfer Descriptor */
Richard_Xiong 0:1855e9b8c2a2 169 volatile USB_INT32U BufEnd; /* Physical address of end of buffer */
Richard_Xiong 0:1855e9b8c2a2 170 } HCTD;
Richard_Xiong 0:1855e9b8c2a2 171
Richard_Xiong 0:1855e9b8c2a2 172 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
Richard_Xiong 0:1855e9b8c2a2 173 volatile USB_INT32U IntTable[32]; /* Interrupt Table */
Richard_Xiong 0:1855e9b8c2a2 174 volatile USB_INT32U FrameNumber; /* Frame Number */
Richard_Xiong 0:1855e9b8c2a2 175 volatile USB_INT32U DoneHead; /* Done Head */
Richard_Xiong 0:1855e9b8c2a2 176 volatile USB_INT08U Reserved[116]; /* Reserved for future use */
Richard_Xiong 0:1855e9b8c2a2 177 volatile USB_INT08U Unknown[4]; /* Unused */
Richard_Xiong 0:1855e9b8c2a2 178 } HCCA;
Richard_Xiong 0:1855e9b8c2a2 179
Richard_Xiong 0:1855e9b8c2a2 180 /*
Richard_Xiong 0:1855e9b8c2a2 181 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 182 * EXTERN DECLARATIONS
Richard_Xiong 0:1855e9b8c2a2 183 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 184 */
Richard_Xiong 0:1855e9b8c2a2 185
Richard_Xiong 0:1855e9b8c2a2 186 extern volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 187 extern volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 188 extern volatile HCTD *TDHead; /* Head transfer descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 189 extern volatile HCTD *TDTail; /* Tail transfer descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 190 extern volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
Richard_Xiong 0:1855e9b8c2a2 191
Richard_Xiong 0:1855e9b8c2a2 192 /*
Richard_Xiong 0:1855e9b8c2a2 193 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 194 * FUNCTION PROTOTYPES
Richard_Xiong 0:1855e9b8c2a2 195 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 196 */
Richard_Xiong 0:1855e9b8c2a2 197
Richard_Xiong 0:1855e9b8c2a2 198 void Host_Init (void);
Richard_Xiong 0:1855e9b8c2a2 199
Richard_Xiong 0:1855e9b8c2a2 200 extern "C" void USB_IRQHandler(void) __irq;
Richard_Xiong 0:1855e9b8c2a2 201
Richard_Xiong 0:1855e9b8c2a2 202 USB_INT32S Host_EnumDev (void);
Richard_Xiong 0:1855e9b8c2a2 203
Richard_Xiong 0:1855e9b8c2a2 204 USB_INT32S Host_ProcessTD(volatile HCED *ed,
Richard_Xiong 0:1855e9b8c2a2 205 volatile USB_INT32U token,
Richard_Xiong 0:1855e9b8c2a2 206 volatile USB_INT08U *buffer,
Richard_Xiong 0:1855e9b8c2a2 207 USB_INT32U buffer_len);
Richard_Xiong 0:1855e9b8c2a2 208
Richard_Xiong 0:1855e9b8c2a2 209 void Host_DelayUS ( USB_INT32U delay);
Richard_Xiong 0:1855e9b8c2a2 210 void Host_DelayMS ( USB_INT32U delay);
Richard_Xiong 0:1855e9b8c2a2 211
Richard_Xiong 0:1855e9b8c2a2 212
Richard_Xiong 0:1855e9b8c2a2 213 void Host_TDInit (volatile HCTD *td);
Richard_Xiong 0:1855e9b8c2a2 214 void Host_EDInit (volatile HCED *ed);
Richard_Xiong 0:1855e9b8c2a2 215 void Host_HCCAInit (volatile HCCA *hcca);
Richard_Xiong 0:1855e9b8c2a2 216
Richard_Xiong 0:1855e9b8c2a2 217 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
Richard_Xiong 0:1855e9b8c2a2 218 USB_INT08U b_request,
Richard_Xiong 0:1855e9b8c2a2 219 USB_INT16U w_value,
Richard_Xiong 0:1855e9b8c2a2 220 USB_INT16U w_index,
Richard_Xiong 0:1855e9b8c2a2 221 USB_INT16U w_length,
Richard_Xiong 0:1855e9b8c2a2 222 volatile USB_INT08U *buffer);
Richard_Xiong 0:1855e9b8c2a2 223
Richard_Xiong 0:1855e9b8c2a2 224 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
Richard_Xiong 0:1855e9b8c2a2 225 USB_INT08U b_request,
Richard_Xiong 0:1855e9b8c2a2 226 USB_INT16U w_value,
Richard_Xiong 0:1855e9b8c2a2 227 USB_INT16U w_index,
Richard_Xiong 0:1855e9b8c2a2 228 USB_INT16U w_length,
Richard_Xiong 0:1855e9b8c2a2 229 volatile USB_INT08U *buffer);
Richard_Xiong 0:1855e9b8c2a2 230
Richard_Xiong 0:1855e9b8c2a2 231 void Host_FillSetup( USB_INT08U bm_request_type,
Richard_Xiong 0:1855e9b8c2a2 232 USB_INT08U b_request,
Richard_Xiong 0:1855e9b8c2a2 233 USB_INT16U w_value,
Richard_Xiong 0:1855e9b8c2a2 234 USB_INT16U w_index,
Richard_Xiong 0:1855e9b8c2a2 235 USB_INT16U w_length);
Richard_Xiong 0:1855e9b8c2a2 236
Richard_Xiong 0:1855e9b8c2a2 237
Richard_Xiong 0:1855e9b8c2a2 238 void Host_WDHWait (void);
Richard_Xiong 0:1855e9b8c2a2 239
Richard_Xiong 0:1855e9b8c2a2 240
Richard_Xiong 0:1855e9b8c2a2 241 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem);
Richard_Xiong 0:1855e9b8c2a2 242 void WriteLE32U (volatile USB_INT08U *pmem,
Richard_Xiong 0:1855e9b8c2a2 243 USB_INT32U val);
Richard_Xiong 0:1855e9b8c2a2 244 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem);
Richard_Xiong 0:1855e9b8c2a2 245 void WriteLE16U (volatile USB_INT08U *pmem,
Richard_Xiong 0:1855e9b8c2a2 246 USB_INT16U val);
Richard_Xiong 0:1855e9b8c2a2 247 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem);
Richard_Xiong 0:1855e9b8c2a2 248 void WriteBE32U (volatile USB_INT08U *pmem,
Richard_Xiong 0:1855e9b8c2a2 249 USB_INT32U val);
Richard_Xiong 0:1855e9b8c2a2 250 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem);
Richard_Xiong 0:1855e9b8c2a2 251 void WriteBE16U (volatile USB_INT08U *pmem,
Richard_Xiong 0:1855e9b8c2a2 252 USB_INT16U val);
Richard_Xiong 0:1855e9b8c2a2 253
Richard_Xiong 0:1855e9b8c2a2 254 #endif