Haoyu Xiong / Mbed 2 deprecated SerialTesting

Testing

Dependencies:   mbed FatFileSystemCpp

USBHostLite/usbhost_lpc17xx.cpp@0:1855e9b8c2a2, 2020-04-24 (annotated)

Committer:
Richard_Xiong
Date:
Fri Apr 24 01:49:33 2020 +0000
Revision:
0:1855e9b8c2a2
USBTesting

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Richard_Xiong 0:1855e9b8c2a2 1 /*
Richard_Xiong 0:1855e9b8c2a2 2 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 3 * NXP USB Host Stack
Richard_Xiong 0:1855e9b8c2a2 4 *
Richard_Xiong 0:1855e9b8c2a2 5 * (c) Copyright 2008, NXP SemiConductors
Richard_Xiong 0:1855e9b8c2a2 6 * (c) Copyright 2008, OnChip Technologies LLC
Richard_Xiong 0:1855e9b8c2a2 7 * All Rights Reserved
Richard_Xiong 0:1855e9b8c2a2 8 *
Richard_Xiong 0:1855e9b8c2a2 9 * www.nxp.com
Richard_Xiong 0:1855e9b8c2a2 10 * www.onchiptech.com
Richard_Xiong 0:1855e9b8c2a2 11 *
Richard_Xiong 0:1855e9b8c2a2 12 * File : usbhost_lpc17xx.c
Richard_Xiong 0:1855e9b8c2a2 13 * Programmer(s) : Ravikanth.P
Richard_Xiong 0:1855e9b8c2a2 14 * Version :
Richard_Xiong 0:1855e9b8c2a2 15 *
Richard_Xiong 0:1855e9b8c2a2 16 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 17 */
Richard_Xiong 0:1855e9b8c2a2 18
Richard_Xiong 0:1855e9b8c2a2 19 /*
Richard_Xiong 0:1855e9b8c2a2 20 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 21 * INCLUDE HEADER FILES
Richard_Xiong 0:1855e9b8c2a2 22 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 23 */
Richard_Xiong 0:1855e9b8c2a2 24
Richard_Xiong 0:1855e9b8c2a2 25 #include "usbhost_lpc17xx.h"
Richard_Xiong 0:1855e9b8c2a2 26
Richard_Xiong 0:1855e9b8c2a2 27 /*
Richard_Xiong 0:1855e9b8c2a2 28 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 29 * GLOBAL VARIABLES
Richard_Xiong 0:1855e9b8c2a2 30 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 31 */
Richard_Xiong 0:1855e9b8c2a2 32 int gUSBConnected;
Richard_Xiong 0:1855e9b8c2a2 33
Richard_Xiong 0:1855e9b8c2a2 34 volatile USB_INT32U HOST_RhscIntr = 0; /* Root Hub Status Change interrupt */
Richard_Xiong 0:1855e9b8c2a2 35 volatile USB_INT32U HOST_WdhIntr = 0; /* Semaphore to wait until the TD is submitted */
Richard_Xiong 0:1855e9b8c2a2 36 volatile USB_INT08U HOST_TDControlStatus = 0;
Richard_Xiong 0:1855e9b8c2a2 37 volatile HCED *EDCtrl; /* Control endpoint descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 38 volatile HCED *EDBulkIn; /* BulkIn endpoint descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 39 volatile HCED *EDBulkOut; /* BulkOut endpoint descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 40 volatile HCTD *TDHead; /* Head transfer descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 41 volatile HCTD *TDTail; /* Tail transfer descriptor structure */
Richard_Xiong 0:1855e9b8c2a2 42 volatile HCCA *Hcca; /* Host Controller Communications Area structure */
Richard_Xiong 0:1855e9b8c2a2 43 USB_INT16U *TDBufNonVol; /* Identical to TDBuffer just to reduce compiler warnings */
Richard_Xiong 0:1855e9b8c2a2 44 volatile USB_INT08U *TDBuffer; /* Current Buffer Pointer of transfer descriptor */
Richard_Xiong 0:1855e9b8c2a2 45
Richard_Xiong 0:1855e9b8c2a2 46 // USB host structures
Richard_Xiong 0:1855e9b8c2a2 47 // AHB SRAM block 1
Richard_Xiong 0:1855e9b8c2a2 48 #define HOSTBASEADDR 0x2007C000
Richard_Xiong 0:1855e9b8c2a2 49 // reserve memory for the linker
Richard_Xiong 0:1855e9b8c2a2 50 static USB_INT08U HostBuf[0x200] __attribute__((at(HOSTBASEADDR)));
Richard_Xiong 0:1855e9b8c2a2 51 /*
Richard_Xiong 0:1855e9b8c2a2 52 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 53 * DELAY IN MILLI SECONDS
Richard_Xiong 0:1855e9b8c2a2 54 *
Richard_Xiong 0:1855e9b8c2a2 55 * Description: This function provides a delay in milli seconds
Richard_Xiong 0:1855e9b8c2a2 56 *
Richard_Xiong 0:1855e9b8c2a2 57 * Arguments : delay The delay required
Richard_Xiong 0:1855e9b8c2a2 58 *
Richard_Xiong 0:1855e9b8c2a2 59 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 60 *
Richard_Xiong 0:1855e9b8c2a2 61 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 62 */
Richard_Xiong 0:1855e9b8c2a2 63
Richard_Xiong 0:1855e9b8c2a2 64 void Host_DelayMS (USB_INT32U delay)
Richard_Xiong 0:1855e9b8c2a2 65 {
Richard_Xiong 0:1855e9b8c2a2 66 volatile USB_INT32U i;
Richard_Xiong 0:1855e9b8c2a2 67
Richard_Xiong 0:1855e9b8c2a2 68
Richard_Xiong 0:1855e9b8c2a2 69 for (i = 0; i < delay; i++) {
Richard_Xiong 0:1855e9b8c2a2 70 Host_DelayUS(1000);
Richard_Xiong 0:1855e9b8c2a2 71 }
Richard_Xiong 0:1855e9b8c2a2 72 }
Richard_Xiong 0:1855e9b8c2a2 73
Richard_Xiong 0:1855e9b8c2a2 74 /*
Richard_Xiong 0:1855e9b8c2a2 75 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 76 * DELAY IN MICRO SECONDS
Richard_Xiong 0:1855e9b8c2a2 77 *
Richard_Xiong 0:1855e9b8c2a2 78 * Description: This function provides a delay in micro seconds
Richard_Xiong 0:1855e9b8c2a2 79 *
Richard_Xiong 0:1855e9b8c2a2 80 * Arguments : delay The delay required
Richard_Xiong 0:1855e9b8c2a2 81 *
Richard_Xiong 0:1855e9b8c2a2 82 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 83 *
Richard_Xiong 0:1855e9b8c2a2 84 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 85 */
Richard_Xiong 0:1855e9b8c2a2 86
Richard_Xiong 0:1855e9b8c2a2 87 void Host_DelayUS (USB_INT32U delay)
Richard_Xiong 0:1855e9b8c2a2 88 {
Richard_Xiong 0:1855e9b8c2a2 89 volatile USB_INT32U i;
Richard_Xiong 0:1855e9b8c2a2 90
Richard_Xiong 0:1855e9b8c2a2 91
Richard_Xiong 0:1855e9b8c2a2 92 for (i = 0; i < (4 * delay); i++) { /* This logic was tested. It gives app. 1 micro sec delay */
Richard_Xiong 0:1855e9b8c2a2 93 ;
Richard_Xiong 0:1855e9b8c2a2 94 }
Richard_Xiong 0:1855e9b8c2a2 95 }
Richard_Xiong 0:1855e9b8c2a2 96
Richard_Xiong 0:1855e9b8c2a2 97 // bits of the USB/OTG clock control register
Richard_Xiong 0:1855e9b8c2a2 98 #define HOST_CLK_EN (1<<0)
Richard_Xiong 0:1855e9b8c2a2 99 #define DEV_CLK_EN (1<<1)
Richard_Xiong 0:1855e9b8c2a2 100 #define PORTSEL_CLK_EN (1<<3)
Richard_Xiong 0:1855e9b8c2a2 101 #define AHB_CLK_EN (1<<4)
Richard_Xiong 0:1855e9b8c2a2 102
Richard_Xiong 0:1855e9b8c2a2 103 // bits of the USB/OTG clock status register
Richard_Xiong 0:1855e9b8c2a2 104 #define HOST_CLK_ON (1<<0)
Richard_Xiong 0:1855e9b8c2a2 105 #define DEV_CLK_ON (1<<1)
Richard_Xiong 0:1855e9b8c2a2 106 #define PORTSEL_CLK_ON (1<<3)
Richard_Xiong 0:1855e9b8c2a2 107 #define AHB_CLK_ON (1<<4)
Richard_Xiong 0:1855e9b8c2a2 108
Richard_Xiong 0:1855e9b8c2a2 109 // we need host clock, OTG/portsel clock and AHB clock
Richard_Xiong 0:1855e9b8c2a2 110 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
Richard_Xiong 0:1855e9b8c2a2 111
Richard_Xiong 0:1855e9b8c2a2 112 /*
Richard_Xiong 0:1855e9b8c2a2 113 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 114 * INITIALIZE THE HOST CONTROLLER
Richard_Xiong 0:1855e9b8c2a2 115 *
Richard_Xiong 0:1855e9b8c2a2 116 * Description: This function initializes lpc17xx host controller
Richard_Xiong 0:1855e9b8c2a2 117 *
Richard_Xiong 0:1855e9b8c2a2 118 * Arguments : None
Richard_Xiong 0:1855e9b8c2a2 119 *
Richard_Xiong 0:1855e9b8c2a2 120 * Returns :
Richard_Xiong 0:1855e9b8c2a2 121 *
Richard_Xiong 0:1855e9b8c2a2 122 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 123 */
Richard_Xiong 0:1855e9b8c2a2 124 void Host_Init (void)
Richard_Xiong 0:1855e9b8c2a2 125 {
Richard_Xiong 0:1855e9b8c2a2 126 PRINT_Log("In Host_Init\n");
Richard_Xiong 0:1855e9b8c2a2 127 NVIC_DisableIRQ(USB_IRQn); /* Disable the USB interrupt source */
Richard_Xiong 0:1855e9b8c2a2 128
Richard_Xiong 0:1855e9b8c2a2 129 // turn on power for USB
Richard_Xiong 0:1855e9b8c2a2 130 LPC_SC->PCONP |= (1UL<<31);
Richard_Xiong 0:1855e9b8c2a2 131 // Enable USB host clock, port selection and AHB clock
Richard_Xiong 0:1855e9b8c2a2 132 LPC_USB->USBClkCtrl |= CLOCK_MASK;
Richard_Xiong 0:1855e9b8c2a2 133 // Wait for clocks to become available
Richard_Xiong 0:1855e9b8c2a2 134 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK)
Richard_Xiong 0:1855e9b8c2a2 135 ;
Richard_Xiong 0:1855e9b8c2a2 136
Richard_Xiong 0:1855e9b8c2a2 137 // it seems the bits[0:1] mean the following
Richard_Xiong 0:1855e9b8c2a2 138 // 0: U1=device, U2=host
Richard_Xiong 0:1855e9b8c2a2 139 // 1: U1=host, U2=host
Richard_Xiong 0:1855e9b8c2a2 140 // 2: reserved
Richard_Xiong 0:1855e9b8c2a2 141 // 3: U1=host, U2=device
Richard_Xiong 0:1855e9b8c2a2 142 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
Richard_Xiong 0:1855e9b8c2a2 143 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
Richard_Xiong 0:1855e9b8c2a2 144 LPC_USB->OTGStCtrl |= 1;
Richard_Xiong 0:1855e9b8c2a2 145
Richard_Xiong 0:1855e9b8c2a2 146 // now that we've configured the ports, we can turn off the portsel clock
Richard_Xiong 0:1855e9b8c2a2 147 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
Richard_Xiong 0:1855e9b8c2a2 148
Richard_Xiong 0:1855e9b8c2a2 149 // power pins are not connected on mbed, so we can skip them
Richard_Xiong 0:1855e9b8c2a2 150 /* P1[18] = USB_UP_LED, 01 */
Richard_Xiong 0:1855e9b8c2a2 151 /* P1[19] = /USB_PPWR, 10 */
Richard_Xiong 0:1855e9b8c2a2 152 /* P1[22] = USB_PWRD, 10 */
Richard_Xiong 0:1855e9b8c2a2 153 /* P1[27] = /USB_OVRCR, 10 */
Richard_Xiong 0:1855e9b8c2a2 154 /*LPC_PINCON->PINSEL3 &= ~((3<<4) | (3<<6) | (3<<12) | (3<<22));
Richard_Xiong 0:1855e9b8c2a2 155 LPC_PINCON->PINSEL3 |= ((1<<4)|(2<<6) | (2<<12) | (2<<22)); // 0x00802080
Richard_Xiong 0:1855e9b8c2a2 156 */
Richard_Xiong 0:1855e9b8c2a2 157
Richard_Xiong 0:1855e9b8c2a2 158 // configure USB D+/D- pins
Richard_Xiong 0:1855e9b8c2a2 159 /* P0[29] = USB_D+, 01 */
Richard_Xiong 0:1855e9b8c2a2 160 /* P0[30] = USB_D-, 01 */
Richard_Xiong 0:1855e9b8c2a2 161 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
Richard_Xiong 0:1855e9b8c2a2 162 LPC_PINCON->PINSEL1 |= ((1<<26)|(1<<28)); // 0x14000000
Richard_Xiong 0:1855e9b8c2a2 163
Richard_Xiong 0:1855e9b8c2a2 164 PRINT_Log("Initializing Host Stack\n");
Richard_Xiong 0:1855e9b8c2a2 165
Richard_Xiong 0:1855e9b8c2a2 166 Hcca = (volatile HCCA *)(HostBuf+0x000);
Richard_Xiong 0:1855e9b8c2a2 167 TDHead = (volatile HCTD *)(HostBuf+0x100);
Richard_Xiong 0:1855e9b8c2a2 168 TDTail = (volatile HCTD *)(HostBuf+0x110);
Richard_Xiong 0:1855e9b8c2a2 169 EDCtrl = (volatile HCED *)(HostBuf+0x120);
Richard_Xiong 0:1855e9b8c2a2 170 EDBulkIn = (volatile HCED *)(HostBuf+0x130);
Richard_Xiong 0:1855e9b8c2a2 171 EDBulkOut = (volatile HCED *)(HostBuf+0x140);
Richard_Xiong 0:1855e9b8c2a2 172 TDBuffer = (volatile USB_INT08U *)(HostBuf+0x150);
Richard_Xiong 0:1855e9b8c2a2 173
Richard_Xiong 0:1855e9b8c2a2 174 /* Initialize all the TDs, EDs and HCCA to 0 */
Richard_Xiong 0:1855e9b8c2a2 175 Host_EDInit(EDCtrl);
Richard_Xiong 0:1855e9b8c2a2 176 Host_EDInit(EDBulkIn);
Richard_Xiong 0:1855e9b8c2a2 177 Host_EDInit(EDBulkOut);
Richard_Xiong 0:1855e9b8c2a2 178 Host_TDInit(TDHead);
Richard_Xiong 0:1855e9b8c2a2 179 Host_TDInit(TDTail);
Richard_Xiong 0:1855e9b8c2a2 180 Host_HCCAInit(Hcca);
Richard_Xiong 0:1855e9b8c2a2 181
Richard_Xiong 0:1855e9b8c2a2 182 Host_DelayMS(50); /* Wait 50 ms before apply reset */
Richard_Xiong 0:1855e9b8c2a2 183 LPC_USB->HcControl = 0; /* HARDWARE RESET */
Richard_Xiong 0:1855e9b8c2a2 184 LPC_USB->HcControlHeadED = 0; /* Initialize Control list head to Zero */
Richard_Xiong 0:1855e9b8c2a2 185 LPC_USB->HcBulkHeadED = 0; /* Initialize Bulk list head to Zero */
Richard_Xiong 0:1855e9b8c2a2 186
Richard_Xiong 0:1855e9b8c2a2 187 /* SOFTWARE RESET */
Richard_Xiong 0:1855e9b8c2a2 188 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
Richard_Xiong 0:1855e9b8c2a2 189 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL; /* Write Fm Interval and Largest Data Packet Counter */
Richard_Xiong 0:1855e9b8c2a2 190
Richard_Xiong 0:1855e9b8c2a2 191 /* Put HC in operational state */
Richard_Xiong 0:1855e9b8c2a2 192 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
Richard_Xiong 0:1855e9b8c2a2 193 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC; /* Set Global Power */
Richard_Xiong 0:1855e9b8c2a2 194
Richard_Xiong 0:1855e9b8c2a2 195 LPC_USB->HcHCCA = (USB_INT32U)Hcca;
Richard_Xiong 0:1855e9b8c2a2 196 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus; /* Clear Interrrupt Status */
Richard_Xiong 0:1855e9b8c2a2 197
Richard_Xiong 0:1855e9b8c2a2 198
Richard_Xiong 0:1855e9b8c2a2 199 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE |
Richard_Xiong 0:1855e9b8c2a2 200 OR_INTR_ENABLE_WDH |
Richard_Xiong 0:1855e9b8c2a2 201 OR_INTR_ENABLE_RHSC;
Richard_Xiong 0:1855e9b8c2a2 202
Richard_Xiong 0:1855e9b8c2a2 203 NVIC_SetPriority(USB_IRQn, 0); /* highest priority */
Richard_Xiong 0:1855e9b8c2a2 204 /* Enable the USB Interrupt */
Richard_Xiong 0:1855e9b8c2a2 205 NVIC_EnableIRQ(USB_IRQn);
Richard_Xiong 0:1855e9b8c2a2 206 PRINT_Log("Host Initialized\n");
Richard_Xiong 0:1855e9b8c2a2 207 }
Richard_Xiong 0:1855e9b8c2a2 208
Richard_Xiong 0:1855e9b8c2a2 209 /*
Richard_Xiong 0:1855e9b8c2a2 210 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 211 * INTERRUPT SERVICE ROUTINE
Richard_Xiong 0:1855e9b8c2a2 212 *
Richard_Xiong 0:1855e9b8c2a2 213 * Description: This function services the interrupt caused by host controller
Richard_Xiong 0:1855e9b8c2a2 214 *
Richard_Xiong 0:1855e9b8c2a2 215 * Arguments : None
Richard_Xiong 0:1855e9b8c2a2 216 *
Richard_Xiong 0:1855e9b8c2a2 217 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 218 *
Richard_Xiong 0:1855e9b8c2a2 219 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 220 */
Richard_Xiong 0:1855e9b8c2a2 221
Richard_Xiong 0:1855e9b8c2a2 222 void USB_IRQHandler (void) __irq
Richard_Xiong 0:1855e9b8c2a2 223 {
Richard_Xiong 0:1855e9b8c2a2 224 USB_INT32U int_status;
Richard_Xiong 0:1855e9b8c2a2 225 USB_INT32U ie_status;
Richard_Xiong 0:1855e9b8c2a2 226
Richard_Xiong 0:1855e9b8c2a2 227 int_status = LPC_USB->HcInterruptStatus; /* Read Interrupt Status */
Richard_Xiong 0:1855e9b8c2a2 228 ie_status = LPC_USB->HcInterruptEnable; /* Read Interrupt enable status */
Richard_Xiong 0:1855e9b8c2a2 229
Richard_Xiong 0:1855e9b8c2a2 230 if (!(int_status & ie_status)) {
Richard_Xiong 0:1855e9b8c2a2 231 return;
Richard_Xiong 0:1855e9b8c2a2 232 } else {
Richard_Xiong 0:1855e9b8c2a2 233
Richard_Xiong 0:1855e9b8c2a2 234 int_status = int_status & ie_status;
Richard_Xiong 0:1855e9b8c2a2 235 if (int_status & OR_INTR_STATUS_RHSC) { /* Root hub status change interrupt */
Richard_Xiong 0:1855e9b8c2a2 236 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
Richard_Xiong 0:1855e9b8c2a2 237 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
Richard_Xiong 0:1855e9b8c2a2 238 /*
Richard_Xiong 0:1855e9b8c2a2 239 * When DRWE is on, Connect Status Change
Richard_Xiong 0:1855e9b8c2a2 240 * means a remote wakeup event.
Richard_Xiong 0:1855e9b8c2a2 241 */
Richard_Xiong 0:1855e9b8c2a2 242 HOST_RhscIntr = 1;// JUST SOMETHING FOR A BREAKPOINT
Richard_Xiong 0:1855e9b8c2a2 243 }
Richard_Xiong 0:1855e9b8c2a2 244 else {
Richard_Xiong 0:1855e9b8c2a2 245 /*
Richard_Xiong 0:1855e9b8c2a2 246 * When DRWE is off, Connect Status Change
Richard_Xiong 0:1855e9b8c2a2 247 * is NOT a remote wakeup event
Richard_Xiong 0:1855e9b8c2a2 248 */
Richard_Xiong 0:1855e9b8c2a2 249 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
Richard_Xiong 0:1855e9b8c2a2 250 if (!gUSBConnected) {
Richard_Xiong 0:1855e9b8c2a2 251 HOST_TDControlStatus = 0;
Richard_Xiong 0:1855e9b8c2a2 252 HOST_WdhIntr = 0;
Richard_Xiong 0:1855e9b8c2a2 253 HOST_RhscIntr = 1;
Richard_Xiong 0:1855e9b8c2a2 254 gUSBConnected = 1;
Richard_Xiong 0:1855e9b8c2a2 255 }
Richard_Xiong 0:1855e9b8c2a2 256 else
Richard_Xiong 0:1855e9b8c2a2 257 PRINT_Log("Spurious status change (connected)?\n");
Richard_Xiong 0:1855e9b8c2a2 258 } else {
Richard_Xiong 0:1855e9b8c2a2 259 if (gUSBConnected) {
Richard_Xiong 0:1855e9b8c2a2 260 LPC_USB->HcInterruptEnable = 0; // why do we get multiple disc. rupts???
Richard_Xiong 0:1855e9b8c2a2 261 HOST_RhscIntr = 0;
Richard_Xiong 0:1855e9b8c2a2 262 gUSBConnected = 0;
Richard_Xiong 0:1855e9b8c2a2 263 }
Richard_Xiong 0:1855e9b8c2a2 264 else
Richard_Xiong 0:1855e9b8c2a2 265 PRINT_Log("Spurious status change (disconnected)?\n");
Richard_Xiong 0:1855e9b8c2a2 266 }
Richard_Xiong 0:1855e9b8c2a2 267 }
Richard_Xiong 0:1855e9b8c2a2 268 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
Richard_Xiong 0:1855e9b8c2a2 269 }
Richard_Xiong 0:1855e9b8c2a2 270 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
Richard_Xiong 0:1855e9b8c2a2 271 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
Richard_Xiong 0:1855e9b8c2a2 272 }
Richard_Xiong 0:1855e9b8c2a2 273 }
Richard_Xiong 0:1855e9b8c2a2 274 if (int_status & OR_INTR_STATUS_WDH) { /* Writeback Done Head interrupt */
Richard_Xiong 0:1855e9b8c2a2 275 HOST_WdhIntr = 1;
Richard_Xiong 0:1855e9b8c2a2 276 HOST_TDControlStatus = (TDHead->Control >> 28) & 0xf;
Richard_Xiong 0:1855e9b8c2a2 277 }
Richard_Xiong 0:1855e9b8c2a2 278 LPC_USB->HcInterruptStatus = int_status; /* Clear interrupt status register */
Richard_Xiong 0:1855e9b8c2a2 279 }
Richard_Xiong 0:1855e9b8c2a2 280 return;
Richard_Xiong 0:1855e9b8c2a2 281 }
Richard_Xiong 0:1855e9b8c2a2 282
Richard_Xiong 0:1855e9b8c2a2 283 /*
Richard_Xiong 0:1855e9b8c2a2 284 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 285 * PROCESS TRANSFER DESCRIPTOR
Richard_Xiong 0:1855e9b8c2a2 286 *
Richard_Xiong 0:1855e9b8c2a2 287 * Description: This function processes the transfer descriptor
Richard_Xiong 0:1855e9b8c2a2 288 *
Richard_Xiong 0:1855e9b8c2a2 289 * Arguments : ed Endpoint descriptor that contains this transfer descriptor
Richard_Xiong 0:1855e9b8c2a2 290 * token SETUP, IN, OUT
Richard_Xiong 0:1855e9b8c2a2 291 * buffer Current Buffer Pointer of the transfer descriptor
Richard_Xiong 0:1855e9b8c2a2 292 * buffer_len Length of the buffer
Richard_Xiong 0:1855e9b8c2a2 293 *
Richard_Xiong 0:1855e9b8c2a2 294 * Returns : OK if TD submission is successful
Richard_Xiong 0:1855e9b8c2a2 295 * ERROR if TD submission fails
Richard_Xiong 0:1855e9b8c2a2 296 *
Richard_Xiong 0:1855e9b8c2a2 297 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 298 */
Richard_Xiong 0:1855e9b8c2a2 299
Richard_Xiong 0:1855e9b8c2a2 300 USB_INT32S Host_ProcessTD (volatile HCED *ed,
Richard_Xiong 0:1855e9b8c2a2 301 volatile USB_INT32U token,
Richard_Xiong 0:1855e9b8c2a2 302 volatile USB_INT08U *buffer,
Richard_Xiong 0:1855e9b8c2a2 303 USB_INT32U buffer_len)
Richard_Xiong 0:1855e9b8c2a2 304 {
Richard_Xiong 0:1855e9b8c2a2 305 volatile USB_INT32U td_toggle;
Richard_Xiong 0:1855e9b8c2a2 306
Richard_Xiong 0:1855e9b8c2a2 307
Richard_Xiong 0:1855e9b8c2a2 308 if (ed == EDCtrl) {
Richard_Xiong 0:1855e9b8c2a2 309 if (token == TD_SETUP) {
Richard_Xiong 0:1855e9b8c2a2 310 td_toggle = TD_TOGGLE_0;
Richard_Xiong 0:1855e9b8c2a2 311 } else {
Richard_Xiong 0:1855e9b8c2a2 312 td_toggle = TD_TOGGLE_1;
Richard_Xiong 0:1855e9b8c2a2 313 }
Richard_Xiong 0:1855e9b8c2a2 314 } else {
Richard_Xiong 0:1855e9b8c2a2 315 td_toggle = 0;
Richard_Xiong 0:1855e9b8c2a2 316 }
Richard_Xiong 0:1855e9b8c2a2 317 TDHead->Control = (TD_ROUNDING |
Richard_Xiong 0:1855e9b8c2a2 318 token |
Richard_Xiong 0:1855e9b8c2a2 319 TD_DELAY_INT(0) |
Richard_Xiong 0:1855e9b8c2a2 320 td_toggle |
Richard_Xiong 0:1855e9b8c2a2 321 TD_CC);
Richard_Xiong 0:1855e9b8c2a2 322 TDTail->Control = 0;
Richard_Xiong 0:1855e9b8c2a2 323 TDHead->CurrBufPtr = (USB_INT32U) buffer;
Richard_Xiong 0:1855e9b8c2a2 324 TDTail->CurrBufPtr = 0;
Richard_Xiong 0:1855e9b8c2a2 325 TDHead->Next = (USB_INT32U) TDTail;
Richard_Xiong 0:1855e9b8c2a2 326 TDTail->Next = 0;
Richard_Xiong 0:1855e9b8c2a2 327 TDHead->BufEnd = (USB_INT32U)(buffer + (buffer_len - 1));
Richard_Xiong 0:1855e9b8c2a2 328 TDTail->BufEnd = 0;
Richard_Xiong 0:1855e9b8c2a2 329
Richard_Xiong 0:1855e9b8c2a2 330 ed->HeadTd = (USB_INT32U)TDHead | ((ed->HeadTd) & 0x00000002);
Richard_Xiong 0:1855e9b8c2a2 331 ed->TailTd = (USB_INT32U)TDTail;
Richard_Xiong 0:1855e9b8c2a2 332 ed->Next = 0;
Richard_Xiong 0:1855e9b8c2a2 333
Richard_Xiong 0:1855e9b8c2a2 334 if (ed == EDCtrl) {
Richard_Xiong 0:1855e9b8c2a2 335 LPC_USB->HcControlHeadED = (USB_INT32U)ed;
Richard_Xiong 0:1855e9b8c2a2 336 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_CLF;
Richard_Xiong 0:1855e9b8c2a2 337 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_CLE;
Richard_Xiong 0:1855e9b8c2a2 338 } else {
Richard_Xiong 0:1855e9b8c2a2 339 LPC_USB->HcBulkHeadED = (USB_INT32U)ed;
Richard_Xiong 0:1855e9b8c2a2 340 LPC_USB->HcCommandStatus = LPC_USB->HcCommandStatus | OR_CMD_STATUS_BLF;
Richard_Xiong 0:1855e9b8c2a2 341 LPC_USB->HcControl = LPC_USB->HcControl | OR_CONTROL_BLE;
Richard_Xiong 0:1855e9b8c2a2 342 }
Richard_Xiong 0:1855e9b8c2a2 343
Richard_Xiong 0:1855e9b8c2a2 344 Host_WDHWait();
Richard_Xiong 0:1855e9b8c2a2 345
Richard_Xiong 0:1855e9b8c2a2 346 // if (!(TDHead->Control & 0xF0000000)) {
Richard_Xiong 0:1855e9b8c2a2 347 if (!HOST_TDControlStatus) {
Richard_Xiong 0:1855e9b8c2a2 348 return (OK);
Richard_Xiong 0:1855e9b8c2a2 349 } else {
Richard_Xiong 0:1855e9b8c2a2 350 return (ERR_TD_FAIL);
Richard_Xiong 0:1855e9b8c2a2 351 }
Richard_Xiong 0:1855e9b8c2a2 352 }
Richard_Xiong 0:1855e9b8c2a2 353
Richard_Xiong 0:1855e9b8c2a2 354 /*
Richard_Xiong 0:1855e9b8c2a2 355 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 356 * ENUMERATE THE DEVICE
Richard_Xiong 0:1855e9b8c2a2 357 *
Richard_Xiong 0:1855e9b8c2a2 358 * Description: This function is used to enumerate the device connected
Richard_Xiong 0:1855e9b8c2a2 359 *
Richard_Xiong 0:1855e9b8c2a2 360 * Arguments : None
Richard_Xiong 0:1855e9b8c2a2 361 *
Richard_Xiong 0:1855e9b8c2a2 362 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 363 *
Richard_Xiong 0:1855e9b8c2a2 364 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 365 */
Richard_Xiong 0:1855e9b8c2a2 366
Richard_Xiong 0:1855e9b8c2a2 367 USB_INT32S Host_EnumDev (void)
Richard_Xiong 0:1855e9b8c2a2 368 {
Richard_Xiong 0:1855e9b8c2a2 369 USB_INT32S rc;
Richard_Xiong 0:1855e9b8c2a2 370
Richard_Xiong 0:1855e9b8c2a2 371 PRINT_Log("Connect a Mass Storage device\n");
Richard_Xiong 0:1855e9b8c2a2 372 while (!HOST_RhscIntr)
Richard_Xiong 0:1855e9b8c2a2 373 __WFI();
Richard_Xiong 0:1855e9b8c2a2 374 Host_DelayMS(100); /* USB 2.0 spec says atleast 50ms delay beore port reset */
Richard_Xiong 0:1855e9b8c2a2 375 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS; // Initiate port reset
Richard_Xiong 0:1855e9b8c2a2 376 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS)
Richard_Xiong 0:1855e9b8c2a2 377 __WFI(); // Wait for port reset to complete...
Richard_Xiong 0:1855e9b8c2a2 378 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC; // ...and clear port reset signal
Richard_Xiong 0:1855e9b8c2a2 379 Host_DelayMS(200); /* Wait for 100 MS after port reset */
Richard_Xiong 0:1855e9b8c2a2 380
Richard_Xiong 0:1855e9b8c2a2 381 EDCtrl->Control = 8 << 16; /* Put max pkt size = 8 */
Richard_Xiong 0:1855e9b8c2a2 382 /* Read first 8 bytes of device desc */
Richard_Xiong 0:1855e9b8c2a2 383 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_DEVICE, 0, TDBuffer, 8);
Richard_Xiong 0:1855e9b8c2a2 384 if (rc != OK) {
Richard_Xiong 0:1855e9b8c2a2 385 PRINT_Err(rc);
Richard_Xiong 0:1855e9b8c2a2 386 return (rc);
Richard_Xiong 0:1855e9b8c2a2 387 }
Richard_Xiong 0:1855e9b8c2a2 388 EDCtrl->Control = TDBuffer[7] << 16; /* Get max pkt size of endpoint 0 */
Richard_Xiong 0:1855e9b8c2a2 389 rc = HOST_SET_ADDRESS(1); /* Set the device address to 1 */
Richard_Xiong 0:1855e9b8c2a2 390 if (rc != OK) {
Richard_Xiong 0:1855e9b8c2a2 391 PRINT_Err(rc);
Richard_Xiong 0:1855e9b8c2a2 392 return (rc);
Richard_Xiong 0:1855e9b8c2a2 393 }
Richard_Xiong 0:1855e9b8c2a2 394 Host_DelayMS(2);
Richard_Xiong 0:1855e9b8c2a2 395 EDCtrl->Control = (EDCtrl->Control) | 1; /* Modify control pipe with address 1 */
Richard_Xiong 0:1855e9b8c2a2 396 /* Get the configuration descriptor */
Richard_Xiong 0:1855e9b8c2a2 397 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, 9);
Richard_Xiong 0:1855e9b8c2a2 398 if (rc != OK) {
Richard_Xiong 0:1855e9b8c2a2 399 PRINT_Err(rc);
Richard_Xiong 0:1855e9b8c2a2 400 return (rc);
Richard_Xiong 0:1855e9b8c2a2 401 }
Richard_Xiong 0:1855e9b8c2a2 402 /* Get the first configuration data */
Richard_Xiong 0:1855e9b8c2a2 403 rc = HOST_GET_DESCRIPTOR(USB_DESCRIPTOR_TYPE_CONFIGURATION, 0, TDBuffer, ReadLE16U(&TDBuffer[2]));
Richard_Xiong 0:1855e9b8c2a2 404 if (rc != OK) {
Richard_Xiong 0:1855e9b8c2a2 405 PRINT_Err(rc);
Richard_Xiong 0:1855e9b8c2a2 406 return (rc);
Richard_Xiong 0:1855e9b8c2a2 407 }
Richard_Xiong 0:1855e9b8c2a2 408 rc = MS_ParseConfiguration(); /* Parse the configuration */
Richard_Xiong 0:1855e9b8c2a2 409 if (rc != OK) {
Richard_Xiong 0:1855e9b8c2a2 410 PRINT_Err(rc);
Richard_Xiong 0:1855e9b8c2a2 411 return (rc);
Richard_Xiong 0:1855e9b8c2a2 412 }
Richard_Xiong 0:1855e9b8c2a2 413 rc = USBH_SET_CONFIGURATION(1); /* Select device configuration 1 */
Richard_Xiong 0:1855e9b8c2a2 414 if (rc != OK) {
Richard_Xiong 0:1855e9b8c2a2 415 PRINT_Err(rc);
Richard_Xiong 0:1855e9b8c2a2 416 }
Richard_Xiong 0:1855e9b8c2a2 417 Host_DelayMS(100); /* Some devices may require this delay */
Richard_Xiong 0:1855e9b8c2a2 418 return (rc);
Richard_Xiong 0:1855e9b8c2a2 419 }
Richard_Xiong 0:1855e9b8c2a2 420
Richard_Xiong 0:1855e9b8c2a2 421 /*
Richard_Xiong 0:1855e9b8c2a2 422 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 423 * RECEIVE THE CONTROL INFORMATION
Richard_Xiong 0:1855e9b8c2a2 424 *
Richard_Xiong 0:1855e9b8c2a2 425 * Description: This function is used to receive the control information
Richard_Xiong 0:1855e9b8c2a2 426 *
Richard_Xiong 0:1855e9b8c2a2 427 * Arguments : bm_request_type
Richard_Xiong 0:1855e9b8c2a2 428 * b_request
Richard_Xiong 0:1855e9b8c2a2 429 * w_value
Richard_Xiong 0:1855e9b8c2a2 430 * w_index
Richard_Xiong 0:1855e9b8c2a2 431 * w_length
Richard_Xiong 0:1855e9b8c2a2 432 * buffer
Richard_Xiong 0:1855e9b8c2a2 433 *
Richard_Xiong 0:1855e9b8c2a2 434 * Returns : OK if Success
Richard_Xiong 0:1855e9b8c2a2 435 * ERROR if Failed
Richard_Xiong 0:1855e9b8c2a2 436 *
Richard_Xiong 0:1855e9b8c2a2 437 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 438 */
Richard_Xiong 0:1855e9b8c2a2 439
Richard_Xiong 0:1855e9b8c2a2 440 USB_INT32S Host_CtrlRecv ( USB_INT08U bm_request_type,
Richard_Xiong 0:1855e9b8c2a2 441 USB_INT08U b_request,
Richard_Xiong 0:1855e9b8c2a2 442 USB_INT16U w_value,
Richard_Xiong 0:1855e9b8c2a2 443 USB_INT16U w_index,
Richard_Xiong 0:1855e9b8c2a2 444 USB_INT16U w_length,
Richard_Xiong 0:1855e9b8c2a2 445 volatile USB_INT08U *buffer)
Richard_Xiong 0:1855e9b8c2a2 446 {
Richard_Xiong 0:1855e9b8c2a2 447 USB_INT32S rc;
Richard_Xiong 0:1855e9b8c2a2 448
Richard_Xiong 0:1855e9b8c2a2 449
Richard_Xiong 0:1855e9b8c2a2 450 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
Richard_Xiong 0:1855e9b8c2a2 451 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
Richard_Xiong 0:1855e9b8c2a2 452 if (rc == OK) {
Richard_Xiong 0:1855e9b8c2a2 453 if (w_length) {
Richard_Xiong 0:1855e9b8c2a2 454 rc = Host_ProcessTD(EDCtrl, TD_IN, TDBuffer, w_length);
Richard_Xiong 0:1855e9b8c2a2 455 }
Richard_Xiong 0:1855e9b8c2a2 456 if (rc == OK) {
Richard_Xiong 0:1855e9b8c2a2 457 rc = Host_ProcessTD(EDCtrl, TD_OUT, NULL, 0);
Richard_Xiong 0:1855e9b8c2a2 458 }
Richard_Xiong 0:1855e9b8c2a2 459 }
Richard_Xiong 0:1855e9b8c2a2 460 return (rc);
Richard_Xiong 0:1855e9b8c2a2 461 }
Richard_Xiong 0:1855e9b8c2a2 462
Richard_Xiong 0:1855e9b8c2a2 463 /*
Richard_Xiong 0:1855e9b8c2a2 464 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 465 * SEND THE CONTROL INFORMATION
Richard_Xiong 0:1855e9b8c2a2 466 *
Richard_Xiong 0:1855e9b8c2a2 467 * Description: This function is used to send the control information
Richard_Xiong 0:1855e9b8c2a2 468 *
Richard_Xiong 0:1855e9b8c2a2 469 * Arguments : None
Richard_Xiong 0:1855e9b8c2a2 470 *
Richard_Xiong 0:1855e9b8c2a2 471 * Returns : OK if Success
Richard_Xiong 0:1855e9b8c2a2 472 * ERR_INVALID_BOOTSIG if Failed
Richard_Xiong 0:1855e9b8c2a2 473 *
Richard_Xiong 0:1855e9b8c2a2 474 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 475 */
Richard_Xiong 0:1855e9b8c2a2 476
Richard_Xiong 0:1855e9b8c2a2 477 USB_INT32S Host_CtrlSend ( USB_INT08U bm_request_type,
Richard_Xiong 0:1855e9b8c2a2 478 USB_INT08U b_request,
Richard_Xiong 0:1855e9b8c2a2 479 USB_INT16U w_value,
Richard_Xiong 0:1855e9b8c2a2 480 USB_INT16U w_index,
Richard_Xiong 0:1855e9b8c2a2 481 USB_INT16U w_length,
Richard_Xiong 0:1855e9b8c2a2 482 volatile USB_INT08U *buffer)
Richard_Xiong 0:1855e9b8c2a2 483 {
Richard_Xiong 0:1855e9b8c2a2 484 USB_INT32S rc;
Richard_Xiong 0:1855e9b8c2a2 485
Richard_Xiong 0:1855e9b8c2a2 486
Richard_Xiong 0:1855e9b8c2a2 487 Host_FillSetup(bm_request_type, b_request, w_value, w_index, w_length);
Richard_Xiong 0:1855e9b8c2a2 488
Richard_Xiong 0:1855e9b8c2a2 489 rc = Host_ProcessTD(EDCtrl, TD_SETUP, TDBuffer, 8);
Richard_Xiong 0:1855e9b8c2a2 490 if (rc == OK) {
Richard_Xiong 0:1855e9b8c2a2 491 if (w_length) {
Richard_Xiong 0:1855e9b8c2a2 492 rc = Host_ProcessTD(EDCtrl, TD_OUT, TDBuffer, w_length);
Richard_Xiong 0:1855e9b8c2a2 493 }
Richard_Xiong 0:1855e9b8c2a2 494 if (rc == OK) {
Richard_Xiong 0:1855e9b8c2a2 495 rc = Host_ProcessTD(EDCtrl, TD_IN, NULL, 0);
Richard_Xiong 0:1855e9b8c2a2 496 }
Richard_Xiong 0:1855e9b8c2a2 497 }
Richard_Xiong 0:1855e9b8c2a2 498 return (rc);
Richard_Xiong 0:1855e9b8c2a2 499 }
Richard_Xiong 0:1855e9b8c2a2 500
Richard_Xiong 0:1855e9b8c2a2 501 /*
Richard_Xiong 0:1855e9b8c2a2 502 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 503 * FILL SETUP PACKET
Richard_Xiong 0:1855e9b8c2a2 504 *
Richard_Xiong 0:1855e9b8c2a2 505 * Description: This function is used to fill the setup packet
Richard_Xiong 0:1855e9b8c2a2 506 *
Richard_Xiong 0:1855e9b8c2a2 507 * Arguments : None
Richard_Xiong 0:1855e9b8c2a2 508 *
Richard_Xiong 0:1855e9b8c2a2 509 * Returns : OK if Success
Richard_Xiong 0:1855e9b8c2a2 510 * ERR_INVALID_BOOTSIG if Failed
Richard_Xiong 0:1855e9b8c2a2 511 *
Richard_Xiong 0:1855e9b8c2a2 512 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 513 */
Richard_Xiong 0:1855e9b8c2a2 514
Richard_Xiong 0:1855e9b8c2a2 515 void Host_FillSetup (USB_INT08U bm_request_type,
Richard_Xiong 0:1855e9b8c2a2 516 USB_INT08U b_request,
Richard_Xiong 0:1855e9b8c2a2 517 USB_INT16U w_value,
Richard_Xiong 0:1855e9b8c2a2 518 USB_INT16U w_index,
Richard_Xiong 0:1855e9b8c2a2 519 USB_INT16U w_length)
Richard_Xiong 0:1855e9b8c2a2 520 {
Richard_Xiong 0:1855e9b8c2a2 521 int i;
Richard_Xiong 0:1855e9b8c2a2 522 for (i=0;i<w_length;i++)
Richard_Xiong 0:1855e9b8c2a2 523 TDBuffer[i] = 0;
Richard_Xiong 0:1855e9b8c2a2 524
Richard_Xiong 0:1855e9b8c2a2 525 TDBuffer[0] = bm_request_type;
Richard_Xiong 0:1855e9b8c2a2 526 TDBuffer[1] = b_request;
Richard_Xiong 0:1855e9b8c2a2 527 WriteLE16U(&TDBuffer[2], w_value);
Richard_Xiong 0:1855e9b8c2a2 528 WriteLE16U(&TDBuffer[4], w_index);
Richard_Xiong 0:1855e9b8c2a2 529 WriteLE16U(&TDBuffer[6], w_length);
Richard_Xiong 0:1855e9b8c2a2 530 }
Richard_Xiong 0:1855e9b8c2a2 531
Richard_Xiong 0:1855e9b8c2a2 532
Richard_Xiong 0:1855e9b8c2a2 533
Richard_Xiong 0:1855e9b8c2a2 534 /*
Richard_Xiong 0:1855e9b8c2a2 535 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 536 * INITIALIZE THE TRANSFER DESCRIPTOR
Richard_Xiong 0:1855e9b8c2a2 537 *
Richard_Xiong 0:1855e9b8c2a2 538 * Description: This function initializes transfer descriptor
Richard_Xiong 0:1855e9b8c2a2 539 *
Richard_Xiong 0:1855e9b8c2a2 540 * Arguments : Pointer to TD structure
Richard_Xiong 0:1855e9b8c2a2 541 *
Richard_Xiong 0:1855e9b8c2a2 542 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 543 *
Richard_Xiong 0:1855e9b8c2a2 544 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 545 */
Richard_Xiong 0:1855e9b8c2a2 546
Richard_Xiong 0:1855e9b8c2a2 547 void Host_TDInit (volatile HCTD *td)
Richard_Xiong 0:1855e9b8c2a2 548 {
Richard_Xiong 0:1855e9b8c2a2 549
Richard_Xiong 0:1855e9b8c2a2 550 td->Control = 0;
Richard_Xiong 0:1855e9b8c2a2 551 td->CurrBufPtr = 0;
Richard_Xiong 0:1855e9b8c2a2 552 td->Next = 0;
Richard_Xiong 0:1855e9b8c2a2 553 td->BufEnd = 0;
Richard_Xiong 0:1855e9b8c2a2 554 }
Richard_Xiong 0:1855e9b8c2a2 555
Richard_Xiong 0:1855e9b8c2a2 556 /*
Richard_Xiong 0:1855e9b8c2a2 557 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 558 * INITIALIZE THE ENDPOINT DESCRIPTOR
Richard_Xiong 0:1855e9b8c2a2 559 *
Richard_Xiong 0:1855e9b8c2a2 560 * Description: This function initializes endpoint descriptor
Richard_Xiong 0:1855e9b8c2a2 561 *
Richard_Xiong 0:1855e9b8c2a2 562 * Arguments : Pointer to ED strcuture
Richard_Xiong 0:1855e9b8c2a2 563 *
Richard_Xiong 0:1855e9b8c2a2 564 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 565 *
Richard_Xiong 0:1855e9b8c2a2 566 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 567 */
Richard_Xiong 0:1855e9b8c2a2 568
Richard_Xiong 0:1855e9b8c2a2 569 void Host_EDInit (volatile HCED *ed)
Richard_Xiong 0:1855e9b8c2a2 570 {
Richard_Xiong 0:1855e9b8c2a2 571
Richard_Xiong 0:1855e9b8c2a2 572 ed->Control = 0;
Richard_Xiong 0:1855e9b8c2a2 573 ed->TailTd = 0;
Richard_Xiong 0:1855e9b8c2a2 574 ed->HeadTd = 0;
Richard_Xiong 0:1855e9b8c2a2 575 ed->Next = 0;
Richard_Xiong 0:1855e9b8c2a2 576 }
Richard_Xiong 0:1855e9b8c2a2 577
Richard_Xiong 0:1855e9b8c2a2 578 /*
Richard_Xiong 0:1855e9b8c2a2 579 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 580 * INITIALIZE HOST CONTROLLER COMMUNICATIONS AREA
Richard_Xiong 0:1855e9b8c2a2 581 *
Richard_Xiong 0:1855e9b8c2a2 582 * Description: This function initializes host controller communications area
Richard_Xiong 0:1855e9b8c2a2 583 *
Richard_Xiong 0:1855e9b8c2a2 584 * Arguments : Pointer to HCCA
Richard_Xiong 0:1855e9b8c2a2 585 *
Richard_Xiong 0:1855e9b8c2a2 586 * Returns :
Richard_Xiong 0:1855e9b8c2a2 587 *
Richard_Xiong 0:1855e9b8c2a2 588 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 589 */
Richard_Xiong 0:1855e9b8c2a2 590
Richard_Xiong 0:1855e9b8c2a2 591 void Host_HCCAInit (volatile HCCA *hcca)
Richard_Xiong 0:1855e9b8c2a2 592 {
Richard_Xiong 0:1855e9b8c2a2 593 USB_INT32U i;
Richard_Xiong 0:1855e9b8c2a2 594
Richard_Xiong 0:1855e9b8c2a2 595
Richard_Xiong 0:1855e9b8c2a2 596 for (i = 0; i < 32; i++) {
Richard_Xiong 0:1855e9b8c2a2 597
Richard_Xiong 0:1855e9b8c2a2 598 hcca->IntTable[i] = 0;
Richard_Xiong 0:1855e9b8c2a2 599 hcca->FrameNumber = 0;
Richard_Xiong 0:1855e9b8c2a2 600 hcca->DoneHead = 0;
Richard_Xiong 0:1855e9b8c2a2 601 }
Richard_Xiong 0:1855e9b8c2a2 602
Richard_Xiong 0:1855e9b8c2a2 603 }
Richard_Xiong 0:1855e9b8c2a2 604
Richard_Xiong 0:1855e9b8c2a2 605 /*
Richard_Xiong 0:1855e9b8c2a2 606 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 607 * WAIT FOR WDH INTERRUPT
Richard_Xiong 0:1855e9b8c2a2 608 *
Richard_Xiong 0:1855e9b8c2a2 609 * Description: This function is infinite loop which breaks when ever a WDH interrupt rises
Richard_Xiong 0:1855e9b8c2a2 610 *
Richard_Xiong 0:1855e9b8c2a2 611 * Arguments : None
Richard_Xiong 0:1855e9b8c2a2 612 *
Richard_Xiong 0:1855e9b8c2a2 613 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 614 *
Richard_Xiong 0:1855e9b8c2a2 615 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 616 */
Richard_Xiong 0:1855e9b8c2a2 617
Richard_Xiong 0:1855e9b8c2a2 618 void Host_WDHWait (void)
Richard_Xiong 0:1855e9b8c2a2 619 {
Richard_Xiong 0:1855e9b8c2a2 620 while (!HOST_WdhIntr)
Richard_Xiong 0:1855e9b8c2a2 621 __WFI();
Richard_Xiong 0:1855e9b8c2a2 622
Richard_Xiong 0:1855e9b8c2a2 623 HOST_WdhIntr = 0;
Richard_Xiong 0:1855e9b8c2a2 624 }
Richard_Xiong 0:1855e9b8c2a2 625
Richard_Xiong 0:1855e9b8c2a2 626 /*
Richard_Xiong 0:1855e9b8c2a2 627 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 628 * READ LE 32U
Richard_Xiong 0:1855e9b8c2a2 629 *
Richard_Xiong 0:1855e9b8c2a2 630 * Description: This function is used to read an unsigned integer from a character buffer in the platform
Richard_Xiong 0:1855e9b8c2a2 631 * containing little endian processor
Richard_Xiong 0:1855e9b8c2a2 632 *
Richard_Xiong 0:1855e9b8c2a2 633 * Arguments : pmem Pointer to the character buffer
Richard_Xiong 0:1855e9b8c2a2 634 *
Richard_Xiong 0:1855e9b8c2a2 635 * Returns : val Unsigned integer
Richard_Xiong 0:1855e9b8c2a2 636 *
Richard_Xiong 0:1855e9b8c2a2 637 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 638 */
Richard_Xiong 0:1855e9b8c2a2 639
Richard_Xiong 0:1855e9b8c2a2 640 USB_INT32U ReadLE32U (volatile USB_INT08U *pmem)
Richard_Xiong 0:1855e9b8c2a2 641 {
Richard_Xiong 0:1855e9b8c2a2 642 USB_INT32U val = *(USB_INT32U*)pmem;
Richard_Xiong 0:1855e9b8c2a2 643 #ifdef __BIG_ENDIAN
Richard_Xiong 0:1855e9b8c2a2 644 return __REV(val);
Richard_Xiong 0:1855e9b8c2a2 645 #else
Richard_Xiong 0:1855e9b8c2a2 646 return val;
Richard_Xiong 0:1855e9b8c2a2 647 #endif
Richard_Xiong 0:1855e9b8c2a2 648 }
Richard_Xiong 0:1855e9b8c2a2 649
Richard_Xiong 0:1855e9b8c2a2 650 /*
Richard_Xiong 0:1855e9b8c2a2 651 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 652 * WRITE LE 32U
Richard_Xiong 0:1855e9b8c2a2 653 *
Richard_Xiong 0:1855e9b8c2a2 654 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
Richard_Xiong 0:1855e9b8c2a2 655 * containing little endian processor.
Richard_Xiong 0:1855e9b8c2a2 656 *
Richard_Xiong 0:1855e9b8c2a2 657 * Arguments : pmem Pointer to the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 658 * val Integer value to be placed in the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 659 *
Richard_Xiong 0:1855e9b8c2a2 660 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 661 *
Richard_Xiong 0:1855e9b8c2a2 662 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 663 */
Richard_Xiong 0:1855e9b8c2a2 664
Richard_Xiong 0:1855e9b8c2a2 665 void WriteLE32U (volatile USB_INT08U *pmem,
Richard_Xiong 0:1855e9b8c2a2 666 USB_INT32U val)
Richard_Xiong 0:1855e9b8c2a2 667 {
Richard_Xiong 0:1855e9b8c2a2 668 #ifdef __BIG_ENDIAN
Richard_Xiong 0:1855e9b8c2a2 669 *(USB_INT32U*)pmem = __REV(val);
Richard_Xiong 0:1855e9b8c2a2 670 #else
Richard_Xiong 0:1855e9b8c2a2 671 *(USB_INT32U*)pmem = val;
Richard_Xiong 0:1855e9b8c2a2 672 #endif
Richard_Xiong 0:1855e9b8c2a2 673 }
Richard_Xiong 0:1855e9b8c2a2 674
Richard_Xiong 0:1855e9b8c2a2 675 /*
Richard_Xiong 0:1855e9b8c2a2 676 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 677 * READ LE 16U
Richard_Xiong 0:1855e9b8c2a2 678 *
Richard_Xiong 0:1855e9b8c2a2 679 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
Richard_Xiong 0:1855e9b8c2a2 680 * containing little endian processor
Richard_Xiong 0:1855e9b8c2a2 681 *
Richard_Xiong 0:1855e9b8c2a2 682 * Arguments : pmem Pointer to the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 683 *
Richard_Xiong 0:1855e9b8c2a2 684 * Returns : val Unsigned short integer
Richard_Xiong 0:1855e9b8c2a2 685 *
Richard_Xiong 0:1855e9b8c2a2 686 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 687 */
Richard_Xiong 0:1855e9b8c2a2 688
Richard_Xiong 0:1855e9b8c2a2 689 USB_INT16U ReadLE16U (volatile USB_INT08U *pmem)
Richard_Xiong 0:1855e9b8c2a2 690 {
Richard_Xiong 0:1855e9b8c2a2 691 USB_INT16U val = *(USB_INT16U*)pmem;
Richard_Xiong 0:1855e9b8c2a2 692 #ifdef __BIG_ENDIAN
Richard_Xiong 0:1855e9b8c2a2 693 return __REV16(val);
Richard_Xiong 0:1855e9b8c2a2 694 #else
Richard_Xiong 0:1855e9b8c2a2 695 return val;
Richard_Xiong 0:1855e9b8c2a2 696 #endif
Richard_Xiong 0:1855e9b8c2a2 697 }
Richard_Xiong 0:1855e9b8c2a2 698
Richard_Xiong 0:1855e9b8c2a2 699 /*
Richard_Xiong 0:1855e9b8c2a2 700 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 701 * WRITE LE 16U
Richard_Xiong 0:1855e9b8c2a2 702 *
Richard_Xiong 0:1855e9b8c2a2 703 * Description: This function is used to write an unsigned short integer into a charecter buffer in the
Richard_Xiong 0:1855e9b8c2a2 704 * platform containing little endian processor
Richard_Xiong 0:1855e9b8c2a2 705 *
Richard_Xiong 0:1855e9b8c2a2 706 * Arguments : pmem Pointer to the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 707 * val Value to be placed in the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 708 *
Richard_Xiong 0:1855e9b8c2a2 709 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 710 *
Richard_Xiong 0:1855e9b8c2a2 711 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 712 */
Richard_Xiong 0:1855e9b8c2a2 713
Richard_Xiong 0:1855e9b8c2a2 714 void WriteLE16U (volatile USB_INT08U *pmem,
Richard_Xiong 0:1855e9b8c2a2 715 USB_INT16U val)
Richard_Xiong 0:1855e9b8c2a2 716 {
Richard_Xiong 0:1855e9b8c2a2 717 #ifdef __BIG_ENDIAN
Richard_Xiong 0:1855e9b8c2a2 718 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
Richard_Xiong 0:1855e9b8c2a2 719 #else
Richard_Xiong 0:1855e9b8c2a2 720 *(USB_INT16U*)pmem = val;
Richard_Xiong 0:1855e9b8c2a2 721 #endif
Richard_Xiong 0:1855e9b8c2a2 722 }
Richard_Xiong 0:1855e9b8c2a2 723
Richard_Xiong 0:1855e9b8c2a2 724 /*
Richard_Xiong 0:1855e9b8c2a2 725 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 726 * READ BE 32U
Richard_Xiong 0:1855e9b8c2a2 727 *
Richard_Xiong 0:1855e9b8c2a2 728 * Description: This function is used to read an unsigned integer from a charecter buffer in the platform
Richard_Xiong 0:1855e9b8c2a2 729 * containing big endian processor
Richard_Xiong 0:1855e9b8c2a2 730 *
Richard_Xiong 0:1855e9b8c2a2 731 * Arguments : pmem Pointer to the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 732 *
Richard_Xiong 0:1855e9b8c2a2 733 * Returns : val Unsigned integer
Richard_Xiong 0:1855e9b8c2a2 734 *
Richard_Xiong 0:1855e9b8c2a2 735 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 736 */
Richard_Xiong 0:1855e9b8c2a2 737
Richard_Xiong 0:1855e9b8c2a2 738 USB_INT32U ReadBE32U (volatile USB_INT08U *pmem)
Richard_Xiong 0:1855e9b8c2a2 739 {
Richard_Xiong 0:1855e9b8c2a2 740 USB_INT32U val = *(USB_INT32U*)pmem;
Richard_Xiong 0:1855e9b8c2a2 741 #ifdef __BIG_ENDIAN
Richard_Xiong 0:1855e9b8c2a2 742 return val;
Richard_Xiong 0:1855e9b8c2a2 743 #else
Richard_Xiong 0:1855e9b8c2a2 744 return __REV(val);
Richard_Xiong 0:1855e9b8c2a2 745 #endif
Richard_Xiong 0:1855e9b8c2a2 746 }
Richard_Xiong 0:1855e9b8c2a2 747
Richard_Xiong 0:1855e9b8c2a2 748 /*
Richard_Xiong 0:1855e9b8c2a2 749 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 750 * WRITE BE 32U
Richard_Xiong 0:1855e9b8c2a2 751 *
Richard_Xiong 0:1855e9b8c2a2 752 * Description: This function is used to write an unsigned integer into a charecter buffer in the platform
Richard_Xiong 0:1855e9b8c2a2 753 * containing big endian processor
Richard_Xiong 0:1855e9b8c2a2 754 *
Richard_Xiong 0:1855e9b8c2a2 755 * Arguments : pmem Pointer to the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 756 * val Value to be placed in the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 757 *
Richard_Xiong 0:1855e9b8c2a2 758 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 759 *
Richard_Xiong 0:1855e9b8c2a2 760 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 761 */
Richard_Xiong 0:1855e9b8c2a2 762
Richard_Xiong 0:1855e9b8c2a2 763 void WriteBE32U (volatile USB_INT08U *pmem,
Richard_Xiong 0:1855e9b8c2a2 764 USB_INT32U val)
Richard_Xiong 0:1855e9b8c2a2 765 {
Richard_Xiong 0:1855e9b8c2a2 766 #ifdef __BIG_ENDIAN
Richard_Xiong 0:1855e9b8c2a2 767 *(USB_INT32U*)pmem = val;
Richard_Xiong 0:1855e9b8c2a2 768 #else
Richard_Xiong 0:1855e9b8c2a2 769 *(USB_INT32U*)pmem = __REV(val);
Richard_Xiong 0:1855e9b8c2a2 770 #endif
Richard_Xiong 0:1855e9b8c2a2 771 }
Richard_Xiong 0:1855e9b8c2a2 772
Richard_Xiong 0:1855e9b8c2a2 773 /*
Richard_Xiong 0:1855e9b8c2a2 774 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 775 * READ BE 16U
Richard_Xiong 0:1855e9b8c2a2 776 *
Richard_Xiong 0:1855e9b8c2a2 777 * Description: This function is used to read an unsigned short integer from a charecter buffer in the platform
Richard_Xiong 0:1855e9b8c2a2 778 * containing big endian processor
Richard_Xiong 0:1855e9b8c2a2 779 *
Richard_Xiong 0:1855e9b8c2a2 780 * Arguments : pmem Pointer to the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 781 *
Richard_Xiong 0:1855e9b8c2a2 782 * Returns : val Unsigned short integer
Richard_Xiong 0:1855e9b8c2a2 783 *
Richard_Xiong 0:1855e9b8c2a2 784 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 785 */
Richard_Xiong 0:1855e9b8c2a2 786
Richard_Xiong 0:1855e9b8c2a2 787 USB_INT16U ReadBE16U (volatile USB_INT08U *pmem)
Richard_Xiong 0:1855e9b8c2a2 788 {
Richard_Xiong 0:1855e9b8c2a2 789 USB_INT16U val = *(USB_INT16U*)pmem;
Richard_Xiong 0:1855e9b8c2a2 790 #ifdef __BIG_ENDIAN
Richard_Xiong 0:1855e9b8c2a2 791 return val;
Richard_Xiong 0:1855e9b8c2a2 792 #else
Richard_Xiong 0:1855e9b8c2a2 793 return __REV16(val);
Richard_Xiong 0:1855e9b8c2a2 794 #endif
Richard_Xiong 0:1855e9b8c2a2 795 }
Richard_Xiong 0:1855e9b8c2a2 796
Richard_Xiong 0:1855e9b8c2a2 797 /*
Richard_Xiong 0:1855e9b8c2a2 798 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 799 * WRITE BE 16U
Richard_Xiong 0:1855e9b8c2a2 800 *
Richard_Xiong 0:1855e9b8c2a2 801 * Description: This function is used to write an unsigned short integer into the charecter buffer in the
Richard_Xiong 0:1855e9b8c2a2 802 * platform containing big endian processor
Richard_Xiong 0:1855e9b8c2a2 803 *
Richard_Xiong 0:1855e9b8c2a2 804 * Arguments : pmem Pointer to the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 805 * val Value to be placed in the charecter buffer
Richard_Xiong 0:1855e9b8c2a2 806 *
Richard_Xiong 0:1855e9b8c2a2 807 * Returns : None
Richard_Xiong 0:1855e9b8c2a2 808 *
Richard_Xiong 0:1855e9b8c2a2 809 **************************************************************************************************************
Richard_Xiong 0:1855e9b8c2a2 810 */
Richard_Xiong 0:1855e9b8c2a2 811
Richard_Xiong 0:1855e9b8c2a2 812 void WriteBE16U (volatile USB_INT08U *pmem,
Richard_Xiong 0:1855e9b8c2a2 813 USB_INT16U val)
Richard_Xiong 0:1855e9b8c2a2 814 {
Richard_Xiong 0:1855e9b8c2a2 815 #ifdef __BIG_ENDIAN
Richard_Xiong 0:1855e9b8c2a2 816 *(USB_INT16U*)pmem = val;
Richard_Xiong 0:1855e9b8c2a2 817 #else
Richard_Xiong 0:1855e9b8c2a2 818 *(USB_INT16U*)pmem = (__REV16(val) & 0xFFFF);
Richard_Xiong 0:1855e9b8c2a2 819 #endif
Richard_Xiong 0:1855e9b8c2a2 820 }