Poor-man's logic analyzer
Page last updated 08 Nov 2014, by 
Motoo Tanaka.
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Motoo Tanaka.
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While playing with FRDM and mbed, I wrote a simple sampling program to poll gpios and write the data through the serial. And on my PC, I wrote a simple wave form display using vt100 esc-sequence. Which ended up a poor-man's logic analyzer, still a lot to improve, though... In this picture a 4bit CPU designed with an Altera FPGA are running 3min timer and FRDM-KL25Z is proving PC[3:0] and data[7:0].
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