RETRO ROBOT E
Dependents: RETRO_ROBOT_SC16IS750E
Fork of SC16IS750 by
SC16IS750.cpp@3:9783b6bde958, 2014-02-20 (annotated)
- Committer:
- wim
- Date:
- Thu Feb 20 19:37:55 2014 +0000
- Revision:
- 3:9783b6bde958
- Parent:
- 2:76cb93b511f2
- Child:
- 4:12446ee9f9c8
SC16IS750 SPI or I2C to UART Bridge (First Release)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
wim | 3:9783b6bde958 | 1 | /* SC16IS750 I2C or SPI to UART bridge |
wim | 3:9783b6bde958 | 2 | * v0.1 WH, Nov 2013, Sparkfun WiFly Shield code library alpha 0 used as example, Added I2C I/F and many more methods. |
wim | 3:9783b6bde958 | 3 | * https://forum.sparkfun.com/viewtopic.php?f=13&t=21846 |
wim | 0:d64854a60f95 | 4 | * |
wim | 0:d64854a60f95 | 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy of this software |
wim | 0:d64854a60f95 | 6 | * and associated documentation files (the "Software"), to deal in the Software without restriction, |
wim | 0:d64854a60f95 | 7 | * including without limitation the rights to use, copy, modify, merge, publish, distribute, |
wim | 0:d64854a60f95 | 8 | * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is |
wim | 0:d64854a60f95 | 9 | * furnished to do so, subject to the following conditions: |
wim | 0:d64854a60f95 | 10 | * |
wim | 0:d64854a60f95 | 11 | * The above copyright notice and this permission notice shall be included in all copies or |
wim | 0:d64854a60f95 | 12 | * substantial portions of the Software. |
wim | 0:d64854a60f95 | 13 | * |
wim | 0:d64854a60f95 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING |
wim | 0:d64854a60f95 | 15 | * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
wim | 0:d64854a60f95 | 16 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
wim | 0:d64854a60f95 | 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
wim | 0:d64854a60f95 | 18 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
wim | 0:d64854a60f95 | 19 | */ |
wim | 0:d64854a60f95 | 20 | #include "mbed.h" |
wim | 0:d64854a60f95 | 21 | #include "SC16IS750.h" |
wim | 0:d64854a60f95 | 22 | |
wim | 3:9783b6bde958 | 23 | #define ENABLE_BULK_TRANSFERS 1 |
wim | 3:9783b6bde958 | 24 | #define BULK_BLOCK_LEN 16 |
wim | 0:d64854a60f95 | 25 | |
wim | 0:d64854a60f95 | 26 | /** Abstract class SC16IS750 for converter between either SPI or I2C and a Serial port |
wim | 1:0440152c5387 | 27 | * Constructor for this Abstract Class is protected |
wim | 0:d64854a60f95 | 28 | * Supports both SPI and I2C interfaces through derived classes |
wim | 0:d64854a60f95 | 29 | * |
wim | 0:d64854a60f95 | 30 | * @code |
wim | 0:d64854a60f95 | 31 | * |
wim | 0:d64854a60f95 | 32 | * @endcode |
wim | 0:d64854a60f95 | 33 | */ |
wim | 3:9783b6bde958 | 34 | SC16IS750::SC16IS750() { |
wim | 3:9783b6bde958 | 35 | //SC16IS750::SC16IS750() : Serial(NC, NC) { //Fout, mag geen NC zijn |
wim | 3:9783b6bde958 | 36 | //SC16IS750::SC16IS750() : SerialBase(NC, NC) { //Fout, mag geen NC zijn |
wim | 1:0440152c5387 | 37 | // Dont call _init() here since the SPI or I2C port have not yet been configured... |
wim | 1:0440152c5387 | 38 | //_init(); // initialise UART registers |
wim | 0:d64854a60f95 | 39 | } |
wim | 0:d64854a60f95 | 40 | |
wim | 0:d64854a60f95 | 41 | |
wim | 0:d64854a60f95 | 42 | /** Set baudrate of the serial port. |
wim | 0:d64854a60f95 | 43 | * @param baud integer baudrate (4800, 9600 etc) |
wim | 0:d64854a60f95 | 44 | * @return none |
wim | 0:d64854a60f95 | 45 | */ |
wim | 0:d64854a60f95 | 46 | void SC16IS750::baud(int baudrate) { |
wim | 2:76cb93b511f2 | 47 | unsigned long divisor = SC16IS750_BAUDRATE_DIVISOR(baudrate); |
wim | 0:d64854a60f95 | 48 | char lcr_tmp; |
wim | 0:d64854a60f95 | 49 | |
wim | 0:d64854a60f95 | 50 | _config.baudrate = baudrate; // Save baudrate |
wim | 0:d64854a60f95 | 51 | |
wim | 0:d64854a60f95 | 52 | lcr_tmp = this->readRegister(LCR); // Read current LCR register |
wim | 1:0440152c5387 | 53 | this->writeRegister(LCR, lcr_tmp | LCR_ENABLE_DIV); // Enable Divisor registers |
wim | 0:d64854a60f95 | 54 | this->writeRegister(DLL, ( divisor & 0xFF)); // write divisor LSB |
wim | 0:d64854a60f95 | 55 | this->writeRegister(DLH, ((divisor >> 8) & 0xFF)); // write divisor MSB |
wim | 0:d64854a60f95 | 56 | this->writeRegister(LCR, lcr_tmp); // Restore LCR register, activate regular RBR, THR and IER registers |
wim | 1:0440152c5387 | 57 | |
wim | 0:d64854a60f95 | 58 | } |
wim | 0:d64854a60f95 | 59 | |
wim | 0:d64854a60f95 | 60 | |
wim | 0:d64854a60f95 | 61 | /** Set the transmission format used by the serial port. |
wim | 0:d64854a60f95 | 62 | * @param bits The number of bits in a word (5-8; default = 8) |
wim | 0:d64854a60f95 | 63 | * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None) |
wim | 0:d64854a60f95 | 64 | * @param stop_bits The number of stop bits (1 or 2; default = 1) |
wim | 2:76cb93b511f2 | 65 | * @return none |
wim | 0:d64854a60f95 | 66 | */ |
wim | 0:d64854a60f95 | 67 | void SC16IS750::format(int bits, Serial::Parity parity, int stop_bits) { |
wim | 0:d64854a60f95 | 68 | char lcr_tmp = 0x00; |
wim | 0:d64854a60f95 | 69 | |
wim | 0:d64854a60f95 | 70 | switch (bits) { |
wim | 0:d64854a60f95 | 71 | case 5: lcr_tmp |= LCR_BITS5; |
wim | 0:d64854a60f95 | 72 | break; |
wim | 0:d64854a60f95 | 73 | case 6: lcr_tmp |= LCR_BITS6; |
wim | 0:d64854a60f95 | 74 | break; |
wim | 0:d64854a60f95 | 75 | case 7: lcr_tmp |= LCR_BITS7; |
wim | 0:d64854a60f95 | 76 | break; |
wim | 0:d64854a60f95 | 77 | case 8: lcr_tmp |= LCR_BITS8; |
wim | 0:d64854a60f95 | 78 | break; |
wim | 0:d64854a60f95 | 79 | default: lcr_tmp |= LCR_BITS8; |
wim | 0:d64854a60f95 | 80 | } |
wim | 0:d64854a60f95 | 81 | |
wim | 0:d64854a60f95 | 82 | switch (parity) { |
wim | 0:d64854a60f95 | 83 | case Serial::None: lcr_tmp |= LCR_NONE; |
wim | 0:d64854a60f95 | 84 | break; |
wim | 0:d64854a60f95 | 85 | case Serial::Odd: lcr_tmp |= LCR_ODD; |
wim | 0:d64854a60f95 | 86 | break; |
wim | 0:d64854a60f95 | 87 | case Serial::Even: lcr_tmp |= LCR_EVEN; |
wim | 0:d64854a60f95 | 88 | break; |
wim | 0:d64854a60f95 | 89 | case Serial::Forced1: lcr_tmp |= LCR_FORCED1; |
wim | 0:d64854a60f95 | 90 | break; |
wim | 0:d64854a60f95 | 91 | case Serial::Forced0: lcr_tmp |= LCR_FORCED0; |
wim | 0:d64854a60f95 | 92 | break; |
wim | 0:d64854a60f95 | 93 | default: lcr_tmp |= LCR_NONE; |
wim | 0:d64854a60f95 | 94 | } |
wim | 0:d64854a60f95 | 95 | |
wim | 0:d64854a60f95 | 96 | switch (stop_bits) { |
wim | 0:d64854a60f95 | 97 | case 1: lcr_tmp |= LCR_BITS1; |
wim | 0:d64854a60f95 | 98 | break; |
wim | 0:d64854a60f95 | 99 | case 2: lcr_tmp |= LCR_BITS2; |
wim | 0:d64854a60f95 | 100 | break; |
wim | 0:d64854a60f95 | 101 | default: lcr_tmp |= LCR_BITS1; |
wim | 0:d64854a60f95 | 102 | } |
wim | 0:d64854a60f95 | 103 | |
wim | 0:d64854a60f95 | 104 | _config.dataformat = lcr_tmp; // Save dataformat |
wim | 0:d64854a60f95 | 105 | |
wim | 0:d64854a60f95 | 106 | this->writeRegister(LCR, lcr_tmp); // Set LCR register, activate regular RBR, THR and IER registers |
wim | 0:d64854a60f95 | 107 | |
wim | 0:d64854a60f95 | 108 | }; |
wim | 0:d64854a60f95 | 109 | |
wim | 1:0440152c5387 | 110 | /** Generate a break condition on the serial line |
wim | 2:76cb93b511f2 | 111 | * @return none |
wim | 1:0440152c5387 | 112 | */ |
wim | 1:0440152c5387 | 113 | void SC16IS750::send_break() { |
wim | 1:0440152c5387 | 114 | // Wait for 1.5 frames before clearing the break condition |
wim | 1:0440152c5387 | 115 | // This will have different effects on our platforms, but should |
wim | 1:0440152c5387 | 116 | // ensure that we keep the break active for at least one frame. |
wim | 1:0440152c5387 | 117 | // We consider a full frame (1 start bit + 8 data bits bits + |
wim | 1:0440152c5387 | 118 | // 1 parity bit + 2 stop bits = 12 bits) for computation. |
wim | 1:0440152c5387 | 119 | // One bit time (in us) = 1000000/_baud |
wim | 1:0440152c5387 | 120 | // Twelve bits: 12000000/baud delay |
wim | 1:0440152c5387 | 121 | // 1.5 frames: 18000000/baud delay |
wim | 1:0440152c5387 | 122 | set_break(true); |
wim | 1:0440152c5387 | 123 | wait_us(18000000/_config.baudrate); |
wim | 1:0440152c5387 | 124 | set_break(false); |
wim | 1:0440152c5387 | 125 | }; |
wim | 1:0440152c5387 | 126 | |
wim | 1:0440152c5387 | 127 | /** Set a break condition on the serial line |
wim | 1:0440152c5387 | 128 | * @param enable break condition |
wim | 2:76cb93b511f2 | 129 | * @return none |
wim | 1:0440152c5387 | 130 | */ |
wim | 1:0440152c5387 | 131 | void SC16IS750::set_break(bool enable) { |
wim | 0:d64854a60f95 | 132 | |
wim | 1:0440152c5387 | 133 | if (enable) { |
wim | 1:0440152c5387 | 134 | _config.dataformat |= LCR_BRK_ENA; // Save dataformat |
wim | 1:0440152c5387 | 135 | } |
wim | 1:0440152c5387 | 136 | else { |
wim | 1:0440152c5387 | 137 | _config.dataformat &= ~LCR_BRK_ENA; // Save dataformat |
wim | 1:0440152c5387 | 138 | } |
wim | 1:0440152c5387 | 139 | |
wim | 1:0440152c5387 | 140 | this->writeRegister(LCR, _config.dataformat); // Set LCR register |
wim | 1:0440152c5387 | 141 | } |
wim | 1:0440152c5387 | 142 | |
wim | 1:0440152c5387 | 143 | /** Set the flow control type on the serial port |
wim | 1:0440152c5387 | 144 | * Added for compatibility with Serial Class. |
wim | 1:0440152c5387 | 145 | * SC16IS750 supports only Flow, Pins can not be selected. |
wim | 3:9783b6bde958 | 146 | * This method sets hardware flow control. SC16IS750 supports XON/XOFF, but this is not implemented. |
wim | 0:d64854a60f95 | 147 | * |
wim | 1:0440152c5387 | 148 | * @param type the flow control type (Disabled, RTS, CTS, RTSCTS) |
wim | 2:76cb93b511f2 | 149 | * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS) - NOT USED |
wim | 2:76cb93b511f2 | 150 | * @param flow2 the second flow control pin (CTS for RTSCTS) - NOT USED |
wim | 2:76cb93b511f2 | 151 | * @return none |
wim | 0:d64854a60f95 | 152 | */ |
wim | 1:0440152c5387 | 153 | void SC16IS750::set_flow_control(Flow type, PinName flow1, PinName flow2) { |
wim | 1:0440152c5387 | 154 | char lcr_tmp; |
wim | 1:0440152c5387 | 155 | char efr_tmp = 0x00; |
wim | 1:0440152c5387 | 156 | |
wim | 1:0440152c5387 | 157 | // We need to enable flow control to prevent overflow of buffers and |
wim | 1:0440152c5387 | 158 | // lose data when used with fast devices like the WiFly. |
wim | 1:0440152c5387 | 159 | |
wim | 1:0440152c5387 | 160 | switch (type) { |
wim | 1:0440152c5387 | 161 | case Disabled : |
wim | 1:0440152c5387 | 162 | break; |
wim | 1:0440152c5387 | 163 | case RTS: efr_tmp = EFR_ENABLE_RTS; |
wim | 1:0440152c5387 | 164 | break; |
wim | 1:0440152c5387 | 165 | case CTS: efr_tmp = EFR_ENABLE_CTS; |
wim | 1:0440152c5387 | 166 | break; |
wim | 1:0440152c5387 | 167 | case RTSCTS: efr_tmp = EFR_ENABLE_RTS | EFR_ENABLE_CTS; |
wim | 1:0440152c5387 | 168 | break; |
wim | 1:0440152c5387 | 169 | default: ; |
wim | 1:0440152c5387 | 170 | |
wim | 1:0440152c5387 | 171 | } |
wim | 1:0440152c5387 | 172 | |
wim | 2:76cb93b511f2 | 173 | //Save flowcontrol mode and enable enhanced functions |
wim | 2:76cb93b511f2 | 174 | _config.flowctrl = efr_tmp | EFR_ENABLE_ENHANCED_FUNCTIONS; |
wim | 1:0440152c5387 | 175 | |
wim | 1:0440152c5387 | 176 | lcr_tmp = this->readRegister(LCR); // save LRC register |
wim | 1:0440152c5387 | 177 | this->writeRegister(LCR, LCR_ENABLE_ENHANCED_FUNCTIONS); // write magic number 0xBF to enable access to EFR register |
wim | 1:0440152c5387 | 178 | this->writeRegister(EFR, _config.flowctrl); // set flow and enable enhanced functions |
wim | 1:0440152c5387 | 179 | this->writeRegister(LCR, lcr_tmp); // restore LCR register |
wim | 1:0440152c5387 | 180 | } |
wim | 2:76cb93b511f2 | 181 | |
wim | 2:76cb93b511f2 | 182 | /** Set the RX FIFO flow control levels |
wim | 3:9783b6bde958 | 183 | * This method sets hardware flow control levels. SC16IS750 supports XON/XOFF, but this is not implemented. |
wim | 2:76cb93b511f2 | 184 | * Should be called BEFORE Auto RTS is enabled. |
wim | 2:76cb93b511f2 | 185 | * |
wim | 2:76cb93b511f2 | 186 | * @param resume trigger level to resume transmission (0..15, meaning 0-60 with a granularity of 4) |
wim | 2:76cb93b511f2 | 187 | * @param halt trigger level to resume transmission (0..15, meaning 0-60 with granularity of 4) |
wim | 2:76cb93b511f2 | 188 | * @return none |
wim | 2:76cb93b511f2 | 189 | */ |
wim | 2:76cb93b511f2 | 190 | void SC16IS750::set_flow_triggers(int resume, int halt) { |
wim | 2:76cb93b511f2 | 191 | |
wim | 2:76cb93b511f2 | 192 | // sanity checks |
wim | 2:76cb93b511f2 | 193 | halt = halt & 0x0F; |
wim | 2:76cb93b511f2 | 194 | resume = resume & 0x0F; |
wim | 2:76cb93b511f2 | 195 | if (halt <= resume) { |
wim | 2:76cb93b511f2 | 196 | halt = TCR_HALT_DEFAULT; |
wim | 2:76cb93b511f2 | 197 | resume = TCR_RESUME_DEFAULT; |
wim | 2:76cb93b511f2 | 198 | } |
wim | 2:76cb93b511f2 | 199 | |
wim | 2:76cb93b511f2 | 200 | // Note: TCR accessible only when EFR[4]=1 and MCR[2]=1 |
wim | 2:76cb93b511f2 | 201 | this->writeRegister(TCR, (resume << 4) | halt); // set TCR register |
wim | 2:76cb93b511f2 | 202 | } |
wim | 2:76cb93b511f2 | 203 | |
wim | 2:76cb93b511f2 | 204 | |
wim | 2:76cb93b511f2 | 205 | /** Set the Modem Control register |
wim | 2:76cb93b511f2 | 206 | * This method sets prescaler, enables TCR and TLR |
wim | 2:76cb93b511f2 | 207 | * |
wim | 2:76cb93b511f2 | 208 | * @param none |
wim | 2:76cb93b511f2 | 209 | * @return none |
wim | 2:76cb93b511f2 | 210 | */ |
wim | 2:76cb93b511f2 | 211 | void SC16IS750::set_modem_control() { |
wim | 2:76cb93b511f2 | 212 | |
wim | 2:76cb93b511f2 | 213 | //Note MCR[7:4] and MCR[2] only accessible when EFR[4] is set |
wim | 2:76cb93b511f2 | 214 | if (SC16IS750_PRESCALER == SC16IS750_PRESCALER_1) { // Default prescaler after reset |
wim | 2:76cb93b511f2 | 215 | this->writeRegister(MCR, MCR_PRESCALE_1 | MCR_ENABLE_TCR_TLR); |
wim | 2:76cb93b511f2 | 216 | } |
wim | 2:76cb93b511f2 | 217 | else { |
wim | 2:76cb93b511f2 | 218 | this->writeRegister(MCR, MCR_PRESCALE_4 | MCR_ENABLE_TCR_TLR); |
wim | 2:76cb93b511f2 | 219 | } |
wim | 2:76cb93b511f2 | 220 | } |
wim | 2:76cb93b511f2 | 221 | |
wim | 1:0440152c5387 | 222 | |
wim | 1:0440152c5387 | 223 | |
wim | 1:0440152c5387 | 224 | /** Initialise internal registers |
wim | 1:0440152c5387 | 225 | * Should be in protection section. Public for testing purposes |
wim | 1:0440152c5387 | 226 | * If initialisation fails this method does not return. |
wim | 1:0440152c5387 | 227 | * @param none |
wim | 1:0440152c5387 | 228 | * @return none |
wim | 1:0440152c5387 | 229 | */ |
wim | 1:0440152c5387 | 230 | void SC16IS750::_init() { |
wim | 0:d64854a60f95 | 231 | |
wim | 0:d64854a60f95 | 232 | // Initialise SC16IS750 |
wim | 0:d64854a60f95 | 233 | |
wim | 1:0440152c5387 | 234 | // Software reset, assuming there is no access to the HW Reset pin |
wim | 1:0440152c5387 | 235 | swReset(); |
wim | 2:76cb93b511f2 | 236 | |
wim | 2:76cb93b511f2 | 237 | // Set default baudrate (depends on prescaler) and save in _config |
wim | 2:76cb93b511f2 | 238 | // DLL/DLH |
wim | 0:d64854a60f95 | 239 | baud(); |
wim | 0:d64854a60f95 | 240 | |
wim | 0:d64854a60f95 | 241 | // Set default dataformat and save in _config |
wim | 1:0440152c5387 | 242 | // LCR |
wim | 0:d64854a60f95 | 243 | format(); |
wim | 0:d64854a60f95 | 244 | |
wim | 2:76cb93b511f2 | 245 | // Set dataflow mode and Enables enhanced functions |
wim | 2:76cb93b511f2 | 246 | // Save in _config |
wim | 2:76cb93b511f2 | 247 | // EFR |
wim | 2:76cb93b511f2 | 248 | set_flow_control(); |
wim | 2:76cb93b511f2 | 249 | |
wim | 2:76cb93b511f2 | 250 | |
wim | 3:9783b6bde958 | 251 | // FIFO control, sets TX and RX IRQ trigger levels and enables FIFO and save in _config |
wim | 2:76cb93b511f2 | 252 | // Note FCR[5:4] only accessible when EFR[4] is set (enhanced functions enable) |
wim | 2:76cb93b511f2 | 253 | // FCR, TLR |
wim | 2:76cb93b511f2 | 254 | set_fifo_control(); |
wim | 2:76cb93b511f2 | 255 | flush(); |
wim | 2:76cb93b511f2 | 256 | |
wim | 2:76cb93b511f2 | 257 | // Modem control, sets prescaler, enable TCR and TLR |
wim | 2:76cb93b511f2 | 258 | // Note MCR[7:4] and MCR[2] only accessible when EFR[4] is set (enhanced functions enable) |
wim | 2:76cb93b511f2 | 259 | set_modem_control(); |
wim | 2:76cb93b511f2 | 260 | |
wim | 2:76cb93b511f2 | 261 | // Set RTS trigger levels |
wim | 2:76cb93b511f2 | 262 | // Note TCR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set |
wim | 2:76cb93b511f2 | 263 | set_flow_triggers(); |
wim | 2:76cb93b511f2 | 264 | |
wim | 2:76cb93b511f2 | 265 | |
wim | 1:0440152c5387 | 266 | // Set default break condition and save in _config |
wim | 1:0440152c5387 | 267 | // LCR |
wim | 1:0440152c5387 | 268 | //set_break(); |
wim | 2:76cb93b511f2 | 269 | |
wim | 0:d64854a60f95 | 270 | // The UART bridge should now be successfully initialised. |
wim | 0:d64854a60f95 | 271 | |
wim | 0:d64854a60f95 | 272 | // Test if UART bridge is present and initialised |
wim | 0:d64854a60f95 | 273 | if(!connected()){ |
wim | 0:d64854a60f95 | 274 | #if(0) |
wim | 0:d64854a60f95 | 275 | // Lock up if we fail to initialise UART bridge. |
wim | 1:0440152c5387 | 276 | while(1) {}; |
wim | 0:d64854a60f95 | 277 | #else |
wim | 0:d64854a60f95 | 278 | printf("Failed to initialise UART bridge\r\n"); |
wim | 1:0440152c5387 | 279 | #endif |
wim | 1:0440152c5387 | 280 | } |
wim | 1:0440152c5387 | 281 | else { |
wim | 1:0440152c5387 | 282 | printf("Initialised UART bridge!\r\n"); |
wim | 1:0440152c5387 | 283 | } |
wim | 1:0440152c5387 | 284 | |
wim | 1:0440152c5387 | 285 | } |
wim | 1:0440152c5387 | 286 | |
wim | 2:76cb93b511f2 | 287 | |
wim | 2:76cb93b511f2 | 288 | /** FIFO control, sets TX and RX trigger levels and enables FIFO and save in _config |
wim | 2:76cb93b511f2 | 289 | * Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable) |
wim | 2:76cb93b511f2 | 290 | * Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set |
wim | 2:76cb93b511f2 | 291 | * @param none |
wim | 2:76cb93b511f2 | 292 | * @return none |
wim | 2:76cb93b511f2 | 293 | */ |
wim | 2:76cb93b511f2 | 294 | void SC16IS750::set_fifo_control() { |
wim | 2:76cb93b511f2 | 295 | |
wim | 2:76cb93b511f2 | 296 | // Set default fifoformat |
wim | 2:76cb93b511f2 | 297 | // FCR |
wim | 2:76cb93b511f2 | 298 | _config.fifoenable = true; |
wim | 2:76cb93b511f2 | 299 | |
wim | 2:76cb93b511f2 | 300 | // Note FCR[5:4] (=TX_IRQ_LVL) only accessible when EFR[4] is set (enhanced functions enable) |
wim | 2:76cb93b511f2 | 301 | // _config.fifoformat = FCR_RX_IRQ_8 | FCR_TX_IRQ_56; |
wim | 2:76cb93b511f2 | 302 | _config.fifoformat = FCR_RX_IRQ_8 | FCR_TX_IRQ_8; //Default |
wim | 2:76cb93b511f2 | 303 | |
wim | 2:76cb93b511f2 | 304 | if (_config.fifoenable) |
wim | 2:76cb93b511f2 | 305 | // enable FIFO mode and set FIFO control values |
wim | 2:76cb93b511f2 | 306 | this->writeRegister(FCR, _config.fifoformat | FCR_ENABLE_FIFO); |
wim | 2:76cb93b511f2 | 307 | else |
wim | 2:76cb93b511f2 | 308 | // disable FIFO mode and set FIFO control values |
wim | 2:76cb93b511f2 | 309 | this->writeRegister(FCR, _config.fifoformat); |
wim | 2:76cb93b511f2 | 310 | |
wim | 2:76cb93b511f2 | 311 | // Set Trigger level register TLR for RX and TX interrupt generation |
wim | 2:76cb93b511f2 | 312 | // Note TLR only accessible when EFR[4] is set (enhanced functions enable) and MCR[2] is set |
wim | 2:76cb93b511f2 | 313 | // TRL Trigger levels for RX and TX are 0..15, meaning 0-60 with a granularity of 4 chars |
wim | 2:76cb93b511f2 | 314 | // When TLR for RX or TX are 'Zero' the corresponding values in FCR are used. The FCR settings |
wim | 2:76cb93b511f2 | 315 | // have less resolution (only 4 levels) so TLR is considered an enhanced function. |
wim | 2:76cb93b511f2 | 316 | this->writeRegister(TLR, 0x00); // Use FCR Levels |
wim | 2:76cb93b511f2 | 317 | // this->writeRegister(TLR, (TLR_RX_DEFAULT << 4) | TLR_TX_DEFAULT); // Use Default enhanced levels |
wim | 2:76cb93b511f2 | 318 | |
wim | 2:76cb93b511f2 | 319 | } |
wim | 2:76cb93b511f2 | 320 | |
wim | 2:76cb93b511f2 | 321 | |
wim | 1:0440152c5387 | 322 | /** |
wim | 1:0440152c5387 | 323 | * Flush the UART FIFOs while maintaining current FIFO mode. |
wim | 1:0440152c5387 | 324 | * @param none |
wim | 1:0440152c5387 | 325 | * @return none |
wim | 1:0440152c5387 | 326 | */ |
wim | 1:0440152c5387 | 327 | void SC16IS750::flush() { |
wim | 2:76cb93b511f2 | 328 | // FCR is Write Only, use saved _config |
wim | 1:0440152c5387 | 329 | |
wim | 1:0440152c5387 | 330 | // reset TXFIFO, reset RXFIFO, non FIFO mode |
wim | 3:9783b6bde958 | 331 | this->writeRegister(FCR, FCR_TX_FIFO_RST | FCR_RX_FIFO_RST); |
wim | 1:0440152c5387 | 332 | |
wim | 1:0440152c5387 | 333 | if (_config.fifoenable) |
wim | 1:0440152c5387 | 334 | // enable FIFO mode and set FIFO control values |
wim | 1:0440152c5387 | 335 | this->writeRegister(FCR, _config.fifoformat | FCR_ENABLE_FIFO); |
wim | 1:0440152c5387 | 336 | else |
wim | 1:0440152c5387 | 337 | // disable FIFO mode and set FIFO control values |
wim | 1:0440152c5387 | 338 | this->writeRegister(FCR, _config.fifoformat); |
wim | 1:0440152c5387 | 339 | |
wim | 1:0440152c5387 | 340 | #if(0) |
wim | 1:0440152c5387 | 341 | //original |
wim | 1:0440152c5387 | 342 | /* |
wim | 1:0440152c5387 | 343 | * Flush characters from SC16IS750 receive buffer. |
wim | 1:0440152c5387 | 344 | */ |
wim | 1:0440152c5387 | 345 | |
wim | 1:0440152c5387 | 346 | // Note: This may not be the most appropriate flush approach. |
wim | 1:0440152c5387 | 347 | // It might be better to just flush the UART's buffer |
wim | 1:0440152c5387 | 348 | // rather than the buffer of the connected device |
wim | 1:0440152c5387 | 349 | // which is essentially what this does. |
wim | 1:0440152c5387 | 350 | while(readable() > 0) { |
wim | 1:0440152c5387 | 351 | getc(); |
wim | 0:d64854a60f95 | 352 | } |
wim | 0:d64854a60f95 | 353 | #endif |
wim | 0:d64854a60f95 | 354 | |
wim | 0:d64854a60f95 | 355 | } |
wim | 0:d64854a60f95 | 356 | |
wim | 0:d64854a60f95 | 357 | |
wim | 1:0440152c5387 | 358 | |
wim | 0:d64854a60f95 | 359 | /** |
wim | 0:d64854a60f95 | 360 | * Check that UART is connected and operational. |
wim | 0:d64854a60f95 | 361 | * @param none |
wim | 0:d64854a60f95 | 362 | * @return bool true when connected, false otherwise |
wim | 0:d64854a60f95 | 363 | */ |
wim | 0:d64854a60f95 | 364 | bool SC16IS750::connected() { |
wim | 0:d64854a60f95 | 365 | // Perform read/write test to check if UART is working |
wim | 0:d64854a60f95 | 366 | const char TEST_CHARACTER = 'H'; |
wim | 0:d64854a60f95 | 367 | |
wim | 0:d64854a60f95 | 368 | this->writeRegister(SPR, TEST_CHARACTER); |
wim | 0:d64854a60f95 | 369 | |
wim | 0:d64854a60f95 | 370 | return (this->readRegister(SPR) == TEST_CHARACTER); |
wim | 0:d64854a60f95 | 371 | } |
wim | 0:d64854a60f95 | 372 | |
wim | 0:d64854a60f95 | 373 | |
wim | 0:d64854a60f95 | 374 | |
wim | 0:d64854a60f95 | 375 | /** Determine if there is a character available to read. |
wim | 2:76cb93b511f2 | 376 | * This is data that's already arrived and stored in the receive |
wim | 2:76cb93b511f2 | 377 | * buffer (which holds 64 chars). |
wim | 2:76cb93b511f2 | 378 | * |
wim | 0:d64854a60f95 | 379 | * @return 1 if there is a character available to read, 0 otherwise |
wim | 0:d64854a60f95 | 380 | */ |
wim | 0:d64854a60f95 | 381 | int SC16IS750::readable() { |
wim | 2:76cb93b511f2 | 382 | |
wim | 2:76cb93b511f2 | 383 | // if (this->readableCount() > 0) { // Check count |
wim | 2:76cb93b511f2 | 384 | if (this->readRegister(LSR) & LSR_DR) { // Data in Receiver Bit, at least one character waiting |
wim | 2:76cb93b511f2 | 385 | return 1; |
wim | 2:76cb93b511f2 | 386 | } |
wim | 2:76cb93b511f2 | 387 | else { |
wim | 2:76cb93b511f2 | 388 | return 0; |
wim | 2:76cb93b511f2 | 389 | } |
wim | 2:76cb93b511f2 | 390 | |
wim | 0:d64854a60f95 | 391 | } |
wim | 0:d64854a60f95 | 392 | |
wim | 1:0440152c5387 | 393 | /** Determine how many characters are available to read. |
wim | 2:76cb93b511f2 | 394 | * This is data that's already arrived and stored in the receive |
wim | 2:76cb93b511f2 | 395 | * buffer (which holds 64 chars). |
wim | 2:76cb93b511f2 | 396 | * |
wim | 0:d64854a60f95 | 397 | * @return int Characters available to read |
wim | 0:d64854a60f95 | 398 | */ |
wim | 0:d64854a60f95 | 399 | int SC16IS750::readableCount() { |
wim | 0:d64854a60f95 | 400 | |
wim | 0:d64854a60f95 | 401 | return (this->readRegister(RXLVL)); |
wim | 0:d64854a60f95 | 402 | } |
wim | 0:d64854a60f95 | 403 | |
wim | 0:d64854a60f95 | 404 | /** Determine if there is space available to write a character. |
wim | 0:d64854a60f95 | 405 | * @return 1 if there is a space for a character to write, 0 otherwise |
wim | 0:d64854a60f95 | 406 | */ |
wim | 0:d64854a60f95 | 407 | int SC16IS750::writable() { |
wim | 2:76cb93b511f2 | 408 | |
wim | 2:76cb93b511f2 | 409 | // if ((this->writableCount() > 0) { // Check count |
wim | 2:76cb93b511f2 | 410 | if (this->readRegister(LSR) & LSR_THRE) { // THR Empty, space for at least one character |
wim | 2:76cb93b511f2 | 411 | return 1; |
wim | 2:76cb93b511f2 | 412 | } |
wim | 2:76cb93b511f2 | 413 | else { |
wim | 2:76cb93b511f2 | 414 | return 0; |
wim | 2:76cb93b511f2 | 415 | } |
wim | 0:d64854a60f95 | 416 | } |
wim | 0:d64854a60f95 | 417 | |
wim | 1:0440152c5387 | 418 | /** Determine how much space available for writing characters. |
wim | 2:76cb93b511f2 | 419 | * This considers data that's already stored in the transmit |
wim | 2:76cb93b511f2 | 420 | * buffer (which holds 64 chars). |
wim | 2:76cb93b511f2 | 421 | * |
wim | 1:0440152c5387 | 422 | * @return int character space available to write |
wim | 0:d64854a60f95 | 423 | */ |
wim | 0:d64854a60f95 | 424 | int SC16IS750::writableCount() { |
wim | 0:d64854a60f95 | 425 | |
wim | 2:76cb93b511f2 | 426 | return (this->readRegister(TXLVL)); // TX Level |
wim | 0:d64854a60f95 | 427 | } |
wim | 0:d64854a60f95 | 428 | |
wim | 0:d64854a60f95 | 429 | |
wim | 1:0440152c5387 | 430 | /** |
wim | 1:0440152c5387 | 431 | * Read char from UART Bridge. |
wim | 1:0440152c5387 | 432 | * Acts in the same manner as 'Serial.read()'. |
wim | 1:0440152c5387 | 433 | * @param none |
wim | 1:0440152c5387 | 434 | * @return char read or -1 if no data available. |
wim | 1:0440152c5387 | 435 | */ |
wim | 1:0440152c5387 | 436 | int SC16IS750::getc() { |
wim | 0:d64854a60f95 | 437 | |
wim | 0:d64854a60f95 | 438 | if (!readable()) { |
wim | 0:d64854a60f95 | 439 | return -1; |
wim | 0:d64854a60f95 | 440 | } |
wim | 0:d64854a60f95 | 441 | |
wim | 0:d64854a60f95 | 442 | return this->readRegister(RHR); |
wim | 0:d64854a60f95 | 443 | } |
wim | 0:d64854a60f95 | 444 | |
wim | 3:9783b6bde958 | 445 | |
wim | 1:0440152c5387 | 446 | /** |
wim | 1:0440152c5387 | 447 | * Write char to UART Bridge. Blocking when no free space in FIFO |
wim | 1:0440152c5387 | 448 | * @param value char to be written |
wim | 1:0440152c5387 | 449 | * @return value written |
wim | 1:0440152c5387 | 450 | */ |
wim | 1:0440152c5387 | 451 | int SC16IS750::putc(int value) { |
wim | 2:76cb93b511f2 | 452 | |
wim | 0:d64854a60f95 | 453 | while (this->readRegister(TXLVL) == 0) { |
wim | 0:d64854a60f95 | 454 | // Wait for space in TX buffer |
wim | 1:0440152c5387 | 455 | wait_us(10); |
wim | 0:d64854a60f95 | 456 | }; |
wim | 0:d64854a60f95 | 457 | this->writeRegister(THR, value); |
wim | 1:0440152c5387 | 458 | |
wim | 1:0440152c5387 | 459 | return value; |
wim | 0:d64854a60f95 | 460 | } |
wim | 0:d64854a60f95 | 461 | |
wim | 3:9783b6bde958 | 462 | |
wim | 2:76cb93b511f2 | 463 | /** |
wim | 2:76cb93b511f2 | 464 | * Write char string to UART Bridge. Blocking when no free space in FIFO |
wim | 2:76cb93b511f2 | 465 | * @param *str char string to be written |
wim | 2:76cb93b511f2 | 466 | * @return none |
wim | 2:76cb93b511f2 | 467 | */ |
wim | 3:9783b6bde958 | 468 | void SC16IS750::writeString(const char *str) { |
wim | 0:d64854a60f95 | 469 | |
wim | 0:d64854a60f95 | 470 | #if ENABLE_BULK_TRANSFERS |
wim | 2:76cb93b511f2 | 471 | int len, idx; |
wim | 0:d64854a60f95 | 472 | |
wim | 2:76cb93b511f2 | 473 | len = strlen(str); |
wim | 0:d64854a60f95 | 474 | |
wim | 2:76cb93b511f2 | 475 | // Write blocks of BULK_BLOCK_LEN |
wim | 2:76cb93b511f2 | 476 | while (len > BULK_BLOCK_LEN) { |
wim | 2:76cb93b511f2 | 477 | while(this->readRegister(TXLVL) < BULK_BLOCK_LEN) { |
wim | 2:76cb93b511f2 | 478 | // Wait for space in TX buffer |
wim | 2:76cb93b511f2 | 479 | wait_us(10); |
wim | 2:76cb93b511f2 | 480 | }; |
wim | 2:76cb93b511f2 | 481 | |
wim | 2:76cb93b511f2 | 482 | // Write a block of BULK_BLOCK_LEN bytes |
wim | 3:9783b6bde958 | 483 | #if (0) |
wim | 3:9783b6bde958 | 484 | // Note: can be optimized by writing registeraddress once and then repeatedly write the bytes. |
wim | 2:76cb93b511f2 | 485 | for (idx=0; idx<BULK_BLOCK_LEN; idx++) { |
wim | 2:76cb93b511f2 | 486 | this->writeRegister(THR, str[idx]); |
wim | 2:76cb93b511f2 | 487 | }; |
wim | 3:9783b6bde958 | 488 | #else |
wim | 3:9783b6bde958 | 489 | // optimized |
wim | 3:9783b6bde958 | 490 | this->writeDataBlock(str, BULK_BLOCK_LEN); |
wim | 3:9783b6bde958 | 491 | #endif |
wim | 3:9783b6bde958 | 492 | |
wim | 2:76cb93b511f2 | 493 | len -= BULK_BLOCK_LEN; |
wim | 2:76cb93b511f2 | 494 | str += BULK_BLOCK_LEN; |
wim | 0:d64854a60f95 | 495 | } |
wim | 2:76cb93b511f2 | 496 | |
wim | 2:76cb93b511f2 | 497 | // Write remaining bytes |
wim | 3:9783b6bde958 | 498 | // Note: can be optimized by writing registeraddress once and then repeatedly write the bytes. |
wim | 2:76cb93b511f2 | 499 | for (idx=0; idx<len; idx++) { |
wim | 2:76cb93b511f2 | 500 | while (this->readRegister(TXLVL) == 0) { |
wim | 2:76cb93b511f2 | 501 | // Wait for space in TX buffer |
wim | 2:76cb93b511f2 | 502 | wait_us(10); |
wim | 2:76cb93b511f2 | 503 | }; |
wim | 2:76cb93b511f2 | 504 | this->writeRegister(THR, str[idx]); |
wim | 2:76cb93b511f2 | 505 | } |
wim | 2:76cb93b511f2 | 506 | |
wim | 0:d64854a60f95 | 507 | |
wim | 2:76cb93b511f2 | 508 | #else |
wim | 3:9783b6bde958 | 509 | // Single writes instead of bulktransfer |
wim | 2:76cb93b511f2 | 510 | int len, idx; |
wim | 2:76cb93b511f2 | 511 | |
wim | 2:76cb93b511f2 | 512 | len = strlen(str); |
wim | 2:76cb93b511f2 | 513 | for (idx=0; idx<len; idx++) { |
wim | 2:76cb93b511f2 | 514 | while (this->readRegister(TXLVL) == 0) { |
wim | 2:76cb93b511f2 | 515 | // Wait for space in TX buffer |
wim | 2:76cb93b511f2 | 516 | wait_us(10); |
wim | 2:76cb93b511f2 | 517 | }; |
wim | 2:76cb93b511f2 | 518 | this->writeRegister(THR, str[idx]); |
wim | 2:76cb93b511f2 | 519 | } |
wim | 2:76cb93b511f2 | 520 | #endif |
wim | 0:d64854a60f95 | 521 | } |
wim | 2:76cb93b511f2 | 522 | |
wim | 2:76cb93b511f2 | 523 | |
wim | 3:9783b6bde958 | 524 | /** |
wim | 3:9783b6bde958 | 525 | * Write byte array to UART Bridge. Blocking when no free space in FIFO |
wim | 3:9783b6bde958 | 526 | * @param *data byte array to be written |
wim | 3:9783b6bde958 | 527 | * @param len number of bytes to write |
wim | 3:9783b6bde958 | 528 | * @return none |
wim | 3:9783b6bde958 | 529 | */ |
wim | 3:9783b6bde958 | 530 | void SC16IS750::writeBytes(const char *data, int len) { |
wim | 3:9783b6bde958 | 531 | |
wim | 3:9783b6bde958 | 532 | #if ENABLE_BULK_TRANSFERS |
wim | 3:9783b6bde958 | 533 | int idx; |
wim | 3:9783b6bde958 | 534 | |
wim | 3:9783b6bde958 | 535 | // Write blocks of BULK_BLOCK_LEN |
wim | 3:9783b6bde958 | 536 | while (len > BULK_BLOCK_LEN) { |
wim | 3:9783b6bde958 | 537 | while(this->readRegister(TXLVL) < BULK_BLOCK_LEN) { |
wim | 3:9783b6bde958 | 538 | // Wait for space in TX buffer |
wim | 3:9783b6bde958 | 539 | wait_us(10); |
wim | 3:9783b6bde958 | 540 | }; |
wim | 3:9783b6bde958 | 541 | |
wim | 3:9783b6bde958 | 542 | // Write a block of BULK_BLOCK_LEN bytes |
wim | 3:9783b6bde958 | 543 | #if (0) |
wim | 3:9783b6bde958 | 544 | // Note: can be optimized by writing registeraddress once and then repeatedly write the bytes. |
wim | 3:9783b6bde958 | 545 | for (idx=0; idx<BULK_BLOCK_LEN; idx++) { |
wim | 3:9783b6bde958 | 546 | this->writeRegister(THR, data[idx]); |
wim | 3:9783b6bde958 | 547 | }; |
wim | 3:9783b6bde958 | 548 | #else |
wim | 3:9783b6bde958 | 549 | // optimized |
wim | 3:9783b6bde958 | 550 | this->writeDataBlock(data, BULK_BLOCK_LEN); |
wim | 3:9783b6bde958 | 551 | #endif |
wim | 3:9783b6bde958 | 552 | |
wim | 3:9783b6bde958 | 553 | len -= BULK_BLOCK_LEN; |
wim | 3:9783b6bde958 | 554 | data += BULK_BLOCK_LEN; |
wim | 3:9783b6bde958 | 555 | } |
wim | 3:9783b6bde958 | 556 | |
wim | 3:9783b6bde958 | 557 | // Write remaining bytes |
wim | 3:9783b6bde958 | 558 | // Note: can be optimized by writing registeraddress once and then repeatedly write the bytes. |
wim | 3:9783b6bde958 | 559 | for (idx=0; idx<len; idx++) { |
wim | 3:9783b6bde958 | 560 | while (this->readRegister(TXLVL) == 0) { |
wim | 3:9783b6bde958 | 561 | // Wait for space in TX buffer |
wim | 3:9783b6bde958 | 562 | wait_us(10); |
wim | 3:9783b6bde958 | 563 | }; |
wim | 3:9783b6bde958 | 564 | this->writeRegister(THR, data[idx]); |
wim | 3:9783b6bde958 | 565 | } |
wim | 3:9783b6bde958 | 566 | |
wim | 3:9783b6bde958 | 567 | |
wim | 3:9783b6bde958 | 568 | #else |
wim | 3:9783b6bde958 | 569 | // Single writes instead of bulktransfer |
wim | 3:9783b6bde958 | 570 | int idx; |
wim | 3:9783b6bde958 | 571 | |
wim | 3:9783b6bde958 | 572 | for (idx=0; idx<len; idx++) { |
wim | 3:9783b6bde958 | 573 | while (this->readRegister(TXLVL) == 0) { |
wim | 3:9783b6bde958 | 574 | // Wait for space in TX buffer |
wim | 3:9783b6bde958 | 575 | wait_us(10); |
wim | 3:9783b6bde958 | 576 | }; |
wim | 3:9783b6bde958 | 577 | this->writeRegister(THR, str[idx]); |
wim | 3:9783b6bde958 | 578 | } |
wim | 3:9783b6bde958 | 579 | #endif |
wim | 3:9783b6bde958 | 580 | } |
wim | 3:9783b6bde958 | 581 | |
wim | 3:9783b6bde958 | 582 | |
wim | 3:9783b6bde958 | 583 | |
wim | 0:d64854a60f95 | 584 | |
wim | 1:0440152c5387 | 585 | /** Set direction of I/O port pins. |
wim | 1:0440152c5387 | 586 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
wim | 1:0440152c5387 | 587 | * @param bits Bitpattern for I/O (1=output, 0=input) |
wim | 1:0440152c5387 | 588 | * @return none |
wim | 1:0440152c5387 | 589 | */ |
wim | 0:d64854a60f95 | 590 | void SC16IS750::ioSetDirection(unsigned char bits) { |
wim | 0:d64854a60f95 | 591 | this->writeRegister(IODIR, bits); |
wim | 0:d64854a60f95 | 592 | } |
wim | 0:d64854a60f95 | 593 | |
wim | 1:0440152c5387 | 594 | /** Set bits of I/O port pins. |
wim | 1:0440152c5387 | 595 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
wim | 1:0440152c5387 | 596 | * @param bits Bitpattern for I/O (1= set output bit, 0 = clear output bit) |
wim | 1:0440152c5387 | 597 | * @return none |
wim | 1:0440152c5387 | 598 | */ |
wim | 0:d64854a60f95 | 599 | void SC16IS750::ioSetState(unsigned char bits) { |
wim | 0:d64854a60f95 | 600 | this->writeRegister(IOSTATE, bits); |
wim | 0:d64854a60f95 | 601 | } |
wim | 0:d64854a60f95 | 602 | |
wim | 1:0440152c5387 | 603 | /** Get bits of I/O port pins. |
wim | 1:0440152c5387 | 604 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
wim | 1:0440152c5387 | 605 | * @param none |
wim | 1:0440152c5387 | 606 | * @return bits Bitpattern for I/O (1= bit set, 0 = bit cleared) |
wim | 1:0440152c5387 | 607 | */ |
wim | 1:0440152c5387 | 608 | unsigned char SC16IS750::ioGetState() { |
wim | 1:0440152c5387 | 609 | return this->readRegister(IOSTATE) ; |
wim | 1:0440152c5387 | 610 | } |
wim | 0:d64854a60f95 | 611 | |
wim | 0:d64854a60f95 | 612 | |
wim | 1:0440152c5387 | 613 | /** Software Reset SC16IS750 device. |
wim | 1:0440152c5387 | 614 | * This method is specific to the SPI-I2C UART and not found on the 16750 |
wim | 1:0440152c5387 | 615 | * @param none |
wim | 1:0440152c5387 | 616 | * @return none |
wim | 1:0440152c5387 | 617 | */ |
wim | 1:0440152c5387 | 618 | void SC16IS750::swReset() { |
wim | 1:0440152c5387 | 619 | this->writeRegister(IOCTRL, IOC_SW_RST); |
wim | 1:0440152c5387 | 620 | } |
wim | 1:0440152c5387 | 621 | |
wim | 1:0440152c5387 | 622 | |
wim | 1:0440152c5387 | 623 | // |
wim | 1:0440152c5387 | 624 | // End Abstract Class Implementation |
wim | 0:d64854a60f95 | 625 | // |
wim | 0:d64854a60f95 | 626 | |
wim | 1:0440152c5387 | 627 | |
wim | 1:0440152c5387 | 628 | |
wim | 0:d64854a60f95 | 629 | /** Class SC16IS750_SPI for a converter between SPI and a Serial port |
wim | 0:d64854a60f95 | 630 | * |
wim | 1:0440152c5387 | 631 | * @code |
wim | 1:0440152c5387 | 632 | * |
wim | 1:0440152c5387 | 633 | * @endcode |
wim | 1:0440152c5387 | 634 | * |
wim | 0:d64854a60f95 | 635 | */ |
wim | 0:d64854a60f95 | 636 | SC16IS750_SPI::SC16IS750_SPI (SPI *spi, PinName cs) : _spi(spi), _cs(cs) { |
wim | 0:d64854a60f95 | 637 | _cs = 1; // deselect |
wim | 0:d64854a60f95 | 638 | |
wim | 0:d64854a60f95 | 639 | _spi->format(8, 0); |
wim | 0:d64854a60f95 | 640 | _spi->frequency(1000000); |
wim | 1:0440152c5387 | 641 | // _spi->frequency(100000); //test |
wim | 1:0440152c5387 | 642 | |
wim | 1:0440152c5387 | 643 | // Dont call _init() until SPI port has been configured. |
wim | 1:0440152c5387 | 644 | // That is why _init() is not called in parent Constructor |
wim | 1:0440152c5387 | 645 | _init(); |
wim | 1:0440152c5387 | 646 | |
wim | 0:d64854a60f95 | 647 | }; |
wim | 0:d64854a60f95 | 648 | |
wim | 0:d64854a60f95 | 649 | /** Write value to internal register. |
wim | 0:d64854a60f95 | 650 | * Pure virtual, must be declared in derived class. |
wim | 1:0440152c5387 | 651 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 652 | * @param data The 8bit value to write |
wim | 0:d64854a60f95 | 653 | * @return none |
wim | 0:d64854a60f95 | 654 | */ |
wim | 0:d64854a60f95 | 655 | void SC16IS750_SPI::writeRegister(RegisterName registerAddress, char data) { |
wim | 0:d64854a60f95 | 656 | |
wim | 0:d64854a60f95 | 657 | _cs = 0; // select; |
wim | 0:d64854a60f95 | 658 | _spi->write(registerAddress); |
wim | 0:d64854a60f95 | 659 | _spi->write(data); |
wim | 0:d64854a60f95 | 660 | _cs = 1; // deselect; |
wim | 1:0440152c5387 | 661 | |
wim | 3:9783b6bde958 | 662 | |
wim | 0:d64854a60f95 | 663 | } |
wim | 0:d64854a60f95 | 664 | |
wim | 0:d64854a60f95 | 665 | |
wim | 0:d64854a60f95 | 666 | /** Read value from internal register. |
wim | 1:0440152c5387 | 667 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 668 | * @return char The 8bit value read from the register |
wim | 0:d64854a60f95 | 669 | */ |
wim | 0:d64854a60f95 | 670 | char SC16IS750_SPI::readRegister(RegisterName registerAddress) { |
wim | 0:d64854a60f95 | 671 | |
wim | 0:d64854a60f95 | 672 | // Used in SPI read operations to flush slave's shift register |
wim | 1:0440152c5387 | 673 | const char SPI_DUMMY_CHAR = 0xFF; |
wim | 0:d64854a60f95 | 674 | |
wim | 0:d64854a60f95 | 675 | char result; |
wim | 0:d64854a60f95 | 676 | |
wim | 0:d64854a60f95 | 677 | _cs = 0; // select; |
wim | 0:d64854a60f95 | 678 | _spi->write(SPI_READ_MODE_FLAG | registerAddress); |
wim | 1:0440152c5387 | 679 | result = _spi->write(SPI_DUMMY_CHAR); |
wim | 0:d64854a60f95 | 680 | _cs = 1; // deselect; |
wim | 0:d64854a60f95 | 681 | |
wim | 0:d64854a60f95 | 682 | return result; |
wim | 0:d64854a60f95 | 683 | } |
wim | 0:d64854a60f95 | 684 | |
wim | 3:9783b6bde958 | 685 | |
wim | 3:9783b6bde958 | 686 | /** Write multiple datavalues to Transmitregister. |
wim | 3:9783b6bde958 | 687 | * More Efficient implementation than writing individual bytes |
wim | 3:9783b6bde958 | 688 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
wim | 3:9783b6bde958 | 689 | * Pure virtual, must be declared in derived class. |
wim | 3:9783b6bde958 | 690 | * @param char* databytes The pointer to the block of data |
wim | 3:9783b6bde958 | 691 | * @param len The number of bytes to write |
wim | 3:9783b6bde958 | 692 | * @return none |
wim | 3:9783b6bde958 | 693 | */ |
wim | 3:9783b6bde958 | 694 | void SC16IS750_SPI::writeDataBlock (const char *data, int len) { |
wim | 3:9783b6bde958 | 695 | int i; |
wim | 3:9783b6bde958 | 696 | |
wim | 3:9783b6bde958 | 697 | _cs = 0; // select; |
wim | 3:9783b6bde958 | 698 | |
wim | 3:9783b6bde958 | 699 | // Select the Transmit Holding Register |
wim | 3:9783b6bde958 | 700 | // Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
wim | 3:9783b6bde958 | 701 | _spi->write(THR); |
wim | 3:9783b6bde958 | 702 | |
wim | 3:9783b6bde958 | 703 | for (i=0; i<len; i++, data++) |
wim | 3:9783b6bde958 | 704 | _spi->write(*data); |
wim | 3:9783b6bde958 | 705 | |
wim | 3:9783b6bde958 | 706 | _cs = 1; // deselect; |
wim | 3:9783b6bde958 | 707 | } |
wim | 3:9783b6bde958 | 708 | |
wim | 0:d64854a60f95 | 709 | // |
wim | 0:d64854a60f95 | 710 | // End SPI Implementation |
wim | 1:0440152c5387 | 711 | // |
wim | 0:d64854a60f95 | 712 | |
wim | 0:d64854a60f95 | 713 | |
wim | 0:d64854a60f95 | 714 | /** Class SC16IS750_I2C for a converter between I2C and a Serial port |
wim | 0:d64854a60f95 | 715 | * |
wim | 1:0440152c5387 | 716 | * @code |
wim | 1:0440152c5387 | 717 | * |
wim | 1:0440152c5387 | 718 | * @endcode |
wim | 1:0440152c5387 | 719 | * |
wim | 0:d64854a60f95 | 720 | */ |
wim | 3:9783b6bde958 | 721 | SC16IS750_I2C::SC16IS750_I2C(I2C *i2c, uint8_t deviceAddress) : _i2c(i2c), _slaveAddress(deviceAddress & 0xFE) { |
wim | 0:d64854a60f95 | 722 | |
wim | 1:0440152c5387 | 723 | _i2c->frequency(400000); |
wim | 0:d64854a60f95 | 724 | |
wim | 1:0440152c5387 | 725 | // Dont call _init() until I2C port has been configured. |
wim | 1:0440152c5387 | 726 | // That is why _init() is not called in parent Constructor |
wim | 1:0440152c5387 | 727 | _init(); |
wim | 0:d64854a60f95 | 728 | } |
wim | 0:d64854a60f95 | 729 | |
wim | 0:d64854a60f95 | 730 | |
wim | 0:d64854a60f95 | 731 | /** Write value to internal register. |
wim | 1:0440152c5387 | 732 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 733 | * @param data The 8bit value to write |
wim | 0:d64854a60f95 | 734 | * @return none |
wim | 0:d64854a60f95 | 735 | */ |
wim | 0:d64854a60f95 | 736 | void SC16IS750_I2C::writeRegister(RegisterName registerAddress, char data) { |
wim | 0:d64854a60f95 | 737 | char w[2]; |
wim | 0:d64854a60f95 | 738 | |
wim | 0:d64854a60f95 | 739 | w[0] = registerAddress; |
wim | 0:d64854a60f95 | 740 | w[1] = data; |
wim | 0:d64854a60f95 | 741 | |
wim | 0:d64854a60f95 | 742 | _i2c->write( _slaveAddress, w, 2 ); |
wim | 0:d64854a60f95 | 743 | } |
wim | 0:d64854a60f95 | 744 | |
wim | 0:d64854a60f95 | 745 | |
wim | 0:d64854a60f95 | 746 | /** Read value from internal register. |
wim | 1:0440152c5387 | 747 | * @param registerAddress The address of the Register (enum RegisterName) |
wim | 0:d64854a60f95 | 748 | * @return char The 8bit value read from the register |
wim | 0:d64854a60f95 | 749 | */ |
wim | 0:d64854a60f95 | 750 | char SC16IS750_I2C::readRegister(RegisterName registerAddress) { |
wim | 0:d64854a60f95 | 751 | /* |
wim | 0:d64854a60f95 | 752 | * Read char from SC16IS750 register at <registerAddress>. |
wim | 0:d64854a60f95 | 753 | */ |
wim | 0:d64854a60f95 | 754 | char w[1]; |
wim | 0:d64854a60f95 | 755 | char r[1]; |
wim | 0:d64854a60f95 | 756 | |
wim | 0:d64854a60f95 | 757 | w[0] = registerAddress; |
wim | 0:d64854a60f95 | 758 | |
wim | 0:d64854a60f95 | 759 | _i2c->write( _slaveAddress, w, 1 ); |
wim | 0:d64854a60f95 | 760 | _i2c->read( _slaveAddress, r, 1 ); |
wim | 0:d64854a60f95 | 761 | |
wim | 0:d64854a60f95 | 762 | return ( r[0] ); |
wim | 0:d64854a60f95 | 763 | } |
wim | 0:d64854a60f95 | 764 | |
wim | 0:d64854a60f95 | 765 | |
wim | 3:9783b6bde958 | 766 | /** Write multiple datavalues to Transmitregister. |
wim | 3:9783b6bde958 | 767 | * More Efficient implementation than writing individual bytes |
wim | 3:9783b6bde958 | 768 | * Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
wim | 3:9783b6bde958 | 769 | * Pure virtual, must be declared in derived class. |
wim | 3:9783b6bde958 | 770 | * @param char* databytes The pointer to the block of data |
wim | 3:9783b6bde958 | 771 | * @param len The number of bytes to write |
wim | 3:9783b6bde958 | 772 | * @return none |
wim | 3:9783b6bde958 | 773 | */ |
wim | 3:9783b6bde958 | 774 | void SC16IS750_I2C::writeDataBlock (const char *data, int len) { |
wim | 3:9783b6bde958 | 775 | |
wim | 3:9783b6bde958 | 776 | #if(0) |
wim | 3:9783b6bde958 | 777 | int i; |
wim | 3:9783b6bde958 | 778 | char w[BULK_BLOCK_LEN]; |
wim | 3:9783b6bde958 | 779 | |
wim | 3:9783b6bde958 | 780 | // Select the Transmit Holding Register |
wim | 3:9783b6bde958 | 781 | // Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
wim | 3:9783b6bde958 | 782 | w[0] = THR; |
wim | 3:9783b6bde958 | 783 | |
wim | 3:9783b6bde958 | 784 | // copy the data.. |
wim | 3:9783b6bde958 | 785 | for (i=0; i<len; i++) |
wim | 3:9783b6bde958 | 786 | w[i+1] = data[i]; |
wim | 3:9783b6bde958 | 787 | |
wim | 3:9783b6bde958 | 788 | _i2c->write( _slaveAddress, w, len + 1); |
wim | 3:9783b6bde958 | 789 | #else |
wim | 3:9783b6bde958 | 790 | int i; |
wim | 3:9783b6bde958 | 791 | |
wim | 3:9783b6bde958 | 792 | _i2c->start(); |
wim | 3:9783b6bde958 | 793 | _i2c->write(_slaveAddress); |
wim | 3:9783b6bde958 | 794 | |
wim | 3:9783b6bde958 | 795 | // Select the Transmit Holding Register |
wim | 3:9783b6bde958 | 796 | // Assume that previous check confirmed that the FIFO has sufficient free space to store the data |
wim | 3:9783b6bde958 | 797 | _i2c->write(THR); |
wim | 3:9783b6bde958 | 798 | |
wim | 3:9783b6bde958 | 799 | // send the data.. |
wim | 3:9783b6bde958 | 800 | for (i=0; i<len; i++) |
wim | 3:9783b6bde958 | 801 | _i2c->write(data[i]); |
wim | 3:9783b6bde958 | 802 | |
wim | 3:9783b6bde958 | 803 | _i2c->stop(); |
wim | 3:9783b6bde958 | 804 | #endif |
wim | 3:9783b6bde958 | 805 | } |
wim | 3:9783b6bde958 | 806 | |
wim | 3:9783b6bde958 | 807 | |
wim | 0:d64854a60f95 | 808 | // |
wim | 1:0440152c5387 | 809 | // End I2C Implementation |
wim | 1:0440152c5387 | 810 | // |