Emiel Estiévenart / USBDevice

Base station firmware

USBDevice/USBHAL_LPC11U.cpp@0:ecc3925d3f8c, 2016-05-24 (annotated)

Committer:
Perijah
Date:
Tue May 24 13:16:55 2016 +0000
Revision:
0:ecc3925d3f8c
Base station firmware

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Perijah 0:ecc3925d3f8c 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
Perijah 0:ecc3925d3f8c 2 *
Perijah 0:ecc3925d3f8c 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
Perijah 0:ecc3925d3f8c 4 * and associated documentation files (the "Software"), to deal in the Software without
Perijah 0:ecc3925d3f8c 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
Perijah 0:ecc3925d3f8c 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
Perijah 0:ecc3925d3f8c 7 * Software is furnished to do so, subject to the following conditions:
Perijah 0:ecc3925d3f8c 8 *
Perijah 0:ecc3925d3f8c 9 * The above copyright notice and this permission notice shall be included in all copies or
Perijah 0:ecc3925d3f8c 10 * substantial portions of the Software.
Perijah 0:ecc3925d3f8c 11 *
Perijah 0:ecc3925d3f8c 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Perijah 0:ecc3925d3f8c 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Perijah 0:ecc3925d3f8c 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Perijah 0:ecc3925d3f8c 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Perijah 0:ecc3925d3f8c 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Perijah 0:ecc3925d3f8c 17 */
Perijah 0:ecc3925d3f8c 18
Perijah 0:ecc3925d3f8c 19 #ifdef TARGET_LPC11U24
Perijah 0:ecc3925d3f8c 20
Perijah 0:ecc3925d3f8c 21 #include "USBHAL.h"
Perijah 0:ecc3925d3f8c 22
Perijah 0:ecc3925d3f8c 23 USBHAL * USBHAL::instance;
Perijah 0:ecc3925d3f8c 24
Perijah 0:ecc3925d3f8c 25 // Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
Perijah 0:ecc3925d3f8c 26 #define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
Perijah 0:ecc3925d3f8c 27
Perijah 0:ecc3925d3f8c 28 // Convert physical endpoint number to register bit
Perijah 0:ecc3925d3f8c 29 #define EP(endpoint) (1UL<<endpoint)
Perijah 0:ecc3925d3f8c 30
Perijah 0:ecc3925d3f8c 31 // Convert physical to logical
Perijah 0:ecc3925d3f8c 32 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
Perijah 0:ecc3925d3f8c 33
Perijah 0:ecc3925d3f8c 34 // Get endpoint direction
Perijah 0:ecc3925d3f8c 35 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
Perijah 0:ecc3925d3f8c 36 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
Perijah 0:ecc3925d3f8c 37
Perijah 0:ecc3925d3f8c 38 // USB RAM
Perijah 0:ecc3925d3f8c 39 #define USB_RAM_START (0x20004000)
Perijah 0:ecc3925d3f8c 40 #define USB_RAM_SIZE (0x00000800)
Perijah 0:ecc3925d3f8c 41
Perijah 0:ecc3925d3f8c 42 // SYSAHBCLKCTRL
Perijah 0:ecc3925d3f8c 43 #define CLK_USB (1UL<<14)
Perijah 0:ecc3925d3f8c 44 #define CLK_USBRAM (1UL<<27)
Perijah 0:ecc3925d3f8c 45
Perijah 0:ecc3925d3f8c 46 // USB Information register
Perijah 0:ecc3925d3f8c 47 #define FRAME_NR(a) ((a) & 0x7ff) // Frame number
Perijah 0:ecc3925d3f8c 48
Perijah 0:ecc3925d3f8c 49 // USB Device Command/Status register
Perijah 0:ecc3925d3f8c 50 #define DEV_ADDR_MASK (0x7f) // Device address
Perijah 0:ecc3925d3f8c 51 #define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
Perijah 0:ecc3925d3f8c 52 #define DEV_EN (1UL<<7) // Device enable
Perijah 0:ecc3925d3f8c 53 #define SETUP (1UL<<8) // SETUP token received
Perijah 0:ecc3925d3f8c 54 #define PLL_ON (1UL<<9) // PLL enabled in suspend
Perijah 0:ecc3925d3f8c 55 #define DCON (1UL<<16) // Device status - connect
Perijah 0:ecc3925d3f8c 56 #define DSUS (1UL<<17) // Device status - suspend
Perijah 0:ecc3925d3f8c 57 #define DCON_C (1UL<<24) // Connect change
Perijah 0:ecc3925d3f8c 58 #define DSUS_C (1UL<<25) // Suspend change
Perijah 0:ecc3925d3f8c 59 #define DRES_C (1UL<<26) // Reset change
Perijah 0:ecc3925d3f8c 60 #define VBUSDEBOUNCED (1UL<<28) // Vbus detected
Perijah 0:ecc3925d3f8c 61
Perijah 0:ecc3925d3f8c 62 // Endpoint Command/Status list
Perijah 0:ecc3925d3f8c 63 #define CMDSTS_A (1UL<<31) // Active
Perijah 0:ecc3925d3f8c 64 #define CMDSTS_D (1UL<<30) // Disable
Perijah 0:ecc3925d3f8c 65 #define CMDSTS_S (1UL<<29) // Stall
Perijah 0:ecc3925d3f8c 66 #define CMDSTS_TR (1UL<<28) // Toggle Reset
Perijah 0:ecc3925d3f8c 67 #define CMDSTS_RF (1UL<<27) // Rate Feedback mode
Perijah 0:ecc3925d3f8c 68 #define CMDSTS_TV (1UL<<27) // Toggle Value
Perijah 0:ecc3925d3f8c 69 #define CMDSTS_T (1UL<<26) // Endpoint Type
Perijah 0:ecc3925d3f8c 70 #define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
Perijah 0:ecc3925d3f8c 71 #define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
Perijah 0:ecc3925d3f8c 72
Perijah 0:ecc3925d3f8c 73 #define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
Perijah 0:ecc3925d3f8c 74
Perijah 0:ecc3925d3f8c 75 // USB Non-endpoint interrupt sources
Perijah 0:ecc3925d3f8c 76 #define FRAME_INT (1UL<<30)
Perijah 0:ecc3925d3f8c 77 #define DEV_INT (1UL<<31)
Perijah 0:ecc3925d3f8c 78
Perijah 0:ecc3925d3f8c 79 static volatile int epComplete = 0;
Perijah 0:ecc3925d3f8c 80
Perijah 0:ecc3925d3f8c 81 // One entry for a double-buffered logical endpoint in the endpoint
Perijah 0:ecc3925d3f8c 82 // command/status list. Endpoint 0 is single buffered, out[1] is used
Perijah 0:ecc3925d3f8c 83 // for the SETUP packet and in[1] is not used
Perijah 0:ecc3925d3f8c 84 typedef __packed struct {
Perijah 0:ecc3925d3f8c 85 uint32_t out[2];
Perijah 0:ecc3925d3f8c 86 uint32_t in[2];
Perijah 0:ecc3925d3f8c 87 } EP_COMMAND_STATUS;
Perijah 0:ecc3925d3f8c 88
Perijah 0:ecc3925d3f8c 89 typedef __packed struct {
Perijah 0:ecc3925d3f8c 90 uint8_t out[MAX_PACKET_SIZE_EP0];
Perijah 0:ecc3925d3f8c 91 uint8_t in[MAX_PACKET_SIZE_EP0];
Perijah 0:ecc3925d3f8c 92 uint8_t setup[SETUP_PACKET_SIZE];
Perijah 0:ecc3925d3f8c 93 } CONTROL_TRANSFER;
Perijah 0:ecc3925d3f8c 94
Perijah 0:ecc3925d3f8c 95 typedef __packed struct {
Perijah 0:ecc3925d3f8c 96 uint32_t maxPacket;
Perijah 0:ecc3925d3f8c 97 uint32_t buffer[2];
Perijah 0:ecc3925d3f8c 98 uint32_t options;
Perijah 0:ecc3925d3f8c 99 } EP_STATE;
Perijah 0:ecc3925d3f8c 100
Perijah 0:ecc3925d3f8c 101 static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
Perijah 0:ecc3925d3f8c 102
Perijah 0:ecc3925d3f8c 103 // Pointer to the endpoint command/status list
Perijah 0:ecc3925d3f8c 104 static EP_COMMAND_STATUS *ep = NULL;
Perijah 0:ecc3925d3f8c 105
Perijah 0:ecc3925d3f8c 106 // Pointer to endpoint 0 data (IN/OUT and SETUP)
Perijah 0:ecc3925d3f8c 107 static CONTROL_TRANSFER *ct = NULL;
Perijah 0:ecc3925d3f8c 108
Perijah 0:ecc3925d3f8c 109 // Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
Perijah 0:ecc3925d3f8c 110 // initiating a remote wakeup event.
Perijah 0:ecc3925d3f8c 111 static volatile uint32_t devCmdStat;
Perijah 0:ecc3925d3f8c 112
Perijah 0:ecc3925d3f8c 113 // Pointers used to allocate USB RAM
Perijah 0:ecc3925d3f8c 114 static uint32_t usbRamPtr = USB_RAM_START;
Perijah 0:ecc3925d3f8c 115 static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
Perijah 0:ecc3925d3f8c 116
Perijah 0:ecc3925d3f8c 117 #define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
Perijah 0:ecc3925d3f8c 118
Perijah 0:ecc3925d3f8c 119 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
Perijah 0:ecc3925d3f8c 120 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
Perijah 0:ecc3925d3f8c 121 if (size > 0) {
Perijah 0:ecc3925d3f8c 122 do {
Perijah 0:ecc3925d3f8c 123 *dst++ = *src++;
Perijah 0:ecc3925d3f8c 124 } while (--size > 0);
Perijah 0:ecc3925d3f8c 125 }
Perijah 0:ecc3925d3f8c 126 }
Perijah 0:ecc3925d3f8c 127
Perijah 0:ecc3925d3f8c 128
Perijah 0:ecc3925d3f8c 129 USBHAL::USBHAL(void) {
Perijah 0:ecc3925d3f8c 130 NVIC_DisableIRQ(USB_IRQn);
Perijah 0:ecc3925d3f8c 131
Perijah 0:ecc3925d3f8c 132 // fill in callback array
Perijah 0:ecc3925d3f8c 133 epCallback[0] = &USBHAL::EP1_OUT_callback;
Perijah 0:ecc3925d3f8c 134 epCallback[1] = &USBHAL::EP1_IN_callback;
Perijah 0:ecc3925d3f8c 135 epCallback[2] = &USBHAL::EP2_OUT_callback;
Perijah 0:ecc3925d3f8c 136 epCallback[3] = &USBHAL::EP2_IN_callback;
Perijah 0:ecc3925d3f8c 137 epCallback[4] = &USBHAL::EP3_OUT_callback;
Perijah 0:ecc3925d3f8c 138 epCallback[5] = &USBHAL::EP3_IN_callback;
Perijah 0:ecc3925d3f8c 139 epCallback[6] = &USBHAL::EP4_OUT_callback;
Perijah 0:ecc3925d3f8c 140 epCallback[7] = &USBHAL::EP4_IN_callback;
Perijah 0:ecc3925d3f8c 141
Perijah 0:ecc3925d3f8c 142 // nUSB_CONNECT output
Perijah 0:ecc3925d3f8c 143 LPC_IOCON->PIO0_6 = 0x00000001;
Perijah 0:ecc3925d3f8c 144
Perijah 0:ecc3925d3f8c 145 // Enable clocks (USB registers, USB RAM)
Perijah 0:ecc3925d3f8c 146 LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
Perijah 0:ecc3925d3f8c 147
Perijah 0:ecc3925d3f8c 148 // Ensure device disconnected (DCON not set)
Perijah 0:ecc3925d3f8c 149 LPC_USB->DEVCMDSTAT = 0;
Perijah 0:ecc3925d3f8c 150
Perijah 0:ecc3925d3f8c 151 // to ensure that the USB host sees the device as
Perijah 0:ecc3925d3f8c 152 // disconnected if the target CPU is reset.
Perijah 0:ecc3925d3f8c 153 wait(0.3);
Perijah 0:ecc3925d3f8c 154
Perijah 0:ecc3925d3f8c 155 // Reserve space in USB RAM for endpoint command/status list
Perijah 0:ecc3925d3f8c 156 // Must be 256 byte aligned
Perijah 0:ecc3925d3f8c 157 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
Perijah 0:ecc3925d3f8c 158 ep = (EP_COMMAND_STATUS *)usbRamPtr;
Perijah 0:ecc3925d3f8c 159 usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
Perijah 0:ecc3925d3f8c 160 LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
Perijah 0:ecc3925d3f8c 161
Perijah 0:ecc3925d3f8c 162 // Reserve space in USB RAM for Endpoint 0
Perijah 0:ecc3925d3f8c 163 // Must be 64 byte aligned
Perijah 0:ecc3925d3f8c 164 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
Perijah 0:ecc3925d3f8c 165 ct = (CONTROL_TRANSFER *)usbRamPtr;
Perijah 0:ecc3925d3f8c 166 usbRamPtr += sizeof(CONTROL_TRANSFER);
Perijah 0:ecc3925d3f8c 167 LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
Perijah 0:ecc3925d3f8c 168
Perijah 0:ecc3925d3f8c 169 // Setup command/status list for EP0
Perijah 0:ecc3925d3f8c 170 ep[0].out[0] = 0;
Perijah 0:ecc3925d3f8c 171 ep[0].in[0] = 0;
Perijah 0:ecc3925d3f8c 172 ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
Perijah 0:ecc3925d3f8c 173
Perijah 0:ecc3925d3f8c 174 // Route all interrupts to IRQ, some can be routed to
Perijah 0:ecc3925d3f8c 175 // USB_FIQ if you wish.
Perijah 0:ecc3925d3f8c 176 LPC_USB->INTROUTING = 0;
Perijah 0:ecc3925d3f8c 177
Perijah 0:ecc3925d3f8c 178 // Set device address 0, enable USB device, no remote wakeup
Perijah 0:ecc3925d3f8c 179 devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
Perijah 0:ecc3925d3f8c 180 LPC_USB->DEVCMDSTAT = devCmdStat;
Perijah 0:ecc3925d3f8c 181
Perijah 0:ecc3925d3f8c 182 // Enable interrupts for device events and EP0
Perijah 0:ecc3925d3f8c 183 LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
Perijah 0:ecc3925d3f8c 184 instance = this;
Perijah 0:ecc3925d3f8c 185
Perijah 0:ecc3925d3f8c 186 //attach IRQ handler and enable interrupts
Perijah 0:ecc3925d3f8c 187 NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
Perijah 0:ecc3925d3f8c 188 }
Perijah 0:ecc3925d3f8c 189
Perijah 0:ecc3925d3f8c 190 USBHAL::~USBHAL(void) {
Perijah 0:ecc3925d3f8c 191 // Ensure device disconnected (DCON not set)
Perijah 0:ecc3925d3f8c 192 LPC_USB->DEVCMDSTAT = 0;
Perijah 0:ecc3925d3f8c 193 // Disable USB interrupts
Perijah 0:ecc3925d3f8c 194 NVIC_DisableIRQ(USB_IRQn);
Perijah 0:ecc3925d3f8c 195 }
Perijah 0:ecc3925d3f8c 196
Perijah 0:ecc3925d3f8c 197 void USBHAL::connect(void) {
Perijah 0:ecc3925d3f8c 198 NVIC_EnableIRQ(USB_IRQn);
Perijah 0:ecc3925d3f8c 199 devCmdStat |= DCON;
Perijah 0:ecc3925d3f8c 200 LPC_USB->DEVCMDSTAT = devCmdStat;
Perijah 0:ecc3925d3f8c 201 }
Perijah 0:ecc3925d3f8c 202
Perijah 0:ecc3925d3f8c 203 void USBHAL::disconnect(void) {
Perijah 0:ecc3925d3f8c 204 NVIC_DisableIRQ(USB_IRQn);
Perijah 0:ecc3925d3f8c 205 devCmdStat &= ~DCON;
Perijah 0:ecc3925d3f8c 206 LPC_USB->DEVCMDSTAT = devCmdStat;
Perijah 0:ecc3925d3f8c 207 }
Perijah 0:ecc3925d3f8c 208
Perijah 0:ecc3925d3f8c 209 void USBHAL::configureDevice(void) {
Perijah 0:ecc3925d3f8c 210 // Not required
Perijah 0:ecc3925d3f8c 211 }
Perijah 0:ecc3925d3f8c 212
Perijah 0:ecc3925d3f8c 213 void USBHAL::unconfigureDevice(void) {
Perijah 0:ecc3925d3f8c 214 // Not required
Perijah 0:ecc3925d3f8c 215 }
Perijah 0:ecc3925d3f8c 216
Perijah 0:ecc3925d3f8c 217 void USBHAL::EP0setup(uint8_t *buffer) {
Perijah 0:ecc3925d3f8c 218 // Copy setup packet data
Perijah 0:ecc3925d3f8c 219 USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
Perijah 0:ecc3925d3f8c 220 }
Perijah 0:ecc3925d3f8c 221
Perijah 0:ecc3925d3f8c 222 void USBHAL::EP0read(void) {
Perijah 0:ecc3925d3f8c 223 // Start an endpoint 0 read
Perijah 0:ecc3925d3f8c 224
Perijah 0:ecc3925d3f8c 225 // The USB ISR will call USBDevice_EP0out() when a packet has been read,
Perijah 0:ecc3925d3f8c 226 // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
Perijah 0:ecc3925d3f8c 227 // read the data.
Perijah 0:ecc3925d3f8c 228
Perijah 0:ecc3925d3f8c 229 ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
Perijah 0:ecc3925d3f8c 230 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
Perijah 0:ecc3925d3f8c 231 }
Perijah 0:ecc3925d3f8c 232
Perijah 0:ecc3925d3f8c 233 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
Perijah 0:ecc3925d3f8c 234 // Complete an endpoint 0 read
Perijah 0:ecc3925d3f8c 235 uint32_t bytesRead;
Perijah 0:ecc3925d3f8c 236
Perijah 0:ecc3925d3f8c 237 // Find how many bytes were read
Perijah 0:ecc3925d3f8c 238 bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
Perijah 0:ecc3925d3f8c 239
Perijah 0:ecc3925d3f8c 240 // Copy data
Perijah 0:ecc3925d3f8c 241 USBMemCopy(buffer, ct->out, bytesRead);
Perijah 0:ecc3925d3f8c 242 return bytesRead;
Perijah 0:ecc3925d3f8c 243 }
Perijah 0:ecc3925d3f8c 244
Perijah 0:ecc3925d3f8c 245
Perijah 0:ecc3925d3f8c 246 void USBHAL::EP0readStage(void) {
Perijah 0:ecc3925d3f8c 247 // Not required
Perijah 0:ecc3925d3f8c 248 }
Perijah 0:ecc3925d3f8c 249
Perijah 0:ecc3925d3f8c 250 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
Perijah 0:ecc3925d3f8c 251 // Start and endpoint 0 write
Perijah 0:ecc3925d3f8c 252
Perijah 0:ecc3925d3f8c 253 // The USB ISR will call USBDevice_EP0in() when the data has
Perijah 0:ecc3925d3f8c 254 // been written, the USBDevice layer then calls
Perijah 0:ecc3925d3f8c 255 // USBBusInterface_EP0getWriteResult() to complete the transaction.
Perijah 0:ecc3925d3f8c 256
Perijah 0:ecc3925d3f8c 257 // Copy data
Perijah 0:ecc3925d3f8c 258 USBMemCopy(ct->in, buffer, size);
Perijah 0:ecc3925d3f8c 259
Perijah 0:ecc3925d3f8c 260 // Start transfer
Perijah 0:ecc3925d3f8c 261 ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
Perijah 0:ecc3925d3f8c 262 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
Perijah 0:ecc3925d3f8c 263 }
Perijah 0:ecc3925d3f8c 264
Perijah 0:ecc3925d3f8c 265
Perijah 0:ecc3925d3f8c 266 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
Perijah 0:ecc3925d3f8c 267 uint8_t bf = 0;
Perijah 0:ecc3925d3f8c 268 uint32_t flags = 0;
Perijah 0:ecc3925d3f8c 269
Perijah 0:ecc3925d3f8c 270 //check which buffer must be filled
Perijah 0:ecc3925d3f8c 271 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 272 // Double buffered
Perijah 0:ecc3925d3f8c 273 if (LPC_USB->EPINUSE & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 274 bf = 1;
Perijah 0:ecc3925d3f8c 275 } else {
Perijah 0:ecc3925d3f8c 276 bf = 0;
Perijah 0:ecc3925d3f8c 277 }
Perijah 0:ecc3925d3f8c 278 }
Perijah 0:ecc3925d3f8c 279
Perijah 0:ecc3925d3f8c 280 // if isochronous endpoint, T = 1
Perijah 0:ecc3925d3f8c 281 if(endpointState[endpoint].options & ISOCHRONOUS)
Perijah 0:ecc3925d3f8c 282 {
Perijah 0:ecc3925d3f8c 283 flags |= CMDSTS_T;
Perijah 0:ecc3925d3f8c 284 }
Perijah 0:ecc3925d3f8c 285
Perijah 0:ecc3925d3f8c 286 //Active the endpoint for reading
Perijah 0:ecc3925d3f8c 287 ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
Perijah 0:ecc3925d3f8c 288 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
Perijah 0:ecc3925d3f8c 289 return EP_PENDING;
Perijah 0:ecc3925d3f8c 290 }
Perijah 0:ecc3925d3f8c 291
Perijah 0:ecc3925d3f8c 292 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
Perijah 0:ecc3925d3f8c 293
Perijah 0:ecc3925d3f8c 294 uint8_t bf = 0;
Perijah 0:ecc3925d3f8c 295
Perijah 0:ecc3925d3f8c 296 if (!(epComplete & EP(endpoint)))
Perijah 0:ecc3925d3f8c 297 return EP_PENDING;
Perijah 0:ecc3925d3f8c 298 else {
Perijah 0:ecc3925d3f8c 299 epComplete &= ~EP(endpoint);
Perijah 0:ecc3925d3f8c 300
Perijah 0:ecc3925d3f8c 301 //check which buffer has been filled
Perijah 0:ecc3925d3f8c 302 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 303 // Double buffered (here we read the previous buffer which was used)
Perijah 0:ecc3925d3f8c 304 if (LPC_USB->EPINUSE & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 305 bf = 0;
Perijah 0:ecc3925d3f8c 306 } else {
Perijah 0:ecc3925d3f8c 307 bf = 1;
Perijah 0:ecc3925d3f8c 308 }
Perijah 0:ecc3925d3f8c 309 }
Perijah 0:ecc3925d3f8c 310
Perijah 0:ecc3925d3f8c 311 // Find how many bytes were read
Perijah 0:ecc3925d3f8c 312 *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
Perijah 0:ecc3925d3f8c 313
Perijah 0:ecc3925d3f8c 314 // Copy data
Perijah 0:ecc3925d3f8c 315 USBMemCopy(data, ct->out, *bytesRead);
Perijah 0:ecc3925d3f8c 316 return EP_COMPLETED;
Perijah 0:ecc3925d3f8c 317 }
Perijah 0:ecc3925d3f8c 318 }
Perijah 0:ecc3925d3f8c 319
Perijah 0:ecc3925d3f8c 320 void USBHAL::EP0getWriteResult(void) {
Perijah 0:ecc3925d3f8c 321 // Not required
Perijah 0:ecc3925d3f8c 322 }
Perijah 0:ecc3925d3f8c 323
Perijah 0:ecc3925d3f8c 324 void USBHAL::EP0stall(void) {
Perijah 0:ecc3925d3f8c 325 ep[0].in[0] = CMDSTS_S;
Perijah 0:ecc3925d3f8c 326 ep[0].out[0] = CMDSTS_S;
Perijah 0:ecc3925d3f8c 327 }
Perijah 0:ecc3925d3f8c 328
Perijah 0:ecc3925d3f8c 329 void USBHAL::setAddress(uint8_t address) {
Perijah 0:ecc3925d3f8c 330 devCmdStat &= ~DEV_ADDR_MASK;
Perijah 0:ecc3925d3f8c 331 devCmdStat |= DEV_ADDR(address);
Perijah 0:ecc3925d3f8c 332 LPC_USB->DEVCMDSTAT = devCmdStat;
Perijah 0:ecc3925d3f8c 333 }
Perijah 0:ecc3925d3f8c 334
Perijah 0:ecc3925d3f8c 335 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
Perijah 0:ecc3925d3f8c 336 uint32_t flags = 0;
Perijah 0:ecc3925d3f8c 337 uint32_t bf;
Perijah 0:ecc3925d3f8c 338
Perijah 0:ecc3925d3f8c 339 // Validate parameters
Perijah 0:ecc3925d3f8c 340 if (data == NULL) {
Perijah 0:ecc3925d3f8c 341 return EP_INVALID;
Perijah 0:ecc3925d3f8c 342 }
Perijah 0:ecc3925d3f8c 343
Perijah 0:ecc3925d3f8c 344 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Perijah 0:ecc3925d3f8c 345 return EP_INVALID;
Perijah 0:ecc3925d3f8c 346 }
Perijah 0:ecc3925d3f8c 347
Perijah 0:ecc3925d3f8c 348 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
Perijah 0:ecc3925d3f8c 349 return EP_INVALID;
Perijah 0:ecc3925d3f8c 350 }
Perijah 0:ecc3925d3f8c 351
Perijah 0:ecc3925d3f8c 352 if (size > endpointState[endpoint].maxPacket) {
Perijah 0:ecc3925d3f8c 353 return EP_INVALID;
Perijah 0:ecc3925d3f8c 354 }
Perijah 0:ecc3925d3f8c 355
Perijah 0:ecc3925d3f8c 356 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 357 // Double buffered
Perijah 0:ecc3925d3f8c 358 if (LPC_USB->EPINUSE & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 359 bf = 1;
Perijah 0:ecc3925d3f8c 360 } else {
Perijah 0:ecc3925d3f8c 361 bf = 0;
Perijah 0:ecc3925d3f8c 362 }
Perijah 0:ecc3925d3f8c 363 } else {
Perijah 0:ecc3925d3f8c 364 // Single buffered
Perijah 0:ecc3925d3f8c 365 bf = 0;
Perijah 0:ecc3925d3f8c 366 }
Perijah 0:ecc3925d3f8c 367
Perijah 0:ecc3925d3f8c 368 // Check if already active
Perijah 0:ecc3925d3f8c 369 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
Perijah 0:ecc3925d3f8c 370 return EP_INVALID;
Perijah 0:ecc3925d3f8c 371 }
Perijah 0:ecc3925d3f8c 372
Perijah 0:ecc3925d3f8c 373 // Check if stalled
Perijah 0:ecc3925d3f8c 374 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
Perijah 0:ecc3925d3f8c 375 return EP_STALLED;
Perijah 0:ecc3925d3f8c 376 }
Perijah 0:ecc3925d3f8c 377
Perijah 0:ecc3925d3f8c 378 // Copy data to USB RAM
Perijah 0:ecc3925d3f8c 379 USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
Perijah 0:ecc3925d3f8c 380
Perijah 0:ecc3925d3f8c 381 // Add options
Perijah 0:ecc3925d3f8c 382 if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
Perijah 0:ecc3925d3f8c 383 flags |= CMDSTS_RF;
Perijah 0:ecc3925d3f8c 384 }
Perijah 0:ecc3925d3f8c 385
Perijah 0:ecc3925d3f8c 386 if (endpointState[endpoint].options & ISOCHRONOUS) {
Perijah 0:ecc3925d3f8c 387 flags |= CMDSTS_T;
Perijah 0:ecc3925d3f8c 388 }
Perijah 0:ecc3925d3f8c 389
Perijah 0:ecc3925d3f8c 390 // Add transfer
Perijah 0:ecc3925d3f8c 391 ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
Perijah 0:ecc3925d3f8c 392 endpointState[endpoint].buffer[bf]) \
Perijah 0:ecc3925d3f8c 393 | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
Perijah 0:ecc3925d3f8c 394
Perijah 0:ecc3925d3f8c 395 return EP_PENDING;
Perijah 0:ecc3925d3f8c 396 }
Perijah 0:ecc3925d3f8c 397
Perijah 0:ecc3925d3f8c 398 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
Perijah 0:ecc3925d3f8c 399 uint32_t bf;
Perijah 0:ecc3925d3f8c 400
Perijah 0:ecc3925d3f8c 401 // Validate parameters
Perijah 0:ecc3925d3f8c 402 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Perijah 0:ecc3925d3f8c 403 return EP_INVALID;
Perijah 0:ecc3925d3f8c 404 }
Perijah 0:ecc3925d3f8c 405
Perijah 0:ecc3925d3f8c 406 if (OUT_EP(endpoint)) {
Perijah 0:ecc3925d3f8c 407 return EP_INVALID;
Perijah 0:ecc3925d3f8c 408 }
Perijah 0:ecc3925d3f8c 409
Perijah 0:ecc3925d3f8c 410 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 411 // Double buffered // TODO: FIX THIS
Perijah 0:ecc3925d3f8c 412 if (LPC_USB->EPINUSE & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 413 bf = 1;
Perijah 0:ecc3925d3f8c 414 } else {
Perijah 0:ecc3925d3f8c 415 bf = 0;
Perijah 0:ecc3925d3f8c 416 }
Perijah 0:ecc3925d3f8c 417 } else {
Perijah 0:ecc3925d3f8c 418 // Single buffered
Perijah 0:ecc3925d3f8c 419 bf = 0;
Perijah 0:ecc3925d3f8c 420 }
Perijah 0:ecc3925d3f8c 421
Perijah 0:ecc3925d3f8c 422 // Check if endpoint still active
Perijah 0:ecc3925d3f8c 423 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
Perijah 0:ecc3925d3f8c 424 return EP_PENDING;
Perijah 0:ecc3925d3f8c 425 }
Perijah 0:ecc3925d3f8c 426
Perijah 0:ecc3925d3f8c 427 // Check if stalled
Perijah 0:ecc3925d3f8c 428 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
Perijah 0:ecc3925d3f8c 429 return EP_STALLED;
Perijah 0:ecc3925d3f8c 430 }
Perijah 0:ecc3925d3f8c 431
Perijah 0:ecc3925d3f8c 432 return EP_COMPLETED;
Perijah 0:ecc3925d3f8c 433 }
Perijah 0:ecc3925d3f8c 434
Perijah 0:ecc3925d3f8c 435 void USBHAL::stallEndpoint(uint8_t endpoint) {
Perijah 0:ecc3925d3f8c 436
Perijah 0:ecc3925d3f8c 437 // FIX: should this clear active bit?
Perijah 0:ecc3925d3f8c 438 if (IN_EP(endpoint)) {
Perijah 0:ecc3925d3f8c 439 ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
Perijah 0:ecc3925d3f8c 440 ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
Perijah 0:ecc3925d3f8c 441 } else {
Perijah 0:ecc3925d3f8c 442 ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
Perijah 0:ecc3925d3f8c 443 ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
Perijah 0:ecc3925d3f8c 444 }
Perijah 0:ecc3925d3f8c 445 }
Perijah 0:ecc3925d3f8c 446
Perijah 0:ecc3925d3f8c 447 void USBHAL::unstallEndpoint(uint8_t endpoint) {
Perijah 0:ecc3925d3f8c 448 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 449 // Double buffered
Perijah 0:ecc3925d3f8c 450 if (IN_EP(endpoint)) {
Perijah 0:ecc3925d3f8c 451 ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
Perijah 0:ecc3925d3f8c 452 ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
Perijah 0:ecc3925d3f8c 453
Perijah 0:ecc3925d3f8c 454 if (LPC_USB->EPINUSE & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 455 ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Perijah 0:ecc3925d3f8c 456 } else {
Perijah 0:ecc3925d3f8c 457 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Perijah 0:ecc3925d3f8c 458 }
Perijah 0:ecc3925d3f8c 459 } else {
Perijah 0:ecc3925d3f8c 460 ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
Perijah 0:ecc3925d3f8c 461 ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
Perijah 0:ecc3925d3f8c 462
Perijah 0:ecc3925d3f8c 463 if (LPC_USB->EPINUSE & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 464 ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Perijah 0:ecc3925d3f8c 465 } else {
Perijah 0:ecc3925d3f8c 466 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Perijah 0:ecc3925d3f8c 467 }
Perijah 0:ecc3925d3f8c 468 }
Perijah 0:ecc3925d3f8c 469 } else {
Perijah 0:ecc3925d3f8c 470 // Single buffered
Perijah 0:ecc3925d3f8c 471 if (IN_EP(endpoint)) {
Perijah 0:ecc3925d3f8c 472 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Perijah 0:ecc3925d3f8c 473 } else {
Perijah 0:ecc3925d3f8c 474 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
Perijah 0:ecc3925d3f8c 475 }
Perijah 0:ecc3925d3f8c 476 }
Perijah 0:ecc3925d3f8c 477 }
Perijah 0:ecc3925d3f8c 478
Perijah 0:ecc3925d3f8c 479 bool USBHAL::getEndpointStallState(unsigned char endpoint) {
Perijah 0:ecc3925d3f8c 480 if (IN_EP(endpoint)) {
Perijah 0:ecc3925d3f8c 481 if (LPC_USB->EPINUSE & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 482 if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
Perijah 0:ecc3925d3f8c 483 return true;
Perijah 0:ecc3925d3f8c 484 }
Perijah 0:ecc3925d3f8c 485 } else {
Perijah 0:ecc3925d3f8c 486 if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
Perijah 0:ecc3925d3f8c 487 return true;
Perijah 0:ecc3925d3f8c 488 }
Perijah 0:ecc3925d3f8c 489 }
Perijah 0:ecc3925d3f8c 490 } else {
Perijah 0:ecc3925d3f8c 491 if (LPC_USB->EPINUSE & EP(endpoint)) {
Perijah 0:ecc3925d3f8c 492 if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
Perijah 0:ecc3925d3f8c 493 return true;
Perijah 0:ecc3925d3f8c 494 }
Perijah 0:ecc3925d3f8c 495 } else {
Perijah 0:ecc3925d3f8c 496 if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
Perijah 0:ecc3925d3f8c 497 return true;
Perijah 0:ecc3925d3f8c 498 }
Perijah 0:ecc3925d3f8c 499 }
Perijah 0:ecc3925d3f8c 500 }
Perijah 0:ecc3925d3f8c 501
Perijah 0:ecc3925d3f8c 502 return false;
Perijah 0:ecc3925d3f8c 503 }
Perijah 0:ecc3925d3f8c 504
Perijah 0:ecc3925d3f8c 505 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
Perijah 0:ecc3925d3f8c 506 uint32_t tmpEpRamPtr;
Perijah 0:ecc3925d3f8c 507
Perijah 0:ecc3925d3f8c 508 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
Perijah 0:ecc3925d3f8c 509 return false;
Perijah 0:ecc3925d3f8c 510 }
Perijah 0:ecc3925d3f8c 511
Perijah 0:ecc3925d3f8c 512 // Not applicable to the control endpoints
Perijah 0:ecc3925d3f8c 513 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
Perijah 0:ecc3925d3f8c 514 return false;
Perijah 0:ecc3925d3f8c 515 }
Perijah 0:ecc3925d3f8c 516
Perijah 0:ecc3925d3f8c 517 // Allocate buffers in USB RAM
Perijah 0:ecc3925d3f8c 518 tmpEpRamPtr = epRamPtr;
Perijah 0:ecc3925d3f8c 519
Perijah 0:ecc3925d3f8c 520 // Must be 64 byte aligned
Perijah 0:ecc3925d3f8c 521 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
Perijah 0:ecc3925d3f8c 522
Perijah 0:ecc3925d3f8c 523 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
Perijah 0:ecc3925d3f8c 524 // Out of memory
Perijah 0:ecc3925d3f8c 525 return false;
Perijah 0:ecc3925d3f8c 526 }
Perijah 0:ecc3925d3f8c 527
Perijah 0:ecc3925d3f8c 528 // Allocate first buffer
Perijah 0:ecc3925d3f8c 529 endpointState[endpoint].buffer[0] = tmpEpRamPtr;
Perijah 0:ecc3925d3f8c 530 tmpEpRamPtr += maxPacket;
Perijah 0:ecc3925d3f8c 531
Perijah 0:ecc3925d3f8c 532 if (!(options & SINGLE_BUFFERED)) {
Perijah 0:ecc3925d3f8c 533 // Must be 64 byte aligned
Perijah 0:ecc3925d3f8c 534 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
Perijah 0:ecc3925d3f8c 535
Perijah 0:ecc3925d3f8c 536 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
Perijah 0:ecc3925d3f8c 537 // Out of memory
Perijah 0:ecc3925d3f8c 538 return false;
Perijah 0:ecc3925d3f8c 539 }
Perijah 0:ecc3925d3f8c 540
Perijah 0:ecc3925d3f8c 541 // Allocate second buffer
Perijah 0:ecc3925d3f8c 542 endpointState[endpoint].buffer[1] = tmpEpRamPtr;
Perijah 0:ecc3925d3f8c 543 tmpEpRamPtr += maxPacket;
Perijah 0:ecc3925d3f8c 544 }
Perijah 0:ecc3925d3f8c 545
Perijah 0:ecc3925d3f8c 546 // Commit to this USB RAM allocation
Perijah 0:ecc3925d3f8c 547 epRamPtr = tmpEpRamPtr;
Perijah 0:ecc3925d3f8c 548
Perijah 0:ecc3925d3f8c 549 // Remaining endpoint state values
Perijah 0:ecc3925d3f8c 550 endpointState[endpoint].maxPacket = maxPacket;
Perijah 0:ecc3925d3f8c 551 endpointState[endpoint].options = options;
Perijah 0:ecc3925d3f8c 552
Perijah 0:ecc3925d3f8c 553 // Enable double buffering if required
Perijah 0:ecc3925d3f8c 554 if (options & SINGLE_BUFFERED) {
Perijah 0:ecc3925d3f8c 555 LPC_USB->EPBUFCFG &= ~EP(endpoint);
Perijah 0:ecc3925d3f8c 556 } else {
Perijah 0:ecc3925d3f8c 557 // Double buffered
Perijah 0:ecc3925d3f8c 558 LPC_USB->EPBUFCFG |= EP(endpoint);
Perijah 0:ecc3925d3f8c 559 }
Perijah 0:ecc3925d3f8c 560
Perijah 0:ecc3925d3f8c 561 // Enable interrupt
Perijah 0:ecc3925d3f8c 562 LPC_USB->INTEN |= EP(endpoint);
Perijah 0:ecc3925d3f8c 563
Perijah 0:ecc3925d3f8c 564 // Enable endpoint
Perijah 0:ecc3925d3f8c 565 unstallEndpoint(endpoint);
Perijah 0:ecc3925d3f8c 566 return true;
Perijah 0:ecc3925d3f8c 567 }
Perijah 0:ecc3925d3f8c 568
Perijah 0:ecc3925d3f8c 569 void USBHAL::remoteWakeup(void) {
Perijah 0:ecc3925d3f8c 570 // Clearing DSUS bit initiates a remote wakeup if the
Perijah 0:ecc3925d3f8c 571 // device is currently enabled and suspended - otherwise
Perijah 0:ecc3925d3f8c 572 // it has no effect.
Perijah 0:ecc3925d3f8c 573 LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
Perijah 0:ecc3925d3f8c 574 }
Perijah 0:ecc3925d3f8c 575
Perijah 0:ecc3925d3f8c 576
Perijah 0:ecc3925d3f8c 577 static void disableEndpoints(void) {
Perijah 0:ecc3925d3f8c 578 uint32_t logEp;
Perijah 0:ecc3925d3f8c 579
Perijah 0:ecc3925d3f8c 580 // Ref. Table 158 "When a bus reset is received, software
Perijah 0:ecc3925d3f8c 581 // must set the disable bit of all endpoints to 1".
Perijah 0:ecc3925d3f8c 582
Perijah 0:ecc3925d3f8c 583 for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
Perijah 0:ecc3925d3f8c 584 ep[logEp].out[0] = CMDSTS_D;
Perijah 0:ecc3925d3f8c 585 ep[logEp].out[1] = CMDSTS_D;
Perijah 0:ecc3925d3f8c 586 ep[logEp].in[0] = CMDSTS_D;
Perijah 0:ecc3925d3f8c 587 ep[logEp].in[1] = CMDSTS_D;
Perijah 0:ecc3925d3f8c 588 }
Perijah 0:ecc3925d3f8c 589
Perijah 0:ecc3925d3f8c 590 // Start of USB RAM for endpoints > 0
Perijah 0:ecc3925d3f8c 591 epRamPtr = usbRamPtr;
Perijah 0:ecc3925d3f8c 592 }
Perijah 0:ecc3925d3f8c 593
Perijah 0:ecc3925d3f8c 594
Perijah 0:ecc3925d3f8c 595
Perijah 0:ecc3925d3f8c 596 void USBHAL::_usbisr(void) {
Perijah 0:ecc3925d3f8c 597 instance->usbisr();
Perijah 0:ecc3925d3f8c 598 }
Perijah 0:ecc3925d3f8c 599
Perijah 0:ecc3925d3f8c 600 void USBHAL::usbisr(void) {
Perijah 0:ecc3925d3f8c 601 // Start of frame
Perijah 0:ecc3925d3f8c 602 if (LPC_USB->INTSTAT & FRAME_INT) {
Perijah 0:ecc3925d3f8c 603 // Clear SOF interrupt
Perijah 0:ecc3925d3f8c 604 LPC_USB->INTSTAT = FRAME_INT;
Perijah 0:ecc3925d3f8c 605
Perijah 0:ecc3925d3f8c 606 // SOF event, read frame number
Perijah 0:ecc3925d3f8c 607 SOF(FRAME_NR(LPC_USB->INFO));
Perijah 0:ecc3925d3f8c 608 }
Perijah 0:ecc3925d3f8c 609
Perijah 0:ecc3925d3f8c 610 // Device state
Perijah 0:ecc3925d3f8c 611 if (LPC_USB->INTSTAT & DEV_INT) {
Perijah 0:ecc3925d3f8c 612 LPC_USB->INTSTAT = DEV_INT;
Perijah 0:ecc3925d3f8c 613
Perijah 0:ecc3925d3f8c 614 if (LPC_USB->DEVCMDSTAT & DSUS_C) {
Perijah 0:ecc3925d3f8c 615 // Suspend status changed
Perijah 0:ecc3925d3f8c 616 LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
Perijah 0:ecc3925d3f8c 617 if((LPC_USB->DEVCMDSTAT & DSUS) != 0) {
Perijah 0:ecc3925d3f8c 618 suspendStateChanged(1);
Perijah 0:ecc3925d3f8c 619 }
Perijah 0:ecc3925d3f8c 620 }
Perijah 0:ecc3925d3f8c 621
Perijah 0:ecc3925d3f8c 622 if (LPC_USB->DEVCMDSTAT & DRES_C) {
Perijah 0:ecc3925d3f8c 623 // Bus reset
Perijah 0:ecc3925d3f8c 624 LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
Perijah 0:ecc3925d3f8c 625
Perijah 0:ecc3925d3f8c 626 suspendStateChanged(0);
Perijah 0:ecc3925d3f8c 627
Perijah 0:ecc3925d3f8c 628 // Disable endpoints > 0
Perijah 0:ecc3925d3f8c 629 disableEndpoints();
Perijah 0:ecc3925d3f8c 630
Perijah 0:ecc3925d3f8c 631 // Bus reset event
Perijah 0:ecc3925d3f8c 632 busReset();
Perijah 0:ecc3925d3f8c 633 }
Perijah 0:ecc3925d3f8c 634 }
Perijah 0:ecc3925d3f8c 635
Perijah 0:ecc3925d3f8c 636 // Endpoint 0
Perijah 0:ecc3925d3f8c 637 if (LPC_USB->INTSTAT & EP(EP0OUT)) {
Perijah 0:ecc3925d3f8c 638 // Clear EP0OUT/SETUP interrupt
Perijah 0:ecc3925d3f8c 639 LPC_USB->INTSTAT = EP(EP0OUT);
Perijah 0:ecc3925d3f8c 640
Perijah 0:ecc3925d3f8c 641 // Check if SETUP
Perijah 0:ecc3925d3f8c 642 if (LPC_USB->DEVCMDSTAT & SETUP) {
Perijah 0:ecc3925d3f8c 643 // Clear Active and Stall bits for EP0
Perijah 0:ecc3925d3f8c 644 // Documentation does not make it clear if we must use the
Perijah 0:ecc3925d3f8c 645 // EPSKIP register to achieve this, Fig. 16 and NXP reference
Perijah 0:ecc3925d3f8c 646 // code suggests we can just clear the Active bits - check with
Perijah 0:ecc3925d3f8c 647 // NXP to be sure.
Perijah 0:ecc3925d3f8c 648 ep[0].in[0] = 0;
Perijah 0:ecc3925d3f8c 649 ep[0].out[0] = 0;
Perijah 0:ecc3925d3f8c 650
Perijah 0:ecc3925d3f8c 651 // Clear EP0IN interrupt
Perijah 0:ecc3925d3f8c 652 LPC_USB->INTSTAT = EP(EP0IN);
Perijah 0:ecc3925d3f8c 653
Perijah 0:ecc3925d3f8c 654 // Clear SETUP (and INTONNAK_CI/O) in device status register
Perijah 0:ecc3925d3f8c 655 LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
Perijah 0:ecc3925d3f8c 656
Perijah 0:ecc3925d3f8c 657 // EP0 SETUP event (SETUP data received)
Perijah 0:ecc3925d3f8c 658 EP0setupCallback();
Perijah 0:ecc3925d3f8c 659 } else {
Perijah 0:ecc3925d3f8c 660 // EP0OUT ACK event (OUT data received)
Perijah 0:ecc3925d3f8c 661 EP0out();
Perijah 0:ecc3925d3f8c 662 }
Perijah 0:ecc3925d3f8c 663 }
Perijah 0:ecc3925d3f8c 664
Perijah 0:ecc3925d3f8c 665 if (LPC_USB->INTSTAT & EP(EP0IN)) {
Perijah 0:ecc3925d3f8c 666 // Clear EP0IN interrupt
Perijah 0:ecc3925d3f8c 667 LPC_USB->INTSTAT = EP(EP0IN);
Perijah 0:ecc3925d3f8c 668
Perijah 0:ecc3925d3f8c 669 // EP0IN ACK event (IN data sent)
Perijah 0:ecc3925d3f8c 670 EP0in();
Perijah 0:ecc3925d3f8c 671 }
Perijah 0:ecc3925d3f8c 672
Perijah 0:ecc3925d3f8c 673 for (uint8_t num = 2; num < 5*2; num++) {
Perijah 0:ecc3925d3f8c 674 if (LPC_USB->INTSTAT & EP(num)) {
Perijah 0:ecc3925d3f8c 675 LPC_USB->INTSTAT = EP(num);
Perijah 0:ecc3925d3f8c 676 epComplete |= EP(num);
Perijah 0:ecc3925d3f8c 677 if ((instance->*(epCallback[num - 2]))()) {
Perijah 0:ecc3925d3f8c 678 epComplete &= ~EP(num);
Perijah 0:ecc3925d3f8c 679 }
Perijah 0:ecc3925d3f8c 680 }
Perijah 0:ecc3925d3f8c 681 }
Perijah 0:ecc3925d3f8c 682 }
Perijah 0:ecc3925d3f8c 683
Perijah 0:ecc3925d3f8c 684 #endif