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stm32f4xx_flash.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_flash.h 00004 * @author MCD Application Team 00005 * @version V1.7.1 00006 * @date 20-May-2016 00007 * @brief This file contains all the functions prototypes for the FLASH 00008 * firmware library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> 00013 * 00014 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00015 * You may not use this file except in compliance with the License. 00016 * You may obtain a copy of the License at: 00017 * 00018 * http://www.st.com/software_license_agreement_liberty_v2 00019 * 00020 * Unless required by applicable law or agreed to in writing, software 00021 * distributed under the License is distributed on an "AS IS" BASIS, 00022 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00023 * See the License for the specific language governing permissions and 00024 * limitations under the License. 00025 * 00026 ****************************************************************************** 00027 */ 00028 00029 /* Define to prevent recursive inclusion -------------------------------------*/ 00030 #ifndef __STM32F4xx_FLASH_H 00031 #define __STM32F4xx_FLASH_H 00032 00033 #ifdef __cplusplus 00034 extern "C" { 00035 #endif 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx.h" 00039 00040 /** @addtogroup STM32F4xx_StdPeriph_Driver 00041 * @{ 00042 */ 00043 00044 /** @addtogroup FLASH 00045 * @{ 00046 */ 00047 00048 /* Exported types ------------------------------------------------------------*/ 00049 /** 00050 * @brief FLASH Status 00051 */ 00052 typedef enum 00053 { 00054 FLASH_BUSY2 = 1, 00055 FLASH_ERROR_RD2, 00056 FLASH_ERROR_PGS2, 00057 FLASH_ERROR_PGP2, 00058 FLASH_ERROR_PGA2, 00059 FLASH_ERROR_WRP2, 00060 FLASH_ERROR_PROGRAM2, 00061 FLASH_ERROR_OPERATION2, 00062 FLASH_COMPLETE2 00063 }FLASH_Status; 00064 00065 /* Exported constants --------------------------------------------------------*/ 00066 00067 /** @defgroup FLASH_Exported_Constants 00068 * @{ 00069 */ 00070 00071 /** @defgroup Flash_Latency 00072 * @{ 00073 */ 00074 #define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ 00075 #define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ 00076 #define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ 00077 #define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ 00078 #define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ 00079 #define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ 00080 #define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ 00081 #define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ 00082 #define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */ 00083 #define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */ 00084 #define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */ 00085 #define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */ 00086 #define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */ 00087 #define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */ 00088 #define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */ 00089 #define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */ 00090 00091 00092 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ 00093 ((LATENCY) == FLASH_Latency_1) || \ 00094 ((LATENCY) == FLASH_Latency_2) || \ 00095 ((LATENCY) == FLASH_Latency_3) || \ 00096 ((LATENCY) == FLASH_Latency_4) || \ 00097 ((LATENCY) == FLASH_Latency_5) || \ 00098 ((LATENCY) == FLASH_Latency_6) || \ 00099 ((LATENCY) == FLASH_Latency_7) || \ 00100 ((LATENCY) == FLASH_Latency_8) || \ 00101 ((LATENCY) == FLASH_Latency_9) || \ 00102 ((LATENCY) == FLASH_Latency_10) || \ 00103 ((LATENCY) == FLASH_Latency_11) || \ 00104 ((LATENCY) == FLASH_Latency_12) || \ 00105 ((LATENCY) == FLASH_Latency_13) || \ 00106 ((LATENCY) == FLASH_Latency_14) || \ 00107 ((LATENCY) == FLASH_Latency_15)) 00108 /** 00109 * @} 00110 */ 00111 00112 /** @defgroup FLASH_Voltage_Range 00113 * @{ 00114 */ 00115 #define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ 00116 #define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */ 00117 #define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */ 00118 #define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */ 00119 00120 #define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \ 00121 ((RANGE) == VoltageRange_2) || \ 00122 ((RANGE) == VoltageRange_3) || \ 00123 ((RANGE) == VoltageRange_4)) 00124 /** 00125 * @} 00126 */ 00127 00128 /** @defgroup FLASH_Sectors 00129 * @{ 00130 */ 00131 #define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */ 00132 #define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */ 00133 #define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */ 00134 #define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */ 00135 #define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */ 00136 #define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */ 00137 #define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */ 00138 #define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */ 00139 #define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */ 00140 #define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */ 00141 #define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */ 00142 #define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */ 00143 #define FLASH_Sector_12 ((uint16_t)0x0080) /*!< Sector Number 12 */ 00144 #define FLASH_Sector_13 ((uint16_t)0x0088) /*!< Sector Number 13 */ 00145 #define FLASH_Sector_14 ((uint16_t)0x0090) /*!< Sector Number 14 */ 00146 #define FLASH_Sector_15 ((uint16_t)0x0098) /*!< Sector Number 15 */ 00147 #define FLASH_Sector_16 ((uint16_t)0x00A0) /*!< Sector Number 16 */ 00148 #define FLASH_Sector_17 ((uint16_t)0x00A8) /*!< Sector Number 17 */ 00149 #define FLASH_Sector_18 ((uint16_t)0x00B0) /*!< Sector Number 18 */ 00150 #define FLASH_Sector_19 ((uint16_t)0x00B8) /*!< Sector Number 19 */ 00151 #define FLASH_Sector_20 ((uint16_t)0x00C0) /*!< Sector Number 20 */ 00152 #define FLASH_Sector_21 ((uint16_t)0x00C8) /*!< Sector Number 21 */ 00153 #define FLASH_Sector_22 ((uint16_t)0x00D0) /*!< Sector Number 22 */ 00154 #define FLASH_Sector_23 ((uint16_t)0x00D8) /*!< Sector Number 23 */ 00155 00156 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\ 00157 ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\ 00158 ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\ 00159 ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\ 00160 ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\ 00161 ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11) ||\ 00162 ((SECTOR) == FLASH_Sector_12) || ((SECTOR) == FLASH_Sector_13) ||\ 00163 ((SECTOR) == FLASH_Sector_14) || ((SECTOR) == FLASH_Sector_15) ||\ 00164 ((SECTOR) == FLASH_Sector_16) || ((SECTOR) == FLASH_Sector_17) ||\ 00165 ((SECTOR) == FLASH_Sector_18) || ((SECTOR) == FLASH_Sector_19) ||\ 00166 ((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\ 00167 ((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23)) 00168 00169 #if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F469_479xx) 00170 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\ 00171 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 00172 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ 00173 00174 #if defined (STM32F40_41xxx) || defined(STM32F412xG) 00175 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\ 00176 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 00177 #endif /* STM32F40_41xxx || STM32F412xG */ 00178 00179 #if defined (STM32F401xx) 00180 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\ 00181 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 00182 #endif /* STM32F401xx */ 00183 00184 #if defined (STM32F411xE) || defined (STM32F446xx) 00185 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\ 00186 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 00187 #endif /* STM32F411xE || STM32F446xx */ 00188 00189 #if defined (STM32F410xx) 00190 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) ||\ 00191 (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 00192 #endif /* STM32F410xx */ 00193 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup Option_Bytes_Write_Protection 00199 * @{ 00200 */ 00201 #define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ 00202 #define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ 00203 #define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ 00204 #define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ 00205 #define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ 00206 #define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ 00207 #define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ 00208 #define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ 00209 #define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ 00210 #define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ 00211 #define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ 00212 #define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ 00213 #define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */ 00214 #define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */ 00215 #define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */ 00216 #define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */ 00217 #define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */ 00218 #define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */ 00219 #define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */ 00220 #define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */ 00221 #define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */ 00222 #define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */ 00223 #define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */ 00224 #define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */ 00225 #define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ 00226 00227 #define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup Selection_Protection_Mode 00233 * @{ 00234 */ 00235 #define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ 00236 #define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ 00237 #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable)) 00238 /** 00239 * @} 00240 */ 00241 00242 /** @defgroup Option_Bytes_PC_ReadWrite_Protection 00243 * @{ 00244 */ 00245 #define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ 00246 #define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ 00247 #define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ 00248 #define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ 00249 #define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ 00250 #define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ 00251 #define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ 00252 #define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ 00253 #define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ 00254 #define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ 00255 #define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ 00256 #define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ 00257 #define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ 00258 #define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ 00259 #define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ 00260 #define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ 00261 #define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ 00262 #define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ 00263 #define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ 00264 #define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ 00265 #define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ 00266 #define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ 00267 #define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ 00268 #define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ 00269 #define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ 00270 00271 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) 00272 /** 00273 * @} 00274 */ 00275 00276 /** @defgroup FLASH_Option_Bytes_Read_Protection 00277 * @{ 00278 */ 00279 #define OB_RDP_Level_0 ((uint8_t)0xAA) 00280 #define OB_RDP_Level_1 ((uint8_t)0x55) 00281 /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 00282 it's no more possible to go back to level 1 or 0 */ 00283 #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ 00284 ((LEVEL) == OB_RDP_Level_1))/*||\ 00285 ((LEVEL) == OB_RDP_Level_2))*/ 00286 /** 00287 * @} 00288 */ 00289 00290 /** @defgroup FLASH_Option_Bytes_IWatchdog 00291 * @{ 00292 */ 00293 #define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ 00294 #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ 00295 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) 00296 /** 00297 * @} 00298 */ 00299 00300 /** @defgroup FLASH_Option_Bytes_nRST_STOP 00301 * @{ 00302 */ 00303 #define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ 00304 #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ 00305 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) 00306 /** 00307 * @} 00308 */ 00309 00310 00311 /** @defgroup FLASH_Option_Bytes_nRST_STDBY 00312 * @{ 00313 */ 00314 #define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ 00315 #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ 00316 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) 00317 /** 00318 * @} 00319 */ 00320 00321 /** @defgroup FLASH_BOR_Reset_Level 00322 * @{ 00323 */ 00324 #define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ 00325 #define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ 00326 #define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ 00327 #define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ 00328 #define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ 00329 ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) 00330 /** 00331 * @} 00332 */ 00333 00334 /** @defgroup FLASH_Dual_Boot 00335 * @{ 00336 */ 00337 #define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ 00338 #define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ 00339 #define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled)) 00340 /** 00341 * @} 00342 */ 00343 00344 /** @defgroup FLASH_Interrupts 00345 * @{ 00346 */ 00347 #define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ 00348 #define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ 00349 #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) 00350 /** 00351 * @} 00352 */ 00353 00354 /** @defgroup FLASH_Flags 00355 * @{ 00356 */ 00357 #define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ 00358 #define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ 00359 #define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ 00360 #define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ 00361 #define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ 00362 #define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ 00363 #define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */ 00364 #define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ 00365 #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000)) 00366 #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ 00367 ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ 00368 ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ 00369 ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR)) 00370 /** 00371 * @} 00372 */ 00373 00374 /** @defgroup FLASH_Program_Parallelism 00375 * @{ 00376 */ 00377 #define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) 00378 #define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) 00379 #define FLASH_PSIZE_WORD ((uint32_t)0x00000200) 00380 #define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) 00381 #define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) 00382 /** 00383 * @} 00384 */ 00385 00386 /** @defgroup FLASH_Keys 00387 * @{ 00388 */ 00389 #define RDP_KEY ((uint16_t)0x00A5) 00390 #define FLASH_KEY1 ((uint32_t)0x45670123) 00391 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) 00392 #define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) 00393 #define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) 00394 /** 00395 * @} 00396 */ 00397 00398 /** 00399 * @brief ACR register byte 0 (Bits[7:0]) base address 00400 */ 00401 #define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) 00402 /** 00403 * @brief OPTCR register byte 0 (Bits[7:0]) base address 00404 */ 00405 #define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) 00406 /** 00407 * @brief OPTCR register byte 1 (Bits[15:8]) base address 00408 */ 00409 #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) 00410 /** 00411 * @brief OPTCR register byte 2 (Bits[23:16]) base address 00412 */ 00413 #define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) 00414 /** 00415 * @brief OPTCR register byte 3 (Bits[31:24]) base address 00416 */ 00417 #define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17) 00418 00419 /** 00420 * @brief OPTCR1 register byte 0 (Bits[7:0]) base address 00421 */ 00422 #define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) 00423 00424 /** 00425 * @} 00426 */ 00427 00428 /* Exported macro ------------------------------------------------------------*/ 00429 /* Exported functions --------------------------------------------------------*/ 00430 00431 /* FLASH Interface configuration functions ************************************/ 00432 void FLASH_SetLatency(uint32_t FLASH_Latency); 00433 void FLASH_PrefetchBufferCmd(FunctionalState NewState); 00434 void FLASH_InstructionCacheCmd(FunctionalState NewState); 00435 void FLASH_DataCacheCmd(FunctionalState NewState); 00436 void FLASH_InstructionCacheReset(void); 00437 void FLASH_DataCacheReset(void); 00438 00439 /* FLASH Memory Programming functions *****************************************/ 00440 void FLASH_Unlock(void); 00441 void FLASH_Lock(void); 00442 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); 00443 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); 00444 FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange); 00445 FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange); 00446 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); 00447 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); 00448 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); 00449 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); 00450 00451 /* Option Bytes Programming functions *****************************************/ 00452 void FLASH_OB_Unlock(void); 00453 void FLASH_OB_Lock(void); 00454 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); 00455 void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState); 00456 void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP); 00457 void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState); 00458 void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState); 00459 void FLASH_OB_RDPConfig(uint8_t OB_RDP); 00460 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); 00461 void FLASH_OB_BORConfig(uint8_t OB_BOR); 00462 void FLASH_OB_BootConfig(uint8_t OB_BOOT); 00463 FLASH_Status FLASH_OB_Launch(void); 00464 uint8_t FLASH_OB_GetUser(void); 00465 uint16_t FLASH_OB_GetWRP(void); 00466 uint16_t FLASH_OB_GetWRP1(void); 00467 uint16_t FLASH_OB_GetPCROP(void); 00468 uint16_t FLASH_OB_GetPCROP1(void); 00469 FlagStatus FLASH_OB_GetRDP(void); 00470 uint8_t FLASH_OB_GetBOR(void); 00471 00472 /* Interrupts and flags management functions **********************************/ 00473 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); 00474 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); 00475 void FLASH_ClearFlag(uint32_t FLASH_FLAG); 00476 FLASH_Status FLASH_GetStatus(void); 00477 FLASH_Status FLASH_WaitForLastOperation2(void); 00478 00479 #ifdef __cplusplus 00480 } 00481 #endif 00482 00483 #endif /* __STM32F4xx_FLASH_H */ 00484 00485 /** 00486 * @} 00487 */ 00488 00489 /** 00490 * @} 00491 */ 00492 00493 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00494
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