Nick Zhou
mbed library sources change for ST sensors and ST BLE
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mbed-src
by 
mbed official
Revision 619:034e698bc035, committed 2015-09-04
- Comitter:
- mbed_official
- Date:
- Fri Sep 04 09:30:10 2015 +0100
- Parent:
- 618:484341a108bc
- Child:
- 620:49241b7c6da5
- Commit message:
- Synchronized with git revision 92d1bfad30082571776c810a56fd471d30514ccf
Full URL: https://github.com/mbedmicro/mbed/commit/92d1bfad30082571776c810a56fd471d30514ccf/
Change directory structure and move files.
Changed in this revision
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/W7500x.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1168 +0,0 @@
-/**************************************************************************//**
- * @file W7500x.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
- * Device W7500x
- * @version V3.01
- * @date 06. March 2012
- *
- * @note
- * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef W7500x_H
-#define W7500x_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup W7500x_Definitions W7500x Definitions
- This file defines all structures and symbols for W7500x:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - Peripheral definitions
- @{
-*/
-
-
-/******************************************************************************/
-/* Processor and Core Peripherals */
-/******************************************************************************/
-/** @addtogroup W7500x_CMSIS Device CMSIS Definitions
- Configuration of the Cortex-M0 Processor and Core Peripherals
- @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/****** Cortex-M0 Processor Exceptions Numbers **************************************************/
-
-/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
-/****** W7500x Specific Interrupt Numbers *********************************************************/
- SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
- SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
- UART0_IRQn = 2, /*!< UART 0 Interrupt */
- UART1_IRQn = 3, /*!< UART 1 Interrupt */
- UART2_IRQn = 4, /*!< UART 2 Interrupt */
- I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
- I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
- PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
- PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
- PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
- PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
- DMA_IRQn = 11, /*!< DMA combined Interrupt */
- DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
- DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
- PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
- PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
- PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
- PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
- PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
- PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
- PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
- PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
- RTC_IRQn = 22, /*!< RTC Interrupt */
- ADC_IRQn = 23, /*!< ADC Interrupt */
- WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
- EXTI_IRQn = 25 /*!< EXTI Interrupt */
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M0 Processor and Core Peripherals */
-#define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-
-/*@}*/ /* end of group W7500x_CMSIS */
-
-
-#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
-#include "system_W7500x.h" /* W7500x System include file */
-
-
-/** @addtogroup Exported_types
- * @{
- */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-
-
-
-
-/**
- * @}
- */
-
-
-
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Clock Reset Generator
- */
-typedef struct
-{
- __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
- uint32_t RESERVED0[3];
- __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
- __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
- __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
- __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
- __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
- uint32_t RESERVED1[3];
- __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
- __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
- uint32_t RESERVED2[2];
- __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
- __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
- uint32_t RESERVED3[6];
- __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
- __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
- uint32_t RESERVED4[2];
- __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
- __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
- uint32_t RESERVED5[2];
- __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
- __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
- uint32_t RESERVED6[10];
- __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
- __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
- uint32_t RESERVED7[2];
- __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
- __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
- uint32_t RESERVED8[2];
- __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
- __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
- uint32_t RESERVED9[2];
- __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
- __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
- uint32_t RESERVED10[2];
- __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
- __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
- uint32_t RESERVED11[2];
- __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
- __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
- uint32_t RESERVED12[2];
- __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
- __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
- uint32_t RESERVED13[2];
- __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
- __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
- uint32_t RESERVED14[2];
- __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
- __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
- uint32_t RESERVED15;
- __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
-
- __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
- __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
- uint32_t RESERVED16;
- __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
-
- __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
- __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
- uint32_t RESERVED17[2];
- __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
- uint32_t RESERVED18[3];
- __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
-}CRG_TypeDef;
-
-
-/**
- * @brief UART
- */
-typedef struct
-{
- __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
- union {
- __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
- __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
- } STATUS;
- uint32_t RESERVED0[4];
- __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
- uint32_t RESERVED1;
- __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
- __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
- __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
- __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
- __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
- __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
- __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
- __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
- __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
- __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
- __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
-} UART_TypeDef;
-
-
-/**
- * @brief Simple UART
- */
-typedef struct
-{
- __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
- __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
- __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
- union {
- __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
- __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
- }INT;
- __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
-
-} S_UART_TypeDef;
-
-/**
- * @brief Analog Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
- __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
- __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
- __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
- __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
- uint32_t RESERVED0[2];
- __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
-}ADC_TypeDef;
-
-/**
- * @brief dualtimer
- */
-typedef struct
-{
- __IO uint32_t TimerLoad; // <h> Timer Load </h>
- __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
- __IO uint32_t TimerControl; // <h> Timer Control
- // <o.7> TimerEn: Timer Enable
- // <o.6> TimerMode: Timer Mode
- // <0=> Freerunning-mode
- // <1=> Periodic mode
- // <o.5> IntEnable: Interrupt Enable
- // <o.2..3> TimerPre: Timer Prescale
- // <0=> / 1
- // <1=> / 16
- // <2=> / 256
- // <3=> Undefined!
- // <o.1> TimerSize: Timer Size
- // <0=> 16-bit counter
- // <1=> 32-bit counter
- // <o.0> OneShot: One-shoot mode
- // <0=> Wrapping mode
- // <1=> One-shot mode
- // </h>
- __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
- __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
- __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
- __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
-} DUALTIMER_TypeDef;
-
-/**
- * @brief GPIO
- */
-typedef struct
-{
- __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
- __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
- uint32_t RESERVED0[2];
- __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
- __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
- __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
- __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
- __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
- __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
- __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
- __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
- __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
- __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
- union {
- __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
- __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
- }Interrupt;
- uint32_t RESERVED3[241];
- __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
- __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
-} GPIO_TypeDef;
-
-typedef struct
-{
- __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
- /* Port_01, offset : 0x04 */
- /* Port_02, offset : 0x08 */
- /* Port_03, offset : 0x0C */
- /* Port_04, offset : 0x10 */
- /* Port_05, offset : 0x14 */
- /* Port_06, offset : 0x18 */
- /* Port_07, offset : 0x1C */
- /* Port_08, offset : 0x20 */
- /* Port_09, offset : 0x24 */
- /* Port_10, offset : 0x28 */
- /* Port_11, offset : 0x2C */
- /* Port_12, offset : 0x30 */
- /* Port_13, offset : 0x34 */
- /* Port_14, offset : 0x38 */
- /* Port_15, offset : 0x3C */
-} P_Port_Def;
-
-typedef struct
-{
- __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
- /* Port_01, offset : 0x04 */
- /* Port_02, offset : 0x08 */
- /* Port_03, offset : 0x0C */
- /* Port_04, offset : 0x10 */
-} P_Port_D_Def;
-
-/**
- * @brief I2C Register structure definition
- */
-typedef struct
-{
- __IO uint32_t PRER; //0x00
- __IO uint32_t CTR; //0x04
- __IO uint32_t CMDR; //0x08
- __I uint32_t SR; //0x0C
- __IO uint32_t TSR; //0x10
- __IO uint32_t SADDR; //0x14
- __IO uint32_t TXR; //0x18
- __I uint32_t RXR; //0x1C
- __I uint32_t ISR; //0x20
- __IO uint32_t ISCR; //0x24
- __IO uint32_t ISMR; //0x28
-}I2C_TypeDef;
-
-/**
- * @brief PWM Register structure definition
- */
-typedef struct
-{
- __IO uint32_t IER; //Interrupt enable register
- // <7> IE7 : Channel 7 interrupt enable <R/W>
- // <6> IE6 : Channel 6 interrupt enable <R/W>
- // <5> IE5 : Channel 5 interrupt enable <R/W>
- // <4> IE4 : Channel 4 interrupt enable <R/W>
- // <3> IE3 : Channel 3 interrupt enable <R/W>
- // <2> IE2 : Channel 2 interrupt enable <R/W>
- // <1> IE1 : Channel 1 interrupt enable <R/W>
- // <0> IE0 : Channel 0 interrupt enable <R/W>
-
- __IO uint32_t SSR; //Start Stop register
- // <7> SS7 : Channel 7 TC start or stop <R/W>
- // <6> SS6 : Channel 6 TC start or stop <R/W>
- // <5> SS5 : Channel 5 TC start or stop <R/W>
- // <4> SS4 : Channel 4 TC start or stop <R/W>
- // <3> SS3 : Channel 3 TC start or stop <R/W>
- // <2> SS2 : Channel 2 TC start or stop <R/W>
- // <1> SS1 : Channel 1 TC start or stop <R/W>
- // <0> SS0 : Channel 0 TC start or stop <R/W>
-
- __IO uint32_t PSR; //Pause register
- // <7> PS7 : Channel 7 TC pasue <R/W>
- // <6> PS6 : Channel 6 TC pasue <R/W>
- // <5> PS5 : Channel 5 TC pasue <R/W>
- // <4> PS4 : Channel 4 TC pasue <R/W>
- // <3> PS3 : Channel 3 TC pasue <R/W>
- // <2> PS2 : Channel 2 TC pasue <R/W>
- // <1> PS1 : Channel 1 TC pasue <R/W>
- // <0> PS0 : Channel 0 TC pasue <R/W>
-} PWM_TypeDef;
-
-typedef struct
-{
- __I uint32_t IR; //Interrupt register
- // <2> CI : Capture interrupt <R>
- // <1> OI : Overflow interrupt <R>
- // <0> MI : Match interrupt <R>
-
- __IO uint32_t IER; //Interrupt enable register
- // <2> CIE : Capture interrupt enable <R/W>
- // <1> OIE : Overflow interrupt enable <R/W>
- // <0> MIE : Match interrupt enable <R/W>
-
- __O uint32_t ICR; //Interrupt clear register
- // <2> CIC : Capture interrupt clear <W>
- // <1> OIC : Overflow interrupt clear <W>
- // <0> MIC : Match interrupt clear <W>
-
- __I uint32_t TCR; //Timer/Counter register
- // <0..31> TCR : Timer/Counter register <R>
-
- __I uint32_t PCR; //Prescale counter register
- // <0..5> PCR : Prescale Counter register <R>
-
- __IO uint32_t PR; //Prescale register
- // <0..5> PR : prescale register <R/W>
-
- __IO uint32_t MR; //Match register
- // <0..31> MR : Match register <R/W>
-
- __IO uint32_t LR; //Limit register
- // <0..31> LR : Limit register <R/W>
- __IO uint32_t UDMR; //Up-Down mode register
- // <0> UDM : Up-down mode <R/W>
-
- __IO uint32_t TCMR; //Timer/Counter mode register
- // <0> TCM : Timer/Counter mode <R/W>
-
- __IO uint32_t PEEER; //PWM output enable and external input enable register
- // <0..1> PEEE : PWM output enable and external input enable <R/W>
-
- __IO uint32_t CMR; //Capture mode register
- // <0> CM : Capture mode <R/W>
-
- __IO uint32_t CR; //Capture register
- // <0..31> CR : Capture register <R>
-
- __IO uint32_t PDMR; //Periodic mode register
- // <0> PDM : Periodic mode <R/W>
-
- __IO uint32_t DZER; //Dead-zone enable register
- // <0> DZE : Dead-zone enable <R/W>
-
- __IO uint32_t DZCR; //Dead-zone counter register
- // <0..9> DZC : Dead-zone counter <R/W>
-} PWM_CHn_TypeDef;
-
-typedef struct
-{
- __IO uint32_t PWM_CHn_PR; //Prescale register
- // <0..5> PR : prescale register <R/W>
- __IO uint32_t PWM_CHn_MR; //Match register
- // <0..31> MR : Match register <R/W>
- __IO uint32_t PWM_CHn_LR; //Limit register
- // <0..31> LR : Limit register <R/W>
- __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
- // <0> UDM : Up-down mode <R/W>
- __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
- // <0> PDM : Periodic mode <R/W>
-}PWM_TimerModeInitTypeDef;
-
-typedef struct
-{
- __IO uint32_t PWM_CHn_PR; //Prescale register
- // <0..5> PR : prescale register <R/W>
- __IO uint32_t PWM_CHn_MR; //Match register
- // <0..31> MR : Match register <R/W>
- __IO uint32_t PWM_CHn_LR; //Limit register
- // <0..31> LR : Limit register <R/W>
- __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
- // <0> UDM : Up-down mode <R/W>
- __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
- // <0> PDM : Peiodic mode <R/W>
- __IO uint32_t PWM_CHn_CMR; //Capture mode register
- // <0> CM : Capture mode <R/W>
-}PWM_CaptureModeInitTypeDef;
-
-typedef struct
-{
- __IO uint32_t PWM_CHn_MR;
- __IO uint32_t PWM_CHn_LR;
- __IO uint32_t PWM_CHn_UDMR;
- __IO uint32_t PWM_CHn_PDMR;
- __IO uint32_t PWM_CHn_TCMR;
-}PWM_CounterModeInitTypeDef;
-
-
-/**
- * @brief Random Number generator
- */
-typedef struct
-{
- __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
- __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
- __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
- __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
- __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
- __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
-}RNG_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-typedef struct
-{
- __IO uint32_t CR0;
- __IO uint32_t CR1;
- __IO uint32_t DR;
- __IO uint32_t SR;
- __IO uint32_t CPSR;
- __IO uint32_t IMSC;
- __IO uint32_t RIS;
- __IO uint32_t MIS;
- __IO uint32_t ICR;
- __IO uint32_t DMACR;
-} SSP_TypeDef;
-
-typedef struct
-{
- __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
- __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
- __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
- // <o.1> RESEN: Reset enable
- // <o.0> INTEN: Interrupt enable
- // </h>
- __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
- __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
- __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
- uint32_t RESERVED[762];
- __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
-}WATCHDOG_TypeDef;
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-/* Peripheral and SRAM base address */
-#define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
-#define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
-#define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
-
-#define W7500x_RAM_BASE (0x20000000UL)
-#define W7500x_APB1_BASE (0x40000000UL)
-#define W7500x_APB2_BASE (0x41000000UL)
-#define W7500x_AHB_BASE (0x42000000UL)
-
-#define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
-#define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
-#define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
-
-#define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
-#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
-
-#define W7500x_INFO_BGT (0x0003FDB8)
-#define W7500x_INFO_OSC (0x0003FDBC)
-
-#define W7500x_TRIM_BGT (0x41001210)
-#define W7500x_TRIM_OSC (0x41001004)
-
-#define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
-#define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
-
-#define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
-
-#define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
-#define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
-#define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
-#define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
-
-#define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
-
-#define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
-
-#define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
-#define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
-
-#define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
-
-#define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
-
-#define SSP0_BASE (0x4000A000)
-#define SSP1_BASE (0x4000B000)
-
-#define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
-
-/**
- * @}
- */
-
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-#define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
-
-#define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
-#define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
-#define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
-
-#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
-
-#define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
-#define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
-#define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
-#define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
-
-#define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
-#define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
-#define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
-#define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
-
-#define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
-#define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
-#define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
-#define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
-
-#define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
-#define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
-#define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
-#define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
-
-#define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
-#define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
-#define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
-#define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
-
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-
-
-#define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
-#define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
-#define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
-#define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
-
-#define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
-#define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
-#define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
-#define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
-#define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
-#define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
-#define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
-#define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
-#define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
-
-#define PWM_CH0_BASE (W7500x_PWM_BASE)
-#define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
-#define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
-#define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
-#define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
-#define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
-#define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
-#define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
-
-#define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
-
-#define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
-#define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
-
-#define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
-
-/**
- * @}
- */
-
-
-
-/******************************************************************************/
-/* */
-/* Clock Reset Generator */
-/* */
-/******************************************************************************/
-/**************** Bit definition for CRG_OSC_PDR **************************/
-#define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
-#define CRG_OSC_PDR_PD (0x1ul) // Power Down
-/**************** Bit definition for CRG_PLL_PDR **************************/
-#define CRG_PLL_PDR_PD (0x0ul) // Power Down
-#define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
-/**************** Bit definition for CRG_PLL_FCR **************************/
-//ToDo
-/**************** Bit definition for CRG_PLL_OER **************************/
-#define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
-#define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
-/**************** Bit definition for CRG_PLL_BPR **************************/
-#define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
-#define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
-/**************** Bit definition for CRG_PLL_IFSR **************************/
-#define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_FCLK_SSR **************************/
-#define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
-#define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_FCLK_PVSR **************************/
-#define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
-#define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
-#define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
-#define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
-/**************** Bit definition for CRG_SSPCLK_SSR **************************/
-#define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
-#define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
-#define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_SSPCLK_PVSR **************************/
-#define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
-#define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
-#define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
-#define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
-/**************** Bit definition for CRG_ADCCLK_SSR **************************/
-#define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
-#define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
-#define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_ADCCLK_PVSR **************************/
-#define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
-#define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
-#define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
-#define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
-/**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
-#define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
-#define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
-#define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
-#define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
-#define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
-#define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
-#define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
-#define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
-#define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
-#define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
-#define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
-/**************** Bit definition for CRG_PWMnCLK_SSR **************************/
-#define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
-#define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
-#define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
-#define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
-#define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
-#define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
-#define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
-#define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
-#define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
-#define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
-#define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
-/**************** Bit definition for CRG_RTC_HS_SSR **************************/
-#define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
-#define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
-#define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_RTC_HS_PVSR **************************/
-#define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
-#define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
-#define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
-#define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
-#define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
-#define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
-#define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
-#define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
-/**************** Bit definition for CRG_RTC_SSR **************************/
-#define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
-#define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
-/**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
-#define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
-#define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
-#define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
-#define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
-#define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
-#define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
-#define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
-#define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
-#define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
-#define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
-#define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
-/**************** Bit definition for CRG_WDOGCLK_SSR **************************/
-#define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
-#define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
-/**************** Bit definition for CRG_UARTCLK_SSR **************************/
-#define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
-#define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
-#define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-/**************** Bit definition for CRG_UARTCLK_PVSR **************************/
-#define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
-#define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
-#define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
-#define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
-/**************** Bit definition for CRG_MIICLK_ECR **************************/
-#define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
-#define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
-/**************** Bit definition for CRG_MONCLK_SSR **************************/
-#define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
-#define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
-#define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
-#define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
-#define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
-#define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
-#define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
-#define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
-#define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
-#define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
-#define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
-#define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
-#define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
-#define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
-#define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
-#define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
-#define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
-#define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
-#define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
-#define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
-
-/******************************************************************************/
-/* */
-/* UART */
-/* */
-/******************************************************************************/
-/****************** Bit definition for UART Data(UARTDR) register *************************/
-#define UART_DR_OE (0x01ul << 11) // Overrun Error
-#define UART_DR_BE (0x01ul << 10) // Break Error
-#define UART_DR_PE (0x01ul << 9) // Parity Error
-#define UART_DR_FE (0x01ul << 8) // Framing Error
-//#define UART_DR_DR // ToDo
-/***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
-#define UARTR_SR_OE (0x01ul << 3) // Overrun Error
-#define UARTR_SR_BE (0x01ul << 2) // Break Error
-#define UARTR_SR_PE (0x01ul << 1) // Parity Error
-#define UARTR_SR_FE (0x01ul << 0) // Framing Error
-/***************** Bit definition for UART Error Clear(UARTECR) register ******************/
-#define UARTE_CR_OE (0x01ul << 3) // Overrun Error
-#define UARTE_CR_BE (0x01ul << 2) // Break Error
-#define UARTE_CR_PE (0x01ul << 1) // Parity Error
-#define UARTE_CR_FE (0x01ul << 0) // Framing Error
-/****************** Bit definition for UART Flags(UARTFR) register ************************/
-#define UART_FR_RI (0x01ul << 8) // Ring indicator
-#define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
-#define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
-#define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
-#define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
-#define UART_FR_BUSY (0x01ul << 3) // UART busy
-#define UART_FR_DCD (0x01ul << 2) // Data carrier detect
-#define UART_FR_DSR (0x01ul << 1) // Data set ready
-#define UART_FR_CTS (0x01ul << 0) // Clear to send
-/********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
-#define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
-/********************* Bit definition for Line Control(UARTLCR_H) register *****************/
-#define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
-#define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
-#define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
-#define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
-#define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
-#define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
-#define UART_LCR_H_BRK (0x1ul << 0) // Send break
-/********************* Bit definition for Contro(UARTCR) register *************************/
-#define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
-#define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
-#define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
-#define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
-#define UART_CR_RTS (0x1ul << 11) // Request to send
-#define UART_CR_DTR (0x1ul << 10) // Data transmit ready
-#define UART_CR_RXE (0x1ul << 9) // Receive enable
-#define UART_CR_TXE (0x1ul << 8) // Transmit enable
-#define UART_CR_LBE (0x1ul << 7) // Loop-back enable
-#define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
-#define UART_CR_SIREN (0x1ul << 1) // SIR enable
-#define UART_CR_UARTEN (0x1ul << 0) // UART enable
-/******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
-#define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
-#define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
-/******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
-#define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
-#define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
-#define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
-#define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
-#define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
-#define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
-#define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
-#define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
-#define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
-#define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
-#define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
-/*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
-#define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
-#define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
-#define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
-#define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
-#define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
-#define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
-#define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
-#define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
-#define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
-#define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
-#define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
-/************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
-#define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
-#define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
-#define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
-#define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
-#define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
-#define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
-#define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
-#define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
-#define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
-#define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
-#define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
-/*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
-#define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
-#define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
-#define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
-#define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
-#define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
-#define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
-#define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
-#define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
-#define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
-#define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
-#define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
-/***************** Bit definition for DMA Control(UARTDMACR) register ************************/
-#define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
-#define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
-#define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
-
-/******************************************************************************/
-/* */
-/* Simple UART */
-/* */
-/******************************************************************************/
-/***************** Bit definition for S_UART Data () register ************************/
-#define S_UART_DATA (0xFFul << 0)
-/***************** Bit definition for S_UART State() register ************************/
-#define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
-#define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
-#define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
-/***************** Bit definition for S_UART Control() register ************************/
-#define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
-#define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
-#define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
-#define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
-#define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
-#define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
-#define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
-/***************** Bit definition for S_UART Interrupt() register ************************/
-#define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
-#define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
-#define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
-#define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
-
-/******************************************************************************/
-/* */
-/* Analog Digital Register */
-/* */
-/******************************************************************************/
-
-/*********************** Bit definition for ADC_CTR ***********************/
-//#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
-//#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
-#define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
-#define ADC_CTR_PWD_PD (0x3ul) // Power down
-/*********************** Bit definition for ADC_CHSEL ***********************/
-#define ADC_CHSEL_CH0 (0x0ul) // Channel 0
-#define ADC_CHSEL_CH1 (0x1ul) // Channel 1
-#define ADC_CHSEL_CH2 (0x2ul) // Channel 2
-#define ADC_CHSEL_CH3 (0x3ul) // Channel 3
-#define ADC_CHSEL_CH4 (0x4ul) // Channel 4
-#define ADC_CHSEL_CH5 (0x5ul) // Channel 5
-#define ADC_CHSEL_CH6 (0x6ul) // Channel 6
-#define ADC_CHSEL_CH7 (0x7ul) // Channel 7
-#define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
-/*********************** Bit definition for ADC_START ***********************/
-#define ADC_START_START (0x1ul) // ADC conversion start
-/*********************** Bit definition for ADC_DATA ***********************/
-//ToDo (Readonly)
-
-/*********************** Bit definition for ADC_INT ***********************/
-#define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
-#define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
-//ToDo (Readonly)
-
-/*********************** Bit definition for ADC_INTCLR ***********************/
-#define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
-
-#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
-#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
-
-/******************************************************************************/
-/* */
-/* Dual Timer */
-/* */
-/******************************************************************************/
-
-/*********************** Bit definition for dualtimer ***********************/
-#define DUALTIMER_TimerControl_TimerDIsable 0x0ul
-#define DUALTIMER_TimerControl_TimerEnable 0x1ul
-#define DUALTIMER_TimerControl_TimerEnable_Pos 7
-
-#define DUALTIMER_TimerControl_FreeRunning 0x0ul
-#define DUALTIMER_TimerControl_Periodic 0x1ul
-#define DUALTIMER_TimerControl_TimerMode_Pos 6
-
-#define DUALTIMER_TimerControl_IntDisable 0x0ul
-#define DUALTIMER_TimerControl_IntEnable 0x1ul
-#define DUALTIMER_TimerControl_IntEnable_Pos 5
-
-#define DUALTIMER_TimerControl_Pre_1 0x0ul
-#define DUALTIMER_TimerControl_Pre_16 0x1ul
-#define DUALTIMER_TimerControl_Pre_256 0x2ul
-#define DUALTIMER_TimerControl_Pre_Pos 2
-
-#define DUALTIMER_TimerControl_Size_16 0x0ul
-#define DUALTIMER_TimerControl_Size_32 0x1ul
-#define DUALTIMER_TimerControl_Size_Pos 1
-
-#define DUALTIMER_TimerControl_Wrapping 0x0ul
-#define DUALTIMER_TimerControl_OneShot 0x1ul
-#define DUALTIMER_TimerControl_OneShot_Pos 0
-
-/******************************************************************************/
-/* */
-/* External Interrupt */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for Px_IER **************************/
-#define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
-#define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
-#define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
-#define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
-
-/******************************************************************************/
-/* */
-/* GPIO */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for Px_AFSR **************************/
-#define Px_AFSR_AF0 (0x00ul)
-#define Px_AFSR_AF1 (0x01ul)
-#define Px_AFSR_AF2 (0x02ul)
-#define Px_AFSR_AF3 (0x03ul)
-/**************** Bit definition for Px_PCR **************************/
-#define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
-#define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
-#define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
-#define Px_PCR_OD (0x01ul << 3) // Open Drain
-#define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
-#define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
-
-/******************************************************************************/
-/* */
-/* I2C */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for I2C_CTR **************************/
-#define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
-#define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
-#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
-#define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
-#define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
-#define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
-
-/**************** Bit definition for I2C_CMDR **************************/
-#define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
-#define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
-#define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
-#define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
-
-/**************** Bit definition for I2C_ISCR **************************/
-#define I2C_ISCR_RST (0x01ul << 1) // 0x01
-
-/**************** Bit definition for I2C_SR **************************/
-#define I2C_SR_TX (0x01ul << 9 ) // 0x200
-#define I2C_SR_RX (0x01ul << 8 ) // 0x100
-#define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
-#define I2C_SR_BT (0x01ul << 6 ) // 0x040
-#define I2C_SR_SA (0x01ul << 5 ) // 0x020
-#define I2C_SR_SB (0x01ul << 4 ) // 0x010
-#define I2C_SR_AL (0x01ul << 3 ) // 0x008
-#define I2C_SR_TO (0x01ul << 2 ) // 0x004
-#define I2C_SR_SRW (0x01ul << 1 ) // 0x002
-#define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
-
-/**************** Bit definition for I2C_ISR **************************/
-#define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
-#define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
-#define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
-#define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
-#define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
-
-/**************** Bit definition for I2C_ISMR **************************/
-#define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
-#define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
-#define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
-#define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
-#define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
-
-/******************************************************************************/
-/* */
-/* PWM */
-/* */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* Random number generator Register */
-/* */
-/******************************************************************************/
-
-/*********************** Bit definition for RNG_RUN ***********************/
-#define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
-#define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
-/*********************** Bit definition for RNG_SEED ***********************/
-//ToDo
-
-/*********************** Bit definition for RNG_CLKSEL ***********************/
-#define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
-#define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
-/*********************** Bit definition for RNG_ENABLE ***********************/
-#define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
-#define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
-/*********************** Bit definition for RNG_RN ***********************/
-//ToDo
-
-/*********************** Bit definition for RNG_POLY ***********************/
-//ToDo
-
-
-
-#if !defined (USE_HAL_DRIVER)
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-
-
-#if defined (USE_HAL_DRIVER)
- #include "W7500x_conf.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* W7500x_H */
-
-
-
-/************************ (C) COPYRIGHT Wiznet *****END OF FILE****/
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis.h Fri Sep 04 08:45:09 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * A generic CMSIS include header - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "W7500x.h" -#include "cmsis_nvic.h" - -#endif
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,47 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
-
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
- static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
-
- vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
- uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
- // Return the vector
- return vectors[IRQn + 16];
-}
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/cmsis_nvic.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS 41
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,104 +0,0 @@
-/**************************************************************************//**
- * @file system_CMSDK_CM0.c
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
- * Device CMSDK
- * @version V3.01
- * @date 06. March 2012
- *
- * @note
- * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#include "system_W7500x.h"
-
-
-/*----------------------------------------------------------------------------
- DEFINES
- *----------------------------------------------------------------------------*/
-//#define SYSCLK_EXTERN_OSC
-
-
-
-/*----------------------------------------------------------------------------
- Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemFrequency = 0; /*!< System Clock Frequency (Core Clock) */
-uint32_t SystemCoreClock = 0; /*!< Processor Clock Frequency */
-
-
-/*----------------------------------------------------------------------------
- Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
-{
- uint8_t M,N,OD;
-
-#ifdef SYSCLK_EXTERN_OSC
- CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
-#else
- CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
-#endif
- OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
- N = (CRG->PLL_FCR >> 8 ) & 0x3F;
- M = (CRG->PLL_FCR >> 16) & 0x3F;
-
-#ifdef SYSCLK_EXTERN_OSC
- SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
-#else
- SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
-#endif
-}
-
-uint32_t GetSystemClock()
-{
- return SystemCoreClock;
-}
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System.
- */
-void SystemInit (void)
-{
- uint8_t M,N,OD;
-
- (*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT)));
- (*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC)));
-
-
- // Set PLL input frequency
-#ifdef SYSCLK_EXTERN_OSC
- CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
-#else
- CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
-#endif
- OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
- N = (CRG->PLL_FCR >> 8 ) & 0x3F;
- M = (CRG->PLL_FCR >> 16) & 0x3F;
-
-#ifdef SYSCLK_EXTERN_OSC
- SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
-#else
- SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
-#endif
-}
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/system_W7500x.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,84 +0,0 @@
-/**************************************************************************//**
- * @file system_W7500x.h
- * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
- * Device W7500x
- * @version V3.10
- * @date 23. November 2012
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef SYSTEM_W7500x_H /* ToDo: replace '<Device>' with your device name */
-#define SYSTEM_W7500x_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "W7500x.h"
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-extern uint32_t GetSystemClock(void); /*!< Get System Clock Frequency */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-/*----------------------------------------------------------------------------
- Define clocks
- *----------------------------------------------------------------------------*/
-#define EXTERN_XTAL (8000000UL) /* External Oscillator Frequency */
-#define INTERN_XTAL (8000000UL) /* Internal Oscillator Frequency */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_W7500x_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,1191 @@
+/**************************************************************************//**
+ * @file W7500x.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * Device W7500x
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef W7500x_H
+#define W7500x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup W7500x_Definitions W7500x Definitions
+ This file defines all structures and symbols for W7500x:
+ - registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - Peripheral definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup W7500x_CMSIS Device CMSIS Definitions
+ Configuration of the Cortex-M0 Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers **************************************************/
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+/****** W7500x Specific Interrupt Numbers *********************************************************/
+ SSP0_IRQn = 0, /*!< SSP 0 Interrupt */
+ SSP1_IRQn = 1, /*!< SSP 1 Interrupt */
+ UART0_IRQn = 2, /*!< UART 0 Interrupt */
+ UART1_IRQn = 3, /*!< UART 1 Interrupt */
+ UART2_IRQn = 4, /*!< UART 2 Interrupt */
+ I2C0_IRQn = 5, /*!< I2C 0 Interrupt */
+ I2C1_IRQn = 6, /*!< I2C 1 Interrupt */
+ PORT0_IRQn = 7, /*!< Port 1 combined Interrupt */
+ PORT1_IRQn = 8, /*!< Port 2 combined Interrupt */
+ PORT2_IRQn = 9, /*!< Port 2 combined Interrupt */
+ PORT3_IRQn = 10, /*!< Port 2 combined Interrupt */
+ DMA_IRQn = 11, /*!< DMA combined Interrupt */
+ DUALTIMER0_IRQn = 12, /*!< Dual Timer 0 Interrupt */
+ DUALTIMER1_IRQn = 13, /*!< Dual Timer 1 Interrupt */
+ PWM0_IRQn = 14, /*!< PWM 0 Interrupt */
+ PWM1_IRQn = 15, /*!< PWM 1 Interrupt */
+ PWM2_IRQn = 16, /*!< PWM 2 Interrupt */
+ PWM3_IRQn = 17, /*!< PWM 3 Interrupt */
+ PWM4_IRQn = 18, /*!< PWM 4 Interrupt */
+ PWM5_IRQn = 19, /*!< PWM 5 Interrupt */
+ PWM6_IRQn = 20, /*!< PWM 6 Interrupt */
+ PWM7_IRQn = 21, /*!< PWM 7 Interrupt */
+ RTC_IRQn = 22, /*!< RTC Interrupt */
+ ADC_IRQn = 23, /*!< ADC Interrupt */
+ WZTOE_IRQn = 24, /*!< WZTOE Interrupt */
+ EXTI_IRQn = 25 /*!< EXTI Interrupt */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __CM0_REV 0x0000 /*!< Core Revision r0p0 */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+
+/*@}*/ /* end of group W7500x_CMSIS */
+
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_W7500x.h" /* W7500x System include file */
+
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+
+
+
+/**
+ * @}
+ */
+
+
+
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Clock Reset Generator
+ */
+typedef struct
+{
+ __IO uint32_t OSC_PDR; /*!< Oscillator power down register, Address offset : 0x00 */
+ uint32_t RESERVED0[3];
+ __IO uint32_t PLL_PDR; /*!< PLL power down register, Address offset : 0x10 */
+ __IO uint32_t PLL_FCR; /*!< PLL frequency calculating register, Address offset : 0x14 */
+ __IO uint32_t PLL_OER; /*!< PLL output enable register, Address offset : 0x18 */
+ __IO uint32_t PLL_BPR; /*!< PLL bypass register, Address offset : 0x1c */
+ __IO uint32_t PLL_IFSR; /*!< PLL input frequency select register, Address offset : 0x20 */
+ uint32_t RESERVED1[3];
+ __IO uint32_t FCLK_SSR; /*!< FCLK source select register, Address offset : 0x30 */
+ __IO uint32_t FCLK_PVSR; /*!< FCLK prescale value select register, Address offset : 0x34 */
+ uint32_t RESERVED2[2];
+ __IO uint32_t SSPCLK_SSR; /*!< SSPCLK source select register, Address offset : 0x40 */
+ __IO uint32_t SSPCLK_PVSR; /*!< SSPCLK prescale value select register, Address offset : 0x44 */
+ uint32_t RESERVED3[6];
+ __IO uint32_t ADCCLK_SSR; /*!< ADCCLK source select register, Address offset : 0x60 */
+ __IO uint32_t ADCCLK_PVSR; /*!< ADCCLK prescale value select register, Address offset : 0x64 */
+ uint32_t RESERVED4[2];
+ __IO uint32_t TIMER0CLK_SSR; /*!< TIMER0CLK source select register, Address offset : 0x70 */
+ __IO uint32_t TIMER0CLK_PVSR; /*!< TIMER0CLK prescale value select register, Address offset : 0x74 */
+ uint32_t RESERVED5[2];
+ __IO uint32_t TIMER1CLK_SSR; /*!< TIMER1CLK source select register, Address offset : 0x80 */
+ __IO uint32_t TIMER1CLK_PVSR; /*!< TIMER1CLK prescale value select register, Address offset : 0x84 */
+ uint32_t RESERVED6[10];
+ __IO uint32_t PWM0CLK_SSR; /*!< PWM0CLK source select register, Address offset : 0xb0 */
+ __IO uint32_t PWM0CLK_PVSR; /*!< PWM0CLK prescale value select register, Address offset : 0xb4 */
+ uint32_t RESERVED7[2];
+ __IO uint32_t PWM1CLK_SSR; /*!< PWM1CLK source select register, Address offset : 0xc0 */
+ __IO uint32_t PWM1CLK_PVSR; /*!< PWM1CLK prescale value select register, Address offset : 0xc4 */
+ uint32_t RESERVED8[2];
+ __IO uint32_t PWM2CLK_SSR; /*!< PWM2CLK source select register, Address offset : 0xd0 */
+ __IO uint32_t PWM2CLK_PVSR; /*!< PWM2CLK prescale value select register, Address offset : 0xd4 */
+ uint32_t RESERVED9[2];
+ __IO uint32_t PWM3CLK_SSR; /*!< PWM3CLK source select register, Address offset : 0xe0 */
+ __IO uint32_t PWM3CLK_PVSR; /*!< PWM3CLK prescale value select register, Address offset : 0xe4 */
+ uint32_t RESERVED10[2];
+ __IO uint32_t PWM4CLK_SSR; /*!< PWM4CLK source select register, Address offset : 0xf0 */
+ __IO uint32_t PWM4CLK_PVSR; /*!< PWM4CLK prescale value select register, Address offset : 0xf4 */
+ uint32_t RESERVED11[2];
+ __IO uint32_t PWM5CLK_SSR; /*!< PWM5CLK source select register, Address offset : 0x100 */
+ __IO uint32_t PWM5LK_PVSR; /*!< PWM5CLK prescale value select register, Address offset : 0x104 */
+ uint32_t RESERVED12[2];
+ __IO uint32_t PWM6CLK_SSR; /*!< PWM6CLK source select register, Address offset : 0x110 */
+ __IO uint32_t PWM6CLK_PVSR; /*!< PWM6CLK prescale value select register, Address offset : 0x114 */
+ uint32_t RESERVED13[2];
+ __IO uint32_t PWM7CLK_SSR; /*!< PWM7CLK source select register, Address offset : 0x120 */
+ __IO uint32_t PWM7CLK_PVSR; /*!< PWM7CLK prescale value select register, Address offset : 0x124 */
+ uint32_t RESERVED14[2];
+ __IO uint32_t RTC_HS_SSR; /*!< RTC High Speed source select register, Address offset : 0x130 */
+ __IO uint32_t RTC_HS_PVSR; /*!< RTC High Speed prescale value select register, Address offset : 0x134 */
+ uint32_t RESERVED15;
+ __IO uint32_t RTC_SSR; /*!< RTC source select register, Address offset : 0x13c */
+
+ __IO uint32_t WDOGCLK_HS_SSR; /*!< WDOGCLK High Speed source select register, Address offset : 0x140 */
+ __IO uint32_t WDOGCLK_HS_PVSR; /*!< WDOGCLK High Speed prescale value select register, Address offset : 0x144 */
+ uint32_t RESERVED16;
+ __IO uint32_t WDOGCLK_SSR; /*!< WDOGCLK source select register, Address offset : 0x14c */
+
+ __IO uint32_t UARTCLK_SSR; /*!< UARTCLK source select register, Address offset : 0x150 */
+ __IO uint32_t UARTCLK_PVSR; /*!< UARTCLK prescale value select register, Address offset : 0x154 */
+ uint32_t RESERVED17[2];
+ __IO uint32_t MIICLK_ECR; /*!< MII clock enable control register, Address offset : 0x160 */
+ uint32_t RESERVED18[3];
+ __IO uint32_t MONCLK_SSR; /*!< Monitoring clock source select I found Treasure was IoT Base Station in March.register, Address offset : 0x170 */
+}CRG_TypeDef;
+
+
+/**
+ * @brief UART
+ */
+typedef struct
+{
+ __IO uint32_t DR; /*!< Data, Address offset : 0x00 */
+ union {
+ __I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
+ __O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
+ } STATUS;
+ uint32_t RESERVED0[4];
+ __IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
+ uint32_t RESERVED1;
+ __IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
+ __IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
+ __IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
+ __IO uint32_t LCR_H; /*!< Line Control, Address offset : 0x2C */
+ __IO uint32_t CR; /*!< Control, Address offset : 0x30 */
+ __IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
+ __IO uint32_t IMSC; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
+ __IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
+ __IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
+ __O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
+ __IO uint32_t DMACR; /*!< DMA Control, Address offset : 0x48 */
+} UART_TypeDef;
+
+
+/**
+ * @brief Simple UART
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
+ __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
+ __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
+ union {
+ __I uint32_t STATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
+ __O uint32_t CLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
+ }INT;
+ __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
+
+} S_UART_TypeDef;
+
+/**
+ * @brief Analog Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ADC_CTR; /* ADC control register, Address offset : 0x000 */
+ __IO uint32_t ADC_CHSEL; /* ADC channel select register, Address offset : 0x004 */
+ __IO uint32_t ADC_START; /* ADC start register, Address offset : 0x008 */
+ __I uint32_t ADC_DATA; /* ADC conversion data register, Address offset : 0x00c */
+ __IO uint32_t ADC_INT; /* ADC interrupt register, Address offset : 0x010 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ADC_INTCLR; /* ADC interrupt clear register, Address offset : 0x01c */
+}ADC_TypeDef;
+
+/**
+ * @brief dualtimer
+ */
+typedef struct
+{
+ __IO uint32_t TimerLoad; // <h> Timer Load </h>
+ __I uint32_t TimerValue; // <h> Timer Counter Current Value <r></h>
+ __IO uint32_t TimerControl; // <h> Timer Control
+ // <o.7> TimerEn: Timer Enable
+ // <o.6> TimerMode: Timer Mode
+ // <0=> Freerunning-mode
+ // <1=> Periodic mode
+ // <o.5> IntEnable: Interrupt Enable
+ // <o.2..3> TimerPre: Timer Prescale
+ // <0=> / 1
+ // <1=> / 16
+ // <2=> / 256
+ // <3=> Undefined!
+ // <o.1> TimerSize: Timer Size
+ // <0=> 16-bit counter
+ // <1=> 32-bit counter
+ // <o.0> OneShot: One-shoot mode
+ // <0=> Wrapping mode
+ // <1=> One-shot mode
+ // </h>
+ __O uint32_t TimerIntClr; // <h> Timer Interrupt Clear <w></h>
+ __I uint32_t TimerRIS; // <h> Timer Raw Interrupt Status <r></h>
+ __I uint32_t TimerMIS; // <h> Timer Masked Interrupt Status <r></h>
+ __IO uint32_t TimerBGLoad; // <h> Background Load Register </h>
+} DUALTIMER_TypeDef;
+
+/**
+ * @brief GPIO
+ */
+typedef struct
+{
+ __IO uint32_t DATA; /* DATA Register (R/W), offset : 0x000 */
+ __IO uint32_t DATAOUT; /* Data Output Latch Register (R/W), offset : 0x004 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t OUTENSET; /* Output Enable Set Register (R/W) offset : 0x010 */
+ __IO uint32_t OUTENCLR; /* Output Enable Clear Register (R/W) offset : 0x014 */
+ __IO uint32_t RESERVED1; /* Alternate Function Set Register (R/W) offset : 0x018 */
+ __IO uint32_t RESERVED2; /* Alternate Function Clear Register (R/W) offset : 0x01C */
+ __IO uint32_t INTENSET; /* Interrupt Enable Set Register (R/W) offset : 0x020 */
+ __IO uint32_t INTENCLR; /* Interrupt Enable Clear Register (R/W) offset : 0x024 */
+ __IO uint32_t INTTYPESET; /* Interrupt Type Set Register (R/W) offset : 0x028 */
+ __IO uint32_t INTTYPECLR; /* Interrupt Type Clear Register (R/W) offset : 0x02C */
+ __IO uint32_t INTPOLSET; /* Interrupt Polarity Set Register (R/W) offset : 0x030 */
+ __IO uint32_t INTPOLCLR; /* Interrupt Polarity Clear Register (R/W) offset : 0x034 */
+ union {
+ __I uint32_t INTSTATUS; /* Interrupt Status Register (R/ ) offset : 0x038 */
+ __O uint32_t INTCLEAR; /* Interrupt Clear Register ( /W) offset : 0x038 */
+ }Interrupt;
+ uint32_t RESERVED3[241];
+ __IO uint32_t LB_MASKED[256]; /* Lower byte Masked Access Register (R/W) offset : 0x400 - 0x7FC */
+ __IO uint32_t UB_MASKED[256]; /* Upper byte Masked Access Register (R/W) offset : 0x800 - 0xBFC */
+} GPIO_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t Port[16]; /* Port_00, offset : 0x00 */
+ /* Port_01, offset : 0x04 */
+ /* Port_02, offset : 0x08 */
+ /* Port_03, offset : 0x0C */
+ /* Port_04, offset : 0x10 */
+ /* Port_05, offset : 0x14 */
+ /* Port_06, offset : 0x18 */
+ /* Port_07, offset : 0x1C */
+ /* Port_08, offset : 0x20 */
+ /* Port_09, offset : 0x24 */
+ /* Port_10, offset : 0x28 */
+ /* Port_11, offset : 0x2C */
+ /* Port_12, offset : 0x30 */
+ /* Port_13, offset : 0x34 */
+ /* Port_14, offset : 0x38 */
+ /* Port_15, offset : 0x3C */
+} P_Port_Def;
+
+typedef struct
+{
+ __IO uint32_t Port[5]; /* Port_00, offset : 0x00 */
+ /* Port_01, offset : 0x04 */
+ /* Port_02, offset : 0x08 */
+ /* Port_03, offset : 0x0C */
+ /* Port_04, offset : 0x10 */
+} P_Port_D_Def;
+
+/**
+ * @brief I2C Register structure definition
+ */
+typedef struct
+{
+ __IO uint32_t PRER; //0x00
+ __IO uint32_t CTR; //0x04
+ __IO uint32_t CMDR; //0x08
+ __I uint32_t SR; //0x0C
+ __IO uint32_t TSR; //0x10
+ __IO uint32_t SADDR; //0x14
+ __IO uint32_t TXR; //0x18
+ __I uint32_t RXR; //0x1C
+ __I uint32_t ISR; //0x20
+ __IO uint32_t ISCR; //0x24
+ __IO uint32_t ISMR; //0x28
+}I2C_TypeDef;
+
+/**
+ * @brief PWM Register structure definition
+ */
+typedef struct
+{
+ __IO uint32_t IER; //Interrupt enable register
+ // <7> IE7 : Channel 7 interrupt enable <R/W>
+ // <6> IE6 : Channel 6 interrupt enable <R/W>
+ // <5> IE5 : Channel 5 interrupt enable <R/W>
+ // <4> IE4 : Channel 4 interrupt enable <R/W>
+ // <3> IE3 : Channel 3 interrupt enable <R/W>
+ // <2> IE2 : Channel 2 interrupt enable <R/W>
+ // <1> IE1 : Channel 1 interrupt enable <R/W>
+ // <0> IE0 : Channel 0 interrupt enable <R/W>
+
+ __IO uint32_t SSR; //Start Stop register
+ // <7> SS7 : Channel 7 TC start or stop <R/W>
+ // <6> SS6 : Channel 6 TC start or stop <R/W>
+ // <5> SS5 : Channel 5 TC start or stop <R/W>
+ // <4> SS4 : Channel 4 TC start or stop <R/W>
+ // <3> SS3 : Channel 3 TC start or stop <R/W>
+ // <2> SS2 : Channel 2 TC start or stop <R/W>
+ // <1> SS1 : Channel 1 TC start or stop <R/W>
+ // <0> SS0 : Channel 0 TC start or stop <R/W>
+
+ __IO uint32_t PSR; //Pause register
+ // <7> PS7 : Channel 7 TC pasue <R/W>
+ // <6> PS6 : Channel 6 TC pasue <R/W>
+ // <5> PS5 : Channel 5 TC pasue <R/W>
+ // <4> PS4 : Channel 4 TC pasue <R/W>
+ // <3> PS3 : Channel 3 TC pasue <R/W>
+ // <2> PS2 : Channel 2 TC pasue <R/W>
+ // <1> PS1 : Channel 1 TC pasue <R/W>
+ // <0> PS0 : Channel 0 TC pasue <R/W>
+} PWM_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IR; //Interrupt register
+ // <2> CI : Capture interrupt <R>
+ // <1> OI : Overflow interrupt <R>
+ // <0> MI : Match interrupt <R>
+
+ __IO uint32_t IER; //Interrupt enable register
+ // <2> CIE : Capture interrupt enable <R/W>
+ // <1> OIE : Overflow interrupt enable <R/W>
+ // <0> MIE : Match interrupt enable <R/W>
+
+ __O uint32_t ICR; //Interrupt clear register
+ // <2> CIC : Capture interrupt clear <W>
+ // <1> OIC : Overflow interrupt clear <W>
+ // <0> MIC : Match interrupt clear <W>
+
+ __I uint32_t TCR; //Timer/Counter register
+ // <0..31> TCR : Timer/Counter register <R>
+
+ __I uint32_t PCR; //Prescale counter register
+ // <0..5> PCR : Prescale Counter register <R>
+
+ __IO uint32_t PR; //Prescale register
+ // <0..5> PR : prescale register <R/W>
+
+ __IO uint32_t MR; //Match register
+ // <0..31> MR : Match register <R/W>
+
+ __IO uint32_t LR; //Limit register
+ // <0..31> LR : Limit register <R/W>
+ __IO uint32_t UDMR; //Up-Down mode register
+ // <0> UDM : Up-down mode <R/W>
+
+ __IO uint32_t TCMR; //Timer/Counter mode register
+ // <0> TCM : Timer/Counter mode <R/W>
+
+ __IO uint32_t PEEER; //PWM output enable and external input enable register
+ // <0..1> PEEE : PWM output enable and external input enable <R/W>
+
+ __IO uint32_t CMR; //Capture mode register
+ // <0> CM : Capture mode <R/W>
+
+ __IO uint32_t CR; //Capture register
+ // <0..31> CR : Capture register <R>
+
+ __IO uint32_t PDMR; //Periodic mode register
+ // <0> PDM : Periodic mode <R/W>
+
+ __IO uint32_t DZER; //Dead-zone enable register
+ // <0> DZE : Dead-zone enable <R/W>
+
+ __IO uint32_t DZCR; //Dead-zone counter register
+ // <0..9> DZC : Dead-zone counter <R/W>
+} PWM_CHn_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t PWM_CHn_PR; //Prescale register
+ // <0..5> PR : prescale register <R/W>
+ __IO uint32_t PWM_CHn_MR; //Match register
+ // <0..31> MR : Match register <R/W>
+ __IO uint32_t PWM_CHn_LR; //Limit register
+ // <0..31> LR : Limit register <R/W>
+ __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
+ // <0> UDM : Up-down mode <R/W>
+ __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
+ // <0> PDM : Periodic mode <R/W>
+}PWM_TimerModeInitTypeDef;
+
+typedef struct
+{
+ __IO uint32_t PWM_CHn_PR; //Prescale register
+ // <0..5> PR : prescale register <R/W>
+ __IO uint32_t PWM_CHn_MR; //Match register
+ // <0..31> MR : Match register <R/W>
+ __IO uint32_t PWM_CHn_LR; //Limit register
+ // <0..31> LR : Limit register <R/W>
+ __IO uint32_t PWM_CHn_UDMR; //Up-Down mode register
+ // <0> UDM : Up-down mode <R/W>
+ __IO uint32_t PWM_CHn_PDMR; //Periodic mode register
+ // <0> PDM : Peiodic mode <R/W>
+ __IO uint32_t PWM_CHn_CMR; //Capture mode register
+ // <0> CM : Capture mode <R/W>
+}PWM_CaptureModeInitTypeDef;
+
+typedef struct
+{
+ __IO uint32_t PWM_CHn_MR;
+ __IO uint32_t PWM_CHn_LR;
+ __IO uint32_t PWM_CHn_UDMR;
+ __IO uint32_t PWM_CHn_PDMR;
+ __IO uint32_t PWM_CHn_TCMR;
+}PWM_CounterModeInitTypeDef;
+
+
+/**
+ * @brief Random Number generator
+ */
+typedef struct
+{
+ __IO uint32_t RNG_RUN; /* RNG run register, Address offset : 0x000 */
+ __IO uint32_t RNG_SEED; /* RNG seed value register, Address offset : 0x004 */
+ __IO uint32_t RNG_CLKSEL; /* RNG Clock source select register, Address offset : 0x008 */
+ __IO uint32_t RNG_MODE; /* RNG MODE select register, Address offset : 0x00c */
+ __I uint32_t RNG_RN; /* RNG random number value register, Address offset : 0x010 */
+ __IO uint32_t RNG_POLY; /* RNG polynomial register, Address offset : 0x014 */
+}RNG_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __IO uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} SSP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t WatchdogLoad; // <h> Watchdog Load Register </h>
+ __I uint32_t WatchdogValue; // <h> Watchdog Value Register </h>
+ __IO uint32_t WatchdogControl; // <h> Watchdog Control Register
+ // <o.1> RESEN: Reset enable
+ // <o.0> INTEN: Interrupt enable
+ // </h>
+ __O uint32_t WatchdogIntClr; // <h> Watchdog Clear Interrupt Register </h>
+ __I uint32_t WatchdogRIS; // <h> Watchdog Raw Interrupt Status Register </h>
+ __I uint32_t WatchdogMIS; // <h> Watchdog Interrupt Status Register </h>
+ uint32_t RESERVED[762];
+ __IO uint32_t WatchdogLock; // <h> Watchdog Lock Register </h>
+}WATCHDOG_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+/* Peripheral and SRAM base address */
+#define W7500x_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
+#define W7500x_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
+#define W7500x_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
+
+#define W7500x_RAM_BASE (0x20000000UL)
+#define W7500x_APB1_BASE (0x40000000UL)
+#define W7500x_APB2_BASE (0x41000000UL)
+#define W7500x_AHB_BASE (0x42000000UL)
+
+#define W7500x_UART0_BASE (W7500x_APB1_BASE + 0x0000C000UL)
+#define W7500x_UART1_BASE (W7500x_APB1_BASE + 0x0000D000UL)
+#define W7500x_UART2_BASE (W7500x_APB1_BASE + 0x00006000UL)
+
+#define W7500x_CRG_BASE (W7500x_APB2_BASE + 0x00001000UL)
+#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
+
+#define W7500x_INFO_BGT (0x0003FDB8)
+#define W7500x_INFO_OSC (0x0003FDBC)
+
+#define W7500x_TRIM_BGT (0x41001210)
+#define W7500x_TRIM_OSC (0x41001004)
+
+#define W7500x_DUALTIMER0_BASE (W7500x_APB1_BASE + 0x00001000ul)
+#define W7500x_DUALTIMER1_BASE (W7500x_APB1_BASE + 0x00002000ul)
+
+#define EXTI_Px_BASE (W7500x_APB2_BASE + 0x00002200UL)
+
+#define GPIOA_BASE (W7500x_AHB_BASE + 0x00000000UL) // W7500x_AHB_BASE : 0x42000000UL
+#define GPIOB_BASE (W7500x_AHB_BASE + 0x01000000UL)
+#define GPIOC_BASE (W7500x_AHB_BASE + 0x02000000UL)
+#define GPIOD_BASE (W7500x_AHB_BASE + 0x03000000UL)
+
+#define P_AFSR_BASE (W7500x_APB2_BASE + 0x00002000UL)
+
+#define P_PCR_BASE (W7500x_APB2_BASE + 0x00003000UL)
+
+#define I2C0_BASE (W7500x_APB1_BASE + 0x8000)
+#define I2C1_BASE (W7500x_APB1_BASE + 0x9000)
+
+#define W7500x_PWM_BASE (W7500x_APB1_BASE + 0x00005000UL)
+
+#define W7500x_RNG_BASE (W7500x_APB1_BASE + 0x00007000UL)
+
+#define SSP0_BASE (0x4000A000)
+#define SSP1_BASE (0x4000B000)
+
+#define W7500x_WATCHDOG_BASE (W7500x_APB1_BASE + 0x0000UL)
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define CRG ((CRG_TypeDef *) W7500x_CRG_BASE)
+
+#define UART0 ((UART_TypeDef *) W7500x_UART0_BASE)
+#define UART1 ((UART_TypeDef *) W7500x_UART1_BASE)
+#define UART2 ((S_UART_TypeDef *) W7500x_UART2_BASE)
+
+#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
+
+#define DUALTIMER0_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE) )
+#define DUALTIMER0_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER0_BASE + 0x20ul))
+#define DUALTIMER1_0 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE) )
+#define DUALTIMER1_1 ((DUALTIMER_TypeDef *) (W7500x_DUALTIMER1_BASE + 0x20ul))
+
+#define EXTI_PA ((P_Port_Def *) (EXTI_Px_BASE + 0x00000000UL)) /* PA_XX External interrupt Enable Register */
+#define EXTI_PB ((P_Port_Def *) (EXTI_Px_BASE + 0x00000040UL)) /* PB_XX External interrupt Enable Register */
+#define EXTI_PC ((P_Port_Def *) (EXTI_Px_BASE + 0x00000080UL)) /* PC_XX External interrupt Enable Register */
+#define EXTI_PD ((P_Port_D_Def *) (EXTI_Px_BASE + 0x000000C0UL)) /* PD_XX External interrupt Enable Register */
+
+#define GPIOA ((GPIO_TypeDef *) (GPIOA_BASE) )
+#define GPIOB ((GPIO_TypeDef *) (GPIOB_BASE) )
+#define GPIOC ((GPIO_TypeDef *) (GPIOC_BASE) )
+#define GPIOD ((GPIO_TypeDef *) (GPIOD_BASE) )
+
+#define PA_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000000UL)) /* PA_XX Pad Alternate Function Select Register */
+#define PB_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000040UL)) /* PB_XX Pad Alternate Function Select Register */
+#define PC_AFSR ((P_Port_Def *) (P_AFSR_BASE + 0x00000080UL)) /* PC_XX Pad Alternate Function Select Register */
+#define PD_AFSR ((P_Port_D_Def *) (P_AFSR_BASE + 0x000000C0UL)) /* PD_XX Pad Alternate Function Select Register */
+
+#define PA_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000000UL)) /* PA_XX Pad Control Register */
+#define PB_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000040UL)) /* PB_XX Pad Control Register */
+#define PC_PCR ((P_Port_Def *) (P_PCR_BASE + 0x00000080UL)) /* PC_XX Pad Control Register */
+#define PD_PCR ((P_Port_D_Def *) (P_PCR_BASE + 0x000000C0UL)) /* PD_XX Pad Control Register */
+
+#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+
+
+#define TIMCLKEN0_0 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0x80ul)
+#define TIMCLKEN0_1 *(uint32_t *)(W7500x_DUALTIMER0_BASE + 0xA0ul)
+#define TIMCLKEN1_0 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0x80ul)
+#define TIMCLKEN1_1 *(uint32_t *)(W7500x_DUALTIMER1_BASE + 0xA0ul)
+
+#define PWM ((PWM_TypeDef *) (W7500x_PWM_BASE + 0x800UL ))
+#define PWM_CH0 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE))
+#define PWM_CH1 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x100UL))
+#define PWM_CH2 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x200UL))
+#define PWM_CH3 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x300UL))
+#define PWM_CH4 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x400UL))
+#define PWM_CH5 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x500UL))
+#define PWM_CH6 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x600UL))
+#define PWM_CH7 ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + 0x700UL))
+
+#define PWM_CH0_BASE (W7500x_PWM_BASE)
+#define PWM_CH1_BASE (W7500x_PWM_BASE + 0x100UL)
+#define PWM_CH2_BASE (W7500x_PWM_BASE + 0x200UL)
+#define PWM_CH3_BASE (W7500x_PWM_BASE + 0x300UL)
+#define PWM_CH4_BASE (W7500x_PWM_BASE + 0x400UL)
+#define PWM_CH5_BASE (W7500x_PWM_BASE + 0x500UL)
+#define PWM_CH6_BASE (W7500x_PWM_BASE + 0x600UL)
+#define PWM_CH7_BASE (W7500x_PWM_BASE + 0x700UL)
+
+#define RNG ((RNG_TypeDef *) W7500x_RNG_BASE)
+
+#define SSP0 ((SSP_TypeDef*) (SSP0_BASE))
+#define SSP1 ((SSP_TypeDef*) (SSP1_BASE))
+
+#define WATCHDOG ((WATCHDOG_TypeDef *) W7500x_WATCHDOG_BASE)
+
+/**
+ * @}
+ */
+
+
+
+/******************************************************************************/
+/* */
+/* Clock Reset Generator */
+/* */
+/******************************************************************************/
+/**************** Bit definition for CRG_OSC_PDR **************************/
+#define CRG_OSC_PDR_NRMLOP (0x0ul) // Normal Operation
+#define CRG_OSC_PDR_PD (0x1ul) // Power Down
+/**************** Bit definition for CRG_PLL_PDR **************************/
+#define CRG_PLL_PDR_PD (0x0ul) // Power Down
+#define CRG_PLL_PDR_NRMLOP (0x1ul) // Normal Operation
+/**************** Bit definition for CRG_PLL_FCR **************************/
+//ToDo
+/**************** Bit definition for CRG_PLL_OER **************************/
+#define CRG_PLL_OER_DIS (0x0ul) // Clock out is disable
+#define CRG_PLL_OER_EN (0x1ul) // Clock out is enable
+/**************** Bit definition for CRG_PLL_BPR **************************/
+#define CRG_PLL_BPR_DIS (0x0ul) // Bypass disable. Normal operation
+#define CRG_PLL_BPR_EN (0x1ul) // Bypass enable. Clock will be set to external clock
+/**************** Bit definition for CRG_PLL_IFSR **************************/
+#define CRG_PLL_IFSR_RCLK (0x0ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_PLL_IFSR_OCLK (0x1ul) // External oscillator clock (OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_FCLK_SSR **************************/
+#define CRG_FCLK_SSR_MCLK (0x01ul) // 00,01 Output clock of PLL(MCLK)
+#define CRG_FCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_FCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_FCLK_PVSR **************************/
+#define CRG_FCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
+#define CRG_FCLK_PVSR_DIV2 (0x01ul) // 1/2
+#define CRG_FCLK_PVSR_DIV4 (0x02ul) // 1/4
+#define CRG_FCLK_PVSR_DIV8 (0x03ul) // 1/8
+/**************** Bit definition for CRG_SSPCLK_SSR **************************/
+#define CRG_SSPCLK_SSR_DIS (0x00ul) // Disable clock
+#define CRG_SSPCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
+#define CRG_SSPCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_SSPCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_SSPCLK_PVSR **************************/
+#define CRG_SSPCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
+#define CRG_SSPCLK_PVSR_DIV2 (0x01ul) // 1/2
+#define CRG_SSPCLK_PVSR_DIV4 (0x02ul) // 1/4
+#define CRG_SSPCLK_PVSR_DIV8 (0x03ul) // 1/8
+/**************** Bit definition for CRG_ADCCLK_SSR **************************/
+#define CRG_ADCCLK_SSR_DIS (0x00ul) // Disable clock
+#define CRG_ADCCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
+#define CRG_ADCCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_ADCCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_ADCCLK_PVSR **************************/
+#define CRG_ADCCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
+#define CRG_ADCCLK_PVSR_DIV2 (0x01ul) // 1/2
+#define CRG_ADCCLK_PVSR_DIV4 (0x02ul) // 1/4
+#define CRG_ADCCLK_PVSR_DIV8 (0x03ul) // 1/8
+/**************** Bit definition for CRG_TIMER0/1CLK_SSR **************************/
+#define CRG_TIMERCLK_SSR_DIS (0x00ul) // Disable clock
+#define CRG_TIMERCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
+#define CRG_TIMERCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_TIMERCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_TIMER0/1CLK_PVSR **************************/
+#define CRG_TIMERCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
+#define CRG_TIMERCLK_PVSR_DIV2 (0x01ul) // 1/2
+#define CRG_TIMERCLK_PVSR_DIV4 (0x02ul) // 1/4
+#define CRG_TIMERCLK_PVSR_DIV8 (0x03ul) // 1/8
+#define CRG_TIMERCLK_PVSR_DIV16 (0x04ul) // 1/16
+#define CRG_TIMERCLK_PVSR_DIV32 (0x05ul) // 1/32
+#define CRG_TIMERCLK_PVSR_DIV64 (0x06ul) // 1/64
+#define CRG_TIMERCLK_PVSR_DIV128 (0x07ul) // 1/128
+/**************** Bit definition for CRG_PWMnCLK_SSR **************************/
+#define CRG_PWMCLK_SSR_DIS (0x00ul) // Disable clock
+#define CRG_PWMCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
+#define CRG_PWMCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_PWMCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_PWMnCLK_PVSR **************************/
+#define CRG_PWMCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
+#define CRG_PWMCLK_PVSR_DIV2 (0x01ul) // 1/2
+#define CRG_PWMCLK_PVSR_DIV4 (0x02ul) // 1/4
+#define CRG_PWMCLK_PVSR_DIV8 (0x03ul) // 1/8
+#define CRG_PWMCLK_PVSR_DIV16 (0x04ul) // 1/16
+#define CRG_PWMCLK_PVSR_DIV32 (0x05ul) // 1/32
+#define CRG_PWMCLK_PVSR_DIV64 (0x06ul) // 1/64
+#define CRG_PWMCLK_PVSR_DIV128 (0x07ul) // 1/128
+/**************** Bit definition for CRG_RTC_HS_SSR **************************/
+#define CRG_RTC_HS_SSR_DIS (0x00ul) // Disable clock
+#define CRG_RTC_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
+#define CRG_RTC_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_RTC_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_RTC_HS_PVSR **************************/
+#define CRG_RTC_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
+#define CRG_RTC_HS_PVSR_DIV2 (0x01ul) // 1/2
+#define CRG_RTC_HS_PVSR_DIV4 (0x02ul) // 1/4
+#define CRG_RTC_HS_PVSR_DIV8 (0x03ul) // 1/8
+#define CRG_RTC_HS_PVSR_DIV16 (0x04ul) // 1/16
+#define CRG_RTC_HS_PVSR_DIV32 (0x05ul) // 1/32
+#define CRG_RTC_HS_PVSR_DIV64 (0x06ul) // 1/64
+#define CRG_RTC_HS_PVSR_DIV128 (0x07ul) // 1/128
+/**************** Bit definition for CRG_RTC_SSR **************************/
+#define CRG_RTC_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
+#define CRG_RTC_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
+/**************** Bit definition for CRG_WDOGCLK_HS_SSR **************************/
+#define CRG_WDOGCLK_HS_SSR_DIS (0x00ul) // Disable clock
+#define CRG_WDOGCLK_HS_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
+#define CRG_WDOGCLK_HS_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_WDOGCLK_HS_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_WDOGCLK_HS_PVSR **************************/
+#define CRG_WDOGCLK_HS_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
+#define CRG_WDOGCLK_HS_PVSR_DIV2 (0x01ul) // 1/2
+#define CRG_WDOGCLK_HS_PVSR_DIV4 (0x02ul) // 1/4
+#define CRG_WDOGCLK_HS_PVSR_DIV8 (0x03ul) // 1/8
+#define CRG_WDOGCLK_HS_PVSR_DIV16 (0x04ul) // 1/16
+#define CRG_WDOGCLK_HS_PVSR_DIV32 (0x05ul) // 1/32
+#define CRG_WDOGCLK_HS_PVSR_DIV64 (0x06ul) // 1/64
+#define CRG_WDOGCLK_HS_PVSR_DIV128 (0x07ul) // 1/128
+/**************** Bit definition for CRG_WDOGCLK_SSR **************************/
+#define CRG_WDOGCLK_SSR_HS (0x00ul) // RTCCLK HS(High Speed clock)
+#define CRG_WDOGCLK_SSR_LW (0x01ul) // 32K_OSC_CLK(Low Speed external oscillator clock)
+/**************** Bit definition for CRG_UARTCLK_SSR **************************/
+#define CRG_UARTCLK_SSR_DIS (0x00ul) // Disable clock
+#define CRG_UARTCLK_SSR_MCLK (0x01ul) // PLL output clock(MCLK)
+#define CRG_UARTCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_UARTCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+/**************** Bit definition for CRG_UARTCLK_PVSR **************************/
+#define CRG_UARTCLK_PVSR_DIV1 (0x00ul) // 1/1 (bypass)
+#define CRG_UARTCLK_PVSR_DIV2 (0x01ul) // 1/2
+#define CRG_UARTCLK_PVSR_DIV4 (0x02ul) // 1/4
+#define CRG_UARTCLK_PVSR_DIV8 (0x03ul) // 1/8
+/**************** Bit definition for CRG_MIICLK_ECR **************************/
+#define CRG_MIICLK_ECR_EN_RXCLK (0x01ul << 0) // Enable MII_RCK and MII_RCK_N
+#define CRG_MIICLK_ECR_EN_TXCLK (0x01ul << 1) // Enable MII_TCK and MII_TCK_N
+/**************** Bit definition for CRG_MONCLK_SSR **************************/
+#define CRG_MONCLK_SSR_MCLK (0x00ul) // PLL output clock (MCLK)
+#define CRG_MONCLK_SSR_FCLK (0x01ul) // FCLK
+#define CRG_MONCLK_SSR_RCLK (0x02ul) // Internal 8MHz RC oscillator clock(RCLK)
+#define CRG_MONCLK_SSR_OCLK (0x03ul) // External oscillator clock(OCLK, 8MHz ~ 24MHz)
+#define CRG_MONCLK_SSR_ADCCLK (0x04ul) // ADCCLK
+#define CRG_MONCLK_SSR_SSPCLK (0x05ul) // SSPCLK
+#define CRG_MONCLK_SSR_TIMCLK0 (0x06ul) // TIMCLK0
+#define CRG_MONCLK_SSR_TIMCLK1 (0x07ul) // TIMCLK1
+#define CRG_MONCLK_SSR_PWMCLK0 (0x08ul) // PWMCLK0
+#define CRG_MONCLK_SSR_PWMCLK1 (0x09ul) // PWMCLK1
+#define CRG_MONCLK_SSR_PWMCLK2 (0x0Aul) // PWMCLK2
+#define CRG_MONCLK_SSR_PWMCLK3 (0x0Bul) // PWMCLK3
+#define CRG_MONCLK_SSR_PWMCLK4 (0x0Cul) // PWMCLK4
+#define CRG_MONCLK_SSR_PWMCLK5 (0x0Dul) // PWMCLK5
+#define CRG_MONCLK_SSR_PWMCLK6 (0x0Eul) // PWMCLK6
+#define CRG_MONCLK_SSR_PWMCLK7 (0x0Ful) // PWMCLK7
+#define CRG_MONCLK_SSR_UARTCLK (0x10ul) // UARTCLK
+#define CRG_MONCLK_SSR_MII_RXCLK (0x11ul) // MII_RXCLK
+#define CRG_MONCLK_SSR_MII_TXCLK (0x12ul) // MII_TXCLK
+#define CRG_MONCLK_SSR_RTCCLK (0x13ul) // RTCCLK
+
+/******************************************************************************/
+/* */
+/* UART */
+/* */
+/******************************************************************************/
+/****************** Bit definition for UART Data(UARTDR) register *************************/
+#define UART_DR_OE (0x01ul << 11) // Overrun Error
+#define UART_DR_BE (0x01ul << 10) // Break Error
+#define UART_DR_PE (0x01ul << 9) // Parity Error
+#define UART_DR_FE (0x01ul << 8) // Framing Error
+//#define UART_DR_DR // ToDo
+/***************** Bit definition for UART Receive Status(UARTRSR) register ***************/
+#define UARTR_SR_OE (0x01ul << 3) // Overrun Error
+#define UARTR_SR_BE (0x01ul << 2) // Break Error
+#define UARTR_SR_PE (0x01ul << 1) // Parity Error
+#define UARTR_SR_FE (0x01ul << 0) // Framing Error
+/***************** Bit definition for UART Error Clear(UARTECR) register ******************/
+#define UARTE_CR_OE (0x01ul << 3) // Overrun Error
+#define UARTE_CR_BE (0x01ul << 2) // Break Error
+#define UARTE_CR_PE (0x01ul << 1) // Parity Error
+#define UARTE_CR_FE (0x01ul << 0) // Framing Error
+/****************** Bit definition for UART Flags(UARTFR) register ************************/
+#define UART_FR_RI (0x01ul << 8) // Ring indicator
+#define UART_FR_TXFE (0x01ul << 7) // Transmit FIFO empty
+#define UART_FR_RXFF (0x01ul << 6) // Receive FIFO full
+#define UART_FR_TXFF (0x01ul << 5) // Transmit FIFO full
+#define UART_FR_RXFE (0x01ul << 4) // Receive FIFO empty
+#define UART_FR_BUSY (0x01ul << 3) // UART busy
+#define UART_FR_DCD (0x01ul << 2) // Data carrier detect
+#define UART_FR_DSR (0x01ul << 1) // Data set ready
+#define UART_FR_CTS (0x01ul << 0) // Clear to send
+/********** Bit definition for UART Low-power Counter(UARTILPR) register *******************/
+#define UARTILPR_COUNTER (0xFFul << 0) // 8-bit low-power divisor value (0..255)
+/********************* Bit definition for Line Control(UARTLCR_H) register *****************/
+#define UART_LCR_H_SPS (0x1ul << 7) // Stick parity select
+#define UART_LCR_H_WLEN(n) ((n & 0x3ul) << 5) // Word length ( 0=5bits, 1=6bits, 2=7bits, 3=8bits )
+#define UART_LCR_H_FEN (0x1ul << 4) // Enable FIFOs
+#define UART_LCR_H_STP2 (0x1ul << 3) // Two stop bits select
+#define UART_LCR_H_EPS (0x1ul << 2) // Even parity select
+#define UART_LCR_H_PEN (0x1ul << 1) // Parity enable
+#define UART_LCR_H_BRK (0x1ul << 0) // Send break
+/********************* Bit definition for Contro(UARTCR) register *************************/
+#define UART_CR_CTSEn (0x1ul << 15) // CTS hardware flow control enable
+#define UART_CR_RTSEn (0x1ul << 14) // RTS hardware flow control enable
+#define UART_CR_Out2 (0x1ul << 13) // Complement of Out2 modem status output
+#define UART_CR_Out1 (0x1ul << 12) // Complement of Out1 modem status output
+#define UART_CR_RTS (0x1ul << 11) // Request to send
+#define UART_CR_DTR (0x1ul << 10) // Data transmit ready
+#define UART_CR_RXE (0x1ul << 9) // Receive enable
+#define UART_CR_TXE (0x1ul << 8) // Transmit enable
+#define UART_CR_LBE (0x1ul << 7) // Loop-back enable
+#define UART_CR_SIRLP (0x1ul << 2) // IrDA SIR low power mode
+#define UART_CR_SIREN (0x1ul << 1) // SIR enable
+#define UART_CR_UARTEN (0x1ul << 0) // UART enable
+/******* Bit definition for Interrupt FIFO Level Select(UARTIFLS) register *****************/
+#define UART_IFLS_RXIFLSEL(n) ((n & 0x7ul) << 3) // Receive interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
+#define UART_IFLS_TXIFLSEL(n) ((n & 0x7ul) << 0) // Transmit interrupt FIFO level select(0=1/8 full, 1=1/4 full, 2=1/2 full, 3=3/4 full, 4=7/8 full)
+/******* Bit definition for Interrupt Mask Set/Clear(UARTIMSC) register ********************/
+#define UART_IMSC_OEIM (0x1ul << 10) // Overrun error interrupt mask
+#define UART_IMSC_BEIM (0x1ul << 9) // Break error interrupt mask
+#define UART_IMSC_PEIM (0x1ul << 8) // Parity error interrupt mask
+#define UART_IMSC_FEIM (0x1ul << 7) // Framing error interrupt mask
+#define UART_IMSC_RTIM (0x1ul << 6) // Receive interrupt mask
+#define UART_IMSC_TXIM (0x1ul << 5) // Transmit interrupt mask
+#define UART_IMSC_RXIM (0x1ul << 4) // Receive interrupt mask
+#define UART_IMSC_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt mask
+#define UART_IMSC_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt mask
+#define UART_IMSC_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt mask
+#define UART_IMSC_RIMIM (0x1ul << 0) // nUARTRI modem interrupt mask
+/*************** Bit definition for Raw Interrupt Status(UARTRIS) register *****************/
+#define UART_RIS_OEIM (0x1ul << 10) // Overrun error interrupt status
+#define UART_RIS_BEIM (0x1ul << 9) // Break error interrupt status
+#define UART_RIS_PEIM (0x1ul << 8) // Parity error interrupt status
+#define UART_RIS_FEIM (0x1ul << 7) // Framing error interrupt status
+#define UART_RIS_RTIM (0x1ul << 6) // Receive interrupt status
+#define UART_RIS_TXIM (0x1ul << 5) // Transmit interrupt status
+#define UART_RIS_RXIM (0x1ul << 4) // Receive interrupt status
+#define UART_RIS_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt status
+#define UART_RIS_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt status
+#define UART_RIS_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt status
+#define UART_RIS_RIMIM (0x1ul << 0) // nUARTRI modem interrupt status
+/************** Bit definition for Masked Interrupt Status(UARTMIS) register ****************/
+#define UART_MIS_OEIM (0x1ul << 10) // Overrun error masked interrupt status
+#define UART_MIS_BEIM (0x1ul << 9) // Break error masked interrupt status
+#define UART_MIS_PEIM (0x1ul << 8) // Parity error masked interrupt status
+#define UART_MIS_FEIM (0x1ul << 7) // Framing error masked interrupt status
+#define UART_MIS_RTIM (0x1ul << 6) // Receive masked interrupt status
+#define UART_MIS_TXIM (0x1ul << 5) // Transmit masked interrupt status
+#define UART_MIS_RXIM (0x1ul << 4) // Receive masked interrupt status
+#define UART_MIS_DSRMIM (0x1ul << 3) // nUARTDSR modem masked interrupt status
+#define UART_MIS_DCDMIM (0x1ul << 2) // nUARTDCD modem masked interrupt status
+#define UART_MIS_CTSMIM (0x1ul << 1) // nUARTCTS modem masked interrupt status
+#define UART_MIS_RIMIM (0x1ul << 0) // nUARTRI modem masked interrupt status
+/*************** Bit definition for Interrupt Clear(UARTICR) register ************************/
+#define UART_ICR_OEIM (0x1ul << 10) // Overrun error interrupt clear
+#define UART_ICR_BEIM (0x1ul << 9) // Break error interrupt clear
+#define UART_ICR_PEIM (0x1ul << 8) // Parity error interrupt clear
+#define UART_ICR_FEIM (0x1ul << 7) // Framing error interrupt clear
+#define UART_ICR_RTIM (0x1ul << 6) // Receive interrupt clear
+#define UART_ICR_TXIM (0x1ul << 5) // Transmit interrupt clear
+#define UART_ICR_RXIM (0x1ul << 4) // Receive interrupt clear
+#define UART_ICR_DSRMIM (0x1ul << 3) // nUARTDSR modem interrupt clear
+#define UART_ICR_DCDMIM (0x1ul << 2) // nUARTDCD modem interrupt clear
+#define UART_ICR_CTSMIM (0x1ul << 1) // nUARTCTS modem interrupt clear
+#define UART_ICR_RIMIM (0x1ul << 0) // nUARTRI modem interrupt clear
+/***************** Bit definition for DMA Control(UARTDMACR) register ************************/
+#define UART_DMACR_DMAONERR (0x1ul << 2) // DMA on error
+#define UART_DMACR_TXDMAE (0x1ul << 1) // Transmit DMA enable
+#define UART_DMACR_RXDMAE (0x1ul << 0) // Receive DMA enable
+
+/******************************************************************************/
+/* */
+/* Simple UART */
+/* */
+/******************************************************************************/
+/***************** Bit definition for S_UART Data () register ************************/
+#define S_UART_DATA (0xFFul << 0)
+/***************** Bit definition for S_UART State() register ************************/
+#define S_UART_STATE_TX_BUF_OVERRUN (0x01ul << 2) // TX buffer overrun, wirte 1 to clear.
+#define S_UART_STATE_RX_BUF_FULL (0x01ul << 1) // RX buffer full, read only.
+#define S_UART_STATE_TX_BUF_FULL (0x01ul << 0) // TX buffer full, read only.
+/***************** Bit definition for S_UART Control() register ************************/
+#define S_UART_CTRL_HIGH_SPEED_TEST (0x01ul << 6) // High-speed test mode for TX only.
+#define S_UART_CTRL_RX_OVERRUN_EN (0x01ul << 5) // RX overrun interrupt enable.
+#define S_UART_CTRL_TX_OVERRUN_EN (0x01ul << 4) // TX overrun interrupt enable.
+#define S_UART_CTRL_RX_INT_EN (0x01ul << 3) // RX interrupt enable.
+#define S_UART_CTRL_TX_INT_EN (0x01ul << 2) // TX interrupt enable.
+#define S_UART_CTRL_RX_EN (0x01ul << 1) // RX enable.
+#define S_UART_CTRL_TX_EN (0x01ul << 0) // TX enable.
+/***************** Bit definition for S_UART Interrupt() register ************************/
+#define S_UART_INT_RX_OVERRUN (0x01ul << 3) // RX overrun interrupt. Wirte 1 to clear
+#define S_UART_INT_TX_OVERRUN (0x01ul << 2) // TX overrun interrupt. Write 1 to clear
+#define S_UART_INT_RX (0x01ul << 1) // RX interrupt. Write 1 to clear
+#define S_UART_INT_TX (0x01ul << 0) // TX interrupt. Write 1 to clear
+
+/******************************************************************************/
+/* */
+/* Analog Digital Register */
+/* */
+/******************************************************************************/
+
+/*********************** Bit definition for ADC_CTR ***********************/
+//#define ADC_CTR_SAMSEL_ABNORMAL (0x0ul) // Abnormal Operation
+//#define ADC_CTR_SAMSEL_NORMAL (0x1ul) // Normal Operation
+#define ADC_CTR_PWD_NRMOP (0x1ul) // Active Operation
+#define ADC_CTR_PWD_PD (0x3ul) // Power down
+/*********************** Bit definition for ADC_CHSEL ***********************/
+#define ADC_CHSEL_CH0 (0x0ul) // Channel 0
+#define ADC_CHSEL_CH1 (0x1ul) // Channel 1
+#define ADC_CHSEL_CH2 (0x2ul) // Channel 2
+#define ADC_CHSEL_CH3 (0x3ul) // Channel 3
+#define ADC_CHSEL_CH4 (0x4ul) // Channel 4
+#define ADC_CHSEL_CH5 (0x5ul) // Channel 5
+#define ADC_CHSEL_CH6 (0x6ul) // Channel 6
+#define ADC_CHSEL_CH7 (0x7ul) // Channel 7
+#define ADC_CHSEL_CH15 (0xful) // LDO output(1.5V)
+/*********************** Bit definition for ADC_START ***********************/
+#define ADC_START_START (0x1ul) // ADC conversion start
+/*********************** Bit definition for ADC_DATA ***********************/
+//ToDo (Readonly)
+
+/*********************** Bit definition for ADC_INT ***********************/
+#define ADC_INT_MASK_DIS (0x0ul << 1) // Interrupt disable
+#define ADC_INT_MASK_ENA (0x1ul << 1) // Interrupt enable
+//ToDo (Readonly)
+
+/*********************** Bit definition for ADC_INTCLR ***********************/
+#define ADC_INTCLEAR (0x1ul) // ADC Interrupt clear
+
+#define W7500x_ADC_BASE (W7500x_APB2_BASE + 0x00000000UL)
+#define ADC ((ADC_TypeDef *) W7500x_ADC_BASE)
+
+/******************************************************************************/
+/* */
+/* Dual Timer */
+/* */
+/******************************************************************************/
+
+/*********************** Bit definition for dualtimer ***********************/
+#define DUALTIMER_TimerControl_TimerDIsable 0x0ul
+#define DUALTIMER_TimerControl_TimerEnable 0x1ul
+#define DUALTIMER_TimerControl_TimerEnable_Pos 7
+
+#define DUALTIMER_TimerControl_FreeRunning 0x0ul
+#define DUALTIMER_TimerControl_Periodic 0x1ul
+#define DUALTIMER_TimerControl_TimerMode_Pos 6
+
+#define DUALTIMER_TimerControl_IntDisable 0x0ul
+#define DUALTIMER_TimerControl_IntEnable 0x1ul
+#define DUALTIMER_TimerControl_IntEnable_Pos 5
+
+#define DUALTIMER_TimerControl_Pre_1 0x0ul
+#define DUALTIMER_TimerControl_Pre_16 0x1ul
+#define DUALTIMER_TimerControl_Pre_256 0x2ul
+#define DUALTIMER_TimerControl_Pre_Pos 2
+
+#define DUALTIMER_TimerControl_Size_16 0x0ul
+#define DUALTIMER_TimerControl_Size_32 0x1ul
+#define DUALTIMER_TimerControl_Size_Pos 1
+
+#define DUALTIMER_TimerControl_Wrapping 0x0ul
+#define DUALTIMER_TimerControl_OneShot 0x1ul
+#define DUALTIMER_TimerControl_OneShot_Pos 0
+
+/******************************************************************************/
+/* */
+/* External Interrupt */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for Px_IER **************************/
+#define EXTI_Px_INTPOR_RISING_EDGE (0x00ul << 0)
+#define EXTI_Px_INTPOR_FALLING_EDGE (0x01ul << 0)
+#define EXTI_Px_INTEN_DISABLE (0x00ul << 1)
+#define EXTI_Px_INTEN_ENABLE (0x01ul << 1)
+
+/******************************************************************************/
+/* */
+/* GPIO */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for Px_AFSR **************************/
+#define Px_AFSR_AF0 (0x00ul)
+#define Px_AFSR_AF1 (0x01ul)
+#define Px_AFSR_AF2 (0x02ul)
+#define Px_AFSR_AF3 (0x03ul)
+/**************** Bit definition for Px_PCR **************************/
+#define Px_PCR_PUPD_DOWN (0x01ul << 0) // Pull Down
+#define Px_PCR_PUPD_UP (0x01ul << 1) // Pull Up
+#define Px_PCR_DS_HIGH (0x01ul << 2) // High Driving
+#define Px_PCR_OD (0x01ul << 3) // Open Drain
+#define Px_PCR_IE (0x01ul << 5) // Input Buffer Enable
+#define Px_PCR_CS_SUMMIT (0x01ul << 6) // Use Summit Trigger Input Buffer
+
+/******************************************************************************/
+/* */
+/* I2C */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for I2C_CTR **************************/
+#define I2C_CTR_COREEN (0x01ul << 7 ) // 0x80
+#define I2C_CTR_INTEREN (0x01ul << 6 ) // 0x40
+#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
+#define I2C_CTR_ADDR10 (0x01ul << 4 ) // 0x10
+#define I2C_CTR_CTRRWN (0x01ul << 3 ) // 0x08
+#define I2C_CTR_CTEN (0x01ul << 2 ) // 0x04
+
+/**************** Bit definition for I2C_CMDR **************************/
+#define I2C_CMDR_STA (0x01ul << 7 ) // 0x80
+#define I2C_CMDR_STO (0x01ul << 6 ) // 0x40
+#define I2C_CMDR_ACK (0x01ul << 5 ) // 0x20
+#define I2C_CMDR_RESTA (0x01ul << 4 ) // 0x10
+
+/**************** Bit definition for I2C_ISCR **************************/
+#define I2C_ISCR_RST (0x01ul << 1) // 0x01
+
+/**************** Bit definition for I2C_SR **************************/
+#define I2C_SR_TX (0x01ul << 9 ) // 0x200
+#define I2C_SR_RX (0x01ul << 8 ) // 0x100
+#define I2C_SR_ACKT (0x01ul << 7 ) // 0x080
+#define I2C_SR_BT (0x01ul << 6 ) // 0x040
+#define I2C_SR_SA (0x01ul << 5 ) // 0x020
+#define I2C_SR_SB (0x01ul << 4 ) // 0x010
+#define I2C_SR_AL (0x01ul << 3 ) // 0x008
+#define I2C_SR_TO (0x01ul << 2 ) // 0x004
+#define I2C_SR_SRW (0x01ul << 1 ) // 0x002
+#define I2C_SR_ACKR (0x01ul << 0 ) // 0x001
+
+/**************** Bit definition for I2C_ISR **************************/
+#define I2C_ISR_STAE (0x01ul << 4 ) // 0x010
+#define I2C_ISR_STOE (0x01ul << 3 ) // 0x008
+#define I2C_ISR_TOE (0x01ul << 2 ) // 0x004
+#define I2C_ISR_ACK_RXE (0x01ul << 1 ) // 0x002
+#define I2C_ISR_ACK_TXE (0x01ul << 0 ) // 0x001
+
+/**************** Bit definition for I2C_ISMR **************************/
+#define I2C_ISR_STAEM (0x01ul << 4 ) // 0x010
+#define I2C_ISR_STOEM (0x01ul << 3 ) // 0x008
+#define I2C_ISR_TOEM (0x01ul << 2 ) // 0x004
+#define I2C_ISR_ACK_RXEM (0x01ul << 1 ) // 0x002
+#define I2C_ISR_ACK_TXEM (0x01ul << 0 ) // 0x001
+
+/******************************************************************************/
+/* */
+/* PWM */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Random number generator Register */
+/* */
+/******************************************************************************/
+
+/*********************** Bit definition for RNG_RUN ***********************/
+#define RNG_RUN_STOP (0x0ul) // STOP RNG shift register
+#define RNG_RUN_RUN (0x1ul) // RUN RNG shift register
+/*********************** Bit definition for RNG_SEED ***********************/
+//ToDo
+
+/*********************** Bit definition for RNG_CLKSEL ***********************/
+#define RNG_CLKSEL_RNGCLK (0x0ul) // RNGCLK is source clock for rng shift register
+#define RNG_CLKSEL_APBCLK (0x1ul) // APBCLK is source clock for rng shift register
+/*********************** Bit definition for RNG_ENABLE ***********************/
+#define RNG_MANUAL_DISABLE (0x0ul) // RNG disble
+#define RNG_MANUAL_ENABLE (0x1ul) // RNG enable
+/*********************** Bit definition for RNG_RN ***********************/
+//ToDo
+
+/*********************** Bit definition for RNG_POLY ***********************/
+//ToDo
+
+
+
+typedef enum
+{
+ PAD_PA = 0,
+ PAD_PB,
+ PAD_PC,
+ PAD_PD
+}PAD_Type;
+
+typedef enum
+{
+ PAD_AF0 = Px_AFSR_AF0,
+ PAD_AF1 = Px_AFSR_AF1,
+ PAD_AF2 = Px_AFSR_AF2,
+ PAD_AF3 = Px_AFSR_AF3
+}PAD_AF_TypeDef;
+
+
+#if !defined (USE_HAL_DRIVER)
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+
+
+#if defined (USE_HAL_DRIVER)
+// #include "system_W7500x.h"
+// #include "W7500x_conf.h"
+#endif
+
+#ifdef USE_FULL_ASSERT
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* W7500x_H */
+
+
+
+/************************ (C) COPYRIGHT Wiznet *****END OF FILE****/
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-#include "W7500x.h"
-
-void ADC_PowerDownEnable (FunctionalState NewState)
-{
- if (NewState != DISABLE) ADC->ADC_CTR = ADC_CTR_PWD_PD;
- else ADC->ADC_CTR = ADC_CTR_PWD_NRMOP;
-}
-
-void ADC_ChannelSelect (ADC_CH num)
-{
- assert_param(IS_ADC_CH_NUM(num));
- ADC->ADC_CHSEL = num;
-}
-
-void ADC_Start (void)
-{
- ADC->ADC_START = ADC_START_START;
-}
-
-uint16_t ADC_ReadData (void)
-{
- return ((uint16_t)ADC->ADC_DATA);
-}
-
-void ADC_InterruptMask (FunctionalState NewState)
-{
- if (NewState != DISABLE) ADC->ADC_INT = ADC_INT_MASK_ENA;
- else ADC->ADC_INT = ADC_INT_MASK_DIS;
-}
-
-uint8_t ADC_IsInterrupt (void)
-{
- return (((uint8_t)ADC->ADC_INT && 0x01ul));
-}
-
-void ADC_InterruptClear (void)
-{
- ADC->ADC_INT = ADC_INTCLEAR;
-}
-
-void ADC_Init (void)
-{
- // ADC_CLK on
- ADC_PowerDownEnable(DISABLE);
- //ADC_ChannelSelect(num);
-}
-
-void ADC_DeInit (void)
-{
- // ADC_CLK off
- ADC_PowerDownEnable(ENABLE);
- ADC_InterruptMask(DISABLE);
-}
-
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_adc.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/**
- ******************************************************************************
- * @file
- * @author
- * @version
- * @date
- * @brief This file contains all the functions prototypes for the ADC
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __W7500X_ADC_H
-#define __W7500X_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "W7500x.h"
-
-typedef enum { ADC_CH0 = 0,
- ADC_CH1 = 1,
- ADC_CH2 = 2,
- ADC_CH3 = 3,
- ADC_CH4 = 4,
- ADC_CH5 = 5,
- ADC_CH6 = 6,
- ADC_CH7 = 7,
- ADC_CH15 = 15} ADC_CH;
-
-#define IS_ADC_CH_NUM(NUM) (((NUM) == ADC_CH0) || \
- ((NUM) == ADC_CH1) || \
- ((NUM) == ADC_CH2) || \
- ((NUM) == ADC_CH3) || \
- ((NUM) == ADC_CH4) || \
- ((NUM) == ADC_CH5) || \
- ((NUM) == ADC_CH6) || \
- ((NUM) == ADC_CH7) || \
- ((NUM) == ADC_CH15))
-
-void ADC_Init(void);
-void ADC_DeInit(void);
-void ADC_PowerDownEnable (FunctionalState NewState);
-void ADC_ChannelSelect (ADC_CH num);
-void ADC_Start (void);
-uint16_t ADC_ReadData (void);
-void ADC_InterruptMask (FunctionalState NewState);
-uint8_t ADC_IsInterrupt (void);
-void ADC_InterruptClear (void);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif //__W7500X_ADC_H
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_conf.h Fri Sep 04 08:45:09 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,16 +0,0 @@ -#include "W7500x_gpio.h" -#include "W7500x_exti.h" -#include "W7500x_pwm.h" -#include "W7500x_uart.h" -#include "W7500x_i2c.h" -#include "W7500x_adc.h" -#include "W7500x_dualtimer.h" -#include "system_W7500x.h" - - -#ifdef USE_FULL_ASSERT - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__)) -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ -
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,276 +0,0 @@
-#include "W7500x_crg.h"
-
-void CRG_DeInit(void)
-{
-//To Do
-}
-
-void CRG_OSC_PowerDownEnable(FunctionalState NewState)
-{
- if(NewState != DISABLE) CRG->OSC_PDR = CRG_OSC_PDR_PD;
- else CRG->OSC_PDR = CRG_OSC_PDR_NRMLOP;
-}
-
-void CRG_PLL_PowerDownEnable(FunctionalState NewState)
-{
- if(NewState != DISABLE) CRG->PLL_PDR = CRG_PLL_PDR_PD;
- else CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP;
-}
-
-void CRG_PLL_OutputEnable(FunctionalState NewState)
-{
- if(NewState != DISABLE) CRG->PLL_OER = CRG_PLL_OER_EN;
- else CRG->PLL_OER = CRG_PLL_OER_DIS;
-}
-
-void CRG_PLL_BypassEnable(FunctionalState NewState)
-{
- if(NewState != DISABLE) CRG->PLL_BPR = CRG_PLL_BPR_EN;
- else CRG->PLL_BPR = CRG_PLL_BPR_DIS;
-}
-
-void CRG_PLL_InputFrequencySelect(CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_PLL_SRC(src));
-
- if( src == CRG_RCLK ) CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
- else CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
-}
-
-void CRG_FCLK_SourceSelect(CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_FCLK_SRC(src));
-
- if ( src == CRG_RCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_RCLK;
- else if ( src == CRG_OCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_OCLK;
- else CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK;
-}
-
-void CRG_FCLK_SetPrescale(CRG_PREDIV prediv)
-{
- assert_param(IS_CRG_FCLK_PREDIV(prediv));
-
- if ( prediv == CRG_PREDIV1 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1;
- else if ( prediv == CRG_PREDIV2 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV2;
- else if ( prediv == CRG_PREDIV4 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV4;
- else CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV8;
-}
-
-void CRG_SSPCLK_SourceSelect(CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_SSPCLK_SRC(src));
-
- if ( src == CRG_CLK_DIS ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS;
- else if ( src == CRG_MCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK;
- else if ( src == CRG_RCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_RCLK;
- else CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_OCLK;
-}
-
-void CRG_SSPCLK_SetPrescale(CRG_PREDIV prediv)
-{
- assert_param(IS_CRG_SSPCLK_PREDIV(prediv));
-
- if ( prediv == CRG_PREDIV1 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1;
- else if ( prediv == CRG_PREDIV2 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV2;
- else if ( prediv == CRG_PREDIV4 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV4;
- else CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV8;
-}
-
-void CRG_ADCCLK_SourceSelect(CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_ADCCLK_SRC(src));
-
- if ( src == CRG_CLK_DIS ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS;
- else if ( src == CRG_MCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_MCLK;
- else if ( src == CRG_RCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_RCLK;
- else CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_OCLK;
-}
-
-void CRG_ADCCLK_SetPrescale(CRG_PREDIV prediv)
-{
- assert_param(IS_CRG_ADCCLK_PREDIV(prediv));
-
- if ( prediv == CRG_PREDIV1 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1;
- else if ( prediv == CRG_PREDIV2 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV2;
- else if ( prediv == CRG_PREDIV4 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV4;
- else CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV8;
-}
-
-void CRG_TIMERCLK_SourceSelect(CRG_TIMER num, CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_TIMERCLK_NUM(num));
- assert_param(IS_CRG_TIMERCLK_SRC(src));
-
- if ( src == CRG_CLK_DIS ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_DIS);
- else if ( src == CRG_MCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_MCLK);
- else if ( src == CRG_RCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_RCLK);
- else CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_OCLK);
-}
-
-void CRG_TIMERCLK_SetPrescale(CRG_TIMER num, CRG_PREDIV prediv)
-{
- assert_param(IS_CRG_TIMERCLK_NUM(num));
- assert_param(IS_CRG_TIMERCLK_PREDIV(prediv));
-
- if ( prediv == CRG_PREDIV1 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV1);
- else if ( prediv == CRG_PREDIV2 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV2);
- else if ( prediv == CRG_PREDIV4 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV4);
- else if ( prediv == CRG_PREDIV8 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV8);
- else if ( prediv == CRG_PREDIV16 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV16);
- else if ( prediv == CRG_PREDIV32 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV32);
- else if ( prediv == CRG_PREDIV64 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV64);
- else CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV128);
-}
-
-void CRG_PWMCLK_SourceSelect(CRG_PWM num, CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_PWMCLK_NUM(num));
- assert_param(IS_CRG_PWMCLK_SRC(src));
-
- if ( src == CRG_CLK_DIS ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_DIS);
- else if ( src == CRG_MCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_MCLK);
- else if ( src == CRG_RCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_RCLK);
- else CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_OCLK);
-}
-
-void CRG_PWMCLK_SetPrescale(CRG_PWM num, CRG_PREDIV prediv)
-{
- assert_param(IS_CRG_PWMCLK_NUM(num));
- assert_param(IS_CRG_PWMCLK_PREDIV(prediv));
-
- if ( prediv == CRG_PREDIV1 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV1);
- else if ( prediv == CRG_PREDIV2 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV2);
- else if ( prediv == CRG_PREDIV4 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV4);
- else if ( prediv == CRG_PREDIV8 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV8);
- else if ( prediv == CRG_PREDIV16 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV16);
- else if ( prediv == CRG_PREDIV32 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV32);
- else if ( prediv == CRG_PREDIV64 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV64);
- else CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV128);
-}
-
-void CRG_RTC_HS_SourceSelect(CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_RTC_HS_SRC(src));
-
- if ( src == CRG_CLK_DIS ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_DIS;
- else if ( src == CRG_MCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_MCLK;
- else if ( src == CRG_RCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_RCLK;
- else CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_OCLK;
-
- if ( src != CRG_CLK_DIS ) CRG_RTC_SourceSelect(CRG_CLK_HIGH);
-}
-
-void CRG_RTC_HS_SetPrescale(CRG_PREDIV prediv)
-{
- assert_param(IS_CRG_RTC_HS_PREDIV(prediv));
-
- if ( prediv == CRG_PREDIV1 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV1;
- else if ( prediv == CRG_PREDIV2 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV2;
- else if ( prediv == CRG_PREDIV4 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV4;
- else if ( prediv == CRG_PREDIV8 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV8;
- else if ( prediv == CRG_PREDIV16 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV16;
- else if ( prediv == CRG_PREDIV32 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV32;
- else if ( prediv == CRG_PREDIV64 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV64;
- else CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV128;
-}
-
-void CRG_RTC_SourceSelect(CRG_CLK_LOW_SOURCE src)
-{
- assert_param(IS_CRG_RTC_LOW_SRC(src));
-
- if (src == CRG_CLK_LOW)
- {
- CRG_RTC_HS_SourceSelect(CRG_CLK_DIS);
- CRG->RTC_SSR = CRG_RTC_SSR_LW;
- }
- else
- {
- CRG->RTC_SSR = CRG_RTC_SSR_HS;
- }
-}
-
-void CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_WDOGCLK_HS_SRC(src));
-
- if ( src == CRG_CLK_DIS ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_DIS;
- else if ( src == CRG_MCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_MCLK;
- else if ( src == CRG_RCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_RCLK;
- else CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_OCLK;
-
- if ( src != CRG_CLK_DIS ) CRG_WDOGCLK_SourceSelect(CRG_CLK_HIGH);
-}
-
-void CRG_WDOGCLK_HS_SetPrescale(CRG_PREDIV prediv)
-{
- assert_param(IS_CRG_WDOGCLK_HS_PREDIV(prediv));
-
- if ( prediv == CRG_PREDIV1 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV1;
- else if ( prediv == CRG_PREDIV2 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV2;
- else if ( prediv == CRG_PREDIV4 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV4;
- else if ( prediv == CRG_PREDIV8 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV8;
- else if ( prediv == CRG_PREDIV16 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV16;
- else if ( prediv == CRG_PREDIV32 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV32;
- else if ( prediv == CRG_PREDIV64 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV64;
- else CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV128;
-}
-
-void CRG_WDOGCLK_SourceSelect(CRG_CLK_LOW_SOURCE src)
-{
- assert_param(IS_CRG_WDOGCLK_LOW_SRC(src));
-
- if (src == CRG_CLK_LOW)
- {
- CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_DIS);
- CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_LW;
- }
- else
- {
- CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_HS;
- }
-}
-
-void CRG_UARTCLK_SourceSelect(CRG_CLK_SOURCE src)
-{
- assert_param(IS_CRG_UARTCLK_SRC(src));
-
- if ( src == CRG_CLK_DIS ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_DIS;
- else if ( src == CRG_MCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK;
- else if ( src == CRG_RCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK;
- else CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK;
-}
-
-void CRG_UARTCLK_SetPrescale(CRG_PREDIV prediv)
-{
- assert_param(IS_CRG_UARTCLK_PREDIV(prediv));
-
- if ( prediv == CRG_PREDIV1 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1;
- else if ( prediv == CRG_PREDIV2 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV2;
- else if ( prediv == CRG_PREDIV4 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV4;
- else CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV8;
-}
-
-void CRG_MII_Enable(FunctionalState rx_clk, FunctionalState tx_clk)
-{
- assert_param(IS_FUNCTIONAL_STATE(rx_clk));
- assert_param(IS_FUNCTIONAL_STATE(tx_clk));
-
- if ( rx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_RXCLK;
- else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_RXCLK);
-
- if ( tx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_TXCLK;
- else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_TXCLK);
-}
-
-void CRG_SetMonitoringClock(uint32_t value)
-{
- assert_param(IS_CRG_MONCLK_SSR(value));
-
- CRG->MONCLK_SSR = value;
-}
-
-uint32_t CRG_GetMonitoringClock(void)
-{
- return (uint8_t)CRG->MONCLK_SSR;
-}
-
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_crg.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,145 +0,0 @@
-/**
- ******************************************************************************
- * @file
- * @author
- * @version
- * @date
- * @brief This file contains all the functions prototypes for the Clock Reset Generator
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __W7500X_CRG_H
-#define __W7500X_CRG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "W7500x.h"
-
-// It will be in W7500x_crg.h
-typedef enum { CRG_CLK_DIS = 0, CRG_MCLK, CRG_RCLK, CRG_OCLK } CRG_CLK_SOURCE;
-typedef enum { CRG_CLK_HIGH = 0, CRG_CLK_LOW } CRG_CLK_LOW_SOURCE;
-typedef enum { CRG_PREDIV1 = 0, CRG_PREDIV2, CRG_PREDIV4, CRG_PREDIV8, CRG_PREDIV16, \
- CRG_PREDIV32, CRG_PREDIV64, CRG_PREDIV128 } CRG_PREDIV;
-typedef enum { CRG_TIMER0 = 0, CRG_TIMER1 } CRG_TIMER;
-typedef enum { CRG_PWM0 = 0, CRG_PWM1, CRG_PWM2, CRG_PWM3, CRG_PWM4, CRG_PWM5, CRG_PWM6, CRG_PWM7 } CRG_PWM;
-
-
-
-#define IS_CRG_PLL_SRC(SRC) (((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
-#define IS_CRG_FCLK_SRC(SRC) (((SRC) == CRG_MCLK) || ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
-
-#define CRG_CLK_SRC_DEFAULT(SRC) (((SRC) == CRG_CLK_DIS) || ((SRC) == CRG_MCLK) || \
- ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
-#define CRG_CLK_SRC_LOW(SRC) (((SRC) == CRG_CLK_HIGH) || ((SRC) == CRG_CLK_LOW))
-
-#define CRG_CLK_PREDIV_DEFAULT(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
- ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8))
-#define CRG_CLK_PREDIV_ADVANCE(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
- ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8) || \
- ((DIV) == CRG_PREDIV16) || ((DIV) == CRG_PREDIV32) || \
- ((DIV) == CRG_PREDIV64) || ((DIV) == CRG_PREDIV128))
-
-
-#define IS_CRG_FCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
-
-#define IS_CRG_SSPCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
-#define IS_CRG_SSPCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
-
-#define IS_CRG_ADCCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
-#define IS_CRG_ADCCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
-
-
-
-
-
-#define IS_CRG_TIMERCLK_NUM(NUM) (((NUM) == CRG_TIMER0) || ((NUM) == CRG_TIMER1))
-#define IS_CRG_TIMERCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
-#define IS_CRG_TIMERCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
-
-#define CRG_SET_TIMERCLK_SSR(NUM,VALUE) \
- (*((volatile uint32_t *)(CRG->TIMER0CLK_SSR) + (0x10ul * NUM)) = VALUE)
-#define CRG_SET_TIMERCLK_PREDIV(NUM,VALUE) \
- (*((volatile uint32_t *)(CRG->TIMER0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
-//#define CRG_SET_TIMERCLK_SSR(num,value) CRG->TIMER##num##CLK_SSR = value
-//#define CRG_SET_TIMERCLK_PREDIV(num,value) CRG->TIMER##num##CLK_PVSR = value
-
-
-#define IS_CRG_PWMCLK_NUM(NUM) (((NUM) == CRG_PWM0) || ((NUM) == CRG_PWM1) || \
- ((NUM) == CRG_PWM2) || ((NUM) == CRG_PWM3) || \
- ((NUM) == CRG_PWM4) || ((NUM) == CRG_PWM5) || \
- ((NUM) == CRG_PWM6) || ((NUM) == CRG_PWM7) )
-#define IS_CRG_PWMCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
-#define IS_CRG_PWMCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
-
-#define CRG_SET_PWMCLK_SSR(NUM,VALUE) \
- (*((volatile uint32_t *)(CRG->PWM0CLK_SSR) + (0x10ul * NUM)) = VALUE)
-#define CRG_SET_PWMCLK_PREDIV(NUM,VALUE) \
- (*((volatile uint32_t *)(CRG->PWM0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
-//#define CRG_SET_PWMCLK_SSR(num,value) CRG->PWM##num##CLK_SSR = value
-//#define CRG_SET_PWMCLK_PREDIV(num,value) CRG->PWM##num##CLK_PVSR = value
-
-#define IS_CRG_RTC_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
-#define IS_CRG_RTC_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
-#define IS_CRG_RTC_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
-
-#define IS_CRG_WDOGCLK_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
-#define IS_CRG_WDOGCLK_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
-#define IS_CRG_WDOGCLK_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
-
-#define IS_CRG_UARTCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
-#define IS_CRG_UARTCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
-
-#define IS_CRG_MONCLK_SSR(value) (((value) >= 0x00ul) || ((value) <= 0x13ul))
-
-void CRG_DeInit(void);
-void CRG_OSC_PowerDownEnable (FunctionalState NewState);
-void CRG_PLL_PowerDownEnable (FunctionalState NewState);
-void CRG_PLL_OutputEnable (FunctionalState NewState);
-void CRG_PLL_BypassEnable (FunctionalState NewState);
-void CRG_PLL_InputFrequencySelect (CRG_CLK_SOURCE src);
-
-void CRG_FCLK_SourceSelect (CRG_CLK_SOURCE src);
-void CRG_FCLK_SetPrescale (CRG_PREDIV prediv);
-
-void CRG_SSPCLK_SourceSelect (CRG_CLK_SOURCE src);
-void CRG_SSPCLK_SetPrescale (CRG_PREDIV prediv);
-
-void CRG_ADCCLK_SourceSelect (CRG_CLK_SOURCE src);
-void CRG_ADCCLK_SetPrescale (CRG_PREDIV prediv);
-
-void CRG_TIMERCLK_SourceSelect (CRG_TIMER num, CRG_CLK_SOURCE src);
-void CRG_TIMERCLK_SetPrescale (CRG_TIMER num, CRG_PREDIV prediv);
-
-void CRG_PWMCLK_SourceSelect (CRG_PWM num, CRG_CLK_SOURCE src);
-void CRG_PWMCLK_SetPrescale (CRG_PWM num, CRG_PREDIV prediv);
-
-void CRG_RTC_HS_SourceSelect (CRG_CLK_SOURCE src);
-void CRG_RTC_HS_SetPrescale (CRG_PREDIV prediv);
-void CRG_RTC_SourceSelect (CRG_CLK_LOW_SOURCE src);
-
-void CRG_WDOGCLK_HS_SourceSelect (CRG_CLK_SOURCE src);
-void CRG_WDOGCLK_HS_SetPrescale (CRG_PREDIV prediv);
-void CRG_WDOGCLK_SourceSelect (CRG_CLK_LOW_SOURCE src);
-
-void CRG_UARTCLK_SourceSelect (CRG_CLK_SOURCE src);
-void CRG_UARTCLK_SetPrescale (CRG_PREDIV prediv);
-
-void CRG_MII_Enable (FunctionalState rx_clk, FunctionalState tx_clk);
-
-void CRG_SetMonitoringClock (uint32_t value);
-uint32_t CRG_GetMonitoringClock (void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_dualtimer.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,205 +0,0 @@
-/**
- ******************************************************************************
- * @file W7500x_stdPeriph_Driver/src/W7500x_dualtimer.c
- * @author IOP Team
- * @version v1.0.0
- * @date 01-May-2015
- * @brief This file contains all the functions prototypes for the dualtimer
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Includes -------------------------------------------*/
-#include "W7500x.h"
-
-void DUALTIMER_ClockEnable(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- if(DUALTIMERn == DUALTIMER0_0)
- TIMCLKEN0_0 = DUALTIMER_Clock_Enable;
- else if(DUALTIMERn == DUALTIMER0_1)
- TIMCLKEN0_1 = DUALTIMER_Clock_Enable;
- else if(DUALTIMERn == DUALTIMER1_0)
- TIMCLKEN1_0 = DUALTIMER_Clock_Enable;
- else if(DUALTIMERn == DUALTIMER1_1)
- TIMCLKEN1_1 = DUALTIMER_Clock_Enable;
-}
-
-void DUALTIMER_ClockDisable(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- if(DUALTIMERn == DUALTIMER0_0)
- TIMCLKEN0_0 = DUALTIMER_Clock_Disable;
- else if(DUALTIMERn == DUALTIMER0_1)
- TIMCLKEN0_1 = DUALTIMER_Clock_Disable;
- else if(DUALTIMERn == DUALTIMER1_0)
- TIMCLKEN1_0 = DUALTIMER_Clock_Disable;
- else if(DUALTIMERn == DUALTIMER1_1)
- TIMCLKEN1_1 = DUALTIMER_Clock_Disable;
-}
-
-void DUALTIMER_DeInit(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- DUALTIMER_Stop(DUALTIMERn);
-
- DUALTIMERn->TimerLoad = 0x0;
- DUALTIMERn->TimerControl = 0x20;
- DUALTIMERn->TimerBGLoad = 0x0;
-}
-
-void DUALTIMER_Init(DUALTIMER_TypeDef* DUALTIMERn, DUALTIMER_InitTypDef* DUALTIMER_InitStruct)
-{
- uint32_t tmp = 0;
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
- assert_param(IS_DUALTIMER_TimerMode(DUALTIMER_InitStruct->TimerControl_Mode));
- assert_param(IS_DUALTIMER_TimerPre(DUALTIMER_InitStruct->TimerControl_Pre));
- assert_param(IS_DUALTIMER_TimerSize(DUALTIMER_InitStruct->TimerControl_Size));
- assert_param(IS_DUALTIMER_OneShot(DUALTIMER_InitStruct->TimerControl_OneShot));
-
- DUALTIMER_Stop(DUALTIMERn);
-
- DUALTIMERn->TimerLoad = DUALTIMER_InitStruct->TimerLoad;
-
- tmp = DUALTIMERn->TimerControl;
- tmp |= (DUALTIMER_InitStruct->TimerControl_Mode << DUALTIMER_TimerControl_TimerMode_Pos);
- tmp |= (DUALTIMER_InitStruct->TimerControl_Pre << DUALTIMER_TimerControl_Pre_Pos);
- tmp |= (DUALTIMER_InitStruct->TimerControl_Size << DUALTIMER_TimerControl_Size_Pos);
- tmp |= (DUALTIMER_InitStruct->TimerControl_OneShot << DUALTIMER_TimerControl_OneShot_Pos);
- //Reset values not used
- tmp &= 0xEF;
-
- DUALTIMERn->TimerControl = tmp;
-}
-
-void DUALTIMER_IntConfig(DUALTIMER_TypeDef* DUALTIMERn, FunctionalState state)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- if(state == ENABLE)
- DUALTIMERn->TimerControl |= (DUALTIMER_TimerControl_IntEnable << DUALTIMER_TimerControl_IntEnable_Pos);
- else
- DUALTIMERn->TimerControl &= ~(DUALTIMER_TimerControl_IntEnable << DUALTIMER_TimerControl_IntEnable_Pos);
-}
-
-void DUALTIMER_IntClear(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- DUALTIMERn->TimerIntClr = DUALTIMER_Int_Clear;
-}
-
-ITStatus DUALTIMER_GetIntStatus(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- return (ITStatus)DUALTIMERn->TimerMIS;
-}
-
-FlagStatus DUALTIMER_GetIntEnableStatus(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- return (FlagStatus)((DUALTIMERn->TimerControl >> DUALTIMER_TimerControl_IntEnable_Pos) & 0x1);
-}
-
-void DUALTIMER_Start(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- DUALTIMERn->TimerControl |= (DUALTIMER_TimerControl_TimerEnable << DUALTIMER_TimerControl_TimerEnable_Pos);
-}
-
-void DUALTIMER_Stop(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- DUALTIMERn->TimerControl &= ~(DUALTIMER_TimerControl_TimerEnable << DUALTIMER_TimerControl_TimerEnable_Pos);
-}
-
-uint32_t DUALTIMER_GetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- return DUALTIMERn->TimerLoad;
-}
-
-void DUALTIMER_SetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerLoad)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- DUALTIMERn->TimerLoad = TimerLoad;
-}
-
-uint32_t DUALTIMER_GetTimerValue(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- return DUALTIMERn->TimerValue;
-}
-
-uint32_t DUALTIMER_GetTimerControl(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- return DUALTIMERn->TimerControl;
-}
-
-void DUALTIMER_SetTimerControl(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerControl)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- DUALTIMERn->TimerControl = TimerControl;
-}
-
-uint32_t DUALTIMER_GetTimerRIS(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- return DUALTIMERn->TimerRIS;
-}
-
-uint32_t DUALTIMER_GetTimerMIS(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- return DUALTIMERn->TimerMIS;
-}
-
-uint32_t DUALTIMER_GetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- return DUALTIMERn->TimerBGLoad;
-}
-
-void DUALTIMER_SetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerBGLoad)
-{
- /* Check the parameters */
- assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
-
- DUALTIMERn->TimerBGLoad = TimerBGLoad;
-}
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_dualtimer.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,96 +0,0 @@
-/**
- ******************************************************************************
- * @file W7500x_stdPeriph_Driver/inc/W7500x_dualtimer.h
- * @author IOP Team
- * @version V1.0.0
- * @date 01-May-2015
- * @brief This file contains all the functions prototypes for the dualtimer
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __W7500X_DUALTIMER_H
-#define __W7500X_DUALTIMER_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "W7500x.h"
-
-/**********************************************************************************************/
-/**********************************************************************************************/
-// This structure and define must be in W7500x.h
-/**********************************************************************************************/
-/**********************************************************************************************/
-
-typedef struct
-{
- uint32_t TimerLoad;
- uint32_t TimerControl_Mode;
- uint32_t TimerControl_Pre;
- uint32_t TimerControl_Size;
- uint32_t TimerControl_OneShot;
-}DUALTIMER_InitTypDef;
-
-
-#define IS_DUALTIMER_TimerMode(MODE) (MODE <= 1)
-#define IS_DUALTIMER_TimerPre(PREE) (PRE <= 2)
-#define IS_DUALTIMER_TimerSize(SIZE) (SIZE <= 1)
-#define IS_DUALTIMER_OneShot(ONESHOT) (ONESHOT <= 1)
-
-
-
-
-
-
-#define DUALTIMER_Int_Clear 0x1ul
-
-#define DUALTIMER_Clock_Enable 0x1ul
-#define DUALTIMER_Clock_Disable ~DUALTIMER_Clock_Enable
-
-
-#define IS_DUALTIMER_ALL_CH(CH) ((CH == DUALTIMER0_0) || \
- (CH == DUALTIMER0_1) || \
- (CH == DUALTIMER1_0) || \
- (CH == DUALTIMER1_1))
-
-
-
-void DUALTIMER_ClockEnable(DUALTIMER_TypeDef* DUALTIMERn);
-void DUALTIMER_ClockDisable(DUALTIMER_TypeDef* DUALTIMERn);
-void DUALTIMER_DeInit(DUALTIMER_TypeDef* DUALTIMERn);
-void DUALTIMER_Init(DUALTIMER_TypeDef* DUALTIMERn, DUALTIMER_InitTypDef* DUALTIMER_InitStruct);
-void DUALTIMER_IntConfig(DUALTIMER_TypeDef* DUALTIMERn, FunctionalState state);
-void DUALTIMER_IntClear(DUALTIMER_TypeDef* DUALTIMERn);
-ITStatus DUALTIMER_GetIntStatus(DUALTIMER_TypeDef* DUALTIMERn);
-FlagStatus DUALTIMER_GetIntEnableStatus(DUALTIMER_TypeDef* DUALTIMERn);
-void DUALTIMER_Start(DUALTIMER_TypeDef* DUALTIMERn);
-void DUALTIMER_Stop(DUALTIMER_TypeDef* DUALTIMERn);
-uint32_t DUALTIMER_GetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn);
-void DUALTIMER_SetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerLoad);
-uint32_t DUALTIMER_GetTimerValue(DUALTIMER_TypeDef* DUALTIMERn);
-uint32_t DUALTIMER_GetTimerControl(DUALTIMER_TypeDef* DUALTIMERn);
-void DUALTIMER_SetTimerControl(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerControl);
-uint32_t DUALTIMER_GetTimerRIS(DUALTIMER_TypeDef* DUALTIMERn);
-uint32_t DUALTIMER_GetTimerMIS(DUALTIMER_TypeDef* DUALTIMERn);
-uint32_t DUALTIMER_GetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn);
-void DUALTIMER_SetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerBGLoad);
-
-
-
-//======================= Interrupt handler ==============================
-//void DUALTIMER0_Handler();
-//void DUALTIMER1_Handler();
-
-
-#ifdef __cplusplus
- }
-#endif
-
-
-#endif //__W7500X_DUALTIMER_H
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,157 +0,0 @@
-#include "W7500x.h"
-
-
-
-/**
- * @brief Deinitializes the EXTI peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void EXTI_DeInit(void)
-{
- uint32_t i, loop =16;
- for(i=0; i<loop; i++)
- {
- EXTI_PA->Port[i] = 0x00;
- EXTI_PB->Port[i] = 0x00;
- EXTI_PC->Port[i] = 0x00;
- }
- for(i=0; i<5; i++)
- {
- EXTI_PD->Port[i] = 0x00;
- }
-}
-
-/**
- * @brief Initializes the EXTI peripheral according to the specified
- * parameters in the EXTI_InitStruct.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
- * that contains the configuration information for the EXTI peripheral.
- * @retval None
- */
-void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
- P_Port_Def *px_exti;
-
- assert_param(IS_PAD_TYPE(Px));
-
- if (Px == PAD_PA) px_exti = EXTI_PA;
- else if (Px == PAD_PB) px_exti = EXTI_PB;
- else if (Px == PAD_PC) px_exti = EXTI_PC;
- else
- {
- px_exti = (P_Port_Def*)EXTI_PD;
- loop = 5;
- }
-
- for(pinpos = 0x00; pinpos < loop; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
-
- currentpin = (EXTI_InitStruct->EXTI_Line) & pos;
- if(currentpin == pos)
- {
- px_exti->Port[pinpos] |= EXTI_Px_INTEN_ENABLE;
-
- if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising)
- px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE;
- else
- px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE;
- }
- }
-
-}
-
-void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity )
-{
- uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
- P_Port_Def *px_exti;
-
- assert_param(IS_PAD_TYPE(Px));
-
- if (Px == PAD_PA) px_exti = EXTI_PA;
- else if (Px == PAD_PB) px_exti = EXTI_PB;
- else if (Px == PAD_PC) px_exti = EXTI_PC;
- else
- {
- px_exti = (P_Port_Def*)EXTI_PD;
- loop = 5;
- }
-
- for(pinpos = 0x00; pinpos < loop; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
-
- currentpin = GPIO_Pin & pos;
- if(currentpin == pos)
- {
- if(Polarity == EXTI_Trigger_Rising)
- px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE;
- else
- px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE;
- }
- }
-
-}
-
-/**
- * @brief Fills each EXTI_InitStruct member with its reset value.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- EXTI_InitStruct->EXTI_Line = 0xFF;
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
-}
-
-uint16_t EXTI_Px_GetEXTEN(PAD_Type Px)
-{
- uint32_t i, loop = 16;
- uint16_t ret=0;
- P_Port_Def *px_exti;
-
- assert_param(IS_PAD_TYPE(Px));
-
- if (Px == PAD_PA) px_exti = EXTI_PA;
- else if (Px == PAD_PB) px_exti = EXTI_PB;
- else if (Px == PAD_PC) px_exti = EXTI_PC;
- else
- {
- px_exti = (P_Port_Def*)EXTI_PD;
- loop = 5;
- }
-
- for(i = 0x00; i < loop; i++)
- {
- ret |= (((px_exti->Port[i]&0x2)>>1)<<i);
- }
- return ret;
-}
-
-uint16_t EXTI_Px_GetEXTINTPOL(PAD_Type Px)
-{
- uint32_t i, loop = 16;
- uint16_t ret=0;
- P_Port_Def *px_exti;
-
- assert_param(IS_PAD_TYPE(Px));
-
- if (Px == PAD_PA) px_exti = EXTI_PA;
- else if (Px == PAD_PB) px_exti = EXTI_PB;
- else if (Px == PAD_PC) px_exti = EXTI_PC;
- else
- {
- px_exti = (P_Port_Def*)EXTI_PD;
- loop = 5;
- }
-
- for(i = 0x00; i < loop; i++)
- {
- ret |= ((px_exti->Port[i]&0x1)<<i);
- }
- return ret;
-}
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_exti.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/**
- ******************************************************************************
- * @file
- * @author
- * @version
- * @date
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __W7500X_EXTI_H
-#define __W7500X_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
- /* Includes ------------------------------------------------------------------*/
-#include "W7500x.h"
-
-
- /**
- * @brief EXTI mode enumeration
- */
-
-typedef enum
-{
- EXTI_Mode_Disable = 0x00,
- EXTI_Mode_Interrupt = 0x02
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Rising) || \
- ((MODE) == EXTI_Mode_Interrupt))
-
-/**
- * @brief EXTI Trigger enumeration
- */
-
-typedef enum
-{
- EXTI_Trigger_Rising = 0x00,
- EXTI_Trigger_Falling = 0x01
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
- ((TRIGGER) == EXTI_Trigger_Falling))
-
-/**
- * @brief EXTI Init Structure definition
- */
-
-typedef struct
-{
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
- This parameter can be any combination of @ref EXTI_Lines */
-
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.This parameter can be a value of @ref EXTIMode_TypeDef */
-
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
-}EXTI_InitTypeDef;
-
-/**
- * @}
- */
-
-void EXTI_DeInit(void);
-void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity );
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-uint32_t EXTI_GetEXTIConfig(PAD_Type Px, uint16_t GPIO_Pin);
-uint16_t EXTI_Px_GetEXTEN(PAD_Type Px);
-uint16_t EXTI_Px_GetEXTINTPOL(PAD_Type Px);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif //__W7500X_EXTI_H
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,298 +0,0 @@
-#include "W7500x.h"
-
-
-
-void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- uint32_t i, loop =16;
- P_Port_Def *px_pcr;
- P_Port_Def *px_afsr;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- /* DeInit GPIOx Registers */
- GPIOx->DATA = 0x0000;
- GPIOx->DATAOUT = 0x0000;
- //GPIOx->OUTENSET = 0x0000;
- GPIOx->OUTENCLR = 0xFFFF;
- //GPIOx->INTENSET = 0x0000;
- GPIOx->INTENCLR = 0xFFFF;
- //GPIOx->INTTYPESET = 0x0000;
- GPIOx->INTTYPECLR = 0xFFFF;
- //GPIOx->INTPOLSET = 0x0000;
- GPIOx->INTPOLCLR = 0xFFFF;
-
-
- /* DeInit GPIOx
- * Pad Control Register
- * Pad Extern interrupt Enable Register
- * Pad Alternate Function Select Register
- */
- if (GPIOx == GPIOA)
- {
- px_pcr = PA_PCR;
- px_afsr = PA_AFSR;
- }
- else if (GPIOx == GPIOB)
- {
- px_pcr = PB_PCR;
- px_afsr = PB_AFSR;
- }
- else if (GPIOx == GPIOC)
- {
- px_pcr = PC_PCR;
- px_afsr = PC_AFSR;
- }
- else // if (GPIOx == GPIOD)
- {
- px_pcr = (P_Port_Def*)PD_PCR;
- px_afsr = (P_Port_Def*)PD_AFSR;
- loop = 5;
- }
-
- for(i=0; i<loop; i++)
- {
- px_pcr->Port[i] = 0x60;
- px_afsr->Port[i] = PAD_AF0;
-
- }
-}
-
-void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
- P_Port_Def *px_pcr;
-
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
-// assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- if (GPIOx == GPIOA) px_pcr = PA_PCR;
- else if (GPIOx == GPIOB) px_pcr = PB_PCR;
- else if (GPIOx == GPIOC) px_pcr = PC_PCR;
- else
- {
- px_pcr = (P_Port_Def*)PD_PCR;
- loop = 5;
- }
-
- for(pinpos = 0x00; pinpos < loop; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
-
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if(currentpin == pos)
- {
- if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT)
- {
- GPIOx->OUTENSET |= pos;
- }
- else // GPIO_Mode_In
- {
- GPIOx->OUTENCLR = pos;
- }
-
- // Configure pull-up pull-down bits
- if(GPIO_InitStruct->GPIO_Pad & Px_PCR_PUPD_UP)
- {
- px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN);
- px_pcr->Port[pinpos] |= Px_PCR_PUPD_UP;
- }
- else
- {
- px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN);
- px_pcr->Port[pinpos] |= Px_PCR_PUPD_DOWN;
- }
-
- // Configure Driving stregnth selections bit
- if(GPIO_InitStruct->GPIO_Pad & Px_PCR_DS_HIGH)
- {
- px_pcr->Port[pinpos] |= Px_PCR_DS_HIGH;
- }
- else
- {
- px_pcr->Port[pinpos] &= ~(Px_PCR_DS_HIGH);
- }
-
- // Configure Open Drain selections bit
- if(GPIO_InitStruct->GPIO_Pad & Px_PCR_OD)
- {
- px_pcr->Port[pinpos] |= Px_PCR_OD;
- }
- else
- {
- px_pcr->Port[pinpos] &= ~(Px_PCR_OD);
- }
-
- // Configure Input buffer enable selection bit
- if(GPIO_InitStruct->GPIO_Pad & Px_PCR_IE)
- {
- px_pcr->Port[pinpos] |= Px_PCR_IE;
- }
- else
- {
- px_pcr->Port[pinpos] &= ~(Px_PCR_IE);
- }
-
- // Configure input type (CMOS input or Summit trigger input) select bit
- if(GPIO_InitStruct->GPIO_Pad & Px_PCR_CS_SUMMIT)
- {
- px_pcr->Port[pinpos] |= Px_PCR_CS_SUMMIT;
- }
- else
- {
- px_pcr->Port[pinpos] &= ~(Px_PCR_CS_SUMMIT);
- }
- }
- }
-}
-
-void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Pad = (GPIOPad_TypeDef)(GPIO_PuPd_UP);
-}
-
-
-uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if((GPIOx->DATA & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
-
- return bitstatus;
-}
-
-uint16_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- return ((uint16_t)GPIOx->DATA);
-}
-
-uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
-
-
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if((GPIOx->DATAOUT & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
-
- return bitstatus;
-}
-uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALLPERIPH(GPIOx));
- return ((uint16_t)GPIOx->DATAOUT);
-}
-
-void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = GPIO_Pin;
- (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = GPIO_Pin;
-}
-
-void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = ~(GPIO_Pin);
- (GPIOx->UB_MASKED[(uint8_t)(GPIO_Pin>>8)]) = ~(GPIO_Pin);
-}
-
-void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = BitVal;
- (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = BitVal;
-}
-
-void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->DATAOUT = PortVal;
-}
-
-void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF)
-{
- int i;
- uint16_t idx =0x1;
- assert_param(IS_PAD_Type(Px));
-
- for(i=0;i<16;i++)
- {
- if(GPIO_Pin & (idx<<i))
- {
- if(Px == PAD_PA)
- {
- assert_param(IS_PA_NUM(i));
- PA_AFSR->Port[i] &= ~(0x03ul);
- PA_AFSR->Port[i] |= P_AF;
- }
- else if(Px == PAD_PB)
- {
- assert_param(IS_PB_NUM(i));
- PB_AFSR->Port[i] &= ~(0x03ul);
- PB_AFSR->Port[i] |= P_AF;
- }
- else if(Px == PAD_PC)
- {
- assert_param(IS_PC_NUM(i));
- PC_AFSR->Port[i] &= ~(0x03ul);
- PC_AFSR->Port[i] |= P_AF;
- }
- else
- {
- assert_param(IS_PD_NUM(i));
- PD_AFSR->Port[i] &= ~(0x03ul);
- PD_AFSR->Port[i] |= P_AF;
- }
- }
- }
-}
-
-void GPIO_OutEnClr(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- GPIOx->OUTENCLR = GPIO_Pin;
-}
-
-void GPIO_OutEnSet(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- GPIOx->OUTENSET = GPIO_Pin;
-}
-
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_gpio.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,137 +0,0 @@
-/**
- ******************************************************************************
- * @file
- * @author
- * @version
- * @date
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __W7500X_HAL_GPIO_H
-#define __W7500X_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "W7500x.h"
-
-#define GPIO_Pin_0 (uint16_t)(0x01 << 0) // Pin 0 Selected
-#define GPIO_Pin_1 (uint16_t)(0x01 << 1) // Pin 1 Selected
-#define GPIO_Pin_2 (uint16_t)(0x01 << 2) // Pin 2 Selected
-#define GPIO_Pin_3 (uint16_t)(0x01 << 3) // Pin 3 Selected
-#define GPIO_Pin_4 (uint16_t)(0x01 << 4) // Pin 4 Selected
-#define GPIO_Pin_5 (uint16_t)(0x01 << 5) // Pin 5 Selected
-#define GPIO_Pin_6 (uint16_t)(0x01 << 6) // Pin 6 Selected
-#define GPIO_Pin_7 (uint16_t)(0x01 << 7) // Pin 7 Selected
-#define GPIO_Pin_8 (uint16_t)(0x01 << 8) // Pin 8 Selected
-#define GPIO_Pin_9 (uint16_t)(0x01 << 9) // Pin 9 Selected
-#define GPIO_Pin_10 (uint16_t)(0x01 << 10) // Pin 10 Selected
-#define GPIO_Pin_11 (uint16_t)(0x01 << 11) // Pin 11 Selected
-#define GPIO_Pin_12 (uint16_t)(0x01 << 12) // Pin 12 Selected
-#define GPIO_Pin_13 (uint16_t)(0x01 << 13) // Pin 13 Selected
-#define GPIO_Pin_14 (uint16_t)(0x01 << 14) // Pin 14 Selected
-#define GPIO_Pin_15 (uint16_t)(0x01 << 15) // Pin 15 Selected
-#define GPIO_Pin_All (uint16_t)(0xFFFF) // All pins Selected
-
-
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || \
- (((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || \
- (((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || \
- (((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || \
- (((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || \
- (((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || \
- (((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || \
- (((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15) )
-
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) )
-
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02 /*!< GPIO Alternate function Mode */
-}GPIOMode_TypeDef;
-
-typedef enum
-{
- GPIO_NO_PUPD = 0x0ul,
- GPIO_PuPd_UP = Px_PCR_PUPD_UP,
- GPIO_PuPd_DOWN = Px_PCR_PUPD_DOWN,
- GPIO_PuPd_Default = 0x0ul,
-}GPIOPad_TypeDef;
-
-typedef struct
-{
- uint32_t GPIO_Pin;
- GPIOMode_TypeDef GPIO_Mode;
- GPIOPad_TypeDef GPIO_Pad;
-}GPIO_InitTypeDef;
-
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-
-typedef enum
-{
- PAD_PA = 0,
- PAD_PB,
- PAD_PC,
- PAD_PD
-}PAD_Type;
-
-typedef enum
-{
- PAD_AF0 = Px_AFSR_AF0,
- PAD_AF1 = Px_AFSR_AF1,
- PAD_AF2 = Px_AFSR_AF2,
- PAD_AF3 = Px_AFSR_AF3
-}PAD_AF_TypeDef;
-
-#define IS_PAD_TYPE(Px) (((Px) == PAD_PA) || ((Px) == PAD_PB) \
- ((Px) == PAD_PC) || ((Px) == PAD_PD))
-
-#define IS_PA_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
-#define IS_PB_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
-#define IS_PC_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
-#define IS_PD_NUM(NUM) (((NUM)>=0) && ((NUM)< 5))
-
-#define IS_PAD_AF(AF) (((AF) == PAD_AF0) || ((AF) == PAD_AF1) || \
- ((AF) == PAD_AF2) || ((AF) == PAD_AF3))
-
-
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION_ == Bit_RESET) || (ACTION) ==Bit_SET))
-
-void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx);
-void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-void HAL_PAD_AFConfig(PAD_Type Px, uint16_t Pnum, PAD_AF_TypeDef P_AF);
-
-void GPIO_OutEnClr(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_OutEnSet(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __W7500X_HAL_GPIO_H
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,290 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-/*include -------------------------------------*/
-#include <stdio.h>
-#include "W7500x.h"
-
-GPIO_InitTypeDef GPIO_InitDef;
-
-uint32_t I2C_Init(I2C_ConfigStruct* conf)
-{
- uint32_t scl_port_num;
- uint32_t scl_pin_index;
- uint32_t sda_port_num;
- uint32_t sda_pin_index;
-
- scl_port_num = I2C_PORT(conf->scl);
- scl_pin_index = I2C_PIN_INDEX(conf->scl);
-
- sda_port_num = I2C_PORT(conf->sda);
- sda_pin_index = I2C_PIN_INDEX(conf->sda);
-
- //SCL setting
- GPIO_InitDef.GPIO_Pin = scl_pin_index;
- GPIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
-
- HAL_GPIO_Init((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), &GPIO_InitDef);
- HAL_GPIO_SetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
-
- //SDA setting
- GPIO_InitDef.GPIO_Pin = sda_pin_index;
- GPIO_InitDef.GPIO_Mode = GPIO_Mode_IN;
-
- HAL_GPIO_Init((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), &GPIO_InitDef);
- HAL_GPIO_ResetBits((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
-
- //Pin muxing
- HAL_PAD_AFConfig(scl_port_num, scl_pin_index, PAD_AF1);
- HAL_PAD_AFConfig(sda_port_num, sda_pin_index, PAD_AF1);
-
- return 0;
-}
-
-void I2C_WriteBitSCL(I2C_ConfigStruct* conf, uint8_t data)
-{
- uint32_t scl_port_num = I2C_PORT(conf->scl);
- uint32_t scl_pin_index = I2C_PIN_INDEX(conf->scl);
-
- if(data == 1)
- HAL_GPIO_SetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
- else
- HAL_GPIO_ResetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
-
-}
-
-void I2C_WriteBitSDA(I2C_ConfigStruct* conf, uint8_t data)
-{
- uint32_t sda_port_num = I2C_PORT(conf->sda);
- uint32_t sda_pin_index = I2C_PIN_INDEX(conf->sda);
-
- if(data == 1)
- GPIO_OutEnClr((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
- else
- GPIO_OutEnSet((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
-
-}
-
-uint8_t I2C_ReadBitSDA(I2C_ConfigStruct* conf)
-{
- uint32_t sda_port_num = I2C_PORT(conf->sda);
- uint32_t sda_pin_index = I2C_PIN_INDEX(conf->sda);
-
- if(HAL_GPIO_ReadInputDataBit((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index))
- return 1;
- else
- return 0;
-
-
- return 0;
-}
-
-void I2C_Start(I2C_ConfigStruct* conf)
-{
- I2C_WriteBitSCL(conf, 1);
- I2C_WriteBitSDA(conf, 1);
-
- I2C_WriteBitSDA(conf, 0);
- I2C_WriteBitSCL(conf, 0);
-}
-
-void I2C_Stop(I2C_ConfigStruct* conf)
-{
- I2C_WriteBitSCL(conf, 0);
- I2C_WriteBitSDA(conf, 0);
-
- I2C_WriteBitSCL(conf, 1);
- I2C_WriteBitSDA(conf, 1);
-}
-
-uint8_t I2C_WriteByte(I2C_ConfigStruct* conf, uint8_t data)
-{
- int i;
- uint8_t ret;
-
- //Write byte
- for(i=0; i<8; i++)
- {
- if((data << i) & 0x80)
- I2C_WriteBitSDA(conf, 1);
- else
- I2C_WriteBitSDA(conf, 0);
-
- I2C_WriteBitSCL(conf, 1);
- I2C_WriteBitSCL(conf, 0);
- }
- //Make clk for receiving ack
- I2C_WriteBitSDA(conf, 1);
- I2C_WriteBitSCL(conf, 1);
- //Read Ack/Nack
- ret = I2C_ReadBitSDA(conf);
-
- I2C_WriteBitSCL(conf, 0);
-
- return ret;
-}
-
-void I2C_SendACK(I2C_ConfigStruct* conf)
-{
- I2C_WriteBitSDA(conf, 0);
- I2C_WriteBitSCL(conf, 1);
-
- I2C_WriteBitSCL(conf, 0);
-}
-
-void I2C_SendNACK(I2C_ConfigStruct* conf)
-{
- I2C_WriteBitSDA(conf, 1);
- I2C_WriteBitSCL(conf, 1);
-
- I2C_WriteBitSCL(conf, 0);
-}
-
-uint8_t I2C_ReadByte(I2C_ConfigStruct* conf)
-{
- int i;
- uint8_t ret = 0;
-
- I2C_WriteBitSDA(conf, 1); //out enable clear(GPIO is input)
-
- //Read byte
- for(i=0; i<8; i++)
- {
- I2C_WriteBitSCL(conf, 1);
- ret = (ret << 1) | (I2C_ReadBitSDA(conf));
- I2C_WriteBitSCL(conf, 0);
- }
-
- return ret;
-}
-
-int I2C_Write(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
-{
- int i;
-
- I2C_Start(conf);
-
- //Write addr
- if(I2C_WriteByte(conf, addr) != 0)
- {
- printf("Received NACK at address phase!!\r\n");
- return -1;
- }
-
- //Write data
- for(i=0; i<len; i++)
- {
- if(I2C_WriteByte(conf, data[i]))
- return -1;
- }
-
- I2C_Stop(conf);
-
- return 0;//success
-}
-
-int I2C_WriteRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
-{
- int i;
-
- I2C_Start(conf);
-
- //Write addr
- if(I2C_WriteByte(conf, addr) != 0)
- {
- printf("Received NACK at address phase!!\r\n");
- return -1;
- }
-
- //Write data
- for(i=0; i<len; i++)
- {
- if(I2C_WriteByte(conf, data[i]))
- return -1;
- }
-
- return 0;//success
-}
-
-int I2C_Read(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
-{
- int i;
-
- I2C_Start(conf);
-
- //Write addr | read command
- if(I2C_WriteByte(conf, (addr | 1)) != 0)
- {
- printf("Received NACK at address phase!!\r\n");
- return -1;
- }
-
- //Read data
- for(i=0; i<len; i++)
- {
- data[i] = I2C_ReadByte(conf);
-
- if( i == (len - 1) )
- I2C_SendNACK(conf);
- else
- I2C_SendACK(conf);
- }
-
- I2C_Stop(conf);
-
- return 0;//success
-}
-
-int I2C_ReadRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
-{
- int i;
-
- I2C_Start(conf);
-
- //Write addr | read command
- if(I2C_WriteByte(conf, (addr | 1)) != 0)
- {
- printf("Received NACK at address phase!!\r\n");
- return -1;
- }
-
- //Read data
- for(i=0; i<len; i++)
- {
- data[i] = I2C_ReadByte(conf);
-
- if( i == (len - 1) )
- I2C_SendNACK(conf);
- else
- I2C_SendACK(conf);
- }
-
- return 0;//success
-}
-
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-/*include -------------------------------------*/
-#include "W7500x.h"
-
-#ifndef __W7500X_I2C_H
-#define __W7500X_I2C_H
-
-
-typedef enum {
- I2C_PA_5 = 0x05,
- I2C_PA_6 = 0x06,
- I2C_PA_9 = 0x09,
- I2C_PA_10 = 0x0A,
- I2C_PC_4 = 0x24,
- I2C_PC_5 = 0x25,
- I2C_PC_8 = 0x28,
- // Not connected
- I2C_NC = (int)0xFFFFFFFF
-} I2C_PinName;
-
-typedef struct
-{
- I2C_PinName scl;
- I2C_PinName sda;
-}I2C_ConfigStruct;
-
-
-#define I2C_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D)
-#define I2C_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit
-
-uint32_t I2C_Init(I2C_ConfigStruct* conf);
-
-void I2C_WriteBitSDA(I2C_ConfigStruct* conf, uint8_t data);
-void I2C_WriteBitSCL(I2C_ConfigStruct* conf, uint8_t data);
-uint8_t I2C_ReadBitSDA(I2C_ConfigStruct* conf);
-
-void I2C_SendACK(I2C_ConfigStruct* conf);
-void I2C_SendNACK(I2C_ConfigStruct* conf);
-
-uint8_t I2C_WriteByte(I2C_ConfigStruct* conf, uint8_t data);
-uint8_t I2C_ReadByte(I2C_ConfigStruct* conf);
-
-void I2C_Start(I2C_ConfigStruct* conf);
-void I2C_Stop(I2C_ConfigStruct* conf);
-
-int I2C_Write(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len);
-int I2C_WriteRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len);
-int I2C_Read(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len);
-int I2C_ReadRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len);
-
-
- #endif //__W7500X_I2C_H
-
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,905 +0,0 @@
-/**
- ******************************************************************************
- * @file
- * @author
- * @version
- * @date
- * @brief This file contains all the functions prototypes for the UART
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Includes -------------------------------------------*/
-#include "W7500x.h"
-
-void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn)
-{
- if( PWM_CHn == PWM_CH0 )
- {
- PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register
- PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register
- PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register
- PWM_CH0->IER = 0; ///< Interrupt enable register
- PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear |
- PWM_CHn_ICR_OverflowInterruptClear |
- PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
- PWM_CH0->PR = 0; ///< Prescale register
- PWM_CH0->MR = 0; ///< Match register
- PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register
- PWM_CH0->UDMR = 0; ///< Up Dowm mode register
- PWM_CH0->TCMR = 0; ///< Timer Counter mode register
- PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register
- PWM_CH0->CMR = 0; ///< Capture mode register
- PWM_CH0->PDMR = 0; ///< Periodic Mode register
- PWM_CH0->DZER = 0; ///< Dead Zone Enable register
- PWM_CH0->DZCR = 0; ///< Dead Zone Counter register
- }
- else if( PWM_CHn == PWM_CH1 )
- {
- PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register
- PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register
- PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register
- PWM_CH1->IER = 0; ///< Interrupt enable register
- PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear |
- PWM_CHn_ICR_OverflowInterruptClear |
- PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
- PWM_CH1->PR = 0; ///< Prescale register
- PWM_CH1->MR = 0; ///< Match register
- PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register
- PWM_CH1->UDMR = 0; ///< Up Dowm mode register
- PWM_CH1->TCMR = 0; ///< Timer Counter mode register
- PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register
- PWM_CH1->CMR = 0; ///< Capture mode register
- PWM_CH1->PDMR = 0; ///< Periodic Mode register
- PWM_CH1->DZER = 0; ///< Dead Zone Enable register
- PWM_CH1->DZCR = 0; ///< Dead Zone Counter register
- }
- else if( PWM_CHn == PWM_CH2)
- {
- PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register
- PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register
- PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register
- PWM_CH2->IER = 0; ///< Interrupt enable register
- PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear |
- PWM_CHn_ICR_OverflowInterruptClear |
- PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
- PWM_CH2->PR = 0; ///< Prescale register
- PWM_CH2->MR = 0; ///< Match register
- PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register
- PWM_CH2->UDMR = 0; ///< Up Dowm mode register
- PWM_CH2->TCMR = 0; ///< Timer Counter mode register
- PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register
- PWM_CH2->CMR = 0; ///< Capture mode register
- PWM_CH2->PDMR = 0; ///< Periodic Mode register
- PWM_CH2->DZER = 0; ///< Dead Zone Enable register
- PWM_CH2->DZCR = 0; ///< Dead Zone Counter register
- }
- else if( PWM_CHn == PWM_CH3 )
- {
- PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register
- PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register
- PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register
- PWM_CH3->IER = 0; ///< Interrupt enable register
- PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear |
- PWM_CHn_ICR_OverflowInterruptClear |
- PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
- PWM_CH3->MR = 0; ///< Match register
- PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register
- PWM_CH3->UDMR = 0; ///< Up Dowm mode register
- PWM_CH3->TCMR = 0; ///< Timer Counter mode register
- PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register
- PWM_CH3->CMR = 0; ///< Capture mode register
- PWM_CH3->PDMR = 0; ///< Periodic Mode register
- PWM_CH3->DZER = 0; ///< Dead Zone Enable register
- PWM_CH3->DZCR = 0; ///< Dead Zone Counter register
- }
- else if( PWM_CHn == PWM_CH4 )
- {
- PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register
- PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register
- PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register
- PWM_CH4->IER = 0; ///< Interrupt enable register
- PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear |
- PWM_CHn_ICR_OverflowInterruptClear |
- PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
- PWM_CH4->PR = 0; ///< Prescale register
- PWM_CH4->MR = 0; ///< Match register
- PWM_CH4->LR = 0xFFFF; ///< Limit register
- PWM_CH4->UDMR = 0; ///< Up Dowm mode register
- PWM_CH4->TCMR = 0; ///< Timer Counter mode register
- PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register
- PWM_CH4->CMR = 0; ///< Capture mode register
- PWM_CH4->PDMR = 0; ///< Periodic Mode register
- PWM_CH4->DZER = 0; ///< Dead Zone Enable register
- PWM_CH4->DZCR = 0; ///< Dead Zone Counter register
- }
- else if( PWM_CHn == PWM_CH5 )
- {
- PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register
- PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register
- PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register
- PWM_CH5->IER = 0; ///< Interrupt enable register
- PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear |
- PWM_CHn_ICR_OverflowInterruptClear |
- PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
- PWM_CH5->PR = 0; ///< Prescale register
- PWM_CH5->MR = 0; ///< Match register
- PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register
- PWM_CH5->UDMR = 0; ///< Up Dowm mode register
- PWM_CH5->TCMR = 0; ///< Timer Counter mode register
- PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register
- PWM_CH5->CMR = 0; ///< Capture mode register
- PWM_CH5->PDMR = 0; ///< Periodic Mode register
- PWM_CH5->DZER = 0; ///< Dead Zone Enable register
- PWM_CH5->DZCR = 0; ///< Dead Zone Counter register
- }
- else if( PWM_CHn == PWM_CH6 )
- {
- PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register
- PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register
- PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register
- PWM_CH6->IER = 0; ///< Interrupt enable register
- PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear |
- PWM_CHn_ICR_OverflowInterruptClear |
- PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
- PWM_CH6->PR = 0; ///< Prescale register
- PWM_CH6->MR = 0; ///< Match register
- PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register
- PWM_CH6->UDMR = 0; ///< Up Dowm mode register
- PWM_CH6->TCMR = 0; ///< Timer Counter mode register
- PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register
- PWM_CH6->CMR = 0; ///< Capture mode register
- PWM_CH6->PDMR = 0; ///< Periodic Mode register
- PWM_CH6->DZER = 0; ///< Dead Zone Enable register
- PWM_CH6->DZCR = 0; ///< Dead Zone Counter register
- }
- else if( PWM_CHn == PWM_CH7 )
- {
- PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register
- PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register
- PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register
- PWM_CH7->IER = 0; ///< Interrupt enable register
- PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear |
- PWM_CHn_ICR_OverflowInterruptClear |
- PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
- PWM_CH7->PR = 0; ///< Prescale register
- PWM_CH7->MR = 0; ///< Match register
- PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register
- PWM_CH7->UDMR = 0; ///< Up Dowm mode register
- PWM_CH7->TCMR = 0; ///< Timer Counter mode register
- PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register
- PWM_CH7->CMR = 0; ///< Capture mode register
- PWM_CH7->PDMR = 0; ///< Periodic Mode register
- PWM_CH7->DZER = 0; ///< Dead Zone Enable register
- PWM_CH7->DZCR = 0; ///< Dead Zone Counter register
- }
-}
-
-
-void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet
-{
- /* Stop PWM_CHn */
- PWM_CHn_Stop(PWM_CHn);
- /* Select Timer/Counter mode as Timer mode */
- PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
- /* Set Prescale register value */
- PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR;
- /* Set Match register value */
- PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR;
- /* Set Limit register value */
- PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR;
- /* Select Up-down mode */
- PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR;
- /* Select Periodic mode */
- PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR;
-}
-
-void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR));
- assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR));
- assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR));
- assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR));
- assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR));
- assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR));
-
- /* Stop PWM_CHn */
- PWM_CHn_Stop(PWM_CHn);
- /* Select Timer/Counter mode as Timer mode */
- PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
- /* Set Prescale register value */
- PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR;
- /* Set Match register value */
- PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR;
- /* Set Limit register value */
- PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR;
- /* Select Up-down mode */
- PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR;
- /* Select Periodic mode */
- PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR;
- /* Select Capture mode */
- PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR;
- /* External input enable */
- PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
-}
-
-void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- /* Stop PWM_CHn */
- PWM_CHn_Stop(PWM_CHn);
- /* Select Timer/Counter mode as Timer mode */
- PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
- /* Set Match register value */
- PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR;
- /* Set Limit register value */
- PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR;
- /* Select Up-down mode */
- PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR;
- /* Select Periodic mode */
- PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR;
- /* Select Counter mode */
- PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR;
- /* Enable external input */
- PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
-}
-
-void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR));
- assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR));
- assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR));
- assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR));
- assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR));
- assert_param(IS_PWM_Deadznoe(PWM_CHn));
-
- /* Stop PWM_CHn */
- PWM_CHn_Stop(PWM_CHn);
- /* Select Timer/Counter mode as Timer mode */
- PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
- /* Set Prescale register value */
- PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR;
- /* Set Match register value */
- PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR;
- /* Set Limit register value */
- PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR;
- /* Select Up-down mode */
- PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR;
- /* Select Periodic mode */
- PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR;
- /* Enable Dead Zone generation */
- PWM_CHn->DZER = PWM_CHn_DZER_Enable;
- /* Set Dead Zone Counter */
- PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR;
-}
-
-void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_Output(outputEnDisable));
- if( PWM_CHn->DZER )
- assert_param(IS_PWM_Deadznoe(PWM_CHn));
-
- /* Stop PWM_CHn */
- PWM_CHn_Stop(PWM_CHn);
- /*Config PWM output and External input */
- PWM_CHn->PEEER = outputEnDisable;
-}
-
-void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn)
-{
- PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable);
-}
-
-void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn)
-{
- PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable);
-}
-
-void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- /* Stop PWM_CHn */
- PWM_CHn_Stop(PWM_CHn);
-
- if(state == ENABLE)
- {
- if(PWM_CHn == PWM_CH0) {
- PWM->IER |= PWM_IER_IE0_Enable;
- }
- else if(PWM_CHn == PWM_CH1) {
- PWM->IER |= PWM_IER_IE1_Enable;
- }
- else if(PWM_CHn == PWM_CH2) {
- PWM->IER |= PWM_IER_IE2_Enable;
- }
- else if(PWM_CHn == PWM_CH3) {
- PWM->IER |= PWM_IER_IE3_Enable;
- }
- else if(PWM_CHn == PWM_CH4) {
- PWM->IER |= PWM_IER_IE4_Enable;
- }
- else if(PWM_CHn == PWM_CH5) {
- PWM->IER |= PWM_IER_IE5_Enable;
- }
- else if(PWM_CHn == PWM_CH6) {
- PWM->IER |= PWM_IER_IE6_Enable;
- }
- else if(PWM_CHn == PWM_CH7) {
- PWM->IER |= PWM_IER_IE7_Enable;
- }
- }
- else
- {
- if(PWM_CHn == PWM_CH0) {
- PWM->IER &= PWM_IER_IE0_Disable;
- }
- else if(PWM_CHn == PWM_CH1) {
- PWM->IER &= PWM_IER_IE1_Disable;
- }
- else if(PWM_CHn == PWM_CH2) {
- PWM->IER &= PWM_IER_IE2_Disable;
- }
- else if(PWM_CHn == PWM_CH3) {
- PWM->IER &= PWM_IER_IE3_Disable;
- }
- else if(PWM_CHn == PWM_CH4) {
- PWM->IER &= PWM_IER_IE4_Disable;
- }
- else if(PWM_CHn == PWM_CH5) {
- PWM->IER &= PWM_IER_IE5_Disable;
- }
- else if(PWM_CHn == PWM_CH6) {
- PWM->IER &= PWM_IER_IE6_Disable;
- }
- else if(PWM_CHn == PWM_CH7) {
- PWM->IER &= PWM_IER_IE7_Disable;
- }
- }
-}
-
-FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn)
-{
- FlagStatus ret_val = RESET;
-
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- if(PWM_CHn == PWM_CH0) {
- ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0);
- }
- else if(PWM_CHn == PWM_CH1) {
- ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1);
- }
- else if(PWM_CHn == PWM_CH2) {
- ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2);
- }
- else if(PWM_CHn == PWM_CH3) {
- ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3);
- }
- else if(PWM_CHn == PWM_CH4) {
- ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4);
- }
- else if(PWM_CHn == PWM_CH5) {
- ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5);
- }
- else if(PWM_CHn == PWM_CH6) {
- ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6);
- }
- else if(PWM_CHn == PWM_CH7) {
- ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7);
- }
-
- return ret_val;
-}
-
-void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
-
- assert_param(IS_PWM_CHn_IER(PWM_CHn_IER));
-
- /* Stop PWM_CHn */
- PWM_CHn_Stop(PWM_CHn);
-
- if(state == ENABLE)
- PWM_CHn->IER |= PWM_CHn_IER;
- else
- PWM_CHn->IER &= ~PWM_CHn_IER;
-}
-
-uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->IER;
-}
-
-uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->IR;
-}
-
-void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR)
-{
- /* Check the parameters */
-
- PWM_CHn->ICR = PWM_CHn_ICR;
-}
-
-void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- /* Set Start Stop register */
- if(PWM_CHn == PWM_CH0) {
- PWM->SSR |= PWM_SSR_SS0_Start;
- }
- else if(PWM_CHn == PWM_CH1) {
- PWM->SSR |= PWM_SSR_SS1_Start;
- }
- else if(PWM_CHn == PWM_CH2) {
- PWM->SSR |= PWM_SSR_SS2_Start;
- }
- else if(PWM_CHn == PWM_CH3) {
- PWM->SSR |= PWM_SSR_SS3_Start;
- }
- else if(PWM_CHn == PWM_CH4) {
- PWM->SSR |= PWM_SSR_SS4_Start;
- }
- else if(PWM_CHn == PWM_CH5) {
- PWM->SSR |= PWM_SSR_SS5_Start;
- }
- else if(PWM_CHn == PWM_CH6) {
- PWM->SSR |= PWM_SSR_SS6_Start;
- }
- else if(PWM_CHn == PWM_CH7) {
- PWM->SSR |= PWM_SSR_SS7_Start;
- }
-}
-
-void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete
-{
- /* Set Start Stop register */
- PWM->SSR |= ssr_bit_flag;
-}
-
-void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Reset Start Stop register */
- if(PWM_CHn == PWM_CH0) {
- PWM->SSR &= PWM_SSR_SS0_Stop;
- }
- else if(PWM_CHn == PWM_CH1) {
- PWM->SSR &= PWM_SSR_SS1_Stop;
- }
- else if(PWM_CHn == PWM_CH2) {
- PWM->SSR &= PWM_SSR_SS2_Stop;
- }
- else if(PWM_CHn == PWM_CH3) {
- PWM->SSR &= PWM_SSR_SS3_Stop;
- }
- else if(PWM_CHn == PWM_CH4) {
- PWM->SSR &= PWM_SSR_SS4_Stop;
- }
- else if(PWM_CHn == PWM_CH5) {
- PWM->SSR &= PWM_SSR_SS5_Stop;
- }
- else if(PWM_CHn == PWM_CH6) {
- PWM->SSR &= PWM_SSR_SS6_Stop;
- }
- else if(PWM_CHn == PWM_CH7) {
- PWM->SSR &= PWM_SSR_SS7_Stop;
- }
-}
-
-void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete
-{
- /* Reset Start Stop register */
- PWM->SSR &= ~ssr_bit_flag;
-}
-
-void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn)
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- /* Set Pause register */
- if(PWM_CHn == PWM_CH0) {
- PWM->PSR |= PWM_PSR_PS0_Pause;
- }
- else if(PWM_CHn == PWM_CH1) {
- PWM->PSR |= PWM_PSR_PS1_Pause;
- }
- else if(PWM_CHn == PWM_CH2) {
- PWM->PSR |= PWM_PSR_PS2_Pause;
- }
- else if(PWM_CHn == PWM_CH3) {
- PWM->PSR |= PWM_PSR_PS3_Pause;
- }
- else if(PWM_CHn == PWM_CH4) {
- PWM->PSR |= PWM_PSR_PS4_Pause;
- }
- else if(PWM_CHn == PWM_CH5) {
- PWM->PSR |= PWM_PSR_PS5_Pause;
- }
- else if(PWM_CHn == PWM_CH6) {
- PWM->PSR |= PWM_PSR_PS6_Pause;
- }
- else if(PWM_CHn == PWM_CH7) {
- PWM->PSR |= PWM_PSR_PS7_Pause;
- }
-}
-
-void PWM_Multi_Pause(uint32_t psr_bit_flag)
-{
- PWM->PSR |= psr_bit_flag;
-}
-
-void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn)
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- /* Reset Pause register */
- if(PWM_CHn == PWM_CH0) {
- PWM->PSR &= PWM_PSR_PS0_Restart;
- }
- else if(PWM_CHn == PWM_CH1) {
- PWM->PSR &= PWM_PSR_PS1_Restart;
- }
- else if(PWM_CHn == PWM_CH2) {
- PWM->PSR &= PWM_PSR_PS2_Restart;
- }
- else if(PWM_CHn == PWM_CH3) {
- PWM->PSR &= PWM_PSR_PS3_Restart;
- }
- else if(PWM_CHn == PWM_CH4) {
- PWM->PSR &= PWM_PSR_PS4_Restart;
- }
- else if(PWM_CHn == PWM_CH5) {
- PWM->PSR &= PWM_PSR_PS5_Restart;
- }
- else if(PWM_CHn == PWM_CH6) {
- PWM->PSR &= PWM_PSR_PS6_Restart;
- }
- else if(PWM_CHn == PWM_CH7) {
- PWM->PSR &= PWM_PSR_PS7_Restart;
- }
-}
-
-void PWM_Multi_Restart(uint32_t psr_bit_flag)
-{
- PWM->PSR &= ~psr_bit_flag;
-}
-
-
-uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->TCR;
-}
-
-uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->PCR;
-}
-
-uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->PR;
-}
-
-void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_PR_FILTER(PR));
-
- PWM_CHn->PR = PR;
-}
-
-uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->MR;
-}
-
-void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- PWM_CHn->MR = MR;
-}
-
-uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->LR;
-}
-
-void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- PWM_CHn->LR = LR;
-}
-
-uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->UDMR;
-}
-
-void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_CHn_UDMR(UDMR));
-
- PWM_CHn->UDMR = UDMR;
-}
-
-uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->TCMR;
-}
-
-void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_CHn_TCMR(TCMR));
-
- PWM_CHn->TCMR = TCMR;
-}
-
-uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->PEEER;
-}
-
-void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_CHn_PEEER(PEEER));
-
- PWM_CHn->PEEER = PEEER;
-}
-
-uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->CMR;
-}
-
-void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_CHn_CMR(CMR));
-
- PWM_CHn->CMR = CMR;
-}
-
-uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn)
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->CR;
-}
-
-uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->PDMR;
-}
-
-void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_CHn_PDMR(PDMR));
-
- PWM_CHn->PDMR = PDMR;
-}
-
-uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->DZER;
-}
-
-void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_CHn_DZER(DZER));
-
- PWM_CHn->DZER = DZER;
-}
-
-uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
-
- return PWM_CHn->DZCR;
-}
-
-void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete
-{
- /* Check the parameters */
- assert_param(IS_PWM_ALL_CH(PWM_CHn));
- assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR));
-
- PWM_CHn->DZCR = DZCR;
-}
-
-void PWM_CH0_ClearMatchInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear);
-}
-
-void PWM_CH0_ClearOverflowInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear);
-}
-
-void PWM_CH0_ClearCaptureInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear);
-}
-
-void PWM_CH1_ClearMatchInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear);
-}
-
-void PWM_CH1_ClearOverflowInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear);
-}
-
-void PWM_CH1_ClearCaptureInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear);
-}
-
-void PWM_CH2_ClearMatchInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear);
-}
-
-void PWM_CH2_ClearOverflowInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear);
-}
-
-void PWM_CH2_ClearCaptureInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear);
-}
-
-void PWM_CH3_ClearMatchInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear);
-}
-
-void PWM_CH3_ClearOverflowInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear);
-}
-
-void PWM_CH3_ClearCaptureInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear);
-}
-
-void PWM_CH4_ClearMatchInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear);
-}
-
-void PWM_CH4_ClearOverflowInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear);
-}
-
-void PWM_CH4_ClearCaptureInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear);
-}
-
-void PWM_CH5_ClearMatchInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear);
-}
-
-void PWM_CH5_ClearOverflowInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear);
-}
-
-void PWM_CH5_ClearCaptureInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear);
-}
-
-void PWM_CH6_ClearMatchInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear);
-}
-
-void PWM_CH6_ClearOverflowInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear);
-}
-
-void PWM_CH6_ClearCaptureInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear);
-}
-
-void PWM_CH7_ClearMatchInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear);
-}
-
-void PWM_CH7_ClearOverflowInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear);
-}
-
-void PWM_CH7_ClearCaptureInt(void)
-{
- PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear);
-}
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,289 +0,0 @@
-/**
- ******************************************************************************
- * @file
- * @author
- * @version
- * @date
- * @brief This file contains all the functions prototypes for the UART
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __W7500X_PWM_H
-#define __W7500X_PWM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "W7500x.h"
-
-/**********************************************************************************************/
-/**********************************************************************************************/
-// This structure and define must be in W7500x.h
-/**********************************************************************************************/
-/**********************************************************************************************/
-
-typedef struct
-{
- uint32_t PWM_CHn_PEEER;
-}PWM_CtrlPWMOutputTypeDef;
-
-typedef struct
-{
- uint32_t PWM_CHn_PR;
- uint32_t PWM_CHn_MR;
- uint32_t PWM_CHn_LR;
- uint32_t PWM_CHn_UDMR;
- uint32_t PWM_CHn_PDMR;
- uint32_t PWM_CHn_DZCR;
-}PWM_DeadzoneModeInitTypDef;
-
-#define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
- (CHn == PWM_CH1) || \
- (CHn == PWM_CH2) || \
- (CHn == PWM_CH3) || \
- (CHn == PWM_CH4) || \
- (CHn == PWM_CH5) || \
- (CHn == PWM_CH6) || \
- (CHn == PWM_CH7))
-
-#define PWM_IER_IE0_Enable (0x1ul << 0)
-#define PWM_IER_IE1_Enable (0x1ul << 1)
-#define PWM_IER_IE2_Enable (0x1ul << 2)
-#define PWM_IER_IE3_Enable (0x1ul << 3)
-#define PWM_IER_IE4_Enable (0x1ul << 4)
-#define PWM_IER_IE5_Enable (0x1ul << 5)
-#define PWM_IER_IE6_Enable (0x1ul << 6)
-#define PWM_IER_IE7_Enable (0x1ul << 7)
-
-#define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
-#define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
-#define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
-#define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
-#define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
-#define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
-#define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
-#define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
-
-#define PWM_SSR_SS0_Start (0x1ul << 0)
-#define PWM_SSR_SS1_Start (0x1ul << 1)
-#define PWM_SSR_SS2_Start (0x1ul << 2)
-#define PWM_SSR_SS3_Start (0x1ul << 3)
-#define PWM_SSR_SS4_Start (0x1ul << 4)
-#define PWM_SSR_SS5_Start (0x1ul << 5)
-#define PWM_SSR_SS6_Start (0x1ul << 6)
-#define PWM_SSR_SS7_Start (0x1ul << 7)
-
-#define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
-#define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
-#define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
-#define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
-#define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
-#define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
-#define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
-#define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
-
-#define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
-
-#define PWM_PSR_PS0_Pause (0x1ul << 0)
-#define PWM_PSR_PS1_Pause (0x1ul << 1)
-#define PWM_PSR_PS2_Pause (0x1ul << 2)
-#define PWM_PSR_PS3_Pause (0x1ul << 3)
-#define PWM_PSR_PS4_Pause (0x1ul << 4)
-#define PWM_PSR_PS5_Pause (0x1ul << 5)
-#define PWM_PSR_PS6_Pause (0x1ul << 6)
-#define PWM_PSR_PS7_Pause (0x1ul << 7)
-
-#define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
-#define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
-#define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
-#define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
-#define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
-#define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
-#define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
-#define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
-
-#define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
-
-#define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
-#define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
-#define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
-#define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
-
-#define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
-#define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
-#define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
-
-#define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
-#define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
-#define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
-#define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
-
-/*
-#define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
- ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
- ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
- ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
- ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
- ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
- ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
- ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
-*/
-
-
-#define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
-
-
-#define PWM_CHn_UDMR_UpCount (0x0ul)
-#define PWM_CHn_UDMR_DownCount (0x1ul)
-#define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
- (MODE == PWM_CHn_UDMR_DownCount))
-
-#define PWM_CHn_TCMR_TimerMode (0x0ul)
-#define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
-#define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
-#define PWM_CHn_TCMR_BothCounterMode (0x3ul)
-#define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
- (MODE == PWM_CHn_TCMR_FallingCounterMode) || \
- (MODE == PWM_CHn_TCMR_BothCounterMode))
-
-#define PWM_CHn_PEEER_Disable (0x0ul)
-#define PWM_CHn_PEEER_ExtEnable (0x1ul)
-#define PWM_CHn_PEEER_PWMEnable (0x2ul)
-#define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
- (ENABLE == PWM_CHn_PEEER_ExtEnable) || \
- (ENABLE == PWM_CHn_PEEER_PWMEnable))
-
-#define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
- (ENABLE == PWM_CHn_PEEER_PWMEnable))
-
-#define PWM_CHn_CMR_RisingEdge 0x0ul
-#define PWM_CHn_CMR_FallingEdge 0x1ul
-#define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
- (MODE == PWM_CHn_CMR_FallingEdge))
-
-#define PWM_CHn_PDMR_Oneshot (0x0ul)
-#define PWM_CHn_PDMR_Periodic (0x1ul)
-#define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
- (MODE == PWM_CHn_PDMR_Oneshot))
-
-#define PWM_CHn_DZER_Enable (0x1ul)
-#define PWM_CHn_DZER_Disable (0x0ul)
-#define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
- (ENABLE == PWM_CHn_DZER_Disable))
-
-#define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
- ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
- ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
- ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
- ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
- ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
- ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
- ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
-
-#define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
-
-
-
-
-
-
-void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
-void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
-void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
-void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
-void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
-void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
-void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
-void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
-FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
-void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_Multi_Start(uint32_t ssr_bit_flag);
-void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_Multi_Stop(uint32_t ssr_bit_flag);
-void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_Multi_Pause(uint32_t psr_bit_flag);
-void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_Multi_Restart(uint32_t psr_bit_flag);
-uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
-uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
-uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
-uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
-uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
-uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
-uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
-uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
-uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
-uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
-uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
-uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
-uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
-void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
-uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
-void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
-void PWM_CH0_ClearMatchInt(void);
-void PWM_CH0_ClearOverflowInt(void);
-void PWM_CH0_ClearCaptureInt(void);
-void PWM_CH1_ClearMatchInt(void);
-void PWM_CH1_ClearOverflowInt(void);
-void PWM_CH1_ClearCaptureInt(void);
-void PWM_CH2_ClearMatchInt(void);
-void PWM_CH2_ClearOverflowInt(void);
-void PWM_CH2_ClearCaptureInt(void);
-void PWM_CH3_ClearMatchInt(void);
-void PWM_CH3_ClearOverflowInt(void);
-void PWM_CH3_ClearCaptureInt(void);
-void PWM_CH4_ClearMatchInt(void);
-void PWM_CH4_ClearOverflowInt(void);
-void PWM_CH4_ClearCaptureInt(void);
-void PWM_CH5_ClearMatchInt(void);
-void PWM_CH5_ClearOverflowInt(void);
-void PWM_CH5_ClearCaptureInt(void);
-void PWM_CH6_ClearMatchInt(void);
-void PWM_CH6_ClearOverflowInt(void);
-void PWM_CH6_ClearCaptureInt(void);
-void PWM_CH7_ClearMatchInt(void);
-void PWM_CH7_ClearOverflowInt(void);
-void PWM_CH7_ClearCaptureInt(void);
-
-
-void PWM0_Handler(void);
-void PWM1_Handler(void);
-void PWM2_Handler(void);
-void PWM3_Handler(void);
-void PWM4_Handler(void);
-void PWM5_Handler(void);
-void PWM6_Handler(void);
-void PWM7_Handler(void);
-
-
-
-
-//Temporary macro=======
-#define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
-//======================
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif //__W7500X_PWM_H
-
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.c Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,370 +0,0 @@
-/**
- ******************************************************************************
- * @file W7500x_uart.c
- * @author
- * @version
- * @date
- * @brief
- ******************************************************************************
- * @attention
- *
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "W7500x.h"
-
-void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
-{
- /* UART_InitStruct members default value */
- UART_InitStruct->UART_BaudRate = 115200;
- UART_InitStruct->UART_WordLength = UART_WordLength_8b ;
- UART_InitStruct->UART_StopBits = UART_StopBits_1;
- UART_InitStruct->UART_Parity = UART_Parity_No ;
- UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
- UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ;
-}
-
-void UART_DeInit(UART_TypeDef *UARTx)
-{
-
-}
-
-uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct)
-{
- float baud_divisor;
- uint32_t tmpreg=0x00, uartclock=0x00;
- uint32_t integer_baud = 0x00, fractional_baud = 0x00;
-
- assert_param(IS_UART_01_PERIPH(UARTx));
- assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength));
- assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
- assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl));
- assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode));
-
-
- UARTx->CR &= ~(UART_CR_UARTEN);
-
- // Set baudrate
- CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz )
- uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR);
-
- baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate));
- integer_baud = (uint32_t)baud_divisor;
- fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5);
-
- UARTx->IBRD = integer_baud;
- UARTx->FBRD = fractional_baud;
-
-
- tmpreg = UARTx->LCR_H;
- tmpreg &= ~(0x00EE);
- tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity);
- UARTx->LCR_H |= tmpreg;
-
- tmpreg = UARTx->CR;
- tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN);
- tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl);
- UARTx->CR |= tmpreg;
-
- UARTx->CR |= UART_CR_UARTEN;
-
- return 0;
-}
-
-
-void UART_SendData(UART_TypeDef* UARTx, uint16_t Data)
-{
- assert_param(IS_UART_01_PERIPH(UARTx));
-
- UARTx->DR = Data;
-}
-
-
-uint16_t UART_ReceiveData(UART_TypeDef* UARTx)
-{
- assert_param(IS_UART_01_PERIPH(UARTx));
-
- return (uint16_t)(UARTx->DR);
-}
-
-
-void UART_SendBreak(UART_TypeDef* UARTx)
-{
- assert_param(IS_UART_01_PERIPH(UARTx));
-
- UARTx->LCR_H |= UART_LCR_H_BRK;
-}
-
-
-FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
-{
- FlagStatus bitstatus = RESET;
-
- assert_param(IS_UART_01_PERIPH(UARTx));
- assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
-
- if( (UARTx->STATUS.RSR & UART_RECV_STATUS) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-
-void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
-{
- assert_param(IS_UART_01_PERIPH(UARTx));
- assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
-
- UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS;
-}
-
-
-FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- assert_param(IS_UART_01_PERIPH(UARTx));
- assert_param(IS_UART_FLAG(UART_FLAG));
-
- if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-
-}
-
-/*
-void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG)
-{
-
-}
-*/
-
-void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState)
-{
- assert_param(IS_UART_01_PERIPH(UARTx));
- assert_param(IS_UART_IT_FLAG(UART_IT));
-
- if ( NewState != DISABLE )
- {
- UARTx->IMSC |= UART_IT;
- }
- else
- {
- UARTx->ICR |= UART_IT;
- }
-}
-
-
-ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT)
-{
- ITStatus bitstatus = RESET;
-
- assert_param(IS_UART_01_PERIPH(UARTx));
- assert_param(IS_UART_IT_FLAG(UART_IT));
-
- if ((UARTx->MIS & UART_IT) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT)
-{
- assert_param(IS_UART_01_PERIPH(UARTx));
- assert_param(IS_UART_IT_FLAG(UART_IT));
-
- UARTx->ICR |= UART_IT;
-}
-
-
-void S_UART_DeInit()
-{
-
-}
-
-uint32_t S_UART_Init(uint32_t baud)
-{
- uint32_t tmpreg=0x00;
- uint32_t uartclock = 0x00, integer_baud = 0x00;
-
- assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode));
-
- if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK)
- {
- uartclock = INTERN_XTAL;
- }
- else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK)
- {
- uartclock = EXTERN_XTAL;
- }
- else
- {
- uartclock = GetSystemClock();
- }
-
- integer_baud = (uint32_t)(uartclock / baud);
- UART2->BAUDDIV = integer_baud;
-
- tmpreg = UART2->CTRL;
- tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
- tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
- UART2->CTRL = tmpreg;
-
- return 0;
-}
-
-void S_UART_SendData(uint16_t Data)
-{
- while(UART2->STATE & S_UART_STATE_TX_BUF_FULL);
- UART2->DATA = Data;
-}
-
-uint16_t S_UART_ReceiveData()
-{
- return (uint16_t)(UART2->DATA);
-}
-
-
-FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- assert_param(IS_S_UART_FLAG(S_UART_FLAG));
-
- if ((UART2->STATE & S_UART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-
-void S_UART_ITConfig(uint16_t S_UART_IT, FunctionalState NewState)
-{
- assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
-
- if ( NewState != DISABLE )
- {
- UART2->CTRL |= S_UART_IT;
- }
- else
- {
- UART2->CTRL &= ~(S_UART_IT);
- }
-}
-
-ITStatus S_UART_GetITStatus(uint16_t S_UART_IT)
-{
- ITStatus bitstatus = RESET;
-
- assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
-
- if ((UART2->INT.STATUS & (S_UART_IT >> 2)) != (uint16_t) RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-void S_UART_ClearITPendingBit(uint16_t S_UART_IT)
-{
- assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
-
- UART2->INT.CLEAR |= (S_UART_IT >> 2);
-}
-
-
-/**************************************************/
-// It will be moved to application board's driver */
-/**************************************************/
-uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch)
-{
- UART_SendData(UARTx,ch);
-
- while(UARTx->FR & UART_FR_BUSY);
-
- return (ch);
-}
-
-void UartPuts(UART_TypeDef* UARTx, uint8_t *str)
-{
- uint8_t ch;
-
- do{
- ch = *str;
- if(ch != (uint8_t)0x0)
- {
- UartPutc(UARTx, ch);
- }
- *str++;
- }while(ch != 0);
-}
-
-uint8_t UartGetc(UART_TypeDef* UARTx)
-{
- while(UARTx->FR & UART_FR_RXFE);
-
- return (UARTx->DR & 0xFF);
-}
-
-
-uint8_t S_UartPutc(uint8_t ch)
-{
- S_UART_SendData(ch);
-
- return (ch);
-}
-
-void S_UartPuts(uint8_t *str)
-{
- uint8_t ch;
-
- do{
- ch = *str;
- if(ch != (uint8_t)0x0)
- {
- S_UART_SendData(ch);
- }
- *str++;
- }while(ch != 0);
-}
-
-uint8_t S_UartGetc()
-{
- while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 );
- return (uint8_t)S_UART_ReceiveData();
-}
-
-
--- a/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_uart.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,289 +0,0 @@
-/**
- ******************************************************************************
- * @file
- * @author
- * @version
- * @date
- * @brief This file contains all the functions prototypes for the UART
- * firmware library.
- ******************************************************************************
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __W7500X_UART_H
-#define __W7500X_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "W7500x.h"
-
-
-/**
- * @brief UART Init Structure definition
- */
-
-typedef struct
-{
- uint32_t UART_BaudRate;
- uint16_t UART_WordLength;
- uint16_t UART_StopBits;
- uint16_t UART_Parity;
- uint16_t UART_Mode;
- uint16_t UART_HardwareFlowControl;
-} UART_InitTypeDef;
-
-/**
- * @}
- */
-
-
-/** @defgroup UART_Exported_Constants
- * @{
- */
-
-#define IS_UART_01_PERIPH(PERIPH) (((PERIPH) == UART0) || ((PERIPH) == UART1))
-#define IS_UART_2_PERIPH(PERIPH) ((PERIPH) == UART2)
-
-/**
- * @}
- */
-
-
-
-/** @addtogroup UART_Word_Length
- * @{
- */
-
-#define UART_WordLength_8b ((uint16_t)UART_LCR_H_WLEN(3))
-#define UART_WordLength_7b ((uint16_t)UART_LCR_H_WLEN(2))
-#define UART_WordLength_6b ((uint16_t)UART_LCR_H_WLEN(1))
-#define UART_WordLength_5b ((uint16_t)UART_LCR_H_WLEN(0))
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_8b) || \
- ((LENGTH) == UART_WordLength_7b) || \
- ((LENGTH) == UART_WordLength_6b) || \
- ((LENGTH) == UART_WordLength_5b) )
-/**
- * @}
- */
-
-
-/** @addtogroup UART_Parity
- * @{
- */
-
-#define UART_Parity_No ((uint16_t)0x0000)
-#define UART_Parity_Even ((uint16_t)(UART_LCR_H_PEN | UART_LCR_H_EPS))
-#define UART_Parity_Odd ((uint16_t)(UART_LCR_H_PEN))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
- ((PARITY) == UART_Parity_Even) || \
- ((PARITY) == UART_Parity_Odd))
-
-/**
- * @}
- */
-
-
-/** @addtogroup UART_Stop_Bits
- * @{
- */
-
-#define UART_StopBits_1 ((uint16_t)0x0000)
-#define UART_StopBits_2 ((uint16_t)(UART_LCR_H_STP2))
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
- ((STOPBITS) == UART_StopBits_2))
-/**
- * @}
- */
-
-
-/** @addtogroup UART_Mode
- * @{
- */
-
-#define UART_Mode_Rx ((uint16_t)(UART_CR_RXE))
-#define UART_Mode_Tx ((uint16_t)(UART_CR_TXE))
-#define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \
- ((MODE) == UART_Mode_Tx))
-
-/**
- * @}
- */
-
-
-/** @addtogroup UART_Hardware_Flow_Control
- * @{
- */
-
-#define UART_HardwareFlowControl_None ((uint16_t)0x0000)
-#define UART_HardwareFlowControl_RTS ((uint16_t)UART_CR_RTSEn)
-#define UART_HardwareFlowControl_CTS ((uint16_t)UART_CR_CTSEn)
-#define UART_HardwareFlowControl_RTS_CTS ((uint16_t)(UART_CR_RTSEn | UART_CR_CTSEn))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) \
- (((CONTROL) == UART_HardwareFlowControl_None) || \
- ((CONTROL) == UART_HardwareFlowControl_RTS) || \
- ((CONTROL) == UART_HardwareFlowControl_CTS) || \
- ((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
-/**
- * @}
- */
-
-
-/** @addtogroup UART_Receive Status
- * @{
- */
-
-#define UART_RECV_STATUS_OE ((uint16_t)0x01UL << 3) /*!< Overrun error */
-#define UART_RECV_STATUS_BE ((uint16_t)0x01UL << 2) /*!< Break error */
-#define UART_RECV_STATUS_PE ((uint16_t)0x01UL << 1) /*!< Parity error */
-#define UART_RECV_STATUS_FE ((uint16_t)0x01UL << 0) /*!< Framing error */
-#define IS_UART_RECV_STATUS(FLAG) (((FLAG) == UART_RECV_STATUS_OE) || ((FLAG) == UART_RECV_STATUS_BE) || \
- ((FLAG) == UART_RECV_STATUS_PE) || ((FLAG) == UART_RECV_STATUS_FE))
-/**
- * @}
- */
-
-
-
-/** @addtogroup UART_Flags
- * @{
- */
-
-#define UART_FLAG_RI ((uint16_t)0x01UL << 8) /*!< Ring indicator */
-#define UART_FLAG_TXFE ((uint16_t)0x01UL << 7) /*!< Transmit FIFO empty */
-#define UART_FLAG_RXFF ((uint16_t)0x01UL << 6) /*!< Receive FIFO full */
-#define UART_FLAG_TXFF ((uint16_t)0x01UL << 5) /*!< Transmit FIFO full */
-#define UART_FLAG_RXFE ((uint16_t)0x01UL << 4) /*!< Receive FIFO empty */
-#define UART_FLAG_BUSY ((uint16_t)0x01UL << 3) /*!< UART busy */
-#define UART_FLAG_DCD ((uint16_t)0x01UL << 2) /*!< Data carrier detect */
-#define UART_FLAG_DSR ((uint16_t)0x01UL << 1) /*!< Data set ready */
-#define UART_FLAG_CTS ((uint16_t)0x01UL << 0) /*!< Clear to send */
-#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_RI) || ((FLAG) == UART_FLAG_TXFE) || \
- ((FLAG) == UART_FLAG_RXFF) || ((FLAG) == UART_FLAG_TXFF) || \
- ((FLAG) == UART_FLAG_RXFE) || ((FLAG) == UART_FLAG_BUSY) || \
- ((FLAG) == UART_FLAG_DCD) || ((FLAG) == UART_FLAG_DSR) || \
- ((FLAG) == UART_FLAG_CTS))
-
-/**
- * @}
- */
-
-
-/** @addtogroup UART_IT_Flags
- * @{
- */
-
-#define UART_IT_FLAG_OEI ((uint16_t)0x01UL << 10) /*!< Overrun error interrupt */
-#define UART_IT_FLAG_BEI ((uint16_t)0x01UL << 9) /*!< Break error interrupt */
-#define UART_IT_FLAG_PEI ((uint16_t)0x01UL << 8) /*!< Parity error interrupt */
-#define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */
-#define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */
-#define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */
-#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */
-#define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */
-#define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */
-#define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */
-#define UART_IT_FLAG_RIMI ((uint16_t)0x01UL << 0) /*!< UARTRI modem interrupt */
-#define IS_UART_IT_FLAG(FLAG) (((FLAG) == UART_IT_FLAG_OEI) || ((FLAG) == UART_IT_FLAG_BEI) || \
- ((FLAG) == UART_IT_FLAG_PEI) || ((FLAG) == UART_IT_FLAG_FEI) || \
- ((FLAG) == UART_IT_FLAG_RTI) || ((FLAG) == UART_IT_FLAG_TXI) || \
- ((FLAG) == UART_IT_FLAG_RXI) || ((FLAG) == UART_IT_FLAG_DSRMI) || \
- ((FLAG) == UART_IT_FLAG_DCDMI)|| ((FLAG) == UART_IT_FLAG_CTSMI) || \
- ((FLAG) == UART_IT_FLAG_RIMI))
-/**
- * @}
- */
-/** @addtogroup UART_FIFO_Level Select
- * @{
- */
-
-#define UART_IFLS_RXIFLSEL7_8 ((uint16_t)(UART_IFLS_RXIFLSEL(4)))
-#define UART_IFLS_RXIFLSEL3_4 ((uint16_t)(UART_IFLS_RXIFLSEL(3)))
-#define UART_IFLS_RXIFLSEL1_2 ((uint16_t)(UART_IFLS_RXIFLSEL(2)))
-#define UART_IFLS_RXIFLSEL1_4 ((uint16_t)(UART_IFLS_RXIFLSEL(1)))
-#define UART_IFLS_RXIFLSEL1_8 ((uint16_t)(UART_IFLS_RXIFLSEL(0)))
-#define UART_IFLS_TXIFLSEL7_8 ((uint16_t)(UART_IFLS_TXIFLSEL(4)))
-#define UART_IFLS_TXIFLSEL3_4 ((uint16_t)(UART_IFLS_TXIFLSEL(3)))
-#define UART_IFLS_TXIFLSEL1_2 ((uint16_t)(UART_IFLS_TXIFLSEL(2)))
-#define UART_IFLS_TXIFLSEL1_4 ((uint16_t)(UART_IFLS_TXIFLSEL(1)))
-#define UART_IFLS_TXIFLSEL1_8 ((uint16_t)(UART_IFLS_TXIFLSEL(0)))
-
-#define IS_UART_FIFO_Level(FLAG) (((FLAG) == UART_IFLS_RXIFLSEL7_8) || ((FLAG) == UART_IFLS_RXIFLSEL3_4)|| \
- ((FLAG) == UART_IFLS_RXIFLSEL1_2)|| ((FLAG) == UART_IFLS_RXIFLSEL1_4)|| ((FLAG) == UART_IFLS_RXIFLSEL1_8)||\
- ((FLAG) == UART_IFLS_TXIFLSEL7_8)|| ((FLAG) == UART_IFLS_TXIFLSEL3_4)|| \
- ((FLAG) == UART_IFLS_TXIFLSEL1_2)|| ((FLAG) == UART_IFLS_TXIFLSEL1_4)||((FLAG) == UART_IFLS_TXIFLSEL1_8))
-
-/**
- * @}
- */
-
-/** @addtogroup S_UART_Flags
- * @{
- */
-#define S_UART_FLAG_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */
-#define S_UART_FLAG_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */
-#define S_UART_FLAG_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */
-#define S_UART_FLAG_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */
-#define IS_S_UART_FLAG(FLAG) (((FLAG) == S_UART_FLAG_RXO) || ((FLAG) == S_UART_FLAG_TXO) || \
- ((FLAG) == S_UART_FLAG_RXF) || ((FLAG) == S_UART_FLAG_TXF))
-/**
- * @}
- */
-
-
-/** @addtogroup S_UART_IT_Flags
- * @{
- */
-
-#define S_UART_IT_FLAG_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */
-#define S_UART_IT_FLAG_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */
-#define S_UART_IT_FLAG_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */
-#define S_UART_IT_FLAG_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */
-#define IS_S_UART_IT_FLAG(FLAG) (((FLAG) == S_UART_IT_FLAG_RXOI) || ((FLAG) == S_UART_IT_FLAG_TXOI) || \
- ((FLAG) == S_UART_IT_FLAG_RXI) || ((FLAG) == S_UART_IT_FLAG_TXI))
-
-/**
- * @}
- */
-
-
-void UART_StructInit (UART_InitTypeDef* UART_InitStruct);
-
-uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct);
-void UART_SendData (UART_TypeDef* UARTx, uint16_t Data);
-uint16_t UART_ReceiveData (UART_TypeDef* UARTx);
-void UART_SendBreak (UART_TypeDef* UARTx);
-void UART_ClearRecvStatus (UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS);
-FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG);
-void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState);
-ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT);
-void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT);
-
-
-void S_UART_DeInit(void);
-uint32_t S_UART_Init(uint32_t baud);
-void S_UART_SendData(uint16_t Data);
-uint16_t S_UART_ReceiveData(void);
-
-
-
-uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch);
-void UartPuts (UART_TypeDef* UARTx, uint8_t *str);
-uint8_t UartGetc (UART_TypeDef* UARTx);
-
-uint8_t S_UartPutc(uint8_t ch);
-void S_UartPuts(uint8_t *str);
-uint8_t S_UartGetc(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif // __W7500X_UART_H
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/cmsis.h Fri Sep 04 09:30:10 2015 +0100 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "W7500x.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/cmsis_nvic.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
+
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ // Return the vector
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/cmsis_nvic.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS 41
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/system_W7500x.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,104 @@
+/**************************************************************************//**
+ * @file system_CMSDK_CM0.c
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
+ * Device CMSDK
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include "system_W7500x.h"
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+//#define SYSCLK_EXTERN_OSC
+
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemFrequency = 0; /*!< System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock = 0; /*!< Processor Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint8_t M,N,OD;
+
+#ifdef SYSCLK_EXTERN_OSC
+ CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
+#else
+ CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
+#endif
+ OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
+ N = (CRG->PLL_FCR >> 8 ) & 0x3F;
+ M = (CRG->PLL_FCR >> 16) & 0x3F;
+
+#ifdef SYSCLK_EXTERN_OSC
+ SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
+#else
+ SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
+#endif
+}
+
+uint32_t GetSystemClock()
+{
+ return SystemCoreClock;
+}
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+ uint8_t M,N,OD;
+
+ (*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT)));
+ (*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC)));
+
+
+ // Set PLL input frequency
+#ifdef SYSCLK_EXTERN_OSC
+ CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
+#else
+ CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
+#endif
+ OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
+ N = (CRG->PLL_FCR >> 8 ) & 0x3F;
+ M = (CRG->PLL_FCR >> 16) & 0x3F;
+
+#ifdef SYSCLK_EXTERN_OSC
+ SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
+#else
+ SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
+#endif
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/system_W7500x.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,84 @@
+/**************************************************************************//**
+ * @file system_W7500x.h
+ * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
+ * Device W7500x
+ * @version V3.10
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_W7500x_H /* ToDo: replace '<Device>' with your device name */
+#define SYSTEM_W7500x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "W7500x.h"
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t GetSystemClock(void); /*!< Get System Clock Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define EXTERN_XTAL (8000000UL) /* External Oscillator Frequency */
+#define INTERN_XTAL (8000000UL) /* Internal Oscillator Frequency */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_W7500x_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_0 = (int)W7500x_ADC_BASE
+} ADCName;
+
+typedef enum {
+ UART_0 = (int)W7500x_UART0_BASE,
+ UART_1 = (int)W7500x_UART1_BASE
+} UARTName;
+
+
+typedef enum {
+ SPI_0 = (int)SSP0_BASE,
+ SPI_1 = (int)SSP1_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)I2C0_BASE,
+ I2C_1 = (int)I2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_0 = (int)PWM_CH0_BASE,
+ PWM_1 = (int)PWM_CH1_BASE,
+ PWM_2 = (int)PWM_CH2_BASE,
+ PWM_3 = (int)PWM_CH3_BASE,
+ PWM_4 = (int)PWM_CH4_BASE,
+ PWM_5 = (int)PWM_CH5_BASE,
+ PWM_6 = (int)PWM_CH6_BASE,
+ PWM_7 = (int)PWM_CH7_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/PortNames.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralNames.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-#include "PinNames.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- ADC_0 = (int)W7500x_ADC_BASE
-} ADCName;
-
-typedef enum {
- UART_0 = (int)W7500x_UART0_BASE,
- UART_1 = (int)W7500x_UART1_BASE
-} UARTName;
-
-#define STDIO_UART_TX PC_2
-#define STDIO_UART_RX PC_3
-#define STDIO_UART UART_1
-
-typedef enum {
- SPI_0 = (int)SSP0_BASE,
- SPI_1 = (int)SSP1_BASE
-} SPIName;
-
-typedef enum {
- I2C_0 = (int)I2C0_BASE,
- I2C_1 = (int)I2C1_BASE
-} I2CName;
-
-typedef enum {
- PWM_0 = (int)PWM_CH0_BASE,
- PWM_1 = (int)PWM_CH1_BASE,
- PWM_2 = (int)PWM_CH2_BASE,
- PWM_3 = (int)PWM_CH3_BASE,
- PWM_4 = (int)PWM_CH4_BASE,
- PWM_5 = (int)PWM_CH5_BASE,
- PWM_6 = (int)PWM_CH6_BASE,
- PWM_7 = (int)PWM_CH7_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c Fri Sep 04 08:45:09 2015 +0100
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PeripheralPins.c Fri Sep 04 09:30:10 2015 +0100
@@ -73,7 +73,7 @@
{PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
{PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
{PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
- {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
{NC, NC, 0}
};
@@ -82,32 +82,32 @@
const PinMap PinMap_SPI_SCLK[] = {
{PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
{PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
- {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
- {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
{PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
- {PC_10, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
- {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
{PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
- {PC_11, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
- {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
{PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
- {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
- {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
{NC , NC , 0}
};
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/PortNames.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h Fri Sep 04 08:45:09 2015 +0100 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device.h Fri Sep 04 09:30:10 2015 +0100 @@ -67,6 +67,11 @@ #define DEVICE_STDIO_MESSAGES 1 +#define STDIO_UART_TX PC_2 +#define STDIO_UART_RX PC_3 +#define STDIO_UART UART_1 + + #define DEVICE_ERROR_RED 0 #include "objects.h"
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/objects.h Fri Sep 04 08:45:09 2015 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,105 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-#include "PortNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- IRQn_Type irq_n;
- uint32_t event;
- PinName pin;
- uint32_t pin_index;
- uint32_t pin_num;
- uint32_t port_num;
- uint32_t rise_null;
- uint32_t fall_null;
-};
-
-struct port_s {
- PortName port;
- uint32_t mask;
- PinDirection direction;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
- ADCName adc;
- PinName pin;
-};
-
-struct serial_s {
- UARTName uart;
- int index; // Used by irq
- uint32_t baudrate;
- uint32_t databits;
- uint32_t stopbits;
- uint32_t parity;
- PinName pin_tx;
- PinName pin_rx;
-};
-
-struct spi_s {
- SSP_TypeDef *spi;
-};
-
-struct i2c_s {
- I2CName I2Cx;
- PinName sda;
- PinName scl;
- uint16_t ADDRESS;
- uint16_t is_setAddress;
-};
-
-struct pwmout_s {
- PWM_CHn_TypeDef * PWM_CHx;
- PinName pin;
- uint32_t period;
- uint32_t pulse;
- uint32_t PrescalerValue;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,55 @@
+#include "W7500x.h"
+#include "W7500x_adc.h"
+
+void ADC_PowerDownEnable (FunctionalState NewState)
+{
+ if (NewState != DISABLE) ADC->ADC_CTR = ADC_CTR_PWD_PD;
+ else ADC->ADC_CTR = ADC_CTR_PWD_NRMOP;
+}
+
+void ADC_ChannelSelect (ADC_CH num)
+{
+ assert_param(IS_ADC_CH_NUM(num));
+ ADC->ADC_CHSEL = num;
+}
+
+void ADC_Start (void)
+{
+ ADC->ADC_START = ADC_START_START;
+}
+
+uint16_t ADC_ReadData (void)
+{
+ return ((uint16_t)ADC->ADC_DATA);
+}
+
+void ADC_InterruptMask (FunctionalState NewState)
+{
+ if (NewState != DISABLE) ADC->ADC_INT = ADC_INT_MASK_ENA;
+ else ADC->ADC_INT = ADC_INT_MASK_DIS;
+}
+
+uint8_t ADC_IsInterrupt (void)
+{
+ return (((uint8_t)ADC->ADC_INT && 0x01ul));
+}
+
+void ADC_InterruptClear (void)
+{
+ ADC->ADC_INT = ADC_INTCLEAR;
+}
+
+void ADC_Init (void)
+{
+ // ADC_CLK on
+ ADC_PowerDownEnable(DISABLE);
+ //ADC_ChannelSelect(num);
+}
+
+void ADC_DeInit (void)
+{
+ // ADC_CLK off
+ ADC_PowerDownEnable(ENABLE);
+ ADC_InterruptMask(DISABLE);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,59 @@
+/**
+ ******************************************************************************
+ * @file
+ * @author
+ * @version
+ * @date
+ * @brief This file contains all the functions prototypes for the ADC
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __W7500X_ADC_H
+#define __W7500X_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "W7500x.h"
+
+typedef enum { ADC_CH0 = 0,
+ ADC_CH1 = 1,
+ ADC_CH2 = 2,
+ ADC_CH3 = 3,
+ ADC_CH4 = 4,
+ ADC_CH5 = 5,
+ ADC_CH6 = 6,
+ ADC_CH7 = 7,
+ ADC_CH15 = 15} ADC_CH;
+
+#define IS_ADC_CH_NUM(NUM) (((NUM) == ADC_CH0) || \
+ ((NUM) == ADC_CH1) || \
+ ((NUM) == ADC_CH2) || \
+ ((NUM) == ADC_CH3) || \
+ ((NUM) == ADC_CH4) || \
+ ((NUM) == ADC_CH5) || \
+ ((NUM) == ADC_CH6) || \
+ ((NUM) == ADC_CH7) || \
+ ((NUM) == ADC_CH15))
+
+void ADC_Init(void);
+void ADC_DeInit(void);
+void ADC_PowerDownEnable (FunctionalState NewState);
+void ADC_ChannelSelect (ADC_CH num);
+void ADC_Start (void);
+uint16_t ADC_ReadData (void);
+void ADC_InterruptMask (FunctionalState NewState);
+uint8_t ADC_IsInterrupt (void);
+void ADC_InterruptClear (void);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif //__W7500X_ADC_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_conf.h Fri Sep 04 09:30:10 2015 +0100 @@ -0,0 +1,16 @@ +#include "W7500x_gpio.h" +#include "W7500x_exti.h" +#include "W7500x_pwm.h" +#include "W7500x_uart.h" +#include "W7500x_i2c.h" +#include "W7500x_adc.h" +#include "W7500x_dualtimer.h" +#include "system_W7500x.h" + + +#ifdef USE_FULL_ASSERT + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__)) +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,276 @@
+#include "W7500x_crg.h"
+
+void CRG_DeInit(void)
+{
+//To Do
+}
+
+void CRG_OSC_PowerDownEnable(FunctionalState NewState)
+{
+ if(NewState != DISABLE) CRG->OSC_PDR = CRG_OSC_PDR_PD;
+ else CRG->OSC_PDR = CRG_OSC_PDR_NRMLOP;
+}
+
+void CRG_PLL_PowerDownEnable(FunctionalState NewState)
+{
+ if(NewState != DISABLE) CRG->PLL_PDR = CRG_PLL_PDR_PD;
+ else CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP;
+}
+
+void CRG_PLL_OutputEnable(FunctionalState NewState)
+{
+ if(NewState != DISABLE) CRG->PLL_OER = CRG_PLL_OER_EN;
+ else CRG->PLL_OER = CRG_PLL_OER_DIS;
+}
+
+void CRG_PLL_BypassEnable(FunctionalState NewState)
+{
+ if(NewState != DISABLE) CRG->PLL_BPR = CRG_PLL_BPR_EN;
+ else CRG->PLL_BPR = CRG_PLL_BPR_DIS;
+}
+
+void CRG_PLL_InputFrequencySelect(CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_PLL_SRC(src));
+
+ if( src == CRG_RCLK ) CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
+ else CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
+}
+
+void CRG_FCLK_SourceSelect(CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_FCLK_SRC(src));
+
+ if ( src == CRG_RCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_RCLK;
+ else if ( src == CRG_OCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_OCLK;
+ else CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK;
+}
+
+void CRG_FCLK_SetPrescale(CRG_PREDIV prediv)
+{
+ assert_param(IS_CRG_FCLK_PREDIV(prediv));
+
+ if ( prediv == CRG_PREDIV1 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1;
+ else if ( prediv == CRG_PREDIV2 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV2;
+ else if ( prediv == CRG_PREDIV4 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV4;
+ else CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV8;
+}
+
+void CRG_SSPCLK_SourceSelect(CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_SSPCLK_SRC(src));
+
+ if ( src == CRG_CLK_DIS ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS;
+ else if ( src == CRG_MCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK;
+ else if ( src == CRG_RCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_RCLK;
+ else CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_OCLK;
+}
+
+void CRG_SSPCLK_SetPrescale(CRG_PREDIV prediv)
+{
+ assert_param(IS_CRG_SSPCLK_PREDIV(prediv));
+
+ if ( prediv == CRG_PREDIV1 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1;
+ else if ( prediv == CRG_PREDIV2 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV2;
+ else if ( prediv == CRG_PREDIV4 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV4;
+ else CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV8;
+}
+
+void CRG_ADCCLK_SourceSelect(CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_ADCCLK_SRC(src));
+
+ if ( src == CRG_CLK_DIS ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS;
+ else if ( src == CRG_MCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_MCLK;
+ else if ( src == CRG_RCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_RCLK;
+ else CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_OCLK;
+}
+
+void CRG_ADCCLK_SetPrescale(CRG_PREDIV prediv)
+{
+ assert_param(IS_CRG_ADCCLK_PREDIV(prediv));
+
+ if ( prediv == CRG_PREDIV1 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1;
+ else if ( prediv == CRG_PREDIV2 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV2;
+ else if ( prediv == CRG_PREDIV4 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV4;
+ else CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV8;
+}
+
+void CRG_TIMERCLK_SourceSelect(CRG_TIMER num, CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_TIMERCLK_NUM(num));
+ assert_param(IS_CRG_TIMERCLK_SRC(src));
+
+ if ( src == CRG_CLK_DIS ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_DIS);
+ else if ( src == CRG_MCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_MCLK);
+ else if ( src == CRG_RCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_RCLK);
+ else CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_OCLK);
+}
+
+void CRG_TIMERCLK_SetPrescale(CRG_TIMER num, CRG_PREDIV prediv)
+{
+ assert_param(IS_CRG_TIMERCLK_NUM(num));
+ assert_param(IS_CRG_TIMERCLK_PREDIV(prediv));
+
+ if ( prediv == CRG_PREDIV1 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV1);
+ else if ( prediv == CRG_PREDIV2 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV2);
+ else if ( prediv == CRG_PREDIV4 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV4);
+ else if ( prediv == CRG_PREDIV8 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV8);
+ else if ( prediv == CRG_PREDIV16 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV16);
+ else if ( prediv == CRG_PREDIV32 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV32);
+ else if ( prediv == CRG_PREDIV64 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV64);
+ else CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV128);
+}
+
+void CRG_PWMCLK_SourceSelect(CRG_PWM num, CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_PWMCLK_NUM(num));
+ assert_param(IS_CRG_PWMCLK_SRC(src));
+
+ if ( src == CRG_CLK_DIS ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_DIS);
+ else if ( src == CRG_MCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_MCLK);
+ else if ( src == CRG_RCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_RCLK);
+ else CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_OCLK);
+}
+
+void CRG_PWMCLK_SetPrescale(CRG_PWM num, CRG_PREDIV prediv)
+{
+ assert_param(IS_CRG_PWMCLK_NUM(num));
+ assert_param(IS_CRG_PWMCLK_PREDIV(prediv));
+
+ if ( prediv == CRG_PREDIV1 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV1);
+ else if ( prediv == CRG_PREDIV2 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV2);
+ else if ( prediv == CRG_PREDIV4 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV4);
+ else if ( prediv == CRG_PREDIV8 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV8);
+ else if ( prediv == CRG_PREDIV16 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV16);
+ else if ( prediv == CRG_PREDIV32 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV32);
+ else if ( prediv == CRG_PREDIV64 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV64);
+ else CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV128);
+}
+
+void CRG_RTC_HS_SourceSelect(CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_RTC_HS_SRC(src));
+
+ if ( src == CRG_CLK_DIS ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_DIS;
+ else if ( src == CRG_MCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_MCLK;
+ else if ( src == CRG_RCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_RCLK;
+ else CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_OCLK;
+
+ if ( src != CRG_CLK_DIS ) CRG_RTC_SourceSelect(CRG_CLK_HIGH);
+}
+
+void CRG_RTC_HS_SetPrescale(CRG_PREDIV prediv)
+{
+ assert_param(IS_CRG_RTC_HS_PREDIV(prediv));
+
+ if ( prediv == CRG_PREDIV1 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV1;
+ else if ( prediv == CRG_PREDIV2 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV2;
+ else if ( prediv == CRG_PREDIV4 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV4;
+ else if ( prediv == CRG_PREDIV8 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV8;
+ else if ( prediv == CRG_PREDIV16 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV16;
+ else if ( prediv == CRG_PREDIV32 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV32;
+ else if ( prediv == CRG_PREDIV64 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV64;
+ else CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV128;
+}
+
+void CRG_RTC_SourceSelect(CRG_CLK_LOW_SOURCE src)
+{
+ assert_param(IS_CRG_RTC_LOW_SRC(src));
+
+ if (src == CRG_CLK_LOW)
+ {
+ CRG_RTC_HS_SourceSelect(CRG_CLK_DIS);
+ CRG->RTC_SSR = CRG_RTC_SSR_LW;
+ }
+ else
+ {
+ CRG->RTC_SSR = CRG_RTC_SSR_HS;
+ }
+}
+
+void CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_WDOGCLK_HS_SRC(src));
+
+ if ( src == CRG_CLK_DIS ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_DIS;
+ else if ( src == CRG_MCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_MCLK;
+ else if ( src == CRG_RCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_RCLK;
+ else CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_OCLK;
+
+ if ( src != CRG_CLK_DIS ) CRG_WDOGCLK_SourceSelect(CRG_CLK_HIGH);
+}
+
+void CRG_WDOGCLK_HS_SetPrescale(CRG_PREDIV prediv)
+{
+ assert_param(IS_CRG_WDOGCLK_HS_PREDIV(prediv));
+
+ if ( prediv == CRG_PREDIV1 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV1;
+ else if ( prediv == CRG_PREDIV2 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV2;
+ else if ( prediv == CRG_PREDIV4 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV4;
+ else if ( prediv == CRG_PREDIV8 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV8;
+ else if ( prediv == CRG_PREDIV16 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV16;
+ else if ( prediv == CRG_PREDIV32 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV32;
+ else if ( prediv == CRG_PREDIV64 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV64;
+ else CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV128;
+}
+
+void CRG_WDOGCLK_SourceSelect(CRG_CLK_LOW_SOURCE src)
+{
+ assert_param(IS_CRG_WDOGCLK_LOW_SRC(src));
+
+ if (src == CRG_CLK_LOW)
+ {
+ CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_DIS);
+ CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_LW;
+ }
+ else
+ {
+ CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_HS;
+ }
+}
+
+void CRG_UARTCLK_SourceSelect(CRG_CLK_SOURCE src)
+{
+ assert_param(IS_CRG_UARTCLK_SRC(src));
+
+ if ( src == CRG_CLK_DIS ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_DIS;
+ else if ( src == CRG_MCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK;
+ else if ( src == CRG_RCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK;
+ else CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK;
+}
+
+void CRG_UARTCLK_SetPrescale(CRG_PREDIV prediv)
+{
+ assert_param(IS_CRG_UARTCLK_PREDIV(prediv));
+
+ if ( prediv == CRG_PREDIV1 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1;
+ else if ( prediv == CRG_PREDIV2 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV2;
+ else if ( prediv == CRG_PREDIV4 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV4;
+ else CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV8;
+}
+
+void CRG_MII_Enable(FunctionalState rx_clk, FunctionalState tx_clk)
+{
+ assert_param(IS_FUNCTIONAL_STATE(rx_clk));
+ assert_param(IS_FUNCTIONAL_STATE(tx_clk));
+
+ if ( rx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_RXCLK;
+ else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_RXCLK);
+
+ if ( tx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_TXCLK;
+ else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_TXCLK);
+}
+
+void CRG_SetMonitoringClock(uint32_t value)
+{
+ assert_param(IS_CRG_MONCLK_SSR(value));
+
+ CRG->MONCLK_SSR = value;
+}
+
+uint32_t CRG_GetMonitoringClock(void)
+{
+ return (uint8_t)CRG->MONCLK_SSR;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,145 @@
+/**
+ ******************************************************************************
+ * @file
+ * @author
+ * @version
+ * @date
+ * @brief This file contains all the functions prototypes for the Clock Reset Generator
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __W7500X_CRG_H
+#define __W7500X_CRG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "W7500x.h"
+
+// It will be in W7500x_crg.h
+typedef enum { CRG_CLK_DIS = 0, CRG_MCLK, CRG_RCLK, CRG_OCLK } CRG_CLK_SOURCE;
+typedef enum { CRG_CLK_HIGH = 0, CRG_CLK_LOW } CRG_CLK_LOW_SOURCE;
+typedef enum { CRG_PREDIV1 = 0, CRG_PREDIV2, CRG_PREDIV4, CRG_PREDIV8, CRG_PREDIV16, \
+ CRG_PREDIV32, CRG_PREDIV64, CRG_PREDIV128 } CRG_PREDIV;
+typedef enum { CRG_TIMER0 = 0, CRG_TIMER1 } CRG_TIMER;
+typedef enum { CRG_PWM0 = 0, CRG_PWM1, CRG_PWM2, CRG_PWM3, CRG_PWM4, CRG_PWM5, CRG_PWM6, CRG_PWM7 } CRG_PWM;
+
+
+
+#define IS_CRG_PLL_SRC(SRC) (((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
+#define IS_CRG_FCLK_SRC(SRC) (((SRC) == CRG_MCLK) || ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
+
+#define CRG_CLK_SRC_DEFAULT(SRC) (((SRC) == CRG_CLK_DIS) || ((SRC) == CRG_MCLK) || \
+ ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
+#define CRG_CLK_SRC_LOW(SRC) (((SRC) == CRG_CLK_HIGH) || ((SRC) == CRG_CLK_LOW))
+
+#define CRG_CLK_PREDIV_DEFAULT(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
+ ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8))
+#define CRG_CLK_PREDIV_ADVANCE(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
+ ((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8) || \
+ ((DIV) == CRG_PREDIV16) || ((DIV) == CRG_PREDIV32) || \
+ ((DIV) == CRG_PREDIV64) || ((DIV) == CRG_PREDIV128))
+
+
+#define IS_CRG_FCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
+
+#define IS_CRG_SSPCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
+#define IS_CRG_SSPCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
+
+#define IS_CRG_ADCCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
+#define IS_CRG_ADCCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
+
+
+
+
+
+#define IS_CRG_TIMERCLK_NUM(NUM) (((NUM) == CRG_TIMER0) || ((NUM) == CRG_TIMER1))
+#define IS_CRG_TIMERCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
+#define IS_CRG_TIMERCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
+
+#define CRG_SET_TIMERCLK_SSR(NUM,VALUE) \
+ (*((volatile uint32_t *)(CRG->TIMER0CLK_SSR) + (0x10ul * NUM)) = VALUE)
+#define CRG_SET_TIMERCLK_PREDIV(NUM,VALUE) \
+ (*((volatile uint32_t *)(CRG->TIMER0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
+//#define CRG_SET_TIMERCLK_SSR(num,value) CRG->TIMER##num##CLK_SSR = value
+//#define CRG_SET_TIMERCLK_PREDIV(num,value) CRG->TIMER##num##CLK_PVSR = value
+
+
+#define IS_CRG_PWMCLK_NUM(NUM) (((NUM) == CRG_PWM0) || ((NUM) == CRG_PWM1) || \
+ ((NUM) == CRG_PWM2) || ((NUM) == CRG_PWM3) || \
+ ((NUM) == CRG_PWM4) || ((NUM) == CRG_PWM5) || \
+ ((NUM) == CRG_PWM6) || ((NUM) == CRG_PWM7) )
+#define IS_CRG_PWMCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
+#define IS_CRG_PWMCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
+
+#define CRG_SET_PWMCLK_SSR(NUM,VALUE) \
+ (*((volatile uint32_t *)(CRG->PWM0CLK_SSR) + (0x10ul * NUM)) = VALUE)
+#define CRG_SET_PWMCLK_PREDIV(NUM,VALUE) \
+ (*((volatile uint32_t *)(CRG->PWM0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
+//#define CRG_SET_PWMCLK_SSR(num,value) CRG->PWM##num##CLK_SSR = value
+//#define CRG_SET_PWMCLK_PREDIV(num,value) CRG->PWM##num##CLK_PVSR = value
+
+#define IS_CRG_RTC_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
+#define IS_CRG_RTC_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
+#define IS_CRG_RTC_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
+
+#define IS_CRG_WDOGCLK_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
+#define IS_CRG_WDOGCLK_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
+#define IS_CRG_WDOGCLK_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
+
+#define IS_CRG_UARTCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
+#define IS_CRG_UARTCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
+
+#define IS_CRG_MONCLK_SSR(value) (((value) >= 0x00ul) || ((value) <= 0x13ul))
+
+void CRG_DeInit(void);
+void CRG_OSC_PowerDownEnable (FunctionalState NewState);
+void CRG_PLL_PowerDownEnable (FunctionalState NewState);
+void CRG_PLL_OutputEnable (FunctionalState NewState);
+void CRG_PLL_BypassEnable (FunctionalState NewState);
+void CRG_PLL_InputFrequencySelect (CRG_CLK_SOURCE src);
+
+void CRG_FCLK_SourceSelect (CRG_CLK_SOURCE src);
+void CRG_FCLK_SetPrescale (CRG_PREDIV prediv);
+
+void CRG_SSPCLK_SourceSelect (CRG_CLK_SOURCE src);
+void CRG_SSPCLK_SetPrescale (CRG_PREDIV prediv);
+
+void CRG_ADCCLK_SourceSelect (CRG_CLK_SOURCE src);
+void CRG_ADCCLK_SetPrescale (CRG_PREDIV prediv);
+
+void CRG_TIMERCLK_SourceSelect (CRG_TIMER num, CRG_CLK_SOURCE src);
+void CRG_TIMERCLK_SetPrescale (CRG_TIMER num, CRG_PREDIV prediv);
+
+void CRG_PWMCLK_SourceSelect (CRG_PWM num, CRG_CLK_SOURCE src);
+void CRG_PWMCLK_SetPrescale (CRG_PWM num, CRG_PREDIV prediv);
+
+void CRG_RTC_HS_SourceSelect (CRG_CLK_SOURCE src);
+void CRG_RTC_HS_SetPrescale (CRG_PREDIV prediv);
+void CRG_RTC_SourceSelect (CRG_CLK_LOW_SOURCE src);
+
+void CRG_WDOGCLK_HS_SourceSelect (CRG_CLK_SOURCE src);
+void CRG_WDOGCLK_HS_SetPrescale (CRG_PREDIV prediv);
+void CRG_WDOGCLK_SourceSelect (CRG_CLK_LOW_SOURCE src);
+
+void CRG_UARTCLK_SourceSelect (CRG_CLK_SOURCE src);
+void CRG_UARTCLK_SetPrescale (CRG_PREDIV prediv);
+
+void CRG_MII_Enable (FunctionalState rx_clk, FunctionalState tx_clk);
+
+void CRG_SetMonitoringClock (uint32_t value);
+uint32_t CRG_GetMonitoringClock (void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_dualtimer.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,206 @@
+/**
+ ******************************************************************************
+ * @file W7500x_stdPeriph_Driver/src/W7500x_dualtimer.c
+ * @author IOP Team
+ * @version v1.0.0
+ * @date 01-May-2015
+ * @brief This file contains all the functions prototypes for the dualtimer
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Includes -------------------------------------------*/
+#include "W7500x.h"
+#include "W7500x_dualtimer.h"
+
+void DUALTIMER_ClockEnable(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ if(DUALTIMERn == DUALTIMER0_0)
+ TIMCLKEN0_0 = DUALTIMER_Clock_Enable;
+ else if(DUALTIMERn == DUALTIMER0_1)
+ TIMCLKEN0_1 = DUALTIMER_Clock_Enable;
+ else if(DUALTIMERn == DUALTIMER1_0)
+ TIMCLKEN1_0 = DUALTIMER_Clock_Enable;
+ else if(DUALTIMERn == DUALTIMER1_1)
+ TIMCLKEN1_1 = DUALTIMER_Clock_Enable;
+}
+
+void DUALTIMER_ClockDisable(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ if(DUALTIMERn == DUALTIMER0_0)
+ TIMCLKEN0_0 = DUALTIMER_Clock_Disable;
+ else if(DUALTIMERn == DUALTIMER0_1)
+ TIMCLKEN0_1 = DUALTIMER_Clock_Disable;
+ else if(DUALTIMERn == DUALTIMER1_0)
+ TIMCLKEN1_0 = DUALTIMER_Clock_Disable;
+ else if(DUALTIMERn == DUALTIMER1_1)
+ TIMCLKEN1_1 = DUALTIMER_Clock_Disable;
+}
+
+void DUALTIMER_DeInit(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ DUALTIMER_Stop(DUALTIMERn);
+
+ DUALTIMERn->TimerLoad = 0x0;
+ DUALTIMERn->TimerControl = 0x20;
+ DUALTIMERn->TimerBGLoad = 0x0;
+}
+
+void DUALTIMER_Init(DUALTIMER_TypeDef* DUALTIMERn, DUALTIMER_InitTypDef* DUALTIMER_InitStruct)
+{
+ uint32_t tmp = 0;
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+ assert_param(IS_DUALTIMER_TimerMode(DUALTIMER_InitStruct->TimerControl_Mode));
+ assert_param(IS_DUALTIMER_TimerPre(DUALTIMER_InitStruct->TimerControl_Pre));
+ assert_param(IS_DUALTIMER_TimerSize(DUALTIMER_InitStruct->TimerControl_Size));
+ assert_param(IS_DUALTIMER_OneShot(DUALTIMER_InitStruct->TimerControl_OneShot));
+
+ DUALTIMER_Stop(DUALTIMERn);
+
+ DUALTIMERn->TimerLoad = DUALTIMER_InitStruct->TimerLoad;
+
+ tmp = DUALTIMERn->TimerControl;
+ tmp |= (DUALTIMER_InitStruct->TimerControl_Mode << DUALTIMER_TimerControl_TimerMode_Pos);
+ tmp |= (DUALTIMER_InitStruct->TimerControl_Pre << DUALTIMER_TimerControl_Pre_Pos);
+ tmp |= (DUALTIMER_InitStruct->TimerControl_Size << DUALTIMER_TimerControl_Size_Pos);
+ tmp |= (DUALTIMER_InitStruct->TimerControl_OneShot << DUALTIMER_TimerControl_OneShot_Pos);
+ //Reset values not used
+ tmp &= 0xEF;
+
+ DUALTIMERn->TimerControl = tmp;
+}
+
+void DUALTIMER_IntConfig(DUALTIMER_TypeDef* DUALTIMERn, FunctionalState state)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ if(state == ENABLE)
+ DUALTIMERn->TimerControl |= (DUALTIMER_TimerControl_IntEnable << DUALTIMER_TimerControl_IntEnable_Pos);
+ else
+ DUALTIMERn->TimerControl &= ~(DUALTIMER_TimerControl_IntEnable << DUALTIMER_TimerControl_IntEnable_Pos);
+}
+
+void DUALTIMER_IntClear(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ DUALTIMERn->TimerIntClr = DUALTIMER_Int_Clear;
+}
+
+ITStatus DUALTIMER_GetIntStatus(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ return (ITStatus)DUALTIMERn->TimerMIS;
+}
+
+FlagStatus DUALTIMER_GetIntEnableStatus(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ return (FlagStatus)((DUALTIMERn->TimerControl >> DUALTIMER_TimerControl_IntEnable_Pos) & 0x1);
+}
+
+void DUALTIMER_Start(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ DUALTIMERn->TimerControl |= (DUALTIMER_TimerControl_TimerEnable << DUALTIMER_TimerControl_TimerEnable_Pos);
+}
+
+void DUALTIMER_Stop(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ DUALTIMERn->TimerControl &= ~(DUALTIMER_TimerControl_TimerEnable << DUALTIMER_TimerControl_TimerEnable_Pos);
+}
+
+uint32_t DUALTIMER_GetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ return DUALTIMERn->TimerLoad;
+}
+
+void DUALTIMER_SetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerLoad)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ DUALTIMERn->TimerLoad = TimerLoad;
+}
+
+uint32_t DUALTIMER_GetTimerValue(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ return DUALTIMERn->TimerValue;
+}
+
+uint32_t DUALTIMER_GetTimerControl(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ return DUALTIMERn->TimerControl;
+}
+
+void DUALTIMER_SetTimerControl(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerControl)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ DUALTIMERn->TimerControl = TimerControl;
+}
+
+uint32_t DUALTIMER_GetTimerRIS(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ return DUALTIMERn->TimerRIS;
+}
+
+uint32_t DUALTIMER_GetTimerMIS(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ return DUALTIMERn->TimerMIS;
+}
+
+uint32_t DUALTIMER_GetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ return DUALTIMERn->TimerBGLoad;
+}
+
+void DUALTIMER_SetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerBGLoad)
+{
+ /* Check the parameters */
+ assert_param(IS_DUALTIMER_ALL_CH(DUALTIMERn));
+
+ DUALTIMERn->TimerBGLoad = TimerBGLoad;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_dualtimer.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,96 @@
+/**
+ ******************************************************************************
+ * @file W7500x_stdPeriph_Driver/inc/W7500x_dualtimer.h
+ * @author IOP Team
+ * @version V1.0.0
+ * @date 01-May-2015
+ * @brief This file contains all the functions prototypes for the dualtimer
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __W7500X_DUALTIMER_H
+#define __W7500X_DUALTIMER_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "W7500x.h"
+
+/**********************************************************************************************/
+/**********************************************************************************************/
+// This structure and define must be in W7500x.h
+/**********************************************************************************************/
+/**********************************************************************************************/
+
+typedef struct
+{
+ uint32_t TimerLoad;
+ uint32_t TimerControl_Mode;
+ uint32_t TimerControl_Pre;
+ uint32_t TimerControl_Size;
+ uint32_t TimerControl_OneShot;
+}DUALTIMER_InitTypDef;
+
+
+#define IS_DUALTIMER_TimerMode(MODE) (MODE <= 1)
+#define IS_DUALTIMER_TimerPre(PREE) (PRE <= 2)
+#define IS_DUALTIMER_TimerSize(SIZE) (SIZE <= 1)
+#define IS_DUALTIMER_OneShot(ONESHOT) (ONESHOT <= 1)
+
+
+
+
+
+
+#define DUALTIMER_Int_Clear 0x1ul
+
+#define DUALTIMER_Clock_Enable 0x1ul
+#define DUALTIMER_Clock_Disable ~DUALTIMER_Clock_Enable
+
+
+#define IS_DUALTIMER_ALL_CH(CH) ((CH == DUALTIMER0_0) || \
+ (CH == DUALTIMER0_1) || \
+ (CH == DUALTIMER1_0) || \
+ (CH == DUALTIMER1_1))
+
+
+
+void DUALTIMER_ClockEnable(DUALTIMER_TypeDef* DUALTIMERn);
+void DUALTIMER_ClockDisable(DUALTIMER_TypeDef* DUALTIMERn);
+void DUALTIMER_DeInit(DUALTIMER_TypeDef* DUALTIMERn);
+void DUALTIMER_Init(DUALTIMER_TypeDef* DUALTIMERn, DUALTIMER_InitTypDef* DUALTIMER_InitStruct);
+void DUALTIMER_IntConfig(DUALTIMER_TypeDef* DUALTIMERn, FunctionalState state);
+void DUALTIMER_IntClear(DUALTIMER_TypeDef* DUALTIMERn);
+ITStatus DUALTIMER_GetIntStatus(DUALTIMER_TypeDef* DUALTIMERn);
+FlagStatus DUALTIMER_GetIntEnableStatus(DUALTIMER_TypeDef* DUALTIMERn);
+void DUALTIMER_Start(DUALTIMER_TypeDef* DUALTIMERn);
+void DUALTIMER_Stop(DUALTIMER_TypeDef* DUALTIMERn);
+uint32_t DUALTIMER_GetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn);
+void DUALTIMER_SetTimerLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerLoad);
+uint32_t DUALTIMER_GetTimerValue(DUALTIMER_TypeDef* DUALTIMERn);
+uint32_t DUALTIMER_GetTimerControl(DUALTIMER_TypeDef* DUALTIMERn);
+void DUALTIMER_SetTimerControl(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerControl);
+uint32_t DUALTIMER_GetTimerRIS(DUALTIMER_TypeDef* DUALTIMERn);
+uint32_t DUALTIMER_GetTimerMIS(DUALTIMER_TypeDef* DUALTIMERn);
+uint32_t DUALTIMER_GetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn);
+void DUALTIMER_SetTimerBGLoad(DUALTIMER_TypeDef* DUALTIMERn, uint32_t TimerBGLoad);
+
+
+
+//======================= Interrupt handler ==============================
+//void DUALTIMER0_Handler();
+//void DUALTIMER1_Handler();
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+
+#endif //__W7500X_DUALTIMER_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_exti.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,158 @@
+#include "W7500x.h"
+#include "W7500x_exti.h"
+#include "W7500x_gpio.h"
+
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void EXTI_DeInit(void)
+{
+ uint32_t i, loop =16;
+ for(i=0; i<loop; i++)
+ {
+ EXTI_PA->Port[i] = 0x00;
+ EXTI_PB->Port[i] = 0x00;
+ EXTI_PC->Port[i] = 0x00;
+ }
+ for(i=0; i<5; i++)
+ {
+ EXTI_PD->Port[i] = 0x00;
+ }
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+ * that contains the configuration information for the EXTI peripheral.
+ * @retval None
+ */
+void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
+ P_Port_Def *px_exti;
+
+ assert_param(IS_PAD_TYPE(Px));
+
+ if (Px == PAD_PA) px_exti = EXTI_PA;
+ else if (Px == PAD_PB) px_exti = EXTI_PB;
+ else if (Px == PAD_PC) px_exti = EXTI_PC;
+ else
+ {
+ px_exti = (P_Port_Def*)EXTI_PD;
+ loop = 5;
+ }
+
+ for(pinpos = 0x00; pinpos < loop; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+
+ currentpin = (EXTI_InitStruct->EXTI_Line) & pos;
+ if(currentpin == pos)
+ {
+ px_exti->Port[pinpos] |= EXTI_Px_INTEN_ENABLE;
+
+ if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising)
+ px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE;
+ else
+ px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE;
+ }
+ }
+
+}
+
+void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity )
+{
+ uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
+ P_Port_Def *px_exti;
+
+ assert_param(IS_PAD_TYPE(Px));
+
+ if (Px == PAD_PA) px_exti = EXTI_PA;
+ else if (Px == PAD_PB) px_exti = EXTI_PB;
+ else if (Px == PAD_PC) px_exti = EXTI_PC;
+ else
+ {
+ px_exti = (P_Port_Def*)EXTI_PD;
+ loop = 5;
+ }
+
+ for(pinpos = 0x00; pinpos < loop; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+
+ currentpin = GPIO_Pin & pos;
+ if(currentpin == pos)
+ {
+ if(Polarity == EXTI_Trigger_Rising)
+ px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE;
+ else
+ px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE;
+ }
+ }
+
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = 0xFF;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+}
+
+uint16_t EXTI_Px_GetEXTEN(PAD_Type Px)
+{
+ uint32_t i, loop = 16;
+ uint16_t ret=0;
+ P_Port_Def *px_exti;
+
+ assert_param(IS_PAD_TYPE(Px));
+
+ if (Px == PAD_PA) px_exti = EXTI_PA;
+ else if (Px == PAD_PB) px_exti = EXTI_PB;
+ else if (Px == PAD_PC) px_exti = EXTI_PC;
+ else
+ {
+ px_exti = (P_Port_Def*)EXTI_PD;
+ loop = 5;
+ }
+
+ for(i = 0x00; i < loop; i++)
+ {
+ ret |= (((px_exti->Port[i]&0x2)>>1)<<i);
+ }
+ return ret;
+}
+
+uint16_t EXTI_Px_GetEXTINTPOL(PAD_Type Px)
+{
+ uint32_t i, loop = 16;
+ uint16_t ret=0;
+ P_Port_Def *px_exti;
+
+ assert_param(IS_PAD_TYPE(Px));
+
+ if (Px == PAD_PA) px_exti = EXTI_PA;
+ else if (Px == PAD_PB) px_exti = EXTI_PB;
+ else if (Px == PAD_PC) px_exti = EXTI_PC;
+ else
+ {
+ px_exti = (P_Port_Def*)EXTI_PD;
+ loop = 5;
+ }
+
+ for(i = 0x00; i < loop; i++)
+ {
+ ret |= ((px_exti->Port[i]&0x1)<<i);
+ }
+ return ret;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_exti.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,86 @@
+/**
+ ******************************************************************************
+ * @file
+ * @author
+ * @version
+ * @date
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __W7500X_EXTI_H
+#define __W7500X_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+ /* Includes ------------------------------------------------------------------*/
+#include "W7500x.h"
+
+
+ /**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Disable = 0x00,
+ EXTI_Mode_Interrupt = 0x02
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Rising) || \
+ ((MODE) == EXTI_Mode_Interrupt))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x00,
+ EXTI_Trigger_Falling = 0x01
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling))
+
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+}EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+void EXTI_DeInit(void);
+void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity );
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+uint32_t EXTI_GetEXTIConfig(PAD_Type Px, uint16_t GPIO_Pin);
+uint16_t EXTI_Px_GetEXTEN(PAD_Type Px);
+uint16_t EXTI_Px_GetEXTINTPOL(PAD_Type Px);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif //__W7500X_EXTI_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,297 @@
+#include "W7500x.h"
+#include "W7500x_gpio.h"
+
+void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ uint32_t i, loop =16;
+ P_Port_Def *px_pcr;
+ P_Port_Def *px_afsr;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ /* DeInit GPIOx Registers */
+ GPIOx->DATA = 0x0000;
+ GPIOx->DATAOUT = 0x0000;
+ //GPIOx->OUTENSET = 0x0000;
+ GPIOx->OUTENCLR = 0xFFFF;
+ //GPIOx->INTENSET = 0x0000;
+ GPIOx->INTENCLR = 0xFFFF;
+ //GPIOx->INTTYPESET = 0x0000;
+ GPIOx->INTTYPECLR = 0xFFFF;
+ //GPIOx->INTPOLSET = 0x0000;
+ GPIOx->INTPOLCLR = 0xFFFF;
+
+
+ /* DeInit GPIOx
+ * Pad Control Register
+ * Pad Extern interrupt Enable Register
+ * Pad Alternate Function Select Register
+ */
+ if (GPIOx == GPIOA)
+ {
+ px_pcr = PA_PCR;
+ px_afsr = PA_AFSR;
+ }
+ else if (GPIOx == GPIOB)
+ {
+ px_pcr = PB_PCR;
+ px_afsr = PB_AFSR;
+ }
+ else if (GPIOx == GPIOC)
+ {
+ px_pcr = PC_PCR;
+ px_afsr = PC_AFSR;
+ }
+ else // if (GPIOx == GPIOD)
+ {
+ px_pcr = (P_Port_Def*)PD_PCR;
+ px_afsr = (P_Port_Def*)PD_AFSR;
+ loop = 5;
+ }
+
+ for(i=0; i<loop; i++)
+ {
+ px_pcr->Port[i] = 0x60;
+ px_afsr->Port[i] = PAD_AF0;
+
+ }
+}
+
+void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
+ P_Port_Def *px_pcr;
+
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+// assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+ if (GPIOx == GPIOA) px_pcr = PA_PCR;
+ else if (GPIOx == GPIOB) px_pcr = PB_PCR;
+ else if (GPIOx == GPIOC) px_pcr = PC_PCR;
+ else
+ {
+ px_pcr = (P_Port_Def*)PD_PCR;
+ loop = 5;
+ }
+
+ for(pinpos = 0x00; pinpos < loop; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+ if(currentpin == pos)
+ {
+ if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT)
+ {
+ GPIOx->OUTENSET |= pos;
+ }
+ else // GPIO_Mode_In
+ {
+ GPIOx->OUTENCLR = pos;
+ }
+
+ // Configure pull-up pull-down bits
+ if(GPIO_InitStruct->GPIO_Pad & Px_PCR_PUPD_UP)
+ {
+ px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN);
+ px_pcr->Port[pinpos] |= Px_PCR_PUPD_UP;
+ }
+ else
+ {
+ px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN);
+ px_pcr->Port[pinpos] |= Px_PCR_PUPD_DOWN;
+ }
+
+ // Configure Driving stregnth selections bit
+ if(GPIO_InitStruct->GPIO_Pad & Px_PCR_DS_HIGH)
+ {
+ px_pcr->Port[pinpos] |= Px_PCR_DS_HIGH;
+ }
+ else
+ {
+ px_pcr->Port[pinpos] &= ~(Px_PCR_DS_HIGH);
+ }
+
+ // Configure Open Drain selections bit
+ if(GPIO_InitStruct->GPIO_Pad & Px_PCR_OD)
+ {
+ px_pcr->Port[pinpos] |= Px_PCR_OD;
+ }
+ else
+ {
+ px_pcr->Port[pinpos] &= ~(Px_PCR_OD);
+ }
+
+ // Configure Input buffer enable selection bit
+ if(GPIO_InitStruct->GPIO_Pad & Px_PCR_IE)
+ {
+ px_pcr->Port[pinpos] |= Px_PCR_IE;
+ }
+ else
+ {
+ px_pcr->Port[pinpos] &= ~(Px_PCR_IE);
+ }
+
+ // Configure input type (CMOS input or Summit trigger input) select bit
+ if(GPIO_InitStruct->GPIO_Pad & Px_PCR_CS_SUMMIT)
+ {
+ px_pcr->Port[pinpos] |= Px_PCR_CS_SUMMIT;
+ }
+ else
+ {
+ px_pcr->Port[pinpos] &= ~(Px_PCR_CS_SUMMIT);
+ }
+ }
+ }
+}
+
+void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+ GPIO_InitStruct->GPIO_Pad = (GPIOPad_TypeDef)(GPIO_PuPd_UP);
+}
+
+
+uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if((GPIOx->DATA & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+
+ return bitstatus;
+}
+
+uint16_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ return ((uint16_t)GPIOx->DATA);
+}
+
+uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+
+
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if((GPIOx->DATAOUT & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+
+ return bitstatus;
+}
+uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALLPERIPH(GPIOx));
+ return ((uint16_t)GPIOx->DATAOUT);
+}
+
+void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = GPIO_Pin;
+ (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = GPIO_Pin;
+}
+
+void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = ~(GPIO_Pin);
+ (GPIOx->UB_MASKED[(uint8_t)(GPIO_Pin>>8)]) = ~(GPIO_Pin);
+}
+
+void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ (GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = BitVal;
+ (GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = BitVal;
+}
+
+void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->DATAOUT = PortVal;
+}
+
+void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF)
+{
+ int i;
+ uint16_t idx =0x1;
+ assert_param(IS_PAD_Type(Px));
+
+ for(i=0;i<16;i++)
+ {
+ if(GPIO_Pin & (idx<<i))
+ {
+ if(Px == PAD_PA)
+ {
+ assert_param(IS_PA_NUM(i));
+ PA_AFSR->Port[i] &= ~(0x03ul);
+ PA_AFSR->Port[i] |= P_AF;
+ }
+ else if(Px == PAD_PB)
+ {
+ assert_param(IS_PB_NUM(i));
+ PB_AFSR->Port[i] &= ~(0x03ul);
+ PB_AFSR->Port[i] |= P_AF;
+ }
+ else if(Px == PAD_PC)
+ {
+ assert_param(IS_PC_NUM(i));
+ PC_AFSR->Port[i] &= ~(0x03ul);
+ PC_AFSR->Port[i] |= P_AF;
+ }
+ else
+ {
+ assert_param(IS_PD_NUM(i));
+ PD_AFSR->Port[i] &= ~(0x03ul);
+ PD_AFSR->Port[i] |= P_AF;
+ }
+ }
+ }
+}
+
+void GPIO_OutEnClr(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIOx->OUTENCLR = GPIO_Pin;
+}
+
+void GPIO_OutEnSet(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIOx->OUTENSET = GPIO_Pin;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,122 @@
+/**
+ ******************************************************************************
+ * @file
+ * @author
+ * @version
+ * @date
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __W7500X_HAL_GPIO_H
+#define __W7500X_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "W7500x.h"
+
+#define GPIO_Pin_0 (uint16_t)(0x01 << 0) // Pin 0 Selected
+#define GPIO_Pin_1 (uint16_t)(0x01 << 1) // Pin 1 Selected
+#define GPIO_Pin_2 (uint16_t)(0x01 << 2) // Pin 2 Selected
+#define GPIO_Pin_3 (uint16_t)(0x01 << 3) // Pin 3 Selected
+#define GPIO_Pin_4 (uint16_t)(0x01 << 4) // Pin 4 Selected
+#define GPIO_Pin_5 (uint16_t)(0x01 << 5) // Pin 5 Selected
+#define GPIO_Pin_6 (uint16_t)(0x01 << 6) // Pin 6 Selected
+#define GPIO_Pin_7 (uint16_t)(0x01 << 7) // Pin 7 Selected
+#define GPIO_Pin_8 (uint16_t)(0x01 << 8) // Pin 8 Selected
+#define GPIO_Pin_9 (uint16_t)(0x01 << 9) // Pin 9 Selected
+#define GPIO_Pin_10 (uint16_t)(0x01 << 10) // Pin 10 Selected
+#define GPIO_Pin_11 (uint16_t)(0x01 << 11) // Pin 11 Selected
+#define GPIO_Pin_12 (uint16_t)(0x01 << 12) // Pin 12 Selected
+#define GPIO_Pin_13 (uint16_t)(0x01 << 13) // Pin 13 Selected
+#define GPIO_Pin_14 (uint16_t)(0x01 << 14) // Pin 14 Selected
+#define GPIO_Pin_15 (uint16_t)(0x01 << 15) // Pin 15 Selected
+#define GPIO_Pin_All (uint16_t)(0xFFFF) // All pins Selected
+
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || \
+ (((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || \
+ (((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || \
+ (((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || \
+ (((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || \
+ (((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || \
+ (((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || \
+ (((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15) )
+
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) )
+
+typedef enum
+{
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
+ GPIO_Mode_AF = 0x02 /*!< GPIO Alternate function Mode */
+}GPIOMode_TypeDef;
+
+typedef enum
+{
+ GPIO_NO_PUPD = 0x0ul,
+ GPIO_PuPd_UP = Px_PCR_PUPD_UP,
+ GPIO_PuPd_DOWN = Px_PCR_PUPD_DOWN,
+ GPIO_PuPd_Default = 0x0ul,
+}GPIOPad_TypeDef;
+
+typedef struct
+{
+ uint32_t GPIO_Pin;
+ GPIOMode_TypeDef GPIO_Mode;
+ GPIOPad_TypeDef GPIO_Pad;
+}GPIO_InitTypeDef;
+
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+
+#define IS_PAD_TYPE(Px) (((Px) == PAD_PA) || ((Px) == PAD_PB) \
+ ((Px) == PAD_PC) || ((Px) == PAD_PD))
+
+#define IS_PA_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
+#define IS_PB_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
+#define IS_PC_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
+#define IS_PD_NUM(NUM) (((NUM)>=0) && ((NUM)< 5))
+
+#define IS_PAD_AF(AF) (((AF) == PAD_AF0) || ((AF) == PAD_AF1) || \
+ ((AF) == PAD_AF2) || ((AF) == PAD_AF3))
+
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION_ == Bit_RESET) || (ACTION) ==Bit_SET))
+
+void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void HAL_PAD_AFConfig(PAD_Type Px, uint16_t Pnum, PAD_AF_TypeDef P_AF);
+
+void GPIO_OutEnClr(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_OutEnSet(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __W7500X_HAL_GPIO_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_i2c.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,288 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+/*include -------------------------------------*/
+#include "W7500x.h"
+#include "W7500x_i2c.h"
+#include "W7500x_gpio.h"
+
+GPIO_InitTypeDef GPIO_InitDef;
+
+uint32_t I2C_Init(I2C_ConfigStruct* conf)
+{
+ uint32_t scl_port_num;
+ uint32_t scl_pin_index;
+ uint32_t sda_port_num;
+ uint32_t sda_pin_index;
+
+ scl_port_num = I2C_PORT(conf->scl);
+ scl_pin_index = I2C_PIN_INDEX(conf->scl);
+
+ sda_port_num = I2C_PORT(conf->sda);
+ sda_pin_index = I2C_PIN_INDEX(conf->sda);
+
+ //SCL setting
+ GPIO_InitDef.GPIO_Pin = scl_pin_index;
+ GPIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
+
+ HAL_GPIO_Init((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), &GPIO_InitDef);
+ HAL_GPIO_SetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
+
+ //SDA setting
+ GPIO_InitDef.GPIO_Pin = sda_pin_index;
+ GPIO_InitDef.GPIO_Mode = GPIO_Mode_IN;
+
+ HAL_GPIO_Init((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), &GPIO_InitDef);
+ HAL_GPIO_ResetBits((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
+
+ //Pin muxing
+ HAL_PAD_AFConfig((PAD_Type)scl_port_num, (uint16_t)scl_pin_index, PAD_AF1);
+ HAL_PAD_AFConfig((PAD_Type)sda_port_num, (uint16_t)sda_pin_index, PAD_AF1);
+
+ return 0;
+}
+
+void I2C_WriteBitSCL(I2C_ConfigStruct* conf, uint8_t data)
+{
+ uint32_t scl_port_num = I2C_PORT(conf->scl);
+ uint32_t scl_pin_index = I2C_PIN_INDEX(conf->scl);
+
+ if(data == 1)
+ HAL_GPIO_SetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
+ else
+ HAL_GPIO_ResetBits((GPIO_TypeDef*)(GPIOA_BASE + (scl_port_num << 24)), scl_pin_index);
+
+}
+
+void I2C_WriteBitSDA(I2C_ConfigStruct* conf, uint8_t data)
+{
+ uint32_t sda_port_num = I2C_PORT(conf->sda);
+ uint32_t sda_pin_index = I2C_PIN_INDEX(conf->sda);
+
+ if(data == 1)
+ GPIO_OutEnClr((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
+ else
+ GPIO_OutEnSet((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index);
+
+}
+
+uint8_t I2C_ReadBitSDA(I2C_ConfigStruct* conf)
+{
+ uint32_t sda_port_num = I2C_PORT(conf->sda);
+ uint32_t sda_pin_index = I2C_PIN_INDEX(conf->sda);
+
+ if(HAL_GPIO_ReadInputDataBit((GPIO_TypeDef*)(GPIOA_BASE + (sda_port_num << 24)), sda_pin_index))
+ return 1;
+
+ return 0;
+}
+
+void I2C_Start(I2C_ConfigStruct* conf)
+{
+ I2C_WriteBitSCL(conf, 1);
+ I2C_WriteBitSDA(conf, 1);
+
+ I2C_WriteBitSDA(conf, 0);
+ I2C_WriteBitSCL(conf, 0);
+}
+
+void I2C_Stop(I2C_ConfigStruct* conf)
+{
+ I2C_WriteBitSCL(conf, 0);
+ I2C_WriteBitSDA(conf, 0);
+
+ I2C_WriteBitSCL(conf, 1);
+ I2C_WriteBitSDA(conf, 1);
+}
+
+uint8_t I2C_WriteByte(I2C_ConfigStruct* conf, uint8_t data)
+{
+ int i;
+ uint8_t ret;
+
+ //Write byte
+ for(i=0; i<8; i++)
+ {
+ if((data << i) & 0x80)
+ I2C_WriteBitSDA(conf, 1);
+ else
+ I2C_WriteBitSDA(conf, 0);
+
+ I2C_WriteBitSCL(conf, 1);
+ I2C_WriteBitSCL(conf, 0);
+ }
+ //Make clk for receiving ack
+ I2C_WriteBitSDA(conf, 1);
+ I2C_WriteBitSCL(conf, 1);
+ //Read Ack/Nack
+ ret = I2C_ReadBitSDA(conf);
+
+ I2C_WriteBitSCL(conf, 0);
+
+ return ret;
+}
+
+void I2C_SendACK(I2C_ConfigStruct* conf)
+{
+ I2C_WriteBitSDA(conf, 0);
+ I2C_WriteBitSCL(conf, 1);
+
+ I2C_WriteBitSCL(conf, 0);
+}
+
+void I2C_SendNACK(I2C_ConfigStruct* conf)
+{
+ I2C_WriteBitSDA(conf, 1);
+ I2C_WriteBitSCL(conf, 1);
+
+ I2C_WriteBitSCL(conf, 0);
+}
+
+uint8_t I2C_ReadByte(I2C_ConfigStruct* conf)
+{
+ int i;
+ uint8_t ret = 0;
+
+ I2C_WriteBitSDA(conf, 1); //out enable clear(GPIO is input)
+
+ //Read byte
+ for(i=0; i<8; i++)
+ {
+ I2C_WriteBitSCL(conf, 1);
+ ret = (ret << 1) | (I2C_ReadBitSDA(conf));
+ I2C_WriteBitSCL(conf, 0);
+ }
+
+ return ret;
+}
+
+int I2C_Write(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
+{
+ int i;
+
+ I2C_Start(conf);
+
+ //Write addr
+ if(I2C_WriteByte(conf, addr) != 0)
+ {
+ //printf("Received NACK at address phase!!\r\n");
+ return -1;
+ }
+
+ //Write data
+ for(i=0; i<len; i++)
+ {
+ if(I2C_WriteByte(conf, data[i]))
+ return -1;
+ }
+
+ I2C_Stop(conf);
+
+ return 0;//success
+}
+
+int I2C_WriteRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
+{
+ int i;
+
+ I2C_Start(conf);
+
+ //Write addr
+ if(I2C_WriteByte(conf, addr) != 0)
+ {
+ //printf("Received NACK at address phase!!\r\n");
+ return -1;
+ }
+
+ //Write data
+ for(i=0; i<len; i++)
+ {
+ if(I2C_WriteByte(conf, data[i]))
+ return -1;
+ }
+
+ return 0;//success
+}
+
+int I2C_Read(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
+{
+ int i;
+
+ I2C_Start(conf);
+
+ //Write addr | read command
+ if(I2C_WriteByte(conf, (addr | 1)) != 0)
+ {
+ //printf("Received NACK at address phase!!\r\n");
+ return -1;
+ }
+
+ //Read data
+ for(i=0; i<len; i++)
+ {
+ data[i] = I2C_ReadByte(conf);
+
+ if( i == (len - 1) )
+ I2C_SendNACK(conf);
+ else
+ I2C_SendACK(conf);
+ }
+
+ I2C_Stop(conf);
+
+ return 0;//success
+}
+
+int I2C_ReadRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len)
+{
+ int i;
+
+ I2C_Start(conf);
+
+ //Write addr | read command
+ if(I2C_WriteByte(conf, (addr | 1)) != 0)
+ {
+ //printf("Received NACK at address phase!!\r\n");
+ return -1;
+ }
+
+ //Read data
+ for(i=0; i<len; i++)
+ {
+ data[i] = I2C_ReadByte(conf);
+
+ if( i == (len - 1) )
+ I2C_SendNACK(conf);
+ else
+ I2C_SendACK(conf);
+ }
+
+ return 0;//success
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_i2c.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+/*include -------------------------------------*/
+#ifndef __W7500X_I2C_H
+#define __W7500X_I2C_H
+
+#include "W7500x.h"
+
+
+typedef enum {
+ I2C_PA_5 = 0x05,
+ I2C_PA_6 = 0x06,
+ I2C_PA_9 = 0x09,
+ I2C_PA_10 = 0x0A,
+ I2C_PC_4 = 0x24,
+ I2C_PC_5 = 0x25,
+ I2C_PC_8 = 0x28,
+ // Not connected
+ I2C_NC = (int)0xFFFFFFFF
+} I2C_PinName;
+
+typedef struct
+{
+ I2C_PinName scl;
+ I2C_PinName sda;
+}I2C_ConfigStruct;
+
+
+#define I2C_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D)
+#define I2C_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit
+
+uint32_t I2C_Init(I2C_ConfigStruct* conf);
+
+void I2C_WriteBitSDA(I2C_ConfigStruct* conf, uint8_t data);
+void I2C_WriteBitSCL(I2C_ConfigStruct* conf, uint8_t data);
+uint8_t I2C_ReadBitSDA(I2C_ConfigStruct* conf);
+
+void I2C_SendACK(I2C_ConfigStruct* conf);
+void I2C_SendNACK(I2C_ConfigStruct* conf);
+
+uint8_t I2C_WriteByte(I2C_ConfigStruct* conf, uint8_t data);
+uint8_t I2C_ReadByte(I2C_ConfigStruct* conf);
+
+void I2C_Start(I2C_ConfigStruct* conf);
+void I2C_Stop(I2C_ConfigStruct* conf);
+
+int I2C_Write(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len);
+int I2C_WriteRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len);
+int I2C_Read(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len);
+int I2C_ReadRepeated(I2C_ConfigStruct* conf, uint8_t addr, uint8_t* data, uint32_t len);
+
+
+ #endif //__W7500X_I2C_H
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,906 @@
+/**
+ ******************************************************************************
+ * @file
+ * @author
+ * @version
+ * @date
+ * @brief This file contains all the functions prototypes for the UART
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Includes -------------------------------------------*/
+#include "W7500x.h"
+#include "W7500x_pwm.h"
+
+void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn)
+{
+ if( PWM_CHn == PWM_CH0 )
+ {
+ PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register
+ PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register
+ PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register
+ PWM_CH0->IER = 0; ///< Interrupt enable register
+ PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear |
+ PWM_CHn_ICR_OverflowInterruptClear |
+ PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
+ PWM_CH0->PR = 0; ///< Prescale register
+ PWM_CH0->MR = 0; ///< Match register
+ PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register
+ PWM_CH0->UDMR = 0; ///< Up Dowm mode register
+ PWM_CH0->TCMR = 0; ///< Timer Counter mode register
+ PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register
+ PWM_CH0->CMR = 0; ///< Capture mode register
+ PWM_CH0->PDMR = 0; ///< Periodic Mode register
+ PWM_CH0->DZER = 0; ///< Dead Zone Enable register
+ PWM_CH0->DZCR = 0; ///< Dead Zone Counter register
+ }
+ else if( PWM_CHn == PWM_CH1 )
+ {
+ PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register
+ PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register
+ PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register
+ PWM_CH1->IER = 0; ///< Interrupt enable register
+ PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear |
+ PWM_CHn_ICR_OverflowInterruptClear |
+ PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
+ PWM_CH1->PR = 0; ///< Prescale register
+ PWM_CH1->MR = 0; ///< Match register
+ PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register
+ PWM_CH1->UDMR = 0; ///< Up Dowm mode register
+ PWM_CH1->TCMR = 0; ///< Timer Counter mode register
+ PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register
+ PWM_CH1->CMR = 0; ///< Capture mode register
+ PWM_CH1->PDMR = 0; ///< Periodic Mode register
+ PWM_CH1->DZER = 0; ///< Dead Zone Enable register
+ PWM_CH1->DZCR = 0; ///< Dead Zone Counter register
+ }
+ else if( PWM_CHn == PWM_CH2)
+ {
+ PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register
+ PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register
+ PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register
+ PWM_CH2->IER = 0; ///< Interrupt enable register
+ PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear |
+ PWM_CHn_ICR_OverflowInterruptClear |
+ PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
+ PWM_CH2->PR = 0; ///< Prescale register
+ PWM_CH2->MR = 0; ///< Match register
+ PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register
+ PWM_CH2->UDMR = 0; ///< Up Dowm mode register
+ PWM_CH2->TCMR = 0; ///< Timer Counter mode register
+ PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register
+ PWM_CH2->CMR = 0; ///< Capture mode register
+ PWM_CH2->PDMR = 0; ///< Periodic Mode register
+ PWM_CH2->DZER = 0; ///< Dead Zone Enable register
+ PWM_CH2->DZCR = 0; ///< Dead Zone Counter register
+ }
+ else if( PWM_CHn == PWM_CH3 )
+ {
+ PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register
+ PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register
+ PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register
+ PWM_CH3->IER = 0; ///< Interrupt enable register
+ PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear |
+ PWM_CHn_ICR_OverflowInterruptClear |
+ PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
+ PWM_CH3->MR = 0; ///< Match register
+ PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register
+ PWM_CH3->UDMR = 0; ///< Up Dowm mode register
+ PWM_CH3->TCMR = 0; ///< Timer Counter mode register
+ PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register
+ PWM_CH3->CMR = 0; ///< Capture mode register
+ PWM_CH3->PDMR = 0; ///< Periodic Mode register
+ PWM_CH3->DZER = 0; ///< Dead Zone Enable register
+ PWM_CH3->DZCR = 0; ///< Dead Zone Counter register
+ }
+ else if( PWM_CHn == PWM_CH4 )
+ {
+ PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register
+ PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register
+ PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register
+ PWM_CH4->IER = 0; ///< Interrupt enable register
+ PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear |
+ PWM_CHn_ICR_OverflowInterruptClear |
+ PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
+ PWM_CH4->PR = 0; ///< Prescale register
+ PWM_CH4->MR = 0; ///< Match register
+ PWM_CH4->LR = 0xFFFF; ///< Limit register
+ PWM_CH4->UDMR = 0; ///< Up Dowm mode register
+ PWM_CH4->TCMR = 0; ///< Timer Counter mode register
+ PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register
+ PWM_CH4->CMR = 0; ///< Capture mode register
+ PWM_CH4->PDMR = 0; ///< Periodic Mode register
+ PWM_CH4->DZER = 0; ///< Dead Zone Enable register
+ PWM_CH4->DZCR = 0; ///< Dead Zone Counter register
+ }
+ else if( PWM_CHn == PWM_CH5 )
+ {
+ PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register
+ PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register
+ PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register
+ PWM_CH5->IER = 0; ///< Interrupt enable register
+ PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear |
+ PWM_CHn_ICR_OverflowInterruptClear |
+ PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
+ PWM_CH5->PR = 0; ///< Prescale register
+ PWM_CH5->MR = 0; ///< Match register
+ PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register
+ PWM_CH5->UDMR = 0; ///< Up Dowm mode register
+ PWM_CH5->TCMR = 0; ///< Timer Counter mode register
+ PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register
+ PWM_CH5->CMR = 0; ///< Capture mode register
+ PWM_CH5->PDMR = 0; ///< Periodic Mode register
+ PWM_CH5->DZER = 0; ///< Dead Zone Enable register
+ PWM_CH5->DZCR = 0; ///< Dead Zone Counter register
+ }
+ else if( PWM_CHn == PWM_CH6 )
+ {
+ PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register
+ PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register
+ PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register
+ PWM_CH6->IER = 0; ///< Interrupt enable register
+ PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear |
+ PWM_CHn_ICR_OverflowInterruptClear |
+ PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
+ PWM_CH6->PR = 0; ///< Prescale register
+ PWM_CH6->MR = 0; ///< Match register
+ PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register
+ PWM_CH6->UDMR = 0; ///< Up Dowm mode register
+ PWM_CH6->TCMR = 0; ///< Timer Counter mode register
+ PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register
+ PWM_CH6->CMR = 0; ///< Capture mode register
+ PWM_CH6->PDMR = 0; ///< Periodic Mode register
+ PWM_CH6->DZER = 0; ///< Dead Zone Enable register
+ PWM_CH6->DZCR = 0; ///< Dead Zone Counter register
+ }
+ else if( PWM_CHn == PWM_CH7 )
+ {
+ PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register
+ PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register
+ PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register
+ PWM_CH7->IER = 0; ///< Interrupt enable register
+ PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear |
+ PWM_CHn_ICR_OverflowInterruptClear |
+ PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
+ PWM_CH7->PR = 0; ///< Prescale register
+ PWM_CH7->MR = 0; ///< Match register
+ PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register
+ PWM_CH7->UDMR = 0; ///< Up Dowm mode register
+ PWM_CH7->TCMR = 0; ///< Timer Counter mode register
+ PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register
+ PWM_CH7->CMR = 0; ///< Capture mode register
+ PWM_CH7->PDMR = 0; ///< Periodic Mode register
+ PWM_CH7->DZER = 0; ///< Dead Zone Enable register
+ PWM_CH7->DZCR = 0; ///< Dead Zone Counter register
+ }
+}
+
+
+void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet
+{
+ /* Stop PWM_CHn */
+ PWM_CHn_Stop(PWM_CHn);
+ /* Select Timer/Counter mode as Timer mode */
+ PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
+ /* Set Prescale register value */
+ PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR;
+ /* Set Match register value */
+ PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR;
+ /* Set Limit register value */
+ PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR;
+ /* Select Up-down mode */
+ PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR;
+ /* Select Periodic mode */
+ PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR;
+}
+
+void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR));
+ assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR));
+ assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR));
+ assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR));
+ assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR));
+ assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR));
+
+ /* Stop PWM_CHn */
+ PWM_CHn_Stop(PWM_CHn);
+ /* Select Timer/Counter mode as Timer mode */
+ PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
+ /* Set Prescale register value */
+ PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR;
+ /* Set Match register value */
+ PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR;
+ /* Set Limit register value */
+ PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR;
+ /* Select Up-down mode */
+ PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR;
+ /* Select Periodic mode */
+ PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR;
+ /* Select Capture mode */
+ PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR;
+ /* External input enable */
+ PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
+}
+
+void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ /* Stop PWM_CHn */
+ PWM_CHn_Stop(PWM_CHn);
+ /* Select Timer/Counter mode as Timer mode */
+ PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
+ /* Set Match register value */
+ PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR;
+ /* Set Limit register value */
+ PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR;
+ /* Select Up-down mode */
+ PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR;
+ /* Select Periodic mode */
+ PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR;
+ /* Select Counter mode */
+ PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR;
+ /* Enable external input */
+ PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
+}
+
+void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR));
+ assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR));
+ assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR));
+ assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR));
+ assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR));
+ assert_param(IS_PWM_Deadznoe(PWM_CHn));
+
+ /* Stop PWM_CHn */
+ PWM_CHn_Stop(PWM_CHn);
+ /* Select Timer/Counter mode as Timer mode */
+ PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
+ /* Set Prescale register value */
+ PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR;
+ /* Set Match register value */
+ PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR;
+ /* Set Limit register value */
+ PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR;
+ /* Select Up-down mode */
+ PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR;
+ /* Select Periodic mode */
+ PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR;
+ /* Enable Dead Zone generation */
+ PWM_CHn->DZER = PWM_CHn_DZER_Enable;
+ /* Set Dead Zone Counter */
+ PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR;
+}
+
+void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_Output(outputEnDisable));
+ if( PWM_CHn->DZER )
+ assert_param(IS_PWM_Deadznoe(PWM_CHn));
+
+ /* Stop PWM_CHn */
+ PWM_CHn_Stop(PWM_CHn);
+ /*Config PWM output and External input */
+ PWM_CHn->PEEER = outputEnDisable;
+}
+
+void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn)
+{
+ PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable);
+}
+
+void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn)
+{
+ PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable);
+}
+
+void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ /* Stop PWM_CHn */
+ PWM_CHn_Stop(PWM_CHn);
+
+ if(state == ENABLE)
+ {
+ if(PWM_CHn == PWM_CH0) {
+ PWM->IER |= PWM_IER_IE0_Enable;
+ }
+ else if(PWM_CHn == PWM_CH1) {
+ PWM->IER |= PWM_IER_IE1_Enable;
+ }
+ else if(PWM_CHn == PWM_CH2) {
+ PWM->IER |= PWM_IER_IE2_Enable;
+ }
+ else if(PWM_CHn == PWM_CH3) {
+ PWM->IER |= PWM_IER_IE3_Enable;
+ }
+ else if(PWM_CHn == PWM_CH4) {
+ PWM->IER |= PWM_IER_IE4_Enable;
+ }
+ else if(PWM_CHn == PWM_CH5) {
+ PWM->IER |= PWM_IER_IE5_Enable;
+ }
+ else if(PWM_CHn == PWM_CH6) {
+ PWM->IER |= PWM_IER_IE6_Enable;
+ }
+ else if(PWM_CHn == PWM_CH7) {
+ PWM->IER |= PWM_IER_IE7_Enable;
+ }
+ }
+ else
+ {
+ if(PWM_CHn == PWM_CH0) {
+ PWM->IER &= PWM_IER_IE0_Disable;
+ }
+ else if(PWM_CHn == PWM_CH1) {
+ PWM->IER &= PWM_IER_IE1_Disable;
+ }
+ else if(PWM_CHn == PWM_CH2) {
+ PWM->IER &= PWM_IER_IE2_Disable;
+ }
+ else if(PWM_CHn == PWM_CH3) {
+ PWM->IER &= PWM_IER_IE3_Disable;
+ }
+ else if(PWM_CHn == PWM_CH4) {
+ PWM->IER &= PWM_IER_IE4_Disable;
+ }
+ else if(PWM_CHn == PWM_CH5) {
+ PWM->IER &= PWM_IER_IE5_Disable;
+ }
+ else if(PWM_CHn == PWM_CH6) {
+ PWM->IER &= PWM_IER_IE6_Disable;
+ }
+ else if(PWM_CHn == PWM_CH7) {
+ PWM->IER &= PWM_IER_IE7_Disable;
+ }
+ }
+}
+
+FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn)
+{
+ FlagStatus ret_val = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ if(PWM_CHn == PWM_CH0) {
+ ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0);
+ }
+ else if(PWM_CHn == PWM_CH1) {
+ ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1);
+ }
+ else if(PWM_CHn == PWM_CH2) {
+ ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2);
+ }
+ else if(PWM_CHn == PWM_CH3) {
+ ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3);
+ }
+ else if(PWM_CHn == PWM_CH4) {
+ ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4);
+ }
+ else if(PWM_CHn == PWM_CH5) {
+ ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5);
+ }
+ else if(PWM_CHn == PWM_CH6) {
+ ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6);
+ }
+ else if(PWM_CHn == PWM_CH7) {
+ ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7);
+ }
+
+ return ret_val;
+}
+
+void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+
+ assert_param(IS_PWM_CHn_IER(PWM_CHn_IER));
+
+ /* Stop PWM_CHn */
+ PWM_CHn_Stop(PWM_CHn);
+
+ if(state == ENABLE)
+ PWM_CHn->IER |= PWM_CHn_IER;
+ else
+ PWM_CHn->IER &= ~PWM_CHn_IER;
+}
+
+uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->IER;
+}
+
+uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->IR;
+}
+
+void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR)
+{
+ /* Check the parameters */
+
+ PWM_CHn->ICR = PWM_CHn_ICR;
+}
+
+void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ /* Set Start Stop register */
+ if(PWM_CHn == PWM_CH0) {
+ PWM->SSR |= PWM_SSR_SS0_Start;
+ }
+ else if(PWM_CHn == PWM_CH1) {
+ PWM->SSR |= PWM_SSR_SS1_Start;
+ }
+ else if(PWM_CHn == PWM_CH2) {
+ PWM->SSR |= PWM_SSR_SS2_Start;
+ }
+ else if(PWM_CHn == PWM_CH3) {
+ PWM->SSR |= PWM_SSR_SS3_Start;
+ }
+ else if(PWM_CHn == PWM_CH4) {
+ PWM->SSR |= PWM_SSR_SS4_Start;
+ }
+ else if(PWM_CHn == PWM_CH5) {
+ PWM->SSR |= PWM_SSR_SS5_Start;
+ }
+ else if(PWM_CHn == PWM_CH6) {
+ PWM->SSR |= PWM_SSR_SS6_Start;
+ }
+ else if(PWM_CHn == PWM_CH7) {
+ PWM->SSR |= PWM_SSR_SS7_Start;
+ }
+}
+
+void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete
+{
+ /* Set Start Stop register */
+ PWM->SSR |= ssr_bit_flag;
+}
+
+void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Reset Start Stop register */
+ if(PWM_CHn == PWM_CH0) {
+ PWM->SSR &= PWM_SSR_SS0_Stop;
+ }
+ else if(PWM_CHn == PWM_CH1) {
+ PWM->SSR &= PWM_SSR_SS1_Stop;
+ }
+ else if(PWM_CHn == PWM_CH2) {
+ PWM->SSR &= PWM_SSR_SS2_Stop;
+ }
+ else if(PWM_CHn == PWM_CH3) {
+ PWM->SSR &= PWM_SSR_SS3_Stop;
+ }
+ else if(PWM_CHn == PWM_CH4) {
+ PWM->SSR &= PWM_SSR_SS4_Stop;
+ }
+ else if(PWM_CHn == PWM_CH5) {
+ PWM->SSR &= PWM_SSR_SS5_Stop;
+ }
+ else if(PWM_CHn == PWM_CH6) {
+ PWM->SSR &= PWM_SSR_SS6_Stop;
+ }
+ else if(PWM_CHn == PWM_CH7) {
+ PWM->SSR &= PWM_SSR_SS7_Stop;
+ }
+}
+
+void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete
+{
+ /* Reset Start Stop register */
+ PWM->SSR &= ~ssr_bit_flag;
+}
+
+void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn)
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ /* Set Pause register */
+ if(PWM_CHn == PWM_CH0) {
+ PWM->PSR |= PWM_PSR_PS0_Pause;
+ }
+ else if(PWM_CHn == PWM_CH1) {
+ PWM->PSR |= PWM_PSR_PS1_Pause;
+ }
+ else if(PWM_CHn == PWM_CH2) {
+ PWM->PSR |= PWM_PSR_PS2_Pause;
+ }
+ else if(PWM_CHn == PWM_CH3) {
+ PWM->PSR |= PWM_PSR_PS3_Pause;
+ }
+ else if(PWM_CHn == PWM_CH4) {
+ PWM->PSR |= PWM_PSR_PS4_Pause;
+ }
+ else if(PWM_CHn == PWM_CH5) {
+ PWM->PSR |= PWM_PSR_PS5_Pause;
+ }
+ else if(PWM_CHn == PWM_CH6) {
+ PWM->PSR |= PWM_PSR_PS6_Pause;
+ }
+ else if(PWM_CHn == PWM_CH7) {
+ PWM->PSR |= PWM_PSR_PS7_Pause;
+ }
+}
+
+void PWM_Multi_Pause(uint32_t psr_bit_flag)
+{
+ PWM->PSR |= psr_bit_flag;
+}
+
+void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn)
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ /* Reset Pause register */
+ if(PWM_CHn == PWM_CH0) {
+ PWM->PSR &= PWM_PSR_PS0_Restart;
+ }
+ else if(PWM_CHn == PWM_CH1) {
+ PWM->PSR &= PWM_PSR_PS1_Restart;
+ }
+ else if(PWM_CHn == PWM_CH2) {
+ PWM->PSR &= PWM_PSR_PS2_Restart;
+ }
+ else if(PWM_CHn == PWM_CH3) {
+ PWM->PSR &= PWM_PSR_PS3_Restart;
+ }
+ else if(PWM_CHn == PWM_CH4) {
+ PWM->PSR &= PWM_PSR_PS4_Restart;
+ }
+ else if(PWM_CHn == PWM_CH5) {
+ PWM->PSR &= PWM_PSR_PS5_Restart;
+ }
+ else if(PWM_CHn == PWM_CH6) {
+ PWM->PSR &= PWM_PSR_PS6_Restart;
+ }
+ else if(PWM_CHn == PWM_CH7) {
+ PWM->PSR &= PWM_PSR_PS7_Restart;
+ }
+}
+
+void PWM_Multi_Restart(uint32_t psr_bit_flag)
+{
+ PWM->PSR &= ~psr_bit_flag;
+}
+
+
+uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->TCR;
+}
+
+uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->PCR;
+}
+
+uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->PR;
+}
+
+void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_PR_FILTER(PR));
+
+ PWM_CHn->PR = PR;
+}
+
+uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->MR;
+}
+
+void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ PWM_CHn->MR = MR;
+}
+
+uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->LR;
+}
+
+void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ PWM_CHn->LR = LR;
+}
+
+uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->UDMR;
+}
+
+void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_CHn_UDMR(UDMR));
+
+ PWM_CHn->UDMR = UDMR;
+}
+
+uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->TCMR;
+}
+
+void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_CHn_TCMR(TCMR));
+
+ PWM_CHn->TCMR = TCMR;
+}
+
+uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->PEEER;
+}
+
+void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_CHn_PEEER(PEEER));
+
+ PWM_CHn->PEEER = PEEER;
+}
+
+uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->CMR;
+}
+
+void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_CHn_CMR(CMR));
+
+ PWM_CHn->CMR = CMR;
+}
+
+uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn)
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->CR;
+}
+
+uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->PDMR;
+}
+
+void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_CHn_PDMR(PDMR));
+
+ PWM_CHn->PDMR = PDMR;
+}
+
+uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->DZER;
+}
+
+void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_CHn_DZER(DZER));
+
+ PWM_CHn->DZER = DZER;
+}
+
+uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+
+ return PWM_CHn->DZCR;
+}
+
+void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete
+{
+ /* Check the parameters */
+ assert_param(IS_PWM_ALL_CH(PWM_CHn));
+ assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR));
+
+ PWM_CHn->DZCR = DZCR;
+}
+
+void PWM_CH0_ClearMatchInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear);
+}
+
+void PWM_CH0_ClearOverflowInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear);
+}
+
+void PWM_CH0_ClearCaptureInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear);
+}
+
+void PWM_CH1_ClearMatchInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear);
+}
+
+void PWM_CH1_ClearOverflowInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear);
+}
+
+void PWM_CH1_ClearCaptureInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear);
+}
+
+void PWM_CH2_ClearMatchInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear);
+}
+
+void PWM_CH2_ClearOverflowInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear);
+}
+
+void PWM_CH2_ClearCaptureInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear);
+}
+
+void PWM_CH3_ClearMatchInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear);
+}
+
+void PWM_CH3_ClearOverflowInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear);
+}
+
+void PWM_CH3_ClearCaptureInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear);
+}
+
+void PWM_CH4_ClearMatchInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear);
+}
+
+void PWM_CH4_ClearOverflowInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear);
+}
+
+void PWM_CH4_ClearCaptureInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear);
+}
+
+void PWM_CH5_ClearMatchInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear);
+}
+
+void PWM_CH5_ClearOverflowInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear);
+}
+
+void PWM_CH5_ClearCaptureInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear);
+}
+
+void PWM_CH6_ClearMatchInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear);
+}
+
+void PWM_CH6_ClearOverflowInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear);
+}
+
+void PWM_CH6_ClearCaptureInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear);
+}
+
+void PWM_CH7_ClearMatchInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear);
+}
+
+void PWM_CH7_ClearOverflowInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear);
+}
+
+void PWM_CH7_ClearCaptureInt(void)
+{
+ PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,289 @@
+/**
+ ******************************************************************************
+ * @file
+ * @author
+ * @version
+ * @date
+ * @brief This file contains all the functions prototypes for the UART
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __W7500X_PWM_H
+#define __W7500X_PWM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "W7500x.h"
+
+/**********************************************************************************************/
+/**********************************************************************************************/
+// This structure and define must be in W7500x.h
+/**********************************************************************************************/
+/**********************************************************************************************/
+
+typedef struct
+{
+ uint32_t PWM_CHn_PEEER;
+}PWM_CtrlPWMOutputTypeDef;
+
+typedef struct
+{
+ uint32_t PWM_CHn_PR;
+ uint32_t PWM_CHn_MR;
+ uint32_t PWM_CHn_LR;
+ uint32_t PWM_CHn_UDMR;
+ uint32_t PWM_CHn_PDMR;
+ uint32_t PWM_CHn_DZCR;
+}PWM_DeadzoneModeInitTypDef;
+
+#define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
+ (CHn == PWM_CH1) || \
+ (CHn == PWM_CH2) || \
+ (CHn == PWM_CH3) || \
+ (CHn == PWM_CH4) || \
+ (CHn == PWM_CH5) || \
+ (CHn == PWM_CH6) || \
+ (CHn == PWM_CH7))
+
+#define PWM_IER_IE0_Enable (0x1ul << 0)
+#define PWM_IER_IE1_Enable (0x1ul << 1)
+#define PWM_IER_IE2_Enable (0x1ul << 2)
+#define PWM_IER_IE3_Enable (0x1ul << 3)
+#define PWM_IER_IE4_Enable (0x1ul << 4)
+#define PWM_IER_IE5_Enable (0x1ul << 5)
+#define PWM_IER_IE6_Enable (0x1ul << 6)
+#define PWM_IER_IE7_Enable (0x1ul << 7)
+
+#define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
+#define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
+#define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
+#define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
+#define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
+#define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
+#define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
+#define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
+
+#define PWM_SSR_SS0_Start (0x1ul << 0)
+#define PWM_SSR_SS1_Start (0x1ul << 1)
+#define PWM_SSR_SS2_Start (0x1ul << 2)
+#define PWM_SSR_SS3_Start (0x1ul << 3)
+#define PWM_SSR_SS4_Start (0x1ul << 4)
+#define PWM_SSR_SS5_Start (0x1ul << 5)
+#define PWM_SSR_SS6_Start (0x1ul << 6)
+#define PWM_SSR_SS7_Start (0x1ul << 7)
+
+#define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
+#define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
+#define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
+#define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
+#define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
+#define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
+#define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
+#define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
+
+#define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
+
+#define PWM_PSR_PS0_Pause (0x1ul << 0)
+#define PWM_PSR_PS1_Pause (0x1ul << 1)
+#define PWM_PSR_PS2_Pause (0x1ul << 2)
+#define PWM_PSR_PS3_Pause (0x1ul << 3)
+#define PWM_PSR_PS4_Pause (0x1ul << 4)
+#define PWM_PSR_PS5_Pause (0x1ul << 5)
+#define PWM_PSR_PS6_Pause (0x1ul << 6)
+#define PWM_PSR_PS7_Pause (0x1ul << 7)
+
+#define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
+#define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
+#define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
+#define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
+#define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
+#define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
+#define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
+#define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
+
+#define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
+
+#define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
+#define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
+#define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
+#define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
+
+#define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
+#define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
+#define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
+
+#define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
+#define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
+#define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
+#define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
+
+/*
+#define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
+ ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
+ ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
+ ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
+ ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
+ ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
+ ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
+ ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
+*/
+
+
+#define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
+
+
+#define PWM_CHn_UDMR_UpCount (0x0ul)
+#define PWM_CHn_UDMR_DownCount (0x1ul)
+#define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
+ (MODE == PWM_CHn_UDMR_DownCount))
+
+#define PWM_CHn_TCMR_TimerMode (0x0ul)
+#define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
+#define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
+#define PWM_CHn_TCMR_BothCounterMode (0x3ul)
+#define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
+ (MODE == PWM_CHn_TCMR_FallingCounterMode) || \
+ (MODE == PWM_CHn_TCMR_BothCounterMode))
+
+#define PWM_CHn_PEEER_Disable (0x0ul)
+#define PWM_CHn_PEEER_ExtEnable (0x1ul)
+#define PWM_CHn_PEEER_PWMEnable (0x2ul)
+#define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
+ (ENABLE == PWM_CHn_PEEER_ExtEnable) || \
+ (ENABLE == PWM_CHn_PEEER_PWMEnable))
+
+#define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
+ (ENABLE == PWM_CHn_PEEER_PWMEnable))
+
+#define PWM_CHn_CMR_RisingEdge 0x0ul
+#define PWM_CHn_CMR_FallingEdge 0x1ul
+#define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
+ (MODE == PWM_CHn_CMR_FallingEdge))
+
+#define PWM_CHn_PDMR_Oneshot (0x0ul)
+#define PWM_CHn_PDMR_Periodic (0x1ul)
+#define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
+ (MODE == PWM_CHn_PDMR_Oneshot))
+
+#define PWM_CHn_DZER_Enable (0x1ul)
+#define PWM_CHn_DZER_Disable (0x0ul)
+#define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
+ (ENABLE == PWM_CHn_DZER_Disable))
+
+#define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
+ ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
+ ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
+ ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
+ ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
+ ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
+ ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
+ ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
+
+#define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
+
+
+
+
+
+
+void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
+void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
+void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
+void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
+void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
+void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
+void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
+void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
+FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
+void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_Multi_Start(uint32_t ssr_bit_flag);
+void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_Multi_Stop(uint32_t ssr_bit_flag);
+void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_Multi_Pause(uint32_t psr_bit_flag);
+void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_Multi_Restart(uint32_t psr_bit_flag);
+uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
+uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
+uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
+uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
+uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
+uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
+uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
+uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
+uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
+uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
+uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
+uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
+uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
+void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
+uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
+void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
+void PWM_CH0_ClearMatchInt(void);
+void PWM_CH0_ClearOverflowInt(void);
+void PWM_CH0_ClearCaptureInt(void);
+void PWM_CH1_ClearMatchInt(void);
+void PWM_CH1_ClearOverflowInt(void);
+void PWM_CH1_ClearCaptureInt(void);
+void PWM_CH2_ClearMatchInt(void);
+void PWM_CH2_ClearOverflowInt(void);
+void PWM_CH2_ClearCaptureInt(void);
+void PWM_CH3_ClearMatchInt(void);
+void PWM_CH3_ClearOverflowInt(void);
+void PWM_CH3_ClearCaptureInt(void);
+void PWM_CH4_ClearMatchInt(void);
+void PWM_CH4_ClearOverflowInt(void);
+void PWM_CH4_ClearCaptureInt(void);
+void PWM_CH5_ClearMatchInt(void);
+void PWM_CH5_ClearOverflowInt(void);
+void PWM_CH5_ClearCaptureInt(void);
+void PWM_CH6_ClearMatchInt(void);
+void PWM_CH6_ClearOverflowInt(void);
+void PWM_CH6_ClearCaptureInt(void);
+void PWM_CH7_ClearMatchInt(void);
+void PWM_CH7_ClearOverflowInt(void);
+void PWM_CH7_ClearCaptureInt(void);
+
+
+void PWM0_Handler(void);
+void PWM1_Handler(void);
+void PWM2_Handler(void);
+void PWM3_Handler(void);
+void PWM4_Handler(void);
+void PWM5_Handler(void);
+void PWM6_Handler(void);
+void PWM7_Handler(void);
+
+
+
+
+//Temporary macro=======
+#define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
+//======================
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif //__W7500X_PWM_H
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,371 @@
+/**
+ ******************************************************************************
+ * @file W7500x_uart.c
+ * @author
+ * @version
+ * @date
+ * @brief
+ ******************************************************************************
+ * @attention
+ *
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "W7500x.h"
+#include "W7500x_uart.h"
+
+void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
+{
+ /* UART_InitStruct members default value */
+ UART_InitStruct->UART_BaudRate = 115200;
+ UART_InitStruct->UART_WordLength = UART_WordLength_8b ;
+ UART_InitStruct->UART_StopBits = UART_StopBits_1;
+ UART_InitStruct->UART_Parity = UART_Parity_No ;
+ UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
+ UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ;
+}
+
+void UART_DeInit(UART_TypeDef *UARTx)
+{
+
+}
+
+uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct)
+{
+ float baud_divisor;
+ uint32_t tmpreg=0x00, uartclock=0x00;
+ uint32_t integer_baud = 0x00, fractional_baud = 0x00;
+
+ assert_param(IS_UART_01_PERIPH(UARTx));
+ assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength));
+ assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
+ assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl));
+ assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode));
+
+
+ UARTx->CR &= ~(UART_CR_UARTEN);
+
+ // Set baudrate
+ CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz )
+ uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR);
+
+ baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate));
+ integer_baud = (uint32_t)baud_divisor;
+ fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5);
+
+ UARTx->IBRD = integer_baud;
+ UARTx->FBRD = fractional_baud;
+
+
+ tmpreg = UARTx->LCR_H;
+ tmpreg &= ~(0x00EE);
+ tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity);
+ UARTx->LCR_H |= tmpreg;
+
+ tmpreg = UARTx->CR;
+ tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN);
+ tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl);
+ UARTx->CR |= tmpreg;
+
+ UARTx->CR |= UART_CR_UARTEN;
+
+ return 0;
+}
+
+
+void UART_SendData(UART_TypeDef* UARTx, uint16_t Data)
+{
+ assert_param(IS_UART_01_PERIPH(UARTx));
+
+ UARTx->DR = Data;
+}
+
+
+uint16_t UART_ReceiveData(UART_TypeDef* UARTx)
+{
+ assert_param(IS_UART_01_PERIPH(UARTx));
+
+ return (uint16_t)(UARTx->DR);
+}
+
+
+void UART_SendBreak(UART_TypeDef* UARTx)
+{
+ assert_param(IS_UART_01_PERIPH(UARTx));
+
+ UARTx->LCR_H |= UART_LCR_H_BRK;
+}
+
+
+FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
+{
+ FlagStatus bitstatus = RESET;
+
+ assert_param(IS_UART_01_PERIPH(UARTx));
+ assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
+
+ if( (UARTx->STATUS.RSR & UART_RECV_STATUS) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+
+void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
+{
+ assert_param(IS_UART_01_PERIPH(UARTx));
+ assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
+
+ UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS;
+}
+
+
+FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ assert_param(IS_UART_01_PERIPH(UARTx));
+ assert_param(IS_UART_FLAG(UART_FLAG));
+
+ if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+
+}
+
+/*
+void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG)
+{
+
+}
+*/
+
+void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState)
+{
+ assert_param(IS_UART_01_PERIPH(UARTx));
+ assert_param(IS_UART_IT_FLAG(UART_IT));
+
+ if ( NewState != DISABLE )
+ {
+ UARTx->IMSC |= UART_IT;
+ }
+ else
+ {
+ UARTx->ICR |= UART_IT;
+ }
+}
+
+
+ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ assert_param(IS_UART_01_PERIPH(UARTx));
+ assert_param(IS_UART_IT_FLAG(UART_IT));
+
+ if ((UARTx->MIS & UART_IT) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT)
+{
+ assert_param(IS_UART_01_PERIPH(UARTx));
+ assert_param(IS_UART_IT_FLAG(UART_IT));
+
+ UARTx->ICR |= UART_IT;
+}
+
+
+void S_UART_DeInit()
+{
+
+}
+
+uint32_t S_UART_Init(uint32_t baud)
+{
+ uint32_t tmpreg=0x00;
+ uint32_t uartclock = 0x00, integer_baud = 0x00;
+
+ assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode));
+
+ if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK)
+ {
+ uartclock = INTERN_XTAL;
+ }
+ else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK)
+ {
+ uartclock = EXTERN_XTAL;
+ }
+ else
+ {
+ uartclock = GetSystemClock();
+ }
+
+ integer_baud = (uint32_t)(uartclock / baud);
+ UART2->BAUDDIV = integer_baud;
+
+ tmpreg = UART2->CTRL;
+ tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
+ tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
+ UART2->CTRL = tmpreg;
+
+ return 0;
+}
+
+void S_UART_SendData(uint16_t Data)
+{
+ while(UART2->STATE & S_UART_STATE_TX_BUF_FULL);
+ UART2->DATA = Data;
+}
+
+uint16_t S_UART_ReceiveData()
+{
+ return (uint16_t)(UART2->DATA);
+}
+
+
+FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ assert_param(IS_S_UART_FLAG(S_UART_FLAG));
+
+ if ((UART2->STATE & S_UART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+
+void S_UART_ITConfig(uint16_t S_UART_IT, FunctionalState NewState)
+{
+ assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
+
+ if ( NewState != DISABLE )
+ {
+ UART2->CTRL |= S_UART_IT;
+ }
+ else
+ {
+ UART2->CTRL &= ~(S_UART_IT);
+ }
+}
+
+ITStatus S_UART_GetITStatus(uint16_t S_UART_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
+
+ if ((UART2->INT.STATUS & (S_UART_IT >> 2)) != (uint16_t) RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+void S_UART_ClearITPendingBit(uint16_t S_UART_IT)
+{
+ assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
+
+ UART2->INT.CLEAR |= (S_UART_IT >> 2);
+}
+
+
+/**************************************************/
+// It will be moved to application board's driver */
+/**************************************************/
+uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch)
+{
+ UART_SendData(UARTx,ch);
+
+ while(UARTx->FR & UART_FR_BUSY);
+
+ return (ch);
+}
+
+void UartPuts(UART_TypeDef* UARTx, uint8_t *str)
+{
+ uint8_t ch;
+
+ do{
+ ch = *str;
+ if(ch != (uint8_t)0x0)
+ {
+ UartPutc(UARTx, ch);
+ }
+ *str++;
+ }while(ch != 0);
+}
+
+uint8_t UartGetc(UART_TypeDef* UARTx)
+{
+ while(UARTx->FR & UART_FR_RXFE);
+
+ return (UARTx->DR & 0xFF);
+}
+
+
+uint8_t S_UartPutc(uint8_t ch)
+{
+ S_UART_SendData(ch);
+
+ return (ch);
+}
+
+void S_UartPuts(uint8_t *str)
+{
+ uint8_t ch;
+
+ do{
+ ch = *str;
+ if(ch != (uint8_t)0x0)
+ {
+ S_UART_SendData(ch);
+ }
+ *str++;
+ }while(ch != 0);
+}
+
+uint8_t S_UartGetc()
+{
+ while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 );
+ return (uint8_t)S_UART_ReceiveData();
+}
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,289 @@
+/**
+ ******************************************************************************
+ * @file
+ * @author
+ * @version
+ * @date
+ * @brief This file contains all the functions prototypes for the UART
+ * firmware library.
+ ******************************************************************************
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __W7500X_UART_H
+#define __W7500X_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "W7500x.h"
+
+
+/**
+ * @brief UART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t UART_BaudRate;
+ uint16_t UART_WordLength;
+ uint16_t UART_StopBits;
+ uint16_t UART_Parity;
+ uint16_t UART_Mode;
+ uint16_t UART_HardwareFlowControl;
+} UART_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/** @defgroup UART_Exported_Constants
+ * @{
+ */
+
+#define IS_UART_01_PERIPH(PERIPH) (((PERIPH) == UART0) || ((PERIPH) == UART1))
+#define IS_UART_2_PERIPH(PERIPH) ((PERIPH) == UART2)
+
+/**
+ * @}
+ */
+
+
+
+/** @addtogroup UART_Word_Length
+ * @{
+ */
+
+#define UART_WordLength_8b ((uint16_t)UART_LCR_H_WLEN(3))
+#define UART_WordLength_7b ((uint16_t)UART_LCR_H_WLEN(2))
+#define UART_WordLength_6b ((uint16_t)UART_LCR_H_WLEN(1))
+#define UART_WordLength_5b ((uint16_t)UART_LCR_H_WLEN(0))
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_8b) || \
+ ((LENGTH) == UART_WordLength_7b) || \
+ ((LENGTH) == UART_WordLength_6b) || \
+ ((LENGTH) == UART_WordLength_5b) )
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_Parity
+ * @{
+ */
+
+#define UART_Parity_No ((uint16_t)0x0000)
+#define UART_Parity_Even ((uint16_t)(UART_LCR_H_PEN | UART_LCR_H_EPS))
+#define UART_Parity_Odd ((uint16_t)(UART_LCR_H_PEN))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
+ ((PARITY) == UART_Parity_Even) || \
+ ((PARITY) == UART_Parity_Odd))
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_Stop_Bits
+ * @{
+ */
+
+#define UART_StopBits_1 ((uint16_t)0x0000)
+#define UART_StopBits_2 ((uint16_t)(UART_LCR_H_STP2))
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
+ ((STOPBITS) == UART_StopBits_2))
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_Mode
+ * @{
+ */
+
+#define UART_Mode_Rx ((uint16_t)(UART_CR_RXE))
+#define UART_Mode_Tx ((uint16_t)(UART_CR_TXE))
+#define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \
+ ((MODE) == UART_Mode_Tx))
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_Hardware_Flow_Control
+ * @{
+ */
+
+#define UART_HardwareFlowControl_None ((uint16_t)0x0000)
+#define UART_HardwareFlowControl_RTS ((uint16_t)UART_CR_RTSEn)
+#define UART_HardwareFlowControl_CTS ((uint16_t)UART_CR_CTSEn)
+#define UART_HardwareFlowControl_RTS_CTS ((uint16_t)(UART_CR_RTSEn | UART_CR_CTSEn))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) \
+ (((CONTROL) == UART_HardwareFlowControl_None) || \
+ ((CONTROL) == UART_HardwareFlowControl_RTS) || \
+ ((CONTROL) == UART_HardwareFlowControl_CTS) || \
+ ((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_Receive Status
+ * @{
+ */
+
+#define UART_RECV_STATUS_OE ((uint16_t)0x01UL << 3) /*!< Overrun error */
+#define UART_RECV_STATUS_BE ((uint16_t)0x01UL << 2) /*!< Break error */
+#define UART_RECV_STATUS_PE ((uint16_t)0x01UL << 1) /*!< Parity error */
+#define UART_RECV_STATUS_FE ((uint16_t)0x01UL << 0) /*!< Framing error */
+#define IS_UART_RECV_STATUS(FLAG) (((FLAG) == UART_RECV_STATUS_OE) || ((FLAG) == UART_RECV_STATUS_BE) || \
+ ((FLAG) == UART_RECV_STATUS_PE) || ((FLAG) == UART_RECV_STATUS_FE))
+/**
+ * @}
+ */
+
+
+
+/** @addtogroup UART_Flags
+ * @{
+ */
+
+#define UART_FLAG_RI ((uint16_t)0x01UL << 8) /*!< Ring indicator */
+#define UART_FLAG_TXFE ((uint16_t)0x01UL << 7) /*!< Transmit FIFO empty */
+#define UART_FLAG_RXFF ((uint16_t)0x01UL << 6) /*!< Receive FIFO full */
+#define UART_FLAG_TXFF ((uint16_t)0x01UL << 5) /*!< Transmit FIFO full */
+#define UART_FLAG_RXFE ((uint16_t)0x01UL << 4) /*!< Receive FIFO empty */
+#define UART_FLAG_BUSY ((uint16_t)0x01UL << 3) /*!< UART busy */
+#define UART_FLAG_DCD ((uint16_t)0x01UL << 2) /*!< Data carrier detect */
+#define UART_FLAG_DSR ((uint16_t)0x01UL << 1) /*!< Data set ready */
+#define UART_FLAG_CTS ((uint16_t)0x01UL << 0) /*!< Clear to send */
+#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_RI) || ((FLAG) == UART_FLAG_TXFE) || \
+ ((FLAG) == UART_FLAG_RXFF) || ((FLAG) == UART_FLAG_TXFF) || \
+ ((FLAG) == UART_FLAG_RXFE) || ((FLAG) == UART_FLAG_BUSY) || \
+ ((FLAG) == UART_FLAG_DCD) || ((FLAG) == UART_FLAG_DSR) || \
+ ((FLAG) == UART_FLAG_CTS))
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup UART_IT_Flags
+ * @{
+ */
+
+#define UART_IT_FLAG_OEI ((uint16_t)0x01UL << 10) /*!< Overrun error interrupt */
+#define UART_IT_FLAG_BEI ((uint16_t)0x01UL << 9) /*!< Break error interrupt */
+#define UART_IT_FLAG_PEI ((uint16_t)0x01UL << 8) /*!< Parity error interrupt */
+#define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */
+#define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */
+#define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */
+#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */
+#define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */
+#define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */
+#define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */
+#define UART_IT_FLAG_RIMI ((uint16_t)0x01UL << 0) /*!< UARTRI modem interrupt */
+#define IS_UART_IT_FLAG(FLAG) (((FLAG) == UART_IT_FLAG_OEI) || ((FLAG) == UART_IT_FLAG_BEI) || \
+ ((FLAG) == UART_IT_FLAG_PEI) || ((FLAG) == UART_IT_FLAG_FEI) || \
+ ((FLAG) == UART_IT_FLAG_RTI) || ((FLAG) == UART_IT_FLAG_TXI) || \
+ ((FLAG) == UART_IT_FLAG_RXI) || ((FLAG) == UART_IT_FLAG_DSRMI) || \
+ ((FLAG) == UART_IT_FLAG_DCDMI)|| ((FLAG) == UART_IT_FLAG_CTSMI) || \
+ ((FLAG) == UART_IT_FLAG_RIMI))
+/**
+ * @}
+ */
+/** @addtogroup UART_FIFO_Level Select
+ * @{
+ */
+
+#define UART_IFLS_RXIFLSEL7_8 ((uint16_t)(UART_IFLS_RXIFLSEL(4)))
+#define UART_IFLS_RXIFLSEL3_4 ((uint16_t)(UART_IFLS_RXIFLSEL(3)))
+#define UART_IFLS_RXIFLSEL1_2 ((uint16_t)(UART_IFLS_RXIFLSEL(2)))
+#define UART_IFLS_RXIFLSEL1_4 ((uint16_t)(UART_IFLS_RXIFLSEL(1)))
+#define UART_IFLS_RXIFLSEL1_8 ((uint16_t)(UART_IFLS_RXIFLSEL(0)))
+#define UART_IFLS_TXIFLSEL7_8 ((uint16_t)(UART_IFLS_TXIFLSEL(4)))
+#define UART_IFLS_TXIFLSEL3_4 ((uint16_t)(UART_IFLS_TXIFLSEL(3)))
+#define UART_IFLS_TXIFLSEL1_2 ((uint16_t)(UART_IFLS_TXIFLSEL(2)))
+#define UART_IFLS_TXIFLSEL1_4 ((uint16_t)(UART_IFLS_TXIFLSEL(1)))
+#define UART_IFLS_TXIFLSEL1_8 ((uint16_t)(UART_IFLS_TXIFLSEL(0)))
+
+#define IS_UART_FIFO_Level(FLAG) (((FLAG) == UART_IFLS_RXIFLSEL7_8) || ((FLAG) == UART_IFLS_RXIFLSEL3_4)|| \
+ ((FLAG) == UART_IFLS_RXIFLSEL1_2)|| ((FLAG) == UART_IFLS_RXIFLSEL1_4)|| ((FLAG) == UART_IFLS_RXIFLSEL1_8)||\
+ ((FLAG) == UART_IFLS_TXIFLSEL7_8)|| ((FLAG) == UART_IFLS_TXIFLSEL3_4)|| \
+ ((FLAG) == UART_IFLS_TXIFLSEL1_2)|| ((FLAG) == UART_IFLS_TXIFLSEL1_4)||((FLAG) == UART_IFLS_TXIFLSEL1_8))
+
+/**
+ * @}
+ */
+
+/** @addtogroup S_UART_Flags
+ * @{
+ */
+#define S_UART_FLAG_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */
+#define S_UART_FLAG_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */
+#define S_UART_FLAG_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */
+#define S_UART_FLAG_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */
+#define IS_S_UART_FLAG(FLAG) (((FLAG) == S_UART_FLAG_RXO) || ((FLAG) == S_UART_FLAG_TXO) || \
+ ((FLAG) == S_UART_FLAG_RXF) || ((FLAG) == S_UART_FLAG_TXF))
+/**
+ * @}
+ */
+
+
+/** @addtogroup S_UART_IT_Flags
+ * @{
+ */
+
+#define S_UART_IT_FLAG_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */
+#define S_UART_IT_FLAG_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */
+#define S_UART_IT_FLAG_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */
+#define S_UART_IT_FLAG_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */
+#define IS_S_UART_IT_FLAG(FLAG) (((FLAG) == S_UART_IT_FLAG_RXOI) || ((FLAG) == S_UART_IT_FLAG_TXOI) || \
+ ((FLAG) == S_UART_IT_FLAG_RXI) || ((FLAG) == S_UART_IT_FLAG_TXI))
+
+/**
+ * @}
+ */
+
+
+void UART_StructInit (UART_InitTypeDef* UART_InitStruct);
+
+uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct);
+void UART_SendData (UART_TypeDef* UARTx, uint16_t Data);
+uint16_t UART_ReceiveData (UART_TypeDef* UARTx);
+void UART_SendBreak (UART_TypeDef* UARTx);
+void UART_ClearRecvStatus (UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS);
+FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG);
+void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState);
+ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT);
+void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT);
+
+
+void S_UART_DeInit(void);
+uint32_t S_UART_Init(uint32_t baud);
+void S_UART_SendData(uint16_t Data);
+uint16_t S_UART_ReceiveData(void);
+
+
+
+uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch);
+void UartPuts (UART_TypeDef* UARTx, uint8_t *str);
+uint8_t UartGetc (UART_TypeDef* UARTx);
+
+uint8_t S_UartPutc(uint8_t ch);
+void S_UartPuts(uint8_t *str);
+uint8_t S_UartGetc(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __W7500X_UART_H
+
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c Fri Sep 04 08:45:09 2015 +0100 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/analogin_api.c Fri Sep 04 09:30:10 2015 +0100 @@ -36,6 +36,7 @@ #include "wait_api.h" #include "cmsis.h" #include "pinmap.h" +#include "W7500x_adc.h" #include "PeripheralPins.h"
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c Fri Sep 04 08:45:09 2015 +0100
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c Fri Sep 04 09:30:10 2015 +0100
@@ -46,7 +46,7 @@
#ifdef __cplusplus
extern "C"{
#endif
-
+void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num);
void PORT0_Handler(void)
{
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h Fri Sep 04 08:45:09 2015 +0100
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/gpio_object.h Fri Sep 04 09:30:10 2015 +0100
@@ -32,6 +32,7 @@
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
+#include "W7500x_gpio.h"
#ifdef __cplusplus
extern "C" {
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c Fri Sep 04 08:45:09 2015 +0100
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/i2c_api.c Fri Sep 04 09:30:10 2015 +0100
@@ -40,6 +40,7 @@
#include "wait_api.h"
#include "us_ticker_api.h"
+#include "W7500x_i2c.h"
/* Timeout values for flags and events waiting loops. These timeouts are
not based on accurate values, they just guarantee that the application will
@@ -106,12 +107,12 @@
if(stop)
{
- if(I2C_Read(&conf, address, data, length) != 0)
+ if(I2C_Read(&conf, address, (uint8_t*)data, length) != 0)
return -1;
}
else
{
- if(I2C_ReadRepeated(&conf, address, data, length) != 0)
+ if(I2C_ReadRepeated(&conf, address, (uint8_t*)data, length) != 0)
return -1;
}
@@ -129,12 +130,12 @@
if(stop)
{
- if(I2C_Write(&conf, address, data, length) != 0)
+ if(I2C_Write(&conf, address, (uint8_t*)data, length) != 0)
return -1;
}
else
{
- if(I2C_WriteRepeated(&conf, address, data, length) != 0)
+ if(I2C_WriteRepeated(&conf, address, (uint8_t*)data, length) != 0)
return -1;
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/objects.h Fri Sep 04 09:30:10 2015 +0100
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "PortNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t event;
+ PinName pin;
+ uint32_t pin_index;
+ uint32_t pin_num;
+ uint32_t port_num;
+ uint32_t rise_null;
+ uint32_t fall_null;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+ PinName pin_tx;
+ PinName pin_rx;
+};
+
+struct spi_s {
+ SSP_TypeDef *spi;
+};
+
+struct i2c_s {
+ I2CName I2Cx;
+ PinName sda;
+ PinName scl;
+ uint16_t ADDRESS;
+ uint16_t is_setAddress;
+};
+
+struct pwmout_s {
+ PWM_CHn_TypeDef * PWM_CHx;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+ uint32_t PrescalerValue;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c Fri Sep 04 08:45:09 2015 +0100 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/pinmap.c Fri Sep 04 09:30:10 2015 +0100 @@ -32,6 +32,8 @@ #include "pinmap.h" #include "PortNames.h" #include "mbed_error.h" +#include "W7500x.h" +#include "W7500x_gpio.h" uint32_t Get_GPIO_BaseAddress(uint32_t port_idx)
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c Fri Sep 04 08:45:09 2015 +0100 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/pwmout_api.c Fri Sep 04 09:30:10 2015 +0100 @@ -35,6 +35,7 @@ #include "pinmap.h" #include "mbed_error.h" #include "PeripheralPins.h" +#include "W7500x_pwm.h" static PWM_TimerModeInitTypeDef TimerModeStructure;
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c Fri Sep 04 08:45:09 2015 +0100 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/rtc_api.c Fri Sep 04 09:30:10 2015 +0100 @@ -14,6 +14,8 @@ * limitations under the License. */ #include "rtc_api.h" +#include "cmsis.h" +#include "W7500x_pwm.h" time_t wiz_rtc_time; char rtc_enabled = 0;
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c Fri Sep 04 08:45:09 2015 +0100 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c Fri Sep 04 09:30:10 2015 +0100 @@ -37,6 +37,7 @@ #include "pinmap.h" #include <string.h> #include "PeripheralPins.h" +#include "W7500x_uart.h" #define UART_NUM (2)
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c Fri Sep 04 08:45:09 2015 +0100 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c Fri Sep 04 09:30:10 2015 +0100 @@ -32,6 +32,8 @@ #include "us_ticker_api.h" #include "PeripheralNames.h" #include "system_W7500x.h" +#include "W7500x_dualtimer.h" +#include "W7500x_pwm.h" #define TIMER_0 DUALTIMER0_0 #define TIMER_1 PWM_CH1