Takaaki Numai
inport from local
Dependents: Hobbyking_Cheetah_0511
targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c@0:85b3fd62ea1a, 2020-03-16 (annotated)
- Committer:
- NYX
- Date:
- Mon Mar 16 06:35:48 2020 +0000
- Revision:
- 0:85b3fd62ea1a
reinport to mbed;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| NYX | 0:85b3fd62ea1a | 1 | /** |
| NYX | 0:85b3fd62ea1a | 2 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 3 | * @file system_stm32f4xx.c |
| NYX | 0:85b3fd62ea1a | 4 | * @author MCD Application Team |
| NYX | 0:85b3fd62ea1a | 5 | * @version V2.6.1 |
| NYX | 0:85b3fd62ea1a | 6 | * @date 14-February-2017 |
| NYX | 0:85b3fd62ea1a | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
| NYX | 0:85b3fd62ea1a | 8 | * |
| NYX | 0:85b3fd62ea1a | 9 | * This file provides two functions and one global variable to be called from |
| NYX | 0:85b3fd62ea1a | 10 | * user application: |
| NYX | 0:85b3fd62ea1a | 11 | * - SystemInit(): This function is called at startup just after reset and |
| NYX | 0:85b3fd62ea1a | 12 | * before branch to main program. This call is made inside |
| NYX | 0:85b3fd62ea1a | 13 | * the "startup_stm32f4xx.s" file. |
| NYX | 0:85b3fd62ea1a | 14 | * |
| NYX | 0:85b3fd62ea1a | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| NYX | 0:85b3fd62ea1a | 16 | * by the user application to setup the SysTick |
| NYX | 0:85b3fd62ea1a | 17 | * timer or configure other parameters. |
| NYX | 0:85b3fd62ea1a | 18 | * |
| NYX | 0:85b3fd62ea1a | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| NYX | 0:85b3fd62ea1a | 20 | * be called whenever the core clock is changed |
| NYX | 0:85b3fd62ea1a | 21 | * during program execution. |
| NYX | 0:85b3fd62ea1a | 22 | * |
| NYX | 0:85b3fd62ea1a | 23 | * |
| NYX | 0:85b3fd62ea1a | 24 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 25 | * @attention |
| NYX | 0:85b3fd62ea1a | 26 | * |
| NYX | 0:85b3fd62ea1a | 27 | * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> |
| NYX | 0:85b3fd62ea1a | 28 | * |
| NYX | 0:85b3fd62ea1a | 29 | * Redistribution and use in source and binary forms, with or without modification, |
| NYX | 0:85b3fd62ea1a | 30 | * are permitted provided that the following conditions are met: |
| NYX | 0:85b3fd62ea1a | 31 | * 1. Redistributions of source code must retain the above copyright notice, |
| NYX | 0:85b3fd62ea1a | 32 | * this list of conditions and the following disclaimer. |
| NYX | 0:85b3fd62ea1a | 33 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| NYX | 0:85b3fd62ea1a | 34 | * this list of conditions and the following disclaimer in the documentation |
| NYX | 0:85b3fd62ea1a | 35 | * and/or other materials provided with the distribution. |
| NYX | 0:85b3fd62ea1a | 36 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| NYX | 0:85b3fd62ea1a | 37 | * may be used to endorse or promote products derived from this software |
| NYX | 0:85b3fd62ea1a | 38 | * without specific prior written permission. |
| NYX | 0:85b3fd62ea1a | 39 | * |
| NYX | 0:85b3fd62ea1a | 40 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| NYX | 0:85b3fd62ea1a | 41 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| NYX | 0:85b3fd62ea1a | 42 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| NYX | 0:85b3fd62ea1a | 43 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| NYX | 0:85b3fd62ea1a | 44 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| NYX | 0:85b3fd62ea1a | 45 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| NYX | 0:85b3fd62ea1a | 46 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| NYX | 0:85b3fd62ea1a | 47 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| NYX | 0:85b3fd62ea1a | 48 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| NYX | 0:85b3fd62ea1a | 49 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| NYX | 0:85b3fd62ea1a | 50 | * |
| NYX | 0:85b3fd62ea1a | 51 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 52 | */ |
| NYX | 0:85b3fd62ea1a | 53 | |
| NYX | 0:85b3fd62ea1a | 54 | /** @addtogroup CMSIS |
| NYX | 0:85b3fd62ea1a | 55 | * @{ |
| NYX | 0:85b3fd62ea1a | 56 | */ |
| NYX | 0:85b3fd62ea1a | 57 | |
| NYX | 0:85b3fd62ea1a | 58 | /** @addtogroup stm32f4xx_system |
| NYX | 0:85b3fd62ea1a | 59 | * @{ |
| NYX | 0:85b3fd62ea1a | 60 | */ |
| NYX | 0:85b3fd62ea1a | 61 | |
| NYX | 0:85b3fd62ea1a | 62 | /** @addtogroup STM32F4xx_System_Private_Includes |
| NYX | 0:85b3fd62ea1a | 63 | * @{ |
| NYX | 0:85b3fd62ea1a | 64 | */ |
| NYX | 0:85b3fd62ea1a | 65 | |
| NYX | 0:85b3fd62ea1a | 66 | |
| NYX | 0:85b3fd62ea1a | 67 | #include "stm32f4xx.h" |
| NYX | 0:85b3fd62ea1a | 68 | |
| NYX | 0:85b3fd62ea1a | 69 | #if !defined (HSE_VALUE) |
| NYX | 0:85b3fd62ea1a | 70 | #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ |
| NYX | 0:85b3fd62ea1a | 71 | #endif /* HSE_VALUE */ |
| NYX | 0:85b3fd62ea1a | 72 | |
| NYX | 0:85b3fd62ea1a | 73 | #if !defined (HSI_VALUE) |
| NYX | 0:85b3fd62ea1a | 74 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| NYX | 0:85b3fd62ea1a | 75 | #endif /* HSI_VALUE */ |
| NYX | 0:85b3fd62ea1a | 76 | |
| NYX | 0:85b3fd62ea1a | 77 | /** |
| NYX | 0:85b3fd62ea1a | 78 | * @} |
| NYX | 0:85b3fd62ea1a | 79 | */ |
| NYX | 0:85b3fd62ea1a | 80 | |
| NYX | 0:85b3fd62ea1a | 81 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions |
| NYX | 0:85b3fd62ea1a | 82 | * @{ |
| NYX | 0:85b3fd62ea1a | 83 | */ |
| NYX | 0:85b3fd62ea1a | 84 | |
| NYX | 0:85b3fd62ea1a | 85 | /** |
| NYX | 0:85b3fd62ea1a | 86 | * @} |
| NYX | 0:85b3fd62ea1a | 87 | */ |
| NYX | 0:85b3fd62ea1a | 88 | |
| NYX | 0:85b3fd62ea1a | 89 | /** @addtogroup STM32F4xx_System_Private_Defines |
| NYX | 0:85b3fd62ea1a | 90 | * @{ |
| NYX | 0:85b3fd62ea1a | 91 | */ |
| NYX | 0:85b3fd62ea1a | 92 | |
| NYX | 0:85b3fd62ea1a | 93 | /************************* Miscellaneous Configuration ************************/ |
| NYX | 0:85b3fd62ea1a | 94 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ |
| NYX | 0:85b3fd62ea1a | 95 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| NYX | 0:85b3fd62ea1a | 96 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| NYX | 0:85b3fd62ea1a | 97 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) |
| NYX | 0:85b3fd62ea1a | 98 | /* #define DATA_IN_ExtSRAM */ |
| NYX | 0:85b3fd62ea1a | 99 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ |
| NYX | 0:85b3fd62ea1a | 100 | STM32F412Zx || STM32F412Vx */ |
| NYX | 0:85b3fd62ea1a | 101 | |
| NYX | 0:85b3fd62ea1a | 102 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| NYX | 0:85b3fd62ea1a | 103 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| NYX | 0:85b3fd62ea1a | 104 | /* #define DATA_IN_ExtSDRAM */ |
| NYX | 0:85b3fd62ea1a | 105 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
| NYX | 0:85b3fd62ea1a | 106 | STM32F479xx */ |
| NYX | 0:85b3fd62ea1a | 107 | |
| NYX | 0:85b3fd62ea1a | 108 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| NYX | 0:85b3fd62ea1a | 109 | Internal SRAM. */ |
| NYX | 0:85b3fd62ea1a | 110 | /* #define VECT_TAB_SRAM */ |
| NYX | 0:85b3fd62ea1a | 111 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
| NYX | 0:85b3fd62ea1a | 112 | This value must be a multiple of 0x200. */ |
| NYX | 0:85b3fd62ea1a | 113 | /******************************************************************************/ |
| NYX | 0:85b3fd62ea1a | 114 | |
| NYX | 0:85b3fd62ea1a | 115 | /** |
| NYX | 0:85b3fd62ea1a | 116 | * @} |
| NYX | 0:85b3fd62ea1a | 117 | */ |
| NYX | 0:85b3fd62ea1a | 118 | |
| NYX | 0:85b3fd62ea1a | 119 | /** @addtogroup STM32F4xx_System_Private_Macros |
| NYX | 0:85b3fd62ea1a | 120 | * @{ |
| NYX | 0:85b3fd62ea1a | 121 | */ |
| NYX | 0:85b3fd62ea1a | 122 | |
| NYX | 0:85b3fd62ea1a | 123 | /** |
| NYX | 0:85b3fd62ea1a | 124 | * @} |
| NYX | 0:85b3fd62ea1a | 125 | */ |
| NYX | 0:85b3fd62ea1a | 126 | |
| NYX | 0:85b3fd62ea1a | 127 | /** @addtogroup STM32F4xx_System_Private_Variables |
| NYX | 0:85b3fd62ea1a | 128 | * @{ |
| NYX | 0:85b3fd62ea1a | 129 | */ |
| NYX | 0:85b3fd62ea1a | 130 | /* This variable is updated in three ways: |
| NYX | 0:85b3fd62ea1a | 131 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| NYX | 0:85b3fd62ea1a | 132 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| NYX | 0:85b3fd62ea1a | 133 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| NYX | 0:85b3fd62ea1a | 134 | Note: If you use this function to configure the system clock; then there |
| NYX | 0:85b3fd62ea1a | 135 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| NYX | 0:85b3fd62ea1a | 136 | variable is updated automatically. |
| NYX | 0:85b3fd62ea1a | 137 | */ |
| NYX | 0:85b3fd62ea1a | 138 | uint32_t SystemCoreClock = 16000000; |
| NYX | 0:85b3fd62ea1a | 139 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| NYX | 0:85b3fd62ea1a | 140 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; |
| NYX | 0:85b3fd62ea1a | 141 | /** |
| NYX | 0:85b3fd62ea1a | 142 | * @} |
| NYX | 0:85b3fd62ea1a | 143 | */ |
| NYX | 0:85b3fd62ea1a | 144 | |
| NYX | 0:85b3fd62ea1a | 145 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes |
| NYX | 0:85b3fd62ea1a | 146 | * @{ |
| NYX | 0:85b3fd62ea1a | 147 | */ |
| NYX | 0:85b3fd62ea1a | 148 | |
| NYX | 0:85b3fd62ea1a | 149 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| NYX | 0:85b3fd62ea1a | 150 | static void SystemInit_ExtMemCtl(void); |
| NYX | 0:85b3fd62ea1a | 151 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| NYX | 0:85b3fd62ea1a | 152 | |
| NYX | 0:85b3fd62ea1a | 153 | /** |
| NYX | 0:85b3fd62ea1a | 154 | * @} |
| NYX | 0:85b3fd62ea1a | 155 | */ |
| NYX | 0:85b3fd62ea1a | 156 | |
| NYX | 0:85b3fd62ea1a | 157 | /** @addtogroup STM32F4xx_System_Private_Functions |
| NYX | 0:85b3fd62ea1a | 158 | * @{ |
| NYX | 0:85b3fd62ea1a | 159 | */ |
| NYX | 0:85b3fd62ea1a | 160 | |
| NYX | 0:85b3fd62ea1a | 161 | /*+ MBED */ |
| NYX | 0:85b3fd62ea1a | 162 | #if 0 |
| NYX | 0:85b3fd62ea1a | 163 | /*- MBED */ |
| NYX | 0:85b3fd62ea1a | 164 | |
| NYX | 0:85b3fd62ea1a | 165 | /** |
| NYX | 0:85b3fd62ea1a | 166 | * @brief Setup the microcontroller system |
| NYX | 0:85b3fd62ea1a | 167 | * Initialize the FPU setting, vector table location and External memory |
| NYX | 0:85b3fd62ea1a | 168 | * configuration. |
| NYX | 0:85b3fd62ea1a | 169 | * @param None |
| NYX | 0:85b3fd62ea1a | 170 | * @retval None |
| NYX | 0:85b3fd62ea1a | 171 | */ |
| NYX | 0:85b3fd62ea1a | 172 | void SystemInit(void) |
| NYX | 0:85b3fd62ea1a | 173 | { |
| NYX | 0:85b3fd62ea1a | 174 | /* FPU settings ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 175 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| NYX | 0:85b3fd62ea1a | 176 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
| NYX | 0:85b3fd62ea1a | 177 | #endif |
| NYX | 0:85b3fd62ea1a | 178 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| NYX | 0:85b3fd62ea1a | 179 | /* Set HSION bit */ |
| NYX | 0:85b3fd62ea1a | 180 | RCC->CR |= (uint32_t)0x00000001; |
| NYX | 0:85b3fd62ea1a | 181 | |
| NYX | 0:85b3fd62ea1a | 182 | /* Reset CFGR register */ |
| NYX | 0:85b3fd62ea1a | 183 | RCC->CFGR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 184 | |
| NYX | 0:85b3fd62ea1a | 185 | /* Reset HSEON, CSSON and PLLON bits */ |
| NYX | 0:85b3fd62ea1a | 186 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| NYX | 0:85b3fd62ea1a | 187 | |
| NYX | 0:85b3fd62ea1a | 188 | /* Reset PLLCFGR register */ |
| NYX | 0:85b3fd62ea1a | 189 | RCC->PLLCFGR = 0x24003010; |
| NYX | 0:85b3fd62ea1a | 190 | |
| NYX | 0:85b3fd62ea1a | 191 | /* Reset HSEBYP bit */ |
| NYX | 0:85b3fd62ea1a | 192 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| NYX | 0:85b3fd62ea1a | 193 | |
| NYX | 0:85b3fd62ea1a | 194 | /* Disable all interrupts */ |
| NYX | 0:85b3fd62ea1a | 195 | RCC->CIR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 196 | |
| NYX | 0:85b3fd62ea1a | 197 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| NYX | 0:85b3fd62ea1a | 198 | SystemInit_ExtMemCtl(); |
| NYX | 0:85b3fd62ea1a | 199 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| NYX | 0:85b3fd62ea1a | 200 | |
| NYX | 0:85b3fd62ea1a | 201 | /* Configure the Vector Table location add offset address ------------------*/ |
| NYX | 0:85b3fd62ea1a | 202 | #ifdef VECT_TAB_SRAM |
| NYX | 0:85b3fd62ea1a | 203 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
| NYX | 0:85b3fd62ea1a | 204 | #else |
| NYX | 0:85b3fd62ea1a | 205 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| NYX | 0:85b3fd62ea1a | 206 | #endif |
| NYX | 0:85b3fd62ea1a | 207 | } |
| NYX | 0:85b3fd62ea1a | 208 | |
| NYX | 0:85b3fd62ea1a | 209 | /*+ MBED */ |
| NYX | 0:85b3fd62ea1a | 210 | #endif |
| NYX | 0:85b3fd62ea1a | 211 | /*- MBED */ |
| NYX | 0:85b3fd62ea1a | 212 | |
| NYX | 0:85b3fd62ea1a | 213 | /** |
| NYX | 0:85b3fd62ea1a | 214 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| NYX | 0:85b3fd62ea1a | 215 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| NYX | 0:85b3fd62ea1a | 216 | * be used by the user application to setup the SysTick timer or configure |
| NYX | 0:85b3fd62ea1a | 217 | * other parameters. |
| NYX | 0:85b3fd62ea1a | 218 | * |
| NYX | 0:85b3fd62ea1a | 219 | * @note Each time the core clock (HCLK) changes, this function must be called |
| NYX | 0:85b3fd62ea1a | 220 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| NYX | 0:85b3fd62ea1a | 221 | * based on this variable will be incorrect. |
| NYX | 0:85b3fd62ea1a | 222 | * |
| NYX | 0:85b3fd62ea1a | 223 | * @note - The system frequency computed by this function is not the real |
| NYX | 0:85b3fd62ea1a | 224 | * frequency in the chip. It is calculated based on the predefined |
| NYX | 0:85b3fd62ea1a | 225 | * constant and the selected clock source: |
| NYX | 0:85b3fd62ea1a | 226 | * |
| NYX | 0:85b3fd62ea1a | 227 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| NYX | 0:85b3fd62ea1a | 228 | * |
| NYX | 0:85b3fd62ea1a | 229 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| NYX | 0:85b3fd62ea1a | 230 | * |
| NYX | 0:85b3fd62ea1a | 231 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| NYX | 0:85b3fd62ea1a | 232 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| NYX | 0:85b3fd62ea1a | 233 | * |
| NYX | 0:85b3fd62ea1a | 234 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
| NYX | 0:85b3fd62ea1a | 235 | * 16 MHz) but the real value may vary depending on the variations |
| NYX | 0:85b3fd62ea1a | 236 | * in voltage and temperature. |
| NYX | 0:85b3fd62ea1a | 237 | * |
| NYX | 0:85b3fd62ea1a | 238 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value |
| NYX | 0:85b3fd62ea1a | 239 | * depends on the application requirements), user has to ensure that HSE_VALUE |
| NYX | 0:85b3fd62ea1a | 240 | * is same as the real frequency of the crystal used. Otherwise, this function |
| NYX | 0:85b3fd62ea1a | 241 | * may have wrong result. |
| NYX | 0:85b3fd62ea1a | 242 | * |
| NYX | 0:85b3fd62ea1a | 243 | * - The result of this function could be not correct when using fractional |
| NYX | 0:85b3fd62ea1a | 244 | * value for HSE crystal. |
| NYX | 0:85b3fd62ea1a | 245 | * |
| NYX | 0:85b3fd62ea1a | 246 | * @param None |
| NYX | 0:85b3fd62ea1a | 247 | * @retval None |
| NYX | 0:85b3fd62ea1a | 248 | */ |
| NYX | 0:85b3fd62ea1a | 249 | void SystemCoreClockUpdate(void) |
| NYX | 0:85b3fd62ea1a | 250 | { |
| NYX | 0:85b3fd62ea1a | 251 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
| NYX | 0:85b3fd62ea1a | 252 | |
| NYX | 0:85b3fd62ea1a | 253 | /* Get SYSCLK source -------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 254 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| NYX | 0:85b3fd62ea1a | 255 | |
| NYX | 0:85b3fd62ea1a | 256 | switch (tmp) |
| NYX | 0:85b3fd62ea1a | 257 | { |
| NYX | 0:85b3fd62ea1a | 258 | case 0x00: /* HSI used as system clock source */ |
| NYX | 0:85b3fd62ea1a | 259 | SystemCoreClock = HSI_VALUE; |
| NYX | 0:85b3fd62ea1a | 260 | break; |
| NYX | 0:85b3fd62ea1a | 261 | case 0x04: /* HSE used as system clock source */ |
| NYX | 0:85b3fd62ea1a | 262 | SystemCoreClock = HSE_VALUE; |
| NYX | 0:85b3fd62ea1a | 263 | break; |
| NYX | 0:85b3fd62ea1a | 264 | case 0x08: /* PLL used as system clock source */ |
| NYX | 0:85b3fd62ea1a | 265 | |
| NYX | 0:85b3fd62ea1a | 266 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
| NYX | 0:85b3fd62ea1a | 267 | SYSCLK = PLL_VCO / PLL_P |
| NYX | 0:85b3fd62ea1a | 268 | */ |
| NYX | 0:85b3fd62ea1a | 269 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
| NYX | 0:85b3fd62ea1a | 270 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
| NYX | 0:85b3fd62ea1a | 271 | |
| NYX | 0:85b3fd62ea1a | 272 | if (pllsource != 0) |
| NYX | 0:85b3fd62ea1a | 273 | { |
| NYX | 0:85b3fd62ea1a | 274 | /* HSE used as PLL clock source */ |
| NYX | 0:85b3fd62ea1a | 275 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| NYX | 0:85b3fd62ea1a | 276 | } |
| NYX | 0:85b3fd62ea1a | 277 | else |
| NYX | 0:85b3fd62ea1a | 278 | { |
| NYX | 0:85b3fd62ea1a | 279 | /* HSI used as PLL clock source */ |
| NYX | 0:85b3fd62ea1a | 280 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| NYX | 0:85b3fd62ea1a | 281 | } |
| NYX | 0:85b3fd62ea1a | 282 | |
| NYX | 0:85b3fd62ea1a | 283 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
| NYX | 0:85b3fd62ea1a | 284 | SystemCoreClock = pllvco/pllp; |
| NYX | 0:85b3fd62ea1a | 285 | break; |
| NYX | 0:85b3fd62ea1a | 286 | default: |
| NYX | 0:85b3fd62ea1a | 287 | SystemCoreClock = HSI_VALUE; |
| NYX | 0:85b3fd62ea1a | 288 | break; |
| NYX | 0:85b3fd62ea1a | 289 | } |
| NYX | 0:85b3fd62ea1a | 290 | /* Compute HCLK frequency --------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 291 | /* Get HCLK prescaler */ |
| NYX | 0:85b3fd62ea1a | 292 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| NYX | 0:85b3fd62ea1a | 293 | /* HCLK frequency */ |
| NYX | 0:85b3fd62ea1a | 294 | SystemCoreClock >>= tmp; |
| NYX | 0:85b3fd62ea1a | 295 | } |
| NYX | 0:85b3fd62ea1a | 296 | |
| NYX | 0:85b3fd62ea1a | 297 | #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) |
| NYX | 0:85b3fd62ea1a | 298 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| NYX | 0:85b3fd62ea1a | 299 | || defined(STM32F469xx) || defined(STM32F479xx) |
| NYX | 0:85b3fd62ea1a | 300 | /** |
| NYX | 0:85b3fd62ea1a | 301 | * @brief Setup the external memory controller. |
| NYX | 0:85b3fd62ea1a | 302 | * Called in startup_stm32f4xx.s before jump to main. |
| NYX | 0:85b3fd62ea1a | 303 | * This function configures the external memories (SRAM/SDRAM) |
| NYX | 0:85b3fd62ea1a | 304 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| NYX | 0:85b3fd62ea1a | 305 | * @param None |
| NYX | 0:85b3fd62ea1a | 306 | * @retval None |
| NYX | 0:85b3fd62ea1a | 307 | */ |
| NYX | 0:85b3fd62ea1a | 308 | void SystemInit_ExtMemCtl(void) |
| NYX | 0:85b3fd62ea1a | 309 | { |
| NYX | 0:85b3fd62ea1a | 310 | __IO uint32_t tmp = 0x00; |
| NYX | 0:85b3fd62ea1a | 311 | |
| NYX | 0:85b3fd62ea1a | 312 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| NYX | 0:85b3fd62ea1a | 313 | register __IO uint32_t index; |
| NYX | 0:85b3fd62ea1a | 314 | |
| NYX | 0:85b3fd62ea1a | 315 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ |
| NYX | 0:85b3fd62ea1a | 316 | RCC->AHB1ENR |= 0x000001F8; |
| NYX | 0:85b3fd62ea1a | 317 | |
| NYX | 0:85b3fd62ea1a | 318 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 319 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
| NYX | 0:85b3fd62ea1a | 320 | |
| NYX | 0:85b3fd62ea1a | 321 | /* Connect PDx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 322 | GPIOD->AFR[0] = 0x00CCC0CC; |
| NYX | 0:85b3fd62ea1a | 323 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 324 | /* Configure PDx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 325 | GPIOD->MODER = 0xAAAA0A8A; |
| NYX | 0:85b3fd62ea1a | 326 | /* Configure PDx pins speed to 100 MHz */ |
| NYX | 0:85b3fd62ea1a | 327 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| NYX | 0:85b3fd62ea1a | 328 | /* Configure PDx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 329 | GPIOD->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 330 | /* No pull-up, pull-down for PDx pins */ |
| NYX | 0:85b3fd62ea1a | 331 | GPIOD->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 332 | |
| NYX | 0:85b3fd62ea1a | 333 | /* Connect PEx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 334 | GPIOE->AFR[0] = 0xC00CC0CC; |
| NYX | 0:85b3fd62ea1a | 335 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 336 | /* Configure PEx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 337 | GPIOE->MODER = 0xAAAA828A; |
| NYX | 0:85b3fd62ea1a | 338 | /* Configure PEx pins speed to 100 MHz */ |
| NYX | 0:85b3fd62ea1a | 339 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| NYX | 0:85b3fd62ea1a | 340 | /* Configure PEx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 341 | GPIOE->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 342 | /* No pull-up, pull-down for PEx pins */ |
| NYX | 0:85b3fd62ea1a | 343 | GPIOE->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 344 | |
| NYX | 0:85b3fd62ea1a | 345 | /* Connect PFx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 346 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 347 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 348 | /* Configure PFx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 349 | GPIOF->MODER = 0xAA800AAA; |
| NYX | 0:85b3fd62ea1a | 350 | /* Configure PFx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 351 | GPIOF->OSPEEDR = 0xAA800AAA; |
| NYX | 0:85b3fd62ea1a | 352 | /* Configure PFx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 353 | GPIOF->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 354 | /* No pull-up, pull-down for PFx pins */ |
| NYX | 0:85b3fd62ea1a | 355 | GPIOF->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 356 | |
| NYX | 0:85b3fd62ea1a | 357 | /* Connect PGx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 358 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 359 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 360 | /* Configure PGx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 361 | GPIOG->MODER = 0xAAAAAAAA; |
| NYX | 0:85b3fd62ea1a | 362 | /* Configure PGx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 363 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| NYX | 0:85b3fd62ea1a | 364 | /* Configure PGx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 365 | GPIOG->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 366 | /* No pull-up, pull-down for PGx pins */ |
| NYX | 0:85b3fd62ea1a | 367 | GPIOG->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 368 | |
| NYX | 0:85b3fd62ea1a | 369 | /* Connect PHx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 370 | GPIOH->AFR[0] = 0x00C0CC00; |
| NYX | 0:85b3fd62ea1a | 371 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 372 | /* Configure PHx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 373 | GPIOH->MODER = 0xAAAA08A0; |
| NYX | 0:85b3fd62ea1a | 374 | /* Configure PHx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 375 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| NYX | 0:85b3fd62ea1a | 376 | /* Configure PHx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 377 | GPIOH->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 378 | /* No pull-up, pull-down for PHx pins */ |
| NYX | 0:85b3fd62ea1a | 379 | GPIOH->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 380 | |
| NYX | 0:85b3fd62ea1a | 381 | /* Connect PIx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 382 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 383 | GPIOI->AFR[1] = 0x00000CC0; |
| NYX | 0:85b3fd62ea1a | 384 | /* Configure PIx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 385 | GPIOI->MODER = 0x0028AAAA; |
| NYX | 0:85b3fd62ea1a | 386 | /* Configure PIx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 387 | GPIOI->OSPEEDR = 0x0028AAAA; |
| NYX | 0:85b3fd62ea1a | 388 | /* Configure PIx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 389 | GPIOI->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 390 | /* No pull-up, pull-down for PIx pins */ |
| NYX | 0:85b3fd62ea1a | 391 | GPIOI->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 392 | |
| NYX | 0:85b3fd62ea1a | 393 | /*-- FMC Configuration -------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 394 | /* Enable the FMC interface clock */ |
| NYX | 0:85b3fd62ea1a | 395 | RCC->AHB3ENR |= 0x00000001; |
| NYX | 0:85b3fd62ea1a | 396 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 397 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| NYX | 0:85b3fd62ea1a | 398 | |
| NYX | 0:85b3fd62ea1a | 399 | FMC_Bank5_6->SDCR[0] = 0x000019E4; |
| NYX | 0:85b3fd62ea1a | 400 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| NYX | 0:85b3fd62ea1a | 401 | |
| NYX | 0:85b3fd62ea1a | 402 | /* SDRAM initialization sequence */ |
| NYX | 0:85b3fd62ea1a | 403 | /* Clock enable command */ |
| NYX | 0:85b3fd62ea1a | 404 | FMC_Bank5_6->SDCMR = 0x00000011; |
| NYX | 0:85b3fd62ea1a | 405 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 406 | while((tmpreg != 0) && (timeout-- > 0)) |
| NYX | 0:85b3fd62ea1a | 407 | { |
| NYX | 0:85b3fd62ea1a | 408 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 409 | } |
| NYX | 0:85b3fd62ea1a | 410 | |
| NYX | 0:85b3fd62ea1a | 411 | /* Delay */ |
| NYX | 0:85b3fd62ea1a | 412 | for (index = 0; index<1000; index++); |
| NYX | 0:85b3fd62ea1a | 413 | |
| NYX | 0:85b3fd62ea1a | 414 | /* PALL command */ |
| NYX | 0:85b3fd62ea1a | 415 | FMC_Bank5_6->SDCMR = 0x00000012; |
| NYX | 0:85b3fd62ea1a | 416 | timeout = 0xFFFF; |
| NYX | 0:85b3fd62ea1a | 417 | while((tmpreg != 0) && (timeout-- > 0)) |
| NYX | 0:85b3fd62ea1a | 418 | { |
| NYX | 0:85b3fd62ea1a | 419 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 420 | } |
| NYX | 0:85b3fd62ea1a | 421 | |
| NYX | 0:85b3fd62ea1a | 422 | /* Auto refresh command */ |
| NYX | 0:85b3fd62ea1a | 423 | FMC_Bank5_6->SDCMR = 0x00000073; |
| NYX | 0:85b3fd62ea1a | 424 | timeout = 0xFFFF; |
| NYX | 0:85b3fd62ea1a | 425 | while((tmpreg != 0) && (timeout-- > 0)) |
| NYX | 0:85b3fd62ea1a | 426 | { |
| NYX | 0:85b3fd62ea1a | 427 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 428 | } |
| NYX | 0:85b3fd62ea1a | 429 | |
| NYX | 0:85b3fd62ea1a | 430 | /* MRD register program */ |
| NYX | 0:85b3fd62ea1a | 431 | FMC_Bank5_6->SDCMR = 0x00046014; |
| NYX | 0:85b3fd62ea1a | 432 | timeout = 0xFFFF; |
| NYX | 0:85b3fd62ea1a | 433 | while((tmpreg != 0) && (timeout-- > 0)) |
| NYX | 0:85b3fd62ea1a | 434 | { |
| NYX | 0:85b3fd62ea1a | 435 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 436 | } |
| NYX | 0:85b3fd62ea1a | 437 | |
| NYX | 0:85b3fd62ea1a | 438 | /* Set refresh count */ |
| NYX | 0:85b3fd62ea1a | 439 | tmpreg = FMC_Bank5_6->SDRTR; |
| NYX | 0:85b3fd62ea1a | 440 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| NYX | 0:85b3fd62ea1a | 441 | |
| NYX | 0:85b3fd62ea1a | 442 | /* Disable write protection */ |
| NYX | 0:85b3fd62ea1a | 443 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| NYX | 0:85b3fd62ea1a | 444 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| NYX | 0:85b3fd62ea1a | 445 | |
| NYX | 0:85b3fd62ea1a | 446 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| NYX | 0:85b3fd62ea1a | 447 | /* Configure and enable Bank1_SRAM2 */ |
| NYX | 0:85b3fd62ea1a | 448 | FMC_Bank1->BTCR[2] = 0x00001011; |
| NYX | 0:85b3fd62ea1a | 449 | FMC_Bank1->BTCR[3] = 0x00000201; |
| NYX | 0:85b3fd62ea1a | 450 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| NYX | 0:85b3fd62ea1a | 451 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| NYX | 0:85b3fd62ea1a | 452 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| NYX | 0:85b3fd62ea1a | 453 | /* Configure and enable Bank1_SRAM2 */ |
| NYX | 0:85b3fd62ea1a | 454 | FMC_Bank1->BTCR[2] = 0x00001091; |
| NYX | 0:85b3fd62ea1a | 455 | FMC_Bank1->BTCR[3] = 0x00110212; |
| NYX | 0:85b3fd62ea1a | 456 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| NYX | 0:85b3fd62ea1a | 457 | #endif /* STM32F469xx || STM32F479xx */ |
| NYX | 0:85b3fd62ea1a | 458 | |
| NYX | 0:85b3fd62ea1a | 459 | (void)(tmp); |
| NYX | 0:85b3fd62ea1a | 460 | } |
| NYX | 0:85b3fd62ea1a | 461 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| NYX | 0:85b3fd62ea1a | 462 | #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| NYX | 0:85b3fd62ea1a | 463 | /** |
| NYX | 0:85b3fd62ea1a | 464 | * @brief Setup the external memory controller. |
| NYX | 0:85b3fd62ea1a | 465 | * Called in startup_stm32f4xx.s before jump to main. |
| NYX | 0:85b3fd62ea1a | 466 | * This function configures the external memories (SRAM/SDRAM) |
| NYX | 0:85b3fd62ea1a | 467 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| NYX | 0:85b3fd62ea1a | 468 | * @param None |
| NYX | 0:85b3fd62ea1a | 469 | * @retval None |
| NYX | 0:85b3fd62ea1a | 470 | */ |
| NYX | 0:85b3fd62ea1a | 471 | void SystemInit_ExtMemCtl(void) |
| NYX | 0:85b3fd62ea1a | 472 | { |
| NYX | 0:85b3fd62ea1a | 473 | __IO uint32_t tmp = 0x00; |
| NYX | 0:85b3fd62ea1a | 474 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| NYX | 0:85b3fd62ea1a | 475 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| NYX | 0:85b3fd62ea1a | 476 | #if defined (DATA_IN_ExtSDRAM) |
| NYX | 0:85b3fd62ea1a | 477 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| NYX | 0:85b3fd62ea1a | 478 | register __IO uint32_t index; |
| NYX | 0:85b3fd62ea1a | 479 | |
| NYX | 0:85b3fd62ea1a | 480 | #if defined(STM32F446xx) |
| NYX | 0:85b3fd62ea1a | 481 | /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface |
| NYX | 0:85b3fd62ea1a | 482 | clock */ |
| NYX | 0:85b3fd62ea1a | 483 | RCC->AHB1ENR |= 0x0000007D; |
| NYX | 0:85b3fd62ea1a | 484 | #else |
| NYX | 0:85b3fd62ea1a | 485 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| NYX | 0:85b3fd62ea1a | 486 | clock */ |
| NYX | 0:85b3fd62ea1a | 487 | RCC->AHB1ENR |= 0x000001F8; |
| NYX | 0:85b3fd62ea1a | 488 | #endif /* STM32F446xx */ |
| NYX | 0:85b3fd62ea1a | 489 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 490 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
| NYX | 0:85b3fd62ea1a | 491 | |
| NYX | 0:85b3fd62ea1a | 492 | #if defined(STM32F446xx) |
| NYX | 0:85b3fd62ea1a | 493 | /* Connect PAx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 494 | GPIOA->AFR[0] |= 0xC0000000; |
| NYX | 0:85b3fd62ea1a | 495 | GPIOA->AFR[1] |= 0x00000000; |
| NYX | 0:85b3fd62ea1a | 496 | /* Configure PDx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 497 | GPIOA->MODER |= 0x00008000; |
| NYX | 0:85b3fd62ea1a | 498 | /* Configure PDx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 499 | GPIOA->OSPEEDR |= 0x00008000; |
| NYX | 0:85b3fd62ea1a | 500 | /* Configure PDx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 501 | GPIOA->OTYPER |= 0x00000000; |
| NYX | 0:85b3fd62ea1a | 502 | /* No pull-up, pull-down for PDx pins */ |
| NYX | 0:85b3fd62ea1a | 503 | GPIOA->PUPDR |= 0x00000000; |
| NYX | 0:85b3fd62ea1a | 504 | |
| NYX | 0:85b3fd62ea1a | 505 | /* Connect PCx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 506 | GPIOC->AFR[0] |= 0x00CC0000; |
| NYX | 0:85b3fd62ea1a | 507 | GPIOC->AFR[1] |= 0x00000000; |
| NYX | 0:85b3fd62ea1a | 508 | /* Configure PDx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 509 | GPIOC->MODER |= 0x00000A00; |
| NYX | 0:85b3fd62ea1a | 510 | /* Configure PDx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 511 | GPIOC->OSPEEDR |= 0x00000A00; |
| NYX | 0:85b3fd62ea1a | 512 | /* Configure PDx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 513 | GPIOC->OTYPER |= 0x00000000; |
| NYX | 0:85b3fd62ea1a | 514 | /* No pull-up, pull-down for PDx pins */ |
| NYX | 0:85b3fd62ea1a | 515 | GPIOC->PUPDR |= 0x00000000; |
| NYX | 0:85b3fd62ea1a | 516 | #endif /* STM32F446xx */ |
| NYX | 0:85b3fd62ea1a | 517 | |
| NYX | 0:85b3fd62ea1a | 518 | /* Connect PDx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 519 | GPIOD->AFR[0] = 0x000000CC; |
| NYX | 0:85b3fd62ea1a | 520 | GPIOD->AFR[1] = 0xCC000CCC; |
| NYX | 0:85b3fd62ea1a | 521 | /* Configure PDx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 522 | GPIOD->MODER = 0xA02A000A; |
| NYX | 0:85b3fd62ea1a | 523 | /* Configure PDx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 524 | GPIOD->OSPEEDR = 0xA02A000A; |
| NYX | 0:85b3fd62ea1a | 525 | /* Configure PDx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 526 | GPIOD->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 527 | /* No pull-up, pull-down for PDx pins */ |
| NYX | 0:85b3fd62ea1a | 528 | GPIOD->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 529 | |
| NYX | 0:85b3fd62ea1a | 530 | /* Connect PEx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 531 | GPIOE->AFR[0] = 0xC00000CC; |
| NYX | 0:85b3fd62ea1a | 532 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 533 | /* Configure PEx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 534 | GPIOE->MODER = 0xAAAA800A; |
| NYX | 0:85b3fd62ea1a | 535 | /* Configure PEx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 536 | GPIOE->OSPEEDR = 0xAAAA800A; |
| NYX | 0:85b3fd62ea1a | 537 | /* Configure PEx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 538 | GPIOE->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 539 | /* No pull-up, pull-down for PEx pins */ |
| NYX | 0:85b3fd62ea1a | 540 | GPIOE->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 541 | |
| NYX | 0:85b3fd62ea1a | 542 | /* Connect PFx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 543 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 544 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 545 | /* Configure PFx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 546 | GPIOF->MODER = 0xAA800AAA; |
| NYX | 0:85b3fd62ea1a | 547 | /* Configure PFx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 548 | GPIOF->OSPEEDR = 0xAA800AAA; |
| NYX | 0:85b3fd62ea1a | 549 | /* Configure PFx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 550 | GPIOF->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 551 | /* No pull-up, pull-down for PFx pins */ |
| NYX | 0:85b3fd62ea1a | 552 | GPIOF->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 553 | |
| NYX | 0:85b3fd62ea1a | 554 | /* Connect PGx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 555 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 556 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 557 | /* Configure PGx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 558 | GPIOG->MODER = 0xAAAAAAAA; |
| NYX | 0:85b3fd62ea1a | 559 | /* Configure PGx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 560 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| NYX | 0:85b3fd62ea1a | 561 | /* Configure PGx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 562 | GPIOG->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 563 | /* No pull-up, pull-down for PGx pins */ |
| NYX | 0:85b3fd62ea1a | 564 | GPIOG->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 565 | |
| NYX | 0:85b3fd62ea1a | 566 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| NYX | 0:85b3fd62ea1a | 567 | || defined(STM32F469xx) || defined(STM32F479xx) |
| NYX | 0:85b3fd62ea1a | 568 | /* Connect PHx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 569 | GPIOH->AFR[0] = 0x00C0CC00; |
| NYX | 0:85b3fd62ea1a | 570 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 571 | /* Configure PHx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 572 | GPIOH->MODER = 0xAAAA08A0; |
| NYX | 0:85b3fd62ea1a | 573 | /* Configure PHx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 574 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| NYX | 0:85b3fd62ea1a | 575 | /* Configure PHx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 576 | GPIOH->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 577 | /* No pull-up, pull-down for PHx pins */ |
| NYX | 0:85b3fd62ea1a | 578 | GPIOH->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 579 | |
| NYX | 0:85b3fd62ea1a | 580 | /* Connect PIx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 581 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 582 | GPIOI->AFR[1] = 0x00000CC0; |
| NYX | 0:85b3fd62ea1a | 583 | /* Configure PIx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 584 | GPIOI->MODER = 0x0028AAAA; |
| NYX | 0:85b3fd62ea1a | 585 | /* Configure PIx pins speed to 50 MHz */ |
| NYX | 0:85b3fd62ea1a | 586 | GPIOI->OSPEEDR = 0x0028AAAA; |
| NYX | 0:85b3fd62ea1a | 587 | /* Configure PIx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 588 | GPIOI->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 589 | /* No pull-up, pull-down for PIx pins */ |
| NYX | 0:85b3fd62ea1a | 590 | GPIOI->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 591 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| NYX | 0:85b3fd62ea1a | 592 | |
| NYX | 0:85b3fd62ea1a | 593 | /*-- FMC Configuration -------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 594 | /* Enable the FMC interface clock */ |
| NYX | 0:85b3fd62ea1a | 595 | RCC->AHB3ENR |= 0x00000001; |
| NYX | 0:85b3fd62ea1a | 596 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 597 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| NYX | 0:85b3fd62ea1a | 598 | |
| NYX | 0:85b3fd62ea1a | 599 | /* Configure and enable SDRAM bank1 */ |
| NYX | 0:85b3fd62ea1a | 600 | #if defined(STM32F446xx) |
| NYX | 0:85b3fd62ea1a | 601 | FMC_Bank5_6->SDCR[0] = 0x00001954; |
| NYX | 0:85b3fd62ea1a | 602 | #else |
| NYX | 0:85b3fd62ea1a | 603 | FMC_Bank5_6->SDCR[0] = 0x000019E4; |
| NYX | 0:85b3fd62ea1a | 604 | #endif /* STM32F446xx */ |
| NYX | 0:85b3fd62ea1a | 605 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| NYX | 0:85b3fd62ea1a | 606 | |
| NYX | 0:85b3fd62ea1a | 607 | /* SDRAM initialization sequence */ |
| NYX | 0:85b3fd62ea1a | 608 | /* Clock enable command */ |
| NYX | 0:85b3fd62ea1a | 609 | FMC_Bank5_6->SDCMR = 0x00000011; |
| NYX | 0:85b3fd62ea1a | 610 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 611 | while((tmpreg != 0) && (timeout-- > 0)) |
| NYX | 0:85b3fd62ea1a | 612 | { |
| NYX | 0:85b3fd62ea1a | 613 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 614 | } |
| NYX | 0:85b3fd62ea1a | 615 | |
| NYX | 0:85b3fd62ea1a | 616 | /* Delay */ |
| NYX | 0:85b3fd62ea1a | 617 | for (index = 0; index<1000; index++); |
| NYX | 0:85b3fd62ea1a | 618 | |
| NYX | 0:85b3fd62ea1a | 619 | /* PALL command */ |
| NYX | 0:85b3fd62ea1a | 620 | FMC_Bank5_6->SDCMR = 0x00000012; |
| NYX | 0:85b3fd62ea1a | 621 | timeout = 0xFFFF; |
| NYX | 0:85b3fd62ea1a | 622 | while((tmpreg != 0) && (timeout-- > 0)) |
| NYX | 0:85b3fd62ea1a | 623 | { |
| NYX | 0:85b3fd62ea1a | 624 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 625 | } |
| NYX | 0:85b3fd62ea1a | 626 | |
| NYX | 0:85b3fd62ea1a | 627 | /* Auto refresh command */ |
| NYX | 0:85b3fd62ea1a | 628 | #if defined(STM32F446xx) |
| NYX | 0:85b3fd62ea1a | 629 | FMC_Bank5_6->SDCMR = 0x000000F3; |
| NYX | 0:85b3fd62ea1a | 630 | #else |
| NYX | 0:85b3fd62ea1a | 631 | FMC_Bank5_6->SDCMR = 0x00000073; |
| NYX | 0:85b3fd62ea1a | 632 | #endif /* STM32F446xx */ |
| NYX | 0:85b3fd62ea1a | 633 | timeout = 0xFFFF; |
| NYX | 0:85b3fd62ea1a | 634 | while((tmpreg != 0) && (timeout-- > 0)) |
| NYX | 0:85b3fd62ea1a | 635 | { |
| NYX | 0:85b3fd62ea1a | 636 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 637 | } |
| NYX | 0:85b3fd62ea1a | 638 | |
| NYX | 0:85b3fd62ea1a | 639 | /* MRD register program */ |
| NYX | 0:85b3fd62ea1a | 640 | #if defined(STM32F446xx) |
| NYX | 0:85b3fd62ea1a | 641 | FMC_Bank5_6->SDCMR = 0x00044014; |
| NYX | 0:85b3fd62ea1a | 642 | #else |
| NYX | 0:85b3fd62ea1a | 643 | FMC_Bank5_6->SDCMR = 0x00046014; |
| NYX | 0:85b3fd62ea1a | 644 | #endif /* STM32F446xx */ |
| NYX | 0:85b3fd62ea1a | 645 | timeout = 0xFFFF; |
| NYX | 0:85b3fd62ea1a | 646 | while((tmpreg != 0) && (timeout-- > 0)) |
| NYX | 0:85b3fd62ea1a | 647 | { |
| NYX | 0:85b3fd62ea1a | 648 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| NYX | 0:85b3fd62ea1a | 649 | } |
| NYX | 0:85b3fd62ea1a | 650 | |
| NYX | 0:85b3fd62ea1a | 651 | /* Set refresh count */ |
| NYX | 0:85b3fd62ea1a | 652 | tmpreg = FMC_Bank5_6->SDRTR; |
| NYX | 0:85b3fd62ea1a | 653 | #if defined(STM32F446xx) |
| NYX | 0:85b3fd62ea1a | 654 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); |
| NYX | 0:85b3fd62ea1a | 655 | #else |
| NYX | 0:85b3fd62ea1a | 656 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| NYX | 0:85b3fd62ea1a | 657 | #endif /* STM32F446xx */ |
| NYX | 0:85b3fd62ea1a | 658 | |
| NYX | 0:85b3fd62ea1a | 659 | /* Disable write protection */ |
| NYX | 0:85b3fd62ea1a | 660 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| NYX | 0:85b3fd62ea1a | 661 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| NYX | 0:85b3fd62ea1a | 662 | #endif /* DATA_IN_ExtSDRAM */ |
| NYX | 0:85b3fd62ea1a | 663 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
| NYX | 0:85b3fd62ea1a | 664 | |
| NYX | 0:85b3fd62ea1a | 665 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| NYX | 0:85b3fd62ea1a | 666 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| NYX | 0:85b3fd62ea1a | 667 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) |
| NYX | 0:85b3fd62ea1a | 668 | |
| NYX | 0:85b3fd62ea1a | 669 | #if defined(DATA_IN_ExtSRAM) |
| NYX | 0:85b3fd62ea1a | 670 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 671 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| NYX | 0:85b3fd62ea1a | 672 | RCC->AHB1ENR |= 0x00000078; |
| NYX | 0:85b3fd62ea1a | 673 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 674 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); |
| NYX | 0:85b3fd62ea1a | 675 | |
| NYX | 0:85b3fd62ea1a | 676 | /* Connect PDx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 677 | GPIOD->AFR[0] = 0x00CCC0CC; |
| NYX | 0:85b3fd62ea1a | 678 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 679 | /* Configure PDx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 680 | GPIOD->MODER = 0xAAAA0A8A; |
| NYX | 0:85b3fd62ea1a | 681 | /* Configure PDx pins speed to 100 MHz */ |
| NYX | 0:85b3fd62ea1a | 682 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| NYX | 0:85b3fd62ea1a | 683 | /* Configure PDx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 684 | GPIOD->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 685 | /* No pull-up, pull-down for PDx pins */ |
| NYX | 0:85b3fd62ea1a | 686 | GPIOD->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 687 | |
| NYX | 0:85b3fd62ea1a | 688 | /* Connect PEx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 689 | GPIOE->AFR[0] = 0xC00CC0CC; |
| NYX | 0:85b3fd62ea1a | 690 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| NYX | 0:85b3fd62ea1a | 691 | /* Configure PEx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 692 | GPIOE->MODER = 0xAAAA828A; |
| NYX | 0:85b3fd62ea1a | 693 | /* Configure PEx pins speed to 100 MHz */ |
| NYX | 0:85b3fd62ea1a | 694 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| NYX | 0:85b3fd62ea1a | 695 | /* Configure PEx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 696 | GPIOE->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 697 | /* No pull-up, pull-down for PEx pins */ |
| NYX | 0:85b3fd62ea1a | 698 | GPIOE->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 699 | |
| NYX | 0:85b3fd62ea1a | 700 | /* Connect PFx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 701 | GPIOF->AFR[0] = 0x00CCCCCC; |
| NYX | 0:85b3fd62ea1a | 702 | GPIOF->AFR[1] = 0xCCCC0000; |
| NYX | 0:85b3fd62ea1a | 703 | /* Configure PFx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 704 | GPIOF->MODER = 0xAA000AAA; |
| NYX | 0:85b3fd62ea1a | 705 | /* Configure PFx pins speed to 100 MHz */ |
| NYX | 0:85b3fd62ea1a | 706 | GPIOF->OSPEEDR = 0xFF000FFF; |
| NYX | 0:85b3fd62ea1a | 707 | /* Configure PFx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 708 | GPIOF->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 709 | /* No pull-up, pull-down for PFx pins */ |
| NYX | 0:85b3fd62ea1a | 710 | GPIOF->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 711 | |
| NYX | 0:85b3fd62ea1a | 712 | /* Connect PGx pins to FMC Alternate function */ |
| NYX | 0:85b3fd62ea1a | 713 | GPIOG->AFR[0] = 0x00CCCCCC; |
| NYX | 0:85b3fd62ea1a | 714 | GPIOG->AFR[1] = 0x000000C0; |
| NYX | 0:85b3fd62ea1a | 715 | /* Configure PGx pins in Alternate function mode */ |
| NYX | 0:85b3fd62ea1a | 716 | GPIOG->MODER = 0x00085AAA; |
| NYX | 0:85b3fd62ea1a | 717 | /* Configure PGx pins speed to 100 MHz */ |
| NYX | 0:85b3fd62ea1a | 718 | GPIOG->OSPEEDR = 0x000CAFFF; |
| NYX | 0:85b3fd62ea1a | 719 | /* Configure PGx pins Output type to push-pull */ |
| NYX | 0:85b3fd62ea1a | 720 | GPIOG->OTYPER = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 721 | /* No pull-up, pull-down for PGx pins */ |
| NYX | 0:85b3fd62ea1a | 722 | GPIOG->PUPDR = 0x00000000; |
| NYX | 0:85b3fd62ea1a | 723 | |
| NYX | 0:85b3fd62ea1a | 724 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 725 | /* Enable the FMC/FSMC interface clock */ |
| NYX | 0:85b3fd62ea1a | 726 | RCC->AHB3ENR |= 0x00000001; |
| NYX | 0:85b3fd62ea1a | 727 | |
| NYX | 0:85b3fd62ea1a | 728 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| NYX | 0:85b3fd62ea1a | 729 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 730 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| NYX | 0:85b3fd62ea1a | 731 | /* Configure and enable Bank1_SRAM2 */ |
| NYX | 0:85b3fd62ea1a | 732 | FMC_Bank1->BTCR[2] = 0x00001011; |
| NYX | 0:85b3fd62ea1a | 733 | FMC_Bank1->BTCR[3] = 0x00000201; |
| NYX | 0:85b3fd62ea1a | 734 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| NYX | 0:85b3fd62ea1a | 735 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| NYX | 0:85b3fd62ea1a | 736 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| NYX | 0:85b3fd62ea1a | 737 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 738 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| NYX | 0:85b3fd62ea1a | 739 | /* Configure and enable Bank1_SRAM2 */ |
| NYX | 0:85b3fd62ea1a | 740 | FMC_Bank1->BTCR[2] = 0x00001091; |
| NYX | 0:85b3fd62ea1a | 741 | FMC_Bank1->BTCR[3] = 0x00110212; |
| NYX | 0:85b3fd62ea1a | 742 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| NYX | 0:85b3fd62ea1a | 743 | #endif /* STM32F469xx || STM32F479xx */ |
| NYX | 0:85b3fd62ea1a | 744 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ |
| NYX | 0:85b3fd62ea1a | 745 | || defined(STM32F412Zx) || defined(STM32F412Vx) |
| NYX | 0:85b3fd62ea1a | 746 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 747 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); |
| NYX | 0:85b3fd62ea1a | 748 | /* Configure and enable Bank1_SRAM2 */ |
| NYX | 0:85b3fd62ea1a | 749 | FSMC_Bank1->BTCR[2] = 0x00001011; |
| NYX | 0:85b3fd62ea1a | 750 | FSMC_Bank1->BTCR[3] = 0x00000201; |
| NYX | 0:85b3fd62ea1a | 751 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
| NYX | 0:85b3fd62ea1a | 752 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ |
| NYX | 0:85b3fd62ea1a | 753 | |
| NYX | 0:85b3fd62ea1a | 754 | #endif /* DATA_IN_ExtSRAM */ |
| NYX | 0:85b3fd62ea1a | 755 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ |
| NYX | 0:85b3fd62ea1a | 756 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ |
| NYX | 0:85b3fd62ea1a | 757 | (void)(tmp); |
| NYX | 0:85b3fd62ea1a | 758 | } |
| NYX | 0:85b3fd62ea1a | 759 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ |
| NYX | 0:85b3fd62ea1a | 760 | /** |
| NYX | 0:85b3fd62ea1a | 761 | * @} |
| NYX | 0:85b3fd62ea1a | 762 | */ |
| NYX | 0:85b3fd62ea1a | 763 | |
| NYX | 0:85b3fd62ea1a | 764 | /** |
| NYX | 0:85b3fd62ea1a | 765 | * @} |
| NYX | 0:85b3fd62ea1a | 766 | */ |
| NYX | 0:85b3fd62ea1a | 767 | |
| NYX | 0:85b3fd62ea1a | 768 | /** |
| NYX | 0:85b3fd62ea1a | 769 | * @} |
| NYX | 0:85b3fd62ea1a | 770 | */ |
| NYX | 0:85b3fd62ea1a | 771 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |