Takaaki Numai / mbed-dev

inport from local

Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_usart.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief USART LL module driver.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 38
NYX 0:85b3fd62ea1a 39 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 40 #include "stm32f4xx_ll_usart.h"
NYX 0:85b3fd62ea1a 41 #include "stm32f4xx_ll_rcc.h"
NYX 0:85b3fd62ea1a 42 #include "stm32f4xx_ll_bus.h"
NYX 0:85b3fd62ea1a 43 #ifdef USE_FULL_ASSERT
NYX 0:85b3fd62ea1a 44 #include "stm32_assert.h"
NYX 0:85b3fd62ea1a 45 #else
NYX 0:85b3fd62ea1a 46 #define assert_param(expr) ((void)0U)
NYX 0:85b3fd62ea1a 47 #endif
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /** @addtogroup STM32F4xx_LL_Driver
NYX 0:85b3fd62ea1a 50 * @{
NYX 0:85b3fd62ea1a 51 */
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 /** @addtogroup USART_LL
NYX 0:85b3fd62ea1a 56 * @{
NYX 0:85b3fd62ea1a 57 */
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 61 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 62 /** @addtogroup USART_LL_Private_Constants
NYX 0:85b3fd62ea1a 63 * @{
NYX 0:85b3fd62ea1a 64 */
NYX 0:85b3fd62ea1a 65
NYX 0:85b3fd62ea1a 66 /**
NYX 0:85b3fd62ea1a 67 * @}
NYX 0:85b3fd62ea1a 68 */
NYX 0:85b3fd62ea1a 69
NYX 0:85b3fd62ea1a 70
NYX 0:85b3fd62ea1a 71 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 72 /** @addtogroup USART_LL_Private_Macros
NYX 0:85b3fd62ea1a 73 * @{
NYX 0:85b3fd62ea1a 74 */
NYX 0:85b3fd62ea1a 75
NYX 0:85b3fd62ea1a 76 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
NYX 0:85b3fd62ea1a 77 * divided by the smallest oversampling used on the USART (i.e. 8) */
NYX 0:85b3fd62ea1a 78 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
NYX 0:85b3fd62ea1a 79
NYX 0:85b3fd62ea1a 80 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
NYX 0:85b3fd62ea1a 81 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
NYX 0:85b3fd62ea1a 82 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
NYX 0:85b3fd62ea1a 83 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
NYX 0:85b3fd62ea1a 84
NYX 0:85b3fd62ea1a 85 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
NYX 0:85b3fd62ea1a 86 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
NYX 0:85b3fd62ea1a 87 || ((__VALUE__) == LL_USART_PARITY_ODD))
NYX 0:85b3fd62ea1a 88
NYX 0:85b3fd62ea1a 89 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
NYX 0:85b3fd62ea1a 90 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
NYX 0:85b3fd62ea1a 91
NYX 0:85b3fd62ea1a 92 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
NYX 0:85b3fd62ea1a 93 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
NYX 0:85b3fd62ea1a 94
NYX 0:85b3fd62ea1a 95 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
NYX 0:85b3fd62ea1a 96 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
NYX 0:85b3fd62ea1a 97
NYX 0:85b3fd62ea1a 98 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
NYX 0:85b3fd62ea1a 99 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
NYX 0:85b3fd62ea1a 102 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
NYX 0:85b3fd62ea1a 103
NYX 0:85b3fd62ea1a 104 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
NYX 0:85b3fd62ea1a 105 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
NYX 0:85b3fd62ea1a 108 || ((__VALUE__) == LL_USART_STOPBITS_1) \
NYX 0:85b3fd62ea1a 109 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
NYX 0:85b3fd62ea1a 110 || ((__VALUE__) == LL_USART_STOPBITS_2))
NYX 0:85b3fd62ea1a 111
NYX 0:85b3fd62ea1a 112 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
NYX 0:85b3fd62ea1a 113 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
NYX 0:85b3fd62ea1a 114 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
NYX 0:85b3fd62ea1a 115 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
NYX 0:85b3fd62ea1a 116
NYX 0:85b3fd62ea1a 117 /**
NYX 0:85b3fd62ea1a 118 * @}
NYX 0:85b3fd62ea1a 119 */
NYX 0:85b3fd62ea1a 120
NYX 0:85b3fd62ea1a 121 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 122
NYX 0:85b3fd62ea1a 123 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 124 /** @addtogroup USART_LL_Exported_Functions
NYX 0:85b3fd62ea1a 125 * @{
NYX 0:85b3fd62ea1a 126 */
NYX 0:85b3fd62ea1a 127
NYX 0:85b3fd62ea1a 128 /** @addtogroup USART_LL_EF_Init
NYX 0:85b3fd62ea1a 129 * @{
NYX 0:85b3fd62ea1a 130 */
NYX 0:85b3fd62ea1a 131
NYX 0:85b3fd62ea1a 132 /**
NYX 0:85b3fd62ea1a 133 * @brief De-initialize USART registers (Registers restored to their default values).
NYX 0:85b3fd62ea1a 134 * @param USARTx USART Instance
NYX 0:85b3fd62ea1a 135 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 136 * - SUCCESS: USART registers are de-initialized
NYX 0:85b3fd62ea1a 137 * - ERROR: USART registers are not de-initialized
NYX 0:85b3fd62ea1a 138 */
NYX 0:85b3fd62ea1a 139 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
NYX 0:85b3fd62ea1a 140 {
NYX 0:85b3fd62ea1a 141 ErrorStatus status = SUCCESS;
NYX 0:85b3fd62ea1a 142
NYX 0:85b3fd62ea1a 143 /* Check the parameters */
NYX 0:85b3fd62ea1a 144 assert_param(IS_UART_INSTANCE(USARTx));
NYX 0:85b3fd62ea1a 145
NYX 0:85b3fd62ea1a 146 if (USARTx == USART1)
NYX 0:85b3fd62ea1a 147 {
NYX 0:85b3fd62ea1a 148 /* Force reset of USART clock */
NYX 0:85b3fd62ea1a 149 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
NYX 0:85b3fd62ea1a 150
NYX 0:85b3fd62ea1a 151 /* Release reset of USART clock */
NYX 0:85b3fd62ea1a 152 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
NYX 0:85b3fd62ea1a 153 }
NYX 0:85b3fd62ea1a 154 else if (USARTx == USART2)
NYX 0:85b3fd62ea1a 155 {
NYX 0:85b3fd62ea1a 156 /* Force reset of USART clock */
NYX 0:85b3fd62ea1a 157 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
NYX 0:85b3fd62ea1a 158
NYX 0:85b3fd62ea1a 159 /* Release reset of USART clock */
NYX 0:85b3fd62ea1a 160 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
NYX 0:85b3fd62ea1a 161 }
NYX 0:85b3fd62ea1a 162 #if defined(USART3)
NYX 0:85b3fd62ea1a 163 else if (USARTx == USART3)
NYX 0:85b3fd62ea1a 164 {
NYX 0:85b3fd62ea1a 165 /* Force reset of USART clock */
NYX 0:85b3fd62ea1a 166 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
NYX 0:85b3fd62ea1a 167
NYX 0:85b3fd62ea1a 168 /* Release reset of USART clock */
NYX 0:85b3fd62ea1a 169 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
NYX 0:85b3fd62ea1a 170 }
NYX 0:85b3fd62ea1a 171 #endif /* USART3 */
NYX 0:85b3fd62ea1a 172 #if defined(USART6)
NYX 0:85b3fd62ea1a 173 else if (USARTx == USART6)
NYX 0:85b3fd62ea1a 174 {
NYX 0:85b3fd62ea1a 175 /* Force reset of USART clock */
NYX 0:85b3fd62ea1a 176 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
NYX 0:85b3fd62ea1a 177
NYX 0:85b3fd62ea1a 178 /* Release reset of USART clock */
NYX 0:85b3fd62ea1a 179 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
NYX 0:85b3fd62ea1a 180 }
NYX 0:85b3fd62ea1a 181 #endif /* USART6 */
NYX 0:85b3fd62ea1a 182 #if defined(UART4)
NYX 0:85b3fd62ea1a 183 else if (USARTx == UART4)
NYX 0:85b3fd62ea1a 184 {
NYX 0:85b3fd62ea1a 185 /* Force reset of UART clock */
NYX 0:85b3fd62ea1a 186 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
NYX 0:85b3fd62ea1a 187
NYX 0:85b3fd62ea1a 188 /* Release reset of UART clock */
NYX 0:85b3fd62ea1a 189 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
NYX 0:85b3fd62ea1a 190 }
NYX 0:85b3fd62ea1a 191 #endif /* UART4 */
NYX 0:85b3fd62ea1a 192 #if defined(UART5)
NYX 0:85b3fd62ea1a 193 else if (USARTx == UART5)
NYX 0:85b3fd62ea1a 194 {
NYX 0:85b3fd62ea1a 195 /* Force reset of UART clock */
NYX 0:85b3fd62ea1a 196 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
NYX 0:85b3fd62ea1a 197
NYX 0:85b3fd62ea1a 198 /* Release reset of UART clock */
NYX 0:85b3fd62ea1a 199 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
NYX 0:85b3fd62ea1a 200 }
NYX 0:85b3fd62ea1a 201 #endif /* UART5 */
NYX 0:85b3fd62ea1a 202 #if defined(UART7)
NYX 0:85b3fd62ea1a 203 else if (USARTx == UART7)
NYX 0:85b3fd62ea1a 204 {
NYX 0:85b3fd62ea1a 205 /* Force reset of UART clock */
NYX 0:85b3fd62ea1a 206 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
NYX 0:85b3fd62ea1a 207
NYX 0:85b3fd62ea1a 208 /* Release reset of UART clock */
NYX 0:85b3fd62ea1a 209 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
NYX 0:85b3fd62ea1a 210 }
NYX 0:85b3fd62ea1a 211 #endif /* UART7 */
NYX 0:85b3fd62ea1a 212 #if defined(UART8)
NYX 0:85b3fd62ea1a 213 else if (USARTx == UART8)
NYX 0:85b3fd62ea1a 214 {
NYX 0:85b3fd62ea1a 215 /* Force reset of UART clock */
NYX 0:85b3fd62ea1a 216 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
NYX 0:85b3fd62ea1a 217
NYX 0:85b3fd62ea1a 218 /* Release reset of UART clock */
NYX 0:85b3fd62ea1a 219 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
NYX 0:85b3fd62ea1a 220 }
NYX 0:85b3fd62ea1a 221 #endif /* UART8 */
NYX 0:85b3fd62ea1a 222 #if defined(UART9)
NYX 0:85b3fd62ea1a 223 else if (USARTx == UART9)
NYX 0:85b3fd62ea1a 224 {
NYX 0:85b3fd62ea1a 225 /* Force reset of UART clock */
NYX 0:85b3fd62ea1a 226 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
NYX 0:85b3fd62ea1a 227
NYX 0:85b3fd62ea1a 228 /* Release reset of UART clock */
NYX 0:85b3fd62ea1a 229 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
NYX 0:85b3fd62ea1a 230 }
NYX 0:85b3fd62ea1a 231 #endif /* UART9 */
NYX 0:85b3fd62ea1a 232 #if defined(UART10)
NYX 0:85b3fd62ea1a 233 else if (USARTx == UART10)
NYX 0:85b3fd62ea1a 234 {
NYX 0:85b3fd62ea1a 235 /* Force reset of UART clock */
NYX 0:85b3fd62ea1a 236 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART10);
NYX 0:85b3fd62ea1a 237
NYX 0:85b3fd62ea1a 238 /* Release reset of UART clock */
NYX 0:85b3fd62ea1a 239 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART10);
NYX 0:85b3fd62ea1a 240 }
NYX 0:85b3fd62ea1a 241 #endif /* UART10 */
NYX 0:85b3fd62ea1a 242 else
NYX 0:85b3fd62ea1a 243 {
NYX 0:85b3fd62ea1a 244 status = ERROR;
NYX 0:85b3fd62ea1a 245 }
NYX 0:85b3fd62ea1a 246
NYX 0:85b3fd62ea1a 247 return (status);
NYX 0:85b3fd62ea1a 248 }
NYX 0:85b3fd62ea1a 249
NYX 0:85b3fd62ea1a 250 /**
NYX 0:85b3fd62ea1a 251 * @brief Initialize USART registers according to the specified
NYX 0:85b3fd62ea1a 252 * parameters in USART_InitStruct.
NYX 0:85b3fd62ea1a 253 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
NYX 0:85b3fd62ea1a 254 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
NYX 0:85b3fd62ea1a 255 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
NYX 0:85b3fd62ea1a 256 * @param USARTx USART Instance
NYX 0:85b3fd62ea1a 257 * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
NYX 0:85b3fd62ea1a 258 * that contains the configuration information for the specified USART peripheral.
NYX 0:85b3fd62ea1a 259 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 260 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
NYX 0:85b3fd62ea1a 261 * - ERROR: Problem occurred during USART Registers initialization
NYX 0:85b3fd62ea1a 262 */
NYX 0:85b3fd62ea1a 263 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
NYX 0:85b3fd62ea1a 264 {
NYX 0:85b3fd62ea1a 265 ErrorStatus status = ERROR;
NYX 0:85b3fd62ea1a 266 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 267 LL_RCC_ClocksTypeDef rcc_clocks;
NYX 0:85b3fd62ea1a 268
NYX 0:85b3fd62ea1a 269 /* Check the parameters */
NYX 0:85b3fd62ea1a 270 assert_param(IS_UART_INSTANCE(USARTx));
NYX 0:85b3fd62ea1a 271 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
NYX 0:85b3fd62ea1a 272 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
NYX 0:85b3fd62ea1a 273 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
NYX 0:85b3fd62ea1a 274 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
NYX 0:85b3fd62ea1a 275 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
NYX 0:85b3fd62ea1a 276 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
NYX 0:85b3fd62ea1a 277 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
NYX 0:85b3fd62ea1a 278
NYX 0:85b3fd62ea1a 279 /* USART needs to be in disabled state, in order to be able to configure some bits in
NYX 0:85b3fd62ea1a 280 CRx registers */
NYX 0:85b3fd62ea1a 281 if (LL_USART_IsEnabled(USARTx) == 0U)
NYX 0:85b3fd62ea1a 282 {
NYX 0:85b3fd62ea1a 283 /*---------------------------- USART CR1 Configuration -----------------------
NYX 0:85b3fd62ea1a 284 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
NYX 0:85b3fd62ea1a 285 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
NYX 0:85b3fd62ea1a 286 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
NYX 0:85b3fd62ea1a 287 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
NYX 0:85b3fd62ea1a 288 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
NYX 0:85b3fd62ea1a 289 */
NYX 0:85b3fd62ea1a 290 MODIFY_REG(USARTx->CR1,
NYX 0:85b3fd62ea1a 291 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
NYX 0:85b3fd62ea1a 292 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
NYX 0:85b3fd62ea1a 293 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
NYX 0:85b3fd62ea1a 294 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
NYX 0:85b3fd62ea1a 295
NYX 0:85b3fd62ea1a 296 /*---------------------------- USART CR2 Configuration -----------------------
NYX 0:85b3fd62ea1a 297 * Configure USARTx CR2 (Stop bits) with parameters:
NYX 0:85b3fd62ea1a 298 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
NYX 0:85b3fd62ea1a 299 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
NYX 0:85b3fd62ea1a 300 */
NYX 0:85b3fd62ea1a 301 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
NYX 0:85b3fd62ea1a 302
NYX 0:85b3fd62ea1a 303 /*---------------------------- USART CR3 Configuration -----------------------
NYX 0:85b3fd62ea1a 304 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
NYX 0:85b3fd62ea1a 305 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
NYX 0:85b3fd62ea1a 306 */
NYX 0:85b3fd62ea1a 307 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
NYX 0:85b3fd62ea1a 308
NYX 0:85b3fd62ea1a 309 /*---------------------------- USART BRR Configuration -----------------------
NYX 0:85b3fd62ea1a 310 * Retrieve Clock frequency used for USART Peripheral
NYX 0:85b3fd62ea1a 311 */
NYX 0:85b3fd62ea1a 312 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
NYX 0:85b3fd62ea1a 313 if (USARTx == USART1)
NYX 0:85b3fd62ea1a 314 {
NYX 0:85b3fd62ea1a 315 periphclk = rcc_clocks.PCLK2_Frequency;
NYX 0:85b3fd62ea1a 316 }
NYX 0:85b3fd62ea1a 317 else if (USARTx == USART2)
NYX 0:85b3fd62ea1a 318 {
NYX 0:85b3fd62ea1a 319 periphclk = rcc_clocks.PCLK1_Frequency;
NYX 0:85b3fd62ea1a 320 }
NYX 0:85b3fd62ea1a 321 #if defined(USART3)
NYX 0:85b3fd62ea1a 322 else if (USARTx == USART3)
NYX 0:85b3fd62ea1a 323 {
NYX 0:85b3fd62ea1a 324 periphclk = rcc_clocks.PCLK1_Frequency;
NYX 0:85b3fd62ea1a 325 }
NYX 0:85b3fd62ea1a 326 #endif /* USART3 */
NYX 0:85b3fd62ea1a 327 #if defined(USART6)
NYX 0:85b3fd62ea1a 328 else if (USARTx == USART6)
NYX 0:85b3fd62ea1a 329 {
NYX 0:85b3fd62ea1a 330 periphclk = rcc_clocks.PCLK2_Frequency;
NYX 0:85b3fd62ea1a 331 }
NYX 0:85b3fd62ea1a 332 #endif /* USART6 */
NYX 0:85b3fd62ea1a 333 #if defined(UART4)
NYX 0:85b3fd62ea1a 334 else if (USARTx == UART4)
NYX 0:85b3fd62ea1a 335 {
NYX 0:85b3fd62ea1a 336 periphclk = rcc_clocks.PCLK1_Frequency;
NYX 0:85b3fd62ea1a 337 }
NYX 0:85b3fd62ea1a 338 #endif /* UART4 */
NYX 0:85b3fd62ea1a 339 #if defined(UART5)
NYX 0:85b3fd62ea1a 340 else if (USARTx == UART5)
NYX 0:85b3fd62ea1a 341 {
NYX 0:85b3fd62ea1a 342 periphclk = rcc_clocks.PCLK1_Frequency;
NYX 0:85b3fd62ea1a 343 }
NYX 0:85b3fd62ea1a 344 #endif /* UART5 */
NYX 0:85b3fd62ea1a 345 #if defined(UART7)
NYX 0:85b3fd62ea1a 346 else if (USARTx == UART7)
NYX 0:85b3fd62ea1a 347 {
NYX 0:85b3fd62ea1a 348 periphclk = rcc_clocks.PCLK1_Frequency;
NYX 0:85b3fd62ea1a 349 }
NYX 0:85b3fd62ea1a 350 #endif /* UART7 */
NYX 0:85b3fd62ea1a 351 #if defined(UART8)
NYX 0:85b3fd62ea1a 352 else if (USARTx == UART8)
NYX 0:85b3fd62ea1a 353 {
NYX 0:85b3fd62ea1a 354 periphclk = rcc_clocks.PCLK1_Frequency;
NYX 0:85b3fd62ea1a 355 }
NYX 0:85b3fd62ea1a 356 #endif /* UART8 */
NYX 0:85b3fd62ea1a 357 #if defined(UART9)
NYX 0:85b3fd62ea1a 358 else if (USARTx == UART9)
NYX 0:85b3fd62ea1a 359 {
NYX 0:85b3fd62ea1a 360 periphclk = rcc_clocks.PCLK1_Frequency;
NYX 0:85b3fd62ea1a 361 }
NYX 0:85b3fd62ea1a 362 #endif /* UART9 */
NYX 0:85b3fd62ea1a 363 #if defined(UART10)
NYX 0:85b3fd62ea1a 364 else if (USARTx == UART5)
NYX 0:85b3fd62ea1a 365 {
NYX 0:85b3fd62ea1a 366 periphclk = rcc_clocks.PCLK1_Frequency;
NYX 0:85b3fd62ea1a 367 }
NYX 0:85b3fd62ea1a 368 #endif /* UART10 */
NYX 0:85b3fd62ea1a 369 else
NYX 0:85b3fd62ea1a 370 {
NYX 0:85b3fd62ea1a 371 /* Nothing to do, as error code is already assigned to ERROR value */
NYX 0:85b3fd62ea1a 372 }
NYX 0:85b3fd62ea1a 373
NYX 0:85b3fd62ea1a 374 /* Configure the USART Baud Rate :
NYX 0:85b3fd62ea1a 375 - valid baud rate value (different from 0) is required
NYX 0:85b3fd62ea1a 376 - Peripheral clock as returned by RCC service, should be valid (different from 0).
NYX 0:85b3fd62ea1a 377 */
NYX 0:85b3fd62ea1a 378 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
NYX 0:85b3fd62ea1a 379 && (USART_InitStruct->BaudRate != 0U))
NYX 0:85b3fd62ea1a 380 {
NYX 0:85b3fd62ea1a 381 status = SUCCESS;
NYX 0:85b3fd62ea1a 382 LL_USART_SetBaudRate(USARTx,
NYX 0:85b3fd62ea1a 383 periphclk,
NYX 0:85b3fd62ea1a 384 USART_InitStruct->OverSampling,
NYX 0:85b3fd62ea1a 385 USART_InitStruct->BaudRate);
NYX 0:85b3fd62ea1a 386 }
NYX 0:85b3fd62ea1a 387 }
NYX 0:85b3fd62ea1a 388 /* Endif (=> USART not in Disabled state => return ERROR) */
NYX 0:85b3fd62ea1a 389
NYX 0:85b3fd62ea1a 390 return (status);
NYX 0:85b3fd62ea1a 391 }
NYX 0:85b3fd62ea1a 392
NYX 0:85b3fd62ea1a 393 /**
NYX 0:85b3fd62ea1a 394 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
NYX 0:85b3fd62ea1a 395 * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
NYX 0:85b3fd62ea1a 396 * whose fields will be set to default values.
NYX 0:85b3fd62ea1a 397 * @retval None
NYX 0:85b3fd62ea1a 398 */
NYX 0:85b3fd62ea1a 399
NYX 0:85b3fd62ea1a 400 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
NYX 0:85b3fd62ea1a 401 {
NYX 0:85b3fd62ea1a 402 /* Set USART_InitStruct fields to default values */
NYX 0:85b3fd62ea1a 403 USART_InitStruct->BaudRate = 9600U;
NYX 0:85b3fd62ea1a 404 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
NYX 0:85b3fd62ea1a 405 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
NYX 0:85b3fd62ea1a 406 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
NYX 0:85b3fd62ea1a 407 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
NYX 0:85b3fd62ea1a 408 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
NYX 0:85b3fd62ea1a 409 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
NYX 0:85b3fd62ea1a 410 }
NYX 0:85b3fd62ea1a 411
NYX 0:85b3fd62ea1a 412 /**
NYX 0:85b3fd62ea1a 413 * @brief Initialize USART Clock related settings according to the
NYX 0:85b3fd62ea1a 414 * specified parameters in the USART_ClockInitStruct.
NYX 0:85b3fd62ea1a 415 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
NYX 0:85b3fd62ea1a 416 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
NYX 0:85b3fd62ea1a 417 * @param USARTx USART Instance
NYX 0:85b3fd62ea1a 418 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
NYX 0:85b3fd62ea1a 419 * that contains the Clock configuration information for the specified USART peripheral.
NYX 0:85b3fd62ea1a 420 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 421 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
NYX 0:85b3fd62ea1a 422 * - ERROR: Problem occurred during USART Registers initialization
NYX 0:85b3fd62ea1a 423 */
NYX 0:85b3fd62ea1a 424 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
NYX 0:85b3fd62ea1a 425 {
NYX 0:85b3fd62ea1a 426 ErrorStatus status = SUCCESS;
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 /* Check USART Instance and Clock signal output parameters */
NYX 0:85b3fd62ea1a 429 assert_param(IS_UART_INSTANCE(USARTx));
NYX 0:85b3fd62ea1a 430 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
NYX 0:85b3fd62ea1a 431
NYX 0:85b3fd62ea1a 432 /* USART needs to be in disabled state, in order to be able to configure some bits in
NYX 0:85b3fd62ea1a 433 CRx registers */
NYX 0:85b3fd62ea1a 434 if (LL_USART_IsEnabled(USARTx) == 0U)
NYX 0:85b3fd62ea1a 435 {
NYX 0:85b3fd62ea1a 436 /*---------------------------- USART CR2 Configuration -----------------------*/
NYX 0:85b3fd62ea1a 437 /* If Clock signal has to be output */
NYX 0:85b3fd62ea1a 438 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
NYX 0:85b3fd62ea1a 439 {
NYX 0:85b3fd62ea1a 440 /* Deactivate Clock signal delivery :
NYX 0:85b3fd62ea1a 441 * - Disable Clock Output: USART_CR2_CLKEN cleared
NYX 0:85b3fd62ea1a 442 */
NYX 0:85b3fd62ea1a 443 LL_USART_DisableSCLKOutput(USARTx);
NYX 0:85b3fd62ea1a 444 }
NYX 0:85b3fd62ea1a 445 else
NYX 0:85b3fd62ea1a 446 {
NYX 0:85b3fd62ea1a 447 /* Ensure USART instance is USART capable */
NYX 0:85b3fd62ea1a 448 assert_param(IS_USART_INSTANCE(USARTx));
NYX 0:85b3fd62ea1a 449
NYX 0:85b3fd62ea1a 450 /* Check clock related parameters */
NYX 0:85b3fd62ea1a 451 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
NYX 0:85b3fd62ea1a 452 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
NYX 0:85b3fd62ea1a 453 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
NYX 0:85b3fd62ea1a 454
NYX 0:85b3fd62ea1a 455 /*---------------------------- USART CR2 Configuration -----------------------
NYX 0:85b3fd62ea1a 456 * Configure USARTx CR2 (Clock signal related bits) with parameters:
NYX 0:85b3fd62ea1a 457 * - Enable Clock Output: USART_CR2_CLKEN set
NYX 0:85b3fd62ea1a 458 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
NYX 0:85b3fd62ea1a 459 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
NYX 0:85b3fd62ea1a 460 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
NYX 0:85b3fd62ea1a 461 */
NYX 0:85b3fd62ea1a 462 MODIFY_REG(USARTx->CR2,
NYX 0:85b3fd62ea1a 463 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
NYX 0:85b3fd62ea1a 464 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
NYX 0:85b3fd62ea1a 465 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
NYX 0:85b3fd62ea1a 466 }
NYX 0:85b3fd62ea1a 467 }
NYX 0:85b3fd62ea1a 468 /* Else (USART not in Disabled state => return ERROR */
NYX 0:85b3fd62ea1a 469 else
NYX 0:85b3fd62ea1a 470 {
NYX 0:85b3fd62ea1a 471 status = ERROR;
NYX 0:85b3fd62ea1a 472 }
NYX 0:85b3fd62ea1a 473
NYX 0:85b3fd62ea1a 474 return (status);
NYX 0:85b3fd62ea1a 475 }
NYX 0:85b3fd62ea1a 476
NYX 0:85b3fd62ea1a 477 /**
NYX 0:85b3fd62ea1a 478 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
NYX 0:85b3fd62ea1a 479 * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
NYX 0:85b3fd62ea1a 480 * whose fields will be set to default values.
NYX 0:85b3fd62ea1a 481 * @retval None
NYX 0:85b3fd62ea1a 482 */
NYX 0:85b3fd62ea1a 483 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
NYX 0:85b3fd62ea1a 484 {
NYX 0:85b3fd62ea1a 485 /* Set LL_USART_ClockInitStruct fields with default values */
NYX 0:85b3fd62ea1a 486 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
NYX 0:85b3fd62ea1a 487 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
NYX 0:85b3fd62ea1a 488 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
NYX 0:85b3fd62ea1a 489 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
NYX 0:85b3fd62ea1a 490 }
NYX 0:85b3fd62ea1a 491
NYX 0:85b3fd62ea1a 492 /**
NYX 0:85b3fd62ea1a 493 * @}
NYX 0:85b3fd62ea1a 494 */
NYX 0:85b3fd62ea1a 495
NYX 0:85b3fd62ea1a 496 /**
NYX 0:85b3fd62ea1a 497 * @}
NYX 0:85b3fd62ea1a 498 */
NYX 0:85b3fd62ea1a 499
NYX 0:85b3fd62ea1a 500 /**
NYX 0:85b3fd62ea1a 501 * @}
NYX 0:85b3fd62ea1a 502 */
NYX 0:85b3fd62ea1a 503
NYX 0:85b3fd62ea1a 504 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
NYX 0:85b3fd62ea1a 505
NYX 0:85b3fd62ea1a 506 /**
NYX 0:85b3fd62ea1a 507 * @}
NYX 0:85b3fd62ea1a 508 */
NYX 0:85b3fd62ea1a 509
NYX 0:85b3fd62ea1a 510 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 511
NYX 0:85b3fd62ea1a 512 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
NYX 0:85b3fd62ea1a 513