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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

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User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_ll_tim.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of TIM LL module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_LL_TIM_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_LL_TIM_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	47	#include "stm32f4xx.h"
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_LL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14)
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/** @defgroup TIM_LL TIM
NYX	0:85b3fd62ea1a	56	* @{
NYX	0:85b3fd62ea1a	57	*/
NYX	0:85b3fd62ea1a	58
NYX	0:85b3fd62ea1a	59	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	60	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	61	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
NYX	0:85b3fd62ea1a	62	* @{
NYX	0:85b3fd62ea1a	63	*/
NYX	0:85b3fd62ea1a	64	static const uint8_t OFFSET_TAB_CCMRx[] =
NYX	0:85b3fd62ea1a	65	{
NYX	0:85b3fd62ea1a	66	0x00U, /* 0: TIMx_CH1 */
NYX	0:85b3fd62ea1a	67	0x00U, /* 1: TIMx_CH1N */
NYX	0:85b3fd62ea1a	68	0x00U, /* 2: TIMx_CH2 */
NYX	0:85b3fd62ea1a	69	0x00U, /* 3: TIMx_CH2N */
NYX	0:85b3fd62ea1a	70	0x04U, /* 4: TIMx_CH3 */
NYX	0:85b3fd62ea1a	71	0x04U, /* 5: TIMx_CH3N */
NYX	0:85b3fd62ea1a	72	0x04U /* 6: TIMx_CH4 */
NYX	0:85b3fd62ea1a	73	};
NYX	0:85b3fd62ea1a	74
NYX	0:85b3fd62ea1a	75	static const uint8_t SHIFT_TAB_OCxx[] =
NYX	0:85b3fd62ea1a	76	{
NYX	0:85b3fd62ea1a	77	0U, /* 0: OC1M, OC1FE, OC1PE */
NYX	0:85b3fd62ea1a	78	0U, /* 1: - NA */
NYX	0:85b3fd62ea1a	79	8U, /* 2: OC2M, OC2FE, OC2PE */
NYX	0:85b3fd62ea1a	80	0U, /* 3: - NA */
NYX	0:85b3fd62ea1a	81	0U, /* 4: OC3M, OC3FE, OC3PE */
NYX	0:85b3fd62ea1a	82	0U, /* 5: - NA */
NYX	0:85b3fd62ea1a	83	8U /* 6: OC4M, OC4FE, OC4PE */
NYX	0:85b3fd62ea1a	84	};
NYX	0:85b3fd62ea1a	85
NYX	0:85b3fd62ea1a	86	static const uint8_t SHIFT_TAB_ICxx[] =
NYX	0:85b3fd62ea1a	87	{
NYX	0:85b3fd62ea1a	88	0U, /* 0: CC1S, IC1PSC, IC1F */
NYX	0:85b3fd62ea1a	89	0U, /* 1: - NA */
NYX	0:85b3fd62ea1a	90	8U, /* 2: CC2S, IC2PSC, IC2F */
NYX	0:85b3fd62ea1a	91	0U, /* 3: - NA */
NYX	0:85b3fd62ea1a	92	0U, /* 4: CC3S, IC3PSC, IC3F */
NYX	0:85b3fd62ea1a	93	0U, /* 5: - NA */
NYX	0:85b3fd62ea1a	94	8U /* 6: CC4S, IC4PSC, IC4F */
NYX	0:85b3fd62ea1a	95	};
NYX	0:85b3fd62ea1a	96
NYX	0:85b3fd62ea1a	97	static const uint8_t SHIFT_TAB_CCxP[] =
NYX	0:85b3fd62ea1a	98	{
NYX	0:85b3fd62ea1a	99	0U, /* 0: CC1P */
NYX	0:85b3fd62ea1a	100	2U, /* 1: CC1NP */
NYX	0:85b3fd62ea1a	101	4U, /* 2: CC2P */
NYX	0:85b3fd62ea1a	102	6U, /* 3: CC2NP */
NYX	0:85b3fd62ea1a	103	8U, /* 4: CC3P */
NYX	0:85b3fd62ea1a	104	10U, /* 5: CC3NP */
NYX	0:85b3fd62ea1a	105	12U /* 6: CC4P */
NYX	0:85b3fd62ea1a	106	};
NYX	0:85b3fd62ea1a	107
NYX	0:85b3fd62ea1a	108	static const uint8_t SHIFT_TAB_OISx[] =
NYX	0:85b3fd62ea1a	109	{
NYX	0:85b3fd62ea1a	110	0U, /* 0: OIS1 */
NYX	0:85b3fd62ea1a	111	1U, /* 1: OIS1N */
NYX	0:85b3fd62ea1a	112	2U, /* 2: OIS2 */
NYX	0:85b3fd62ea1a	113	3U, /* 3: OIS2N */
NYX	0:85b3fd62ea1a	114	4U, /* 4: OIS3 */
NYX	0:85b3fd62ea1a	115	5U, /* 5: OIS3N */
NYX	0:85b3fd62ea1a	116	6U /* 6: OIS4 */
NYX	0:85b3fd62ea1a	117	};
NYX	0:85b3fd62ea1a	118	/**
NYX	0:85b3fd62ea1a	119	* @}
NYX	0:85b3fd62ea1a	120	*/
NYX	0:85b3fd62ea1a	121
NYX	0:85b3fd62ea1a	122
NYX	0:85b3fd62ea1a	123	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	124	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
NYX	0:85b3fd62ea1a	125	* @{
NYX	0:85b3fd62ea1a	126	*/
NYX	0:85b3fd62ea1a	127
NYX	0:85b3fd62ea1a	128
NYX	0:85b3fd62ea1a	129	/* Remap mask definitions */
NYX	0:85b3fd62ea1a	130	#define TIMx_OR_RMP_SHIFT 16U
NYX	0:85b3fd62ea1a	131	#define TIMx_OR_RMP_MASK 0x0000FFFFU
NYX	0:85b3fd62ea1a	132	#define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
NYX	0:85b3fd62ea1a	133	#define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
NYX	0:85b3fd62ea1a	134	#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
NYX	0:85b3fd62ea1a	135
NYX	0:85b3fd62ea1a	136	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
NYX	0:85b3fd62ea1a	137	#define DT_DELAY_1 ((uint8_t)0x7FU)
NYX	0:85b3fd62ea1a	138	#define DT_DELAY_2 ((uint8_t)0x3FU)
NYX	0:85b3fd62ea1a	139	#define DT_DELAY_3 ((uint8_t)0x1FU)
NYX	0:85b3fd62ea1a	140	#define DT_DELAY_4 ((uint8_t)0x1FU)
NYX	0:85b3fd62ea1a	141
NYX	0:85b3fd62ea1a	142	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
NYX	0:85b3fd62ea1a	143	#define DT_RANGE_1 ((uint8_t)0x00U)
NYX	0:85b3fd62ea1a	144	#define DT_RANGE_2 ((uint8_t)0x80U)
NYX	0:85b3fd62ea1a	145	#define DT_RANGE_3 ((uint8_t)0xC0U)
NYX	0:85b3fd62ea1a	146	#define DT_RANGE_4 ((uint8_t)0xE0U)
NYX	0:85b3fd62ea1a	147
NYX	0:85b3fd62ea1a	148
NYX	0:85b3fd62ea1a	149	/**
NYX	0:85b3fd62ea1a	150	* @}
NYX	0:85b3fd62ea1a	151	*/
NYX	0:85b3fd62ea1a	152
NYX	0:85b3fd62ea1a	153	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	154	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
NYX	0:85b3fd62ea1a	155	* @{
NYX	0:85b3fd62ea1a	156	*/
NYX	0:85b3fd62ea1a	157	/** @brief Convert channel id into channel index.
NYX	0:85b3fd62ea1a	158	* @param __CHANNEL__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	159	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	160	* @arg @ref LL_TIM_CHANNEL_CH1N
NYX	0:85b3fd62ea1a	161	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	162	* @arg @ref LL_TIM_CHANNEL_CH2N
NYX	0:85b3fd62ea1a	163	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	164	* @arg @ref LL_TIM_CHANNEL_CH3N
NYX	0:85b3fd62ea1a	165	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	166	* @retval none
NYX	0:85b3fd62ea1a	167	*/
NYX	0:85b3fd62ea1a	168	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
NYX	0:85b3fd62ea1a	169	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
NYX	0:85b3fd62ea1a	170	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
NYX	0:85b3fd62ea1a	171	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
NYX	0:85b3fd62ea1a	172	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
NYX	0:85b3fd62ea1a	173	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
NYX	0:85b3fd62ea1a	174	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
NYX	0:85b3fd62ea1a	175
NYX	0:85b3fd62ea1a	176	/** @brief Calculate the deadtime sampling period(in ps).
NYX	0:85b3fd62ea1a	177	* @param __TIMCLK__ timer input clock frequency (in Hz).
NYX	0:85b3fd62ea1a	178	* @param __CKD__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	179	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
NYX	0:85b3fd62ea1a	180	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
NYX	0:85b3fd62ea1a	181	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
NYX	0:85b3fd62ea1a	182	* @retval none
NYX	0:85b3fd62ea1a	183	*/
NYX	0:85b3fd62ea1a	184	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
NYX	0:85b3fd62ea1a	185	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
NYX	0:85b3fd62ea1a	186	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
NYX	0:85b3fd62ea1a	187	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
NYX	0:85b3fd62ea1a	188	/**
NYX	0:85b3fd62ea1a	189	* @}
NYX	0:85b3fd62ea1a	190	*/
NYX	0:85b3fd62ea1a	191
NYX	0:85b3fd62ea1a	192
NYX	0:85b3fd62ea1a	193	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	194	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	195	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
NYX	0:85b3fd62ea1a	196	* @{
NYX	0:85b3fd62ea1a	197	*/
NYX	0:85b3fd62ea1a	198
NYX	0:85b3fd62ea1a	199	/**
NYX	0:85b3fd62ea1a	200	* @brief TIM Time Base configuration structure definition.
NYX	0:85b3fd62ea1a	201	*/
NYX	0:85b3fd62ea1a	202	typedef struct
NYX	0:85b3fd62ea1a	203	{
NYX	0:85b3fd62ea1a	204	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
NYX	0:85b3fd62ea1a	205	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
NYX	0:85b3fd62ea1a	206
NYX	0:85b3fd62ea1a	207	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
NYX	0:85b3fd62ea1a	208
NYX	0:85b3fd62ea1a	209	uint32_t CounterMode; /*!< Specifies the counter mode.
NYX	0:85b3fd62ea1a	210	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
NYX	0:85b3fd62ea1a	211
NYX	0:85b3fd62ea1a	212	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
NYX	0:85b3fd62ea1a	213
NYX	0:85b3fd62ea1a	214	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
NYX	0:85b3fd62ea1a	215	Auto-Reload Register at the next update event.
NYX	0:85b3fd62ea1a	216	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
NYX	0:85b3fd62ea1a	217	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	218
NYX	0:85b3fd62ea1a	219	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
NYX	0:85b3fd62ea1a	220
NYX	0:85b3fd62ea1a	221	uint32_t ClockDivision; /*!< Specifies the clock division.
NYX	0:85b3fd62ea1a	222	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
NYX	0:85b3fd62ea1a	223
NYX	0:85b3fd62ea1a	224	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
NYX	0:85b3fd62ea1a	225
NYX	0:85b3fd62ea1a	226	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
NYX	0:85b3fd62ea1a	227	reaches zero, an update event is generated and counting restarts
NYX	0:85b3fd62ea1a	228	from the RCR value (N).
NYX	0:85b3fd62ea1a	229	This means in PWM mode that (N+1) corresponds to:
NYX	0:85b3fd62ea1a	230	- the number of PWM periods in edge-aligned mode
NYX	0:85b3fd62ea1a	231	- the number of half PWM period in center-aligned mode
NYX	0:85b3fd62ea1a	232	This parameter must be a number between 0x00 and 0xFF.
NYX	0:85b3fd62ea1a	233
NYX	0:85b3fd62ea1a	234	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
NYX	0:85b3fd62ea1a	235	} LL_TIM_InitTypeDef;
NYX	0:85b3fd62ea1a	236
NYX	0:85b3fd62ea1a	237	/**
NYX	0:85b3fd62ea1a	238	* @brief TIM Output Compare configuration structure definition.
NYX	0:85b3fd62ea1a	239	*/
NYX	0:85b3fd62ea1a	240	typedef struct
NYX	0:85b3fd62ea1a	241	{
NYX	0:85b3fd62ea1a	242	uint32_t OCMode; /*!< Specifies the output mode.
NYX	0:85b3fd62ea1a	243	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
NYX	0:85b3fd62ea1a	244
NYX	0:85b3fd62ea1a	245	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
NYX	0:85b3fd62ea1a	246
NYX	0:85b3fd62ea1a	247	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
NYX	0:85b3fd62ea1a	248	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
NYX	0:85b3fd62ea1a	249
NYX	0:85b3fd62ea1a	250	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
NYX	0:85b3fd62ea1a	251
NYX	0:85b3fd62ea1a	252	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
NYX	0:85b3fd62ea1a	253	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
NYX	0:85b3fd62ea1a	254
NYX	0:85b3fd62ea1a	255	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
NYX	0:85b3fd62ea1a	256
NYX	0:85b3fd62ea1a	257	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
NYX	0:85b3fd62ea1a	258	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
NYX	0:85b3fd62ea1a	259
NYX	0:85b3fd62ea1a	260	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
NYX	0:85b3fd62ea1a	261
NYX	0:85b3fd62ea1a	262	uint32_t OCPolarity; /*!< Specifies the output polarity.
NYX	0:85b3fd62ea1a	263	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
NYX	0:85b3fd62ea1a	264
NYX	0:85b3fd62ea1a	265	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
NYX	0:85b3fd62ea1a	266
NYX	0:85b3fd62ea1a	267	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
NYX	0:85b3fd62ea1a	268	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
NYX	0:85b3fd62ea1a	269
NYX	0:85b3fd62ea1a	270	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
NYX	0:85b3fd62ea1a	271
NYX	0:85b3fd62ea1a	272
NYX	0:85b3fd62ea1a	273	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
NYX	0:85b3fd62ea1a	274	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
NYX	0:85b3fd62ea1a	275
NYX	0:85b3fd62ea1a	276	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
NYX	0:85b3fd62ea1a	277
NYX	0:85b3fd62ea1a	278	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
NYX	0:85b3fd62ea1a	279	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
NYX	0:85b3fd62ea1a	280
NYX	0:85b3fd62ea1a	281	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
NYX	0:85b3fd62ea1a	282	} LL_TIM_OC_InitTypeDef;
NYX	0:85b3fd62ea1a	283
NYX	0:85b3fd62ea1a	284	/**
NYX	0:85b3fd62ea1a	285	* @brief TIM Input Capture configuration structure definition.
NYX	0:85b3fd62ea1a	286	*/
NYX	0:85b3fd62ea1a	287
NYX	0:85b3fd62ea1a	288	typedef struct
NYX	0:85b3fd62ea1a	289	{
NYX	0:85b3fd62ea1a	290
NYX	0:85b3fd62ea1a	291	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
NYX	0:85b3fd62ea1a	292	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
NYX	0:85b3fd62ea1a	293
NYX	0:85b3fd62ea1a	294	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
NYX	0:85b3fd62ea1a	295
NYX	0:85b3fd62ea1a	296	uint32_t ICActiveInput; /*!< Specifies the input.
NYX	0:85b3fd62ea1a	297	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
NYX	0:85b3fd62ea1a	298
NYX	0:85b3fd62ea1a	299	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
NYX	0:85b3fd62ea1a	300
NYX	0:85b3fd62ea1a	301	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
NYX	0:85b3fd62ea1a	302	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
NYX	0:85b3fd62ea1a	303
NYX	0:85b3fd62ea1a	304	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
NYX	0:85b3fd62ea1a	305
NYX	0:85b3fd62ea1a	306	uint32_t ICFilter; /*!< Specifies the input capture filter.
NYX	0:85b3fd62ea1a	307	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
NYX	0:85b3fd62ea1a	308
NYX	0:85b3fd62ea1a	309	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
NYX	0:85b3fd62ea1a	310	} LL_TIM_IC_InitTypeDef;
NYX	0:85b3fd62ea1a	311
NYX	0:85b3fd62ea1a	312
NYX	0:85b3fd62ea1a	313	/**
NYX	0:85b3fd62ea1a	314	* @brief TIM Encoder interface configuration structure definition.
NYX	0:85b3fd62ea1a	315	*/
NYX	0:85b3fd62ea1a	316	typedef struct
NYX	0:85b3fd62ea1a	317	{
NYX	0:85b3fd62ea1a	318	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
NYX	0:85b3fd62ea1a	319	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
NYX	0:85b3fd62ea1a	320
NYX	0:85b3fd62ea1a	321	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
NYX	0:85b3fd62ea1a	322
NYX	0:85b3fd62ea1a	323	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
NYX	0:85b3fd62ea1a	324	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
NYX	0:85b3fd62ea1a	325
NYX	0:85b3fd62ea1a	326	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
NYX	0:85b3fd62ea1a	327
NYX	0:85b3fd62ea1a	328	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
NYX	0:85b3fd62ea1a	329	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
NYX	0:85b3fd62ea1a	330
NYX	0:85b3fd62ea1a	331	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
NYX	0:85b3fd62ea1a	332
NYX	0:85b3fd62ea1a	333	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
NYX	0:85b3fd62ea1a	334	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
NYX	0:85b3fd62ea1a	335
NYX	0:85b3fd62ea1a	336	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
NYX	0:85b3fd62ea1a	337
NYX	0:85b3fd62ea1a	338	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
NYX	0:85b3fd62ea1a	339	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
NYX	0:85b3fd62ea1a	340
NYX	0:85b3fd62ea1a	341	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
NYX	0:85b3fd62ea1a	342
NYX	0:85b3fd62ea1a	343	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
NYX	0:85b3fd62ea1a	344	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
NYX	0:85b3fd62ea1a	345
NYX	0:85b3fd62ea1a	346	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
NYX	0:85b3fd62ea1a	347
NYX	0:85b3fd62ea1a	348	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
NYX	0:85b3fd62ea1a	349	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
NYX	0:85b3fd62ea1a	350
NYX	0:85b3fd62ea1a	351	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
NYX	0:85b3fd62ea1a	352
NYX	0:85b3fd62ea1a	353	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
NYX	0:85b3fd62ea1a	354	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
NYX	0:85b3fd62ea1a	355
NYX	0:85b3fd62ea1a	356	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
NYX	0:85b3fd62ea1a	357
NYX	0:85b3fd62ea1a	358	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
NYX	0:85b3fd62ea1a	359	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
NYX	0:85b3fd62ea1a	360
NYX	0:85b3fd62ea1a	361	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
NYX	0:85b3fd62ea1a	362
NYX	0:85b3fd62ea1a	363	} LL_TIM_ENCODER_InitTypeDef;
NYX	0:85b3fd62ea1a	364
NYX	0:85b3fd62ea1a	365	/**
NYX	0:85b3fd62ea1a	366	* @brief TIM Hall sensor interface configuration structure definition.
NYX	0:85b3fd62ea1a	367	*/
NYX	0:85b3fd62ea1a	368	typedef struct
NYX	0:85b3fd62ea1a	369	{
NYX	0:85b3fd62ea1a	370
NYX	0:85b3fd62ea1a	371	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
NYX	0:85b3fd62ea1a	372	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
NYX	0:85b3fd62ea1a	373
NYX	0:85b3fd62ea1a	374	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
NYX	0:85b3fd62ea1a	375
NYX	0:85b3fd62ea1a	376	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
NYX	0:85b3fd62ea1a	377	Prescaler must be set to get a maximum counter period longer than the
NYX	0:85b3fd62ea1a	378	time interval between 2 consecutive changes on the Hall inputs.
NYX	0:85b3fd62ea1a	379	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
NYX	0:85b3fd62ea1a	380
NYX	0:85b3fd62ea1a	381	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
NYX	0:85b3fd62ea1a	382
NYX	0:85b3fd62ea1a	383	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
NYX	0:85b3fd62ea1a	384	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
NYX	0:85b3fd62ea1a	385
NYX	0:85b3fd62ea1a	386	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
NYX	0:85b3fd62ea1a	387
NYX	0:85b3fd62ea1a	388	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
NYX	0:85b3fd62ea1a	389	A positive pulse (TRGO event) is generated with a programmable delay every time
NYX	0:85b3fd62ea1a	390	a change occurs on the Hall inputs.
NYX	0:85b3fd62ea1a	391	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
NYX	0:85b3fd62ea1a	392
NYX	0:85b3fd62ea1a	393	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
NYX	0:85b3fd62ea1a	394	} LL_TIM_HALLSENSOR_InitTypeDef;
NYX	0:85b3fd62ea1a	395
NYX	0:85b3fd62ea1a	396	/**
NYX	0:85b3fd62ea1a	397	* @brief BDTR (Break and Dead Time) structure definition
NYX	0:85b3fd62ea1a	398	*/
NYX	0:85b3fd62ea1a	399	typedef struct
NYX	0:85b3fd62ea1a	400	{
NYX	0:85b3fd62ea1a	401	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
NYX	0:85b3fd62ea1a	402	This parameter can be a value of @ref TIM_LL_EC_OSSR
NYX	0:85b3fd62ea1a	403
NYX	0:85b3fd62ea1a	404	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
NYX	0:85b3fd62ea1a	405
NYX	0:85b3fd62ea1a	406	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
NYX	0:85b3fd62ea1a	407
NYX	0:85b3fd62ea1a	408	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
NYX	0:85b3fd62ea1a	409	This parameter can be a value of @ref TIM_LL_EC_OSSI
NYX	0:85b3fd62ea1a	410
NYX	0:85b3fd62ea1a	411	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
NYX	0:85b3fd62ea1a	412
NYX	0:85b3fd62ea1a	413	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
NYX	0:85b3fd62ea1a	414
NYX	0:85b3fd62ea1a	415	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
NYX	0:85b3fd62ea1a	416	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
NYX	0:85b3fd62ea1a	417
NYX	0:85b3fd62ea1a	418	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
NYX	0:85b3fd62ea1a	419	has been written, their content is frozen until the next reset.*/
NYX	0:85b3fd62ea1a	420
NYX	0:85b3fd62ea1a	421	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
NYX	0:85b3fd62ea1a	422	switching-on of the outputs.
NYX	0:85b3fd62ea1a	423	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
NYX	0:85b3fd62ea1a	424
NYX	0:85b3fd62ea1a	425	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
NYX	0:85b3fd62ea1a	426
NYX	0:85b3fd62ea1a	427	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
NYX	0:85b3fd62ea1a	428
NYX	0:85b3fd62ea1a	429	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
NYX	0:85b3fd62ea1a	430	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
NYX	0:85b3fd62ea1a	431
NYX	0:85b3fd62ea1a	432	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
NYX	0:85b3fd62ea1a	433
NYX	0:85b3fd62ea1a	434	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
NYX	0:85b3fd62ea1a	435
NYX	0:85b3fd62ea1a	436	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
NYX	0:85b3fd62ea1a	437	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
NYX	0:85b3fd62ea1a	438
NYX	0:85b3fd62ea1a	439	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
NYX	0:85b3fd62ea1a	440
NYX	0:85b3fd62ea1a	441	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
NYX	0:85b3fd62ea1a	442
NYX	0:85b3fd62ea1a	443	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
NYX	0:85b3fd62ea1a	444	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
NYX	0:85b3fd62ea1a	445
NYX	0:85b3fd62ea1a	446	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
NYX	0:85b3fd62ea1a	447
NYX	0:85b3fd62ea1a	448	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
NYX	0:85b3fd62ea1a	449	} LL_TIM_BDTR_InitTypeDef;
NYX	0:85b3fd62ea1a	450
NYX	0:85b3fd62ea1a	451	/**
NYX	0:85b3fd62ea1a	452	* @}
NYX	0:85b3fd62ea1a	453	*/
NYX	0:85b3fd62ea1a	454	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	455
NYX	0:85b3fd62ea1a	456	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	457	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
NYX	0:85b3fd62ea1a	458	* @{
NYX	0:85b3fd62ea1a	459	*/
NYX	0:85b3fd62ea1a	460
NYX	0:85b3fd62ea1a	461	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
NYX	0:85b3fd62ea1a	462	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
NYX	0:85b3fd62ea1a	463	* @{
NYX	0:85b3fd62ea1a	464	*/
NYX	0:85b3fd62ea1a	465	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
NYX	0:85b3fd62ea1a	466	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
NYX	0:85b3fd62ea1a	467	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
NYX	0:85b3fd62ea1a	468	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
NYX	0:85b3fd62ea1a	469	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
NYX	0:85b3fd62ea1a	470	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
NYX	0:85b3fd62ea1a	471	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
NYX	0:85b3fd62ea1a	472	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
NYX	0:85b3fd62ea1a	473	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
NYX	0:85b3fd62ea1a	474	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
NYX	0:85b3fd62ea1a	475	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
NYX	0:85b3fd62ea1a	476	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
NYX	0:85b3fd62ea1a	477	/**
NYX	0:85b3fd62ea1a	478	* @}
NYX	0:85b3fd62ea1a	479	*/
NYX	0:85b3fd62ea1a	480
NYX	0:85b3fd62ea1a	481	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	482	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
NYX	0:85b3fd62ea1a	483	* @{
NYX	0:85b3fd62ea1a	484	*/
NYX	0:85b3fd62ea1a	485	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
NYX	0:85b3fd62ea1a	486	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
NYX	0:85b3fd62ea1a	487	/**
NYX	0:85b3fd62ea1a	488	* @}
NYX	0:85b3fd62ea1a	489	*/
NYX	0:85b3fd62ea1a	490
NYX	0:85b3fd62ea1a	491	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
NYX	0:85b3fd62ea1a	492	* @{
NYX	0:85b3fd62ea1a	493	*/
NYX	0:85b3fd62ea1a	494	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
NYX	0:85b3fd62ea1a	495	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
NYX	0:85b3fd62ea1a	496	/**
NYX	0:85b3fd62ea1a	497	* @}
NYX	0:85b3fd62ea1a	498	*/
NYX	0:85b3fd62ea1a	499	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	500
NYX	0:85b3fd62ea1a	501	/** @defgroup TIM_LL_EC_IT IT Defines
NYX	0:85b3fd62ea1a	502	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
NYX	0:85b3fd62ea1a	503	* @{
NYX	0:85b3fd62ea1a	504	*/
NYX	0:85b3fd62ea1a	505	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
NYX	0:85b3fd62ea1a	506	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
NYX	0:85b3fd62ea1a	507	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
NYX	0:85b3fd62ea1a	508	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
NYX	0:85b3fd62ea1a	509	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
NYX	0:85b3fd62ea1a	510	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
NYX	0:85b3fd62ea1a	511	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
NYX	0:85b3fd62ea1a	512	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
NYX	0:85b3fd62ea1a	513	/**
NYX	0:85b3fd62ea1a	514	* @}
NYX	0:85b3fd62ea1a	515	*/
NYX	0:85b3fd62ea1a	516
NYX	0:85b3fd62ea1a	517	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
NYX	0:85b3fd62ea1a	518	* @{
NYX	0:85b3fd62ea1a	519	*/
NYX	0:85b3fd62ea1a	520	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
NYX	0:85b3fd62ea1a	521	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
NYX	0:85b3fd62ea1a	522	/**
NYX	0:85b3fd62ea1a	523	* @}
NYX	0:85b3fd62ea1a	524	*/
NYX	0:85b3fd62ea1a	525
NYX	0:85b3fd62ea1a	526	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
NYX	0:85b3fd62ea1a	527	* @{
NYX	0:85b3fd62ea1a	528	*/
NYX	0:85b3fd62ea1a	529	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
NYX	0:85b3fd62ea1a	530	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
NYX	0:85b3fd62ea1a	531	/**
NYX	0:85b3fd62ea1a	532	* @}
NYX	0:85b3fd62ea1a	533	*/
NYX	0:85b3fd62ea1a	534
NYX	0:85b3fd62ea1a	535	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
NYX	0:85b3fd62ea1a	536	* @{
NYX	0:85b3fd62ea1a	537	*/
NYX	0:85b3fd62ea1a	538	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
NYX	0:85b3fd62ea1a	539	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
NYX	0:85b3fd62ea1a	540	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
NYX	0:85b3fd62ea1a	541	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
NYX	0:85b3fd62ea1a	542	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
NYX	0:85b3fd62ea1a	543	/**
NYX	0:85b3fd62ea1a	544	* @}
NYX	0:85b3fd62ea1a	545	*/
NYX	0:85b3fd62ea1a	546
NYX	0:85b3fd62ea1a	547	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
NYX	0:85b3fd62ea1a	548	* @{
NYX	0:85b3fd62ea1a	549	*/
NYX	0:85b3fd62ea1a	550	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
NYX	0:85b3fd62ea1a	551	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
NYX	0:85b3fd62ea1a	552	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
NYX	0:85b3fd62ea1a	553	/**
NYX	0:85b3fd62ea1a	554	* @}
NYX	0:85b3fd62ea1a	555	*/
NYX	0:85b3fd62ea1a	556
NYX	0:85b3fd62ea1a	557	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
NYX	0:85b3fd62ea1a	558	* @{
NYX	0:85b3fd62ea1a	559	*/
NYX	0:85b3fd62ea1a	560	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
NYX	0:85b3fd62ea1a	561	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
NYX	0:85b3fd62ea1a	562	/**
NYX	0:85b3fd62ea1a	563	* @}
NYX	0:85b3fd62ea1a	564	*/
NYX	0:85b3fd62ea1a	565
NYX	0:85b3fd62ea1a	566	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
NYX	0:85b3fd62ea1a	567	* @{
NYX	0:85b3fd62ea1a	568	*/
NYX	0:85b3fd62ea1a	569	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
NYX	0:85b3fd62ea1a	570	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
NYX	0:85b3fd62ea1a	571	/**
NYX	0:85b3fd62ea1a	572	* @}
NYX	0:85b3fd62ea1a	573	*/
NYX	0:85b3fd62ea1a	574
NYX	0:85b3fd62ea1a	575	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
NYX	0:85b3fd62ea1a	576	* @{
NYX	0:85b3fd62ea1a	577	*/
NYX	0:85b3fd62ea1a	578	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
NYX	0:85b3fd62ea1a	579	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
NYX	0:85b3fd62ea1a	580	/**
NYX	0:85b3fd62ea1a	581	* @}
NYX	0:85b3fd62ea1a	582	*/
NYX	0:85b3fd62ea1a	583
NYX	0:85b3fd62ea1a	584	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
NYX	0:85b3fd62ea1a	585	* @{
NYX	0:85b3fd62ea1a	586	*/
NYX	0:85b3fd62ea1a	587	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
NYX	0:85b3fd62ea1a	588	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
NYX	0:85b3fd62ea1a	589	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
NYX	0:85b3fd62ea1a	590	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
NYX	0:85b3fd62ea1a	591	/**
NYX	0:85b3fd62ea1a	592	* @}
NYX	0:85b3fd62ea1a	593	*/
NYX	0:85b3fd62ea1a	594
NYX	0:85b3fd62ea1a	595	/** @defgroup TIM_LL_EC_CHANNEL Channel
NYX	0:85b3fd62ea1a	596	* @{
NYX	0:85b3fd62ea1a	597	*/
NYX	0:85b3fd62ea1a	598	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
NYX	0:85b3fd62ea1a	599	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
NYX	0:85b3fd62ea1a	600	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
NYX	0:85b3fd62ea1a	601	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
NYX	0:85b3fd62ea1a	602	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
NYX	0:85b3fd62ea1a	603	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
NYX	0:85b3fd62ea1a	604	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
NYX	0:85b3fd62ea1a	605	/**
NYX	0:85b3fd62ea1a	606	* @}
NYX	0:85b3fd62ea1a	607	*/
NYX	0:85b3fd62ea1a	608
NYX	0:85b3fd62ea1a	609	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	610	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
NYX	0:85b3fd62ea1a	611	* @{
NYX	0:85b3fd62ea1a	612	*/
NYX	0:85b3fd62ea1a	613	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
NYX	0:85b3fd62ea1a	614	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
NYX	0:85b3fd62ea1a	615	/**
NYX	0:85b3fd62ea1a	616	* @}
NYX	0:85b3fd62ea1a	617	*/
NYX	0:85b3fd62ea1a	618	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	619
NYX	0:85b3fd62ea1a	620	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
NYX	0:85b3fd62ea1a	621	* @{
NYX	0:85b3fd62ea1a	622	*/
NYX	0:85b3fd62ea1a	623	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
NYX	0:85b3fd62ea1a	624	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
NYX	0:85b3fd62ea1a	625	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
NYX	0:85b3fd62ea1a	626	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
NYX	0:85b3fd62ea1a	627	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
NYX	0:85b3fd62ea1a	628	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
NYX	0:85b3fd62ea1a	629	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
NYX	0:85b3fd62ea1a	630	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
NYX	0:85b3fd62ea1a	631	/**
NYX	0:85b3fd62ea1a	632	* @}
NYX	0:85b3fd62ea1a	633	*/
NYX	0:85b3fd62ea1a	634
NYX	0:85b3fd62ea1a	635	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
NYX	0:85b3fd62ea1a	636	* @{
NYX	0:85b3fd62ea1a	637	*/
NYX	0:85b3fd62ea1a	638	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
NYX	0:85b3fd62ea1a	639	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
NYX	0:85b3fd62ea1a	640	/**
NYX	0:85b3fd62ea1a	641	* @}
NYX	0:85b3fd62ea1a	642	*/
NYX	0:85b3fd62ea1a	643
NYX	0:85b3fd62ea1a	644	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
NYX	0:85b3fd62ea1a	645	* @{
NYX	0:85b3fd62ea1a	646	*/
NYX	0:85b3fd62ea1a	647	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
NYX	0:85b3fd62ea1a	648	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
NYX	0:85b3fd62ea1a	649	/**
NYX	0:85b3fd62ea1a	650	* @}
NYX	0:85b3fd62ea1a	651	*/
NYX	0:85b3fd62ea1a	652
NYX	0:85b3fd62ea1a	653
NYX	0:85b3fd62ea1a	654	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
NYX	0:85b3fd62ea1a	655	* @{
NYX	0:85b3fd62ea1a	656	*/
NYX	0:85b3fd62ea1a	657	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
NYX	0:85b3fd62ea1a	658	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
NYX	0:85b3fd62ea1a	659	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
NYX	0:85b3fd62ea1a	660	/**
NYX	0:85b3fd62ea1a	661	* @}
NYX	0:85b3fd62ea1a	662	*/
NYX	0:85b3fd62ea1a	663
NYX	0:85b3fd62ea1a	664	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
NYX	0:85b3fd62ea1a	665	* @{
NYX	0:85b3fd62ea1a	666	*/
NYX	0:85b3fd62ea1a	667	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
NYX	0:85b3fd62ea1a	668	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
NYX	0:85b3fd62ea1a	669	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
NYX	0:85b3fd62ea1a	670	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
NYX	0:85b3fd62ea1a	671	/**
NYX	0:85b3fd62ea1a	672	* @}
NYX	0:85b3fd62ea1a	673	*/
NYX	0:85b3fd62ea1a	674
NYX	0:85b3fd62ea1a	675	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
NYX	0:85b3fd62ea1a	676	* @{
NYX	0:85b3fd62ea1a	677	*/
NYX	0:85b3fd62ea1a	678	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
NYX	0:85b3fd62ea1a	679	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
NYX	0:85b3fd62ea1a	680	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
NYX	0:85b3fd62ea1a	681	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
NYX	0:85b3fd62ea1a	682	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
NYX	0:85b3fd62ea1a	683	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
NYX	0:85b3fd62ea1a	684	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
NYX	0:85b3fd62ea1a	685	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
NYX	0:85b3fd62ea1a	686	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
NYX	0:85b3fd62ea1a	687	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
NYX	0:85b3fd62ea1a	688	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
NYX	0:85b3fd62ea1a	689	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
NYX	0:85b3fd62ea1a	690	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
NYX	0:85b3fd62ea1a	691	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
NYX	0:85b3fd62ea1a	692	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
NYX	0:85b3fd62ea1a	693	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
NYX	0:85b3fd62ea1a	694	/**
NYX	0:85b3fd62ea1a	695	* @}
NYX	0:85b3fd62ea1a	696	*/
NYX	0:85b3fd62ea1a	697
NYX	0:85b3fd62ea1a	698	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
NYX	0:85b3fd62ea1a	699	* @{
NYX	0:85b3fd62ea1a	700	*/
NYX	0:85b3fd62ea1a	701	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
NYX	0:85b3fd62ea1a	702	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
NYX	0:85b3fd62ea1a	703	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
NYX	0:85b3fd62ea1a	704	/**
NYX	0:85b3fd62ea1a	705	* @}
NYX	0:85b3fd62ea1a	706	*/
NYX	0:85b3fd62ea1a	707
NYX	0:85b3fd62ea1a	708	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
NYX	0:85b3fd62ea1a	709	* @{
NYX	0:85b3fd62ea1a	710	*/
NYX	0:85b3fd62ea1a	711	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
NYX	0:85b3fd62ea1a	712	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
NYX	0:85b3fd62ea1a	713	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
NYX	0:85b3fd62ea1a	714	/**
NYX	0:85b3fd62ea1a	715	* @}
NYX	0:85b3fd62ea1a	716	*/
NYX	0:85b3fd62ea1a	717
NYX	0:85b3fd62ea1a	718	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
NYX	0:85b3fd62ea1a	719	* @{
NYX	0:85b3fd62ea1a	720	*/
NYX	0:85b3fd62ea1a	721	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
NYX	0:85b3fd62ea1a	722	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
NYX	0:85b3fd62ea1a	723	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
NYX	0:85b3fd62ea1a	724	/**
NYX	0:85b3fd62ea1a	725	* @}
NYX	0:85b3fd62ea1a	726	*/
NYX	0:85b3fd62ea1a	727
NYX	0:85b3fd62ea1a	728	/** @defgroup TIM_LL_EC_TRGO Trigger Output
NYX	0:85b3fd62ea1a	729	* @{
NYX	0:85b3fd62ea1a	730	*/
NYX	0:85b3fd62ea1a	731	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
NYX	0:85b3fd62ea1a	732	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
NYX	0:85b3fd62ea1a	733	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
NYX	0:85b3fd62ea1a	734	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
NYX	0:85b3fd62ea1a	735	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
NYX	0:85b3fd62ea1a	736	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
NYX	0:85b3fd62ea1a	737	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
NYX	0:85b3fd62ea1a	738	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
NYX	0:85b3fd62ea1a	739	/**
NYX	0:85b3fd62ea1a	740	* @}
NYX	0:85b3fd62ea1a	741	*/
NYX	0:85b3fd62ea1a	742
NYX	0:85b3fd62ea1a	743
NYX	0:85b3fd62ea1a	744	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
NYX	0:85b3fd62ea1a	745	* @{
NYX	0:85b3fd62ea1a	746	*/
NYX	0:85b3fd62ea1a	747	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
NYX	0:85b3fd62ea1a	748	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
NYX	0:85b3fd62ea1a	749	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
NYX	0:85b3fd62ea1a	750	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
NYX	0:85b3fd62ea1a	751	/**
NYX	0:85b3fd62ea1a	752	* @}
NYX	0:85b3fd62ea1a	753	*/
NYX	0:85b3fd62ea1a	754
NYX	0:85b3fd62ea1a	755	/** @defgroup TIM_LL_EC_TS Trigger Selection
NYX	0:85b3fd62ea1a	756	* @{
NYX	0:85b3fd62ea1a	757	*/
NYX	0:85b3fd62ea1a	758	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
NYX	0:85b3fd62ea1a	759	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
NYX	0:85b3fd62ea1a	760	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
NYX	0:85b3fd62ea1a	761	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
NYX	0:85b3fd62ea1a	762	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
NYX	0:85b3fd62ea1a	763	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
NYX	0:85b3fd62ea1a	764	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
NYX	0:85b3fd62ea1a	765	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
NYX	0:85b3fd62ea1a	766	/**
NYX	0:85b3fd62ea1a	767	* @}
NYX	0:85b3fd62ea1a	768	*/
NYX	0:85b3fd62ea1a	769
NYX	0:85b3fd62ea1a	770	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
NYX	0:85b3fd62ea1a	771	* @{
NYX	0:85b3fd62ea1a	772	*/
NYX	0:85b3fd62ea1a	773	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
NYX	0:85b3fd62ea1a	774	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
NYX	0:85b3fd62ea1a	775	/**
NYX	0:85b3fd62ea1a	776	* @}
NYX	0:85b3fd62ea1a	777	*/
NYX	0:85b3fd62ea1a	778
NYX	0:85b3fd62ea1a	779	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
NYX	0:85b3fd62ea1a	780	* @{
NYX	0:85b3fd62ea1a	781	*/
NYX	0:85b3fd62ea1a	782	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
NYX	0:85b3fd62ea1a	783	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
NYX	0:85b3fd62ea1a	784	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
NYX	0:85b3fd62ea1a	785	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
NYX	0:85b3fd62ea1a	786	/**
NYX	0:85b3fd62ea1a	787	* @}
NYX	0:85b3fd62ea1a	788	*/
NYX	0:85b3fd62ea1a	789
NYX	0:85b3fd62ea1a	790	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
NYX	0:85b3fd62ea1a	791	* @{
NYX	0:85b3fd62ea1a	792	*/
NYX	0:85b3fd62ea1a	793	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
NYX	0:85b3fd62ea1a	794	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
NYX	0:85b3fd62ea1a	795	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
NYX	0:85b3fd62ea1a	796	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
NYX	0:85b3fd62ea1a	797	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
NYX	0:85b3fd62ea1a	798	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
NYX	0:85b3fd62ea1a	799	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
NYX	0:85b3fd62ea1a	800	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
NYX	0:85b3fd62ea1a	801	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
NYX	0:85b3fd62ea1a	802	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
NYX	0:85b3fd62ea1a	803	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
NYX	0:85b3fd62ea1a	804	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
NYX	0:85b3fd62ea1a	805	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
NYX	0:85b3fd62ea1a	806	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
NYX	0:85b3fd62ea1a	807	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
NYX	0:85b3fd62ea1a	808	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
NYX	0:85b3fd62ea1a	809	/**
NYX	0:85b3fd62ea1a	810	* @}
NYX	0:85b3fd62ea1a	811	*/
NYX	0:85b3fd62ea1a	812
NYX	0:85b3fd62ea1a	813
NYX	0:85b3fd62ea1a	814	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
NYX	0:85b3fd62ea1a	815	* @{
NYX	0:85b3fd62ea1a	816	*/
NYX	0:85b3fd62ea1a	817	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
NYX	0:85b3fd62ea1a	818	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
NYX	0:85b3fd62ea1a	819	/**
NYX	0:85b3fd62ea1a	820	* @}
NYX	0:85b3fd62ea1a	821	*/
NYX	0:85b3fd62ea1a	822
NYX	0:85b3fd62ea1a	823
NYX	0:85b3fd62ea1a	824
NYX	0:85b3fd62ea1a	825
NYX	0:85b3fd62ea1a	826	/** @defgroup TIM_LL_EC_OSSI OSSI
NYX	0:85b3fd62ea1a	827	* @{
NYX	0:85b3fd62ea1a	828	*/
NYX	0:85b3fd62ea1a	829	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
NYX	0:85b3fd62ea1a	830	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
NYX	0:85b3fd62ea1a	831	/**
NYX	0:85b3fd62ea1a	832	* @}
NYX	0:85b3fd62ea1a	833	*/
NYX	0:85b3fd62ea1a	834
NYX	0:85b3fd62ea1a	835	/** @defgroup TIM_LL_EC_OSSR OSSR
NYX	0:85b3fd62ea1a	836	* @{
NYX	0:85b3fd62ea1a	837	*/
NYX	0:85b3fd62ea1a	838	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
NYX	0:85b3fd62ea1a	839	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
NYX	0:85b3fd62ea1a	840	/**
NYX	0:85b3fd62ea1a	841	* @}
NYX	0:85b3fd62ea1a	842	*/
NYX	0:85b3fd62ea1a	843
NYX	0:85b3fd62ea1a	844
NYX	0:85b3fd62ea1a	845	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
NYX	0:85b3fd62ea1a	846	* @{
NYX	0:85b3fd62ea1a	847	*/
NYX	0:85b3fd62ea1a	848	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	849	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	850	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	851	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	852	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	853	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	854	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	855	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	856	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	857	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	858	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	859	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	860	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	861	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	862	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	863	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	864	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	865	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
NYX	0:85b3fd62ea1a	866	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0)
NYX	0:85b3fd62ea1a	867	/**
NYX	0:85b3fd62ea1a	868	* @}
NYX	0:85b3fd62ea1a	869	*/
NYX	0:85b3fd62ea1a	870
NYX	0:85b3fd62ea1a	871	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
NYX	0:85b3fd62ea1a	872	* @{
NYX	0:85b3fd62ea1a	873	*/
NYX	0:85b3fd62ea1a	874	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	875	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	876	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	877	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	878	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	879	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	880	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	881	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	882	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	883	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	884	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	885	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	886	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	887	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	888	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	889	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	890	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	891	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
NYX	0:85b3fd62ea1a	892	/**
NYX	0:85b3fd62ea1a	893	* @}
NYX	0:85b3fd62ea1a	894	*/
NYX	0:85b3fd62ea1a	895
NYX	0:85b3fd62ea1a	896
NYX	0:85b3fd62ea1a	897	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
NYX	0:85b3fd62ea1a	898	* @{
NYX	0:85b3fd62ea1a	899	*/
NYX	0:85b3fd62ea1a	900	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /!< TIM2_ITR1 is connected to TIM8_TRGO /
NYX	0:85b3fd62ea1a	901	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
NYX	0:85b3fd62ea1a	902	#define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_HS SOF /
NYX	0:85b3fd62ea1a	903	/**
NYX	0:85b3fd62ea1a	904	* @}
NYX	0:85b3fd62ea1a	905	*/
NYX	0:85b3fd62ea1a	906
NYX	0:85b3fd62ea1a	907	/** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
NYX	0:85b3fd62ea1a	908	* @{
NYX	0:85b3fd62ea1a	909	*/
NYX	0:85b3fd62ea1a	910	#define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /!< TIM5 channel 4 is connected to GPIO /
NYX	0:85b3fd62ea1a	911	#define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSI internal clock /
NYX	0:85b3fd62ea1a	912	#define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSE /
NYX	0:85b3fd62ea1a	913	#define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to RTC wakeup interrupt /
NYX	0:85b3fd62ea1a	914	/**
NYX	0:85b3fd62ea1a	915	* @}
NYX	0:85b3fd62ea1a	916	*/
NYX	0:85b3fd62ea1a	917
NYX	0:85b3fd62ea1a	918	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
NYX	0:85b3fd62ea1a	919	* @{
NYX	0:85b3fd62ea1a	920	*/
NYX	0:85b3fd62ea1a	921	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /!< TIM11 channel 1 is connected to GPIO /
NYX	0:85b3fd62ea1a	922	#define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to GPIO /
NYX	0:85b3fd62ea1a	923	#define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to GPIO /
NYX	0:85b3fd62ea1a	924	#define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to HSE_RTC /
NYX	0:85b3fd62ea1a	925	/**
NYX	0:85b3fd62ea1a	926	* @}
NYX	0:85b3fd62ea1a	927	*/
NYX	0:85b3fd62ea1a	928
NYX	0:85b3fd62ea1a	929
NYX	0:85b3fd62ea1a	930	/**
NYX	0:85b3fd62ea1a	931	* @}
NYX	0:85b3fd62ea1a	932	*/
NYX	0:85b3fd62ea1a	933
NYX	0:85b3fd62ea1a	934	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	935	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
NYX	0:85b3fd62ea1a	936	* @{
NYX	0:85b3fd62ea1a	937	*/
NYX	0:85b3fd62ea1a	938
NYX	0:85b3fd62ea1a	939	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
NYX	0:85b3fd62ea1a	940	* @{
NYX	0:85b3fd62ea1a	941	*/
NYX	0:85b3fd62ea1a	942	/**
NYX	0:85b3fd62ea1a	943	* @brief Write a value in TIM register.
NYX	0:85b3fd62ea1a	944	* @param __INSTANCE__ TIM Instance
NYX	0:85b3fd62ea1a	945	* @param __REG__ Register to be written
NYX	0:85b3fd62ea1a	946	* @param __VALUE__ Value to be written in the register
NYX	0:85b3fd62ea1a	947	* @retval None
NYX	0:85b3fd62ea1a	948	*/
NYX	0:85b3fd62ea1a	949	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
NYX	0:85b3fd62ea1a	950
NYX	0:85b3fd62ea1a	951	/**
NYX	0:85b3fd62ea1a	952	* @brief Read a value in TIM register.
NYX	0:85b3fd62ea1a	953	* @param __INSTANCE__ TIM Instance
NYX	0:85b3fd62ea1a	954	* @param __REG__ Register to be read
NYX	0:85b3fd62ea1a	955	* @retval Register value
NYX	0:85b3fd62ea1a	956	*/
NYX	0:85b3fd62ea1a	957	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
NYX	0:85b3fd62ea1a	958	/**
NYX	0:85b3fd62ea1a	959	* @}
NYX	0:85b3fd62ea1a	960	*/
NYX	0:85b3fd62ea1a	961
NYX	0:85b3fd62ea1a	962	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
NYX	0:85b3fd62ea1a	963	* @{
NYX	0:85b3fd62ea1a	964	*/
NYX	0:85b3fd62ea1a	965
NYX	0:85b3fd62ea1a	966	/**
NYX	0:85b3fd62ea1a	967	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
NYX	0:85b3fd62ea1a	968	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
NYX	0:85b3fd62ea1a	969	* @param __TIMCLK__ timer input clock frequency (in Hz)
NYX	0:85b3fd62ea1a	970	* @param __CKD__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	971	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
NYX	0:85b3fd62ea1a	972	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
NYX	0:85b3fd62ea1a	973	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
NYX	0:85b3fd62ea1a	974	* @param __DT__ deadtime duration (in ns)
NYX	0:85b3fd62ea1a	975	* @retval DTG[0:7]
NYX	0:85b3fd62ea1a	976	*/
NYX	0:85b3fd62ea1a	977	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
NYX	0:85b3fd62ea1a	978	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
NYX	0:85b3fd62ea1a	979	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
NYX	0:85b3fd62ea1a	980	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
NYX	0:85b3fd62ea1a	981	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
NYX	0:85b3fd62ea1a	982	0U)
NYX	0:85b3fd62ea1a	983
NYX	0:85b3fd62ea1a	984	/**
NYX	0:85b3fd62ea1a	985	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
NYX	0:85b3fd62ea1a	986	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
NYX	0:85b3fd62ea1a	987	* @param __TIMCLK__ timer input clock frequency (in Hz)
NYX	0:85b3fd62ea1a	988	* @param __CNTCLK__ counter clock frequency (in Hz)
NYX	0:85b3fd62ea1a	989	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	990	*/
NYX	0:85b3fd62ea1a	991	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
NYX	0:85b3fd62ea1a	992	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
NYX	0:85b3fd62ea1a	993
NYX	0:85b3fd62ea1a	994	/**
NYX	0:85b3fd62ea1a	995	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
NYX	0:85b3fd62ea1a	996	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
NYX	0:85b3fd62ea1a	997	* @param __TIMCLK__ timer input clock frequency (in Hz)
NYX	0:85b3fd62ea1a	998	* @param __PSC__ prescaler
NYX	0:85b3fd62ea1a	999	* @param __FREQ__ output signal frequency (in Hz)
NYX	0:85b3fd62ea1a	1000	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	1001	*/
NYX	0:85b3fd62ea1a	1002	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
NYX	0:85b3fd62ea1a	1003	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
NYX	0:85b3fd62ea1a	1004
NYX	0:85b3fd62ea1a	1005	/**
NYX	0:85b3fd62ea1a	1006	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
NYX	0:85b3fd62ea1a	1007	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
NYX	0:85b3fd62ea1a	1008	* @param __TIMCLK__ timer input clock frequency (in Hz)
NYX	0:85b3fd62ea1a	1009	* @param __PSC__ prescaler
NYX	0:85b3fd62ea1a	1010	* @param __DELAY__ timer output compare active/inactive delay (in us)
NYX	0:85b3fd62ea1a	1011	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	1012	*/
NYX	0:85b3fd62ea1a	1013	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
NYX	0:85b3fd62ea1a	1014	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
NYX	0:85b3fd62ea1a	1015	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
NYX	0:85b3fd62ea1a	1016
NYX	0:85b3fd62ea1a	1017	/**
NYX	0:85b3fd62ea1a	1018	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
NYX	0:85b3fd62ea1a	1019	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
NYX	0:85b3fd62ea1a	1020	* @param __TIMCLK__ timer input clock frequency (in Hz)
NYX	0:85b3fd62ea1a	1021	* @param __PSC__ prescaler
NYX	0:85b3fd62ea1a	1022	* @param __DELAY__ timer output compare active/inactive delay (in us)
NYX	0:85b3fd62ea1a	1023	* @param __PULSE__ pulse duration (in us)
NYX	0:85b3fd62ea1a	1024	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	1025	*/
NYX	0:85b3fd62ea1a	1026	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
NYX	0:85b3fd62ea1a	1027	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
NYX	0:85b3fd62ea1a	1028	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
NYX	0:85b3fd62ea1a	1029
NYX	0:85b3fd62ea1a	1030	/**
NYX	0:85b3fd62ea1a	1031	* @brief HELPER macro retrieving the ratio of the input capture prescaler
NYX	0:85b3fd62ea1a	1032	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
NYX	0:85b3fd62ea1a	1033	* @param __ICPSC__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1034	* @arg @ref LL_TIM_ICPSC_DIV1
NYX	0:85b3fd62ea1a	1035	* @arg @ref LL_TIM_ICPSC_DIV2
NYX	0:85b3fd62ea1a	1036	* @arg @ref LL_TIM_ICPSC_DIV4
NYX	0:85b3fd62ea1a	1037	* @arg @ref LL_TIM_ICPSC_DIV8
NYX	0:85b3fd62ea1a	1038	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
NYX	0:85b3fd62ea1a	1039	*/
NYX	0:85b3fd62ea1a	1040	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
NYX	0:85b3fd62ea1a	1041	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
NYX	0:85b3fd62ea1a	1042
NYX	0:85b3fd62ea1a	1043
NYX	0:85b3fd62ea1a	1044	/**
NYX	0:85b3fd62ea1a	1045	* @}
NYX	0:85b3fd62ea1a	1046	*/
NYX	0:85b3fd62ea1a	1047
NYX	0:85b3fd62ea1a	1048
NYX	0:85b3fd62ea1a	1049	/**
NYX	0:85b3fd62ea1a	1050	* @}
NYX	0:85b3fd62ea1a	1051	*/
NYX	0:85b3fd62ea1a	1052
NYX	0:85b3fd62ea1a	1053	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1054	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
NYX	0:85b3fd62ea1a	1055	* @{
NYX	0:85b3fd62ea1a	1056	*/
NYX	0:85b3fd62ea1a	1057
NYX	0:85b3fd62ea1a	1058	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
NYX	0:85b3fd62ea1a	1059	* @{
NYX	0:85b3fd62ea1a	1060	*/
NYX	0:85b3fd62ea1a	1061	/**
NYX	0:85b3fd62ea1a	1062	* @brief Enable timer counter.
NYX	0:85b3fd62ea1a	1063	* @rmtoll CR1 CEN LL_TIM_EnableCounter
NYX	0:85b3fd62ea1a	1064	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1065	* @retval None
NYX	0:85b3fd62ea1a	1066	*/
NYX	0:85b3fd62ea1a	1067	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1068	{
NYX	0:85b3fd62ea1a	1069	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
NYX	0:85b3fd62ea1a	1070	}
NYX	0:85b3fd62ea1a	1071
NYX	0:85b3fd62ea1a	1072	/**
NYX	0:85b3fd62ea1a	1073	* @brief Disable timer counter.
NYX	0:85b3fd62ea1a	1074	* @rmtoll CR1 CEN LL_TIM_DisableCounter
NYX	0:85b3fd62ea1a	1075	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1076	* @retval None
NYX	0:85b3fd62ea1a	1077	*/
NYX	0:85b3fd62ea1a	1078	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1079	{
NYX	0:85b3fd62ea1a	1080	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
NYX	0:85b3fd62ea1a	1081	}
NYX	0:85b3fd62ea1a	1082
NYX	0:85b3fd62ea1a	1083	/**
NYX	0:85b3fd62ea1a	1084	* @brief Indicates whether the timer counter is enabled.
NYX	0:85b3fd62ea1a	1085	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
NYX	0:85b3fd62ea1a	1086	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1087	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1088	*/
NYX	0:85b3fd62ea1a	1089	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1090	{
NYX	0:85b3fd62ea1a	1091	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
NYX	0:85b3fd62ea1a	1092	}
NYX	0:85b3fd62ea1a	1093
NYX	0:85b3fd62ea1a	1094	/**
NYX	0:85b3fd62ea1a	1095	* @brief Enable update event generation.
NYX	0:85b3fd62ea1a	1096	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
NYX	0:85b3fd62ea1a	1097	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1098	* @retval None
NYX	0:85b3fd62ea1a	1099	*/
NYX	0:85b3fd62ea1a	1100	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1101	{
NYX	0:85b3fd62ea1a	1102	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
NYX	0:85b3fd62ea1a	1103	}
NYX	0:85b3fd62ea1a	1104
NYX	0:85b3fd62ea1a	1105	/**
NYX	0:85b3fd62ea1a	1106	* @brief Disable update event generation.
NYX	0:85b3fd62ea1a	1107	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
NYX	0:85b3fd62ea1a	1108	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1109	* @retval None
NYX	0:85b3fd62ea1a	1110	*/
NYX	0:85b3fd62ea1a	1111	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1112	{
NYX	0:85b3fd62ea1a	1113	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
NYX	0:85b3fd62ea1a	1114	}
NYX	0:85b3fd62ea1a	1115
NYX	0:85b3fd62ea1a	1116	/**
NYX	0:85b3fd62ea1a	1117	* @brief Indicates whether update event generation is enabled.
NYX	0:85b3fd62ea1a	1118	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
NYX	0:85b3fd62ea1a	1119	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1120	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1121	*/
NYX	0:85b3fd62ea1a	1122	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1123	{
NYX	0:85b3fd62ea1a	1124	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
NYX	0:85b3fd62ea1a	1125	}
NYX	0:85b3fd62ea1a	1126
NYX	0:85b3fd62ea1a	1127	/**
NYX	0:85b3fd62ea1a	1128	* @brief Set update event source
NYX	0:85b3fd62ea1a	1129	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
NYX	0:85b3fd62ea1a	1130	* generate an update interrupt or DMA request if enabled:
NYX	0:85b3fd62ea1a	1131	* - Counter overflow/underflow
NYX	0:85b3fd62ea1a	1132	* - Setting the UG bit
NYX	0:85b3fd62ea1a	1133	* - Update generation through the slave mode controller
NYX	0:85b3fd62ea1a	1134	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
NYX	0:85b3fd62ea1a	1135	* overflow/underflow generates an update interrupt or DMA request if enabled.
NYX	0:85b3fd62ea1a	1136	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
NYX	0:85b3fd62ea1a	1137	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1138	* @param UpdateSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1139	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
NYX	0:85b3fd62ea1a	1140	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
NYX	0:85b3fd62ea1a	1141	* @retval None
NYX	0:85b3fd62ea1a	1142	*/
NYX	0:85b3fd62ea1a	1143	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
NYX	0:85b3fd62ea1a	1144	{
NYX	0:85b3fd62ea1a	1145	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
NYX	0:85b3fd62ea1a	1146	}
NYX	0:85b3fd62ea1a	1147
NYX	0:85b3fd62ea1a	1148	/**
NYX	0:85b3fd62ea1a	1149	* @brief Get actual event update source
NYX	0:85b3fd62ea1a	1150	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
NYX	0:85b3fd62ea1a	1151	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1152	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1153	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
NYX	0:85b3fd62ea1a	1154	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
NYX	0:85b3fd62ea1a	1155	*/
NYX	0:85b3fd62ea1a	1156	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1157	{
NYX	0:85b3fd62ea1a	1158	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
NYX	0:85b3fd62ea1a	1159	}
NYX	0:85b3fd62ea1a	1160
NYX	0:85b3fd62ea1a	1161	/**
NYX	0:85b3fd62ea1a	1162	* @brief Set one pulse mode (one shot v.s. repetitive).
NYX	0:85b3fd62ea1a	1163	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
NYX	0:85b3fd62ea1a	1164	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1165	* @param OnePulseMode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1166	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
NYX	0:85b3fd62ea1a	1167	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
NYX	0:85b3fd62ea1a	1168	* @retval None
NYX	0:85b3fd62ea1a	1169	*/
NYX	0:85b3fd62ea1a	1170	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
NYX	0:85b3fd62ea1a	1171	{
NYX	0:85b3fd62ea1a	1172	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
NYX	0:85b3fd62ea1a	1173	}
NYX	0:85b3fd62ea1a	1174
NYX	0:85b3fd62ea1a	1175	/**
NYX	0:85b3fd62ea1a	1176	* @brief Get actual one pulse mode.
NYX	0:85b3fd62ea1a	1177	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
NYX	0:85b3fd62ea1a	1178	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1179	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1180	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
NYX	0:85b3fd62ea1a	1181	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
NYX	0:85b3fd62ea1a	1182	*/
NYX	0:85b3fd62ea1a	1183	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1184	{
NYX	0:85b3fd62ea1a	1185	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
NYX	0:85b3fd62ea1a	1186	}
NYX	0:85b3fd62ea1a	1187
NYX	0:85b3fd62ea1a	1188	/**
NYX	0:85b3fd62ea1a	1189	* @brief Set the timer counter counting mode.
NYX	0:85b3fd62ea1a	1190	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
NYX	0:85b3fd62ea1a	1191	* check whether or not the counter mode selection feature is supported
NYX	0:85b3fd62ea1a	1192	* by a timer instance.
NYX	0:85b3fd62ea1a	1193	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
NYX	0:85b3fd62ea1a	1194	* CR1 CMS LL_TIM_SetCounterMode
NYX	0:85b3fd62ea1a	1195	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1196	* @param CounterMode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1197	* @arg @ref LL_TIM_COUNTERMODE_UP
NYX	0:85b3fd62ea1a	1198	* @arg @ref LL_TIM_COUNTERMODE_DOWN
NYX	0:85b3fd62ea1a	1199	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
NYX	0:85b3fd62ea1a	1200	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
NYX	0:85b3fd62ea1a	1201	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
NYX	0:85b3fd62ea1a	1202	* @retval None
NYX	0:85b3fd62ea1a	1203	*/
NYX	0:85b3fd62ea1a	1204	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
NYX	0:85b3fd62ea1a	1205	{
NYX	0:85b3fd62ea1a	1206	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
NYX	0:85b3fd62ea1a	1207	}
NYX	0:85b3fd62ea1a	1208
NYX	0:85b3fd62ea1a	1209	/**
NYX	0:85b3fd62ea1a	1210	* @brief Get actual counter mode.
NYX	0:85b3fd62ea1a	1211	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
NYX	0:85b3fd62ea1a	1212	* check whether or not the counter mode selection feature is supported
NYX	0:85b3fd62ea1a	1213	* by a timer instance.
NYX	0:85b3fd62ea1a	1214	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
NYX	0:85b3fd62ea1a	1215	* CR1 CMS LL_TIM_GetCounterMode
NYX	0:85b3fd62ea1a	1216	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1217	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1218	* @arg @ref LL_TIM_COUNTERMODE_UP
NYX	0:85b3fd62ea1a	1219	* @arg @ref LL_TIM_COUNTERMODE_DOWN
NYX	0:85b3fd62ea1a	1220	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
NYX	0:85b3fd62ea1a	1221	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
NYX	0:85b3fd62ea1a	1222	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
NYX	0:85b3fd62ea1a	1223	*/
NYX	0:85b3fd62ea1a	1224	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1225	{
NYX	0:85b3fd62ea1a	1226	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
NYX	0:85b3fd62ea1a	1227	}
NYX	0:85b3fd62ea1a	1228
NYX	0:85b3fd62ea1a	1229	/**
NYX	0:85b3fd62ea1a	1230	* @brief Enable auto-reload (ARR) preload.
NYX	0:85b3fd62ea1a	1231	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
NYX	0:85b3fd62ea1a	1232	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1233	* @retval None
NYX	0:85b3fd62ea1a	1234	*/
NYX	0:85b3fd62ea1a	1235	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1236	{
NYX	0:85b3fd62ea1a	1237	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
NYX	0:85b3fd62ea1a	1238	}
NYX	0:85b3fd62ea1a	1239
NYX	0:85b3fd62ea1a	1240	/**
NYX	0:85b3fd62ea1a	1241	* @brief Disable auto-reload (ARR) preload.
NYX	0:85b3fd62ea1a	1242	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
NYX	0:85b3fd62ea1a	1243	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1244	* @retval None
NYX	0:85b3fd62ea1a	1245	*/
NYX	0:85b3fd62ea1a	1246	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1247	{
NYX	0:85b3fd62ea1a	1248	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
NYX	0:85b3fd62ea1a	1249	}
NYX	0:85b3fd62ea1a	1250
NYX	0:85b3fd62ea1a	1251	/**
NYX	0:85b3fd62ea1a	1252	* @brief Indicates whether auto-reload (ARR) preload is enabled.
NYX	0:85b3fd62ea1a	1253	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
NYX	0:85b3fd62ea1a	1254	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1255	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1256	*/
NYX	0:85b3fd62ea1a	1257	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1258	{
NYX	0:85b3fd62ea1a	1259	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
NYX	0:85b3fd62ea1a	1260	}
NYX	0:85b3fd62ea1a	1261
NYX	0:85b3fd62ea1a	1262	/**
NYX	0:85b3fd62ea1a	1263	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
NYX	0:85b3fd62ea1a	1264	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1265	* whether or not the clock division feature is supported by the timer
NYX	0:85b3fd62ea1a	1266	* instance.
NYX	0:85b3fd62ea1a	1267	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
NYX	0:85b3fd62ea1a	1268	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1269	* @param ClockDivision This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1270	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
NYX	0:85b3fd62ea1a	1271	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
NYX	0:85b3fd62ea1a	1272	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
NYX	0:85b3fd62ea1a	1273	* @retval None
NYX	0:85b3fd62ea1a	1274	*/
NYX	0:85b3fd62ea1a	1275	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
NYX	0:85b3fd62ea1a	1276	{
NYX	0:85b3fd62ea1a	1277	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
NYX	0:85b3fd62ea1a	1278	}
NYX	0:85b3fd62ea1a	1279
NYX	0:85b3fd62ea1a	1280	/**
NYX	0:85b3fd62ea1a	1281	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
NYX	0:85b3fd62ea1a	1282	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1283	* whether or not the clock division feature is supported by the timer
NYX	0:85b3fd62ea1a	1284	* instance.
NYX	0:85b3fd62ea1a	1285	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
NYX	0:85b3fd62ea1a	1286	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1287	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1288	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
NYX	0:85b3fd62ea1a	1289	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
NYX	0:85b3fd62ea1a	1290	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
NYX	0:85b3fd62ea1a	1291	*/
NYX	0:85b3fd62ea1a	1292	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1293	{
NYX	0:85b3fd62ea1a	1294	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
NYX	0:85b3fd62ea1a	1295	}
NYX	0:85b3fd62ea1a	1296
NYX	0:85b3fd62ea1a	1297	/**
NYX	0:85b3fd62ea1a	1298	* @brief Set the counter value.
NYX	0:85b3fd62ea1a	1299	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1300	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	1301	* @rmtoll CNT CNT LL_TIM_SetCounter
NYX	0:85b3fd62ea1a	1302	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1303	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
NYX	0:85b3fd62ea1a	1304	* @retval None
NYX	0:85b3fd62ea1a	1305	*/
NYX	0:85b3fd62ea1a	1306	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
NYX	0:85b3fd62ea1a	1307	{
NYX	0:85b3fd62ea1a	1308	WRITE_REG(TIMx->CNT, Counter);
NYX	0:85b3fd62ea1a	1309	}
NYX	0:85b3fd62ea1a	1310
NYX	0:85b3fd62ea1a	1311	/**
NYX	0:85b3fd62ea1a	1312	* @brief Get the counter value.
NYX	0:85b3fd62ea1a	1313	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1314	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	1315	* @rmtoll CNT CNT LL_TIM_GetCounter
NYX	0:85b3fd62ea1a	1316	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1317	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
NYX	0:85b3fd62ea1a	1318	*/
NYX	0:85b3fd62ea1a	1319	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1320	{
NYX	0:85b3fd62ea1a	1321	return (uint32_t)(READ_REG(TIMx->CNT));
NYX	0:85b3fd62ea1a	1322	}
NYX	0:85b3fd62ea1a	1323
NYX	0:85b3fd62ea1a	1324	/**
NYX	0:85b3fd62ea1a	1325	* @brief Get the current direction of the counter
NYX	0:85b3fd62ea1a	1326	* @rmtoll CR1 DIR LL_TIM_GetDirection
NYX	0:85b3fd62ea1a	1327	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1328	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1329	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
NYX	0:85b3fd62ea1a	1330	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
NYX	0:85b3fd62ea1a	1331	*/
NYX	0:85b3fd62ea1a	1332	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1333	{
NYX	0:85b3fd62ea1a	1334	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
NYX	0:85b3fd62ea1a	1335	}
NYX	0:85b3fd62ea1a	1336
NYX	0:85b3fd62ea1a	1337	/**
NYX	0:85b3fd62ea1a	1338	* @brief Set the prescaler value.
NYX	0:85b3fd62ea1a	1339	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
NYX	0:85b3fd62ea1a	1340	* @note The prescaler can be changed on the fly as this control register is buffered. The new
NYX	0:85b3fd62ea1a	1341	* prescaler ratio is taken into account at the next update event.
NYX	0:85b3fd62ea1a	1342	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
NYX	0:85b3fd62ea1a	1343	* @rmtoll PSC PSC LL_TIM_SetPrescaler
NYX	0:85b3fd62ea1a	1344	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1345	* @param Prescaler between Min_Data=0 and Max_Data=65535
NYX	0:85b3fd62ea1a	1346	* @retval None
NYX	0:85b3fd62ea1a	1347	*/
NYX	0:85b3fd62ea1a	1348	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
NYX	0:85b3fd62ea1a	1349	{
NYX	0:85b3fd62ea1a	1350	WRITE_REG(TIMx->PSC, Prescaler);
NYX	0:85b3fd62ea1a	1351	}
NYX	0:85b3fd62ea1a	1352
NYX	0:85b3fd62ea1a	1353	/**
NYX	0:85b3fd62ea1a	1354	* @brief Get the prescaler value.
NYX	0:85b3fd62ea1a	1355	* @rmtoll PSC PSC LL_TIM_GetPrescaler
NYX	0:85b3fd62ea1a	1356	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1357	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
NYX	0:85b3fd62ea1a	1358	*/
NYX	0:85b3fd62ea1a	1359	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1360	{
NYX	0:85b3fd62ea1a	1361	return (uint32_t)(READ_REG(TIMx->PSC));
NYX	0:85b3fd62ea1a	1362	}
NYX	0:85b3fd62ea1a	1363
NYX	0:85b3fd62ea1a	1364	/**
NYX	0:85b3fd62ea1a	1365	* @brief Set the auto-reload value.
NYX	0:85b3fd62ea1a	1366	* @note The counter is blocked while the auto-reload value is null.
NYX	0:85b3fd62ea1a	1367	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1368	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	1369	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
NYX	0:85b3fd62ea1a	1370	* @rmtoll ARR ARR LL_TIM_SetAutoReload
NYX	0:85b3fd62ea1a	1371	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1372	* @param AutoReload between Min_Data=0 and Max_Data=65535
NYX	0:85b3fd62ea1a	1373	* @retval None
NYX	0:85b3fd62ea1a	1374	*/
NYX	0:85b3fd62ea1a	1375	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
NYX	0:85b3fd62ea1a	1376	{
NYX	0:85b3fd62ea1a	1377	WRITE_REG(TIMx->ARR, AutoReload);
NYX	0:85b3fd62ea1a	1378	}
NYX	0:85b3fd62ea1a	1379
NYX	0:85b3fd62ea1a	1380	/**
NYX	0:85b3fd62ea1a	1381	* @brief Get the auto-reload value.
NYX	0:85b3fd62ea1a	1382	* @rmtoll ARR ARR LL_TIM_GetAutoReload
NYX	0:85b3fd62ea1a	1383	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1384	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	1385	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1386	* @retval Auto-reload value
NYX	0:85b3fd62ea1a	1387	*/
NYX	0:85b3fd62ea1a	1388	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1389	{
NYX	0:85b3fd62ea1a	1390	return (uint32_t)(READ_REG(TIMx->ARR));
NYX	0:85b3fd62ea1a	1391	}
NYX	0:85b3fd62ea1a	1392
NYX	0:85b3fd62ea1a	1393	/**
NYX	0:85b3fd62ea1a	1394	* @brief Set the repetition counter value.
NYX	0:85b3fd62ea1a	1395	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1396	* whether or not a timer instance supports a repetition counter.
NYX	0:85b3fd62ea1a	1397	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
NYX	0:85b3fd62ea1a	1398	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1399	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
NYX	0:85b3fd62ea1a	1400	* @retval None
NYX	0:85b3fd62ea1a	1401	*/
NYX	0:85b3fd62ea1a	1402	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
NYX	0:85b3fd62ea1a	1403	{
NYX	0:85b3fd62ea1a	1404	WRITE_REG(TIMx->RCR, RepetitionCounter);
NYX	0:85b3fd62ea1a	1405	}
NYX	0:85b3fd62ea1a	1406
NYX	0:85b3fd62ea1a	1407	/**
NYX	0:85b3fd62ea1a	1408	* @brief Get the repetition counter value.
NYX	0:85b3fd62ea1a	1409	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1410	* whether or not a timer instance supports a repetition counter.
NYX	0:85b3fd62ea1a	1411	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
NYX	0:85b3fd62ea1a	1412	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1413	* @retval Repetition counter value
NYX	0:85b3fd62ea1a	1414	*/
NYX	0:85b3fd62ea1a	1415	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1416	{
NYX	0:85b3fd62ea1a	1417	return (uint32_t)(READ_REG(TIMx->RCR));
NYX	0:85b3fd62ea1a	1418	}
NYX	0:85b3fd62ea1a	1419
NYX	0:85b3fd62ea1a	1420	/**
NYX	0:85b3fd62ea1a	1421	* @}
NYX	0:85b3fd62ea1a	1422	*/
NYX	0:85b3fd62ea1a	1423
NYX	0:85b3fd62ea1a	1424	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
NYX	0:85b3fd62ea1a	1425	* @{
NYX	0:85b3fd62ea1a	1426	*/
NYX	0:85b3fd62ea1a	1427	/**
NYX	0:85b3fd62ea1a	1428	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
NYX	0:85b3fd62ea1a	1429	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
NYX	0:85b3fd62ea1a	1430	* they are updated only when a commutation event (COM) occurs.
NYX	0:85b3fd62ea1a	1431	* @note Only on channels that have a complementary output.
NYX	0:85b3fd62ea1a	1432	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1433	* whether or not a timer instance is able to generate a commutation event.
NYX	0:85b3fd62ea1a	1434	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
NYX	0:85b3fd62ea1a	1435	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1436	* @retval None
NYX	0:85b3fd62ea1a	1437	*/
NYX	0:85b3fd62ea1a	1438	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1439	{
NYX	0:85b3fd62ea1a	1440	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
NYX	0:85b3fd62ea1a	1441	}
NYX	0:85b3fd62ea1a	1442
NYX	0:85b3fd62ea1a	1443	/**
NYX	0:85b3fd62ea1a	1444	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
NYX	0:85b3fd62ea1a	1445	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1446	* whether or not a timer instance is able to generate a commutation event.
NYX	0:85b3fd62ea1a	1447	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
NYX	0:85b3fd62ea1a	1448	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1449	* @retval None
NYX	0:85b3fd62ea1a	1450	*/
NYX	0:85b3fd62ea1a	1451	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1452	{
NYX	0:85b3fd62ea1a	1453	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
NYX	0:85b3fd62ea1a	1454	}
NYX	0:85b3fd62ea1a	1455
NYX	0:85b3fd62ea1a	1456	/**
NYX	0:85b3fd62ea1a	1457	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
NYX	0:85b3fd62ea1a	1458	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	1459	* whether or not a timer instance is able to generate a commutation event.
NYX	0:85b3fd62ea1a	1460	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
NYX	0:85b3fd62ea1a	1461	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1462	* @param CCUpdateSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1463	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
NYX	0:85b3fd62ea1a	1464	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
NYX	0:85b3fd62ea1a	1465	* @retval None
NYX	0:85b3fd62ea1a	1466	*/
NYX	0:85b3fd62ea1a	1467	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
NYX	0:85b3fd62ea1a	1468	{
NYX	0:85b3fd62ea1a	1469	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
NYX	0:85b3fd62ea1a	1470	}
NYX	0:85b3fd62ea1a	1471
NYX	0:85b3fd62ea1a	1472	/**
NYX	0:85b3fd62ea1a	1473	* @brief Set the trigger of the capture/compare DMA request.
NYX	0:85b3fd62ea1a	1474	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
NYX	0:85b3fd62ea1a	1475	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1476	* @param DMAReqTrigger This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1477	* @arg @ref LL_TIM_CCDMAREQUEST_CC
NYX	0:85b3fd62ea1a	1478	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
NYX	0:85b3fd62ea1a	1479	* @retval None
NYX	0:85b3fd62ea1a	1480	*/
NYX	0:85b3fd62ea1a	1481	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
NYX	0:85b3fd62ea1a	1482	{
NYX	0:85b3fd62ea1a	1483	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
NYX	0:85b3fd62ea1a	1484	}
NYX	0:85b3fd62ea1a	1485
NYX	0:85b3fd62ea1a	1486	/**
NYX	0:85b3fd62ea1a	1487	* @brief Get actual trigger of the capture/compare DMA request.
NYX	0:85b3fd62ea1a	1488	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
NYX	0:85b3fd62ea1a	1489	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1490	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1491	* @arg @ref LL_TIM_CCDMAREQUEST_CC
NYX	0:85b3fd62ea1a	1492	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
NYX	0:85b3fd62ea1a	1493	*/
NYX	0:85b3fd62ea1a	1494	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	1495	{
NYX	0:85b3fd62ea1a	1496	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
NYX	0:85b3fd62ea1a	1497	}
NYX	0:85b3fd62ea1a	1498
NYX	0:85b3fd62ea1a	1499	/**
NYX	0:85b3fd62ea1a	1500	* @brief Set the lock level to freeze the
NYX	0:85b3fd62ea1a	1501	* configuration of several capture/compare parameters.
NYX	0:85b3fd62ea1a	1502	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	1503	* the lock mechanism is supported by a timer instance.
NYX	0:85b3fd62ea1a	1504	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
NYX	0:85b3fd62ea1a	1505	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1506	* @param LockLevel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1507	* @arg @ref LL_TIM_LOCKLEVEL_OFF
NYX	0:85b3fd62ea1a	1508	* @arg @ref LL_TIM_LOCKLEVEL_1
NYX	0:85b3fd62ea1a	1509	* @arg @ref LL_TIM_LOCKLEVEL_2
NYX	0:85b3fd62ea1a	1510	* @arg @ref LL_TIM_LOCKLEVEL_3
NYX	0:85b3fd62ea1a	1511	* @retval None
NYX	0:85b3fd62ea1a	1512	*/
NYX	0:85b3fd62ea1a	1513	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
NYX	0:85b3fd62ea1a	1514	{
NYX	0:85b3fd62ea1a	1515	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
NYX	0:85b3fd62ea1a	1516	}
NYX	0:85b3fd62ea1a	1517
NYX	0:85b3fd62ea1a	1518	/**
NYX	0:85b3fd62ea1a	1519	* @brief Enable capture/compare channels.
NYX	0:85b3fd62ea1a	1520	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
NYX	0:85b3fd62ea1a	1521	* CCER CC1NE LL_TIM_CC_EnableChannel\n
NYX	0:85b3fd62ea1a	1522	* CCER CC2E LL_TIM_CC_EnableChannel\n
NYX	0:85b3fd62ea1a	1523	* CCER CC2NE LL_TIM_CC_EnableChannel\n
NYX	0:85b3fd62ea1a	1524	* CCER CC3E LL_TIM_CC_EnableChannel\n
NYX	0:85b3fd62ea1a	1525	* CCER CC3NE LL_TIM_CC_EnableChannel\n
NYX	0:85b3fd62ea1a	1526	* CCER CC4E LL_TIM_CC_EnableChannel
NYX	0:85b3fd62ea1a	1527	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1528	* @param Channels This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	1529	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1530	* @arg @ref LL_TIM_CHANNEL_CH1N
NYX	0:85b3fd62ea1a	1531	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1532	* @arg @ref LL_TIM_CHANNEL_CH2N
NYX	0:85b3fd62ea1a	1533	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1534	* @arg @ref LL_TIM_CHANNEL_CH3N
NYX	0:85b3fd62ea1a	1535	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1536	* @retval None
NYX	0:85b3fd62ea1a	1537	*/
NYX	0:85b3fd62ea1a	1538	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
NYX	0:85b3fd62ea1a	1539	{
NYX	0:85b3fd62ea1a	1540	SET_BIT(TIMx->CCER, Channels);
NYX	0:85b3fd62ea1a	1541	}
NYX	0:85b3fd62ea1a	1542
NYX	0:85b3fd62ea1a	1543	/**
NYX	0:85b3fd62ea1a	1544	* @brief Disable capture/compare channels.
NYX	0:85b3fd62ea1a	1545	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
NYX	0:85b3fd62ea1a	1546	* CCER CC1NE LL_TIM_CC_DisableChannel\n
NYX	0:85b3fd62ea1a	1547	* CCER CC2E LL_TIM_CC_DisableChannel\n
NYX	0:85b3fd62ea1a	1548	* CCER CC2NE LL_TIM_CC_DisableChannel\n
NYX	0:85b3fd62ea1a	1549	* CCER CC3E LL_TIM_CC_DisableChannel\n
NYX	0:85b3fd62ea1a	1550	* CCER CC3NE LL_TIM_CC_DisableChannel\n
NYX	0:85b3fd62ea1a	1551	* CCER CC4E LL_TIM_CC_DisableChannel
NYX	0:85b3fd62ea1a	1552	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1553	* @param Channels This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	1554	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1555	* @arg @ref LL_TIM_CHANNEL_CH1N
NYX	0:85b3fd62ea1a	1556	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1557	* @arg @ref LL_TIM_CHANNEL_CH2N
NYX	0:85b3fd62ea1a	1558	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1559	* @arg @ref LL_TIM_CHANNEL_CH3N
NYX	0:85b3fd62ea1a	1560	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1561	* @retval None
NYX	0:85b3fd62ea1a	1562	*/
NYX	0:85b3fd62ea1a	1563	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
NYX	0:85b3fd62ea1a	1564	{
NYX	0:85b3fd62ea1a	1565	CLEAR_BIT(TIMx->CCER, Channels);
NYX	0:85b3fd62ea1a	1566	}
NYX	0:85b3fd62ea1a	1567
NYX	0:85b3fd62ea1a	1568	/**
NYX	0:85b3fd62ea1a	1569	* @brief Indicate whether channel(s) is(are) enabled.
NYX	0:85b3fd62ea1a	1570	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
NYX	0:85b3fd62ea1a	1571	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
NYX	0:85b3fd62ea1a	1572	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
NYX	0:85b3fd62ea1a	1573	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
NYX	0:85b3fd62ea1a	1574	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
NYX	0:85b3fd62ea1a	1575	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
NYX	0:85b3fd62ea1a	1576	* CCER CC4E LL_TIM_CC_IsEnabledChannel
NYX	0:85b3fd62ea1a	1577	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1578	* @param Channels This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	1579	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1580	* @arg @ref LL_TIM_CHANNEL_CH1N
NYX	0:85b3fd62ea1a	1581	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1582	* @arg @ref LL_TIM_CHANNEL_CH2N
NYX	0:85b3fd62ea1a	1583	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1584	* @arg @ref LL_TIM_CHANNEL_CH3N
NYX	0:85b3fd62ea1a	1585	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1586	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1587	*/
NYX	0:85b3fd62ea1a	1588	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
NYX	0:85b3fd62ea1a	1589	{
NYX	0:85b3fd62ea1a	1590	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
NYX	0:85b3fd62ea1a	1591	}
NYX	0:85b3fd62ea1a	1592
NYX	0:85b3fd62ea1a	1593	/**
NYX	0:85b3fd62ea1a	1594	* @}
NYX	0:85b3fd62ea1a	1595	*/
NYX	0:85b3fd62ea1a	1596
NYX	0:85b3fd62ea1a	1597	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
NYX	0:85b3fd62ea1a	1598	* @{
NYX	0:85b3fd62ea1a	1599	*/
NYX	0:85b3fd62ea1a	1600	/**
NYX	0:85b3fd62ea1a	1601	* @brief Configure an output channel.
NYX	0:85b3fd62ea1a	1602	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1603	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1604	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1605	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1606	* CCER CC1P LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1607	* CCER CC2P LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1608	* CCER CC3P LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1609	* CCER CC4P LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1610	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1611	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1612	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
NYX	0:85b3fd62ea1a	1613	* CR2 OIS4 LL_TIM_OC_ConfigOutput
NYX	0:85b3fd62ea1a	1614	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1615	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1616	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1617	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1618	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1619	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1620	* @param Configuration This parameter must be a combination of all the following values:
NYX	0:85b3fd62ea1a	1621	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
NYX	0:85b3fd62ea1a	1622	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
NYX	0:85b3fd62ea1a	1623	* @retval None
NYX	0:85b3fd62ea1a	1624	*/
NYX	0:85b3fd62ea1a	1625	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
NYX	0:85b3fd62ea1a	1626	{
NYX	0:85b3fd62ea1a	1627	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1628	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1629	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
NYX	0:85b3fd62ea1a	1630	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
NYX	0:85b3fd62ea1a	1631	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
NYX	0:85b3fd62ea1a	1632	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
NYX	0:85b3fd62ea1a	1633	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
NYX	0:85b3fd62ea1a	1634	}
NYX	0:85b3fd62ea1a	1635
NYX	0:85b3fd62ea1a	1636	/**
NYX	0:85b3fd62ea1a	1637	* @brief Define the behavior of the output reference signal OCxREF from which
NYX	0:85b3fd62ea1a	1638	* OCx and OCxN (when relevant) are derived.
NYX	0:85b3fd62ea1a	1639	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
NYX	0:85b3fd62ea1a	1640	* CCMR1 OC2M LL_TIM_OC_SetMode\n
NYX	0:85b3fd62ea1a	1641	* CCMR2 OC3M LL_TIM_OC_SetMode\n
NYX	0:85b3fd62ea1a	1642	* CCMR2 OC4M LL_TIM_OC_SetMode
NYX	0:85b3fd62ea1a	1643	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1644	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1645	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1646	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1647	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1648	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1649	* @param Mode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1650	* @arg @ref LL_TIM_OCMODE_FROZEN
NYX	0:85b3fd62ea1a	1651	* @arg @ref LL_TIM_OCMODE_ACTIVE
NYX	0:85b3fd62ea1a	1652	* @arg @ref LL_TIM_OCMODE_INACTIVE
NYX	0:85b3fd62ea1a	1653	* @arg @ref LL_TIM_OCMODE_TOGGLE
NYX	0:85b3fd62ea1a	1654	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
NYX	0:85b3fd62ea1a	1655	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
NYX	0:85b3fd62ea1a	1656	* @arg @ref LL_TIM_OCMODE_PWM1
NYX	0:85b3fd62ea1a	1657	* @arg @ref LL_TIM_OCMODE_PWM2
NYX	0:85b3fd62ea1a	1658	* @retval None
NYX	0:85b3fd62ea1a	1659	*/
NYX	0:85b3fd62ea1a	1660	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
NYX	0:85b3fd62ea1a	1661	{
NYX	0:85b3fd62ea1a	1662	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1663	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1664	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
NYX	0:85b3fd62ea1a	1665	}
NYX	0:85b3fd62ea1a	1666
NYX	0:85b3fd62ea1a	1667	/**
NYX	0:85b3fd62ea1a	1668	* @brief Get the output compare mode of an output channel.
NYX	0:85b3fd62ea1a	1669	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
NYX	0:85b3fd62ea1a	1670	* CCMR1 OC2M LL_TIM_OC_GetMode\n
NYX	0:85b3fd62ea1a	1671	* CCMR2 OC3M LL_TIM_OC_GetMode\n
NYX	0:85b3fd62ea1a	1672	* CCMR2 OC4M LL_TIM_OC_GetMode
NYX	0:85b3fd62ea1a	1673	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1674	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1675	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1676	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1677	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1678	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1679	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1680	* @arg @ref LL_TIM_OCMODE_FROZEN
NYX	0:85b3fd62ea1a	1681	* @arg @ref LL_TIM_OCMODE_ACTIVE
NYX	0:85b3fd62ea1a	1682	* @arg @ref LL_TIM_OCMODE_INACTIVE
NYX	0:85b3fd62ea1a	1683	* @arg @ref LL_TIM_OCMODE_TOGGLE
NYX	0:85b3fd62ea1a	1684	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
NYX	0:85b3fd62ea1a	1685	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
NYX	0:85b3fd62ea1a	1686	* @arg @ref LL_TIM_OCMODE_PWM1
NYX	0:85b3fd62ea1a	1687	* @arg @ref LL_TIM_OCMODE_PWM2
NYX	0:85b3fd62ea1a	1688	*/
NYX	0:85b3fd62ea1a	1689	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1690	{
NYX	0:85b3fd62ea1a	1691	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1692	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1693	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
NYX	0:85b3fd62ea1a	1694	}
NYX	0:85b3fd62ea1a	1695
NYX	0:85b3fd62ea1a	1696	/**
NYX	0:85b3fd62ea1a	1697	* @brief Set the polarity of an output channel.
NYX	0:85b3fd62ea1a	1698	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
NYX	0:85b3fd62ea1a	1699	* CCER CC1NP LL_TIM_OC_SetPolarity\n
NYX	0:85b3fd62ea1a	1700	* CCER CC2P LL_TIM_OC_SetPolarity\n
NYX	0:85b3fd62ea1a	1701	* CCER CC2NP LL_TIM_OC_SetPolarity\n
NYX	0:85b3fd62ea1a	1702	* CCER CC3P LL_TIM_OC_SetPolarity\n
NYX	0:85b3fd62ea1a	1703	* CCER CC3NP LL_TIM_OC_SetPolarity\n
NYX	0:85b3fd62ea1a	1704	* CCER CC4P LL_TIM_OC_SetPolarity
NYX	0:85b3fd62ea1a	1705	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1706	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1707	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1708	* @arg @ref LL_TIM_CHANNEL_CH1N
NYX	0:85b3fd62ea1a	1709	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1710	* @arg @ref LL_TIM_CHANNEL_CH2N
NYX	0:85b3fd62ea1a	1711	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1712	* @arg @ref LL_TIM_CHANNEL_CH3N
NYX	0:85b3fd62ea1a	1713	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1714	* @param Polarity This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1715	* @arg @ref LL_TIM_OCPOLARITY_HIGH
NYX	0:85b3fd62ea1a	1716	* @arg @ref LL_TIM_OCPOLARITY_LOW
NYX	0:85b3fd62ea1a	1717	* @retval None
NYX	0:85b3fd62ea1a	1718	*/
NYX	0:85b3fd62ea1a	1719	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
NYX	0:85b3fd62ea1a	1720	{
NYX	0:85b3fd62ea1a	1721	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1722	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
NYX	0:85b3fd62ea1a	1723	}
NYX	0:85b3fd62ea1a	1724
NYX	0:85b3fd62ea1a	1725	/**
NYX	0:85b3fd62ea1a	1726	* @brief Get the polarity of an output channel.
NYX	0:85b3fd62ea1a	1727	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
NYX	0:85b3fd62ea1a	1728	* CCER CC1NP LL_TIM_OC_GetPolarity\n
NYX	0:85b3fd62ea1a	1729	* CCER CC2P LL_TIM_OC_GetPolarity\n
NYX	0:85b3fd62ea1a	1730	* CCER CC2NP LL_TIM_OC_GetPolarity\n
NYX	0:85b3fd62ea1a	1731	* CCER CC3P LL_TIM_OC_GetPolarity\n
NYX	0:85b3fd62ea1a	1732	* CCER CC3NP LL_TIM_OC_GetPolarity\n
NYX	0:85b3fd62ea1a	1733	* CCER CC4P LL_TIM_OC_GetPolarity
NYX	0:85b3fd62ea1a	1734	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1735	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1736	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1737	* @arg @ref LL_TIM_CHANNEL_CH1N
NYX	0:85b3fd62ea1a	1738	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1739	* @arg @ref LL_TIM_CHANNEL_CH2N
NYX	0:85b3fd62ea1a	1740	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1741	* @arg @ref LL_TIM_CHANNEL_CH3N
NYX	0:85b3fd62ea1a	1742	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1743	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1744	* @arg @ref LL_TIM_OCPOLARITY_HIGH
NYX	0:85b3fd62ea1a	1745	* @arg @ref LL_TIM_OCPOLARITY_LOW
NYX	0:85b3fd62ea1a	1746	*/
NYX	0:85b3fd62ea1a	1747	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1748	{
NYX	0:85b3fd62ea1a	1749	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1750	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
NYX	0:85b3fd62ea1a	1751	}
NYX	0:85b3fd62ea1a	1752
NYX	0:85b3fd62ea1a	1753	/**
NYX	0:85b3fd62ea1a	1754	* @brief Set the IDLE state of an output channel
NYX	0:85b3fd62ea1a	1755	* @note This function is significant only for the timer instances
NYX	0:85b3fd62ea1a	1756	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
NYX	0:85b3fd62ea1a	1757	* can be used to check whether or not a timer instance provides
NYX	0:85b3fd62ea1a	1758	* a break input.
NYX	0:85b3fd62ea1a	1759	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
NYX	0:85b3fd62ea1a	1760	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
NYX	0:85b3fd62ea1a	1761	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
NYX	0:85b3fd62ea1a	1762	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
NYX	0:85b3fd62ea1a	1763	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
NYX	0:85b3fd62ea1a	1764	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
NYX	0:85b3fd62ea1a	1765	* CR2 OIS4 LL_TIM_OC_SetIdleState
NYX	0:85b3fd62ea1a	1766	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1767	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1768	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1769	* @arg @ref LL_TIM_CHANNEL_CH1N
NYX	0:85b3fd62ea1a	1770	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1771	* @arg @ref LL_TIM_CHANNEL_CH2N
NYX	0:85b3fd62ea1a	1772	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1773	* @arg @ref LL_TIM_CHANNEL_CH3N
NYX	0:85b3fd62ea1a	1774	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1775	* @param IdleState This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1776	* @arg @ref LL_TIM_OCIDLESTATE_LOW
NYX	0:85b3fd62ea1a	1777	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
NYX	0:85b3fd62ea1a	1778	* @retval None
NYX	0:85b3fd62ea1a	1779	*/
NYX	0:85b3fd62ea1a	1780	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
NYX	0:85b3fd62ea1a	1781	{
NYX	0:85b3fd62ea1a	1782	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1783	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
NYX	0:85b3fd62ea1a	1784	}
NYX	0:85b3fd62ea1a	1785
NYX	0:85b3fd62ea1a	1786	/**
NYX	0:85b3fd62ea1a	1787	* @brief Get the IDLE state of an output channel
NYX	0:85b3fd62ea1a	1788	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
NYX	0:85b3fd62ea1a	1789	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
NYX	0:85b3fd62ea1a	1790	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
NYX	0:85b3fd62ea1a	1791	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
NYX	0:85b3fd62ea1a	1792	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
NYX	0:85b3fd62ea1a	1793	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
NYX	0:85b3fd62ea1a	1794	* CR2 OIS4 LL_TIM_OC_GetIdleState
NYX	0:85b3fd62ea1a	1795	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1796	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1797	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1798	* @arg @ref LL_TIM_CHANNEL_CH1N
NYX	0:85b3fd62ea1a	1799	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1800	* @arg @ref LL_TIM_CHANNEL_CH2N
NYX	0:85b3fd62ea1a	1801	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1802	* @arg @ref LL_TIM_CHANNEL_CH3N
NYX	0:85b3fd62ea1a	1803	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1804	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1805	* @arg @ref LL_TIM_OCIDLESTATE_LOW
NYX	0:85b3fd62ea1a	1806	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
NYX	0:85b3fd62ea1a	1807	*/
NYX	0:85b3fd62ea1a	1808	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1809	{
NYX	0:85b3fd62ea1a	1810	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1811	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
NYX	0:85b3fd62ea1a	1812	}
NYX	0:85b3fd62ea1a	1813
NYX	0:85b3fd62ea1a	1814	/**
NYX	0:85b3fd62ea1a	1815	* @brief Enable fast mode for the output channel.
NYX	0:85b3fd62ea1a	1816	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
NYX	0:85b3fd62ea1a	1817	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
NYX	0:85b3fd62ea1a	1818	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
NYX	0:85b3fd62ea1a	1819	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
NYX	0:85b3fd62ea1a	1820	* CCMR2 OC4FE LL_TIM_OC_EnableFast
NYX	0:85b3fd62ea1a	1821	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1822	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1823	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1824	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1825	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1826	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1827	* @retval None
NYX	0:85b3fd62ea1a	1828	*/
NYX	0:85b3fd62ea1a	1829	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1830	{
NYX	0:85b3fd62ea1a	1831	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1832	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1833	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
NYX	0:85b3fd62ea1a	1834
NYX	0:85b3fd62ea1a	1835	}
NYX	0:85b3fd62ea1a	1836
NYX	0:85b3fd62ea1a	1837	/**
NYX	0:85b3fd62ea1a	1838	* @brief Disable fast mode for the output channel.
NYX	0:85b3fd62ea1a	1839	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
NYX	0:85b3fd62ea1a	1840	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
NYX	0:85b3fd62ea1a	1841	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
NYX	0:85b3fd62ea1a	1842	* CCMR2 OC4FE LL_TIM_OC_DisableFast
NYX	0:85b3fd62ea1a	1843	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1844	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1845	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1846	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1847	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1848	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1849	* @retval None
NYX	0:85b3fd62ea1a	1850	*/
NYX	0:85b3fd62ea1a	1851	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1852	{
NYX	0:85b3fd62ea1a	1853	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1854	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1855	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
NYX	0:85b3fd62ea1a	1856
NYX	0:85b3fd62ea1a	1857	}
NYX	0:85b3fd62ea1a	1858
NYX	0:85b3fd62ea1a	1859	/**
NYX	0:85b3fd62ea1a	1860	* @brief Indicates whether fast mode is enabled for the output channel.
NYX	0:85b3fd62ea1a	1861	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
NYX	0:85b3fd62ea1a	1862	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
NYX	0:85b3fd62ea1a	1863	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
NYX	0:85b3fd62ea1a	1864	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
NYX	0:85b3fd62ea1a	1865	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1866	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1867	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1868	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1869	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1870	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1871	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1872	*/
NYX	0:85b3fd62ea1a	1873	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1874	{
NYX	0:85b3fd62ea1a	1875	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1876	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1877	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
NYX	0:85b3fd62ea1a	1878	return (READ_BIT(*pReg, bitfield) == bitfield);
NYX	0:85b3fd62ea1a	1879	}
NYX	0:85b3fd62ea1a	1880
NYX	0:85b3fd62ea1a	1881	/**
NYX	0:85b3fd62ea1a	1882	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
NYX	0:85b3fd62ea1a	1883	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
NYX	0:85b3fd62ea1a	1884	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
NYX	0:85b3fd62ea1a	1885	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
NYX	0:85b3fd62ea1a	1886	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
NYX	0:85b3fd62ea1a	1887	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1888	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1889	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1890	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1891	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1892	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1893	* @retval None
NYX	0:85b3fd62ea1a	1894	*/
NYX	0:85b3fd62ea1a	1895	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1896	{
NYX	0:85b3fd62ea1a	1897	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1898	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1899	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
NYX	0:85b3fd62ea1a	1900	}
NYX	0:85b3fd62ea1a	1901
NYX	0:85b3fd62ea1a	1902	/**
NYX	0:85b3fd62ea1a	1903	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
NYX	0:85b3fd62ea1a	1904	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
NYX	0:85b3fd62ea1a	1905	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
NYX	0:85b3fd62ea1a	1906	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
NYX	0:85b3fd62ea1a	1907	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
NYX	0:85b3fd62ea1a	1908	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1909	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1910	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1911	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1912	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1913	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1914	* @retval None
NYX	0:85b3fd62ea1a	1915	*/
NYX	0:85b3fd62ea1a	1916	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1917	{
NYX	0:85b3fd62ea1a	1918	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1919	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1920	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
NYX	0:85b3fd62ea1a	1921	}
NYX	0:85b3fd62ea1a	1922
NYX	0:85b3fd62ea1a	1923	/**
NYX	0:85b3fd62ea1a	1924	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
NYX	0:85b3fd62ea1a	1925	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
NYX	0:85b3fd62ea1a	1926	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
NYX	0:85b3fd62ea1a	1927	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
NYX	0:85b3fd62ea1a	1928	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
NYX	0:85b3fd62ea1a	1929	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1930	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1931	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1932	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1933	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1934	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1935	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1936	*/
NYX	0:85b3fd62ea1a	1937	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1938	{
NYX	0:85b3fd62ea1a	1939	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1940	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1941	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
NYX	0:85b3fd62ea1a	1942	return (READ_BIT(*pReg, bitfield) == bitfield);
NYX	0:85b3fd62ea1a	1943	}
NYX	0:85b3fd62ea1a	1944
NYX	0:85b3fd62ea1a	1945	/**
NYX	0:85b3fd62ea1a	1946	* @brief Enable clearing the output channel on an external event.
NYX	0:85b3fd62ea1a	1947	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
NYX	0:85b3fd62ea1a	1948	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
NYX	0:85b3fd62ea1a	1949	* or not a timer instance can clear the OCxREF signal on an external event.
NYX	0:85b3fd62ea1a	1950	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
NYX	0:85b3fd62ea1a	1951	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
NYX	0:85b3fd62ea1a	1952	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
NYX	0:85b3fd62ea1a	1953	* CCMR2 OC4CE LL_TIM_OC_EnableClear
NYX	0:85b3fd62ea1a	1954	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1955	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1956	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1957	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1958	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1959	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1960	* @retval None
NYX	0:85b3fd62ea1a	1961	*/
NYX	0:85b3fd62ea1a	1962	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1963	{
NYX	0:85b3fd62ea1a	1964	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1965	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1966	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
NYX	0:85b3fd62ea1a	1967	}
NYX	0:85b3fd62ea1a	1968
NYX	0:85b3fd62ea1a	1969	/**
NYX	0:85b3fd62ea1a	1970	* @brief Disable clearing the output channel on an external event.
NYX	0:85b3fd62ea1a	1971	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
NYX	0:85b3fd62ea1a	1972	* or not a timer instance can clear the OCxREF signal on an external event.
NYX	0:85b3fd62ea1a	1973	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
NYX	0:85b3fd62ea1a	1974	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
NYX	0:85b3fd62ea1a	1975	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
NYX	0:85b3fd62ea1a	1976	* CCMR2 OC4CE LL_TIM_OC_DisableClear
NYX	0:85b3fd62ea1a	1977	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	1978	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1979	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	1980	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	1981	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	1982	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	1983	* @retval None
NYX	0:85b3fd62ea1a	1984	*/
NYX	0:85b3fd62ea1a	1985	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	1986	{
NYX	0:85b3fd62ea1a	1987	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	1988	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	1989	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
NYX	0:85b3fd62ea1a	1990	}
NYX	0:85b3fd62ea1a	1991
NYX	0:85b3fd62ea1a	1992	/**
NYX	0:85b3fd62ea1a	1993	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
NYX	0:85b3fd62ea1a	1994	* @note This function enables clearing the output channel on an external event.
NYX	0:85b3fd62ea1a	1995	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
NYX	0:85b3fd62ea1a	1996	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
NYX	0:85b3fd62ea1a	1997	* or not a timer instance can clear the OCxREF signal on an external event.
NYX	0:85b3fd62ea1a	1998	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
NYX	0:85b3fd62ea1a	1999	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
NYX	0:85b3fd62ea1a	2000	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
NYX	0:85b3fd62ea1a	2001	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
NYX	0:85b3fd62ea1a	2002	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2003	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2004	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2005	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2006	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2007	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2008	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2009	*/
NYX	0:85b3fd62ea1a	2010	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	2011	{
NYX	0:85b3fd62ea1a	2012	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2013	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	2014	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
NYX	0:85b3fd62ea1a	2015	return (READ_BIT(*pReg, bitfield) == bitfield);
NYX	0:85b3fd62ea1a	2016	}
NYX	0:85b3fd62ea1a	2017
NYX	0:85b3fd62ea1a	2018	/**
NYX	0:85b3fd62ea1a	2019	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
NYX	0:85b3fd62ea1a	2020	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2021	* dead-time insertion feature is supported by a timer instance.
NYX	0:85b3fd62ea1a	2022	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
NYX	0:85b3fd62ea1a	2023	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
NYX	0:85b3fd62ea1a	2024	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2025	* @param DeadTime between Min_Data=0 and Max_Data=255
NYX	0:85b3fd62ea1a	2026	* @retval None
NYX	0:85b3fd62ea1a	2027	*/
NYX	0:85b3fd62ea1a	2028	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
NYX	0:85b3fd62ea1a	2029	{
NYX	0:85b3fd62ea1a	2030	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
NYX	0:85b3fd62ea1a	2031	}
NYX	0:85b3fd62ea1a	2032
NYX	0:85b3fd62ea1a	2033	/**
NYX	0:85b3fd62ea1a	2034	* @brief Set compare value for output channel 1 (TIMx_CCR1).
NYX	0:85b3fd62ea1a	2035	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2036	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2037	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2038	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2039	* output channel 1 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2040	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
NYX	0:85b3fd62ea1a	2041	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2042	* @param CompareValue between Min_Data=0 and Max_Data=65535
NYX	0:85b3fd62ea1a	2043	* @retval None
NYX	0:85b3fd62ea1a	2044	*/
NYX	0:85b3fd62ea1a	2045	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
NYX	0:85b3fd62ea1a	2046	{
NYX	0:85b3fd62ea1a	2047	WRITE_REG(TIMx->CCR1, CompareValue);
NYX	0:85b3fd62ea1a	2048	}
NYX	0:85b3fd62ea1a	2049
NYX	0:85b3fd62ea1a	2050	/**
NYX	0:85b3fd62ea1a	2051	* @brief Set compare value for output channel 2 (TIMx_CCR2).
NYX	0:85b3fd62ea1a	2052	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2053	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2054	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2055	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2056	* output channel 2 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2057	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
NYX	0:85b3fd62ea1a	2058	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2059	* @param CompareValue between Min_Data=0 and Max_Data=65535
NYX	0:85b3fd62ea1a	2060	* @retval None
NYX	0:85b3fd62ea1a	2061	*/
NYX	0:85b3fd62ea1a	2062	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
NYX	0:85b3fd62ea1a	2063	{
NYX	0:85b3fd62ea1a	2064	WRITE_REG(TIMx->CCR2, CompareValue);
NYX	0:85b3fd62ea1a	2065	}
NYX	0:85b3fd62ea1a	2066
NYX	0:85b3fd62ea1a	2067	/**
NYX	0:85b3fd62ea1a	2068	* @brief Set compare value for output channel 3 (TIMx_CCR3).
NYX	0:85b3fd62ea1a	2069	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2070	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2071	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2072	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2073	* output channel is supported by a timer instance.
NYX	0:85b3fd62ea1a	2074	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
NYX	0:85b3fd62ea1a	2075	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2076	* @param CompareValue between Min_Data=0 and Max_Data=65535
NYX	0:85b3fd62ea1a	2077	* @retval None
NYX	0:85b3fd62ea1a	2078	*/
NYX	0:85b3fd62ea1a	2079	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
NYX	0:85b3fd62ea1a	2080	{
NYX	0:85b3fd62ea1a	2081	WRITE_REG(TIMx->CCR3, CompareValue);
NYX	0:85b3fd62ea1a	2082	}
NYX	0:85b3fd62ea1a	2083
NYX	0:85b3fd62ea1a	2084	/**
NYX	0:85b3fd62ea1a	2085	* @brief Set compare value for output channel 4 (TIMx_CCR4).
NYX	0:85b3fd62ea1a	2086	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2087	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2088	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2089	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2090	* output channel 4 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2091	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
NYX	0:85b3fd62ea1a	2092	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2093	* @param CompareValue between Min_Data=0 and Max_Data=65535
NYX	0:85b3fd62ea1a	2094	* @retval None
NYX	0:85b3fd62ea1a	2095	*/
NYX	0:85b3fd62ea1a	2096	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
NYX	0:85b3fd62ea1a	2097	{
NYX	0:85b3fd62ea1a	2098	WRITE_REG(TIMx->CCR4, CompareValue);
NYX	0:85b3fd62ea1a	2099	}
NYX	0:85b3fd62ea1a	2100
NYX	0:85b3fd62ea1a	2101	/**
NYX	0:85b3fd62ea1a	2102	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
NYX	0:85b3fd62ea1a	2103	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2104	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2105	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2106	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2107	* output channel 1 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2108	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
NYX	0:85b3fd62ea1a	2109	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2110	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	2111	*/
NYX	0:85b3fd62ea1a	2112	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2113	{
NYX	0:85b3fd62ea1a	2114	return (uint32_t)(READ_REG(TIMx->CCR1));
NYX	0:85b3fd62ea1a	2115	}
NYX	0:85b3fd62ea1a	2116
NYX	0:85b3fd62ea1a	2117	/**
NYX	0:85b3fd62ea1a	2118	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
NYX	0:85b3fd62ea1a	2119	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2120	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2121	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2122	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2123	* output channel 2 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2124	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
NYX	0:85b3fd62ea1a	2125	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2126	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	2127	*/
NYX	0:85b3fd62ea1a	2128	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2129	{
NYX	0:85b3fd62ea1a	2130	return (uint32_t)(READ_REG(TIMx->CCR2));
NYX	0:85b3fd62ea1a	2131	}
NYX	0:85b3fd62ea1a	2132
NYX	0:85b3fd62ea1a	2133	/**
NYX	0:85b3fd62ea1a	2134	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
NYX	0:85b3fd62ea1a	2135	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2136	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2137	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2138	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2139	* output channel 3 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2140	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
NYX	0:85b3fd62ea1a	2141	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2142	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	2143	*/
NYX	0:85b3fd62ea1a	2144	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2145	{
NYX	0:85b3fd62ea1a	2146	return (uint32_t)(READ_REG(TIMx->CCR3));
NYX	0:85b3fd62ea1a	2147	}
NYX	0:85b3fd62ea1a	2148
NYX	0:85b3fd62ea1a	2149	/**
NYX	0:85b3fd62ea1a	2150	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
NYX	0:85b3fd62ea1a	2151	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2152	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2153	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2154	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2155	* output channel 4 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2156	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
NYX	0:85b3fd62ea1a	2157	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2158	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	2159	*/
NYX	0:85b3fd62ea1a	2160	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2161	{
NYX	0:85b3fd62ea1a	2162	return (uint32_t)(READ_REG(TIMx->CCR4));
NYX	0:85b3fd62ea1a	2163	}
NYX	0:85b3fd62ea1a	2164
NYX	0:85b3fd62ea1a	2165	/**
NYX	0:85b3fd62ea1a	2166	* @}
NYX	0:85b3fd62ea1a	2167	*/
NYX	0:85b3fd62ea1a	2168
NYX	0:85b3fd62ea1a	2169	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
NYX	0:85b3fd62ea1a	2170	* @{
NYX	0:85b3fd62ea1a	2171	*/
NYX	0:85b3fd62ea1a	2172	/**
NYX	0:85b3fd62ea1a	2173	* @brief Configure input channel.
NYX	0:85b3fd62ea1a	2174	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2175	* CCMR1 IC1PSC LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2176	* CCMR1 IC1F LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2177	* CCMR1 CC2S LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2178	* CCMR1 IC2PSC LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2179	* CCMR1 IC2F LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2180	* CCMR2 CC3S LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2181	* CCMR2 IC3PSC LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2182	* CCMR2 IC3F LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2183	* CCMR2 CC4S LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2184	* CCMR2 IC4PSC LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2185	* CCMR2 IC4F LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2186	* CCER CC1P LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2187	* CCER CC1NP LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2188	* CCER CC2P LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2189	* CCER CC2NP LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2190	* CCER CC3P LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2191	* CCER CC3NP LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2192	* CCER CC4P LL_TIM_IC_Config\n
NYX	0:85b3fd62ea1a	2193	* CCER CC4NP LL_TIM_IC_Config
NYX	0:85b3fd62ea1a	2194	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2195	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2196	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2197	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2198	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2199	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2200	* @param Configuration This parameter must be a combination of all the following values:
NYX	0:85b3fd62ea1a	2201	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
NYX	0:85b3fd62ea1a	2202	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
NYX	0:85b3fd62ea1a	2203	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
NYX	0:85b3fd62ea1a	2204	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
NYX	0:85b3fd62ea1a	2205	* @retval None
NYX	0:85b3fd62ea1a	2206	*/
NYX	0:85b3fd62ea1a	2207	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
NYX	0:85b3fd62ea1a	2208	{
NYX	0:85b3fd62ea1a	2209	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2210	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	2211	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
NYX	0:85b3fd62ea1a	2212	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
NYX	0:85b3fd62ea1a	2213	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
NYX	0:85b3fd62ea1a	2214	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
NYX	0:85b3fd62ea1a	2215	}
NYX	0:85b3fd62ea1a	2216
NYX	0:85b3fd62ea1a	2217	/**
NYX	0:85b3fd62ea1a	2218	* @brief Set the active input.
NYX	0:85b3fd62ea1a	2219	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
NYX	0:85b3fd62ea1a	2220	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
NYX	0:85b3fd62ea1a	2221	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
NYX	0:85b3fd62ea1a	2222	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
NYX	0:85b3fd62ea1a	2223	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2224	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2225	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2226	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2227	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2228	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2229	* @param ICActiveInput This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2230	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
NYX	0:85b3fd62ea1a	2231	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
NYX	0:85b3fd62ea1a	2232	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
NYX	0:85b3fd62ea1a	2233	* @retval None
NYX	0:85b3fd62ea1a	2234	*/
NYX	0:85b3fd62ea1a	2235	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
NYX	0:85b3fd62ea1a	2236	{
NYX	0:85b3fd62ea1a	2237	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2238	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	2239	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
NYX	0:85b3fd62ea1a	2240	}
NYX	0:85b3fd62ea1a	2241
NYX	0:85b3fd62ea1a	2242	/**
NYX	0:85b3fd62ea1a	2243	* @brief Get the current active input.
NYX	0:85b3fd62ea1a	2244	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
NYX	0:85b3fd62ea1a	2245	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
NYX	0:85b3fd62ea1a	2246	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
NYX	0:85b3fd62ea1a	2247	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
NYX	0:85b3fd62ea1a	2248	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2249	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2250	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2251	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2252	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2253	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2254	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	2255	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
NYX	0:85b3fd62ea1a	2256	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
NYX	0:85b3fd62ea1a	2257	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
NYX	0:85b3fd62ea1a	2258	*/
NYX	0:85b3fd62ea1a	2259	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	2260	{
NYX	0:85b3fd62ea1a	2261	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2262	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	2263	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
NYX	0:85b3fd62ea1a	2264	}
NYX	0:85b3fd62ea1a	2265
NYX	0:85b3fd62ea1a	2266	/**
NYX	0:85b3fd62ea1a	2267	* @brief Set the prescaler of input channel.
NYX	0:85b3fd62ea1a	2268	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
NYX	0:85b3fd62ea1a	2269	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
NYX	0:85b3fd62ea1a	2270	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
NYX	0:85b3fd62ea1a	2271	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
NYX	0:85b3fd62ea1a	2272	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2273	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2274	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2275	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2276	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2277	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2278	* @param ICPrescaler This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2279	* @arg @ref LL_TIM_ICPSC_DIV1
NYX	0:85b3fd62ea1a	2280	* @arg @ref LL_TIM_ICPSC_DIV2
NYX	0:85b3fd62ea1a	2281	* @arg @ref LL_TIM_ICPSC_DIV4
NYX	0:85b3fd62ea1a	2282	* @arg @ref LL_TIM_ICPSC_DIV8
NYX	0:85b3fd62ea1a	2283	* @retval None
NYX	0:85b3fd62ea1a	2284	*/
NYX	0:85b3fd62ea1a	2285	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
NYX	0:85b3fd62ea1a	2286	{
NYX	0:85b3fd62ea1a	2287	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2288	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	2289	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
NYX	0:85b3fd62ea1a	2290	}
NYX	0:85b3fd62ea1a	2291
NYX	0:85b3fd62ea1a	2292	/**
NYX	0:85b3fd62ea1a	2293	* @brief Get the current prescaler value acting on an input channel.
NYX	0:85b3fd62ea1a	2294	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
NYX	0:85b3fd62ea1a	2295	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
NYX	0:85b3fd62ea1a	2296	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
NYX	0:85b3fd62ea1a	2297	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
NYX	0:85b3fd62ea1a	2298	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2299	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2300	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2301	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2302	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2303	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2304	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	2305	* @arg @ref LL_TIM_ICPSC_DIV1
NYX	0:85b3fd62ea1a	2306	* @arg @ref LL_TIM_ICPSC_DIV2
NYX	0:85b3fd62ea1a	2307	* @arg @ref LL_TIM_ICPSC_DIV4
NYX	0:85b3fd62ea1a	2308	* @arg @ref LL_TIM_ICPSC_DIV8
NYX	0:85b3fd62ea1a	2309	*/
NYX	0:85b3fd62ea1a	2310	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	2311	{
NYX	0:85b3fd62ea1a	2312	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2313	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	2314	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
NYX	0:85b3fd62ea1a	2315	}
NYX	0:85b3fd62ea1a	2316
NYX	0:85b3fd62ea1a	2317	/**
NYX	0:85b3fd62ea1a	2318	* @brief Set the input filter duration.
NYX	0:85b3fd62ea1a	2319	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
NYX	0:85b3fd62ea1a	2320	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
NYX	0:85b3fd62ea1a	2321	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
NYX	0:85b3fd62ea1a	2322	* CCMR2 IC4F LL_TIM_IC_SetFilter
NYX	0:85b3fd62ea1a	2323	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2324	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2325	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2326	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2327	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2328	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2329	* @param ICFilter This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2330	* @arg @ref LL_TIM_IC_FILTER_FDIV1
NYX	0:85b3fd62ea1a	2331	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
NYX	0:85b3fd62ea1a	2332	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
NYX	0:85b3fd62ea1a	2333	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
NYX	0:85b3fd62ea1a	2334	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
NYX	0:85b3fd62ea1a	2335	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
NYX	0:85b3fd62ea1a	2336	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
NYX	0:85b3fd62ea1a	2337	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
NYX	0:85b3fd62ea1a	2338	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
NYX	0:85b3fd62ea1a	2339	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
NYX	0:85b3fd62ea1a	2340	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
NYX	0:85b3fd62ea1a	2341	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
NYX	0:85b3fd62ea1a	2342	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
NYX	0:85b3fd62ea1a	2343	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
NYX	0:85b3fd62ea1a	2344	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
NYX	0:85b3fd62ea1a	2345	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
NYX	0:85b3fd62ea1a	2346	* @retval None
NYX	0:85b3fd62ea1a	2347	*/
NYX	0:85b3fd62ea1a	2348	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
NYX	0:85b3fd62ea1a	2349	{
NYX	0:85b3fd62ea1a	2350	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2351	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	2352	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
NYX	0:85b3fd62ea1a	2353	}
NYX	0:85b3fd62ea1a	2354
NYX	0:85b3fd62ea1a	2355	/**
NYX	0:85b3fd62ea1a	2356	* @brief Get the input filter duration.
NYX	0:85b3fd62ea1a	2357	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
NYX	0:85b3fd62ea1a	2358	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
NYX	0:85b3fd62ea1a	2359	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
NYX	0:85b3fd62ea1a	2360	* CCMR2 IC4F LL_TIM_IC_GetFilter
NYX	0:85b3fd62ea1a	2361	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2362	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2363	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2364	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2365	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2366	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2367	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	2368	* @arg @ref LL_TIM_IC_FILTER_FDIV1
NYX	0:85b3fd62ea1a	2369	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
NYX	0:85b3fd62ea1a	2370	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
NYX	0:85b3fd62ea1a	2371	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
NYX	0:85b3fd62ea1a	2372	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
NYX	0:85b3fd62ea1a	2373	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
NYX	0:85b3fd62ea1a	2374	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
NYX	0:85b3fd62ea1a	2375	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
NYX	0:85b3fd62ea1a	2376	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
NYX	0:85b3fd62ea1a	2377	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
NYX	0:85b3fd62ea1a	2378	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
NYX	0:85b3fd62ea1a	2379	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
NYX	0:85b3fd62ea1a	2380	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
NYX	0:85b3fd62ea1a	2381	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
NYX	0:85b3fd62ea1a	2382	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
NYX	0:85b3fd62ea1a	2383	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
NYX	0:85b3fd62ea1a	2384	*/
NYX	0:85b3fd62ea1a	2385	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	2386	{
NYX	0:85b3fd62ea1a	2387	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2388	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
NYX	0:85b3fd62ea1a	2389	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
NYX	0:85b3fd62ea1a	2390	}
NYX	0:85b3fd62ea1a	2391
NYX	0:85b3fd62ea1a	2392	/**
NYX	0:85b3fd62ea1a	2393	* @brief Set the input channel polarity.
NYX	0:85b3fd62ea1a	2394	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
NYX	0:85b3fd62ea1a	2395	* CCER CC1NP LL_TIM_IC_SetPolarity\n
NYX	0:85b3fd62ea1a	2396	* CCER CC2P LL_TIM_IC_SetPolarity\n
NYX	0:85b3fd62ea1a	2397	* CCER CC2NP LL_TIM_IC_SetPolarity\n
NYX	0:85b3fd62ea1a	2398	* CCER CC3P LL_TIM_IC_SetPolarity\n
NYX	0:85b3fd62ea1a	2399	* CCER CC3NP LL_TIM_IC_SetPolarity\n
NYX	0:85b3fd62ea1a	2400	* CCER CC4P LL_TIM_IC_SetPolarity\n
NYX	0:85b3fd62ea1a	2401	* CCER CC4NP LL_TIM_IC_SetPolarity
NYX	0:85b3fd62ea1a	2402	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2403	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2404	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2405	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2406	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2407	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2408	* @param ICPolarity This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2409	* @arg @ref LL_TIM_IC_POLARITY_RISING
NYX	0:85b3fd62ea1a	2410	* @arg @ref LL_TIM_IC_POLARITY_FALLING
NYX	0:85b3fd62ea1a	2411	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
NYX	0:85b3fd62ea1a	2412	* @retval None
NYX	0:85b3fd62ea1a	2413	*/
NYX	0:85b3fd62ea1a	2414	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
NYX	0:85b3fd62ea1a	2415	{
NYX	0:85b3fd62ea1a	2416	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2417	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
NYX	0:85b3fd62ea1a	2418	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
NYX	0:85b3fd62ea1a	2419	}
NYX	0:85b3fd62ea1a	2420
NYX	0:85b3fd62ea1a	2421	/**
NYX	0:85b3fd62ea1a	2422	* @brief Get the current input channel polarity.
NYX	0:85b3fd62ea1a	2423	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
NYX	0:85b3fd62ea1a	2424	* CCER CC1NP LL_TIM_IC_GetPolarity\n
NYX	0:85b3fd62ea1a	2425	* CCER CC2P LL_TIM_IC_GetPolarity\n
NYX	0:85b3fd62ea1a	2426	* CCER CC2NP LL_TIM_IC_GetPolarity\n
NYX	0:85b3fd62ea1a	2427	* CCER CC3P LL_TIM_IC_GetPolarity\n
NYX	0:85b3fd62ea1a	2428	* CCER CC3NP LL_TIM_IC_GetPolarity\n
NYX	0:85b3fd62ea1a	2429	* CCER CC4P LL_TIM_IC_GetPolarity\n
NYX	0:85b3fd62ea1a	2430	* CCER CC4NP LL_TIM_IC_GetPolarity
NYX	0:85b3fd62ea1a	2431	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2432	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2433	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	2434	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	2435	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	2436	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	2437	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	2438	* @arg @ref LL_TIM_IC_POLARITY_RISING
NYX	0:85b3fd62ea1a	2439	* @arg @ref LL_TIM_IC_POLARITY_FALLING
NYX	0:85b3fd62ea1a	2440	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
NYX	0:85b3fd62ea1a	2441	*/
NYX	0:85b3fd62ea1a	2442	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
NYX	0:85b3fd62ea1a	2443	{
NYX	0:85b3fd62ea1a	2444	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
NYX	0:85b3fd62ea1a	2445	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
NYX	0:85b3fd62ea1a	2446	SHIFT_TAB_CCxP[iChannel]);
NYX	0:85b3fd62ea1a	2447	}
NYX	0:85b3fd62ea1a	2448
NYX	0:85b3fd62ea1a	2449	/**
NYX	0:85b3fd62ea1a	2450	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
NYX	0:85b3fd62ea1a	2451	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2452	* a timer instance provides an XOR input.
NYX	0:85b3fd62ea1a	2453	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
NYX	0:85b3fd62ea1a	2454	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2455	* @retval None
NYX	0:85b3fd62ea1a	2456	*/
NYX	0:85b3fd62ea1a	2457	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2458	{
NYX	0:85b3fd62ea1a	2459	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
NYX	0:85b3fd62ea1a	2460	}
NYX	0:85b3fd62ea1a	2461
NYX	0:85b3fd62ea1a	2462	/**
NYX	0:85b3fd62ea1a	2463	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
NYX	0:85b3fd62ea1a	2464	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2465	* a timer instance provides an XOR input.
NYX	0:85b3fd62ea1a	2466	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
NYX	0:85b3fd62ea1a	2467	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2468	* @retval None
NYX	0:85b3fd62ea1a	2469	*/
NYX	0:85b3fd62ea1a	2470	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2471	{
NYX	0:85b3fd62ea1a	2472	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
NYX	0:85b3fd62ea1a	2473	}
NYX	0:85b3fd62ea1a	2474
NYX	0:85b3fd62ea1a	2475	/**
NYX	0:85b3fd62ea1a	2476	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
NYX	0:85b3fd62ea1a	2477	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2478	* a timer instance provides an XOR input.
NYX	0:85b3fd62ea1a	2479	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
NYX	0:85b3fd62ea1a	2480	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2481	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2482	*/
NYX	0:85b3fd62ea1a	2483	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2484	{
NYX	0:85b3fd62ea1a	2485	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
NYX	0:85b3fd62ea1a	2486	}
NYX	0:85b3fd62ea1a	2487
NYX	0:85b3fd62ea1a	2488	/**
NYX	0:85b3fd62ea1a	2489	* @brief Get captured value for input channel 1.
NYX	0:85b3fd62ea1a	2490	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2491	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2492	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2493	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2494	* input channel 1 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2495	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
NYX	0:85b3fd62ea1a	2496	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2497	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	2498	*/
NYX	0:85b3fd62ea1a	2499	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2500	{
NYX	0:85b3fd62ea1a	2501	return (uint32_t)(READ_REG(TIMx->CCR1));
NYX	0:85b3fd62ea1a	2502	}
NYX	0:85b3fd62ea1a	2503
NYX	0:85b3fd62ea1a	2504	/**
NYX	0:85b3fd62ea1a	2505	* @brief Get captured value for input channel 2.
NYX	0:85b3fd62ea1a	2506	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2507	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2508	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2509	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2510	* input channel 2 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2511	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
NYX	0:85b3fd62ea1a	2512	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2513	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	2514	*/
NYX	0:85b3fd62ea1a	2515	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2516	{
NYX	0:85b3fd62ea1a	2517	return (uint32_t)(READ_REG(TIMx->CCR2));
NYX	0:85b3fd62ea1a	2518	}
NYX	0:85b3fd62ea1a	2519
NYX	0:85b3fd62ea1a	2520	/**
NYX	0:85b3fd62ea1a	2521	* @brief Get captured value for input channel 3.
NYX	0:85b3fd62ea1a	2522	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2523	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2524	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2525	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2526	* input channel 3 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2527	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
NYX	0:85b3fd62ea1a	2528	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2529	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	2530	*/
NYX	0:85b3fd62ea1a	2531	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2532	{
NYX	0:85b3fd62ea1a	2533	return (uint32_t)(READ_REG(TIMx->CCR3));
NYX	0:85b3fd62ea1a	2534	}
NYX	0:85b3fd62ea1a	2535
NYX	0:85b3fd62ea1a	2536	/**
NYX	0:85b3fd62ea1a	2537	* @brief Get captured value for input channel 4.
NYX	0:85b3fd62ea1a	2538	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
NYX	0:85b3fd62ea1a	2539	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2540	* whether or not a timer instance supports a 32 bits counter.
NYX	0:85b3fd62ea1a	2541	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2542	* input channel 4 is supported by a timer instance.
NYX	0:85b3fd62ea1a	2543	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
NYX	0:85b3fd62ea1a	2544	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2545	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
NYX	0:85b3fd62ea1a	2546	*/
NYX	0:85b3fd62ea1a	2547	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2548	{
NYX	0:85b3fd62ea1a	2549	return (uint32_t)(READ_REG(TIMx->CCR4));
NYX	0:85b3fd62ea1a	2550	}
NYX	0:85b3fd62ea1a	2551
NYX	0:85b3fd62ea1a	2552	/**
NYX	0:85b3fd62ea1a	2553	* @}
NYX	0:85b3fd62ea1a	2554	*/
NYX	0:85b3fd62ea1a	2555
NYX	0:85b3fd62ea1a	2556	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
NYX	0:85b3fd62ea1a	2557	* @{
NYX	0:85b3fd62ea1a	2558	*/
NYX	0:85b3fd62ea1a	2559	/**
NYX	0:85b3fd62ea1a	2560	* @brief Enable external clock mode 2.
NYX	0:85b3fd62ea1a	2561	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
NYX	0:85b3fd62ea1a	2562	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2563	* whether or not a timer instance supports external clock mode2.
NYX	0:85b3fd62ea1a	2564	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
NYX	0:85b3fd62ea1a	2565	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2566	* @retval None
NYX	0:85b3fd62ea1a	2567	*/
NYX	0:85b3fd62ea1a	2568	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2569	{
NYX	0:85b3fd62ea1a	2570	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
NYX	0:85b3fd62ea1a	2571	}
NYX	0:85b3fd62ea1a	2572
NYX	0:85b3fd62ea1a	2573	/**
NYX	0:85b3fd62ea1a	2574	* @brief Disable external clock mode 2.
NYX	0:85b3fd62ea1a	2575	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2576	* whether or not a timer instance supports external clock mode2.
NYX	0:85b3fd62ea1a	2577	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
NYX	0:85b3fd62ea1a	2578	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2579	* @retval None
NYX	0:85b3fd62ea1a	2580	*/
NYX	0:85b3fd62ea1a	2581	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2582	{
NYX	0:85b3fd62ea1a	2583	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
NYX	0:85b3fd62ea1a	2584	}
NYX	0:85b3fd62ea1a	2585
NYX	0:85b3fd62ea1a	2586	/**
NYX	0:85b3fd62ea1a	2587	* @brief Indicate whether external clock mode 2 is enabled.
NYX	0:85b3fd62ea1a	2588	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2589	* whether or not a timer instance supports external clock mode2.
NYX	0:85b3fd62ea1a	2590	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
NYX	0:85b3fd62ea1a	2591	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2592	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2593	*/
NYX	0:85b3fd62ea1a	2594	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2595	{
NYX	0:85b3fd62ea1a	2596	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
NYX	0:85b3fd62ea1a	2597	}
NYX	0:85b3fd62ea1a	2598
NYX	0:85b3fd62ea1a	2599	/**
NYX	0:85b3fd62ea1a	2600	* @brief Set the clock source of the counter clock.
NYX	0:85b3fd62ea1a	2601	* @note when selected clock source is external clock mode 1, the timer input
NYX	0:85b3fd62ea1a	2602	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
NYX	0:85b3fd62ea1a	2603	* function. This timer input must be configured by calling
NYX	0:85b3fd62ea1a	2604	* the @ref LL_TIM_IC_Config() function.
NYX	0:85b3fd62ea1a	2605	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2606	* whether or not a timer instance supports external clock mode1.
NYX	0:85b3fd62ea1a	2607	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2608	* whether or not a timer instance supports external clock mode2.
NYX	0:85b3fd62ea1a	2609	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
NYX	0:85b3fd62ea1a	2610	* SMCR ECE LL_TIM_SetClockSource
NYX	0:85b3fd62ea1a	2611	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2612	* @param ClockSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2613	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
NYX	0:85b3fd62ea1a	2614	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
NYX	0:85b3fd62ea1a	2615	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
NYX	0:85b3fd62ea1a	2616	* @retval None
NYX	0:85b3fd62ea1a	2617	*/
NYX	0:85b3fd62ea1a	2618	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
NYX	0:85b3fd62ea1a	2619	{
NYX	0:85b3fd62ea1a	2620	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
NYX	0:85b3fd62ea1a	2621	}
NYX	0:85b3fd62ea1a	2622
NYX	0:85b3fd62ea1a	2623	/**
NYX	0:85b3fd62ea1a	2624	* @brief Set the encoder interface mode.
NYX	0:85b3fd62ea1a	2625	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2626	* whether or not a timer instance supports the encoder mode.
NYX	0:85b3fd62ea1a	2627	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
NYX	0:85b3fd62ea1a	2628	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2629	* @param EncoderMode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2630	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
NYX	0:85b3fd62ea1a	2631	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
NYX	0:85b3fd62ea1a	2632	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
NYX	0:85b3fd62ea1a	2633	* @retval None
NYX	0:85b3fd62ea1a	2634	*/
NYX	0:85b3fd62ea1a	2635	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
NYX	0:85b3fd62ea1a	2636	{
NYX	0:85b3fd62ea1a	2637	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
NYX	0:85b3fd62ea1a	2638	}
NYX	0:85b3fd62ea1a	2639
NYX	0:85b3fd62ea1a	2640	/**
NYX	0:85b3fd62ea1a	2641	* @}
NYX	0:85b3fd62ea1a	2642	*/
NYX	0:85b3fd62ea1a	2643
NYX	0:85b3fd62ea1a	2644	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
NYX	0:85b3fd62ea1a	2645	* @{
NYX	0:85b3fd62ea1a	2646	*/
NYX	0:85b3fd62ea1a	2647	/**
NYX	0:85b3fd62ea1a	2648	* @brief Set the trigger output (TRGO) used for timer synchronization .
NYX	0:85b3fd62ea1a	2649	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
NYX	0:85b3fd62ea1a	2650	* whether or not a timer instance can operate as a master timer.
NYX	0:85b3fd62ea1a	2651	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
NYX	0:85b3fd62ea1a	2652	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2653	* @param TimerSynchronization This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2654	* @arg @ref LL_TIM_TRGO_RESET
NYX	0:85b3fd62ea1a	2655	* @arg @ref LL_TIM_TRGO_ENABLE
NYX	0:85b3fd62ea1a	2656	* @arg @ref LL_TIM_TRGO_UPDATE
NYX	0:85b3fd62ea1a	2657	* @arg @ref LL_TIM_TRGO_CC1IF
NYX	0:85b3fd62ea1a	2658	* @arg @ref LL_TIM_TRGO_OC1REF
NYX	0:85b3fd62ea1a	2659	* @arg @ref LL_TIM_TRGO_OC2REF
NYX	0:85b3fd62ea1a	2660	* @arg @ref LL_TIM_TRGO_OC3REF
NYX	0:85b3fd62ea1a	2661	* @arg @ref LL_TIM_TRGO_OC4REF
NYX	0:85b3fd62ea1a	2662	* @retval None
NYX	0:85b3fd62ea1a	2663	*/
NYX	0:85b3fd62ea1a	2664	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
NYX	0:85b3fd62ea1a	2665	{
NYX	0:85b3fd62ea1a	2666	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
NYX	0:85b3fd62ea1a	2667	}
NYX	0:85b3fd62ea1a	2668
NYX	0:85b3fd62ea1a	2669	/**
NYX	0:85b3fd62ea1a	2670	* @brief Set the synchronization mode of a slave timer.
NYX	0:85b3fd62ea1a	2671	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2672	* a timer instance can operate as a slave timer.
NYX	0:85b3fd62ea1a	2673	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
NYX	0:85b3fd62ea1a	2674	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2675	* @param SlaveMode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2676	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
NYX	0:85b3fd62ea1a	2677	* @arg @ref LL_TIM_SLAVEMODE_RESET
NYX	0:85b3fd62ea1a	2678	* @arg @ref LL_TIM_SLAVEMODE_GATED
NYX	0:85b3fd62ea1a	2679	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
NYX	0:85b3fd62ea1a	2680	* @retval None
NYX	0:85b3fd62ea1a	2681	*/
NYX	0:85b3fd62ea1a	2682	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
NYX	0:85b3fd62ea1a	2683	{
NYX	0:85b3fd62ea1a	2684	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
NYX	0:85b3fd62ea1a	2685	}
NYX	0:85b3fd62ea1a	2686
NYX	0:85b3fd62ea1a	2687	/**
NYX	0:85b3fd62ea1a	2688	* @brief Set the selects the trigger input to be used to synchronize the counter.
NYX	0:85b3fd62ea1a	2689	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2690	* a timer instance can operate as a slave timer.
NYX	0:85b3fd62ea1a	2691	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
NYX	0:85b3fd62ea1a	2692	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2693	* @param TriggerInput This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2694	* @arg @ref LL_TIM_TS_ITR0
NYX	0:85b3fd62ea1a	2695	* @arg @ref LL_TIM_TS_ITR1
NYX	0:85b3fd62ea1a	2696	* @arg @ref LL_TIM_TS_ITR2
NYX	0:85b3fd62ea1a	2697	* @arg @ref LL_TIM_TS_ITR3
NYX	0:85b3fd62ea1a	2698	* @arg @ref LL_TIM_TS_TI1F_ED
NYX	0:85b3fd62ea1a	2699	* @arg @ref LL_TIM_TS_TI1FP1
NYX	0:85b3fd62ea1a	2700	* @arg @ref LL_TIM_TS_TI2FP2
NYX	0:85b3fd62ea1a	2701	* @arg @ref LL_TIM_TS_ETRF
NYX	0:85b3fd62ea1a	2702	* @retval None
NYX	0:85b3fd62ea1a	2703	*/
NYX	0:85b3fd62ea1a	2704	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
NYX	0:85b3fd62ea1a	2705	{
NYX	0:85b3fd62ea1a	2706	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
NYX	0:85b3fd62ea1a	2707	}
NYX	0:85b3fd62ea1a	2708
NYX	0:85b3fd62ea1a	2709	/**
NYX	0:85b3fd62ea1a	2710	* @brief Enable the Master/Slave mode.
NYX	0:85b3fd62ea1a	2711	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2712	* a timer instance can operate as a slave timer.
NYX	0:85b3fd62ea1a	2713	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
NYX	0:85b3fd62ea1a	2714	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2715	* @retval None
NYX	0:85b3fd62ea1a	2716	*/
NYX	0:85b3fd62ea1a	2717	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2718	{
NYX	0:85b3fd62ea1a	2719	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
NYX	0:85b3fd62ea1a	2720	}
NYX	0:85b3fd62ea1a	2721
NYX	0:85b3fd62ea1a	2722	/**
NYX	0:85b3fd62ea1a	2723	* @brief Disable the Master/Slave mode.
NYX	0:85b3fd62ea1a	2724	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2725	* a timer instance can operate as a slave timer.
NYX	0:85b3fd62ea1a	2726	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
NYX	0:85b3fd62ea1a	2727	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2728	* @retval None
NYX	0:85b3fd62ea1a	2729	*/
NYX	0:85b3fd62ea1a	2730	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2731	{
NYX	0:85b3fd62ea1a	2732	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
NYX	0:85b3fd62ea1a	2733	}
NYX	0:85b3fd62ea1a	2734
NYX	0:85b3fd62ea1a	2735	/**
NYX	0:85b3fd62ea1a	2736	* @brief Indicates whether the Master/Slave mode is enabled.
NYX	0:85b3fd62ea1a	2737	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2738	* a timer instance can operate as a slave timer.
NYX	0:85b3fd62ea1a	2739	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
NYX	0:85b3fd62ea1a	2740	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2741	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2742	*/
NYX	0:85b3fd62ea1a	2743	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2744	{
NYX	0:85b3fd62ea1a	2745	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
NYX	0:85b3fd62ea1a	2746	}
NYX	0:85b3fd62ea1a	2747
NYX	0:85b3fd62ea1a	2748	/**
NYX	0:85b3fd62ea1a	2749	* @brief Configure the external trigger (ETR) input.
NYX	0:85b3fd62ea1a	2750	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2751	* a timer instance provides an external trigger input.
NYX	0:85b3fd62ea1a	2752	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
NYX	0:85b3fd62ea1a	2753	* SMCR ETPS LL_TIM_ConfigETR\n
NYX	0:85b3fd62ea1a	2754	* SMCR ETF LL_TIM_ConfigETR
NYX	0:85b3fd62ea1a	2755	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2756	* @param ETRPolarity This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2757	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
NYX	0:85b3fd62ea1a	2758	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
NYX	0:85b3fd62ea1a	2759	* @param ETRPrescaler This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2760	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
NYX	0:85b3fd62ea1a	2761	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
NYX	0:85b3fd62ea1a	2762	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
NYX	0:85b3fd62ea1a	2763	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
NYX	0:85b3fd62ea1a	2764	* @param ETRFilter This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2765	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
NYX	0:85b3fd62ea1a	2766	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
NYX	0:85b3fd62ea1a	2767	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
NYX	0:85b3fd62ea1a	2768	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
NYX	0:85b3fd62ea1a	2769	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
NYX	0:85b3fd62ea1a	2770	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
NYX	0:85b3fd62ea1a	2771	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
NYX	0:85b3fd62ea1a	2772	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
NYX	0:85b3fd62ea1a	2773	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
NYX	0:85b3fd62ea1a	2774	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
NYX	0:85b3fd62ea1a	2775	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
NYX	0:85b3fd62ea1a	2776	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
NYX	0:85b3fd62ea1a	2777	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
NYX	0:85b3fd62ea1a	2778	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
NYX	0:85b3fd62ea1a	2779	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
NYX	0:85b3fd62ea1a	2780	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
NYX	0:85b3fd62ea1a	2781	* @retval None
NYX	0:85b3fd62ea1a	2782	*/
NYX	0:85b3fd62ea1a	2783	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
NYX	0:85b3fd62ea1a	2784	uint32_t ETRFilter)
NYX	0:85b3fd62ea1a	2785	{
NYX	0:85b3fd62ea1a	2786	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
NYX	0:85b3fd62ea1a	2787	}
NYX	0:85b3fd62ea1a	2788
NYX	0:85b3fd62ea1a	2789	/**
NYX	0:85b3fd62ea1a	2790	* @}
NYX	0:85b3fd62ea1a	2791	*/
NYX	0:85b3fd62ea1a	2792
NYX	0:85b3fd62ea1a	2793	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
NYX	0:85b3fd62ea1a	2794	* @{
NYX	0:85b3fd62ea1a	2795	*/
NYX	0:85b3fd62ea1a	2796	/**
NYX	0:85b3fd62ea1a	2797	* @brief Enable the break function.
NYX	0:85b3fd62ea1a	2798	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2799	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2800	* @rmtoll BDTR BKE LL_TIM_EnableBRK
NYX	0:85b3fd62ea1a	2801	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2802	* @retval None
NYX	0:85b3fd62ea1a	2803	*/
NYX	0:85b3fd62ea1a	2804	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2805	{
NYX	0:85b3fd62ea1a	2806	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
NYX	0:85b3fd62ea1a	2807	}
NYX	0:85b3fd62ea1a	2808
NYX	0:85b3fd62ea1a	2809	/**
NYX	0:85b3fd62ea1a	2810	* @brief Disable the break function.
NYX	0:85b3fd62ea1a	2811	* @rmtoll BDTR BKE LL_TIM_DisableBRK
NYX	0:85b3fd62ea1a	2812	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2813	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2814	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2815	* @retval None
NYX	0:85b3fd62ea1a	2816	*/
NYX	0:85b3fd62ea1a	2817	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2818	{
NYX	0:85b3fd62ea1a	2819	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
NYX	0:85b3fd62ea1a	2820	}
NYX	0:85b3fd62ea1a	2821
NYX	0:85b3fd62ea1a	2822	/**
NYX	0:85b3fd62ea1a	2823	* @brief Configure the break input.
NYX	0:85b3fd62ea1a	2824	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2825	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2826	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
NYX	0:85b3fd62ea1a	2827	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2828	* @param BreakPolarity This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2829	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
NYX	0:85b3fd62ea1a	2830	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
NYX	0:85b3fd62ea1a	2831	* @retval None
NYX	0:85b3fd62ea1a	2832	*/
NYX	0:85b3fd62ea1a	2833	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
NYX	0:85b3fd62ea1a	2834	{
NYX	0:85b3fd62ea1a	2835	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
NYX	0:85b3fd62ea1a	2836	}
NYX	0:85b3fd62ea1a	2837
NYX	0:85b3fd62ea1a	2838	/**
NYX	0:85b3fd62ea1a	2839	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
NYX	0:85b3fd62ea1a	2840	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2841	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2842	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
NYX	0:85b3fd62ea1a	2843	* BDTR OSSR LL_TIM_SetOffStates
NYX	0:85b3fd62ea1a	2844	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2845	* @param OffStateIdle This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2846	* @arg @ref LL_TIM_OSSI_DISABLE
NYX	0:85b3fd62ea1a	2847	* @arg @ref LL_TIM_OSSI_ENABLE
NYX	0:85b3fd62ea1a	2848	* @param OffStateRun This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2849	* @arg @ref LL_TIM_OSSR_DISABLE
NYX	0:85b3fd62ea1a	2850	* @arg @ref LL_TIM_OSSR_ENABLE
NYX	0:85b3fd62ea1a	2851	* @retval None
NYX	0:85b3fd62ea1a	2852	*/
NYX	0:85b3fd62ea1a	2853	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
NYX	0:85b3fd62ea1a	2854	{
NYX	0:85b3fd62ea1a	2855	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
NYX	0:85b3fd62ea1a	2856	}
NYX	0:85b3fd62ea1a	2857
NYX	0:85b3fd62ea1a	2858	/**
NYX	0:85b3fd62ea1a	2859	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
NYX	0:85b3fd62ea1a	2860	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2861	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2862	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
NYX	0:85b3fd62ea1a	2863	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2864	* @retval None
NYX	0:85b3fd62ea1a	2865	*/
NYX	0:85b3fd62ea1a	2866	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2867	{
NYX	0:85b3fd62ea1a	2868	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
NYX	0:85b3fd62ea1a	2869	}
NYX	0:85b3fd62ea1a	2870
NYX	0:85b3fd62ea1a	2871	/**
NYX	0:85b3fd62ea1a	2872	* @brief Disable automatic output (MOE can be set only by software).
NYX	0:85b3fd62ea1a	2873	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2874	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2875	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
NYX	0:85b3fd62ea1a	2876	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2877	* @retval None
NYX	0:85b3fd62ea1a	2878	*/
NYX	0:85b3fd62ea1a	2879	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2880	{
NYX	0:85b3fd62ea1a	2881	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
NYX	0:85b3fd62ea1a	2882	}
NYX	0:85b3fd62ea1a	2883
NYX	0:85b3fd62ea1a	2884	/**
NYX	0:85b3fd62ea1a	2885	* @brief Indicate whether automatic output is enabled.
NYX	0:85b3fd62ea1a	2886	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2887	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2888	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
NYX	0:85b3fd62ea1a	2889	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2890	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2891	*/
NYX	0:85b3fd62ea1a	2892	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2893	{
NYX	0:85b3fd62ea1a	2894	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
NYX	0:85b3fd62ea1a	2895	}
NYX	0:85b3fd62ea1a	2896
NYX	0:85b3fd62ea1a	2897	/**
NYX	0:85b3fd62ea1a	2898	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
NYX	0:85b3fd62ea1a	2899	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
NYX	0:85b3fd62ea1a	2900	* software and is reset in case of break or break2 event
NYX	0:85b3fd62ea1a	2901	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2902	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2903	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
NYX	0:85b3fd62ea1a	2904	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2905	* @retval None
NYX	0:85b3fd62ea1a	2906	*/
NYX	0:85b3fd62ea1a	2907	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2908	{
NYX	0:85b3fd62ea1a	2909	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
NYX	0:85b3fd62ea1a	2910	}
NYX	0:85b3fd62ea1a	2911
NYX	0:85b3fd62ea1a	2912	/**
NYX	0:85b3fd62ea1a	2913	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
NYX	0:85b3fd62ea1a	2914	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
NYX	0:85b3fd62ea1a	2915	* software and is reset in case of break or break2 event.
NYX	0:85b3fd62ea1a	2916	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2917	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2918	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
NYX	0:85b3fd62ea1a	2919	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2920	* @retval None
NYX	0:85b3fd62ea1a	2921	*/
NYX	0:85b3fd62ea1a	2922	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2923	{
NYX	0:85b3fd62ea1a	2924	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
NYX	0:85b3fd62ea1a	2925	}
NYX	0:85b3fd62ea1a	2926
NYX	0:85b3fd62ea1a	2927	/**
NYX	0:85b3fd62ea1a	2928	* @brief Indicates whether outputs are enabled.
NYX	0:85b3fd62ea1a	2929	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	2930	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	2931	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
NYX	0:85b3fd62ea1a	2932	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2933	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2934	*/
NYX	0:85b3fd62ea1a	2935	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	2936	{
NYX	0:85b3fd62ea1a	2937	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
NYX	0:85b3fd62ea1a	2938	}
NYX	0:85b3fd62ea1a	2939
NYX	0:85b3fd62ea1a	2940	/**
NYX	0:85b3fd62ea1a	2941	* @}
NYX	0:85b3fd62ea1a	2942	*/
NYX	0:85b3fd62ea1a	2943
NYX	0:85b3fd62ea1a	2944	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
NYX	0:85b3fd62ea1a	2945	* @{
NYX	0:85b3fd62ea1a	2946	*/
NYX	0:85b3fd62ea1a	2947	/**
NYX	0:85b3fd62ea1a	2948	* @brief Configures the timer DMA burst feature.
NYX	0:85b3fd62ea1a	2949	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
NYX	0:85b3fd62ea1a	2950	* not a timer instance supports the DMA burst mode.
NYX	0:85b3fd62ea1a	2951	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
NYX	0:85b3fd62ea1a	2952	* DCR DBA LL_TIM_ConfigDMABurst
NYX	0:85b3fd62ea1a	2953	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	2954	* @param DMABurstBaseAddress This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2955	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
NYX	0:85b3fd62ea1a	2956	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
NYX	0:85b3fd62ea1a	2957	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
NYX	0:85b3fd62ea1a	2958	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
NYX	0:85b3fd62ea1a	2959	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
NYX	0:85b3fd62ea1a	2960	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
NYX	0:85b3fd62ea1a	2961	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
NYX	0:85b3fd62ea1a	2962	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
NYX	0:85b3fd62ea1a	2963	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
NYX	0:85b3fd62ea1a	2964	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
NYX	0:85b3fd62ea1a	2965	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
NYX	0:85b3fd62ea1a	2966	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
NYX	0:85b3fd62ea1a	2967	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
NYX	0:85b3fd62ea1a	2968	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
NYX	0:85b3fd62ea1a	2969	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
NYX	0:85b3fd62ea1a	2970	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
NYX	0:85b3fd62ea1a	2971	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
NYX	0:85b3fd62ea1a	2972	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
NYX	0:85b3fd62ea1a	2973	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
NYX	0:85b3fd62ea1a	2974	* @param DMABurstLength This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2975	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
NYX	0:85b3fd62ea1a	2976	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
NYX	0:85b3fd62ea1a	2977	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
NYX	0:85b3fd62ea1a	2978	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
NYX	0:85b3fd62ea1a	2979	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
NYX	0:85b3fd62ea1a	2980	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
NYX	0:85b3fd62ea1a	2981	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
NYX	0:85b3fd62ea1a	2982	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
NYX	0:85b3fd62ea1a	2983	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
NYX	0:85b3fd62ea1a	2984	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
NYX	0:85b3fd62ea1a	2985	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
NYX	0:85b3fd62ea1a	2986	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
NYX	0:85b3fd62ea1a	2987	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
NYX	0:85b3fd62ea1a	2988	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
NYX	0:85b3fd62ea1a	2989	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
NYX	0:85b3fd62ea1a	2990	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
NYX	0:85b3fd62ea1a	2991	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
NYX	0:85b3fd62ea1a	2992	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
NYX	0:85b3fd62ea1a	2993	* @retval None
NYX	0:85b3fd62ea1a	2994	*/
NYX	0:85b3fd62ea1a	2995	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
NYX	0:85b3fd62ea1a	2996	{
NYX	0:85b3fd62ea1a	2997	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
NYX	0:85b3fd62ea1a	2998	}
NYX	0:85b3fd62ea1a	2999
NYX	0:85b3fd62ea1a	3000	/**
NYX	0:85b3fd62ea1a	3001	* @}
NYX	0:85b3fd62ea1a	3002	*/
NYX	0:85b3fd62ea1a	3003
NYX	0:85b3fd62ea1a	3004	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
NYX	0:85b3fd62ea1a	3005	* @{
NYX	0:85b3fd62ea1a	3006	*/
NYX	0:85b3fd62ea1a	3007	/**
NYX	0:85b3fd62ea1a	3008	* @brief Remap TIM inputs (input channel, internal/external triggers).
NYX	0:85b3fd62ea1a	3009	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	3010	* a some timer inputs can be remapped.
NYX	0:85b3fd62ea1a	3011	* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
NYX	0:85b3fd62ea1a	3012	* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
NYX	0:85b3fd62ea1a	3013	* TIM11_OR TI1_RMP LL_TIM_SetRemap
NYX	0:85b3fd62ea1a	3014	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3015	* @param Remap Remap param depends on the TIMx. Description available only
NYX	0:85b3fd62ea1a	3016	* in CHM version of the User Manual (not in .pdf).
NYX	0:85b3fd62ea1a	3017	* Otherwise see Reference Manual description of OR registers.
NYX	0:85b3fd62ea1a	3018	*
NYX	0:85b3fd62ea1a	3019	* Below description summarizes "Timer Instance" and "Remap" param combinations:
NYX	0:85b3fd62ea1a	3020	*
NYX	0:85b3fd62ea1a	3021	* TIM2: one of the following values
NYX	0:85b3fd62ea1a	3022	*
NYX	0:85b3fd62ea1a	3023	* ITR1_RMP can be one of the following values
NYX	0:85b3fd62ea1a	3024	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
NYX	0:85b3fd62ea1a	3025	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
NYX	0:85b3fd62ea1a	3026	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
NYX	0:85b3fd62ea1a	3027	*
NYX	0:85b3fd62ea1a	3028	* TIM5: one of the following values
NYX	0:85b3fd62ea1a	3029	*
NYX	0:85b3fd62ea1a	3030	* @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
NYX	0:85b3fd62ea1a	3031	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
NYX	0:85b3fd62ea1a	3032	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
NYX	0:85b3fd62ea1a	3033	* @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
NYX	0:85b3fd62ea1a	3034	*
NYX	0:85b3fd62ea1a	3035	* TIM11: one of the following values
NYX	0:85b3fd62ea1a	3036	*
NYX	0:85b3fd62ea1a	3037	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
NYX	0:85b3fd62ea1a	3038	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1
NYX	0:85b3fd62ea1a	3039	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC
NYX	0:85b3fd62ea1a	3040	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2
NYX	0:85b3fd62ea1a	3041	*
NYX	0:85b3fd62ea1a	3042	* @retval None
NYX	0:85b3fd62ea1a	3043	*/
NYX	0:85b3fd62ea1a	3044	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
NYX	0:85b3fd62ea1a	3045	{
NYX	0:85b3fd62ea1a	3046	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
NYX	0:85b3fd62ea1a	3047	}
NYX	0:85b3fd62ea1a	3048
NYX	0:85b3fd62ea1a	3049	/**
NYX	0:85b3fd62ea1a	3050	* @}
NYX	0:85b3fd62ea1a	3051	*/
NYX	0:85b3fd62ea1a	3052
NYX	0:85b3fd62ea1a	3053
NYX	0:85b3fd62ea1a	3054	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
NYX	0:85b3fd62ea1a	3055	* @{
NYX	0:85b3fd62ea1a	3056	*/
NYX	0:85b3fd62ea1a	3057	/**
NYX	0:85b3fd62ea1a	3058	* @brief Clear the update interrupt flag (UIF).
NYX	0:85b3fd62ea1a	3059	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
NYX	0:85b3fd62ea1a	3060	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3061	* @retval None
NYX	0:85b3fd62ea1a	3062	*/
NYX	0:85b3fd62ea1a	3063	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3064	{
NYX	0:85b3fd62ea1a	3065	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
NYX	0:85b3fd62ea1a	3066	}
NYX	0:85b3fd62ea1a	3067
NYX	0:85b3fd62ea1a	3068	/**
NYX	0:85b3fd62ea1a	3069	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
NYX	0:85b3fd62ea1a	3070	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
NYX	0:85b3fd62ea1a	3071	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3072	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3073	*/
NYX	0:85b3fd62ea1a	3074	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3075	{
NYX	0:85b3fd62ea1a	3076	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
NYX	0:85b3fd62ea1a	3077	}
NYX	0:85b3fd62ea1a	3078
NYX	0:85b3fd62ea1a	3079	/**
NYX	0:85b3fd62ea1a	3080	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
NYX	0:85b3fd62ea1a	3081	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
NYX	0:85b3fd62ea1a	3082	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3083	* @retval None
NYX	0:85b3fd62ea1a	3084	*/
NYX	0:85b3fd62ea1a	3085	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3086	{
NYX	0:85b3fd62ea1a	3087	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
NYX	0:85b3fd62ea1a	3088	}
NYX	0:85b3fd62ea1a	3089
NYX	0:85b3fd62ea1a	3090	/**
NYX	0:85b3fd62ea1a	3091	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
NYX	0:85b3fd62ea1a	3092	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
NYX	0:85b3fd62ea1a	3093	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3094	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3095	*/
NYX	0:85b3fd62ea1a	3096	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3097	{
NYX	0:85b3fd62ea1a	3098	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
NYX	0:85b3fd62ea1a	3099	}
NYX	0:85b3fd62ea1a	3100
NYX	0:85b3fd62ea1a	3101	/**
NYX	0:85b3fd62ea1a	3102	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
NYX	0:85b3fd62ea1a	3103	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
NYX	0:85b3fd62ea1a	3104	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3105	* @retval None
NYX	0:85b3fd62ea1a	3106	*/
NYX	0:85b3fd62ea1a	3107	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3108	{
NYX	0:85b3fd62ea1a	3109	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
NYX	0:85b3fd62ea1a	3110	}
NYX	0:85b3fd62ea1a	3111
NYX	0:85b3fd62ea1a	3112	/**
NYX	0:85b3fd62ea1a	3113	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
NYX	0:85b3fd62ea1a	3114	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
NYX	0:85b3fd62ea1a	3115	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3116	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3117	*/
NYX	0:85b3fd62ea1a	3118	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3119	{
NYX	0:85b3fd62ea1a	3120	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
NYX	0:85b3fd62ea1a	3121	}
NYX	0:85b3fd62ea1a	3122
NYX	0:85b3fd62ea1a	3123	/**
NYX	0:85b3fd62ea1a	3124	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
NYX	0:85b3fd62ea1a	3125	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
NYX	0:85b3fd62ea1a	3126	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3127	* @retval None
NYX	0:85b3fd62ea1a	3128	*/
NYX	0:85b3fd62ea1a	3129	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3130	{
NYX	0:85b3fd62ea1a	3131	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
NYX	0:85b3fd62ea1a	3132	}
NYX	0:85b3fd62ea1a	3133
NYX	0:85b3fd62ea1a	3134	/**
NYX	0:85b3fd62ea1a	3135	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
NYX	0:85b3fd62ea1a	3136	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
NYX	0:85b3fd62ea1a	3137	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3138	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3139	*/
NYX	0:85b3fd62ea1a	3140	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3141	{
NYX	0:85b3fd62ea1a	3142	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
NYX	0:85b3fd62ea1a	3143	}
NYX	0:85b3fd62ea1a	3144
NYX	0:85b3fd62ea1a	3145	/**
NYX	0:85b3fd62ea1a	3146	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
NYX	0:85b3fd62ea1a	3147	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
NYX	0:85b3fd62ea1a	3148	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3149	* @retval None
NYX	0:85b3fd62ea1a	3150	*/
NYX	0:85b3fd62ea1a	3151	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3152	{
NYX	0:85b3fd62ea1a	3153	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
NYX	0:85b3fd62ea1a	3154	}
NYX	0:85b3fd62ea1a	3155
NYX	0:85b3fd62ea1a	3156	/**
NYX	0:85b3fd62ea1a	3157	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
NYX	0:85b3fd62ea1a	3158	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
NYX	0:85b3fd62ea1a	3159	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3160	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3161	*/
NYX	0:85b3fd62ea1a	3162	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3163	{
NYX	0:85b3fd62ea1a	3164	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
NYX	0:85b3fd62ea1a	3165	}
NYX	0:85b3fd62ea1a	3166
NYX	0:85b3fd62ea1a	3167	/**
NYX	0:85b3fd62ea1a	3168	* @brief Clear the commutation interrupt flag (COMIF).
NYX	0:85b3fd62ea1a	3169	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
NYX	0:85b3fd62ea1a	3170	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3171	* @retval None
NYX	0:85b3fd62ea1a	3172	*/
NYX	0:85b3fd62ea1a	3173	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3174	{
NYX	0:85b3fd62ea1a	3175	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
NYX	0:85b3fd62ea1a	3176	}
NYX	0:85b3fd62ea1a	3177
NYX	0:85b3fd62ea1a	3178	/**
NYX	0:85b3fd62ea1a	3179	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
NYX	0:85b3fd62ea1a	3180	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
NYX	0:85b3fd62ea1a	3181	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3182	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3183	*/
NYX	0:85b3fd62ea1a	3184	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3185	{
NYX	0:85b3fd62ea1a	3186	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
NYX	0:85b3fd62ea1a	3187	}
NYX	0:85b3fd62ea1a	3188
NYX	0:85b3fd62ea1a	3189	/**
NYX	0:85b3fd62ea1a	3190	* @brief Clear the trigger interrupt flag (TIF).
NYX	0:85b3fd62ea1a	3191	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
NYX	0:85b3fd62ea1a	3192	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3193	* @retval None
NYX	0:85b3fd62ea1a	3194	*/
NYX	0:85b3fd62ea1a	3195	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3196	{
NYX	0:85b3fd62ea1a	3197	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
NYX	0:85b3fd62ea1a	3198	}
NYX	0:85b3fd62ea1a	3199
NYX	0:85b3fd62ea1a	3200	/**
NYX	0:85b3fd62ea1a	3201	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
NYX	0:85b3fd62ea1a	3202	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
NYX	0:85b3fd62ea1a	3203	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3204	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3205	*/
NYX	0:85b3fd62ea1a	3206	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3207	{
NYX	0:85b3fd62ea1a	3208	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
NYX	0:85b3fd62ea1a	3209	}
NYX	0:85b3fd62ea1a	3210
NYX	0:85b3fd62ea1a	3211	/**
NYX	0:85b3fd62ea1a	3212	* @brief Clear the break interrupt flag (BIF).
NYX	0:85b3fd62ea1a	3213	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
NYX	0:85b3fd62ea1a	3214	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3215	* @retval None
NYX	0:85b3fd62ea1a	3216	*/
NYX	0:85b3fd62ea1a	3217	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3218	{
NYX	0:85b3fd62ea1a	3219	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
NYX	0:85b3fd62ea1a	3220	}
NYX	0:85b3fd62ea1a	3221
NYX	0:85b3fd62ea1a	3222	/**
NYX	0:85b3fd62ea1a	3223	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
NYX	0:85b3fd62ea1a	3224	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
NYX	0:85b3fd62ea1a	3225	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3226	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3227	*/
NYX	0:85b3fd62ea1a	3228	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3229	{
NYX	0:85b3fd62ea1a	3230	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
NYX	0:85b3fd62ea1a	3231	}
NYX	0:85b3fd62ea1a	3232
NYX	0:85b3fd62ea1a	3233	/**
NYX	0:85b3fd62ea1a	3234	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
NYX	0:85b3fd62ea1a	3235	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
NYX	0:85b3fd62ea1a	3236	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3237	* @retval None
NYX	0:85b3fd62ea1a	3238	*/
NYX	0:85b3fd62ea1a	3239	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3240	{
NYX	0:85b3fd62ea1a	3241	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
NYX	0:85b3fd62ea1a	3242	}
NYX	0:85b3fd62ea1a	3243
NYX	0:85b3fd62ea1a	3244	/**
NYX	0:85b3fd62ea1a	3245	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
NYX	0:85b3fd62ea1a	3246	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
NYX	0:85b3fd62ea1a	3247	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3248	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3249	*/
NYX	0:85b3fd62ea1a	3250	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3251	{
NYX	0:85b3fd62ea1a	3252	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
NYX	0:85b3fd62ea1a	3253	}
NYX	0:85b3fd62ea1a	3254
NYX	0:85b3fd62ea1a	3255	/**
NYX	0:85b3fd62ea1a	3256	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
NYX	0:85b3fd62ea1a	3257	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
NYX	0:85b3fd62ea1a	3258	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3259	* @retval None
NYX	0:85b3fd62ea1a	3260	*/
NYX	0:85b3fd62ea1a	3261	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3262	{
NYX	0:85b3fd62ea1a	3263	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
NYX	0:85b3fd62ea1a	3264	}
NYX	0:85b3fd62ea1a	3265
NYX	0:85b3fd62ea1a	3266	/**
NYX	0:85b3fd62ea1a	3267	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
NYX	0:85b3fd62ea1a	3268	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
NYX	0:85b3fd62ea1a	3269	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3270	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3271	*/
NYX	0:85b3fd62ea1a	3272	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3273	{
NYX	0:85b3fd62ea1a	3274	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
NYX	0:85b3fd62ea1a	3275	}
NYX	0:85b3fd62ea1a	3276
NYX	0:85b3fd62ea1a	3277	/**
NYX	0:85b3fd62ea1a	3278	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
NYX	0:85b3fd62ea1a	3279	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
NYX	0:85b3fd62ea1a	3280	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3281	* @retval None
NYX	0:85b3fd62ea1a	3282	*/
NYX	0:85b3fd62ea1a	3283	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3284	{
NYX	0:85b3fd62ea1a	3285	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
NYX	0:85b3fd62ea1a	3286	}
NYX	0:85b3fd62ea1a	3287
NYX	0:85b3fd62ea1a	3288	/**
NYX	0:85b3fd62ea1a	3289	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
NYX	0:85b3fd62ea1a	3290	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
NYX	0:85b3fd62ea1a	3291	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3292	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3293	*/
NYX	0:85b3fd62ea1a	3294	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3295	{
NYX	0:85b3fd62ea1a	3296	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
NYX	0:85b3fd62ea1a	3297	}
NYX	0:85b3fd62ea1a	3298
NYX	0:85b3fd62ea1a	3299	/**
NYX	0:85b3fd62ea1a	3300	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
NYX	0:85b3fd62ea1a	3301	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
NYX	0:85b3fd62ea1a	3302	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3303	* @retval None
NYX	0:85b3fd62ea1a	3304	*/
NYX	0:85b3fd62ea1a	3305	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3306	{
NYX	0:85b3fd62ea1a	3307	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
NYX	0:85b3fd62ea1a	3308	}
NYX	0:85b3fd62ea1a	3309
NYX	0:85b3fd62ea1a	3310	/**
NYX	0:85b3fd62ea1a	3311	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
NYX	0:85b3fd62ea1a	3312	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
NYX	0:85b3fd62ea1a	3313	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3314	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3315	*/
NYX	0:85b3fd62ea1a	3316	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3317	{
NYX	0:85b3fd62ea1a	3318	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
NYX	0:85b3fd62ea1a	3319	}
NYX	0:85b3fd62ea1a	3320
NYX	0:85b3fd62ea1a	3321	/**
NYX	0:85b3fd62ea1a	3322	* @}
NYX	0:85b3fd62ea1a	3323	*/
NYX	0:85b3fd62ea1a	3324
NYX	0:85b3fd62ea1a	3325	/** @defgroup TIM_LL_EF_IT_Management IT-Management
NYX	0:85b3fd62ea1a	3326	* @{
NYX	0:85b3fd62ea1a	3327	*/
NYX	0:85b3fd62ea1a	3328	/**
NYX	0:85b3fd62ea1a	3329	* @brief Enable update interrupt (UIE).
NYX	0:85b3fd62ea1a	3330	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
NYX	0:85b3fd62ea1a	3331	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3332	* @retval None
NYX	0:85b3fd62ea1a	3333	*/
NYX	0:85b3fd62ea1a	3334	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3335	{
NYX	0:85b3fd62ea1a	3336	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
NYX	0:85b3fd62ea1a	3337	}
NYX	0:85b3fd62ea1a	3338
NYX	0:85b3fd62ea1a	3339	/**
NYX	0:85b3fd62ea1a	3340	* @brief Disable update interrupt (UIE).
NYX	0:85b3fd62ea1a	3341	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
NYX	0:85b3fd62ea1a	3342	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3343	* @retval None
NYX	0:85b3fd62ea1a	3344	*/
NYX	0:85b3fd62ea1a	3345	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3346	{
NYX	0:85b3fd62ea1a	3347	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
NYX	0:85b3fd62ea1a	3348	}
NYX	0:85b3fd62ea1a	3349
NYX	0:85b3fd62ea1a	3350	/**
NYX	0:85b3fd62ea1a	3351	* @brief Indicates whether the update interrupt (UIE) is enabled.
NYX	0:85b3fd62ea1a	3352	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
NYX	0:85b3fd62ea1a	3353	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3354	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3355	*/
NYX	0:85b3fd62ea1a	3356	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3357	{
NYX	0:85b3fd62ea1a	3358	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
NYX	0:85b3fd62ea1a	3359	}
NYX	0:85b3fd62ea1a	3360
NYX	0:85b3fd62ea1a	3361	/**
NYX	0:85b3fd62ea1a	3362	* @brief Enable capture/compare 1 interrupt (CC1IE).
NYX	0:85b3fd62ea1a	3363	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
NYX	0:85b3fd62ea1a	3364	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3365	* @retval None
NYX	0:85b3fd62ea1a	3366	*/
NYX	0:85b3fd62ea1a	3367	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3368	{
NYX	0:85b3fd62ea1a	3369	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
NYX	0:85b3fd62ea1a	3370	}
NYX	0:85b3fd62ea1a	3371
NYX	0:85b3fd62ea1a	3372	/**
NYX	0:85b3fd62ea1a	3373	* @brief Disable capture/compare 1 interrupt (CC1IE).
NYX	0:85b3fd62ea1a	3374	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
NYX	0:85b3fd62ea1a	3375	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3376	* @retval None
NYX	0:85b3fd62ea1a	3377	*/
NYX	0:85b3fd62ea1a	3378	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3379	{
NYX	0:85b3fd62ea1a	3380	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
NYX	0:85b3fd62ea1a	3381	}
NYX	0:85b3fd62ea1a	3382
NYX	0:85b3fd62ea1a	3383	/**
NYX	0:85b3fd62ea1a	3384	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
NYX	0:85b3fd62ea1a	3385	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
NYX	0:85b3fd62ea1a	3386	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3387	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3388	*/
NYX	0:85b3fd62ea1a	3389	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3390	{
NYX	0:85b3fd62ea1a	3391	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
NYX	0:85b3fd62ea1a	3392	}
NYX	0:85b3fd62ea1a	3393
NYX	0:85b3fd62ea1a	3394	/**
NYX	0:85b3fd62ea1a	3395	* @brief Enable capture/compare 2 interrupt (CC2IE).
NYX	0:85b3fd62ea1a	3396	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
NYX	0:85b3fd62ea1a	3397	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3398	* @retval None
NYX	0:85b3fd62ea1a	3399	*/
NYX	0:85b3fd62ea1a	3400	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3401	{
NYX	0:85b3fd62ea1a	3402	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
NYX	0:85b3fd62ea1a	3403	}
NYX	0:85b3fd62ea1a	3404
NYX	0:85b3fd62ea1a	3405	/**
NYX	0:85b3fd62ea1a	3406	* @brief Disable capture/compare 2 interrupt (CC2IE).
NYX	0:85b3fd62ea1a	3407	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
NYX	0:85b3fd62ea1a	3408	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3409	* @retval None
NYX	0:85b3fd62ea1a	3410	*/
NYX	0:85b3fd62ea1a	3411	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3412	{
NYX	0:85b3fd62ea1a	3413	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
NYX	0:85b3fd62ea1a	3414	}
NYX	0:85b3fd62ea1a	3415
NYX	0:85b3fd62ea1a	3416	/**
NYX	0:85b3fd62ea1a	3417	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
NYX	0:85b3fd62ea1a	3418	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
NYX	0:85b3fd62ea1a	3419	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3420	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3421	*/
NYX	0:85b3fd62ea1a	3422	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3423	{
NYX	0:85b3fd62ea1a	3424	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
NYX	0:85b3fd62ea1a	3425	}
NYX	0:85b3fd62ea1a	3426
NYX	0:85b3fd62ea1a	3427	/**
NYX	0:85b3fd62ea1a	3428	* @brief Enable capture/compare 3 interrupt (CC3IE).
NYX	0:85b3fd62ea1a	3429	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
NYX	0:85b3fd62ea1a	3430	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3431	* @retval None
NYX	0:85b3fd62ea1a	3432	*/
NYX	0:85b3fd62ea1a	3433	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3434	{
NYX	0:85b3fd62ea1a	3435	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
NYX	0:85b3fd62ea1a	3436	}
NYX	0:85b3fd62ea1a	3437
NYX	0:85b3fd62ea1a	3438	/**
NYX	0:85b3fd62ea1a	3439	* @brief Disable capture/compare 3 interrupt (CC3IE).
NYX	0:85b3fd62ea1a	3440	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
NYX	0:85b3fd62ea1a	3441	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3442	* @retval None
NYX	0:85b3fd62ea1a	3443	*/
NYX	0:85b3fd62ea1a	3444	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3445	{
NYX	0:85b3fd62ea1a	3446	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
NYX	0:85b3fd62ea1a	3447	}
NYX	0:85b3fd62ea1a	3448
NYX	0:85b3fd62ea1a	3449	/**
NYX	0:85b3fd62ea1a	3450	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
NYX	0:85b3fd62ea1a	3451	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
NYX	0:85b3fd62ea1a	3452	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3453	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3454	*/
NYX	0:85b3fd62ea1a	3455	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3456	{
NYX	0:85b3fd62ea1a	3457	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
NYX	0:85b3fd62ea1a	3458	}
NYX	0:85b3fd62ea1a	3459
NYX	0:85b3fd62ea1a	3460	/**
NYX	0:85b3fd62ea1a	3461	* @brief Enable capture/compare 4 interrupt (CC4IE).
NYX	0:85b3fd62ea1a	3462	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
NYX	0:85b3fd62ea1a	3463	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3464	* @retval None
NYX	0:85b3fd62ea1a	3465	*/
NYX	0:85b3fd62ea1a	3466	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3467	{
NYX	0:85b3fd62ea1a	3468	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
NYX	0:85b3fd62ea1a	3469	}
NYX	0:85b3fd62ea1a	3470
NYX	0:85b3fd62ea1a	3471	/**
NYX	0:85b3fd62ea1a	3472	* @brief Disable capture/compare 4 interrupt (CC4IE).
NYX	0:85b3fd62ea1a	3473	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
NYX	0:85b3fd62ea1a	3474	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3475	* @retval None
NYX	0:85b3fd62ea1a	3476	*/
NYX	0:85b3fd62ea1a	3477	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3478	{
NYX	0:85b3fd62ea1a	3479	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
NYX	0:85b3fd62ea1a	3480	}
NYX	0:85b3fd62ea1a	3481
NYX	0:85b3fd62ea1a	3482	/**
NYX	0:85b3fd62ea1a	3483	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
NYX	0:85b3fd62ea1a	3484	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
NYX	0:85b3fd62ea1a	3485	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3486	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3487	*/
NYX	0:85b3fd62ea1a	3488	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3489	{
NYX	0:85b3fd62ea1a	3490	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
NYX	0:85b3fd62ea1a	3491	}
NYX	0:85b3fd62ea1a	3492
NYX	0:85b3fd62ea1a	3493	/**
NYX	0:85b3fd62ea1a	3494	* @brief Enable commutation interrupt (COMIE).
NYX	0:85b3fd62ea1a	3495	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
NYX	0:85b3fd62ea1a	3496	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3497	* @retval None
NYX	0:85b3fd62ea1a	3498	*/
NYX	0:85b3fd62ea1a	3499	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3500	{
NYX	0:85b3fd62ea1a	3501	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
NYX	0:85b3fd62ea1a	3502	}
NYX	0:85b3fd62ea1a	3503
NYX	0:85b3fd62ea1a	3504	/**
NYX	0:85b3fd62ea1a	3505	* @brief Disable commutation interrupt (COMIE).
NYX	0:85b3fd62ea1a	3506	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
NYX	0:85b3fd62ea1a	3507	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3508	* @retval None
NYX	0:85b3fd62ea1a	3509	*/
NYX	0:85b3fd62ea1a	3510	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3511	{
NYX	0:85b3fd62ea1a	3512	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
NYX	0:85b3fd62ea1a	3513	}
NYX	0:85b3fd62ea1a	3514
NYX	0:85b3fd62ea1a	3515	/**
NYX	0:85b3fd62ea1a	3516	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
NYX	0:85b3fd62ea1a	3517	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
NYX	0:85b3fd62ea1a	3518	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3519	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3520	*/
NYX	0:85b3fd62ea1a	3521	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3522	{
NYX	0:85b3fd62ea1a	3523	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
NYX	0:85b3fd62ea1a	3524	}
NYX	0:85b3fd62ea1a	3525
NYX	0:85b3fd62ea1a	3526	/**
NYX	0:85b3fd62ea1a	3527	* @brief Enable trigger interrupt (TIE).
NYX	0:85b3fd62ea1a	3528	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
NYX	0:85b3fd62ea1a	3529	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3530	* @retval None
NYX	0:85b3fd62ea1a	3531	*/
NYX	0:85b3fd62ea1a	3532	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3533	{
NYX	0:85b3fd62ea1a	3534	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
NYX	0:85b3fd62ea1a	3535	}
NYX	0:85b3fd62ea1a	3536
NYX	0:85b3fd62ea1a	3537	/**
NYX	0:85b3fd62ea1a	3538	* @brief Disable trigger interrupt (TIE).
NYX	0:85b3fd62ea1a	3539	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
NYX	0:85b3fd62ea1a	3540	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3541	* @retval None
NYX	0:85b3fd62ea1a	3542	*/
NYX	0:85b3fd62ea1a	3543	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3544	{
NYX	0:85b3fd62ea1a	3545	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
NYX	0:85b3fd62ea1a	3546	}
NYX	0:85b3fd62ea1a	3547
NYX	0:85b3fd62ea1a	3548	/**
NYX	0:85b3fd62ea1a	3549	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
NYX	0:85b3fd62ea1a	3550	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
NYX	0:85b3fd62ea1a	3551	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3552	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3553	*/
NYX	0:85b3fd62ea1a	3554	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3555	{
NYX	0:85b3fd62ea1a	3556	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
NYX	0:85b3fd62ea1a	3557	}
NYX	0:85b3fd62ea1a	3558
NYX	0:85b3fd62ea1a	3559	/**
NYX	0:85b3fd62ea1a	3560	* @brief Enable break interrupt (BIE).
NYX	0:85b3fd62ea1a	3561	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
NYX	0:85b3fd62ea1a	3562	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3563	* @retval None
NYX	0:85b3fd62ea1a	3564	*/
NYX	0:85b3fd62ea1a	3565	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3566	{
NYX	0:85b3fd62ea1a	3567	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
NYX	0:85b3fd62ea1a	3568	}
NYX	0:85b3fd62ea1a	3569
NYX	0:85b3fd62ea1a	3570	/**
NYX	0:85b3fd62ea1a	3571	* @brief Disable break interrupt (BIE).
NYX	0:85b3fd62ea1a	3572	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
NYX	0:85b3fd62ea1a	3573	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3574	* @retval None
NYX	0:85b3fd62ea1a	3575	*/
NYX	0:85b3fd62ea1a	3576	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3577	{
NYX	0:85b3fd62ea1a	3578	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
NYX	0:85b3fd62ea1a	3579	}
NYX	0:85b3fd62ea1a	3580
NYX	0:85b3fd62ea1a	3581	/**
NYX	0:85b3fd62ea1a	3582	* @brief Indicates whether the break interrupt (BIE) is enabled.
NYX	0:85b3fd62ea1a	3583	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
NYX	0:85b3fd62ea1a	3584	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3585	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3586	*/
NYX	0:85b3fd62ea1a	3587	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3588	{
NYX	0:85b3fd62ea1a	3589	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
NYX	0:85b3fd62ea1a	3590	}
NYX	0:85b3fd62ea1a	3591
NYX	0:85b3fd62ea1a	3592	/**
NYX	0:85b3fd62ea1a	3593	* @}
NYX	0:85b3fd62ea1a	3594	*/
NYX	0:85b3fd62ea1a	3595
NYX	0:85b3fd62ea1a	3596	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
NYX	0:85b3fd62ea1a	3597	* @{
NYX	0:85b3fd62ea1a	3598	*/
NYX	0:85b3fd62ea1a	3599	/**
NYX	0:85b3fd62ea1a	3600	* @brief Enable update DMA request (UDE).
NYX	0:85b3fd62ea1a	3601	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
NYX	0:85b3fd62ea1a	3602	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3603	* @retval None
NYX	0:85b3fd62ea1a	3604	*/
NYX	0:85b3fd62ea1a	3605	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3606	{
NYX	0:85b3fd62ea1a	3607	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
NYX	0:85b3fd62ea1a	3608	}
NYX	0:85b3fd62ea1a	3609
NYX	0:85b3fd62ea1a	3610	/**
NYX	0:85b3fd62ea1a	3611	* @brief Disable update DMA request (UDE).
NYX	0:85b3fd62ea1a	3612	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
NYX	0:85b3fd62ea1a	3613	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3614	* @retval None
NYX	0:85b3fd62ea1a	3615	*/
NYX	0:85b3fd62ea1a	3616	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3617	{
NYX	0:85b3fd62ea1a	3618	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
NYX	0:85b3fd62ea1a	3619	}
NYX	0:85b3fd62ea1a	3620
NYX	0:85b3fd62ea1a	3621	/**
NYX	0:85b3fd62ea1a	3622	* @brief Indicates whether the update DMA request (UDE) is enabled.
NYX	0:85b3fd62ea1a	3623	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
NYX	0:85b3fd62ea1a	3624	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3625	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3626	*/
NYX	0:85b3fd62ea1a	3627	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3628	{
NYX	0:85b3fd62ea1a	3629	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
NYX	0:85b3fd62ea1a	3630	}
NYX	0:85b3fd62ea1a	3631
NYX	0:85b3fd62ea1a	3632	/**
NYX	0:85b3fd62ea1a	3633	* @brief Enable capture/compare 1 DMA request (CC1DE).
NYX	0:85b3fd62ea1a	3634	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
NYX	0:85b3fd62ea1a	3635	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3636	* @retval None
NYX	0:85b3fd62ea1a	3637	*/
NYX	0:85b3fd62ea1a	3638	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3639	{
NYX	0:85b3fd62ea1a	3640	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
NYX	0:85b3fd62ea1a	3641	}
NYX	0:85b3fd62ea1a	3642
NYX	0:85b3fd62ea1a	3643	/**
NYX	0:85b3fd62ea1a	3644	* @brief Disable capture/compare 1 DMA request (CC1DE).
NYX	0:85b3fd62ea1a	3645	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
NYX	0:85b3fd62ea1a	3646	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3647	* @retval None
NYX	0:85b3fd62ea1a	3648	*/
NYX	0:85b3fd62ea1a	3649	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3650	{
NYX	0:85b3fd62ea1a	3651	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
NYX	0:85b3fd62ea1a	3652	}
NYX	0:85b3fd62ea1a	3653
NYX	0:85b3fd62ea1a	3654	/**
NYX	0:85b3fd62ea1a	3655	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
NYX	0:85b3fd62ea1a	3656	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
NYX	0:85b3fd62ea1a	3657	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3658	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3659	*/
NYX	0:85b3fd62ea1a	3660	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3661	{
NYX	0:85b3fd62ea1a	3662	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
NYX	0:85b3fd62ea1a	3663	}
NYX	0:85b3fd62ea1a	3664
NYX	0:85b3fd62ea1a	3665	/**
NYX	0:85b3fd62ea1a	3666	* @brief Enable capture/compare 2 DMA request (CC2DE).
NYX	0:85b3fd62ea1a	3667	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
NYX	0:85b3fd62ea1a	3668	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3669	* @retval None
NYX	0:85b3fd62ea1a	3670	*/
NYX	0:85b3fd62ea1a	3671	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3672	{
NYX	0:85b3fd62ea1a	3673	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
NYX	0:85b3fd62ea1a	3674	}
NYX	0:85b3fd62ea1a	3675
NYX	0:85b3fd62ea1a	3676	/**
NYX	0:85b3fd62ea1a	3677	* @brief Disable capture/compare 2 DMA request (CC2DE).
NYX	0:85b3fd62ea1a	3678	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
NYX	0:85b3fd62ea1a	3679	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3680	* @retval None
NYX	0:85b3fd62ea1a	3681	*/
NYX	0:85b3fd62ea1a	3682	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3683	{
NYX	0:85b3fd62ea1a	3684	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
NYX	0:85b3fd62ea1a	3685	}
NYX	0:85b3fd62ea1a	3686
NYX	0:85b3fd62ea1a	3687	/**
NYX	0:85b3fd62ea1a	3688	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
NYX	0:85b3fd62ea1a	3689	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
NYX	0:85b3fd62ea1a	3690	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3691	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3692	*/
NYX	0:85b3fd62ea1a	3693	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3694	{
NYX	0:85b3fd62ea1a	3695	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
NYX	0:85b3fd62ea1a	3696	}
NYX	0:85b3fd62ea1a	3697
NYX	0:85b3fd62ea1a	3698	/**
NYX	0:85b3fd62ea1a	3699	* @brief Enable capture/compare 3 DMA request (CC3DE).
NYX	0:85b3fd62ea1a	3700	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
NYX	0:85b3fd62ea1a	3701	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3702	* @retval None
NYX	0:85b3fd62ea1a	3703	*/
NYX	0:85b3fd62ea1a	3704	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3705	{
NYX	0:85b3fd62ea1a	3706	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
NYX	0:85b3fd62ea1a	3707	}
NYX	0:85b3fd62ea1a	3708
NYX	0:85b3fd62ea1a	3709	/**
NYX	0:85b3fd62ea1a	3710	* @brief Disable capture/compare 3 DMA request (CC3DE).
NYX	0:85b3fd62ea1a	3711	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
NYX	0:85b3fd62ea1a	3712	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3713	* @retval None
NYX	0:85b3fd62ea1a	3714	*/
NYX	0:85b3fd62ea1a	3715	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3716	{
NYX	0:85b3fd62ea1a	3717	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
NYX	0:85b3fd62ea1a	3718	}
NYX	0:85b3fd62ea1a	3719
NYX	0:85b3fd62ea1a	3720	/**
NYX	0:85b3fd62ea1a	3721	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
NYX	0:85b3fd62ea1a	3722	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
NYX	0:85b3fd62ea1a	3723	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3724	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3725	*/
NYX	0:85b3fd62ea1a	3726	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3727	{
NYX	0:85b3fd62ea1a	3728	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
NYX	0:85b3fd62ea1a	3729	}
NYX	0:85b3fd62ea1a	3730
NYX	0:85b3fd62ea1a	3731	/**
NYX	0:85b3fd62ea1a	3732	* @brief Enable capture/compare 4 DMA request (CC4DE).
NYX	0:85b3fd62ea1a	3733	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
NYX	0:85b3fd62ea1a	3734	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3735	* @retval None
NYX	0:85b3fd62ea1a	3736	*/
NYX	0:85b3fd62ea1a	3737	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3738	{
NYX	0:85b3fd62ea1a	3739	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
NYX	0:85b3fd62ea1a	3740	}
NYX	0:85b3fd62ea1a	3741
NYX	0:85b3fd62ea1a	3742	/**
NYX	0:85b3fd62ea1a	3743	* @brief Disable capture/compare 4 DMA request (CC4DE).
NYX	0:85b3fd62ea1a	3744	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
NYX	0:85b3fd62ea1a	3745	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3746	* @retval None
NYX	0:85b3fd62ea1a	3747	*/
NYX	0:85b3fd62ea1a	3748	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3749	{
NYX	0:85b3fd62ea1a	3750	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
NYX	0:85b3fd62ea1a	3751	}
NYX	0:85b3fd62ea1a	3752
NYX	0:85b3fd62ea1a	3753	/**
NYX	0:85b3fd62ea1a	3754	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
NYX	0:85b3fd62ea1a	3755	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
NYX	0:85b3fd62ea1a	3756	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3757	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3758	*/
NYX	0:85b3fd62ea1a	3759	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3760	{
NYX	0:85b3fd62ea1a	3761	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
NYX	0:85b3fd62ea1a	3762	}
NYX	0:85b3fd62ea1a	3763
NYX	0:85b3fd62ea1a	3764	/**
NYX	0:85b3fd62ea1a	3765	* @brief Enable commutation DMA request (COMDE).
NYX	0:85b3fd62ea1a	3766	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
NYX	0:85b3fd62ea1a	3767	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3768	* @retval None
NYX	0:85b3fd62ea1a	3769	*/
NYX	0:85b3fd62ea1a	3770	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3771	{
NYX	0:85b3fd62ea1a	3772	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
NYX	0:85b3fd62ea1a	3773	}
NYX	0:85b3fd62ea1a	3774
NYX	0:85b3fd62ea1a	3775	/**
NYX	0:85b3fd62ea1a	3776	* @brief Disable commutation DMA request (COMDE).
NYX	0:85b3fd62ea1a	3777	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
NYX	0:85b3fd62ea1a	3778	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3779	* @retval None
NYX	0:85b3fd62ea1a	3780	*/
NYX	0:85b3fd62ea1a	3781	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3782	{
NYX	0:85b3fd62ea1a	3783	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
NYX	0:85b3fd62ea1a	3784	}
NYX	0:85b3fd62ea1a	3785
NYX	0:85b3fd62ea1a	3786	/**
NYX	0:85b3fd62ea1a	3787	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
NYX	0:85b3fd62ea1a	3788	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
NYX	0:85b3fd62ea1a	3789	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3790	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3791	*/
NYX	0:85b3fd62ea1a	3792	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3793	{
NYX	0:85b3fd62ea1a	3794	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
NYX	0:85b3fd62ea1a	3795	}
NYX	0:85b3fd62ea1a	3796
NYX	0:85b3fd62ea1a	3797	/**
NYX	0:85b3fd62ea1a	3798	* @brief Enable trigger interrupt (TDE).
NYX	0:85b3fd62ea1a	3799	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
NYX	0:85b3fd62ea1a	3800	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3801	* @retval None
NYX	0:85b3fd62ea1a	3802	*/
NYX	0:85b3fd62ea1a	3803	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3804	{
NYX	0:85b3fd62ea1a	3805	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
NYX	0:85b3fd62ea1a	3806	}
NYX	0:85b3fd62ea1a	3807
NYX	0:85b3fd62ea1a	3808	/**
NYX	0:85b3fd62ea1a	3809	* @brief Disable trigger interrupt (TDE).
NYX	0:85b3fd62ea1a	3810	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
NYX	0:85b3fd62ea1a	3811	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3812	* @retval None
NYX	0:85b3fd62ea1a	3813	*/
NYX	0:85b3fd62ea1a	3814	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3815	{
NYX	0:85b3fd62ea1a	3816	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
NYX	0:85b3fd62ea1a	3817	}
NYX	0:85b3fd62ea1a	3818
NYX	0:85b3fd62ea1a	3819	/**
NYX	0:85b3fd62ea1a	3820	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
NYX	0:85b3fd62ea1a	3821	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
NYX	0:85b3fd62ea1a	3822	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3823	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3824	*/
NYX	0:85b3fd62ea1a	3825	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3826	{
NYX	0:85b3fd62ea1a	3827	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
NYX	0:85b3fd62ea1a	3828	}
NYX	0:85b3fd62ea1a	3829
NYX	0:85b3fd62ea1a	3830	/**
NYX	0:85b3fd62ea1a	3831	* @}
NYX	0:85b3fd62ea1a	3832	*/
NYX	0:85b3fd62ea1a	3833
NYX	0:85b3fd62ea1a	3834	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
NYX	0:85b3fd62ea1a	3835	* @{
NYX	0:85b3fd62ea1a	3836	*/
NYX	0:85b3fd62ea1a	3837	/**
NYX	0:85b3fd62ea1a	3838	* @brief Generate an update event.
NYX	0:85b3fd62ea1a	3839	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
NYX	0:85b3fd62ea1a	3840	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3841	* @retval None
NYX	0:85b3fd62ea1a	3842	*/
NYX	0:85b3fd62ea1a	3843	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3844	{
NYX	0:85b3fd62ea1a	3845	SET_BIT(TIMx->EGR, TIM_EGR_UG);
NYX	0:85b3fd62ea1a	3846	}
NYX	0:85b3fd62ea1a	3847
NYX	0:85b3fd62ea1a	3848	/**
NYX	0:85b3fd62ea1a	3849	* @brief Generate Capture/Compare 1 event.
NYX	0:85b3fd62ea1a	3850	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
NYX	0:85b3fd62ea1a	3851	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3852	* @retval None
NYX	0:85b3fd62ea1a	3853	*/
NYX	0:85b3fd62ea1a	3854	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3855	{
NYX	0:85b3fd62ea1a	3856	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
NYX	0:85b3fd62ea1a	3857	}
NYX	0:85b3fd62ea1a	3858
NYX	0:85b3fd62ea1a	3859	/**
NYX	0:85b3fd62ea1a	3860	* @brief Generate Capture/Compare 2 event.
NYX	0:85b3fd62ea1a	3861	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
NYX	0:85b3fd62ea1a	3862	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3863	* @retval None
NYX	0:85b3fd62ea1a	3864	*/
NYX	0:85b3fd62ea1a	3865	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3866	{
NYX	0:85b3fd62ea1a	3867	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
NYX	0:85b3fd62ea1a	3868	}
NYX	0:85b3fd62ea1a	3869
NYX	0:85b3fd62ea1a	3870	/**
NYX	0:85b3fd62ea1a	3871	* @brief Generate Capture/Compare 3 event.
NYX	0:85b3fd62ea1a	3872	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
NYX	0:85b3fd62ea1a	3873	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3874	* @retval None
NYX	0:85b3fd62ea1a	3875	*/
NYX	0:85b3fd62ea1a	3876	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3877	{
NYX	0:85b3fd62ea1a	3878	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
NYX	0:85b3fd62ea1a	3879	}
NYX	0:85b3fd62ea1a	3880
NYX	0:85b3fd62ea1a	3881	/**
NYX	0:85b3fd62ea1a	3882	* @brief Generate Capture/Compare 4 event.
NYX	0:85b3fd62ea1a	3883	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
NYX	0:85b3fd62ea1a	3884	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3885	* @retval None
NYX	0:85b3fd62ea1a	3886	*/
NYX	0:85b3fd62ea1a	3887	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3888	{
NYX	0:85b3fd62ea1a	3889	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
NYX	0:85b3fd62ea1a	3890	}
NYX	0:85b3fd62ea1a	3891
NYX	0:85b3fd62ea1a	3892	/**
NYX	0:85b3fd62ea1a	3893	* @brief Generate commutation event.
NYX	0:85b3fd62ea1a	3894	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
NYX	0:85b3fd62ea1a	3895	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3896	* @retval None
NYX	0:85b3fd62ea1a	3897	*/
NYX	0:85b3fd62ea1a	3898	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3899	{
NYX	0:85b3fd62ea1a	3900	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
NYX	0:85b3fd62ea1a	3901	}
NYX	0:85b3fd62ea1a	3902
NYX	0:85b3fd62ea1a	3903	/**
NYX	0:85b3fd62ea1a	3904	* @brief Generate trigger event.
NYX	0:85b3fd62ea1a	3905	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
NYX	0:85b3fd62ea1a	3906	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3907	* @retval None
NYX	0:85b3fd62ea1a	3908	*/
NYX	0:85b3fd62ea1a	3909	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3910	{
NYX	0:85b3fd62ea1a	3911	SET_BIT(TIMx->EGR, TIM_EGR_TG);
NYX	0:85b3fd62ea1a	3912	}
NYX	0:85b3fd62ea1a	3913
NYX	0:85b3fd62ea1a	3914	/**
NYX	0:85b3fd62ea1a	3915	* @brief Generate break event.
NYX	0:85b3fd62ea1a	3916	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
NYX	0:85b3fd62ea1a	3917	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	3918	* @retval None
NYX	0:85b3fd62ea1a	3919	*/
NYX	0:85b3fd62ea1a	3920	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	3921	{
NYX	0:85b3fd62ea1a	3922	SET_BIT(TIMx->EGR, TIM_EGR_BG);
NYX	0:85b3fd62ea1a	3923	}
NYX	0:85b3fd62ea1a	3924
NYX	0:85b3fd62ea1a	3925	/**
NYX	0:85b3fd62ea1a	3926	* @}
NYX	0:85b3fd62ea1a	3927	*/
NYX	0:85b3fd62ea1a	3928
NYX	0:85b3fd62ea1a	3929	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	3930	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
NYX	0:85b3fd62ea1a	3931	* @{
NYX	0:85b3fd62ea1a	3932	*/
NYX	0:85b3fd62ea1a	3933
NYX	0:85b3fd62ea1a	3934	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
NYX	0:85b3fd62ea1a	3935	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
NYX	0:85b3fd62ea1a	3936	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
NYX	0:85b3fd62ea1a	3937	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
NYX	0:85b3fd62ea1a	3938	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
NYX	0:85b3fd62ea1a	3939	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
NYX	0:85b3fd62ea1a	3940	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
NYX	0:85b3fd62ea1a	3941	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
NYX	0:85b3fd62ea1a	3942	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
NYX	0:85b3fd62ea1a	3943	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
NYX	0:85b3fd62ea1a	3944	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
NYX	0:85b3fd62ea1a	3945	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
NYX	0:85b3fd62ea1a	3946	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
NYX	0:85b3fd62ea1a	3947	/**
NYX	0:85b3fd62ea1a	3948	* @}
NYX	0:85b3fd62ea1a	3949	*/
NYX	0:85b3fd62ea1a	3950	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	3951
NYX	0:85b3fd62ea1a	3952	/**
NYX	0:85b3fd62ea1a	3953	* @}
NYX	0:85b3fd62ea1a	3954	*/
NYX	0:85b3fd62ea1a	3955
NYX	0:85b3fd62ea1a	3956	/**
NYX	0:85b3fd62ea1a	3957	* @}
NYX	0:85b3fd62ea1a	3958	*/
NYX	0:85b3fd62ea1a	3959
NYX	0:85b3fd62ea1a	3960	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 */
NYX	0:85b3fd62ea1a	3961
NYX	0:85b3fd62ea1a	3962	/**
NYX	0:85b3fd62ea1a	3963	* @}
NYX	0:85b3fd62ea1a	3964	*/
NYX	0:85b3fd62ea1a	3965
NYX	0:85b3fd62ea1a	3966	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	3967	}
NYX	0:85b3fd62ea1a	3968	#endif
NYX	0:85b3fd62ea1a	3969
NYX	0:85b3fd62ea1a	3970	#endif /* __STM32F4xx_LL_TIM_H */
NYX	0:85b3fd62ea1a	3971	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
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Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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