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inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_ll_tim.c
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief TIM LL module driver.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	38
NYX	0:85b3fd62ea1a	39	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	40	#include "stm32f4xx_ll_tim.h"
NYX	0:85b3fd62ea1a	41	#include "stm32f4xx_ll_bus.h"
NYX	0:85b3fd62ea1a	42
NYX	0:85b3fd62ea1a	43	#ifdef USE_FULL_ASSERT
NYX	0:85b3fd62ea1a	44	#include "stm32_assert.h"
NYX	0:85b3fd62ea1a	45	#else
NYX	0:85b3fd62ea1a	46	#define assert_param(expr) ((void)0U)
NYX	0:85b3fd62ea1a	47	#endif
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_LL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14)
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/** @addtogroup TIM_LL
NYX	0:85b3fd62ea1a	56	* @{
NYX	0:85b3fd62ea1a	57	*/
NYX	0:85b3fd62ea1a	58
NYX	0:85b3fd62ea1a	59	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	60	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	61	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	62	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	63	/** @addtogroup TIM_LL_Private_Macros
NYX	0:85b3fd62ea1a	64	* @{
NYX	0:85b3fd62ea1a	65	*/
NYX	0:85b3fd62ea1a	66	#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
NYX	0:85b3fd62ea1a	67	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
NYX	0:85b3fd62ea1a	68	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
NYX	0:85b3fd62ea1a	69	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
NYX	0:85b3fd62ea1a	70	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
NYX	0:85b3fd62ea1a	71
NYX	0:85b3fd62ea1a	72	#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
NYX	0:85b3fd62ea1a	73	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
NYX	0:85b3fd62ea1a	74	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
NYX	0:85b3fd62ea1a	75
NYX	0:85b3fd62ea1a	76	#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
NYX	0:85b3fd62ea1a	77	\|\| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
NYX	0:85b3fd62ea1a	78	\|\| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
NYX	0:85b3fd62ea1a	79	\|\| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
NYX	0:85b3fd62ea1a	80	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
NYX	0:85b3fd62ea1a	81	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
NYX	0:85b3fd62ea1a	82	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
NYX	0:85b3fd62ea1a	83	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM2))
NYX	0:85b3fd62ea1a	84
NYX	0:85b3fd62ea1a	85	#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
NYX	0:85b3fd62ea1a	86	\|\| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
NYX	0:85b3fd62ea1a	87
NYX	0:85b3fd62ea1a	88	#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
NYX	0:85b3fd62ea1a	89	\|\| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
NYX	0:85b3fd62ea1a	90
NYX	0:85b3fd62ea1a	91	#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
NYX	0:85b3fd62ea1a	92	\|\| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
NYX	0:85b3fd62ea1a	93
NYX	0:85b3fd62ea1a	94	#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
NYX	0:85b3fd62ea1a	95	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
NYX	0:85b3fd62ea1a	96	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
NYX	0:85b3fd62ea1a	97
NYX	0:85b3fd62ea1a	98	#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
NYX	0:85b3fd62ea1a	99	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
NYX	0:85b3fd62ea1a	100	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
NYX	0:85b3fd62ea1a	101	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
NYX	0:85b3fd62ea1a	102
NYX	0:85b3fd62ea1a	103	#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
NYX	0:85b3fd62ea1a	104	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
NYX	0:85b3fd62ea1a	105	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
NYX	0:85b3fd62ea1a	106	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
NYX	0:85b3fd62ea1a	107	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
NYX	0:85b3fd62ea1a	108	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
NYX	0:85b3fd62ea1a	109	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
NYX	0:85b3fd62ea1a	110	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
NYX	0:85b3fd62ea1a	111	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
NYX	0:85b3fd62ea1a	112	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
NYX	0:85b3fd62ea1a	113	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
NYX	0:85b3fd62ea1a	114	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
NYX	0:85b3fd62ea1a	115	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
NYX	0:85b3fd62ea1a	116	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
NYX	0:85b3fd62ea1a	117	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
NYX	0:85b3fd62ea1a	118	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
NYX	0:85b3fd62ea1a	119
NYX	0:85b3fd62ea1a	120	#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
NYX	0:85b3fd62ea1a	121	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
NYX	0:85b3fd62ea1a	122	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
NYX	0:85b3fd62ea1a	123
NYX	0:85b3fd62ea1a	124	#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
NYX	0:85b3fd62ea1a	125	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
NYX	0:85b3fd62ea1a	126	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
NYX	0:85b3fd62ea1a	127
NYX	0:85b3fd62ea1a	128	#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
NYX	0:85b3fd62ea1a	129	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
NYX	0:85b3fd62ea1a	130
NYX	0:85b3fd62ea1a	131	#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
NYX	0:85b3fd62ea1a	132	\|\| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
NYX	0:85b3fd62ea1a	133
NYX	0:85b3fd62ea1a	134	#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
NYX	0:85b3fd62ea1a	135	\|\| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
NYX	0:85b3fd62ea1a	136
NYX	0:85b3fd62ea1a	137	#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
NYX	0:85b3fd62ea1a	138	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
NYX	0:85b3fd62ea1a	139	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
NYX	0:85b3fd62ea1a	140	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
NYX	0:85b3fd62ea1a	141
NYX	0:85b3fd62ea1a	142	#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
NYX	0:85b3fd62ea1a	143	\|\| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
NYX	0:85b3fd62ea1a	144
NYX	0:85b3fd62ea1a	145	#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
NYX	0:85b3fd62ea1a	146	\|\| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
NYX	0:85b3fd62ea1a	147
NYX	0:85b3fd62ea1a	148	#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
NYX	0:85b3fd62ea1a	149	\|\| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
NYX	0:85b3fd62ea1a	150	/**
NYX	0:85b3fd62ea1a	151	* @}
NYX	0:85b3fd62ea1a	152	*/
NYX	0:85b3fd62ea1a	153
NYX	0:85b3fd62ea1a	154
NYX	0:85b3fd62ea1a	155	/* Private function prototypes -----------------------------------------------*/
NYX	0:85b3fd62ea1a	156	/** @defgroup TIM_LL_Private_Functions TIM Private Functions
NYX	0:85b3fd62ea1a	157	* @{
NYX	0:85b3fd62ea1a	158	*/
NYX	0:85b3fd62ea1a	159	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
NYX	0:85b3fd62ea1a	160	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
NYX	0:85b3fd62ea1a	161	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
NYX	0:85b3fd62ea1a	162	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
NYX	0:85b3fd62ea1a	163	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
NYX	0:85b3fd62ea1a	164	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
NYX	0:85b3fd62ea1a	165	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
NYX	0:85b3fd62ea1a	166	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
NYX	0:85b3fd62ea1a	167	/**
NYX	0:85b3fd62ea1a	168	* @}
NYX	0:85b3fd62ea1a	169	*/
NYX	0:85b3fd62ea1a	170
NYX	0:85b3fd62ea1a	171	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	172	/** @addtogroup TIM_LL_Exported_Functions
NYX	0:85b3fd62ea1a	173	* @{
NYX	0:85b3fd62ea1a	174	*/
NYX	0:85b3fd62ea1a	175
NYX	0:85b3fd62ea1a	176	/** @addtogroup TIM_LL_EF_Init
NYX	0:85b3fd62ea1a	177	* @{
NYX	0:85b3fd62ea1a	178	*/
NYX	0:85b3fd62ea1a	179
NYX	0:85b3fd62ea1a	180	/**
NYX	0:85b3fd62ea1a	181	* @brief Set TIMx registers to their reset values.
NYX	0:85b3fd62ea1a	182	* @param TIMx Timer instance
NYX	0:85b3fd62ea1a	183	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	184	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	185	* - ERROR: invalid TIMx instance
NYX	0:85b3fd62ea1a	186	*/
NYX	0:85b3fd62ea1a	187	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
NYX	0:85b3fd62ea1a	188	{
NYX	0:85b3fd62ea1a	189	ErrorStatus result = SUCCESS;
NYX	0:85b3fd62ea1a	190
NYX	0:85b3fd62ea1a	191	/* Check the parameters */
NYX	0:85b3fd62ea1a	192	assert_param(IS_TIM_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	193
NYX	0:85b3fd62ea1a	194	if (TIMx == TIM1)
NYX	0:85b3fd62ea1a	195	{
NYX	0:85b3fd62ea1a	196	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
NYX	0:85b3fd62ea1a	197	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
NYX	0:85b3fd62ea1a	198	}
NYX	0:85b3fd62ea1a	199	#if defined(TIM2)
NYX	0:85b3fd62ea1a	200	else if (TIMx == TIM2)
NYX	0:85b3fd62ea1a	201	{
NYX	0:85b3fd62ea1a	202	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
NYX	0:85b3fd62ea1a	203	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
NYX	0:85b3fd62ea1a	204	}
NYX	0:85b3fd62ea1a	205	#endif
NYX	0:85b3fd62ea1a	206	#if defined(TIM3)
NYX	0:85b3fd62ea1a	207	else if (TIMx == TIM3)
NYX	0:85b3fd62ea1a	208	{
NYX	0:85b3fd62ea1a	209	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
NYX	0:85b3fd62ea1a	210	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
NYX	0:85b3fd62ea1a	211	}
NYX	0:85b3fd62ea1a	212	#endif
NYX	0:85b3fd62ea1a	213	#if defined(TIM4)
NYX	0:85b3fd62ea1a	214	else if (TIMx == TIM4)
NYX	0:85b3fd62ea1a	215	{
NYX	0:85b3fd62ea1a	216	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
NYX	0:85b3fd62ea1a	217	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
NYX	0:85b3fd62ea1a	218	}
NYX	0:85b3fd62ea1a	219	#endif
NYX	0:85b3fd62ea1a	220	#if defined(TIM5)
NYX	0:85b3fd62ea1a	221	else if (TIMx == TIM5)
NYX	0:85b3fd62ea1a	222	{
NYX	0:85b3fd62ea1a	223	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
NYX	0:85b3fd62ea1a	224	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
NYX	0:85b3fd62ea1a	225	}
NYX	0:85b3fd62ea1a	226	#endif
NYX	0:85b3fd62ea1a	227	#if defined(TIM6)
NYX	0:85b3fd62ea1a	228	else if (TIMx == TIM6)
NYX	0:85b3fd62ea1a	229	{
NYX	0:85b3fd62ea1a	230	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
NYX	0:85b3fd62ea1a	231	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
NYX	0:85b3fd62ea1a	232	}
NYX	0:85b3fd62ea1a	233	#endif
NYX	0:85b3fd62ea1a	234	#if defined (TIM7)
NYX	0:85b3fd62ea1a	235	else if (TIMx == TIM7)
NYX	0:85b3fd62ea1a	236	{
NYX	0:85b3fd62ea1a	237	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
NYX	0:85b3fd62ea1a	238	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
NYX	0:85b3fd62ea1a	239	}
NYX	0:85b3fd62ea1a	240	#endif
NYX	0:85b3fd62ea1a	241	#if defined(TIM8)
NYX	0:85b3fd62ea1a	242	else if (TIMx == TIM8)
NYX	0:85b3fd62ea1a	243	{
NYX	0:85b3fd62ea1a	244	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
NYX	0:85b3fd62ea1a	245	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
NYX	0:85b3fd62ea1a	246	}
NYX	0:85b3fd62ea1a	247	#endif
NYX	0:85b3fd62ea1a	248	#if defined(TIM9)
NYX	0:85b3fd62ea1a	249	else if (TIMx == TIM9)
NYX	0:85b3fd62ea1a	250	{
NYX	0:85b3fd62ea1a	251	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
NYX	0:85b3fd62ea1a	252	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
NYX	0:85b3fd62ea1a	253	}
NYX	0:85b3fd62ea1a	254	#endif
NYX	0:85b3fd62ea1a	255	#if defined(TIM10)
NYX	0:85b3fd62ea1a	256	else if (TIMx == TIM10)
NYX	0:85b3fd62ea1a	257	{
NYX	0:85b3fd62ea1a	258	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
NYX	0:85b3fd62ea1a	259	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
NYX	0:85b3fd62ea1a	260	}
NYX	0:85b3fd62ea1a	261	#endif
NYX	0:85b3fd62ea1a	262	#if defined(TIM11)
NYX	0:85b3fd62ea1a	263	else if (TIMx == TIM11)
NYX	0:85b3fd62ea1a	264	{
NYX	0:85b3fd62ea1a	265	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
NYX	0:85b3fd62ea1a	266	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
NYX	0:85b3fd62ea1a	267	}
NYX	0:85b3fd62ea1a	268	#endif
NYX	0:85b3fd62ea1a	269	#if defined(TIM12)
NYX	0:85b3fd62ea1a	270	else if (TIMx == TIM12)
NYX	0:85b3fd62ea1a	271	{
NYX	0:85b3fd62ea1a	272	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
NYX	0:85b3fd62ea1a	273	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
NYX	0:85b3fd62ea1a	274	}
NYX	0:85b3fd62ea1a	275	#endif
NYX	0:85b3fd62ea1a	276	#if defined(TIM13)
NYX	0:85b3fd62ea1a	277	else if (TIMx == TIM13)
NYX	0:85b3fd62ea1a	278	{
NYX	0:85b3fd62ea1a	279	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
NYX	0:85b3fd62ea1a	280	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
NYX	0:85b3fd62ea1a	281	}
NYX	0:85b3fd62ea1a	282	#endif
NYX	0:85b3fd62ea1a	283	#if defined(TIM14)
NYX	0:85b3fd62ea1a	284	else if (TIMx == TIM14)
NYX	0:85b3fd62ea1a	285	{
NYX	0:85b3fd62ea1a	286	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
NYX	0:85b3fd62ea1a	287	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
NYX	0:85b3fd62ea1a	288	}
NYX	0:85b3fd62ea1a	289	#endif
NYX	0:85b3fd62ea1a	290	else
NYX	0:85b3fd62ea1a	291	{
NYX	0:85b3fd62ea1a	292	result = ERROR;
NYX	0:85b3fd62ea1a	293	}
NYX	0:85b3fd62ea1a	294
NYX	0:85b3fd62ea1a	295	return result;
NYX	0:85b3fd62ea1a	296	}
NYX	0:85b3fd62ea1a	297
NYX	0:85b3fd62ea1a	298	/**
NYX	0:85b3fd62ea1a	299	* @brief Set the fields of the time base unit configuration data structure
NYX	0:85b3fd62ea1a	300	* to their default values.
NYX	0:85b3fd62ea1a	301	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
NYX	0:85b3fd62ea1a	302	* @retval None
NYX	0:85b3fd62ea1a	303	*/
NYX	0:85b3fd62ea1a	304	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
NYX	0:85b3fd62ea1a	305	{
NYX	0:85b3fd62ea1a	306	/* Set the default configuration */
NYX	0:85b3fd62ea1a	307	TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
NYX	0:85b3fd62ea1a	308	TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
NYX	0:85b3fd62ea1a	309	TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
NYX	0:85b3fd62ea1a	310	TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
NYX	0:85b3fd62ea1a	311	TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
NYX	0:85b3fd62ea1a	312	}
NYX	0:85b3fd62ea1a	313
NYX	0:85b3fd62ea1a	314	/**
NYX	0:85b3fd62ea1a	315	* @brief Configure the TIMx time base unit.
NYX	0:85b3fd62ea1a	316	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	317	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
NYX	0:85b3fd62ea1a	318	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	319	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	320	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	321	*/
NYX	0:85b3fd62ea1a	322	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct)
NYX	0:85b3fd62ea1a	323	{
NYX	0:85b3fd62ea1a	324	uint32_t tmpcr1 = 0U;
NYX	0:85b3fd62ea1a	325
NYX	0:85b3fd62ea1a	326	/* Check the parameters */
NYX	0:85b3fd62ea1a	327	assert_param(IS_TIM_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	328	assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
NYX	0:85b3fd62ea1a	329	assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
NYX	0:85b3fd62ea1a	330
NYX	0:85b3fd62ea1a	331	tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
NYX	0:85b3fd62ea1a	332
NYX	0:85b3fd62ea1a	333	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
NYX	0:85b3fd62ea1a	334	{
NYX	0:85b3fd62ea1a	335	/* Select the Counter Mode */
NYX	0:85b3fd62ea1a	336	MODIFY_REG(tmpcr1, (TIM_CR1_DIR \| TIM_CR1_CMS), TIM_InitStruct->CounterMode);
NYX	0:85b3fd62ea1a	337	}
NYX	0:85b3fd62ea1a	338
NYX	0:85b3fd62ea1a	339	if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
NYX	0:85b3fd62ea1a	340	{
NYX	0:85b3fd62ea1a	341	/* Set the clock division */
NYX	0:85b3fd62ea1a	342	MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
NYX	0:85b3fd62ea1a	343	}
NYX	0:85b3fd62ea1a	344
NYX	0:85b3fd62ea1a	345	/* Write to TIMx CR1 */
NYX	0:85b3fd62ea1a	346	LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
NYX	0:85b3fd62ea1a	347
NYX	0:85b3fd62ea1a	348	/* Set the Autoreload value */
NYX	0:85b3fd62ea1a	349	LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
NYX	0:85b3fd62ea1a	350
NYX	0:85b3fd62ea1a	351	/* Set the Prescaler value */
NYX	0:85b3fd62ea1a	352	LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
NYX	0:85b3fd62ea1a	353
NYX	0:85b3fd62ea1a	354	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
NYX	0:85b3fd62ea1a	355	{
NYX	0:85b3fd62ea1a	356	/* Set the Repetition Counter value */
NYX	0:85b3fd62ea1a	357	LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
NYX	0:85b3fd62ea1a	358	}
NYX	0:85b3fd62ea1a	359
NYX	0:85b3fd62ea1a	360	/* Generate an update event to reload the Prescaler
NYX	0:85b3fd62ea1a	361	and the repetition counter value (if applicable) immediately */
NYX	0:85b3fd62ea1a	362	LL_TIM_GenerateEvent_UPDATE(TIMx);
NYX	0:85b3fd62ea1a	363
NYX	0:85b3fd62ea1a	364	return SUCCESS;
NYX	0:85b3fd62ea1a	365	}
NYX	0:85b3fd62ea1a	366
NYX	0:85b3fd62ea1a	367	/**
NYX	0:85b3fd62ea1a	368	* @brief Set the fields of the TIMx output channel configuration data
NYX	0:85b3fd62ea1a	369	* structure to their default values.
NYX	0:85b3fd62ea1a	370	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
NYX	0:85b3fd62ea1a	371	* @retval None
NYX	0:85b3fd62ea1a	372	*/
NYX	0:85b3fd62ea1a	373	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
NYX	0:85b3fd62ea1a	374	{
NYX	0:85b3fd62ea1a	375	/* Set the default configuration */
NYX	0:85b3fd62ea1a	376	TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
NYX	0:85b3fd62ea1a	377	TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
NYX	0:85b3fd62ea1a	378	TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
NYX	0:85b3fd62ea1a	379	TIM_OC_InitStruct->CompareValue = 0x00000000U;
NYX	0:85b3fd62ea1a	380	TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
NYX	0:85b3fd62ea1a	381	TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
NYX	0:85b3fd62ea1a	382	TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
NYX	0:85b3fd62ea1a	383	TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
NYX	0:85b3fd62ea1a	384	}
NYX	0:85b3fd62ea1a	385
NYX	0:85b3fd62ea1a	386	/**
NYX	0:85b3fd62ea1a	387	* @brief Configure the TIMx output channel.
NYX	0:85b3fd62ea1a	388	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	389	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	390	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	391	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	392	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	393	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	394	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
NYX	0:85b3fd62ea1a	395	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	396	* - SUCCESS: TIMx output channel is initialized
NYX	0:85b3fd62ea1a	397	* - ERROR: TIMx output channel is not initialized
NYX	0:85b3fd62ea1a	398	*/
NYX	0:85b3fd62ea1a	399	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct)
NYX	0:85b3fd62ea1a	400	{
NYX	0:85b3fd62ea1a	401	ErrorStatus result = ERROR;
NYX	0:85b3fd62ea1a	402
NYX	0:85b3fd62ea1a	403	switch (Channel)
NYX	0:85b3fd62ea1a	404	{
NYX	0:85b3fd62ea1a	405	case LL_TIM_CHANNEL_CH1:
NYX	0:85b3fd62ea1a	406	result = OC1Config(TIMx, TIM_OC_InitStruct);
NYX	0:85b3fd62ea1a	407	break;
NYX	0:85b3fd62ea1a	408	case LL_TIM_CHANNEL_CH2:
NYX	0:85b3fd62ea1a	409	result = OC2Config(TIMx, TIM_OC_InitStruct);
NYX	0:85b3fd62ea1a	410	break;
NYX	0:85b3fd62ea1a	411	case LL_TIM_CHANNEL_CH3:
NYX	0:85b3fd62ea1a	412	result = OC3Config(TIMx, TIM_OC_InitStruct);
NYX	0:85b3fd62ea1a	413	break;
NYX	0:85b3fd62ea1a	414	case LL_TIM_CHANNEL_CH4:
NYX	0:85b3fd62ea1a	415	result = OC4Config(TIMx, TIM_OC_InitStruct);
NYX	0:85b3fd62ea1a	416	break;
NYX	0:85b3fd62ea1a	417	default:
NYX	0:85b3fd62ea1a	418	break;
NYX	0:85b3fd62ea1a	419	}
NYX	0:85b3fd62ea1a	420
NYX	0:85b3fd62ea1a	421	return result;
NYX	0:85b3fd62ea1a	422	}
NYX	0:85b3fd62ea1a	423
NYX	0:85b3fd62ea1a	424	/**
NYX	0:85b3fd62ea1a	425	* @brief Set the fields of the TIMx input channel configuration data
NYX	0:85b3fd62ea1a	426	* structure to their default values.
NYX	0:85b3fd62ea1a	427	* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
NYX	0:85b3fd62ea1a	428	* @retval None
NYX	0:85b3fd62ea1a	429	*/
NYX	0:85b3fd62ea1a	430	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
NYX	0:85b3fd62ea1a	431	{
NYX	0:85b3fd62ea1a	432	/* Set the default configuration */
NYX	0:85b3fd62ea1a	433	TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
NYX	0:85b3fd62ea1a	434	TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
NYX	0:85b3fd62ea1a	435	TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
NYX	0:85b3fd62ea1a	436	TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
NYX	0:85b3fd62ea1a	437	}
NYX	0:85b3fd62ea1a	438
NYX	0:85b3fd62ea1a	439	/**
NYX	0:85b3fd62ea1a	440	* @brief Configure the TIMx input channel.
NYX	0:85b3fd62ea1a	441	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	442	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	443	* @arg @ref LL_TIM_CHANNEL_CH1
NYX	0:85b3fd62ea1a	444	* @arg @ref LL_TIM_CHANNEL_CH2
NYX	0:85b3fd62ea1a	445	* @arg @ref LL_TIM_CHANNEL_CH3
NYX	0:85b3fd62ea1a	446	* @arg @ref LL_TIM_CHANNEL_CH4
NYX	0:85b3fd62ea1a	447	* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
NYX	0:85b3fd62ea1a	448	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	449	* - SUCCESS: TIMx output channel is initialized
NYX	0:85b3fd62ea1a	450	* - ERROR: TIMx output channel is not initialized
NYX	0:85b3fd62ea1a	451	*/
NYX	0:85b3fd62ea1a	452	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct)
NYX	0:85b3fd62ea1a	453	{
NYX	0:85b3fd62ea1a	454	ErrorStatus result = ERROR;
NYX	0:85b3fd62ea1a	455
NYX	0:85b3fd62ea1a	456	switch (Channel)
NYX	0:85b3fd62ea1a	457	{
NYX	0:85b3fd62ea1a	458	case LL_TIM_CHANNEL_CH1:
NYX	0:85b3fd62ea1a	459	result = IC1Config(TIMx, TIM_IC_InitStruct);
NYX	0:85b3fd62ea1a	460	break;
NYX	0:85b3fd62ea1a	461	case LL_TIM_CHANNEL_CH2:
NYX	0:85b3fd62ea1a	462	result = IC2Config(TIMx, TIM_IC_InitStruct);
NYX	0:85b3fd62ea1a	463	break;
NYX	0:85b3fd62ea1a	464	case LL_TIM_CHANNEL_CH3:
NYX	0:85b3fd62ea1a	465	result = IC3Config(TIMx, TIM_IC_InitStruct);
NYX	0:85b3fd62ea1a	466	break;
NYX	0:85b3fd62ea1a	467	case LL_TIM_CHANNEL_CH4:
NYX	0:85b3fd62ea1a	468	result = IC4Config(TIMx, TIM_IC_InitStruct);
NYX	0:85b3fd62ea1a	469	break;
NYX	0:85b3fd62ea1a	470	default:
NYX	0:85b3fd62ea1a	471	break;
NYX	0:85b3fd62ea1a	472	}
NYX	0:85b3fd62ea1a	473
NYX	0:85b3fd62ea1a	474	return result;
NYX	0:85b3fd62ea1a	475	}
NYX	0:85b3fd62ea1a	476
NYX	0:85b3fd62ea1a	477	/**
NYX	0:85b3fd62ea1a	478	* @brief Fills each TIM_EncoderInitStruct field with its default value
NYX	0:85b3fd62ea1a	479	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
NYX	0:85b3fd62ea1a	480	* @retval None
NYX	0:85b3fd62ea1a	481	*/
NYX	0:85b3fd62ea1a	482	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
NYX	0:85b3fd62ea1a	483	{
NYX	0:85b3fd62ea1a	484	/* Set the default configuration */
NYX	0:85b3fd62ea1a	485	TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
NYX	0:85b3fd62ea1a	486	TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
NYX	0:85b3fd62ea1a	487	TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
NYX	0:85b3fd62ea1a	488	TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
NYX	0:85b3fd62ea1a	489	TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
NYX	0:85b3fd62ea1a	490	TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
NYX	0:85b3fd62ea1a	491	TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
NYX	0:85b3fd62ea1a	492	TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
NYX	0:85b3fd62ea1a	493	TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
NYX	0:85b3fd62ea1a	494	}
NYX	0:85b3fd62ea1a	495
NYX	0:85b3fd62ea1a	496	/**
NYX	0:85b3fd62ea1a	497	* @brief Configure the encoder interface of the timer instance.
NYX	0:85b3fd62ea1a	498	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	499	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
NYX	0:85b3fd62ea1a	500	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	501	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	502	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	503	*/
NYX	0:85b3fd62ea1a	504	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct)
NYX	0:85b3fd62ea1a	505	{
NYX	0:85b3fd62ea1a	506	uint32_t tmpccmr1 = 0U;
NYX	0:85b3fd62ea1a	507	uint32_t tmpccer = 0U;
NYX	0:85b3fd62ea1a	508
NYX	0:85b3fd62ea1a	509	/* Check the parameters */
NYX	0:85b3fd62ea1a	510	assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	511	assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
NYX	0:85b3fd62ea1a	512	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
NYX	0:85b3fd62ea1a	513	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
NYX	0:85b3fd62ea1a	514	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
NYX	0:85b3fd62ea1a	515	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
NYX	0:85b3fd62ea1a	516	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
NYX	0:85b3fd62ea1a	517	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
NYX	0:85b3fd62ea1a	518	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
NYX	0:85b3fd62ea1a	519	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
NYX	0:85b3fd62ea1a	520
NYX	0:85b3fd62ea1a	521	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
NYX	0:85b3fd62ea1a	522	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
NYX	0:85b3fd62ea1a	523
NYX	0:85b3fd62ea1a	524	/* Get the TIMx CCMR1 register value */
NYX	0:85b3fd62ea1a	525	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
NYX	0:85b3fd62ea1a	526
NYX	0:85b3fd62ea1a	527	/* Get the TIMx CCER register value */
NYX	0:85b3fd62ea1a	528	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
NYX	0:85b3fd62ea1a	529
NYX	0:85b3fd62ea1a	530	/* Configure TI1 */
NYX	0:85b3fd62ea1a	531	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
NYX	0:85b3fd62ea1a	532	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
NYX	0:85b3fd62ea1a	533	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
NYX	0:85b3fd62ea1a	534	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
NYX	0:85b3fd62ea1a	535
NYX	0:85b3fd62ea1a	536	/* Configure TI2 */
NYX	0:85b3fd62ea1a	537	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC);
NYX	0:85b3fd62ea1a	538	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
NYX	0:85b3fd62ea1a	539	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
NYX	0:85b3fd62ea1a	540	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
NYX	0:85b3fd62ea1a	541
NYX	0:85b3fd62ea1a	542	/* Set TI1 and TI2 polarity and enable TI1 and TI2 */
NYX	0:85b3fd62ea1a	543	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
NYX	0:85b3fd62ea1a	544	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
NYX	0:85b3fd62ea1a	545	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
NYX	0:85b3fd62ea1a	546	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
NYX	0:85b3fd62ea1a	547
NYX	0:85b3fd62ea1a	548	/* Set encoder mode */
NYX	0:85b3fd62ea1a	549	LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
NYX	0:85b3fd62ea1a	550
NYX	0:85b3fd62ea1a	551	/* Write to TIMx CCMR1 */
NYX	0:85b3fd62ea1a	552	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
NYX	0:85b3fd62ea1a	553
NYX	0:85b3fd62ea1a	554	/* Write to TIMx CCER */
NYX	0:85b3fd62ea1a	555	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
NYX	0:85b3fd62ea1a	556
NYX	0:85b3fd62ea1a	557	return SUCCESS;
NYX	0:85b3fd62ea1a	558	}
NYX	0:85b3fd62ea1a	559
NYX	0:85b3fd62ea1a	560	/**
NYX	0:85b3fd62ea1a	561	* @brief Set the fields of the TIMx Hall sensor interface configuration data
NYX	0:85b3fd62ea1a	562	* structure to their default values.
NYX	0:85b3fd62ea1a	563	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
NYX	0:85b3fd62ea1a	564	* @retval None
NYX	0:85b3fd62ea1a	565	*/
NYX	0:85b3fd62ea1a	566	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
NYX	0:85b3fd62ea1a	567	{
NYX	0:85b3fd62ea1a	568	/* Set the default configuration */
NYX	0:85b3fd62ea1a	569	TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
NYX	0:85b3fd62ea1a	570	TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
NYX	0:85b3fd62ea1a	571	TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
NYX	0:85b3fd62ea1a	572	TIM_HallSensorInitStruct->CommutationDelay = 0U;
NYX	0:85b3fd62ea1a	573	}
NYX	0:85b3fd62ea1a	574
NYX	0:85b3fd62ea1a	575	/**
NYX	0:85b3fd62ea1a	576	* @brief Configure the Hall sensor interface of the timer instance.
NYX	0:85b3fd62ea1a	577	* @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
NYX	0:85b3fd62ea1a	578	* to the TI1 input channel
NYX	0:85b3fd62ea1a	579	* @note TIMx slave mode controller is configured in reset mode.
NYX	0:85b3fd62ea1a	580	Selected internal trigger is TI1F_ED.
NYX	0:85b3fd62ea1a	581	* @note Channel 1 is configured as input, IC1 is mapped on TRC.
NYX	0:85b3fd62ea1a	582	* @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
NYX	0:85b3fd62ea1a	583	* between 2 changes on the inputs. It gives information about motor speed.
NYX	0:85b3fd62ea1a	584	* @note Channel 2 is configured in output PWM 2 mode.
NYX	0:85b3fd62ea1a	585	* @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
NYX	0:85b3fd62ea1a	586	* @note OC2REF is selected as trigger output on TRGO.
NYX	0:85b3fd62ea1a	587	* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
NYX	0:85b3fd62ea1a	588	* when TIMx operates in Hall sensor interface mode.
NYX	0:85b3fd62ea1a	589	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	590	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
NYX	0:85b3fd62ea1a	591	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	592	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	593	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	594	*/
NYX	0:85b3fd62ea1a	595	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct)
NYX	0:85b3fd62ea1a	596	{
NYX	0:85b3fd62ea1a	597	uint32_t tmpcr2 = 0U;
NYX	0:85b3fd62ea1a	598	uint32_t tmpccmr1 = 0U;
NYX	0:85b3fd62ea1a	599	uint32_t tmpccer = 0U;
NYX	0:85b3fd62ea1a	600	uint32_t tmpsmcr = 0U;
NYX	0:85b3fd62ea1a	601
NYX	0:85b3fd62ea1a	602	/* Check the parameters */
NYX	0:85b3fd62ea1a	603	assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	604	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
NYX	0:85b3fd62ea1a	605	assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
NYX	0:85b3fd62ea1a	606	assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
NYX	0:85b3fd62ea1a	607
NYX	0:85b3fd62ea1a	608	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
NYX	0:85b3fd62ea1a	609	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
NYX	0:85b3fd62ea1a	610
NYX	0:85b3fd62ea1a	611	/* Get the TIMx CR2 register value */
NYX	0:85b3fd62ea1a	612	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
NYX	0:85b3fd62ea1a	613
NYX	0:85b3fd62ea1a	614	/* Get the TIMx CCMR1 register value */
NYX	0:85b3fd62ea1a	615	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
NYX	0:85b3fd62ea1a	616
NYX	0:85b3fd62ea1a	617	/* Get the TIMx CCER register value */
NYX	0:85b3fd62ea1a	618	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
NYX	0:85b3fd62ea1a	619
NYX	0:85b3fd62ea1a	620	/* Get the TIMx SMCR register value */
NYX	0:85b3fd62ea1a	621	tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
NYX	0:85b3fd62ea1a	622
NYX	0:85b3fd62ea1a	623	/* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
NYX	0:85b3fd62ea1a	624	tmpcr2 \|= TIM_CR2_TI1S;
NYX	0:85b3fd62ea1a	625
NYX	0:85b3fd62ea1a	626	/* OC2REF signal is used as trigger output (TRGO) */
NYX	0:85b3fd62ea1a	627	tmpcr2 \|= LL_TIM_TRGO_OC2REF;
NYX	0:85b3fd62ea1a	628
NYX	0:85b3fd62ea1a	629	/* Configure the slave mode controller */
NYX	0:85b3fd62ea1a	630	tmpsmcr &= (uint32_t)~(TIM_SMCR_TS \| TIM_SMCR_SMS);
NYX	0:85b3fd62ea1a	631	tmpsmcr \|= LL_TIM_TS_TI1F_ED;
NYX	0:85b3fd62ea1a	632	tmpsmcr \|= LL_TIM_SLAVEMODE_RESET;
NYX	0:85b3fd62ea1a	633
NYX	0:85b3fd62ea1a	634	/* Configure input channel 1 */
NYX	0:85b3fd62ea1a	635	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
NYX	0:85b3fd62ea1a	636	tmpccmr1 \|= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
NYX	0:85b3fd62ea1a	637	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
NYX	0:85b3fd62ea1a	638	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
NYX	0:85b3fd62ea1a	639
NYX	0:85b3fd62ea1a	640	/* Configure input channel 2 */
NYX	0:85b3fd62ea1a	641	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M \| TIM_CCMR1_OC2FE \| TIM_CCMR1_OC2PE \| TIM_CCMR1_OC2CE);
NYX	0:85b3fd62ea1a	642	tmpccmr1 \|= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
NYX	0:85b3fd62ea1a	643
NYX	0:85b3fd62ea1a	644	/* Set Channel 1 polarity and enable Channel 1 and Channel2 */
NYX	0:85b3fd62ea1a	645	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
NYX	0:85b3fd62ea1a	646	tmpccer \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
NYX	0:85b3fd62ea1a	647	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
NYX	0:85b3fd62ea1a	648
NYX	0:85b3fd62ea1a	649	/* Write to TIMx CR2 */
NYX	0:85b3fd62ea1a	650	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
NYX	0:85b3fd62ea1a	651
NYX	0:85b3fd62ea1a	652	/* Write to TIMx SMCR */
NYX	0:85b3fd62ea1a	653	LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
NYX	0:85b3fd62ea1a	654
NYX	0:85b3fd62ea1a	655	/* Write to TIMx CCMR1 */
NYX	0:85b3fd62ea1a	656	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
NYX	0:85b3fd62ea1a	657
NYX	0:85b3fd62ea1a	658	/* Write to TIMx CCER */
NYX	0:85b3fd62ea1a	659	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
NYX	0:85b3fd62ea1a	660
NYX	0:85b3fd62ea1a	661	/* Write to TIMx CCR2 */
NYX	0:85b3fd62ea1a	662	LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
NYX	0:85b3fd62ea1a	663
NYX	0:85b3fd62ea1a	664	return SUCCESS;
NYX	0:85b3fd62ea1a	665	}
NYX	0:85b3fd62ea1a	666
NYX	0:85b3fd62ea1a	667	/**
NYX	0:85b3fd62ea1a	668	* @brief Set the fields of the Break and Dead Time configuration data structure
NYX	0:85b3fd62ea1a	669	* to their default values.
NYX	0:85b3fd62ea1a	670	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
NYX	0:85b3fd62ea1a	671	* @retval None
NYX	0:85b3fd62ea1a	672	*/
NYX	0:85b3fd62ea1a	673	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
NYX	0:85b3fd62ea1a	674	{
NYX	0:85b3fd62ea1a	675	/* Set the default configuration */
NYX	0:85b3fd62ea1a	676	TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
NYX	0:85b3fd62ea1a	677	TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
NYX	0:85b3fd62ea1a	678	TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
NYX	0:85b3fd62ea1a	679	TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
NYX	0:85b3fd62ea1a	680	TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
NYX	0:85b3fd62ea1a	681	TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
NYX	0:85b3fd62ea1a	682	TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
NYX	0:85b3fd62ea1a	683	}
NYX	0:85b3fd62ea1a	684
NYX	0:85b3fd62ea1a	685	/**
NYX	0:85b3fd62ea1a	686	* @brief Configure the Break and Dead Time feature of the timer instance.
NYX	0:85b3fd62ea1a	687	* @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
NYX	0:85b3fd62ea1a	688	* depending on the LOCK configuration, it can be necessary to configure all of
NYX	0:85b3fd62ea1a	689	* them during the first write access to the TIMx_BDTR register.
NYX	0:85b3fd62ea1a	690	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
NYX	0:85b3fd62ea1a	691	* a timer instance provides a break input.
NYX	0:85b3fd62ea1a	692	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	693	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
NYX	0:85b3fd62ea1a	694	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	695	* - SUCCESS: Break and Dead Time is initialized
NYX	0:85b3fd62ea1a	696	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	697	*/
NYX	0:85b3fd62ea1a	698	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct)
NYX	0:85b3fd62ea1a	699	{
NYX	0:85b3fd62ea1a	700	uint32_t tmpbdtr = 0;
NYX	0:85b3fd62ea1a	701
NYX	0:85b3fd62ea1a	702	/* Check the parameters */
NYX	0:85b3fd62ea1a	703	assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	704	assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
NYX	0:85b3fd62ea1a	705	assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
NYX	0:85b3fd62ea1a	706	assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
NYX	0:85b3fd62ea1a	707	assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
NYX	0:85b3fd62ea1a	708	assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
NYX	0:85b3fd62ea1a	709	assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
NYX	0:85b3fd62ea1a	710
NYX	0:85b3fd62ea1a	711	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
NYX	0:85b3fd62ea1a	712	the OSSI State, the dead time value and the Automatic Output Enable Bit */
NYX	0:85b3fd62ea1a	713
NYX	0:85b3fd62ea1a	714	/* Set the BDTR bits */
NYX	0:85b3fd62ea1a	715	MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
NYX	0:85b3fd62ea1a	716	MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
NYX	0:85b3fd62ea1a	717	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
NYX	0:85b3fd62ea1a	718	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
NYX	0:85b3fd62ea1a	719	MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
NYX	0:85b3fd62ea1a	720	MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
NYX	0:85b3fd62ea1a	721	MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
NYX	0:85b3fd62ea1a	722	MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
NYX	0:85b3fd62ea1a	723
NYX	0:85b3fd62ea1a	724	/* Set TIMx_BDTR */
NYX	0:85b3fd62ea1a	725	LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
NYX	0:85b3fd62ea1a	726
NYX	0:85b3fd62ea1a	727	return SUCCESS;
NYX	0:85b3fd62ea1a	728	}
NYX	0:85b3fd62ea1a	729	/**
NYX	0:85b3fd62ea1a	730	* @}
NYX	0:85b3fd62ea1a	731	*/
NYX	0:85b3fd62ea1a	732
NYX	0:85b3fd62ea1a	733	/**
NYX	0:85b3fd62ea1a	734	* @}
NYX	0:85b3fd62ea1a	735	*/
NYX	0:85b3fd62ea1a	736
NYX	0:85b3fd62ea1a	737	/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
NYX	0:85b3fd62ea1a	738	* @brief Private functions
NYX	0:85b3fd62ea1a	739	* @{
NYX	0:85b3fd62ea1a	740	*/
NYX	0:85b3fd62ea1a	741	/**
NYX	0:85b3fd62ea1a	742	* @brief Configure the TIMx output channel 1.
NYX	0:85b3fd62ea1a	743	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	744	* @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
NYX	0:85b3fd62ea1a	745	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	746	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	747	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	748	*/
NYX	0:85b3fd62ea1a	749	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
NYX	0:85b3fd62ea1a	750	{
NYX	0:85b3fd62ea1a	751	uint32_t tmpccmr1 = 0U;
NYX	0:85b3fd62ea1a	752	uint32_t tmpccer = 0U;
NYX	0:85b3fd62ea1a	753	uint32_t tmpcr2 = 0U;
NYX	0:85b3fd62ea1a	754
NYX	0:85b3fd62ea1a	755	/* Check the parameters */
NYX	0:85b3fd62ea1a	756	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	757	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
NYX	0:85b3fd62ea1a	758	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
NYX	0:85b3fd62ea1a	759	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
NYX	0:85b3fd62ea1a	760	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
NYX	0:85b3fd62ea1a	761	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
NYX	0:85b3fd62ea1a	762
NYX	0:85b3fd62ea1a	763	/* Disable the Channel 1: Reset the CC1E Bit */
NYX	0:85b3fd62ea1a	764	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
NYX	0:85b3fd62ea1a	765
NYX	0:85b3fd62ea1a	766	/* Get the TIMx CCER register value */
NYX	0:85b3fd62ea1a	767	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
NYX	0:85b3fd62ea1a	768
NYX	0:85b3fd62ea1a	769	/* Get the TIMx CR2 register value */
NYX	0:85b3fd62ea1a	770	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
NYX	0:85b3fd62ea1a	771
NYX	0:85b3fd62ea1a	772	/* Get the TIMx CCMR1 register value */
NYX	0:85b3fd62ea1a	773	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
NYX	0:85b3fd62ea1a	774
NYX	0:85b3fd62ea1a	775	/* Reset Capture/Compare selection Bits */
NYX	0:85b3fd62ea1a	776	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
NYX	0:85b3fd62ea1a	777
NYX	0:85b3fd62ea1a	778	/* Set the Output Compare Mode */
NYX	0:85b3fd62ea1a	779	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
NYX	0:85b3fd62ea1a	780
NYX	0:85b3fd62ea1a	781	/* Set the Output Compare Polarity */
NYX	0:85b3fd62ea1a	782	MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
NYX	0:85b3fd62ea1a	783
NYX	0:85b3fd62ea1a	784	/* Set the Output State */
NYX	0:85b3fd62ea1a	785	MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
NYX	0:85b3fd62ea1a	786
NYX	0:85b3fd62ea1a	787	if (IS_TIM_BREAK_INSTANCE(TIMx))
NYX	0:85b3fd62ea1a	788	{
NYX	0:85b3fd62ea1a	789	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
NYX	0:85b3fd62ea1a	790	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
NYX	0:85b3fd62ea1a	791
NYX	0:85b3fd62ea1a	792	/* Set the complementary output Polarity */
NYX	0:85b3fd62ea1a	793	MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
NYX	0:85b3fd62ea1a	794
NYX	0:85b3fd62ea1a	795	/* Set the complementary output State */
NYX	0:85b3fd62ea1a	796	MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
NYX	0:85b3fd62ea1a	797
NYX	0:85b3fd62ea1a	798	/* Set the Output Idle state */
NYX	0:85b3fd62ea1a	799	MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
NYX	0:85b3fd62ea1a	800
NYX	0:85b3fd62ea1a	801	/* Set the complementary output Idle state */
NYX	0:85b3fd62ea1a	802	MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
NYX	0:85b3fd62ea1a	803	}
NYX	0:85b3fd62ea1a	804
NYX	0:85b3fd62ea1a	805	/* Write to TIMx CR2 */
NYX	0:85b3fd62ea1a	806	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
NYX	0:85b3fd62ea1a	807
NYX	0:85b3fd62ea1a	808	/* Write to TIMx CCMR1 */
NYX	0:85b3fd62ea1a	809	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
NYX	0:85b3fd62ea1a	810
NYX	0:85b3fd62ea1a	811	/* Set the Capture Compare Register value */
NYX	0:85b3fd62ea1a	812	LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
NYX	0:85b3fd62ea1a	813
NYX	0:85b3fd62ea1a	814	/* Write to TIMx CCER */
NYX	0:85b3fd62ea1a	815	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
NYX	0:85b3fd62ea1a	816
NYX	0:85b3fd62ea1a	817	return SUCCESS;
NYX	0:85b3fd62ea1a	818	}
NYX	0:85b3fd62ea1a	819
NYX	0:85b3fd62ea1a	820	/**
NYX	0:85b3fd62ea1a	821	* @brief Configure the TIMx output channel 2.
NYX	0:85b3fd62ea1a	822	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	823	* @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
NYX	0:85b3fd62ea1a	824	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	825	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	826	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	827	*/
NYX	0:85b3fd62ea1a	828	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
NYX	0:85b3fd62ea1a	829	{
NYX	0:85b3fd62ea1a	830	uint32_t tmpccmr1 = 0U;
NYX	0:85b3fd62ea1a	831	uint32_t tmpccer = 0U;
NYX	0:85b3fd62ea1a	832	uint32_t tmpcr2 = 0U;
NYX	0:85b3fd62ea1a	833
NYX	0:85b3fd62ea1a	834	/* Check the parameters */
NYX	0:85b3fd62ea1a	835	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	836	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
NYX	0:85b3fd62ea1a	837	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
NYX	0:85b3fd62ea1a	838	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
NYX	0:85b3fd62ea1a	839	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
NYX	0:85b3fd62ea1a	840	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
NYX	0:85b3fd62ea1a	841
NYX	0:85b3fd62ea1a	842	/* Disable the Channel 2: Reset the CC2E Bit */
NYX	0:85b3fd62ea1a	843	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
NYX	0:85b3fd62ea1a	844
NYX	0:85b3fd62ea1a	845	/* Get the TIMx CCER register value */
NYX	0:85b3fd62ea1a	846	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
NYX	0:85b3fd62ea1a	847
NYX	0:85b3fd62ea1a	848	/* Get the TIMx CR2 register value */
NYX	0:85b3fd62ea1a	849	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
NYX	0:85b3fd62ea1a	850
NYX	0:85b3fd62ea1a	851	/* Get the TIMx CCMR1 register value */
NYX	0:85b3fd62ea1a	852	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
NYX	0:85b3fd62ea1a	853
NYX	0:85b3fd62ea1a	854	/* Reset Capture/Compare selection Bits */
NYX	0:85b3fd62ea1a	855	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
NYX	0:85b3fd62ea1a	856
NYX	0:85b3fd62ea1a	857	/* Select the Output Compare Mode */
NYX	0:85b3fd62ea1a	858	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
NYX	0:85b3fd62ea1a	859
NYX	0:85b3fd62ea1a	860	/* Set the Output Compare Polarity */
NYX	0:85b3fd62ea1a	861	MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
NYX	0:85b3fd62ea1a	862
NYX	0:85b3fd62ea1a	863	/* Set the Output State */
NYX	0:85b3fd62ea1a	864	MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
NYX	0:85b3fd62ea1a	865
NYX	0:85b3fd62ea1a	866	if (IS_TIM_BREAK_INSTANCE(TIMx))
NYX	0:85b3fd62ea1a	867	{
NYX	0:85b3fd62ea1a	868	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
NYX	0:85b3fd62ea1a	869	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
NYX	0:85b3fd62ea1a	870
NYX	0:85b3fd62ea1a	871	/* Set the complementary output Polarity */
NYX	0:85b3fd62ea1a	872	MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
NYX	0:85b3fd62ea1a	873
NYX	0:85b3fd62ea1a	874	/* Set the complementary output State */
NYX	0:85b3fd62ea1a	875	MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
NYX	0:85b3fd62ea1a	876
NYX	0:85b3fd62ea1a	877	/* Set the Output Idle state */
NYX	0:85b3fd62ea1a	878	MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
NYX	0:85b3fd62ea1a	879
NYX	0:85b3fd62ea1a	880	/* Set the complementary output Idle state */
NYX	0:85b3fd62ea1a	881	MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
NYX	0:85b3fd62ea1a	882	}
NYX	0:85b3fd62ea1a	883
NYX	0:85b3fd62ea1a	884	/* Write to TIMx CR2 */
NYX	0:85b3fd62ea1a	885	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
NYX	0:85b3fd62ea1a	886
NYX	0:85b3fd62ea1a	887	/* Write to TIMx CCMR1 */
NYX	0:85b3fd62ea1a	888	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
NYX	0:85b3fd62ea1a	889
NYX	0:85b3fd62ea1a	890	/* Set the Capture Compare Register value */
NYX	0:85b3fd62ea1a	891	LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
NYX	0:85b3fd62ea1a	892
NYX	0:85b3fd62ea1a	893	/* Write to TIMx CCER */
NYX	0:85b3fd62ea1a	894	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
NYX	0:85b3fd62ea1a	895
NYX	0:85b3fd62ea1a	896	return SUCCESS;
NYX	0:85b3fd62ea1a	897	}
NYX	0:85b3fd62ea1a	898
NYX	0:85b3fd62ea1a	899	/**
NYX	0:85b3fd62ea1a	900	* @brief Configure the TIMx output channel 3.
NYX	0:85b3fd62ea1a	901	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	902	* @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
NYX	0:85b3fd62ea1a	903	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	904	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	905	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	906	*/
NYX	0:85b3fd62ea1a	907	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
NYX	0:85b3fd62ea1a	908	{
NYX	0:85b3fd62ea1a	909	uint32_t tmpccmr2 = 0U;
NYX	0:85b3fd62ea1a	910	uint32_t tmpccer = 0U;
NYX	0:85b3fd62ea1a	911	uint32_t tmpcr2 = 0U;
NYX	0:85b3fd62ea1a	912
NYX	0:85b3fd62ea1a	913	/* Check the parameters */
NYX	0:85b3fd62ea1a	914	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	915	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
NYX	0:85b3fd62ea1a	916	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
NYX	0:85b3fd62ea1a	917	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
NYX	0:85b3fd62ea1a	918	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
NYX	0:85b3fd62ea1a	919	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
NYX	0:85b3fd62ea1a	920
NYX	0:85b3fd62ea1a	921	/* Disable the Channel 3: Reset the CC3E Bit */
NYX	0:85b3fd62ea1a	922	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
NYX	0:85b3fd62ea1a	923
NYX	0:85b3fd62ea1a	924	/* Get the TIMx CCER register value */
NYX	0:85b3fd62ea1a	925	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
NYX	0:85b3fd62ea1a	926
NYX	0:85b3fd62ea1a	927	/* Get the TIMx CR2 register value */
NYX	0:85b3fd62ea1a	928	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
NYX	0:85b3fd62ea1a	929
NYX	0:85b3fd62ea1a	930	/* Get the TIMx CCMR2 register value */
NYX	0:85b3fd62ea1a	931	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
NYX	0:85b3fd62ea1a	932
NYX	0:85b3fd62ea1a	933	/* Reset Capture/Compare selection Bits */
NYX	0:85b3fd62ea1a	934	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
NYX	0:85b3fd62ea1a	935
NYX	0:85b3fd62ea1a	936	/* Select the Output Compare Mode */
NYX	0:85b3fd62ea1a	937	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
NYX	0:85b3fd62ea1a	938
NYX	0:85b3fd62ea1a	939	/* Set the Output Compare Polarity */
NYX	0:85b3fd62ea1a	940	MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
NYX	0:85b3fd62ea1a	941
NYX	0:85b3fd62ea1a	942	/* Set the Output State */
NYX	0:85b3fd62ea1a	943	MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
NYX	0:85b3fd62ea1a	944
NYX	0:85b3fd62ea1a	945	if (IS_TIM_BREAK_INSTANCE(TIMx))
NYX	0:85b3fd62ea1a	946	{
NYX	0:85b3fd62ea1a	947	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
NYX	0:85b3fd62ea1a	948	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
NYX	0:85b3fd62ea1a	949
NYX	0:85b3fd62ea1a	950	/* Set the complementary output Polarity */
NYX	0:85b3fd62ea1a	951	MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
NYX	0:85b3fd62ea1a	952
NYX	0:85b3fd62ea1a	953	/* Set the complementary output State */
NYX	0:85b3fd62ea1a	954	MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
NYX	0:85b3fd62ea1a	955
NYX	0:85b3fd62ea1a	956	/* Set the Output Idle state */
NYX	0:85b3fd62ea1a	957	MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
NYX	0:85b3fd62ea1a	958
NYX	0:85b3fd62ea1a	959	/* Set the complementary output Idle state */
NYX	0:85b3fd62ea1a	960	MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
NYX	0:85b3fd62ea1a	961	}
NYX	0:85b3fd62ea1a	962
NYX	0:85b3fd62ea1a	963	/* Write to TIMx CR2 */
NYX	0:85b3fd62ea1a	964	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
NYX	0:85b3fd62ea1a	965
NYX	0:85b3fd62ea1a	966	/* Write to TIMx CCMR2 */
NYX	0:85b3fd62ea1a	967	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
NYX	0:85b3fd62ea1a	968
NYX	0:85b3fd62ea1a	969	/* Set the Capture Compare Register value */
NYX	0:85b3fd62ea1a	970	LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
NYX	0:85b3fd62ea1a	971
NYX	0:85b3fd62ea1a	972	/* Write to TIMx CCER */
NYX	0:85b3fd62ea1a	973	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
NYX	0:85b3fd62ea1a	974
NYX	0:85b3fd62ea1a	975	return SUCCESS;
NYX	0:85b3fd62ea1a	976	}
NYX	0:85b3fd62ea1a	977
NYX	0:85b3fd62ea1a	978	/**
NYX	0:85b3fd62ea1a	979	* @brief Configure the TIMx output channel 4.
NYX	0:85b3fd62ea1a	980	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	981	* @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
NYX	0:85b3fd62ea1a	982	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	983	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	984	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	985	*/
NYX	0:85b3fd62ea1a	986	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
NYX	0:85b3fd62ea1a	987	{
NYX	0:85b3fd62ea1a	988	uint32_t tmpccmr2 = 0U;
NYX	0:85b3fd62ea1a	989	uint32_t tmpccer = 0U;
NYX	0:85b3fd62ea1a	990	uint32_t tmpcr2 = 0U;
NYX	0:85b3fd62ea1a	991
NYX	0:85b3fd62ea1a	992	/* Check the parameters */
NYX	0:85b3fd62ea1a	993	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	994	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
NYX	0:85b3fd62ea1a	995	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
NYX	0:85b3fd62ea1a	996	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
NYX	0:85b3fd62ea1a	997	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
NYX	0:85b3fd62ea1a	998	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
NYX	0:85b3fd62ea1a	999
NYX	0:85b3fd62ea1a	1000	/* Disable the Channel 4: Reset the CC4E Bit */
NYX	0:85b3fd62ea1a	1001	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
NYX	0:85b3fd62ea1a	1002
NYX	0:85b3fd62ea1a	1003	/* Get the TIMx CCER register value */
NYX	0:85b3fd62ea1a	1004	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
NYX	0:85b3fd62ea1a	1005
NYX	0:85b3fd62ea1a	1006	/* Get the TIMx CR2 register value */
NYX	0:85b3fd62ea1a	1007	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
NYX	0:85b3fd62ea1a	1008
NYX	0:85b3fd62ea1a	1009	/* Get the TIMx CCMR2 register value */
NYX	0:85b3fd62ea1a	1010	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
NYX	0:85b3fd62ea1a	1011
NYX	0:85b3fd62ea1a	1012	/* Reset Capture/Compare selection Bits */
NYX	0:85b3fd62ea1a	1013	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
NYX	0:85b3fd62ea1a	1014
NYX	0:85b3fd62ea1a	1015	/* Select the Output Compare Mode */
NYX	0:85b3fd62ea1a	1016	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
NYX	0:85b3fd62ea1a	1017
NYX	0:85b3fd62ea1a	1018	/* Set the Output Compare Polarity */
NYX	0:85b3fd62ea1a	1019	MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
NYX	0:85b3fd62ea1a	1020
NYX	0:85b3fd62ea1a	1021	/* Set the Output State */
NYX	0:85b3fd62ea1a	1022	MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
NYX	0:85b3fd62ea1a	1023
NYX	0:85b3fd62ea1a	1024	if (IS_TIM_BREAK_INSTANCE(TIMx))
NYX	0:85b3fd62ea1a	1025	{
NYX	0:85b3fd62ea1a	1026	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
NYX	0:85b3fd62ea1a	1027	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
NYX	0:85b3fd62ea1a	1028
NYX	0:85b3fd62ea1a	1029	/* Set the Output Idle state */
NYX	0:85b3fd62ea1a	1030	MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
NYX	0:85b3fd62ea1a	1031	}
NYX	0:85b3fd62ea1a	1032
NYX	0:85b3fd62ea1a	1033	/* Write to TIMx CR2 */
NYX	0:85b3fd62ea1a	1034	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
NYX	0:85b3fd62ea1a	1035
NYX	0:85b3fd62ea1a	1036	/* Write to TIMx CCMR2 */
NYX	0:85b3fd62ea1a	1037	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
NYX	0:85b3fd62ea1a	1038
NYX	0:85b3fd62ea1a	1039	/* Set the Capture Compare Register value */
NYX	0:85b3fd62ea1a	1040	LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
NYX	0:85b3fd62ea1a	1041
NYX	0:85b3fd62ea1a	1042	/* Write to TIMx CCER */
NYX	0:85b3fd62ea1a	1043	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
NYX	0:85b3fd62ea1a	1044
NYX	0:85b3fd62ea1a	1045	return SUCCESS;
NYX	0:85b3fd62ea1a	1046	}
NYX	0:85b3fd62ea1a	1047
NYX	0:85b3fd62ea1a	1048
NYX	0:85b3fd62ea1a	1049	/**
NYX	0:85b3fd62ea1a	1050	* @brief Configure the TIMx input channel 1.
NYX	0:85b3fd62ea1a	1051	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	1052	* @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
NYX	0:85b3fd62ea1a	1053	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	1054	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	1055	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	1056	*/
NYX	0:85b3fd62ea1a	1057	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
NYX	0:85b3fd62ea1a	1058	{
NYX	0:85b3fd62ea1a	1059	/* Check the parameters */
NYX	0:85b3fd62ea1a	1060	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	1061	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
NYX	0:85b3fd62ea1a	1062	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
NYX	0:85b3fd62ea1a	1063	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
NYX	0:85b3fd62ea1a	1064	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
NYX	0:85b3fd62ea1a	1065
NYX	0:85b3fd62ea1a	1066	/* Disable the Channel 1: Reset the CC1E Bit */
NYX	0:85b3fd62ea1a	1067	TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
NYX	0:85b3fd62ea1a	1068
NYX	0:85b3fd62ea1a	1069	/* Select the Input and set the filter and the prescaler value */
NYX	0:85b3fd62ea1a	1070	MODIFY_REG(TIMx->CCMR1,
NYX	0:85b3fd62ea1a	1071	(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC),
NYX	0:85b3fd62ea1a	1072	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
NYX	0:85b3fd62ea1a	1073
NYX	0:85b3fd62ea1a	1074	/* Select the Polarity and set the CC1E Bit */
NYX	0:85b3fd62ea1a	1075	MODIFY_REG(TIMx->CCER,
NYX	0:85b3fd62ea1a	1076	(TIM_CCER_CC1P \| TIM_CCER_CC1NP),
NYX	0:85b3fd62ea1a	1077	(TIM_ICInitStruct->ICPolarity \| TIM_CCER_CC1E));
NYX	0:85b3fd62ea1a	1078
NYX	0:85b3fd62ea1a	1079	return SUCCESS;
NYX	0:85b3fd62ea1a	1080	}
NYX	0:85b3fd62ea1a	1081
NYX	0:85b3fd62ea1a	1082	/**
NYX	0:85b3fd62ea1a	1083	* @brief Configure the TIMx input channel 2.
NYX	0:85b3fd62ea1a	1084	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	1085	* @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
NYX	0:85b3fd62ea1a	1086	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	1087	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	1088	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	1089	*/
NYX	0:85b3fd62ea1a	1090	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
NYX	0:85b3fd62ea1a	1091	{
NYX	0:85b3fd62ea1a	1092	/* Check the parameters */
NYX	0:85b3fd62ea1a	1093	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	1094	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
NYX	0:85b3fd62ea1a	1095	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
NYX	0:85b3fd62ea1a	1096	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
NYX	0:85b3fd62ea1a	1097	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
NYX	0:85b3fd62ea1a	1098
NYX	0:85b3fd62ea1a	1099	/* Disable the Channel 2: Reset the CC2E Bit */
NYX	0:85b3fd62ea1a	1100	TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
NYX	0:85b3fd62ea1a	1101
NYX	0:85b3fd62ea1a	1102	/* Select the Input and set the filter and the prescaler value */
NYX	0:85b3fd62ea1a	1103	MODIFY_REG(TIMx->CCMR1,
NYX	0:85b3fd62ea1a	1104	(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC),
NYX	0:85b3fd62ea1a	1105	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
NYX	0:85b3fd62ea1a	1106
NYX	0:85b3fd62ea1a	1107	/* Select the Polarity and set the CC2E Bit */
NYX	0:85b3fd62ea1a	1108	MODIFY_REG(TIMx->CCER,
NYX	0:85b3fd62ea1a	1109	(TIM_CCER_CC2P \| TIM_CCER_CC2NP),
NYX	0:85b3fd62ea1a	1110	((TIM_ICInitStruct->ICPolarity << 4U) \| TIM_CCER_CC2E));
NYX	0:85b3fd62ea1a	1111
NYX	0:85b3fd62ea1a	1112	return SUCCESS;
NYX	0:85b3fd62ea1a	1113	}
NYX	0:85b3fd62ea1a	1114
NYX	0:85b3fd62ea1a	1115	/**
NYX	0:85b3fd62ea1a	1116	* @brief Configure the TIMx input channel 3.
NYX	0:85b3fd62ea1a	1117	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	1118	* @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
NYX	0:85b3fd62ea1a	1119	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	1120	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	1121	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	1122	*/
NYX	0:85b3fd62ea1a	1123	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
NYX	0:85b3fd62ea1a	1124	{
NYX	0:85b3fd62ea1a	1125	/* Check the parameters */
NYX	0:85b3fd62ea1a	1126	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	1127	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
NYX	0:85b3fd62ea1a	1128	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
NYX	0:85b3fd62ea1a	1129	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
NYX	0:85b3fd62ea1a	1130	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
NYX	0:85b3fd62ea1a	1131
NYX	0:85b3fd62ea1a	1132	/* Disable the Channel 3: Reset the CC3E Bit */
NYX	0:85b3fd62ea1a	1133	TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
NYX	0:85b3fd62ea1a	1134
NYX	0:85b3fd62ea1a	1135	/* Select the Input and set the filter and the prescaler value */
NYX	0:85b3fd62ea1a	1136	MODIFY_REG(TIMx->CCMR2,
NYX	0:85b3fd62ea1a	1137	(TIM_CCMR2_CC3S \| TIM_CCMR2_IC3F \| TIM_CCMR2_IC3PSC),
NYX	0:85b3fd62ea1a	1138	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
NYX	0:85b3fd62ea1a	1139
NYX	0:85b3fd62ea1a	1140	/* Select the Polarity and set the CC3E Bit */
NYX	0:85b3fd62ea1a	1141	MODIFY_REG(TIMx->CCER,
NYX	0:85b3fd62ea1a	1142	(TIM_CCER_CC3P \| TIM_CCER_CC3NP),
NYX	0:85b3fd62ea1a	1143	((TIM_ICInitStruct->ICPolarity << 8U) \| TIM_CCER_CC3E));
NYX	0:85b3fd62ea1a	1144
NYX	0:85b3fd62ea1a	1145	return SUCCESS;
NYX	0:85b3fd62ea1a	1146	}
NYX	0:85b3fd62ea1a	1147
NYX	0:85b3fd62ea1a	1148	/**
NYX	0:85b3fd62ea1a	1149	* @brief Configure the TIMx input channel 4.
NYX	0:85b3fd62ea1a	1150	* @param TIMx Timer Instance
NYX	0:85b3fd62ea1a	1151	* @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
NYX	0:85b3fd62ea1a	1152	* @retval An ErrorStatus enumeration value:
NYX	0:85b3fd62ea1a	1153	* - SUCCESS: TIMx registers are de-initialized
NYX	0:85b3fd62ea1a	1154	* - ERROR: not applicable
NYX	0:85b3fd62ea1a	1155	*/
NYX	0:85b3fd62ea1a	1156	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
NYX	0:85b3fd62ea1a	1157	{
NYX	0:85b3fd62ea1a	1158	/* Check the parameters */
NYX	0:85b3fd62ea1a	1159	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
NYX	0:85b3fd62ea1a	1160	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
NYX	0:85b3fd62ea1a	1161	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
NYX	0:85b3fd62ea1a	1162	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
NYX	0:85b3fd62ea1a	1163	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
NYX	0:85b3fd62ea1a	1164
NYX	0:85b3fd62ea1a	1165	/* Disable the Channel 4: Reset the CC4E Bit */
NYX	0:85b3fd62ea1a	1166	TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
NYX	0:85b3fd62ea1a	1167
NYX	0:85b3fd62ea1a	1168	/* Select the Input and set the filter and the prescaler value */
NYX	0:85b3fd62ea1a	1169	MODIFY_REG(TIMx->CCMR2,
NYX	0:85b3fd62ea1a	1170	(TIM_CCMR2_CC4S \| TIM_CCMR2_IC4F \| TIM_CCMR2_IC4PSC),
NYX	0:85b3fd62ea1a	1171	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
NYX	0:85b3fd62ea1a	1172
NYX	0:85b3fd62ea1a	1173	/* Select the Polarity and set the CC2E Bit */
NYX	0:85b3fd62ea1a	1174	MODIFY_REG(TIMx->CCER,
NYX	0:85b3fd62ea1a	1175	(TIM_CCER_CC4P \| TIM_CCER_CC4NP),
NYX	0:85b3fd62ea1a	1176	((TIM_ICInitStruct->ICPolarity << 12U) \| TIM_CCER_CC4E));
NYX	0:85b3fd62ea1a	1177
NYX	0:85b3fd62ea1a	1178	return SUCCESS;
NYX	0:85b3fd62ea1a	1179	}
NYX	0:85b3fd62ea1a	1180
NYX	0:85b3fd62ea1a	1181
NYX	0:85b3fd62ea1a	1182	/**
NYX	0:85b3fd62ea1a	1183	* @}
NYX	0:85b3fd62ea1a	1184	*/
NYX	0:85b3fd62ea1a	1185
NYX	0:85b3fd62ea1a	1186	/**
NYX	0:85b3fd62ea1a	1187	* @}
NYX	0:85b3fd62ea1a	1188	*/
NYX	0:85b3fd62ea1a	1189
NYX	0:85b3fd62ea1a	1190	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 */
NYX	0:85b3fd62ea1a	1191
NYX	0:85b3fd62ea1a	1192	/**
NYX	0:85b3fd62ea1a	1193	* @}
NYX	0:85b3fd62ea1a	1194	*/
NYX	0:85b3fd62ea1a	1195
NYX	0:85b3fd62ea1a	1196	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	1197
NYX	0:85b3fd62ea1a	1198	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

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