mbed-dev - inport from local

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inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_ll_system.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of SYSTEM LL module.
NYX	0:85b3fd62ea1a	8	@verbatim
NYX	0:85b3fd62ea1a	9	==============================================================================
NYX	0:85b3fd62ea1a	10	##### How to use this driver #####
NYX	0:85b3fd62ea1a	11	==============================================================================
NYX	0:85b3fd62ea1a	12	[..]
NYX	0:85b3fd62ea1a	13	The LL SYSTEM driver contains a set of generic APIs that can be
NYX	0:85b3fd62ea1a	14	used by user:
NYX	0:85b3fd62ea1a	15	(+) Some of the FLASH features need to be handled in the SYSTEM file.
NYX	0:85b3fd62ea1a	16	(+) Access to DBGCMU registers
NYX	0:85b3fd62ea1a	17	(+) Access to SYSCFG registers
NYX	0:85b3fd62ea1a	18
NYX	0:85b3fd62ea1a	19	@endverbatim
NYX	0:85b3fd62ea1a	20	******************************************************************************
NYX	0:85b3fd62ea1a	21	* @attention
NYX	0:85b3fd62ea1a	22	*
NYX	0:85b3fd62ea1a	23	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	24	*
NYX	0:85b3fd62ea1a	25	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	26	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	27	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	28	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	29	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	30	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	31	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	32	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	33	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	34	* without specific prior written permission.
NYX	0:85b3fd62ea1a	35	*
NYX	0:85b3fd62ea1a	36	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	37	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	38	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	39	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	40	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	41	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	42	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	43	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	44	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	45	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	46	*
NYX	0:85b3fd62ea1a	47	******************************************************************************
NYX	0:85b3fd62ea1a	48	*/
NYX	0:85b3fd62ea1a	49
NYX	0:85b3fd62ea1a	50	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	51	#ifndef __STM32F4xx_LL_SYSTEM_H
NYX	0:85b3fd62ea1a	52	#define __STM32F4xx_LL_SYSTEM_H
NYX	0:85b3fd62ea1a	53
NYX	0:85b3fd62ea1a	54	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	55	extern "C" {
NYX	0:85b3fd62ea1a	56	#endif
NYX	0:85b3fd62ea1a	57
NYX	0:85b3fd62ea1a	58	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	59	#include "stm32f4xx.h"
NYX	0:85b3fd62ea1a	60
NYX	0:85b3fd62ea1a	61	/** @addtogroup STM32F4xx_LL_Driver
NYX	0:85b3fd62ea1a	62	* @{
NYX	0:85b3fd62ea1a	63	*/
NYX	0:85b3fd62ea1a	64
NYX	0:85b3fd62ea1a	65	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
NYX	0:85b3fd62ea1a	66
NYX	0:85b3fd62ea1a	67	/** @defgroup SYSTEM_LL SYSTEM
NYX	0:85b3fd62ea1a	68	* @{
NYX	0:85b3fd62ea1a	69	*/
NYX	0:85b3fd62ea1a	70
NYX	0:85b3fd62ea1a	71	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	72	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	73
NYX	0:85b3fd62ea1a	74	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	75	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
NYX	0:85b3fd62ea1a	76	* @{
NYX	0:85b3fd62ea1a	77	*/
NYX	0:85b3fd62ea1a	78
NYX	0:85b3fd62ea1a	79	/**
NYX	0:85b3fd62ea1a	80	* @}
NYX	0:85b3fd62ea1a	81	*/
NYX	0:85b3fd62ea1a	82
NYX	0:85b3fd62ea1a	83	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	84
NYX	0:85b3fd62ea1a	85	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	86	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	87	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
NYX	0:85b3fd62ea1a	88	* @{
NYX	0:85b3fd62ea1a	89	*/
NYX	0:85b3fd62ea1a	90
NYX	0:85b3fd62ea1a	91	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
NYX	0:85b3fd62ea1a	92	* @{
NYX	0:85b3fd62ea1a	93	*/
NYX	0:85b3fd62ea1a	94	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /!< Main Flash memory mapped at 0x00000000 /
NYX	0:85b3fd62ea1a	95	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
NYX	0:85b3fd62ea1a	96	#if defined(FSMC_Bank1)
NYX	0:85b3fd62ea1a	97	#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 /
NYX	0:85b3fd62ea1a	98	#endif /* FSMC_Bank1 */
NYX	0:85b3fd62ea1a	99	#if defined(FMC_Bank1)
NYX	0:85b3fd62ea1a	100	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 /
NYX	0:85b3fd62ea1a	101	#endif /* FMC_Bank1 */
NYX	0:85b3fd62ea1a	102	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /!< SRAM1 mapped at 0x00000000 /
NYX	0:85b3fd62ea1a	103	/**
NYX	0:85b3fd62ea1a	104	* @}
NYX	0:85b3fd62ea1a	105	*/
NYX	0:85b3fd62ea1a	106
NYX	0:85b3fd62ea1a	107	#if defined(SYSCFG_PMC_MII_RMII_SEL)
NYX	0:85b3fd62ea1a	108	/** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
NYX	0:85b3fd62ea1a	109	* @{
NYX	0:85b3fd62ea1a	110	*/
NYX	0:85b3fd62ea1a	111	#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /!< ETH Media MII interface /
NYX	0:85b3fd62ea1a	112	#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /!< ETH Media RMII interface /
NYX	0:85b3fd62ea1a	113
NYX	0:85b3fd62ea1a	114	/**
NYX	0:85b3fd62ea1a	115	* @}
NYX	0:85b3fd62ea1a	116	*/
NYX	0:85b3fd62ea1a	117	#endif /* SYSCFG_PMC_MII_RMII_SEL */
NYX	0:85b3fd62ea1a	118
NYX	0:85b3fd62ea1a	119
NYX	0:85b3fd62ea1a	120
NYX	0:85b3fd62ea1a	121	#if defined(SYSCFG_MEMRMP_UFB_MODE)
NYX	0:85b3fd62ea1a	122	/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
NYX	0:85b3fd62ea1a	123	* @{
NYX	0:85b3fd62ea1a	124	*/
NYX	0:85b3fd62ea1a	125	#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
NYX	0:85b3fd62ea1a	126	and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
NYX	0:85b3fd62ea1a	127	#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
NYX	0:85b3fd62ea1a	128	and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
NYX	0:85b3fd62ea1a	129	/**
NYX	0:85b3fd62ea1a	130	* @}
NYX	0:85b3fd62ea1a	131	*/
NYX	0:85b3fd62ea1a	132	#endif /* SYSCFG_MEMRMP_UFB_MODE */
NYX	0:85b3fd62ea1a	133	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
NYX	0:85b3fd62ea1a	134	* @{
NYX	0:85b3fd62ea1a	135	*/
NYX	0:85b3fd62ea1a	136	#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
NYX	0:85b3fd62ea1a	137	#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /!< Enable Fast Mode Plus on FMPI2C_SCL pin /
NYX	0:85b3fd62ea1a	138	#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /!< Enable Fast Mode Plus on FMPI2C_SDA pin/
NYX	0:85b3fd62ea1a	139	#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
NYX	0:85b3fd62ea1a	140	/**
NYX	0:85b3fd62ea1a	141	* @}
NYX	0:85b3fd62ea1a	142	*/
NYX	0:85b3fd62ea1a	143
NYX	0:85b3fd62ea1a	144	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
NYX	0:85b3fd62ea1a	145	* @{
NYX	0:85b3fd62ea1a	146	*/
NYX	0:85b3fd62ea1a	147	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /!< EXTI PORT A /
NYX	0:85b3fd62ea1a	148	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /!< EXTI PORT B /
NYX	0:85b3fd62ea1a	149	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /!< EXTI PORT C /
NYX	0:85b3fd62ea1a	150	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /!< EXTI PORT D /
NYX	0:85b3fd62ea1a	151	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /!< EXTI PORT E /
NYX	0:85b3fd62ea1a	152	#if defined(GPIOF)
NYX	0:85b3fd62ea1a	153	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /!< EXTI PORT F /
NYX	0:85b3fd62ea1a	154	#endif /* GPIOF */
NYX	0:85b3fd62ea1a	155	#if defined(GPIOG)
NYX	0:85b3fd62ea1a	156	#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /!< EXTI PORT G /
NYX	0:85b3fd62ea1a	157	#endif /* GPIOG */
NYX	0:85b3fd62ea1a	158	#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /!< EXTI PORT H /
NYX	0:85b3fd62ea1a	159	#if defined(GPIOI)
NYX	0:85b3fd62ea1a	160	#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /!< EXTI PORT I /
NYX	0:85b3fd62ea1a	161	#endif /* GPIOI */
NYX	0:85b3fd62ea1a	162	#if defined(GPIOJ)
NYX	0:85b3fd62ea1a	163	#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /!< EXTI PORT J /
NYX	0:85b3fd62ea1a	164	#endif /* GPIOJ */
NYX	0:85b3fd62ea1a	165	#if defined(GPIOK)
NYX	0:85b3fd62ea1a	166	#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /!< EXTI PORT k /
NYX	0:85b3fd62ea1a	167	#endif /* GPIOK */
NYX	0:85b3fd62ea1a	168	/**
NYX	0:85b3fd62ea1a	169	* @}
NYX	0:85b3fd62ea1a	170	*/
NYX	0:85b3fd62ea1a	171
NYX	0:85b3fd62ea1a	172	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
NYX	0:85b3fd62ea1a	173	* @{
NYX	0:85b3fd62ea1a	174	*/
NYX	0:85b3fd62ea1a	175	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 \| 0) /!< EXTI_POSITION_0 \| EXTICR[0] /
NYX	0:85b3fd62ea1a	176	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 \| 0) /!< EXTI_POSITION_4 \| EXTICR[0] /
NYX	0:85b3fd62ea1a	177	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 \| 0) /!< EXTI_POSITION_8 \| EXTICR[0] /
NYX	0:85b3fd62ea1a	178	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 \| 0) /!< EXTI_POSITION_12 \| EXTICR[0] /
NYX	0:85b3fd62ea1a	179	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 \| 1) /!< EXTI_POSITION_0 \| EXTICR[1] /
NYX	0:85b3fd62ea1a	180	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 \| 1) /!< EXTI_POSITION_4 \| EXTICR[1] /
NYX	0:85b3fd62ea1a	181	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 \| 1) /!< EXTI_POSITION_8 \| EXTICR[1] /
NYX	0:85b3fd62ea1a	182	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 \| 1) /!< EXTI_POSITION_12 \| EXTICR[1] /
NYX	0:85b3fd62ea1a	183	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 \| 2) /!< EXTI_POSITION_0 \| EXTICR[2] /
NYX	0:85b3fd62ea1a	184	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 \| 2) /!< EXTI_POSITION_4 \| EXTICR[2] /
NYX	0:85b3fd62ea1a	185	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 \| 2) /!< EXTI_POSITION_8 \| EXTICR[2] /
NYX	0:85b3fd62ea1a	186	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 \| 2) /!< EXTI_POSITION_12 \| EXTICR[2] /
NYX	0:85b3fd62ea1a	187	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 \| 3) /!< EXTI_POSITION_0 \| EXTICR[3] /
NYX	0:85b3fd62ea1a	188	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 \| 3) /!< EXTI_POSITION_4 \| EXTICR[3] /
NYX	0:85b3fd62ea1a	189	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 \| 3) /!< EXTI_POSITION_8 \| EXTICR[3] /
NYX	0:85b3fd62ea1a	190	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 \| 3) /!< EXTI_POSITION_12 \| EXTICR[3] /
NYX	0:85b3fd62ea1a	191	/**
NYX	0:85b3fd62ea1a	192	* @}
NYX	0:85b3fd62ea1a	193	*/
NYX	0:85b3fd62ea1a	194
NYX	0:85b3fd62ea1a	195	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
NYX	0:85b3fd62ea1a	196	* @{
NYX	0:85b3fd62ea1a	197	*/
NYX	0:85b3fd62ea1a	198	#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
NYX	0:85b3fd62ea1a	199	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
NYX	0:85b3fd62ea1a	200	with Break Input of TIM1/8 */
NYX	0:85b3fd62ea1a	201	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
NYX	0:85b3fd62ea1a	202	and also the PVDE and PLS bits of the Power Control Interface */
NYX	0:85b3fd62ea1a	203	#endif /* SYSCFG_CFGR2_CLL */
NYX	0:85b3fd62ea1a	204	/**
NYX	0:85b3fd62ea1a	205	* @}
NYX	0:85b3fd62ea1a	206	*/
NYX	0:85b3fd62ea1a	207
NYX	0:85b3fd62ea1a	208	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
NYX	0:85b3fd62ea1a	209	/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
NYX	0:85b3fd62ea1a	210	* @{
NYX	0:85b3fd62ea1a	211	*/
NYX	0:85b3fd62ea1a	212	#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	213	#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
NYX	0:85b3fd62ea1a	214	/**
NYX	0:85b3fd62ea1a	215	* @}
NYX	0:85b3fd62ea1a	216	*/
NYX	0:85b3fd62ea1a	217	/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN
NYX	0:85b3fd62ea1a	218	* @{
NYX	0:85b3fd62ea1a	219	*/
NYX	0:85b3fd62ea1a	220	#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
NYX	0:85b3fd62ea1a	221	#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
NYX	0:85b3fd62ea1a	222	/**
NYX	0:85b3fd62ea1a	223	* @}
NYX	0:85b3fd62ea1a	224	*/
NYX	0:85b3fd62ea1a	225	/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL
NYX	0:85b3fd62ea1a	226	* @{
NYX	0:85b3fd62ea1a	227	*/
NYX	0:85b3fd62ea1a	228	#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL
NYX	0:85b3fd62ea1a	229	#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL
NYX	0:85b3fd62ea1a	230
NYX	0:85b3fd62ea1a	231	#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) \| 0x00000000)
NYX	0:85b3fd62ea1a	232	#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM1D0SEL)
NYX	0:85b3fd62ea1a	233	#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) \| 0x00000000)
NYX	0:85b3fd62ea1a	234	#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM2D0SEL)
NYX	0:85b3fd62ea1a	235	/**
NYX	0:85b3fd62ea1a	236	* @}
NYX	0:85b3fd62ea1a	237	*/
NYX	0:85b3fd62ea1a	238	/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL
NYX	0:85b3fd62ea1a	239	* @{
NYX	0:85b3fd62ea1a	240	*/
NYX	0:85b3fd62ea1a	241	#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
NYX	0:85b3fd62ea1a	242	#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
NYX	0:85b3fd62ea1a	243
NYX	0:85b3fd62ea1a	244	#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) \| 0x00000000)
NYX	0:85b3fd62ea1a	245	#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM1D2SEL)
NYX	0:85b3fd62ea1a	246	#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) \| 0x00000000)
NYX	0:85b3fd62ea1a	247	#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM2D2SEL)
NYX	0:85b3fd62ea1a	248	/**
NYX	0:85b3fd62ea1a	249	* @}
NYX	0:85b3fd62ea1a	250	*/
NYX	0:85b3fd62ea1a	251	/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL
NYX	0:85b3fd62ea1a	252	* @{
NYX	0:85b3fd62ea1a	253	*/
NYX	0:85b3fd62ea1a	254	#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	255	#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
NYX	0:85b3fd62ea1a	256	/**
NYX	0:85b3fd62ea1a	257	* @}
NYX	0:85b3fd62ea1a	258	*/
NYX	0:85b3fd62ea1a	259	/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL
NYX	0:85b3fd62ea1a	260	* @{
NYX	0:85b3fd62ea1a	261	*/
NYX	0:85b3fd62ea1a	262	#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	263	#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
NYX	0:85b3fd62ea1a	264	/**
NYX	0:85b3fd62ea1a	265	* @}
NYX	0:85b3fd62ea1a	266	*/
NYX	0:85b3fd62ea1a	267	/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
NYX	0:85b3fd62ea1a	268	* @{
NYX	0:85b3fd62ea1a	269	*/
NYX	0:85b3fd62ea1a	270	#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	271	#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
NYX	0:85b3fd62ea1a	272	/**
NYX	0:85b3fd62ea1a	273	* @}
NYX	0:85b3fd62ea1a	274	*/
NYX	0:85b3fd62ea1a	275	/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
NYX	0:85b3fd62ea1a	276	* @{
NYX	0:85b3fd62ea1a	277	*/
NYX	0:85b3fd62ea1a	278	#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	279	#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
NYX	0:85b3fd62ea1a	280	/**
NYX	0:85b3fd62ea1a	281	* @}
NYX	0:85b3fd62ea1a	282	*/
NYX	0:85b3fd62ea1a	283
NYX	0:85b3fd62ea1a	284	/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
NYX	0:85b3fd62ea1a	285	* @{
NYX	0:85b3fd62ea1a	286	*/
NYX	0:85b3fd62ea1a	287	#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	288	#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
NYX	0:85b3fd62ea1a	289	/**
NYX	0:85b3fd62ea1a	290	* @}
NYX	0:85b3fd62ea1a	291	*/
NYX	0:85b3fd62ea1a	292	/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
NYX	0:85b3fd62ea1a	293	* @{
NYX	0:85b3fd62ea1a	294	*/
NYX	0:85b3fd62ea1a	295	#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	296	#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
NYX	0:85b3fd62ea1a	297	/**
NYX	0:85b3fd62ea1a	298	* @}
NYX	0:85b3fd62ea1a	299	*/
NYX	0:85b3fd62ea1a	300	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL
NYX	0:85b3fd62ea1a	301	* @{
NYX	0:85b3fd62ea1a	302	*/
NYX	0:85b3fd62ea1a	303	#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	304	#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
NYX	0:85b3fd62ea1a	305	/**
NYX	0:85b3fd62ea1a	306	* @}
NYX	0:85b3fd62ea1a	307	*/
NYX	0:85b3fd62ea1a	308	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL
NYX	0:85b3fd62ea1a	309	* @{
NYX	0:85b3fd62ea1a	310	*/
NYX	0:85b3fd62ea1a	311	#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	312	#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
NYX	0:85b3fd62ea1a	313	/**
NYX	0:85b3fd62ea1a	314	* @}
NYX	0:85b3fd62ea1a	315	*/
NYX	0:85b3fd62ea1a	316	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL
NYX	0:85b3fd62ea1a	317	* @{
NYX	0:85b3fd62ea1a	318	*/
NYX	0:85b3fd62ea1a	319	#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	320	#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
NYX	0:85b3fd62ea1a	321	/**
NYX	0:85b3fd62ea1a	322	* @}
NYX	0:85b3fd62ea1a	323	*/
NYX	0:85b3fd62ea1a	324	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL
NYX	0:85b3fd62ea1a	325	* @{
NYX	0:85b3fd62ea1a	326	*/
NYX	0:85b3fd62ea1a	327	#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	328	#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
NYX	0:85b3fd62ea1a	329	/**
NYX	0:85b3fd62ea1a	330	* @}
NYX	0:85b3fd62ea1a	331	*/
NYX	0:85b3fd62ea1a	332	/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
NYX	0:85b3fd62ea1a	333	* @{
NYX	0:85b3fd62ea1a	334	*/
NYX	0:85b3fd62ea1a	335	#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	336	#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
NYX	0:85b3fd62ea1a	337	/**
NYX	0:85b3fd62ea1a	338	* @}
NYX	0:85b3fd62ea1a	339	*/
NYX	0:85b3fd62ea1a	340	/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
NYX	0:85b3fd62ea1a	341	* @{
NYX	0:85b3fd62ea1a	342	*/
NYX	0:85b3fd62ea1a	343	#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
NYX	0:85b3fd62ea1a	344	#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
NYX	0:85b3fd62ea1a	345	/**
NYX	0:85b3fd62ea1a	346	* @}
NYX	0:85b3fd62ea1a	347	*/
NYX	0:85b3fd62ea1a	348	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
NYX	0:85b3fd62ea1a	349
NYX	0:85b3fd62ea1a	350	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
NYX	0:85b3fd62ea1a	351	* @{
NYX	0:85b3fd62ea1a	352	*/
NYX	0:85b3fd62ea1a	353	#define LL_DBGMCU_TRACE_NONE 0x00000000U /!< TRACE pins not assigned (default state) /
NYX	0:85b3fd62ea1a	354	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
NYX	0:85b3fd62ea1a	355	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
NYX	0:85b3fd62ea1a	356	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
NYX	0:85b3fd62ea1a	357	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
NYX	0:85b3fd62ea1a	358	/**
NYX	0:85b3fd62ea1a	359	* @}
NYX	0:85b3fd62ea1a	360	*/
NYX	0:85b3fd62ea1a	361
NYX	0:85b3fd62ea1a	362	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
NYX	0:85b3fd62ea1a	363	* @{
NYX	0:85b3fd62ea1a	364	*/
NYX	0:85b3fd62ea1a	365	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
NYX	0:85b3fd62ea1a	366	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	367	#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
NYX	0:85b3fd62ea1a	368	#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
NYX	0:85b3fd62ea1a	369	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	370	#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
NYX	0:85b3fd62ea1a	371	#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
NYX	0:85b3fd62ea1a	372	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /!< TIM4 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	373	#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
NYX	0:85b3fd62ea1a	374	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /!< TIM5 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	375	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
NYX	0:85b3fd62ea1a	376	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	377	#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
NYX	0:85b3fd62ea1a	378	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
NYX	0:85b3fd62ea1a	379	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	380	#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
NYX	0:85b3fd62ea1a	381	#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
NYX	0:85b3fd62ea1a	382	#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /!< TIM12 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	383	#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
NYX	0:85b3fd62ea1a	384	#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
NYX	0:85b3fd62ea1a	385	#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /!< TIM13 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	386	#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
NYX	0:85b3fd62ea1a	387	#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
NYX	0:85b3fd62ea1a	388	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	389	#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
NYX	0:85b3fd62ea1a	390	#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
NYX	0:85b3fd62ea1a	391	#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /!< LPTIM counter stopped when core is halted /
NYX	0:85b3fd62ea1a	392	#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
NYX	0:85b3fd62ea1a	393	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC counter stopped when core is halted /
NYX	0:85b3fd62ea1a	394	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
NYX	0:85b3fd62ea1a	395	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
NYX	0:85b3fd62ea1a	396	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
NYX	0:85b3fd62ea1a	397	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /!< I2C2 SMBUS timeout mode stopped when Core is halted /
NYX	0:85b3fd62ea1a	398	#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
NYX	0:85b3fd62ea1a	399	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /!< I2C3 SMBUS timeout mode stopped when Core is halted /
NYX	0:85b3fd62ea1a	400	#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
NYX	0:85b3fd62ea1a	401	#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
NYX	0:85b3fd62ea1a	402	#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /!< I2C4 SMBUS timeout mode stopped when Core is halted /
NYX	0:85b3fd62ea1a	403	#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
NYX	0:85b3fd62ea1a	404	#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
NYX	0:85b3fd62ea1a	405	#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /!< CAN1 debug stopped when Core is halted /
NYX	0:85b3fd62ea1a	406	#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
NYX	0:85b3fd62ea1a	407	#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
NYX	0:85b3fd62ea1a	408	#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /!< CAN2 debug stopped when Core is halted /
NYX	0:85b3fd62ea1a	409	#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
NYX	0:85b3fd62ea1a	410	#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
NYX	0:85b3fd62ea1a	411	#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /!< CAN3 debug stopped when Core is halted /
NYX	0:85b3fd62ea1a	412	#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
NYX	0:85b3fd62ea1a	413	/**
NYX	0:85b3fd62ea1a	414	* @}
NYX	0:85b3fd62ea1a	415	*/
NYX	0:85b3fd62ea1a	416
NYX	0:85b3fd62ea1a	417	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
NYX	0:85b3fd62ea1a	418	* @{
NYX	0:85b3fd62ea1a	419	*/
NYX	0:85b3fd62ea1a	420	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	421	#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
NYX	0:85b3fd62ea1a	422	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /!< TIM8 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	423	#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
NYX	0:85b3fd62ea1a	424	#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /!< TIM9 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	425	#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
NYX	0:85b3fd62ea1a	426	#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /!< TIM10 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	427	#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
NYX	0:85b3fd62ea1a	428	#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /!< TIM11 counter stopped when core is halted /
NYX	0:85b3fd62ea1a	429	/**
NYX	0:85b3fd62ea1a	430	* @}
NYX	0:85b3fd62ea1a	431	*/
NYX	0:85b3fd62ea1a	432
NYX	0:85b3fd62ea1a	433	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
NYX	0:85b3fd62ea1a	434	* @{
NYX	0:85b3fd62ea1a	435	*/
NYX	0:85b3fd62ea1a	436	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
NYX	0:85b3fd62ea1a	437	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
NYX	0:85b3fd62ea1a	438	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
NYX	0:85b3fd62ea1a	439	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
NYX	0:85b3fd62ea1a	440	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
NYX	0:85b3fd62ea1a	441	#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH five wait state /
NYX	0:85b3fd62ea1a	442	#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH six wait state /
NYX	0:85b3fd62ea1a	443	#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH seven wait states /
NYX	0:85b3fd62ea1a	444	#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /!< FLASH eight wait states /
NYX	0:85b3fd62ea1a	445	#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /!< FLASH nine wait states /
NYX	0:85b3fd62ea1a	446	#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /!< FLASH ten wait states /
NYX	0:85b3fd62ea1a	447	#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /!< FLASH eleven wait states /
NYX	0:85b3fd62ea1a	448	#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /!< FLASH twelve wait states /
NYX	0:85b3fd62ea1a	449	#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /!< FLASH thirteen wait states /
NYX	0:85b3fd62ea1a	450	#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /!< FLASH fourteen wait states /
NYX	0:85b3fd62ea1a	451	#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /!< FLASH fifteen wait states /
NYX	0:85b3fd62ea1a	452	/**
NYX	0:85b3fd62ea1a	453	* @}
NYX	0:85b3fd62ea1a	454	*/
NYX	0:85b3fd62ea1a	455
NYX	0:85b3fd62ea1a	456	/**
NYX	0:85b3fd62ea1a	457	* @}
NYX	0:85b3fd62ea1a	458	*/
NYX	0:85b3fd62ea1a	459
NYX	0:85b3fd62ea1a	460	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	461
NYX	0:85b3fd62ea1a	462	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	463	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
NYX	0:85b3fd62ea1a	464	* @{
NYX	0:85b3fd62ea1a	465	*/
NYX	0:85b3fd62ea1a	466
NYX	0:85b3fd62ea1a	467	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
NYX	0:85b3fd62ea1a	468	* @{
NYX	0:85b3fd62ea1a	469	*/
NYX	0:85b3fd62ea1a	470	/**
NYX	0:85b3fd62ea1a	471	* @brief Set memory mapping at address 0x00000000
NYX	0:85b3fd62ea1a	472	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
NYX	0:85b3fd62ea1a	473	* @param Memory This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	474	* @arg @ref LL_SYSCFG_REMAP_FLASH
NYX	0:85b3fd62ea1a	475	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
NYX	0:85b3fd62ea1a	476	* @arg @ref LL_SYSCFG_REMAP_SRAM
NYX	0:85b3fd62ea1a	477	* @arg @ref LL_SYSCFG_REMAP_FSMC (*)
NYX	0:85b3fd62ea1a	478	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
NYX	0:85b3fd62ea1a	479	* @retval None
NYX	0:85b3fd62ea1a	480	*/
NYX	0:85b3fd62ea1a	481	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
NYX	0:85b3fd62ea1a	482	{
NYX	0:85b3fd62ea1a	483	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
NYX	0:85b3fd62ea1a	484	}
NYX	0:85b3fd62ea1a	485
NYX	0:85b3fd62ea1a	486	/**
NYX	0:85b3fd62ea1a	487	* @brief Get memory mapping at address 0x00000000
NYX	0:85b3fd62ea1a	488	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
NYX	0:85b3fd62ea1a	489	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	490	* @arg @ref LL_SYSCFG_REMAP_FLASH
NYX	0:85b3fd62ea1a	491	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
NYX	0:85b3fd62ea1a	492	* @arg @ref LL_SYSCFG_REMAP_SRAM
NYX	0:85b3fd62ea1a	493	* @arg @ref LL_SYSCFG_REMAP_FSMC (*)
NYX	0:85b3fd62ea1a	494	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
NYX	0:85b3fd62ea1a	495	*/
NYX	0:85b3fd62ea1a	496	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
NYX	0:85b3fd62ea1a	497	{
NYX	0:85b3fd62ea1a	498	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
NYX	0:85b3fd62ea1a	499	}
NYX	0:85b3fd62ea1a	500
NYX	0:85b3fd62ea1a	501	#if defined(SYSCFG_MEMRMP_SWP_FMC)
NYX	0:85b3fd62ea1a	502	/**
NYX	0:85b3fd62ea1a	503	* @brief Enables the FMC Memory Mapping Swapping
NYX	0:85b3fd62ea1a	504	* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
NYX	0:85b3fd62ea1a	505	* @note SDRAM is accessible at 0x60000000 and NOR/RAM
NYX	0:85b3fd62ea1a	506	* is accessible at 0xC0000000
NYX	0:85b3fd62ea1a	507	* @retval None
NYX	0:85b3fd62ea1a	508	*/
NYX	0:85b3fd62ea1a	509	__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
NYX	0:85b3fd62ea1a	510	{
NYX	0:85b3fd62ea1a	511	SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
NYX	0:85b3fd62ea1a	512	}
NYX	0:85b3fd62ea1a	513
NYX	0:85b3fd62ea1a	514	/**
NYX	0:85b3fd62ea1a	515	* @brief Disables the FMC Memory Mapping Swapping
NYX	0:85b3fd62ea1a	516	* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
NYX	0:85b3fd62ea1a	517	* @note SDRAM is accessible at 0xC0000000 (default mapping)
NYX	0:85b3fd62ea1a	518	* and NOR/RAM is accessible at 0x60000000 (default mapping)
NYX	0:85b3fd62ea1a	519	* @retval None
NYX	0:85b3fd62ea1a	520	*/
NYX	0:85b3fd62ea1a	521	__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
NYX	0:85b3fd62ea1a	522	{
NYX	0:85b3fd62ea1a	523	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
NYX	0:85b3fd62ea1a	524	}
NYX	0:85b3fd62ea1a	525
NYX	0:85b3fd62ea1a	526	#endif /* SYSCFG_MEMRMP_SWP_FMC */
NYX	0:85b3fd62ea1a	527	/**
NYX	0:85b3fd62ea1a	528	* @brief Enables the Compensation cell Power Down
NYX	0:85b3fd62ea1a	529	* @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
NYX	0:85b3fd62ea1a	530	* @note The I/O compensation cell can be used only when the device supply
NYX	0:85b3fd62ea1a	531	* voltage ranges from 2.4 to 3.6 V
NYX	0:85b3fd62ea1a	532	* @retval None
NYX	0:85b3fd62ea1a	533	*/
NYX	0:85b3fd62ea1a	534	__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
NYX	0:85b3fd62ea1a	535	{
NYX	0:85b3fd62ea1a	536	SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
NYX	0:85b3fd62ea1a	537	}
NYX	0:85b3fd62ea1a	538
NYX	0:85b3fd62ea1a	539	/**
NYX	0:85b3fd62ea1a	540	* @brief Disables the Compensation cell Power Down
NYX	0:85b3fd62ea1a	541	* @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
NYX	0:85b3fd62ea1a	542	* @note The I/O compensation cell can be used only when the device supply
NYX	0:85b3fd62ea1a	543	* voltage ranges from 2.4 to 3.6 V
NYX	0:85b3fd62ea1a	544	* @retval None
NYX	0:85b3fd62ea1a	545	*/
NYX	0:85b3fd62ea1a	546	__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
NYX	0:85b3fd62ea1a	547	{
NYX	0:85b3fd62ea1a	548	CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
NYX	0:85b3fd62ea1a	549	}
NYX	0:85b3fd62ea1a	550
NYX	0:85b3fd62ea1a	551	/**
NYX	0:85b3fd62ea1a	552	* @brief Get Compensation Cell ready Flag
NYX	0:85b3fd62ea1a	553	* @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
NYX	0:85b3fd62ea1a	554	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	555	*/
NYX	0:85b3fd62ea1a	556	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
NYX	0:85b3fd62ea1a	557	{
NYX	0:85b3fd62ea1a	558	return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
NYX	0:85b3fd62ea1a	559	}
NYX	0:85b3fd62ea1a	560
NYX	0:85b3fd62ea1a	561	#if defined(SYSCFG_PMC_MII_RMII_SEL)
NYX	0:85b3fd62ea1a	562	/**
NYX	0:85b3fd62ea1a	563	* @brief Select Ethernet PHY interface
NYX	0:85b3fd62ea1a	564	* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
NYX	0:85b3fd62ea1a	565	* @param Interface This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	566	* @arg @ref LL_SYSCFG_PMC_ETHMII
NYX	0:85b3fd62ea1a	567	* @arg @ref LL_SYSCFG_PMC_ETHRMII
NYX	0:85b3fd62ea1a	568	* @retval None
NYX	0:85b3fd62ea1a	569	*/
NYX	0:85b3fd62ea1a	570	__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
NYX	0:85b3fd62ea1a	571	{
NYX	0:85b3fd62ea1a	572	MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
NYX	0:85b3fd62ea1a	573	}
NYX	0:85b3fd62ea1a	574
NYX	0:85b3fd62ea1a	575	/**
NYX	0:85b3fd62ea1a	576	* @brief Get Ethernet PHY interface
NYX	0:85b3fd62ea1a	577	* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
NYX	0:85b3fd62ea1a	578	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	579	* @arg @ref LL_SYSCFG_PMC_ETHMII
NYX	0:85b3fd62ea1a	580	* @arg @ref LL_SYSCFG_PMC_ETHRMII
NYX	0:85b3fd62ea1a	581	* @retval None
NYX	0:85b3fd62ea1a	582	*/
NYX	0:85b3fd62ea1a	583	__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
NYX	0:85b3fd62ea1a	584	{
NYX	0:85b3fd62ea1a	585	return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
NYX	0:85b3fd62ea1a	586	}
NYX	0:85b3fd62ea1a	587	#endif /* SYSCFG_PMC_MII_RMII_SEL */
NYX	0:85b3fd62ea1a	588
NYX	0:85b3fd62ea1a	589
NYX	0:85b3fd62ea1a	590
NYX	0:85b3fd62ea1a	591	#if defined(SYSCFG_MEMRMP_UFB_MODE)
NYX	0:85b3fd62ea1a	592	/**
NYX	0:85b3fd62ea1a	593	* @brief Select Flash bank mode (Bank flashed at 0x08000000)
NYX	0:85b3fd62ea1a	594	* @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode
NYX	0:85b3fd62ea1a	595	* @param Bank This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	596	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
NYX	0:85b3fd62ea1a	597	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
NYX	0:85b3fd62ea1a	598	* @retval None
NYX	0:85b3fd62ea1a	599	*/
NYX	0:85b3fd62ea1a	600	__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
NYX	0:85b3fd62ea1a	601	{
NYX	0:85b3fd62ea1a	602	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
NYX	0:85b3fd62ea1a	603	}
NYX	0:85b3fd62ea1a	604
NYX	0:85b3fd62ea1a	605	/**
NYX	0:85b3fd62ea1a	606	* @brief Get Flash bank mode (Bank flashed at 0x08000000)
NYX	0:85b3fd62ea1a	607	* @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode
NYX	0:85b3fd62ea1a	608	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	609	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
NYX	0:85b3fd62ea1a	610	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
NYX	0:85b3fd62ea1a	611	*/
NYX	0:85b3fd62ea1a	612	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
NYX	0:85b3fd62ea1a	613	{
NYX	0:85b3fd62ea1a	614	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
NYX	0:85b3fd62ea1a	615	}
NYX	0:85b3fd62ea1a	616	#endif /* SYSCFG_MEMRMP_UFB_MODE */
NYX	0:85b3fd62ea1a	617
NYX	0:85b3fd62ea1a	618	#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
NYX	0:85b3fd62ea1a	619	/**
NYX	0:85b3fd62ea1a	620	* @brief Enable the I2C fast mode plus driving capability.
NYX	0:85b3fd62ea1a	621	* @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n
NYX	0:85b3fd62ea1a	622	* SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus
NYX	0:85b3fd62ea1a	623	* @param ConfigFastModePlus This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	624	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
NYX	0:85b3fd62ea1a	625	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
NYX	0:85b3fd62ea1a	626	* (*) value not defined in all devices
NYX	0:85b3fd62ea1a	627	* @retval None
NYX	0:85b3fd62ea1a	628	*/
NYX	0:85b3fd62ea1a	629	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
NYX	0:85b3fd62ea1a	630	{
NYX	0:85b3fd62ea1a	631	SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
NYX	0:85b3fd62ea1a	632	}
NYX	0:85b3fd62ea1a	633
NYX	0:85b3fd62ea1a	634	/**
NYX	0:85b3fd62ea1a	635	* @brief Disable the I2C fast mode plus driving capability.
NYX	0:85b3fd62ea1a	636	* @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n
NYX	0:85b3fd62ea1a	637	* SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n
NYX	0:85b3fd62ea1a	638	* @param ConfigFastModePlus This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	639	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
NYX	0:85b3fd62ea1a	640	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
NYX	0:85b3fd62ea1a	641	* (*) value not defined in all devices
NYX	0:85b3fd62ea1a	642	* @retval None
NYX	0:85b3fd62ea1a	643	*/
NYX	0:85b3fd62ea1a	644	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
NYX	0:85b3fd62ea1a	645	{
NYX	0:85b3fd62ea1a	646	CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
NYX	0:85b3fd62ea1a	647	}
NYX	0:85b3fd62ea1a	648	#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
NYX	0:85b3fd62ea1a	649
NYX	0:85b3fd62ea1a	650	/**
NYX	0:85b3fd62ea1a	651	* @brief Configure source input for the EXTI external interrupt.
NYX	0:85b3fd62ea1a	652	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
NYX	0:85b3fd62ea1a	653	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
NYX	0:85b3fd62ea1a	654	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
NYX	0:85b3fd62ea1a	655	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
NYX	0:85b3fd62ea1a	656	* @param Port This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	657	* @arg @ref LL_SYSCFG_EXTI_PORTA
NYX	0:85b3fd62ea1a	658	* @arg @ref LL_SYSCFG_EXTI_PORTB
NYX	0:85b3fd62ea1a	659	* @arg @ref LL_SYSCFG_EXTI_PORTC
NYX	0:85b3fd62ea1a	660	* @arg @ref LL_SYSCFG_EXTI_PORTD
NYX	0:85b3fd62ea1a	661	* @arg @ref LL_SYSCFG_EXTI_PORTE
NYX	0:85b3fd62ea1a	662	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
NYX	0:85b3fd62ea1a	663	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
NYX	0:85b3fd62ea1a	664	* @arg @ref LL_SYSCFG_EXTI_PORTH
NYX	0:85b3fd62ea1a	665	*
NYX	0:85b3fd62ea1a	666	* (*) value not defined in all devices
NYX	0:85b3fd62ea1a	667	* @param Line This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	668	* @arg @ref LL_SYSCFG_EXTI_LINE0
NYX	0:85b3fd62ea1a	669	* @arg @ref LL_SYSCFG_EXTI_LINE1
NYX	0:85b3fd62ea1a	670	* @arg @ref LL_SYSCFG_EXTI_LINE2
NYX	0:85b3fd62ea1a	671	* @arg @ref LL_SYSCFG_EXTI_LINE3
NYX	0:85b3fd62ea1a	672	* @arg @ref LL_SYSCFG_EXTI_LINE4
NYX	0:85b3fd62ea1a	673	* @arg @ref LL_SYSCFG_EXTI_LINE5
NYX	0:85b3fd62ea1a	674	* @arg @ref LL_SYSCFG_EXTI_LINE6
NYX	0:85b3fd62ea1a	675	* @arg @ref LL_SYSCFG_EXTI_LINE7
NYX	0:85b3fd62ea1a	676	* @arg @ref LL_SYSCFG_EXTI_LINE8
NYX	0:85b3fd62ea1a	677	* @arg @ref LL_SYSCFG_EXTI_LINE9
NYX	0:85b3fd62ea1a	678	* @arg @ref LL_SYSCFG_EXTI_LINE10
NYX	0:85b3fd62ea1a	679	* @arg @ref LL_SYSCFG_EXTI_LINE11
NYX	0:85b3fd62ea1a	680	* @arg @ref LL_SYSCFG_EXTI_LINE12
NYX	0:85b3fd62ea1a	681	* @arg @ref LL_SYSCFG_EXTI_LINE13
NYX	0:85b3fd62ea1a	682	* @arg @ref LL_SYSCFG_EXTI_LINE14
NYX	0:85b3fd62ea1a	683	* @arg @ref LL_SYSCFG_EXTI_LINE15
NYX	0:85b3fd62ea1a	684	* @retval None
NYX	0:85b3fd62ea1a	685	*/
NYX	0:85b3fd62ea1a	686	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
NYX	0:85b3fd62ea1a	687	{
NYX	0:85b3fd62ea1a	688	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
NYX	0:85b3fd62ea1a	689	}
NYX	0:85b3fd62ea1a	690
NYX	0:85b3fd62ea1a	691	/**
NYX	0:85b3fd62ea1a	692	* @brief Get the configured defined for specific EXTI Line
NYX	0:85b3fd62ea1a	693	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
NYX	0:85b3fd62ea1a	694	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
NYX	0:85b3fd62ea1a	695	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
NYX	0:85b3fd62ea1a	696	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
NYX	0:85b3fd62ea1a	697	* @param Line This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	698	* @arg @ref LL_SYSCFG_EXTI_LINE0
NYX	0:85b3fd62ea1a	699	* @arg @ref LL_SYSCFG_EXTI_LINE1
NYX	0:85b3fd62ea1a	700	* @arg @ref LL_SYSCFG_EXTI_LINE2
NYX	0:85b3fd62ea1a	701	* @arg @ref LL_SYSCFG_EXTI_LINE3
NYX	0:85b3fd62ea1a	702	* @arg @ref LL_SYSCFG_EXTI_LINE4
NYX	0:85b3fd62ea1a	703	* @arg @ref LL_SYSCFG_EXTI_LINE5
NYX	0:85b3fd62ea1a	704	* @arg @ref LL_SYSCFG_EXTI_LINE6
NYX	0:85b3fd62ea1a	705	* @arg @ref LL_SYSCFG_EXTI_LINE7
NYX	0:85b3fd62ea1a	706	* @arg @ref LL_SYSCFG_EXTI_LINE8
NYX	0:85b3fd62ea1a	707	* @arg @ref LL_SYSCFG_EXTI_LINE9
NYX	0:85b3fd62ea1a	708	* @arg @ref LL_SYSCFG_EXTI_LINE10
NYX	0:85b3fd62ea1a	709	* @arg @ref LL_SYSCFG_EXTI_LINE11
NYX	0:85b3fd62ea1a	710	* @arg @ref LL_SYSCFG_EXTI_LINE12
NYX	0:85b3fd62ea1a	711	* @arg @ref LL_SYSCFG_EXTI_LINE13
NYX	0:85b3fd62ea1a	712	* @arg @ref LL_SYSCFG_EXTI_LINE14
NYX	0:85b3fd62ea1a	713	* @arg @ref LL_SYSCFG_EXTI_LINE15
NYX	0:85b3fd62ea1a	714	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	715	* @arg @ref LL_SYSCFG_EXTI_PORTA
NYX	0:85b3fd62ea1a	716	* @arg @ref LL_SYSCFG_EXTI_PORTB
NYX	0:85b3fd62ea1a	717	* @arg @ref LL_SYSCFG_EXTI_PORTC
NYX	0:85b3fd62ea1a	718	* @arg @ref LL_SYSCFG_EXTI_PORTD
NYX	0:85b3fd62ea1a	719	* @arg @ref LL_SYSCFG_EXTI_PORTE
NYX	0:85b3fd62ea1a	720	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
NYX	0:85b3fd62ea1a	721	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
NYX	0:85b3fd62ea1a	722	* @arg @ref LL_SYSCFG_EXTI_PORTH
NYX	0:85b3fd62ea1a	723	* (*) value not defined in all devices
NYX	0:85b3fd62ea1a	724	*/
NYX	0:85b3fd62ea1a	725	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
NYX	0:85b3fd62ea1a	726	{
NYX	0:85b3fd62ea1a	727	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
NYX	0:85b3fd62ea1a	728	}
NYX	0:85b3fd62ea1a	729
NYX	0:85b3fd62ea1a	730	#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
NYX	0:85b3fd62ea1a	731	/**
NYX	0:85b3fd62ea1a	732	* @brief Set connections to TIM1/8 break inputs
NYX	0:85b3fd62ea1a	733	* @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
NYX	0:85b3fd62ea1a	734	* SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
NYX	0:85b3fd62ea1a	735	* @param Break This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	736	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
NYX	0:85b3fd62ea1a	737	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
NYX	0:85b3fd62ea1a	738	* @retval None
NYX	0:85b3fd62ea1a	739	*/
NYX	0:85b3fd62ea1a	740	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
NYX	0:85b3fd62ea1a	741	{
NYX	0:85b3fd62ea1a	742	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
NYX	0:85b3fd62ea1a	743	}
NYX	0:85b3fd62ea1a	744
NYX	0:85b3fd62ea1a	745	/**
NYX	0:85b3fd62ea1a	746	* @brief Get connections to TIM1/8 Break inputs
NYX	0:85b3fd62ea1a	747	* @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
NYX	0:85b3fd62ea1a	748	* SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
NYX	0:85b3fd62ea1a	749	* @retval Returned value can be can be a combination of the following values:
NYX	0:85b3fd62ea1a	750	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
NYX	0:85b3fd62ea1a	751	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
NYX	0:85b3fd62ea1a	752	*/
NYX	0:85b3fd62ea1a	753	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
NYX	0:85b3fd62ea1a	754	{
NYX	0:85b3fd62ea1a	755	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
NYX	0:85b3fd62ea1a	756	}
NYX	0:85b3fd62ea1a	757	#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
NYX	0:85b3fd62ea1a	758	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
NYX	0:85b3fd62ea1a	759	/**
NYX	0:85b3fd62ea1a	760	* @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
NYX	0:85b3fd62ea1a	761	* @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
NYX	0:85b3fd62ea1a	762	* @param ClockSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	763	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
NYX	0:85b3fd62ea1a	764	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
NYX	0:85b3fd62ea1a	765	* @retval None
NYX	0:85b3fd62ea1a	766	*/
NYX	0:85b3fd62ea1a	767	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
NYX	0:85b3fd62ea1a	768	{
NYX	0:85b3fd62ea1a	769	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
NYX	0:85b3fd62ea1a	770	}
NYX	0:85b3fd62ea1a	771	/**
NYX	0:85b3fd62ea1a	772	* @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
NYX	0:85b3fd62ea1a	773	* @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
NYX	0:85b3fd62ea1a	774	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	775	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
NYX	0:85b3fd62ea1a	776	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
NYX	0:85b3fd62ea1a	777	* @retval None
NYX	0:85b3fd62ea1a	778	*/
NYX	0:85b3fd62ea1a	779	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
NYX	0:85b3fd62ea1a	780	{
NYX	0:85b3fd62ea1a	781	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
NYX	0:85b3fd62ea1a	782	}
NYX	0:85b3fd62ea1a	783	/**
NYX	0:85b3fd62ea1a	784	* @brief Enables the DFSDM1 or DFSDM2 Delay clock
NYX	0:85b3fd62ea1a	785	* @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock
NYX	0:85b3fd62ea1a	786	* @param MCHDLY This paramater can be one of the following values
NYX	0:85b3fd62ea1a	787	* @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
NYX	0:85b3fd62ea1a	788	* @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
NYX	0:85b3fd62ea1a	789	* @retval None
NYX	0:85b3fd62ea1a	790	*/
NYX	0:85b3fd62ea1a	791	__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
NYX	0:85b3fd62ea1a	792	{
NYX	0:85b3fd62ea1a	793	SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
NYX	0:85b3fd62ea1a	794	}
NYX	0:85b3fd62ea1a	795
NYX	0:85b3fd62ea1a	796	/**
NYX	0:85b3fd62ea1a	797	* @brief Disables the DFSDM1 or the DFSDM2 Delay clock
NYX	0:85b3fd62ea1a	798	* @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock
NYX	0:85b3fd62ea1a	799	* @param MCHDLY This paramater can be one of the following values
NYX	0:85b3fd62ea1a	800	* @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
NYX	0:85b3fd62ea1a	801	* @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
NYX	0:85b3fd62ea1a	802	* @retval None
NYX	0:85b3fd62ea1a	803	*/
NYX	0:85b3fd62ea1a	804	__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
NYX	0:85b3fd62ea1a	805	{
NYX	0:85b3fd62ea1a	806	CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
NYX	0:85b3fd62ea1a	807	}
NYX	0:85b3fd62ea1a	808
NYX	0:85b3fd62ea1a	809	/**
NYX	0:85b3fd62ea1a	810	* @brief Select the source for DFSDM1 or DFSDM2 DatIn0
NYX	0:85b3fd62ea1a	811	* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source
NYX	0:85b3fd62ea1a	812	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	813	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
NYX	0:85b3fd62ea1a	814	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
NYX	0:85b3fd62ea1a	815	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
NYX	0:85b3fd62ea1a	816	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
NYX	0:85b3fd62ea1a	817	* @retval None
NYX	0:85b3fd62ea1a	818	*/
NYX	0:85b3fd62ea1a	819	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
NYX	0:85b3fd62ea1a	820	{
NYX	0:85b3fd62ea1a	821	MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
NYX	0:85b3fd62ea1a	822	}
NYX	0:85b3fd62ea1a	823	/**
NYX	0:85b3fd62ea1a	824	* @brief Get the source for DFSDM1 or DFSDM2 DatIn0.
NYX	0:85b3fd62ea1a	825	* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source
NYX	0:85b3fd62ea1a	826	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	827	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0
NYX	0:85b3fd62ea1a	828	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0
NYX	0:85b3fd62ea1a	829	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	830	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
NYX	0:85b3fd62ea1a	831	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
NYX	0:85b3fd62ea1a	832	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
NYX	0:85b3fd62ea1a	833	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
NYX	0:85b3fd62ea1a	834	* @retval None
NYX	0:85b3fd62ea1a	835	*/
NYX	0:85b3fd62ea1a	836	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
NYX	0:85b3fd62ea1a	837	{
NYX	0:85b3fd62ea1a	838	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
NYX	0:85b3fd62ea1a	839	}
NYX	0:85b3fd62ea1a	840	/**
NYX	0:85b3fd62ea1a	841	* @brief Select the source for DFSDM1 or DFSDM2 DatIn2
NYX	0:85b3fd62ea1a	842	* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source
NYX	0:85b3fd62ea1a	843	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	844	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
NYX	0:85b3fd62ea1a	845	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
NYX	0:85b3fd62ea1a	846	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
NYX	0:85b3fd62ea1a	847	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
NYX	0:85b3fd62ea1a	848	* @retval None
NYX	0:85b3fd62ea1a	849	*/
NYX	0:85b3fd62ea1a	850	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
NYX	0:85b3fd62ea1a	851	{
NYX	0:85b3fd62ea1a	852	MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
NYX	0:85b3fd62ea1a	853	}
NYX	0:85b3fd62ea1a	854	/**
NYX	0:85b3fd62ea1a	855	* @brief Get the source for DFSDM1 or DFSDM2 DatIn2.
NYX	0:85b3fd62ea1a	856	* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source
NYX	0:85b3fd62ea1a	857	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	858	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2
NYX	0:85b3fd62ea1a	859	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2
NYX	0:85b3fd62ea1a	860	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	861	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
NYX	0:85b3fd62ea1a	862	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
NYX	0:85b3fd62ea1a	863	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
NYX	0:85b3fd62ea1a	864	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
NYX	0:85b3fd62ea1a	865	* @retval None
NYX	0:85b3fd62ea1a	866	*/
NYX	0:85b3fd62ea1a	867	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
NYX	0:85b3fd62ea1a	868	{
NYX	0:85b3fd62ea1a	869	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
NYX	0:85b3fd62ea1a	870	}
NYX	0:85b3fd62ea1a	871
NYX	0:85b3fd62ea1a	872	/**
NYX	0:85b3fd62ea1a	873	* @brief Select the distribution of the bitsream lock gated by TIM4 OC2
NYX	0:85b3fd62ea1a	874	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
NYX	0:85b3fd62ea1a	875	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	876	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
NYX	0:85b3fd62ea1a	877	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
NYX	0:85b3fd62ea1a	878	* @retval None
NYX	0:85b3fd62ea1a	879	*/
NYX	0:85b3fd62ea1a	880	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
NYX	0:85b3fd62ea1a	881	{
NYX	0:85b3fd62ea1a	882	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
NYX	0:85b3fd62ea1a	883	}
NYX	0:85b3fd62ea1a	884	/**
NYX	0:85b3fd62ea1a	885	* @brief Get the distribution of the bitsream lock gated by TIM4 OC2
NYX	0:85b3fd62ea1a	886	* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
NYX	0:85b3fd62ea1a	887	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	888	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
NYX	0:85b3fd62ea1a	889	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
NYX	0:85b3fd62ea1a	890	* @retval None
NYX	0:85b3fd62ea1a	891	*/
NYX	0:85b3fd62ea1a	892	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
NYX	0:85b3fd62ea1a	893	{
NYX	0:85b3fd62ea1a	894	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
NYX	0:85b3fd62ea1a	895	}
NYX	0:85b3fd62ea1a	896
NYX	0:85b3fd62ea1a	897	/**
NYX	0:85b3fd62ea1a	898	* @brief Select the distribution of the bitsream lock gated by TIM4 OC1
NYX	0:85b3fd62ea1a	899	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
NYX	0:85b3fd62ea1a	900	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	901	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
NYX	0:85b3fd62ea1a	902	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
NYX	0:85b3fd62ea1a	903	* @retval None
NYX	0:85b3fd62ea1a	904	*/
NYX	0:85b3fd62ea1a	905	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
NYX	0:85b3fd62ea1a	906	{
NYX	0:85b3fd62ea1a	907	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
NYX	0:85b3fd62ea1a	908	}
NYX	0:85b3fd62ea1a	909	/**
NYX	0:85b3fd62ea1a	910	* @brief Get the distribution of the bitsream lock gated by TIM4 OC1
NYX	0:85b3fd62ea1a	911	* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
NYX	0:85b3fd62ea1a	912	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	913	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
NYX	0:85b3fd62ea1a	914	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
NYX	0:85b3fd62ea1a	915	* @retval None
NYX	0:85b3fd62ea1a	916	*/
NYX	0:85b3fd62ea1a	917	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
NYX	0:85b3fd62ea1a	918	{
NYX	0:85b3fd62ea1a	919	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
NYX	0:85b3fd62ea1a	920	}
NYX	0:85b3fd62ea1a	921
NYX	0:85b3fd62ea1a	922	/**
NYX	0:85b3fd62ea1a	923	* @brief Select the DFSDM1 Clock In
NYX	0:85b3fd62ea1a	924	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection
NYX	0:85b3fd62ea1a	925	* @param ClockSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	926	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
NYX	0:85b3fd62ea1a	927	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
NYX	0:85b3fd62ea1a	928	* @retval None
NYX	0:85b3fd62ea1a	929	*/
NYX	0:85b3fd62ea1a	930	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
NYX	0:85b3fd62ea1a	931	{
NYX	0:85b3fd62ea1a	932	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
NYX	0:85b3fd62ea1a	933	}
NYX	0:85b3fd62ea1a	934	/**
NYX	0:85b3fd62ea1a	935	* @brief GET the DFSDM1 Clock In
NYX	0:85b3fd62ea1a	936	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection
NYX	0:85b3fd62ea1a	937	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	938	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
NYX	0:85b3fd62ea1a	939	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
NYX	0:85b3fd62ea1a	940	* @retval None
NYX	0:85b3fd62ea1a	941	*/
NYX	0:85b3fd62ea1a	942	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
NYX	0:85b3fd62ea1a	943	{
NYX	0:85b3fd62ea1a	944	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
NYX	0:85b3fd62ea1a	945	}
NYX	0:85b3fd62ea1a	946
NYX	0:85b3fd62ea1a	947	/**
NYX	0:85b3fd62ea1a	948	* @brief Select the DFSDM1 Clock Out
NYX	0:85b3fd62ea1a	949	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
NYX	0:85b3fd62ea1a	950	* @param ClockSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	951	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
NYX	0:85b3fd62ea1a	952	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
NYX	0:85b3fd62ea1a	953	* @retval None
NYX	0:85b3fd62ea1a	954	*/
NYX	0:85b3fd62ea1a	955	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
NYX	0:85b3fd62ea1a	956	{
NYX	0:85b3fd62ea1a	957	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
NYX	0:85b3fd62ea1a	958	}
NYX	0:85b3fd62ea1a	959	/**
NYX	0:85b3fd62ea1a	960	* @brief GET the DFSDM1 Clock Out
NYX	0:85b3fd62ea1a	961	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
NYX	0:85b3fd62ea1a	962	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	963	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
NYX	0:85b3fd62ea1a	964	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
NYX	0:85b3fd62ea1a	965	* @retval None
NYX	0:85b3fd62ea1a	966	*/
NYX	0:85b3fd62ea1a	967	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
NYX	0:85b3fd62ea1a	968	{
NYX	0:85b3fd62ea1a	969	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
NYX	0:85b3fd62ea1a	970	}
NYX	0:85b3fd62ea1a	971
NYX	0:85b3fd62ea1a	972	/**
NYX	0:85b3fd62ea1a	973	* @brief Enables the DFSDM2 Delay clock
NYX	0:85b3fd62ea1a	974	* @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock
NYX	0:85b3fd62ea1a	975	* @retval None
NYX	0:85b3fd62ea1a	976	*/
NYX	0:85b3fd62ea1a	977	__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
NYX	0:85b3fd62ea1a	978	{
NYX	0:85b3fd62ea1a	979	SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
NYX	0:85b3fd62ea1a	980	}
NYX	0:85b3fd62ea1a	981
NYX	0:85b3fd62ea1a	982	/**
NYX	0:85b3fd62ea1a	983	* @brief Disables the DFSDM2 Delay clock
NYX	0:85b3fd62ea1a	984	* @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock
NYX	0:85b3fd62ea1a	985	* @retval None
NYX	0:85b3fd62ea1a	986	*/
NYX	0:85b3fd62ea1a	987	__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
NYX	0:85b3fd62ea1a	988	{
NYX	0:85b3fd62ea1a	989	CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
NYX	0:85b3fd62ea1a	990	}
NYX	0:85b3fd62ea1a	991	/**
NYX	0:85b3fd62ea1a	992	* @brief Select the source for DFSDM2 DatIn0
NYX	0:85b3fd62ea1a	993	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source
NYX	0:85b3fd62ea1a	994	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	995	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
NYX	0:85b3fd62ea1a	996	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
NYX	0:85b3fd62ea1a	997	* @retval None
NYX	0:85b3fd62ea1a	998	*/
NYX	0:85b3fd62ea1a	999	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
NYX	0:85b3fd62ea1a	1000	{
NYX	0:85b3fd62ea1a	1001	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
NYX	0:85b3fd62ea1a	1002	}
NYX	0:85b3fd62ea1a	1003	/**
NYX	0:85b3fd62ea1a	1004	* @brief Get the source for DFSDM2 DatIn0.
NYX	0:85b3fd62ea1a	1005	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source
NYX	0:85b3fd62ea1a	1006	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1007	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
NYX	0:85b3fd62ea1a	1008	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
NYX	0:85b3fd62ea1a	1009	* @retval None
NYX	0:85b3fd62ea1a	1010	*/
NYX	0:85b3fd62ea1a	1011	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
NYX	0:85b3fd62ea1a	1012	{
NYX	0:85b3fd62ea1a	1013	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
NYX	0:85b3fd62ea1a	1014	}
NYX	0:85b3fd62ea1a	1015
NYX	0:85b3fd62ea1a	1016	/**
NYX	0:85b3fd62ea1a	1017	* @brief Select the source for DFSDM2 DatIn2
NYX	0:85b3fd62ea1a	1018	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source
NYX	0:85b3fd62ea1a	1019	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1020	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
NYX	0:85b3fd62ea1a	1021	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
NYX	0:85b3fd62ea1a	1022	* @retval None
NYX	0:85b3fd62ea1a	1023	*/
NYX	0:85b3fd62ea1a	1024	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
NYX	0:85b3fd62ea1a	1025	{
NYX	0:85b3fd62ea1a	1026	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
NYX	0:85b3fd62ea1a	1027	}
NYX	0:85b3fd62ea1a	1028	/**
NYX	0:85b3fd62ea1a	1029	* @brief Get the source for DFSDM2 DatIn2.
NYX	0:85b3fd62ea1a	1030	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source
NYX	0:85b3fd62ea1a	1031	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1032	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
NYX	0:85b3fd62ea1a	1033	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
NYX	0:85b3fd62ea1a	1034	* @retval None
NYX	0:85b3fd62ea1a	1035	*/
NYX	0:85b3fd62ea1a	1036	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
NYX	0:85b3fd62ea1a	1037	{
NYX	0:85b3fd62ea1a	1038	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
NYX	0:85b3fd62ea1a	1039	}
NYX	0:85b3fd62ea1a	1040
NYX	0:85b3fd62ea1a	1041	/**
NYX	0:85b3fd62ea1a	1042	* @brief Select the source for DFSDM2 DatIn4
NYX	0:85b3fd62ea1a	1043	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source
NYX	0:85b3fd62ea1a	1044	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1045	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
NYX	0:85b3fd62ea1a	1046	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
NYX	0:85b3fd62ea1a	1047	* @retval None
NYX	0:85b3fd62ea1a	1048	*/
NYX	0:85b3fd62ea1a	1049	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
NYX	0:85b3fd62ea1a	1050	{
NYX	0:85b3fd62ea1a	1051	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
NYX	0:85b3fd62ea1a	1052	}
NYX	0:85b3fd62ea1a	1053	/**
NYX	0:85b3fd62ea1a	1054	* @brief Get the source for DFSDM2 DatIn4.
NYX	0:85b3fd62ea1a	1055	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source
NYX	0:85b3fd62ea1a	1056	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1057	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
NYX	0:85b3fd62ea1a	1058	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
NYX	0:85b3fd62ea1a	1059	* @retval None
NYX	0:85b3fd62ea1a	1060	*/
NYX	0:85b3fd62ea1a	1061	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
NYX	0:85b3fd62ea1a	1062	{
NYX	0:85b3fd62ea1a	1063	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
NYX	0:85b3fd62ea1a	1064	}
NYX	0:85b3fd62ea1a	1065
NYX	0:85b3fd62ea1a	1066	/**
NYX	0:85b3fd62ea1a	1067	* @brief Select the source for DFSDM2 DatIn6
NYX	0:85b3fd62ea1a	1068	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source
NYX	0:85b3fd62ea1a	1069	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1070	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
NYX	0:85b3fd62ea1a	1071	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
NYX	0:85b3fd62ea1a	1072	* @retval None
NYX	0:85b3fd62ea1a	1073	*/
NYX	0:85b3fd62ea1a	1074	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
NYX	0:85b3fd62ea1a	1075	{
NYX	0:85b3fd62ea1a	1076	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
NYX	0:85b3fd62ea1a	1077	}
NYX	0:85b3fd62ea1a	1078	/**
NYX	0:85b3fd62ea1a	1079	* @brief Get the source for DFSDM2 DatIn6.
NYX	0:85b3fd62ea1a	1080	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source
NYX	0:85b3fd62ea1a	1081	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1082	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
NYX	0:85b3fd62ea1a	1083	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
NYX	0:85b3fd62ea1a	1084	* @retval None
NYX	0:85b3fd62ea1a	1085	*/
NYX	0:85b3fd62ea1a	1086	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
NYX	0:85b3fd62ea1a	1087	{
NYX	0:85b3fd62ea1a	1088	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
NYX	0:85b3fd62ea1a	1089	}
NYX	0:85b3fd62ea1a	1090
NYX	0:85b3fd62ea1a	1091	/**
NYX	0:85b3fd62ea1a	1092	* @brief Select the distribution of the bitsream lock gated by TIM3 OC4
NYX	0:85b3fd62ea1a	1093	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
NYX	0:85b3fd62ea1a	1094	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1095	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
NYX	0:85b3fd62ea1a	1096	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
NYX	0:85b3fd62ea1a	1097	* @retval None
NYX	0:85b3fd62ea1a	1098	*/
NYX	0:85b3fd62ea1a	1099	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
NYX	0:85b3fd62ea1a	1100	{
NYX	0:85b3fd62ea1a	1101	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
NYX	0:85b3fd62ea1a	1102	}
NYX	0:85b3fd62ea1a	1103	/**
NYX	0:85b3fd62ea1a	1104	* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
NYX	0:85b3fd62ea1a	1105	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
NYX	0:85b3fd62ea1a	1106	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1107	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
NYX	0:85b3fd62ea1a	1108	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
NYX	0:85b3fd62ea1a	1109	* @retval None
NYX	0:85b3fd62ea1a	1110	*/
NYX	0:85b3fd62ea1a	1111	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
NYX	0:85b3fd62ea1a	1112	{
NYX	0:85b3fd62ea1a	1113	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
NYX	0:85b3fd62ea1a	1114	}
NYX	0:85b3fd62ea1a	1115
NYX	0:85b3fd62ea1a	1116	/**
NYX	0:85b3fd62ea1a	1117	* @brief Select the distribution of the bitsream lock gated by TIM3 OC3
NYX	0:85b3fd62ea1a	1118	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
NYX	0:85b3fd62ea1a	1119	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1120	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
NYX	0:85b3fd62ea1a	1121	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
NYX	0:85b3fd62ea1a	1122	* @retval None
NYX	0:85b3fd62ea1a	1123	*/
NYX	0:85b3fd62ea1a	1124	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
NYX	0:85b3fd62ea1a	1125	{
NYX	0:85b3fd62ea1a	1126	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
NYX	0:85b3fd62ea1a	1127	}
NYX	0:85b3fd62ea1a	1128	/**
NYX	0:85b3fd62ea1a	1129	* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
NYX	0:85b3fd62ea1a	1130	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
NYX	0:85b3fd62ea1a	1131	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1132	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
NYX	0:85b3fd62ea1a	1133	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
NYX	0:85b3fd62ea1a	1134	* @retval None
NYX	0:85b3fd62ea1a	1135	*/
NYX	0:85b3fd62ea1a	1136	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
NYX	0:85b3fd62ea1a	1137	{
NYX	0:85b3fd62ea1a	1138	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
NYX	0:85b3fd62ea1a	1139	}
NYX	0:85b3fd62ea1a	1140
NYX	0:85b3fd62ea1a	1141	/**
NYX	0:85b3fd62ea1a	1142	* @brief Select the distribution of the bitsream lock gated by TIM3 OC2
NYX	0:85b3fd62ea1a	1143	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
NYX	0:85b3fd62ea1a	1144	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1145	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
NYX	0:85b3fd62ea1a	1146	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
NYX	0:85b3fd62ea1a	1147	* @retval None
NYX	0:85b3fd62ea1a	1148	*/
NYX	0:85b3fd62ea1a	1149	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
NYX	0:85b3fd62ea1a	1150	{
NYX	0:85b3fd62ea1a	1151	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
NYX	0:85b3fd62ea1a	1152	}
NYX	0:85b3fd62ea1a	1153	/**
NYX	0:85b3fd62ea1a	1154	* @brief Get the distribution of the bitsream lock gated by TIM3 OC2
NYX	0:85b3fd62ea1a	1155	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
NYX	0:85b3fd62ea1a	1156	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1157	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
NYX	0:85b3fd62ea1a	1158	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
NYX	0:85b3fd62ea1a	1159	* @retval None
NYX	0:85b3fd62ea1a	1160	*/
NYX	0:85b3fd62ea1a	1161	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
NYX	0:85b3fd62ea1a	1162	{
NYX	0:85b3fd62ea1a	1163	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
NYX	0:85b3fd62ea1a	1164	}
NYX	0:85b3fd62ea1a	1165
NYX	0:85b3fd62ea1a	1166	/**
NYX	0:85b3fd62ea1a	1167	* @brief Select the distribution of the bitsream lock gated by TIM3 OC1
NYX	0:85b3fd62ea1a	1168	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
NYX	0:85b3fd62ea1a	1169	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1170	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
NYX	0:85b3fd62ea1a	1171	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
NYX	0:85b3fd62ea1a	1172	* @retval None
NYX	0:85b3fd62ea1a	1173	*/
NYX	0:85b3fd62ea1a	1174	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
NYX	0:85b3fd62ea1a	1175	{
NYX	0:85b3fd62ea1a	1176	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
NYX	0:85b3fd62ea1a	1177	}
NYX	0:85b3fd62ea1a	1178	/**
NYX	0:85b3fd62ea1a	1179	* @brief Get the distribution of the bitsream lock gated by TIM3 OC1
NYX	0:85b3fd62ea1a	1180	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
NYX	0:85b3fd62ea1a	1181	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1182	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
NYX	0:85b3fd62ea1a	1183	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
NYX	0:85b3fd62ea1a	1184	* @retval None
NYX	0:85b3fd62ea1a	1185	*/
NYX	0:85b3fd62ea1a	1186	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
NYX	0:85b3fd62ea1a	1187	{
NYX	0:85b3fd62ea1a	1188	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
NYX	0:85b3fd62ea1a	1189	}
NYX	0:85b3fd62ea1a	1190
NYX	0:85b3fd62ea1a	1191	/**
NYX	0:85b3fd62ea1a	1192	* @brief Select the DFSDM2 Clock In
NYX	0:85b3fd62ea1a	1193	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection
NYX	0:85b3fd62ea1a	1194	* @param ClockSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1195	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
NYX	0:85b3fd62ea1a	1196	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
NYX	0:85b3fd62ea1a	1197	* @retval None
NYX	0:85b3fd62ea1a	1198	*/
NYX	0:85b3fd62ea1a	1199	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
NYX	0:85b3fd62ea1a	1200	{
NYX	0:85b3fd62ea1a	1201	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
NYX	0:85b3fd62ea1a	1202	}
NYX	0:85b3fd62ea1a	1203	/**
NYX	0:85b3fd62ea1a	1204	* @brief GET the DFSDM2 Clock In
NYX	0:85b3fd62ea1a	1205	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection
NYX	0:85b3fd62ea1a	1206	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1207	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
NYX	0:85b3fd62ea1a	1208	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
NYX	0:85b3fd62ea1a	1209	* @retval None
NYX	0:85b3fd62ea1a	1210	*/
NYX	0:85b3fd62ea1a	1211	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
NYX	0:85b3fd62ea1a	1212	{
NYX	0:85b3fd62ea1a	1213	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
NYX	0:85b3fd62ea1a	1214	}
NYX	0:85b3fd62ea1a	1215
NYX	0:85b3fd62ea1a	1216	/**
NYX	0:85b3fd62ea1a	1217	* @brief Select the DFSDM2 Clock Out
NYX	0:85b3fd62ea1a	1218	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
NYX	0:85b3fd62ea1a	1219	* @param ClockSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1220	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
NYX	0:85b3fd62ea1a	1221	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
NYX	0:85b3fd62ea1a	1222	* @retval None
NYX	0:85b3fd62ea1a	1223	*/
NYX	0:85b3fd62ea1a	1224	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
NYX	0:85b3fd62ea1a	1225	{
NYX	0:85b3fd62ea1a	1226	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
NYX	0:85b3fd62ea1a	1227	}
NYX	0:85b3fd62ea1a	1228	/**
NYX	0:85b3fd62ea1a	1229	* @brief GET the DFSDM2 Clock Out
NYX	0:85b3fd62ea1a	1230	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
NYX	0:85b3fd62ea1a	1231	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1232	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
NYX	0:85b3fd62ea1a	1233	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
NYX	0:85b3fd62ea1a	1234	* @retval None
NYX	0:85b3fd62ea1a	1235	*/
NYX	0:85b3fd62ea1a	1236	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
NYX	0:85b3fd62ea1a	1237	{
NYX	0:85b3fd62ea1a	1238	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
NYX	0:85b3fd62ea1a	1239	}
NYX	0:85b3fd62ea1a	1240
NYX	0:85b3fd62ea1a	1241	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
NYX	0:85b3fd62ea1a	1242	/**
NYX	0:85b3fd62ea1a	1243	* @}
NYX	0:85b3fd62ea1a	1244	*/
NYX	0:85b3fd62ea1a	1245
NYX	0:85b3fd62ea1a	1246
NYX	0:85b3fd62ea1a	1247	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
NYX	0:85b3fd62ea1a	1248	* @{
NYX	0:85b3fd62ea1a	1249	*/
NYX	0:85b3fd62ea1a	1250
NYX	0:85b3fd62ea1a	1251	/**
NYX	0:85b3fd62ea1a	1252	* @brief Return the device identifier
NYX	0:85b3fd62ea1a	1253	* @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
NYX	0:85b3fd62ea1a	1254	* @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
NYX	0:85b3fd62ea1a	1255	* @note For STM32F401xx devices, the device ID is 0x423
NYX	0:85b3fd62ea1a	1256	* @note For STM32F401xx devices, the device ID is 0x433
NYX	0:85b3fd62ea1a	1257	* @note For STM32F411xx devices, the device ID is 0x431
NYX	0:85b3fd62ea1a	1258	* @note For STM32F410xx devices, the device ID is 0x458
NYX	0:85b3fd62ea1a	1259	* @note For STM32F412xx devices, the device ID is 0x441
NYX	0:85b3fd62ea1a	1260	* @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
NYX	0:85b3fd62ea1a	1261	* @note For STM32F446xx devices, the device ID is 0x421
NYX	0:85b3fd62ea1a	1262	* @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
NYX	0:85b3fd62ea1a	1263	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
NYX	0:85b3fd62ea1a	1264	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
NYX	0:85b3fd62ea1a	1265	*/
NYX	0:85b3fd62ea1a	1266	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
NYX	0:85b3fd62ea1a	1267	{
NYX	0:85b3fd62ea1a	1268	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
NYX	0:85b3fd62ea1a	1269	}
NYX	0:85b3fd62ea1a	1270
NYX	0:85b3fd62ea1a	1271	/**
NYX	0:85b3fd62ea1a	1272	* @brief Return the device revision identifier
NYX	0:85b3fd62ea1a	1273	* @note This field indicates the revision of the device.
NYX	0:85b3fd62ea1a	1274	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
NYX	0:85b3fd62ea1a	1275	For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
NYX	0:85b3fd62ea1a	1276	For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
NYX	0:85b3fd62ea1a	1277	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
NYX	0:85b3fd62ea1a	1278	For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
NYX	0:85b3fd62ea1a	1279	For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
NYX	0:85b3fd62ea1a	1280	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
NYX	0:85b3fd62ea1a	1281	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
NYX	0:85b3fd62ea1a	1282	*/
NYX	0:85b3fd62ea1a	1283	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
NYX	0:85b3fd62ea1a	1284	{
NYX	0:85b3fd62ea1a	1285	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
NYX	0:85b3fd62ea1a	1286	}
NYX	0:85b3fd62ea1a	1287
NYX	0:85b3fd62ea1a	1288	/**
NYX	0:85b3fd62ea1a	1289	* @brief Enable the Debug Module during SLEEP mode
NYX	0:85b3fd62ea1a	1290	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
NYX	0:85b3fd62ea1a	1291	* @retval None
NYX	0:85b3fd62ea1a	1292	*/
NYX	0:85b3fd62ea1a	1293	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
NYX	0:85b3fd62ea1a	1294	{
NYX	0:85b3fd62ea1a	1295	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
NYX	0:85b3fd62ea1a	1296	}
NYX	0:85b3fd62ea1a	1297
NYX	0:85b3fd62ea1a	1298	/**
NYX	0:85b3fd62ea1a	1299	* @brief Disable the Debug Module during SLEEP mode
NYX	0:85b3fd62ea1a	1300	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
NYX	0:85b3fd62ea1a	1301	* @retval None
NYX	0:85b3fd62ea1a	1302	*/
NYX	0:85b3fd62ea1a	1303	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
NYX	0:85b3fd62ea1a	1304	{
NYX	0:85b3fd62ea1a	1305	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
NYX	0:85b3fd62ea1a	1306	}
NYX	0:85b3fd62ea1a	1307
NYX	0:85b3fd62ea1a	1308	/**
NYX	0:85b3fd62ea1a	1309	* @brief Enable the Debug Module during STOP mode
NYX	0:85b3fd62ea1a	1310	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
NYX	0:85b3fd62ea1a	1311	* @retval None
NYX	0:85b3fd62ea1a	1312	*/
NYX	0:85b3fd62ea1a	1313	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
NYX	0:85b3fd62ea1a	1314	{
NYX	0:85b3fd62ea1a	1315	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
NYX	0:85b3fd62ea1a	1316	}
NYX	0:85b3fd62ea1a	1317
NYX	0:85b3fd62ea1a	1318	/**
NYX	0:85b3fd62ea1a	1319	* @brief Disable the Debug Module during STOP mode
NYX	0:85b3fd62ea1a	1320	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
NYX	0:85b3fd62ea1a	1321	* @retval None
NYX	0:85b3fd62ea1a	1322	*/
NYX	0:85b3fd62ea1a	1323	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
NYX	0:85b3fd62ea1a	1324	{
NYX	0:85b3fd62ea1a	1325	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
NYX	0:85b3fd62ea1a	1326	}
NYX	0:85b3fd62ea1a	1327
NYX	0:85b3fd62ea1a	1328	/**
NYX	0:85b3fd62ea1a	1329	* @brief Enable the Debug Module during STANDBY mode
NYX	0:85b3fd62ea1a	1330	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
NYX	0:85b3fd62ea1a	1331	* @retval None
NYX	0:85b3fd62ea1a	1332	*/
NYX	0:85b3fd62ea1a	1333	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
NYX	0:85b3fd62ea1a	1334	{
NYX	0:85b3fd62ea1a	1335	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
NYX	0:85b3fd62ea1a	1336	}
NYX	0:85b3fd62ea1a	1337
NYX	0:85b3fd62ea1a	1338	/**
NYX	0:85b3fd62ea1a	1339	* @brief Disable the Debug Module during STANDBY mode
NYX	0:85b3fd62ea1a	1340	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
NYX	0:85b3fd62ea1a	1341	* @retval None
NYX	0:85b3fd62ea1a	1342	*/
NYX	0:85b3fd62ea1a	1343	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
NYX	0:85b3fd62ea1a	1344	{
NYX	0:85b3fd62ea1a	1345	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
NYX	0:85b3fd62ea1a	1346	}
NYX	0:85b3fd62ea1a	1347
NYX	0:85b3fd62ea1a	1348	/**
NYX	0:85b3fd62ea1a	1349	* @brief Set Trace pin assignment control
NYX	0:85b3fd62ea1a	1350	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
NYX	0:85b3fd62ea1a	1351	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
NYX	0:85b3fd62ea1a	1352	* @param PinAssignment This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1353	* @arg @ref LL_DBGMCU_TRACE_NONE
NYX	0:85b3fd62ea1a	1354	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
NYX	0:85b3fd62ea1a	1355	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
NYX	0:85b3fd62ea1a	1356	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
NYX	0:85b3fd62ea1a	1357	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
NYX	0:85b3fd62ea1a	1358	* @retval None
NYX	0:85b3fd62ea1a	1359	*/
NYX	0:85b3fd62ea1a	1360	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
NYX	0:85b3fd62ea1a	1361	{
NYX	0:85b3fd62ea1a	1362	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
NYX	0:85b3fd62ea1a	1363	}
NYX	0:85b3fd62ea1a	1364
NYX	0:85b3fd62ea1a	1365	/**
NYX	0:85b3fd62ea1a	1366	* @brief Get Trace pin assignment control
NYX	0:85b3fd62ea1a	1367	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
NYX	0:85b3fd62ea1a	1368	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
NYX	0:85b3fd62ea1a	1369	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1370	* @arg @ref LL_DBGMCU_TRACE_NONE
NYX	0:85b3fd62ea1a	1371	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
NYX	0:85b3fd62ea1a	1372	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
NYX	0:85b3fd62ea1a	1373	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
NYX	0:85b3fd62ea1a	1374	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
NYX	0:85b3fd62ea1a	1375	*/
NYX	0:85b3fd62ea1a	1376	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
NYX	0:85b3fd62ea1a	1377	{
NYX	0:85b3fd62ea1a	1378	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
NYX	0:85b3fd62ea1a	1379	}
NYX	0:85b3fd62ea1a	1380
NYX	0:85b3fd62ea1a	1381	/**
NYX	0:85b3fd62ea1a	1382	* @brief Freeze APB1 peripherals (group1 peripherals)
NYX	0:85b3fd62ea1a	1383	* @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1384	* DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1385	* DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1386	* DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1387	* DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1388	* DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1389	* DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1390	* DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1391	* DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1392	* DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1393	* DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1394	* DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1395	* DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1396	* DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1397	* DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1398	* DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1399	* DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1400	* DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1401	* DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1402	* DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
NYX	0:85b3fd62ea1a	1403	* @param Periphs This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	1404	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
NYX	0:85b3fd62ea1a	1405	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
NYX	0:85b3fd62ea1a	1406	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
NYX	0:85b3fd62ea1a	1407	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
NYX	0:85b3fd62ea1a	1408	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
NYX	0:85b3fd62ea1a	1409	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
NYX	0:85b3fd62ea1a	1410	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
NYX	0:85b3fd62ea1a	1411	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
NYX	0:85b3fd62ea1a	1412	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
NYX	0:85b3fd62ea1a	1413	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
NYX	0:85b3fd62ea1a	1414	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
NYX	0:85b3fd62ea1a	1415	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
NYX	0:85b3fd62ea1a	1416	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
NYX	0:85b3fd62ea1a	1417	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
NYX	0:85b3fd62ea1a	1418	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
NYX	0:85b3fd62ea1a	1419	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
NYX	0:85b3fd62ea1a	1420	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
NYX	0:85b3fd62ea1a	1421	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
NYX	0:85b3fd62ea1a	1422	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
NYX	0:85b3fd62ea1a	1423	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
NYX	0:85b3fd62ea1a	1424	*
NYX	0:85b3fd62ea1a	1425	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	1426	* @retval None
NYX	0:85b3fd62ea1a	1427	*/
NYX	0:85b3fd62ea1a	1428	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
NYX	0:85b3fd62ea1a	1429	{
NYX	0:85b3fd62ea1a	1430	SET_BIT(DBGMCU->APB1FZ, Periphs);
NYX	0:85b3fd62ea1a	1431	}
NYX	0:85b3fd62ea1a	1432
NYX	0:85b3fd62ea1a	1433	/**
NYX	0:85b3fd62ea1a	1434	* @brief Unfreeze APB1 peripherals (group1 peripherals)
NYX	0:85b3fd62ea1a	1435	* @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1436	* DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1437	* DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1438	* DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1439	* DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1440	* DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1441	* DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1442	* DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1443	* DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1444	* DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1445	* DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1446	* DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1447	* DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1448	* DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1449	* DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1450	* DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1451	* DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1452	* DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1453	* DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1454	* DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
NYX	0:85b3fd62ea1a	1455	* @param Periphs This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	1456	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
NYX	0:85b3fd62ea1a	1457	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
NYX	0:85b3fd62ea1a	1458	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
NYX	0:85b3fd62ea1a	1459	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
NYX	0:85b3fd62ea1a	1460	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
NYX	0:85b3fd62ea1a	1461	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
NYX	0:85b3fd62ea1a	1462	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
NYX	0:85b3fd62ea1a	1463	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
NYX	0:85b3fd62ea1a	1464	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
NYX	0:85b3fd62ea1a	1465	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
NYX	0:85b3fd62ea1a	1466	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
NYX	0:85b3fd62ea1a	1467	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
NYX	0:85b3fd62ea1a	1468	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
NYX	0:85b3fd62ea1a	1469	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
NYX	0:85b3fd62ea1a	1470	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
NYX	0:85b3fd62ea1a	1471	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
NYX	0:85b3fd62ea1a	1472	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
NYX	0:85b3fd62ea1a	1473	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
NYX	0:85b3fd62ea1a	1474	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
NYX	0:85b3fd62ea1a	1475	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
NYX	0:85b3fd62ea1a	1476	*
NYX	0:85b3fd62ea1a	1477	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	1478	* @retval None
NYX	0:85b3fd62ea1a	1479	*/
NYX	0:85b3fd62ea1a	1480	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
NYX	0:85b3fd62ea1a	1481	{
NYX	0:85b3fd62ea1a	1482	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
NYX	0:85b3fd62ea1a	1483	}
NYX	0:85b3fd62ea1a	1484
NYX	0:85b3fd62ea1a	1485	/**
NYX	0:85b3fd62ea1a	1486	* @brief Freeze APB2 peripherals
NYX	0:85b3fd62ea1a	1487	* @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1488	* DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1489	* DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1490	* DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
NYX	0:85b3fd62ea1a	1491	* DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
NYX	0:85b3fd62ea1a	1492	* @param Periphs This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	1493	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
NYX	0:85b3fd62ea1a	1494	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
NYX	0:85b3fd62ea1a	1495	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
NYX	0:85b3fd62ea1a	1496	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
NYX	0:85b3fd62ea1a	1497	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
NYX	0:85b3fd62ea1a	1498	*
NYX	0:85b3fd62ea1a	1499	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	1500	* @retval None
NYX	0:85b3fd62ea1a	1501	*/
NYX	0:85b3fd62ea1a	1502	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
NYX	0:85b3fd62ea1a	1503	{
NYX	0:85b3fd62ea1a	1504	SET_BIT(DBGMCU->APB2FZ, Periphs);
NYX	0:85b3fd62ea1a	1505	}
NYX	0:85b3fd62ea1a	1506
NYX	0:85b3fd62ea1a	1507	/**
NYX	0:85b3fd62ea1a	1508	* @brief Unfreeze APB2 peripherals
NYX	0:85b3fd62ea1a	1509	* @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1510	* DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1511	* DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1512	* DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
NYX	0:85b3fd62ea1a	1513	* DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
NYX	0:85b3fd62ea1a	1514	* @param Periphs This parameter can be a combination of the following values:
NYX	0:85b3fd62ea1a	1515	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
NYX	0:85b3fd62ea1a	1516	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
NYX	0:85b3fd62ea1a	1517	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
NYX	0:85b3fd62ea1a	1518	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
NYX	0:85b3fd62ea1a	1519	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
NYX	0:85b3fd62ea1a	1520	*
NYX	0:85b3fd62ea1a	1521	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	1522	* @retval None
NYX	0:85b3fd62ea1a	1523	*/
NYX	0:85b3fd62ea1a	1524	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
NYX	0:85b3fd62ea1a	1525	{
NYX	0:85b3fd62ea1a	1526	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
NYX	0:85b3fd62ea1a	1527	}
NYX	0:85b3fd62ea1a	1528	/**
NYX	0:85b3fd62ea1a	1529	* @}
NYX	0:85b3fd62ea1a	1530	*/
NYX	0:85b3fd62ea1a	1531
NYX	0:85b3fd62ea1a	1532	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
NYX	0:85b3fd62ea1a	1533	* @{
NYX	0:85b3fd62ea1a	1534	*/
NYX	0:85b3fd62ea1a	1535
NYX	0:85b3fd62ea1a	1536	/**
NYX	0:85b3fd62ea1a	1537	* @brief Set FLASH Latency
NYX	0:85b3fd62ea1a	1538	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
NYX	0:85b3fd62ea1a	1539	* @param Latency This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1540	* @arg @ref LL_FLASH_LATENCY_0
NYX	0:85b3fd62ea1a	1541	* @arg @ref LL_FLASH_LATENCY_1
NYX	0:85b3fd62ea1a	1542	* @arg @ref LL_FLASH_LATENCY_2
NYX	0:85b3fd62ea1a	1543	* @arg @ref LL_FLASH_LATENCY_3
NYX	0:85b3fd62ea1a	1544	* @arg @ref LL_FLASH_LATENCY_4
NYX	0:85b3fd62ea1a	1545	* @arg @ref LL_FLASH_LATENCY_5
NYX	0:85b3fd62ea1a	1546	* @arg @ref LL_FLASH_LATENCY_6
NYX	0:85b3fd62ea1a	1547	* @arg @ref LL_FLASH_LATENCY_7
NYX	0:85b3fd62ea1a	1548	* @arg @ref LL_FLASH_LATENCY_8
NYX	0:85b3fd62ea1a	1549	* @arg @ref LL_FLASH_LATENCY_9
NYX	0:85b3fd62ea1a	1550	* @arg @ref LL_FLASH_LATENCY_10
NYX	0:85b3fd62ea1a	1551	* @arg @ref LL_FLASH_LATENCY_11
NYX	0:85b3fd62ea1a	1552	* @arg @ref LL_FLASH_LATENCY_12
NYX	0:85b3fd62ea1a	1553	* @arg @ref LL_FLASH_LATENCY_13
NYX	0:85b3fd62ea1a	1554	* @arg @ref LL_FLASH_LATENCY_14
NYX	0:85b3fd62ea1a	1555	* @arg @ref LL_FLASH_LATENCY_15
NYX	0:85b3fd62ea1a	1556	* @retval None
NYX	0:85b3fd62ea1a	1557	*/
NYX	0:85b3fd62ea1a	1558	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
NYX	0:85b3fd62ea1a	1559	{
NYX	0:85b3fd62ea1a	1560	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
NYX	0:85b3fd62ea1a	1561	}
NYX	0:85b3fd62ea1a	1562
NYX	0:85b3fd62ea1a	1563	/**
NYX	0:85b3fd62ea1a	1564	* @brief Get FLASH Latency
NYX	0:85b3fd62ea1a	1565	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
NYX	0:85b3fd62ea1a	1566	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1567	* @arg @ref LL_FLASH_LATENCY_0
NYX	0:85b3fd62ea1a	1568	* @arg @ref LL_FLASH_LATENCY_1
NYX	0:85b3fd62ea1a	1569	* @arg @ref LL_FLASH_LATENCY_2
NYX	0:85b3fd62ea1a	1570	* @arg @ref LL_FLASH_LATENCY_3
NYX	0:85b3fd62ea1a	1571	* @arg @ref LL_FLASH_LATENCY_4
NYX	0:85b3fd62ea1a	1572	* @arg @ref LL_FLASH_LATENCY_5
NYX	0:85b3fd62ea1a	1573	* @arg @ref LL_FLASH_LATENCY_6
NYX	0:85b3fd62ea1a	1574	* @arg @ref LL_FLASH_LATENCY_7
NYX	0:85b3fd62ea1a	1575	* @arg @ref LL_FLASH_LATENCY_8
NYX	0:85b3fd62ea1a	1576	* @arg @ref LL_FLASH_LATENCY_9
NYX	0:85b3fd62ea1a	1577	* @arg @ref LL_FLASH_LATENCY_10
NYX	0:85b3fd62ea1a	1578	* @arg @ref LL_FLASH_LATENCY_11
NYX	0:85b3fd62ea1a	1579	* @arg @ref LL_FLASH_LATENCY_12
NYX	0:85b3fd62ea1a	1580	* @arg @ref LL_FLASH_LATENCY_13
NYX	0:85b3fd62ea1a	1581	* @arg @ref LL_FLASH_LATENCY_14
NYX	0:85b3fd62ea1a	1582	* @arg @ref LL_FLASH_LATENCY_15
NYX	0:85b3fd62ea1a	1583	*/
NYX	0:85b3fd62ea1a	1584	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
NYX	0:85b3fd62ea1a	1585	{
NYX	0:85b3fd62ea1a	1586	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
NYX	0:85b3fd62ea1a	1587	}
NYX	0:85b3fd62ea1a	1588
NYX	0:85b3fd62ea1a	1589	/**
NYX	0:85b3fd62ea1a	1590	* @brief Enable Prefetch
NYX	0:85b3fd62ea1a	1591	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
NYX	0:85b3fd62ea1a	1592	* @retval None
NYX	0:85b3fd62ea1a	1593	*/
NYX	0:85b3fd62ea1a	1594	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
NYX	0:85b3fd62ea1a	1595	{
NYX	0:85b3fd62ea1a	1596	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
NYX	0:85b3fd62ea1a	1597	}
NYX	0:85b3fd62ea1a	1598
NYX	0:85b3fd62ea1a	1599	/**
NYX	0:85b3fd62ea1a	1600	* @brief Disable Prefetch
NYX	0:85b3fd62ea1a	1601	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
NYX	0:85b3fd62ea1a	1602	* @retval None
NYX	0:85b3fd62ea1a	1603	*/
NYX	0:85b3fd62ea1a	1604	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
NYX	0:85b3fd62ea1a	1605	{
NYX	0:85b3fd62ea1a	1606	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
NYX	0:85b3fd62ea1a	1607	}
NYX	0:85b3fd62ea1a	1608
NYX	0:85b3fd62ea1a	1609	/**
NYX	0:85b3fd62ea1a	1610	* @brief Check if Prefetch buffer is enabled
NYX	0:85b3fd62ea1a	1611	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
NYX	0:85b3fd62ea1a	1612	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1613	*/
NYX	0:85b3fd62ea1a	1614	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
NYX	0:85b3fd62ea1a	1615	{
NYX	0:85b3fd62ea1a	1616	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
NYX	0:85b3fd62ea1a	1617	}
NYX	0:85b3fd62ea1a	1618
NYX	0:85b3fd62ea1a	1619	/**
NYX	0:85b3fd62ea1a	1620	* @brief Enable Instruction cache
NYX	0:85b3fd62ea1a	1621	* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
NYX	0:85b3fd62ea1a	1622	* @retval None
NYX	0:85b3fd62ea1a	1623	*/
NYX	0:85b3fd62ea1a	1624	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
NYX	0:85b3fd62ea1a	1625	{
NYX	0:85b3fd62ea1a	1626	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
NYX	0:85b3fd62ea1a	1627	}
NYX	0:85b3fd62ea1a	1628
NYX	0:85b3fd62ea1a	1629	/**
NYX	0:85b3fd62ea1a	1630	* @brief Disable Instruction cache
NYX	0:85b3fd62ea1a	1631	* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
NYX	0:85b3fd62ea1a	1632	* @retval None
NYX	0:85b3fd62ea1a	1633	*/
NYX	0:85b3fd62ea1a	1634	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
NYX	0:85b3fd62ea1a	1635	{
NYX	0:85b3fd62ea1a	1636	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
NYX	0:85b3fd62ea1a	1637	}
NYX	0:85b3fd62ea1a	1638
NYX	0:85b3fd62ea1a	1639	/**
NYX	0:85b3fd62ea1a	1640	* @brief Enable Data cache
NYX	0:85b3fd62ea1a	1641	* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
NYX	0:85b3fd62ea1a	1642	* @retval None
NYX	0:85b3fd62ea1a	1643	*/
NYX	0:85b3fd62ea1a	1644	__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
NYX	0:85b3fd62ea1a	1645	{
NYX	0:85b3fd62ea1a	1646	SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
NYX	0:85b3fd62ea1a	1647	}
NYX	0:85b3fd62ea1a	1648
NYX	0:85b3fd62ea1a	1649	/**
NYX	0:85b3fd62ea1a	1650	* @brief Disable Data cache
NYX	0:85b3fd62ea1a	1651	* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
NYX	0:85b3fd62ea1a	1652	* @retval None
NYX	0:85b3fd62ea1a	1653	*/
NYX	0:85b3fd62ea1a	1654	__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
NYX	0:85b3fd62ea1a	1655	{
NYX	0:85b3fd62ea1a	1656	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
NYX	0:85b3fd62ea1a	1657	}
NYX	0:85b3fd62ea1a	1658
NYX	0:85b3fd62ea1a	1659	/**
NYX	0:85b3fd62ea1a	1660	* @brief Enable Instruction cache reset
NYX	0:85b3fd62ea1a	1661	* @note bit can be written only when the instruction cache is disabled
NYX	0:85b3fd62ea1a	1662	* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
NYX	0:85b3fd62ea1a	1663	* @retval None
NYX	0:85b3fd62ea1a	1664	*/
NYX	0:85b3fd62ea1a	1665	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
NYX	0:85b3fd62ea1a	1666	{
NYX	0:85b3fd62ea1a	1667	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
NYX	0:85b3fd62ea1a	1668	}
NYX	0:85b3fd62ea1a	1669
NYX	0:85b3fd62ea1a	1670	/**
NYX	0:85b3fd62ea1a	1671	* @brief Disable Instruction cache reset
NYX	0:85b3fd62ea1a	1672	* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
NYX	0:85b3fd62ea1a	1673	* @retval None
NYX	0:85b3fd62ea1a	1674	*/
NYX	0:85b3fd62ea1a	1675	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
NYX	0:85b3fd62ea1a	1676	{
NYX	0:85b3fd62ea1a	1677	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
NYX	0:85b3fd62ea1a	1678	}
NYX	0:85b3fd62ea1a	1679
NYX	0:85b3fd62ea1a	1680	/**
NYX	0:85b3fd62ea1a	1681	* @brief Enable Data cache reset
NYX	0:85b3fd62ea1a	1682	* @note bit can be written only when the data cache is disabled
NYX	0:85b3fd62ea1a	1683	* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
NYX	0:85b3fd62ea1a	1684	* @retval None
NYX	0:85b3fd62ea1a	1685	*/
NYX	0:85b3fd62ea1a	1686	__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
NYX	0:85b3fd62ea1a	1687	{
NYX	0:85b3fd62ea1a	1688	SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
NYX	0:85b3fd62ea1a	1689	}
NYX	0:85b3fd62ea1a	1690
NYX	0:85b3fd62ea1a	1691	/**
NYX	0:85b3fd62ea1a	1692	* @brief Disable Data cache reset
NYX	0:85b3fd62ea1a	1693	* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
NYX	0:85b3fd62ea1a	1694	* @retval None
NYX	0:85b3fd62ea1a	1695	*/
NYX	0:85b3fd62ea1a	1696	__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
NYX	0:85b3fd62ea1a	1697	{
NYX	0:85b3fd62ea1a	1698	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
NYX	0:85b3fd62ea1a	1699	}
NYX	0:85b3fd62ea1a	1700
NYX	0:85b3fd62ea1a	1701
NYX	0:85b3fd62ea1a	1702	/**
NYX	0:85b3fd62ea1a	1703	* @}
NYX	0:85b3fd62ea1a	1704	*/
NYX	0:85b3fd62ea1a	1705
NYX	0:85b3fd62ea1a	1706	/**
NYX	0:85b3fd62ea1a	1707	* @}
NYX	0:85b3fd62ea1a	1708	*/
NYX	0:85b3fd62ea1a	1709
NYX	0:85b3fd62ea1a	1710	/**
NYX	0:85b3fd62ea1a	1711	* @}
NYX	0:85b3fd62ea1a	1712	*/
NYX	0:85b3fd62ea1a	1713
NYX	0:85b3fd62ea1a	1714	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
NYX	0:85b3fd62ea1a	1715
NYX	0:85b3fd62ea1a	1716	/**
NYX	0:85b3fd62ea1a	1717	* @}
NYX	0:85b3fd62ea1a	1718	*/
NYX	0:85b3fd62ea1a	1719
NYX	0:85b3fd62ea1a	1720	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	1721	}
NYX	0:85b3fd62ea1a	1722	#endif
NYX	0:85b3fd62ea1a	1723
NYX	0:85b3fd62ea1a	1724	#endif /* __STM32F4xx_LL_SYSTEM_H */
NYX	0:85b3fd62ea1a	1725
NYX	0:85b3fd62ea1a	1726	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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