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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

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NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_spi.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of SPI LL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_LL_SPI_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_LL_SPI_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #include "stm32f4xx.h"
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /** @addtogroup STM32F4xx_LL_Driver
NYX 0:85b3fd62ea1a 50 * @{
NYX 0:85b3fd62ea1a 51 */
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 /** @defgroup SPI_LL SPI
NYX 0:85b3fd62ea1a 56 * @{
NYX 0:85b3fd62ea1a 57 */
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 61 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 64 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 65 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
NYX 0:85b3fd62ea1a 66 * @{
NYX 0:85b3fd62ea1a 67 */
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 /**
NYX 0:85b3fd62ea1a 70 * @brief SPI Init structures definition
NYX 0:85b3fd62ea1a 71 */
NYX 0:85b3fd62ea1a 72 typedef struct
NYX 0:85b3fd62ea1a 73 {
NYX 0:85b3fd62ea1a 74 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
NYX 0:85b3fd62ea1a 75 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
NYX 0:85b3fd62ea1a 76
NYX 0:85b3fd62ea1a 77 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
NYX 0:85b3fd62ea1a 78
NYX 0:85b3fd62ea1a 79 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
NYX 0:85b3fd62ea1a 80 This parameter can be a value of @ref SPI_LL_EC_MODE.
NYX 0:85b3fd62ea1a 81
NYX 0:85b3fd62ea1a 82 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
NYX 0:85b3fd62ea1a 83
NYX 0:85b3fd62ea1a 84 uint32_t DataWidth; /*!< Specifies the SPI data width.
NYX 0:85b3fd62ea1a 85 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
NYX 0:85b3fd62ea1a 86
NYX 0:85b3fd62ea1a 87 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
NYX 0:85b3fd62ea1a 88
NYX 0:85b3fd62ea1a 89 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
NYX 0:85b3fd62ea1a 90 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
NYX 0:85b3fd62ea1a 91
NYX 0:85b3fd62ea1a 92 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
NYX 0:85b3fd62ea1a 93
NYX 0:85b3fd62ea1a 94 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
NYX 0:85b3fd62ea1a 95 This parameter can be a value of @ref SPI_LL_EC_PHASE.
NYX 0:85b3fd62ea1a 96
NYX 0:85b3fd62ea1a 97 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
NYX 0:85b3fd62ea1a 98
NYX 0:85b3fd62ea1a 99 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
NYX 0:85b3fd62ea1a 100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
NYX 0:85b3fd62ea1a 101
NYX 0:85b3fd62ea1a 102 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
NYX 0:85b3fd62ea1a 103
NYX 0:85b3fd62ea1a 104 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
NYX 0:85b3fd62ea1a 105 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
NYX 0:85b3fd62ea1a 106 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
NYX 0:85b3fd62ea1a 107
NYX 0:85b3fd62ea1a 108 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
NYX 0:85b3fd62ea1a 109
NYX 0:85b3fd62ea1a 110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
NYX 0:85b3fd62ea1a 111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
NYX 0:85b3fd62ea1a 116 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
NYX 0:85b3fd62ea1a 119
NYX 0:85b3fd62ea1a 120 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
NYX 0:85b3fd62ea1a 121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
NYX 0:85b3fd62ea1a 122
NYX 0:85b3fd62ea1a 123 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
NYX 0:85b3fd62ea1a 124
NYX 0:85b3fd62ea1a 125 } LL_SPI_InitTypeDef;
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 /**
NYX 0:85b3fd62ea1a 128 * @}
NYX 0:85b3fd62ea1a 129 */
NYX 0:85b3fd62ea1a 130 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 131
NYX 0:85b3fd62ea1a 132 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
NYX 0:85b3fd62ea1a 134 * @{
NYX 0:85b3fd62ea1a 135 */
NYX 0:85b3fd62ea1a 136
NYX 0:85b3fd62ea1a 137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
NYX 0:85b3fd62ea1a 138 * @brief Flags defines which can be used with LL_SPI_ReadReg function
NYX 0:85b3fd62ea1a 139 * @{
NYX 0:85b3fd62ea1a 140 */
NYX 0:85b3fd62ea1a 141 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
NYX 0:85b3fd62ea1a 142 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
NYX 0:85b3fd62ea1a 143 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
NYX 0:85b3fd62ea1a 144 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
NYX 0:85b3fd62ea1a 145 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
NYX 0:85b3fd62ea1a 146 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
NYX 0:85b3fd62ea1a 147 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
NYX 0:85b3fd62ea1a 148 /**
NYX 0:85b3fd62ea1a 149 * @}
NYX 0:85b3fd62ea1a 150 */
NYX 0:85b3fd62ea1a 151
NYX 0:85b3fd62ea1a 152 /** @defgroup SPI_LL_EC_IT IT Defines
NYX 0:85b3fd62ea1a 153 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
NYX 0:85b3fd62ea1a 154 * @{
NYX 0:85b3fd62ea1a 155 */
NYX 0:85b3fd62ea1a 156 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
NYX 0:85b3fd62ea1a 157 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
NYX 0:85b3fd62ea1a 158 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
NYX 0:85b3fd62ea1a 159 /**
NYX 0:85b3fd62ea1a 160 * @}
NYX 0:85b3fd62ea1a 161 */
NYX 0:85b3fd62ea1a 162
NYX 0:85b3fd62ea1a 163 /** @defgroup SPI_LL_EC_MODE Operation Mode
NYX 0:85b3fd62ea1a 164 * @{
NYX 0:85b3fd62ea1a 165 */
NYX 0:85b3fd62ea1a 166 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
NYX 0:85b3fd62ea1a 167 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
NYX 0:85b3fd62ea1a 168 /**
NYX 0:85b3fd62ea1a 169 * @}
NYX 0:85b3fd62ea1a 170 */
NYX 0:85b3fd62ea1a 171
NYX 0:85b3fd62ea1a 172 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
NYX 0:85b3fd62ea1a 173 * @{
NYX 0:85b3fd62ea1a 174 */
NYX 0:85b3fd62ea1a 175 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
NYX 0:85b3fd62ea1a 176 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
NYX 0:85b3fd62ea1a 177 /**
NYX 0:85b3fd62ea1a 178 * @}
NYX 0:85b3fd62ea1a 179 */
NYX 0:85b3fd62ea1a 180
NYX 0:85b3fd62ea1a 181 /** @defgroup SPI_LL_EC_PHASE Clock Phase
NYX 0:85b3fd62ea1a 182 * @{
NYX 0:85b3fd62ea1a 183 */
NYX 0:85b3fd62ea1a 184 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
NYX 0:85b3fd62ea1a 185 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
NYX 0:85b3fd62ea1a 186 /**
NYX 0:85b3fd62ea1a 187 * @}
NYX 0:85b3fd62ea1a 188 */
NYX 0:85b3fd62ea1a 189
NYX 0:85b3fd62ea1a 190 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
NYX 0:85b3fd62ea1a 191 * @{
NYX 0:85b3fd62ea1a 192 */
NYX 0:85b3fd62ea1a 193 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
NYX 0:85b3fd62ea1a 194 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
NYX 0:85b3fd62ea1a 195 /**
NYX 0:85b3fd62ea1a 196 * @}
NYX 0:85b3fd62ea1a 197 */
NYX 0:85b3fd62ea1a 198
NYX 0:85b3fd62ea1a 199 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
NYX 0:85b3fd62ea1a 200 * @{
NYX 0:85b3fd62ea1a 201 */
NYX 0:85b3fd62ea1a 202 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
NYX 0:85b3fd62ea1a 203 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
NYX 0:85b3fd62ea1a 204 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
NYX 0:85b3fd62ea1a 205 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
NYX 0:85b3fd62ea1a 206 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
NYX 0:85b3fd62ea1a 207 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
NYX 0:85b3fd62ea1a 208 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
NYX 0:85b3fd62ea1a 209 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
NYX 0:85b3fd62ea1a 210 /**
NYX 0:85b3fd62ea1a 211 * @}
NYX 0:85b3fd62ea1a 212 */
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
NYX 0:85b3fd62ea1a 215 * @{
NYX 0:85b3fd62ea1a 216 */
NYX 0:85b3fd62ea1a 217 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
NYX 0:85b3fd62ea1a 218 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
NYX 0:85b3fd62ea1a 219 /**
NYX 0:85b3fd62ea1a 220 * @}
NYX 0:85b3fd62ea1a 221 */
NYX 0:85b3fd62ea1a 222
NYX 0:85b3fd62ea1a 223 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
NYX 0:85b3fd62ea1a 224 * @{
NYX 0:85b3fd62ea1a 225 */
NYX 0:85b3fd62ea1a 226 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
NYX 0:85b3fd62ea1a 227 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
NYX 0:85b3fd62ea1a 228 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
NYX 0:85b3fd62ea1a 229 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
NYX 0:85b3fd62ea1a 230 /**
NYX 0:85b3fd62ea1a 231 * @}
NYX 0:85b3fd62ea1a 232 */
NYX 0:85b3fd62ea1a 233
NYX 0:85b3fd62ea1a 234 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
NYX 0:85b3fd62ea1a 235 * @{
NYX 0:85b3fd62ea1a 236 */
NYX 0:85b3fd62ea1a 237 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
NYX 0:85b3fd62ea1a 238 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
NYX 0:85b3fd62ea1a 239 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
NYX 0:85b3fd62ea1a 240 /**
NYX 0:85b3fd62ea1a 241 * @}
NYX 0:85b3fd62ea1a 242 */
NYX 0:85b3fd62ea1a 243
NYX 0:85b3fd62ea1a 244 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
NYX 0:85b3fd62ea1a 245 * @{
NYX 0:85b3fd62ea1a 246 */
NYX 0:85b3fd62ea1a 247 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
NYX 0:85b3fd62ea1a 248 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
NYX 0:85b3fd62ea1a 249 /**
NYX 0:85b3fd62ea1a 250 * @}
NYX 0:85b3fd62ea1a 251 */
NYX 0:85b3fd62ea1a 252 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 253
NYX 0:85b3fd62ea1a 254 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
NYX 0:85b3fd62ea1a 255 * @{
NYX 0:85b3fd62ea1a 256 */
NYX 0:85b3fd62ea1a 257 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
NYX 0:85b3fd62ea1a 258 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
NYX 0:85b3fd62ea1a 259 /**
NYX 0:85b3fd62ea1a 260 * @}
NYX 0:85b3fd62ea1a 261 */
NYX 0:85b3fd62ea1a 262 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 263
NYX 0:85b3fd62ea1a 264 /**
NYX 0:85b3fd62ea1a 265 * @}
NYX 0:85b3fd62ea1a 266 */
NYX 0:85b3fd62ea1a 267
NYX 0:85b3fd62ea1a 268 /* Exported macro ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 269 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
NYX 0:85b3fd62ea1a 270 * @{
NYX 0:85b3fd62ea1a 271 */
NYX 0:85b3fd62ea1a 272
NYX 0:85b3fd62ea1a 273 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
NYX 0:85b3fd62ea1a 274 * @{
NYX 0:85b3fd62ea1a 275 */
NYX 0:85b3fd62ea1a 276
NYX 0:85b3fd62ea1a 277 /**
NYX 0:85b3fd62ea1a 278 * @brief Write a value in SPI register
NYX 0:85b3fd62ea1a 279 * @param __INSTANCE__ SPI Instance
NYX 0:85b3fd62ea1a 280 * @param __REG__ Register to be written
NYX 0:85b3fd62ea1a 281 * @param __VALUE__ Value to be written in the register
NYX 0:85b3fd62ea1a 282 * @retval None
NYX 0:85b3fd62ea1a 283 */
NYX 0:85b3fd62ea1a 284 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
NYX 0:85b3fd62ea1a 285
NYX 0:85b3fd62ea1a 286 /**
NYX 0:85b3fd62ea1a 287 * @brief Read a value in SPI register
NYX 0:85b3fd62ea1a 288 * @param __INSTANCE__ SPI Instance
NYX 0:85b3fd62ea1a 289 * @param __REG__ Register to be read
NYX 0:85b3fd62ea1a 290 * @retval Register value
NYX 0:85b3fd62ea1a 291 */
NYX 0:85b3fd62ea1a 292 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
NYX 0:85b3fd62ea1a 293 /**
NYX 0:85b3fd62ea1a 294 * @}
NYX 0:85b3fd62ea1a 295 */
NYX 0:85b3fd62ea1a 296
NYX 0:85b3fd62ea1a 297 /**
NYX 0:85b3fd62ea1a 298 * @}
NYX 0:85b3fd62ea1a 299 */
NYX 0:85b3fd62ea1a 300
NYX 0:85b3fd62ea1a 301 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 302 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
NYX 0:85b3fd62ea1a 303 * @{
NYX 0:85b3fd62ea1a 304 */
NYX 0:85b3fd62ea1a 305
NYX 0:85b3fd62ea1a 306 /** @defgroup SPI_LL_EF_Configuration Configuration
NYX 0:85b3fd62ea1a 307 * @{
NYX 0:85b3fd62ea1a 308 */
NYX 0:85b3fd62ea1a 309
NYX 0:85b3fd62ea1a 310 /**
NYX 0:85b3fd62ea1a 311 * @brief Enable SPI peripheral
NYX 0:85b3fd62ea1a 312 * @rmtoll CR1 SPE LL_SPI_Enable
NYX 0:85b3fd62ea1a 313 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 314 * @retval None
NYX 0:85b3fd62ea1a 315 */
NYX 0:85b3fd62ea1a 316 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 317 {
NYX 0:85b3fd62ea1a 318 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
NYX 0:85b3fd62ea1a 319 }
NYX 0:85b3fd62ea1a 320
NYX 0:85b3fd62ea1a 321 /**
NYX 0:85b3fd62ea1a 322 * @brief Disable SPI peripheral
NYX 0:85b3fd62ea1a 323 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
NYX 0:85b3fd62ea1a 324 * @rmtoll CR1 SPE LL_SPI_Disable
NYX 0:85b3fd62ea1a 325 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 326 * @retval None
NYX 0:85b3fd62ea1a 327 */
NYX 0:85b3fd62ea1a 328 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 329 {
NYX 0:85b3fd62ea1a 330 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
NYX 0:85b3fd62ea1a 331 }
NYX 0:85b3fd62ea1a 332
NYX 0:85b3fd62ea1a 333 /**
NYX 0:85b3fd62ea1a 334 * @brief Check if SPI peripheral is enabled
NYX 0:85b3fd62ea1a 335 * @rmtoll CR1 SPE LL_SPI_IsEnabled
NYX 0:85b3fd62ea1a 336 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 337 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 338 */
NYX 0:85b3fd62ea1a 339 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 340 {
NYX 0:85b3fd62ea1a 341 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
NYX 0:85b3fd62ea1a 342 }
NYX 0:85b3fd62ea1a 343
NYX 0:85b3fd62ea1a 344 /**
NYX 0:85b3fd62ea1a 345 * @brief Set SPI operation mode to Master or Slave
NYX 0:85b3fd62ea1a 346 * @note This bit should not be changed when communication is ongoing.
NYX 0:85b3fd62ea1a 347 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
NYX 0:85b3fd62ea1a 348 * CR1 SSI LL_SPI_SetMode
NYX 0:85b3fd62ea1a 349 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 350 * @param Mode This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 351 * @arg @ref LL_SPI_MODE_MASTER
NYX 0:85b3fd62ea1a 352 * @arg @ref LL_SPI_MODE_SLAVE
NYX 0:85b3fd62ea1a 353 * @retval None
NYX 0:85b3fd62ea1a 354 */
NYX 0:85b3fd62ea1a 355 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
NYX 0:85b3fd62ea1a 356 {
NYX 0:85b3fd62ea1a 357 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
NYX 0:85b3fd62ea1a 358 }
NYX 0:85b3fd62ea1a 359
NYX 0:85b3fd62ea1a 360 /**
NYX 0:85b3fd62ea1a 361 * @brief Get SPI operation mode (Master or Slave)
NYX 0:85b3fd62ea1a 362 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
NYX 0:85b3fd62ea1a 363 * CR1 SSI LL_SPI_GetMode
NYX 0:85b3fd62ea1a 364 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 365 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 366 * @arg @ref LL_SPI_MODE_MASTER
NYX 0:85b3fd62ea1a 367 * @arg @ref LL_SPI_MODE_SLAVE
NYX 0:85b3fd62ea1a 368 */
NYX 0:85b3fd62ea1a 369 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 370 {
NYX 0:85b3fd62ea1a 371 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
NYX 0:85b3fd62ea1a 372 }
NYX 0:85b3fd62ea1a 373
NYX 0:85b3fd62ea1a 374 /**
NYX 0:85b3fd62ea1a 375 * @brief Set serial protocol used
NYX 0:85b3fd62ea1a 376 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
NYX 0:85b3fd62ea1a 377 * @rmtoll CR2 FRF LL_SPI_SetStandard
NYX 0:85b3fd62ea1a 378 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 379 * @param Standard This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 380 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
NYX 0:85b3fd62ea1a 381 * @arg @ref LL_SPI_PROTOCOL_TI
NYX 0:85b3fd62ea1a 382 * @retval None
NYX 0:85b3fd62ea1a 383 */
NYX 0:85b3fd62ea1a 384 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
NYX 0:85b3fd62ea1a 385 {
NYX 0:85b3fd62ea1a 386 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
NYX 0:85b3fd62ea1a 387 }
NYX 0:85b3fd62ea1a 388
NYX 0:85b3fd62ea1a 389 /**
NYX 0:85b3fd62ea1a 390 * @brief Get serial protocol used
NYX 0:85b3fd62ea1a 391 * @rmtoll CR2 FRF LL_SPI_GetStandard
NYX 0:85b3fd62ea1a 392 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 393 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 394 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
NYX 0:85b3fd62ea1a 395 * @arg @ref LL_SPI_PROTOCOL_TI
NYX 0:85b3fd62ea1a 396 */
NYX 0:85b3fd62ea1a 397 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 398 {
NYX 0:85b3fd62ea1a 399 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
NYX 0:85b3fd62ea1a 400 }
NYX 0:85b3fd62ea1a 401
NYX 0:85b3fd62ea1a 402 /**
NYX 0:85b3fd62ea1a 403 * @brief Set clock phase
NYX 0:85b3fd62ea1a 404 * @note This bit should not be changed when communication is ongoing.
NYX 0:85b3fd62ea1a 405 * This bit is not used in SPI TI mode.
NYX 0:85b3fd62ea1a 406 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
NYX 0:85b3fd62ea1a 407 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 408 * @param ClockPhase This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 409 * @arg @ref LL_SPI_PHASE_1EDGE
NYX 0:85b3fd62ea1a 410 * @arg @ref LL_SPI_PHASE_2EDGE
NYX 0:85b3fd62ea1a 411 * @retval None
NYX 0:85b3fd62ea1a 412 */
NYX 0:85b3fd62ea1a 413 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
NYX 0:85b3fd62ea1a 414 {
NYX 0:85b3fd62ea1a 415 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
NYX 0:85b3fd62ea1a 416 }
NYX 0:85b3fd62ea1a 417
NYX 0:85b3fd62ea1a 418 /**
NYX 0:85b3fd62ea1a 419 * @brief Get clock phase
NYX 0:85b3fd62ea1a 420 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
NYX 0:85b3fd62ea1a 421 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 422 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 423 * @arg @ref LL_SPI_PHASE_1EDGE
NYX 0:85b3fd62ea1a 424 * @arg @ref LL_SPI_PHASE_2EDGE
NYX 0:85b3fd62ea1a 425 */
NYX 0:85b3fd62ea1a 426 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 427 {
NYX 0:85b3fd62ea1a 428 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
NYX 0:85b3fd62ea1a 429 }
NYX 0:85b3fd62ea1a 430
NYX 0:85b3fd62ea1a 431 /**
NYX 0:85b3fd62ea1a 432 * @brief Set clock polarity
NYX 0:85b3fd62ea1a 433 * @note This bit should not be changed when communication is ongoing.
NYX 0:85b3fd62ea1a 434 * This bit is not used in SPI TI mode.
NYX 0:85b3fd62ea1a 435 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
NYX 0:85b3fd62ea1a 436 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 437 * @param ClockPolarity This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 438 * @arg @ref LL_SPI_POLARITY_LOW
NYX 0:85b3fd62ea1a 439 * @arg @ref LL_SPI_POLARITY_HIGH
NYX 0:85b3fd62ea1a 440 * @retval None
NYX 0:85b3fd62ea1a 441 */
NYX 0:85b3fd62ea1a 442 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
NYX 0:85b3fd62ea1a 443 {
NYX 0:85b3fd62ea1a 444 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
NYX 0:85b3fd62ea1a 445 }
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 /**
NYX 0:85b3fd62ea1a 448 * @brief Get clock polarity
NYX 0:85b3fd62ea1a 449 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
NYX 0:85b3fd62ea1a 450 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 451 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 452 * @arg @ref LL_SPI_POLARITY_LOW
NYX 0:85b3fd62ea1a 453 * @arg @ref LL_SPI_POLARITY_HIGH
NYX 0:85b3fd62ea1a 454 */
NYX 0:85b3fd62ea1a 455 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 456 {
NYX 0:85b3fd62ea1a 457 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
NYX 0:85b3fd62ea1a 458 }
NYX 0:85b3fd62ea1a 459
NYX 0:85b3fd62ea1a 460 /**
NYX 0:85b3fd62ea1a 461 * @brief Set baud rate prescaler
NYX 0:85b3fd62ea1a 462 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
NYX 0:85b3fd62ea1a 463 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
NYX 0:85b3fd62ea1a 464 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 465 * @param BaudRate This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 466 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
NYX 0:85b3fd62ea1a 467 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
NYX 0:85b3fd62ea1a 468 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
NYX 0:85b3fd62ea1a 469 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
NYX 0:85b3fd62ea1a 470 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
NYX 0:85b3fd62ea1a 471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
NYX 0:85b3fd62ea1a 472 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
NYX 0:85b3fd62ea1a 473 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
NYX 0:85b3fd62ea1a 474 * @retval None
NYX 0:85b3fd62ea1a 475 */
NYX 0:85b3fd62ea1a 476 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
NYX 0:85b3fd62ea1a 477 {
NYX 0:85b3fd62ea1a 478 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
NYX 0:85b3fd62ea1a 479 }
NYX 0:85b3fd62ea1a 480
NYX 0:85b3fd62ea1a 481 /**
NYX 0:85b3fd62ea1a 482 * @brief Get baud rate prescaler
NYX 0:85b3fd62ea1a 483 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
NYX 0:85b3fd62ea1a 484 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 485 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 486 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
NYX 0:85b3fd62ea1a 487 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
NYX 0:85b3fd62ea1a 488 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
NYX 0:85b3fd62ea1a 489 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
NYX 0:85b3fd62ea1a 490 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
NYX 0:85b3fd62ea1a 491 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
NYX 0:85b3fd62ea1a 492 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
NYX 0:85b3fd62ea1a 493 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
NYX 0:85b3fd62ea1a 494 */
NYX 0:85b3fd62ea1a 495 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 496 {
NYX 0:85b3fd62ea1a 497 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
NYX 0:85b3fd62ea1a 498 }
NYX 0:85b3fd62ea1a 499
NYX 0:85b3fd62ea1a 500 /**
NYX 0:85b3fd62ea1a 501 * @brief Set transfer bit order
NYX 0:85b3fd62ea1a 502 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
NYX 0:85b3fd62ea1a 503 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
NYX 0:85b3fd62ea1a 504 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 505 * @param BitOrder This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 506 * @arg @ref LL_SPI_LSB_FIRST
NYX 0:85b3fd62ea1a 507 * @arg @ref LL_SPI_MSB_FIRST
NYX 0:85b3fd62ea1a 508 * @retval None
NYX 0:85b3fd62ea1a 509 */
NYX 0:85b3fd62ea1a 510 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
NYX 0:85b3fd62ea1a 511 {
NYX 0:85b3fd62ea1a 512 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
NYX 0:85b3fd62ea1a 513 }
NYX 0:85b3fd62ea1a 514
NYX 0:85b3fd62ea1a 515 /**
NYX 0:85b3fd62ea1a 516 * @brief Get transfer bit order
NYX 0:85b3fd62ea1a 517 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
NYX 0:85b3fd62ea1a 518 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 519 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 520 * @arg @ref LL_SPI_LSB_FIRST
NYX 0:85b3fd62ea1a 521 * @arg @ref LL_SPI_MSB_FIRST
NYX 0:85b3fd62ea1a 522 */
NYX 0:85b3fd62ea1a 523 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 524 {
NYX 0:85b3fd62ea1a 525 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
NYX 0:85b3fd62ea1a 526 }
NYX 0:85b3fd62ea1a 527
NYX 0:85b3fd62ea1a 528 /**
NYX 0:85b3fd62ea1a 529 * @brief Set transfer direction mode
NYX 0:85b3fd62ea1a 530 * @note For Half-Duplex mode, Rx Direction is set by default.
NYX 0:85b3fd62ea1a 531 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
NYX 0:85b3fd62ea1a 532 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
NYX 0:85b3fd62ea1a 533 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
NYX 0:85b3fd62ea1a 534 * CR1 BIDIOE LL_SPI_SetTransferDirection
NYX 0:85b3fd62ea1a 535 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 536 * @param TransferDirection This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 537 * @arg @ref LL_SPI_FULL_DUPLEX
NYX 0:85b3fd62ea1a 538 * @arg @ref LL_SPI_SIMPLEX_RX
NYX 0:85b3fd62ea1a 539 * @arg @ref LL_SPI_HALF_DUPLEX_RX
NYX 0:85b3fd62ea1a 540 * @arg @ref LL_SPI_HALF_DUPLEX_TX
NYX 0:85b3fd62ea1a 541 * @retval None
NYX 0:85b3fd62ea1a 542 */
NYX 0:85b3fd62ea1a 543 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
NYX 0:85b3fd62ea1a 544 {
NYX 0:85b3fd62ea1a 545 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
NYX 0:85b3fd62ea1a 546 }
NYX 0:85b3fd62ea1a 547
NYX 0:85b3fd62ea1a 548 /**
NYX 0:85b3fd62ea1a 549 * @brief Get transfer direction mode
NYX 0:85b3fd62ea1a 550 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
NYX 0:85b3fd62ea1a 551 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
NYX 0:85b3fd62ea1a 552 * CR1 BIDIOE LL_SPI_GetTransferDirection
NYX 0:85b3fd62ea1a 553 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 554 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 555 * @arg @ref LL_SPI_FULL_DUPLEX
NYX 0:85b3fd62ea1a 556 * @arg @ref LL_SPI_SIMPLEX_RX
NYX 0:85b3fd62ea1a 557 * @arg @ref LL_SPI_HALF_DUPLEX_RX
NYX 0:85b3fd62ea1a 558 * @arg @ref LL_SPI_HALF_DUPLEX_TX
NYX 0:85b3fd62ea1a 559 */
NYX 0:85b3fd62ea1a 560 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 561 {
NYX 0:85b3fd62ea1a 562 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
NYX 0:85b3fd62ea1a 563 }
NYX 0:85b3fd62ea1a 564
NYX 0:85b3fd62ea1a 565 /**
NYX 0:85b3fd62ea1a 566 * @brief Set frame data width
NYX 0:85b3fd62ea1a 567 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
NYX 0:85b3fd62ea1a 568 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 569 * @param DataWidth This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 570 * @arg @ref LL_SPI_DATAWIDTH_8BIT
NYX 0:85b3fd62ea1a 571 * @arg @ref LL_SPI_DATAWIDTH_16BIT
NYX 0:85b3fd62ea1a 572 * @retval None
NYX 0:85b3fd62ea1a 573 */
NYX 0:85b3fd62ea1a 574 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
NYX 0:85b3fd62ea1a 575 {
NYX 0:85b3fd62ea1a 576 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
NYX 0:85b3fd62ea1a 577 }
NYX 0:85b3fd62ea1a 578
NYX 0:85b3fd62ea1a 579 /**
NYX 0:85b3fd62ea1a 580 * @brief Get frame data width
NYX 0:85b3fd62ea1a 581 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
NYX 0:85b3fd62ea1a 582 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 583 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 584 * @arg @ref LL_SPI_DATAWIDTH_8BIT
NYX 0:85b3fd62ea1a 585 * @arg @ref LL_SPI_DATAWIDTH_16BIT
NYX 0:85b3fd62ea1a 586 */
NYX 0:85b3fd62ea1a 587 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 588 {
NYX 0:85b3fd62ea1a 589 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
NYX 0:85b3fd62ea1a 590 }
NYX 0:85b3fd62ea1a 591
NYX 0:85b3fd62ea1a 592 /**
NYX 0:85b3fd62ea1a 593 * @}
NYX 0:85b3fd62ea1a 594 */
NYX 0:85b3fd62ea1a 595
NYX 0:85b3fd62ea1a 596 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
NYX 0:85b3fd62ea1a 597 * @{
NYX 0:85b3fd62ea1a 598 */
NYX 0:85b3fd62ea1a 599
NYX 0:85b3fd62ea1a 600 /**
NYX 0:85b3fd62ea1a 601 * @brief Enable CRC
NYX 0:85b3fd62ea1a 602 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
NYX 0:85b3fd62ea1a 603 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
NYX 0:85b3fd62ea1a 604 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 605 * @retval None
NYX 0:85b3fd62ea1a 606 */
NYX 0:85b3fd62ea1a 607 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 608 {
NYX 0:85b3fd62ea1a 609 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
NYX 0:85b3fd62ea1a 610 }
NYX 0:85b3fd62ea1a 611
NYX 0:85b3fd62ea1a 612 /**
NYX 0:85b3fd62ea1a 613 * @brief Disable CRC
NYX 0:85b3fd62ea1a 614 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
NYX 0:85b3fd62ea1a 615 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
NYX 0:85b3fd62ea1a 616 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 617 * @retval None
NYX 0:85b3fd62ea1a 618 */
NYX 0:85b3fd62ea1a 619 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 620 {
NYX 0:85b3fd62ea1a 621 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
NYX 0:85b3fd62ea1a 622 }
NYX 0:85b3fd62ea1a 623
NYX 0:85b3fd62ea1a 624 /**
NYX 0:85b3fd62ea1a 625 * @brief Check if CRC is enabled
NYX 0:85b3fd62ea1a 626 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
NYX 0:85b3fd62ea1a 627 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
NYX 0:85b3fd62ea1a 628 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 629 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 630 */
NYX 0:85b3fd62ea1a 631 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 632 {
NYX 0:85b3fd62ea1a 633 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
NYX 0:85b3fd62ea1a 634 }
NYX 0:85b3fd62ea1a 635
NYX 0:85b3fd62ea1a 636 /**
NYX 0:85b3fd62ea1a 637 * @brief Set CRCNext to transfer CRC on the line
NYX 0:85b3fd62ea1a 638 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
NYX 0:85b3fd62ea1a 639 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
NYX 0:85b3fd62ea1a 640 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 641 * @retval None
NYX 0:85b3fd62ea1a 642 */
NYX 0:85b3fd62ea1a 643 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 644 {
NYX 0:85b3fd62ea1a 645 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
NYX 0:85b3fd62ea1a 646 }
NYX 0:85b3fd62ea1a 647
NYX 0:85b3fd62ea1a 648 /**
NYX 0:85b3fd62ea1a 649 * @brief Set polynomial for CRC calculation
NYX 0:85b3fd62ea1a 650 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
NYX 0:85b3fd62ea1a 651 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 652 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
NYX 0:85b3fd62ea1a 653 * @retval None
NYX 0:85b3fd62ea1a 654 */
NYX 0:85b3fd62ea1a 655 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
NYX 0:85b3fd62ea1a 656 {
NYX 0:85b3fd62ea1a 657 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
NYX 0:85b3fd62ea1a 658 }
NYX 0:85b3fd62ea1a 659
NYX 0:85b3fd62ea1a 660 /**
NYX 0:85b3fd62ea1a 661 * @brief Get polynomial for CRC calculation
NYX 0:85b3fd62ea1a 662 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
NYX 0:85b3fd62ea1a 663 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 664 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
NYX 0:85b3fd62ea1a 665 */
NYX 0:85b3fd62ea1a 666 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 667 {
NYX 0:85b3fd62ea1a 668 return (uint32_t)(READ_REG(SPIx->CRCPR));
NYX 0:85b3fd62ea1a 669 }
NYX 0:85b3fd62ea1a 670
NYX 0:85b3fd62ea1a 671 /**
NYX 0:85b3fd62ea1a 672 * @brief Get Rx CRC
NYX 0:85b3fd62ea1a 673 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
NYX 0:85b3fd62ea1a 674 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 675 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
NYX 0:85b3fd62ea1a 676 */
NYX 0:85b3fd62ea1a 677 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 678 {
NYX 0:85b3fd62ea1a 679 return (uint32_t)(READ_REG(SPIx->RXCRCR));
NYX 0:85b3fd62ea1a 680 }
NYX 0:85b3fd62ea1a 681
NYX 0:85b3fd62ea1a 682 /**
NYX 0:85b3fd62ea1a 683 * @brief Get Tx CRC
NYX 0:85b3fd62ea1a 684 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
NYX 0:85b3fd62ea1a 685 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 686 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
NYX 0:85b3fd62ea1a 687 */
NYX 0:85b3fd62ea1a 688 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 689 {
NYX 0:85b3fd62ea1a 690 return (uint32_t)(READ_REG(SPIx->TXCRCR));
NYX 0:85b3fd62ea1a 691 }
NYX 0:85b3fd62ea1a 692
NYX 0:85b3fd62ea1a 693 /**
NYX 0:85b3fd62ea1a 694 * @}
NYX 0:85b3fd62ea1a 695 */
NYX 0:85b3fd62ea1a 696
NYX 0:85b3fd62ea1a 697 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
NYX 0:85b3fd62ea1a 698 * @{
NYX 0:85b3fd62ea1a 699 */
NYX 0:85b3fd62ea1a 700
NYX 0:85b3fd62ea1a 701 /**
NYX 0:85b3fd62ea1a 702 * @brief Set NSS mode
NYX 0:85b3fd62ea1a 703 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
NYX 0:85b3fd62ea1a 704 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
NYX 0:85b3fd62ea1a 705 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
NYX 0:85b3fd62ea1a 706 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 707 * @param NSS This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 708 * @arg @ref LL_SPI_NSS_SOFT
NYX 0:85b3fd62ea1a 709 * @arg @ref LL_SPI_NSS_HARD_INPUT
NYX 0:85b3fd62ea1a 710 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
NYX 0:85b3fd62ea1a 711 * @retval None
NYX 0:85b3fd62ea1a 712 */
NYX 0:85b3fd62ea1a 713 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
NYX 0:85b3fd62ea1a 714 {
NYX 0:85b3fd62ea1a 715 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
NYX 0:85b3fd62ea1a 716 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
NYX 0:85b3fd62ea1a 717 }
NYX 0:85b3fd62ea1a 718
NYX 0:85b3fd62ea1a 719 /**
NYX 0:85b3fd62ea1a 720 * @brief Get NSS mode
NYX 0:85b3fd62ea1a 721 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
NYX 0:85b3fd62ea1a 722 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
NYX 0:85b3fd62ea1a 723 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 724 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 725 * @arg @ref LL_SPI_NSS_SOFT
NYX 0:85b3fd62ea1a 726 * @arg @ref LL_SPI_NSS_HARD_INPUT
NYX 0:85b3fd62ea1a 727 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
NYX 0:85b3fd62ea1a 728 */
NYX 0:85b3fd62ea1a 729 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 730 {
NYX 0:85b3fd62ea1a 731 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
NYX 0:85b3fd62ea1a 732 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
NYX 0:85b3fd62ea1a 733 return (Ssm | Ssoe);
NYX 0:85b3fd62ea1a 734 }
NYX 0:85b3fd62ea1a 735
NYX 0:85b3fd62ea1a 736 /**
NYX 0:85b3fd62ea1a 737 * @}
NYX 0:85b3fd62ea1a 738 */
NYX 0:85b3fd62ea1a 739
NYX 0:85b3fd62ea1a 740 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
NYX 0:85b3fd62ea1a 741 * @{
NYX 0:85b3fd62ea1a 742 */
NYX 0:85b3fd62ea1a 743
NYX 0:85b3fd62ea1a 744 /**
NYX 0:85b3fd62ea1a 745 * @brief Check if Rx buffer is not empty
NYX 0:85b3fd62ea1a 746 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
NYX 0:85b3fd62ea1a 747 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 748 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 749 */
NYX 0:85b3fd62ea1a 750 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 751 {
NYX 0:85b3fd62ea1a 752 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
NYX 0:85b3fd62ea1a 753 }
NYX 0:85b3fd62ea1a 754
NYX 0:85b3fd62ea1a 755 /**
NYX 0:85b3fd62ea1a 756 * @brief Check if Tx buffer is empty
NYX 0:85b3fd62ea1a 757 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
NYX 0:85b3fd62ea1a 758 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 759 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 760 */
NYX 0:85b3fd62ea1a 761 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 762 {
NYX 0:85b3fd62ea1a 763 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
NYX 0:85b3fd62ea1a 764 }
NYX 0:85b3fd62ea1a 765
NYX 0:85b3fd62ea1a 766 /**
NYX 0:85b3fd62ea1a 767 * @brief Get CRC error flag
NYX 0:85b3fd62ea1a 768 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
NYX 0:85b3fd62ea1a 769 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 770 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 771 */
NYX 0:85b3fd62ea1a 772 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 773 {
NYX 0:85b3fd62ea1a 774 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
NYX 0:85b3fd62ea1a 775 }
NYX 0:85b3fd62ea1a 776
NYX 0:85b3fd62ea1a 777 /**
NYX 0:85b3fd62ea1a 778 * @brief Get mode fault error flag
NYX 0:85b3fd62ea1a 779 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
NYX 0:85b3fd62ea1a 780 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 781 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 782 */
NYX 0:85b3fd62ea1a 783 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 784 {
NYX 0:85b3fd62ea1a 785 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
NYX 0:85b3fd62ea1a 786 }
NYX 0:85b3fd62ea1a 787
NYX 0:85b3fd62ea1a 788 /**
NYX 0:85b3fd62ea1a 789 * @brief Get overrun error flag
NYX 0:85b3fd62ea1a 790 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
NYX 0:85b3fd62ea1a 791 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 792 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 793 */
NYX 0:85b3fd62ea1a 794 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 795 {
NYX 0:85b3fd62ea1a 796 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
NYX 0:85b3fd62ea1a 797 }
NYX 0:85b3fd62ea1a 798
NYX 0:85b3fd62ea1a 799 /**
NYX 0:85b3fd62ea1a 800 * @brief Get busy flag
NYX 0:85b3fd62ea1a 801 * @note The BSY flag is cleared under any one of the following conditions:
NYX 0:85b3fd62ea1a 802 * -When the SPI is correctly disabled
NYX 0:85b3fd62ea1a 803 * -When a fault is detected in Master mode (MODF bit set to 1)
NYX 0:85b3fd62ea1a 804 * -In Master mode, when it finishes a data transmission and no new data is ready to be
NYX 0:85b3fd62ea1a 805 * sent
NYX 0:85b3fd62ea1a 806 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
NYX 0:85b3fd62ea1a 807 * each data transfer.
NYX 0:85b3fd62ea1a 808 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
NYX 0:85b3fd62ea1a 809 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 810 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 811 */
NYX 0:85b3fd62ea1a 812 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 813 {
NYX 0:85b3fd62ea1a 814 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
NYX 0:85b3fd62ea1a 815 }
NYX 0:85b3fd62ea1a 816
NYX 0:85b3fd62ea1a 817 /**
NYX 0:85b3fd62ea1a 818 * @brief Get frame format error flag
NYX 0:85b3fd62ea1a 819 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
NYX 0:85b3fd62ea1a 820 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 821 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 822 */
NYX 0:85b3fd62ea1a 823 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 824 {
NYX 0:85b3fd62ea1a 825 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
NYX 0:85b3fd62ea1a 826 }
NYX 0:85b3fd62ea1a 827
NYX 0:85b3fd62ea1a 828 /**
NYX 0:85b3fd62ea1a 829 * @brief Clear CRC error flag
NYX 0:85b3fd62ea1a 830 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
NYX 0:85b3fd62ea1a 831 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 832 * @retval None
NYX 0:85b3fd62ea1a 833 */
NYX 0:85b3fd62ea1a 834 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 835 {
NYX 0:85b3fd62ea1a 836 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
NYX 0:85b3fd62ea1a 837 }
NYX 0:85b3fd62ea1a 838
NYX 0:85b3fd62ea1a 839 /**
NYX 0:85b3fd62ea1a 840 * @brief Clear mode fault error flag
NYX 0:85b3fd62ea1a 841 * @note Clearing this flag is done by a read access to the SPIx_SR
NYX 0:85b3fd62ea1a 842 * register followed by a write access to the SPIx_CR1 register
NYX 0:85b3fd62ea1a 843 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
NYX 0:85b3fd62ea1a 844 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 845 * @retval None
NYX 0:85b3fd62ea1a 846 */
NYX 0:85b3fd62ea1a 847 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 848 {
NYX 0:85b3fd62ea1a 849 __IO uint32_t tmpreg;
NYX 0:85b3fd62ea1a 850 tmpreg = SPIx->SR;
NYX 0:85b3fd62ea1a 851 (void) tmpreg;
NYX 0:85b3fd62ea1a 852 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
NYX 0:85b3fd62ea1a 853 (void) tmpreg;
NYX 0:85b3fd62ea1a 854 }
NYX 0:85b3fd62ea1a 855
NYX 0:85b3fd62ea1a 856 /**
NYX 0:85b3fd62ea1a 857 * @brief Clear overrun error flag
NYX 0:85b3fd62ea1a 858 * @note Clearing this flag is done by a read access to the SPIx_DR
NYX 0:85b3fd62ea1a 859 * register followed by a read access to the SPIx_SR register
NYX 0:85b3fd62ea1a 860 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
NYX 0:85b3fd62ea1a 861 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 862 * @retval None
NYX 0:85b3fd62ea1a 863 */
NYX 0:85b3fd62ea1a 864 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 865 {
NYX 0:85b3fd62ea1a 866 __IO uint32_t tmpreg;
NYX 0:85b3fd62ea1a 867 tmpreg = SPIx->DR;
NYX 0:85b3fd62ea1a 868 (void) tmpreg;
NYX 0:85b3fd62ea1a 869 tmpreg = SPIx->SR;
NYX 0:85b3fd62ea1a 870 (void) tmpreg;
NYX 0:85b3fd62ea1a 871 }
NYX 0:85b3fd62ea1a 872
NYX 0:85b3fd62ea1a 873 /**
NYX 0:85b3fd62ea1a 874 * @brief Clear frame format error flag
NYX 0:85b3fd62ea1a 875 * @note Clearing this flag is done by reading SPIx_SR register
NYX 0:85b3fd62ea1a 876 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
NYX 0:85b3fd62ea1a 877 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 878 * @retval None
NYX 0:85b3fd62ea1a 879 */
NYX 0:85b3fd62ea1a 880 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 881 {
NYX 0:85b3fd62ea1a 882 __IO uint32_t tmpreg;
NYX 0:85b3fd62ea1a 883 tmpreg = SPIx->SR;
NYX 0:85b3fd62ea1a 884 (void) tmpreg;
NYX 0:85b3fd62ea1a 885 }
NYX 0:85b3fd62ea1a 886
NYX 0:85b3fd62ea1a 887 /**
NYX 0:85b3fd62ea1a 888 * @}
NYX 0:85b3fd62ea1a 889 */
NYX 0:85b3fd62ea1a 890
NYX 0:85b3fd62ea1a 891 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
NYX 0:85b3fd62ea1a 892 * @{
NYX 0:85b3fd62ea1a 893 */
NYX 0:85b3fd62ea1a 894
NYX 0:85b3fd62ea1a 895 /**
NYX 0:85b3fd62ea1a 896 * @brief Enable error interrupt
NYX 0:85b3fd62ea1a 897 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
NYX 0:85b3fd62ea1a 898 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
NYX 0:85b3fd62ea1a 899 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 900 * @retval None
NYX 0:85b3fd62ea1a 901 */
NYX 0:85b3fd62ea1a 902 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 903 {
NYX 0:85b3fd62ea1a 904 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
NYX 0:85b3fd62ea1a 905 }
NYX 0:85b3fd62ea1a 906
NYX 0:85b3fd62ea1a 907 /**
NYX 0:85b3fd62ea1a 908 * @brief Enable Rx buffer not empty interrupt
NYX 0:85b3fd62ea1a 909 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
NYX 0:85b3fd62ea1a 910 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 911 * @retval None
NYX 0:85b3fd62ea1a 912 */
NYX 0:85b3fd62ea1a 913 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 914 {
NYX 0:85b3fd62ea1a 915 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
NYX 0:85b3fd62ea1a 916 }
NYX 0:85b3fd62ea1a 917
NYX 0:85b3fd62ea1a 918 /**
NYX 0:85b3fd62ea1a 919 * @brief Enable Tx buffer empty interrupt
NYX 0:85b3fd62ea1a 920 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
NYX 0:85b3fd62ea1a 921 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 922 * @retval None
NYX 0:85b3fd62ea1a 923 */
NYX 0:85b3fd62ea1a 924 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 925 {
NYX 0:85b3fd62ea1a 926 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
NYX 0:85b3fd62ea1a 927 }
NYX 0:85b3fd62ea1a 928
NYX 0:85b3fd62ea1a 929 /**
NYX 0:85b3fd62ea1a 930 * @brief Disable error interrupt
NYX 0:85b3fd62ea1a 931 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
NYX 0:85b3fd62ea1a 932 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
NYX 0:85b3fd62ea1a 933 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 934 * @retval None
NYX 0:85b3fd62ea1a 935 */
NYX 0:85b3fd62ea1a 936 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 937 {
NYX 0:85b3fd62ea1a 938 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
NYX 0:85b3fd62ea1a 939 }
NYX 0:85b3fd62ea1a 940
NYX 0:85b3fd62ea1a 941 /**
NYX 0:85b3fd62ea1a 942 * @brief Disable Rx buffer not empty interrupt
NYX 0:85b3fd62ea1a 943 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
NYX 0:85b3fd62ea1a 944 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 945 * @retval None
NYX 0:85b3fd62ea1a 946 */
NYX 0:85b3fd62ea1a 947 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 948 {
NYX 0:85b3fd62ea1a 949 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
NYX 0:85b3fd62ea1a 950 }
NYX 0:85b3fd62ea1a 951
NYX 0:85b3fd62ea1a 952 /**
NYX 0:85b3fd62ea1a 953 * @brief Disable Tx buffer empty interrupt
NYX 0:85b3fd62ea1a 954 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
NYX 0:85b3fd62ea1a 955 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 956 * @retval None
NYX 0:85b3fd62ea1a 957 */
NYX 0:85b3fd62ea1a 958 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 959 {
NYX 0:85b3fd62ea1a 960 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
NYX 0:85b3fd62ea1a 961 }
NYX 0:85b3fd62ea1a 962
NYX 0:85b3fd62ea1a 963 /**
NYX 0:85b3fd62ea1a 964 * @brief Check if error interrupt is enabled
NYX 0:85b3fd62ea1a 965 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
NYX 0:85b3fd62ea1a 966 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 967 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 968 */
NYX 0:85b3fd62ea1a 969 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 970 {
NYX 0:85b3fd62ea1a 971 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
NYX 0:85b3fd62ea1a 972 }
NYX 0:85b3fd62ea1a 973
NYX 0:85b3fd62ea1a 974 /**
NYX 0:85b3fd62ea1a 975 * @brief Check if Rx buffer not empty interrupt is enabled
NYX 0:85b3fd62ea1a 976 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
NYX 0:85b3fd62ea1a 977 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 978 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 979 */
NYX 0:85b3fd62ea1a 980 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 981 {
NYX 0:85b3fd62ea1a 982 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
NYX 0:85b3fd62ea1a 983 }
NYX 0:85b3fd62ea1a 984
NYX 0:85b3fd62ea1a 985 /**
NYX 0:85b3fd62ea1a 986 * @brief Check if Tx buffer empty interrupt
NYX 0:85b3fd62ea1a 987 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
NYX 0:85b3fd62ea1a 988 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 989 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 990 */
NYX 0:85b3fd62ea1a 991 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 992 {
NYX 0:85b3fd62ea1a 993 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
NYX 0:85b3fd62ea1a 994 }
NYX 0:85b3fd62ea1a 995
NYX 0:85b3fd62ea1a 996 /**
NYX 0:85b3fd62ea1a 997 * @}
NYX 0:85b3fd62ea1a 998 */
NYX 0:85b3fd62ea1a 999
NYX 0:85b3fd62ea1a 1000 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
NYX 0:85b3fd62ea1a 1001 * @{
NYX 0:85b3fd62ea1a 1002 */
NYX 0:85b3fd62ea1a 1003
NYX 0:85b3fd62ea1a 1004 /**
NYX 0:85b3fd62ea1a 1005 * @brief Enable DMA Rx
NYX 0:85b3fd62ea1a 1006 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
NYX 0:85b3fd62ea1a 1007 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1008 * @retval None
NYX 0:85b3fd62ea1a 1009 */
NYX 0:85b3fd62ea1a 1010 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1011 {
NYX 0:85b3fd62ea1a 1012 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 1013 }
NYX 0:85b3fd62ea1a 1014
NYX 0:85b3fd62ea1a 1015 /**
NYX 0:85b3fd62ea1a 1016 * @brief Disable DMA Rx
NYX 0:85b3fd62ea1a 1017 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
NYX 0:85b3fd62ea1a 1018 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1019 * @retval None
NYX 0:85b3fd62ea1a 1020 */
NYX 0:85b3fd62ea1a 1021 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1022 {
NYX 0:85b3fd62ea1a 1023 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
NYX 0:85b3fd62ea1a 1024 }
NYX 0:85b3fd62ea1a 1025
NYX 0:85b3fd62ea1a 1026 /**
NYX 0:85b3fd62ea1a 1027 * @brief Check if DMA Rx is enabled
NYX 0:85b3fd62ea1a 1028 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
NYX 0:85b3fd62ea1a 1029 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1030 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1031 */
NYX 0:85b3fd62ea1a 1032 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1033 {
NYX 0:85b3fd62ea1a 1034 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
NYX 0:85b3fd62ea1a 1035 }
NYX 0:85b3fd62ea1a 1036
NYX 0:85b3fd62ea1a 1037 /**
NYX 0:85b3fd62ea1a 1038 * @brief Enable DMA Tx
NYX 0:85b3fd62ea1a 1039 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
NYX 0:85b3fd62ea1a 1040 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1041 * @retval None
NYX 0:85b3fd62ea1a 1042 */
NYX 0:85b3fd62ea1a 1043 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1044 {
NYX 0:85b3fd62ea1a 1045 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 1046 }
NYX 0:85b3fd62ea1a 1047
NYX 0:85b3fd62ea1a 1048 /**
NYX 0:85b3fd62ea1a 1049 * @brief Disable DMA Tx
NYX 0:85b3fd62ea1a 1050 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
NYX 0:85b3fd62ea1a 1051 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1052 * @retval None
NYX 0:85b3fd62ea1a 1053 */
NYX 0:85b3fd62ea1a 1054 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1055 {
NYX 0:85b3fd62ea1a 1056 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
NYX 0:85b3fd62ea1a 1057 }
NYX 0:85b3fd62ea1a 1058
NYX 0:85b3fd62ea1a 1059 /**
NYX 0:85b3fd62ea1a 1060 * @brief Check if DMA Tx is enabled
NYX 0:85b3fd62ea1a 1061 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
NYX 0:85b3fd62ea1a 1062 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1063 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1064 */
NYX 0:85b3fd62ea1a 1065 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1066 {
NYX 0:85b3fd62ea1a 1067 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
NYX 0:85b3fd62ea1a 1068 }
NYX 0:85b3fd62ea1a 1069
NYX 0:85b3fd62ea1a 1070 /**
NYX 0:85b3fd62ea1a 1071 * @brief Get the data register address used for DMA transfer
NYX 0:85b3fd62ea1a 1072 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
NYX 0:85b3fd62ea1a 1073 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1074 * @retval Address of data register
NYX 0:85b3fd62ea1a 1075 */
NYX 0:85b3fd62ea1a 1076 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1077 {
NYX 0:85b3fd62ea1a 1078 return (uint32_t) & (SPIx->DR);
NYX 0:85b3fd62ea1a 1079 }
NYX 0:85b3fd62ea1a 1080
NYX 0:85b3fd62ea1a 1081 /**
NYX 0:85b3fd62ea1a 1082 * @}
NYX 0:85b3fd62ea1a 1083 */
NYX 0:85b3fd62ea1a 1084
NYX 0:85b3fd62ea1a 1085 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
NYX 0:85b3fd62ea1a 1086 * @{
NYX 0:85b3fd62ea1a 1087 */
NYX 0:85b3fd62ea1a 1088
NYX 0:85b3fd62ea1a 1089 /**
NYX 0:85b3fd62ea1a 1090 * @brief Read 8-Bits in the data register
NYX 0:85b3fd62ea1a 1091 * @rmtoll DR DR LL_SPI_ReceiveData8
NYX 0:85b3fd62ea1a 1092 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1093 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
NYX 0:85b3fd62ea1a 1094 */
NYX 0:85b3fd62ea1a 1095 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1096 {
NYX 0:85b3fd62ea1a 1097 return (uint8_t)(READ_REG(SPIx->DR));
NYX 0:85b3fd62ea1a 1098 }
NYX 0:85b3fd62ea1a 1099
NYX 0:85b3fd62ea1a 1100 /**
NYX 0:85b3fd62ea1a 1101 * @brief Read 16-Bits in the data register
NYX 0:85b3fd62ea1a 1102 * @rmtoll DR DR LL_SPI_ReceiveData16
NYX 0:85b3fd62ea1a 1103 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1104 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
NYX 0:85b3fd62ea1a 1105 */
NYX 0:85b3fd62ea1a 1106 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1107 {
NYX 0:85b3fd62ea1a 1108 return (uint16_t)(READ_REG(SPIx->DR));
NYX 0:85b3fd62ea1a 1109 }
NYX 0:85b3fd62ea1a 1110
NYX 0:85b3fd62ea1a 1111 /**
NYX 0:85b3fd62ea1a 1112 * @brief Write 8-Bits in the data register
NYX 0:85b3fd62ea1a 1113 * @rmtoll DR DR LL_SPI_TransmitData8
NYX 0:85b3fd62ea1a 1114 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1115 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
NYX 0:85b3fd62ea1a 1116 * @retval None
NYX 0:85b3fd62ea1a 1117 */
NYX 0:85b3fd62ea1a 1118 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
NYX 0:85b3fd62ea1a 1119 {
NYX 0:85b3fd62ea1a 1120 SPIx->DR = TxData;
NYX 0:85b3fd62ea1a 1121 }
NYX 0:85b3fd62ea1a 1122
NYX 0:85b3fd62ea1a 1123 /**
NYX 0:85b3fd62ea1a 1124 * @brief Write 16-Bits in the data register
NYX 0:85b3fd62ea1a 1125 * @rmtoll DR DR LL_SPI_TransmitData16
NYX 0:85b3fd62ea1a 1126 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1127 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
NYX 0:85b3fd62ea1a 1128 * @retval None
NYX 0:85b3fd62ea1a 1129 */
NYX 0:85b3fd62ea1a 1130 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
NYX 0:85b3fd62ea1a 1131 {
NYX 0:85b3fd62ea1a 1132 SPIx->DR = TxData;
NYX 0:85b3fd62ea1a 1133 }
NYX 0:85b3fd62ea1a 1134
NYX 0:85b3fd62ea1a 1135 /**
NYX 0:85b3fd62ea1a 1136 * @}
NYX 0:85b3fd62ea1a 1137 */
NYX 0:85b3fd62ea1a 1138 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 1139 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 1140 * @{
NYX 0:85b3fd62ea1a 1141 */
NYX 0:85b3fd62ea1a 1142
NYX 0:85b3fd62ea1a 1143 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
NYX 0:85b3fd62ea1a 1144 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
NYX 0:85b3fd62ea1a 1145 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
NYX 0:85b3fd62ea1a 1146
NYX 0:85b3fd62ea1a 1147 /**
NYX 0:85b3fd62ea1a 1148 * @}
NYX 0:85b3fd62ea1a 1149 */
NYX 0:85b3fd62ea1a 1150 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 1151 /**
NYX 0:85b3fd62ea1a 1152 * @}
NYX 0:85b3fd62ea1a 1153 */
NYX 0:85b3fd62ea1a 1154
NYX 0:85b3fd62ea1a 1155 /**
NYX 0:85b3fd62ea1a 1156 * @}
NYX 0:85b3fd62ea1a 1157 */
NYX 0:85b3fd62ea1a 1158
NYX 0:85b3fd62ea1a 1159 /** @defgroup I2S_LL I2S
NYX 0:85b3fd62ea1a 1160 * @{
NYX 0:85b3fd62ea1a 1161 */
NYX 0:85b3fd62ea1a 1162
NYX 0:85b3fd62ea1a 1163 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1164 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1165 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1166
NYX 0:85b3fd62ea1a 1167 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1168 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 1169 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
NYX 0:85b3fd62ea1a 1170 * @{
NYX 0:85b3fd62ea1a 1171 */
NYX 0:85b3fd62ea1a 1172
NYX 0:85b3fd62ea1a 1173 /**
NYX 0:85b3fd62ea1a 1174 * @brief I2S Init structure definition
NYX 0:85b3fd62ea1a 1175 */
NYX 0:85b3fd62ea1a 1176
NYX 0:85b3fd62ea1a 1177 typedef struct
NYX 0:85b3fd62ea1a 1178 {
NYX 0:85b3fd62ea1a 1179 uint32_t Mode; /*!< Specifies the I2S operating mode.
NYX 0:85b3fd62ea1a 1180 This parameter can be a value of @ref I2S_LL_EC_MODE
NYX 0:85b3fd62ea1a 1181
NYX 0:85b3fd62ea1a 1182 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
NYX 0:85b3fd62ea1a 1183
NYX 0:85b3fd62ea1a 1184 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
NYX 0:85b3fd62ea1a 1185 This parameter can be a value of @ref I2S_LL_EC_STANDARD
NYX 0:85b3fd62ea1a 1186
NYX 0:85b3fd62ea1a 1187 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
NYX 0:85b3fd62ea1a 1188
NYX 0:85b3fd62ea1a 1189
NYX 0:85b3fd62ea1a 1190 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
NYX 0:85b3fd62ea1a 1191 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
NYX 0:85b3fd62ea1a 1192
NYX 0:85b3fd62ea1a 1193 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
NYX 0:85b3fd62ea1a 1194
NYX 0:85b3fd62ea1a 1195
NYX 0:85b3fd62ea1a 1196 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
NYX 0:85b3fd62ea1a 1197 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
NYX 0:85b3fd62ea1a 1198
NYX 0:85b3fd62ea1a 1199 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
NYX 0:85b3fd62ea1a 1200
NYX 0:85b3fd62ea1a 1201
NYX 0:85b3fd62ea1a 1202 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
NYX 0:85b3fd62ea1a 1203 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
NYX 0:85b3fd62ea1a 1204
NYX 0:85b3fd62ea1a 1205 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
NYX 0:85b3fd62ea1a 1206 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
NYX 0:85b3fd62ea1a 1207
NYX 0:85b3fd62ea1a 1208
NYX 0:85b3fd62ea1a 1209 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
NYX 0:85b3fd62ea1a 1210 This parameter can be a value of @ref I2S_LL_EC_POLARITY
NYX 0:85b3fd62ea1a 1211
NYX 0:85b3fd62ea1a 1212 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
NYX 0:85b3fd62ea1a 1213
NYX 0:85b3fd62ea1a 1214 } LL_I2S_InitTypeDef;
NYX 0:85b3fd62ea1a 1215
NYX 0:85b3fd62ea1a 1216 /**
NYX 0:85b3fd62ea1a 1217 * @}
NYX 0:85b3fd62ea1a 1218 */
NYX 0:85b3fd62ea1a 1219 #endif /*USE_FULL_LL_DRIVER*/
NYX 0:85b3fd62ea1a 1220
NYX 0:85b3fd62ea1a 1221 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1222 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
NYX 0:85b3fd62ea1a 1223 * @{
NYX 0:85b3fd62ea1a 1224 */
NYX 0:85b3fd62ea1a 1225
NYX 0:85b3fd62ea1a 1226 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
NYX 0:85b3fd62ea1a 1227 * @brief Flags defines which can be used with LL_I2S_ReadReg function
NYX 0:85b3fd62ea1a 1228 * @{
NYX 0:85b3fd62ea1a 1229 */
NYX 0:85b3fd62ea1a 1230 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
NYX 0:85b3fd62ea1a 1231 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
NYX 0:85b3fd62ea1a 1232 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
NYX 0:85b3fd62ea1a 1233 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
NYX 0:85b3fd62ea1a 1234 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
NYX 0:85b3fd62ea1a 1235 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
NYX 0:85b3fd62ea1a 1236 /**
NYX 0:85b3fd62ea1a 1237 * @}
NYX 0:85b3fd62ea1a 1238 */
NYX 0:85b3fd62ea1a 1239
NYX 0:85b3fd62ea1a 1240 /** @defgroup SPI_LL_EC_IT IT Defines
NYX 0:85b3fd62ea1a 1241 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
NYX 0:85b3fd62ea1a 1242 * @{
NYX 0:85b3fd62ea1a 1243 */
NYX 0:85b3fd62ea1a 1244 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
NYX 0:85b3fd62ea1a 1245 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
NYX 0:85b3fd62ea1a 1246 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
NYX 0:85b3fd62ea1a 1247 /**
NYX 0:85b3fd62ea1a 1248 * @}
NYX 0:85b3fd62ea1a 1249 */
NYX 0:85b3fd62ea1a 1250
NYX 0:85b3fd62ea1a 1251 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
NYX 0:85b3fd62ea1a 1252 * @{
NYX 0:85b3fd62ea1a 1253 */
NYX 0:85b3fd62ea1a 1254 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
NYX 0:85b3fd62ea1a 1255 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
NYX 0:85b3fd62ea1a 1256 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
NYX 0:85b3fd62ea1a 1257 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
NYX 0:85b3fd62ea1a 1258 /**
NYX 0:85b3fd62ea1a 1259 * @}
NYX 0:85b3fd62ea1a 1260 */
NYX 0:85b3fd62ea1a 1261
NYX 0:85b3fd62ea1a 1262 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
NYX 0:85b3fd62ea1a 1263 * @{
NYX 0:85b3fd62ea1a 1264 */
NYX 0:85b3fd62ea1a 1265 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
NYX 0:85b3fd62ea1a 1266 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
NYX 0:85b3fd62ea1a 1267 /**
NYX 0:85b3fd62ea1a 1268 * @}
NYX 0:85b3fd62ea1a 1269 */
NYX 0:85b3fd62ea1a 1270
NYX 0:85b3fd62ea1a 1271 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
NYX 0:85b3fd62ea1a 1272 * @{
NYX 0:85b3fd62ea1a 1273 */
NYX 0:85b3fd62ea1a 1274 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
NYX 0:85b3fd62ea1a 1275 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
NYX 0:85b3fd62ea1a 1276 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
NYX 0:85b3fd62ea1a 1277 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
NYX 0:85b3fd62ea1a 1278 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
NYX 0:85b3fd62ea1a 1279 /**
NYX 0:85b3fd62ea1a 1280 * @}
NYX 0:85b3fd62ea1a 1281 */
NYX 0:85b3fd62ea1a 1282
NYX 0:85b3fd62ea1a 1283 /** @defgroup I2S_LL_EC_MODE Operation Mode
NYX 0:85b3fd62ea1a 1284 * @{
NYX 0:85b3fd62ea1a 1285 */
NYX 0:85b3fd62ea1a 1286 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
NYX 0:85b3fd62ea1a 1287 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
NYX 0:85b3fd62ea1a 1288 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
NYX 0:85b3fd62ea1a 1289 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
NYX 0:85b3fd62ea1a 1290 /**
NYX 0:85b3fd62ea1a 1291 * @}
NYX 0:85b3fd62ea1a 1292 */
NYX 0:85b3fd62ea1a 1293
NYX 0:85b3fd62ea1a 1294 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
NYX 0:85b3fd62ea1a 1295 * @{
NYX 0:85b3fd62ea1a 1296 */
NYX 0:85b3fd62ea1a 1297 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
NYX 0:85b3fd62ea1a 1298 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
NYX 0:85b3fd62ea1a 1299 /**
NYX 0:85b3fd62ea1a 1300 * @}
NYX 0:85b3fd62ea1a 1301 */
NYX 0:85b3fd62ea1a 1302
NYX 0:85b3fd62ea1a 1303 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 1304
NYX 0:85b3fd62ea1a 1305 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
NYX 0:85b3fd62ea1a 1306 * @{
NYX 0:85b3fd62ea1a 1307 */
NYX 0:85b3fd62ea1a 1308 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
NYX 0:85b3fd62ea1a 1309 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
NYX 0:85b3fd62ea1a 1310 /**
NYX 0:85b3fd62ea1a 1311 * @}
NYX 0:85b3fd62ea1a 1312 */
NYX 0:85b3fd62ea1a 1313
NYX 0:85b3fd62ea1a 1314 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
NYX 0:85b3fd62ea1a 1315 * @{
NYX 0:85b3fd62ea1a 1316 */
NYX 0:85b3fd62ea1a 1317
NYX 0:85b3fd62ea1a 1318 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
NYX 0:85b3fd62ea1a 1319 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
NYX 0:85b3fd62ea1a 1320 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
NYX 0:85b3fd62ea1a 1321 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
NYX 0:85b3fd62ea1a 1322 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
NYX 0:85b3fd62ea1a 1323 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
NYX 0:85b3fd62ea1a 1324 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
NYX 0:85b3fd62ea1a 1325 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
NYX 0:85b3fd62ea1a 1326 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
NYX 0:85b3fd62ea1a 1327 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
NYX 0:85b3fd62ea1a 1328 /**
NYX 0:85b3fd62ea1a 1329 * @}
NYX 0:85b3fd62ea1a 1330 */
NYX 0:85b3fd62ea1a 1331 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 1332
NYX 0:85b3fd62ea1a 1333 /**
NYX 0:85b3fd62ea1a 1334 * @}
NYX 0:85b3fd62ea1a 1335 */
NYX 0:85b3fd62ea1a 1336
NYX 0:85b3fd62ea1a 1337 /* Exported macro ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1338 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
NYX 0:85b3fd62ea1a 1339 * @{
NYX 0:85b3fd62ea1a 1340 */
NYX 0:85b3fd62ea1a 1341
NYX 0:85b3fd62ea1a 1342 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
NYX 0:85b3fd62ea1a 1343 * @{
NYX 0:85b3fd62ea1a 1344 */
NYX 0:85b3fd62ea1a 1345
NYX 0:85b3fd62ea1a 1346 /**
NYX 0:85b3fd62ea1a 1347 * @brief Write a value in I2S register
NYX 0:85b3fd62ea1a 1348 * @param __INSTANCE__ I2S Instance
NYX 0:85b3fd62ea1a 1349 * @param __REG__ Register to be written
NYX 0:85b3fd62ea1a 1350 * @param __VALUE__ Value to be written in the register
NYX 0:85b3fd62ea1a 1351 * @retval None
NYX 0:85b3fd62ea1a 1352 */
NYX 0:85b3fd62ea1a 1353 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
NYX 0:85b3fd62ea1a 1354
NYX 0:85b3fd62ea1a 1355 /**
NYX 0:85b3fd62ea1a 1356 * @brief Read a value in I2S register
NYX 0:85b3fd62ea1a 1357 * @param __INSTANCE__ I2S Instance
NYX 0:85b3fd62ea1a 1358 * @param __REG__ Register to be read
NYX 0:85b3fd62ea1a 1359 * @retval Register value
NYX 0:85b3fd62ea1a 1360 */
NYX 0:85b3fd62ea1a 1361 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
NYX 0:85b3fd62ea1a 1362 /**
NYX 0:85b3fd62ea1a 1363 * @}
NYX 0:85b3fd62ea1a 1364 */
NYX 0:85b3fd62ea1a 1365
NYX 0:85b3fd62ea1a 1366 /**
NYX 0:85b3fd62ea1a 1367 * @}
NYX 0:85b3fd62ea1a 1368 */
NYX 0:85b3fd62ea1a 1369
NYX 0:85b3fd62ea1a 1370
NYX 0:85b3fd62ea1a 1371 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1372
NYX 0:85b3fd62ea1a 1373 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
NYX 0:85b3fd62ea1a 1374 * @{
NYX 0:85b3fd62ea1a 1375 */
NYX 0:85b3fd62ea1a 1376
NYX 0:85b3fd62ea1a 1377 /** @defgroup I2S_LL_EF_Configuration Configuration
NYX 0:85b3fd62ea1a 1378 * @{
NYX 0:85b3fd62ea1a 1379 */
NYX 0:85b3fd62ea1a 1380
NYX 0:85b3fd62ea1a 1381 /**
NYX 0:85b3fd62ea1a 1382 * @brief Select I2S mode and Enable I2S peripheral
NYX 0:85b3fd62ea1a 1383 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
NYX 0:85b3fd62ea1a 1384 * I2SCFGR I2SE LL_I2S_Enable
NYX 0:85b3fd62ea1a 1385 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1386 * @retval None
NYX 0:85b3fd62ea1a 1387 */
NYX 0:85b3fd62ea1a 1388 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1389 {
NYX 0:85b3fd62ea1a 1390 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
NYX 0:85b3fd62ea1a 1391 }
NYX 0:85b3fd62ea1a 1392
NYX 0:85b3fd62ea1a 1393 /**
NYX 0:85b3fd62ea1a 1394 * @brief Disable I2S peripheral
NYX 0:85b3fd62ea1a 1395 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
NYX 0:85b3fd62ea1a 1396 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1397 * @retval None
NYX 0:85b3fd62ea1a 1398 */
NYX 0:85b3fd62ea1a 1399 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1400 {
NYX 0:85b3fd62ea1a 1401 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
NYX 0:85b3fd62ea1a 1402 }
NYX 0:85b3fd62ea1a 1403
NYX 0:85b3fd62ea1a 1404 /**
NYX 0:85b3fd62ea1a 1405 * @brief Check if I2S peripheral is enabled
NYX 0:85b3fd62ea1a 1406 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
NYX 0:85b3fd62ea1a 1407 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1408 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1409 */
NYX 0:85b3fd62ea1a 1410 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1411 {
NYX 0:85b3fd62ea1a 1412 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
NYX 0:85b3fd62ea1a 1413 }
NYX 0:85b3fd62ea1a 1414
NYX 0:85b3fd62ea1a 1415 /**
NYX 0:85b3fd62ea1a 1416 * @brief Set I2S data frame length
NYX 0:85b3fd62ea1a 1417 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
NYX 0:85b3fd62ea1a 1418 * I2SCFGR CHLEN LL_I2S_SetDataFormat
NYX 0:85b3fd62ea1a 1419 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1420 * @param DataFormat This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1421 * @arg @ref LL_I2S_DATAFORMAT_16B
NYX 0:85b3fd62ea1a 1422 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
NYX 0:85b3fd62ea1a 1423 * @arg @ref LL_I2S_DATAFORMAT_24B
NYX 0:85b3fd62ea1a 1424 * @arg @ref LL_I2S_DATAFORMAT_32B
NYX 0:85b3fd62ea1a 1425 * @retval None
NYX 0:85b3fd62ea1a 1426 */
NYX 0:85b3fd62ea1a 1427 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
NYX 0:85b3fd62ea1a 1428 {
NYX 0:85b3fd62ea1a 1429 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
NYX 0:85b3fd62ea1a 1430 }
NYX 0:85b3fd62ea1a 1431
NYX 0:85b3fd62ea1a 1432 /**
NYX 0:85b3fd62ea1a 1433 * @brief Get I2S data frame length
NYX 0:85b3fd62ea1a 1434 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
NYX 0:85b3fd62ea1a 1435 * I2SCFGR CHLEN LL_I2S_GetDataFormat
NYX 0:85b3fd62ea1a 1436 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1437 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 1438 * @arg @ref LL_I2S_DATAFORMAT_16B
NYX 0:85b3fd62ea1a 1439 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
NYX 0:85b3fd62ea1a 1440 * @arg @ref LL_I2S_DATAFORMAT_24B
NYX 0:85b3fd62ea1a 1441 * @arg @ref LL_I2S_DATAFORMAT_32B
NYX 0:85b3fd62ea1a 1442 */
NYX 0:85b3fd62ea1a 1443 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1444 {
NYX 0:85b3fd62ea1a 1445 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
NYX 0:85b3fd62ea1a 1446 }
NYX 0:85b3fd62ea1a 1447
NYX 0:85b3fd62ea1a 1448 /**
NYX 0:85b3fd62ea1a 1449 * @brief Set I2S clock polarity
NYX 0:85b3fd62ea1a 1450 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
NYX 0:85b3fd62ea1a 1451 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1452 * @param ClockPolarity This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1453 * @arg @ref LL_I2S_POLARITY_LOW
NYX 0:85b3fd62ea1a 1454 * @arg @ref LL_I2S_POLARITY_HIGH
NYX 0:85b3fd62ea1a 1455 * @retval None
NYX 0:85b3fd62ea1a 1456 */
NYX 0:85b3fd62ea1a 1457 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
NYX 0:85b3fd62ea1a 1458 {
NYX 0:85b3fd62ea1a 1459 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
NYX 0:85b3fd62ea1a 1460 }
NYX 0:85b3fd62ea1a 1461
NYX 0:85b3fd62ea1a 1462 /**
NYX 0:85b3fd62ea1a 1463 * @brief Get I2S clock polarity
NYX 0:85b3fd62ea1a 1464 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
NYX 0:85b3fd62ea1a 1465 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1466 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 1467 * @arg @ref LL_I2S_POLARITY_LOW
NYX 0:85b3fd62ea1a 1468 * @arg @ref LL_I2S_POLARITY_HIGH
NYX 0:85b3fd62ea1a 1469 */
NYX 0:85b3fd62ea1a 1470 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1471 {
NYX 0:85b3fd62ea1a 1472 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
NYX 0:85b3fd62ea1a 1473 }
NYX 0:85b3fd62ea1a 1474
NYX 0:85b3fd62ea1a 1475 /**
NYX 0:85b3fd62ea1a 1476 * @brief Set I2S standard protocol
NYX 0:85b3fd62ea1a 1477 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
NYX 0:85b3fd62ea1a 1478 * I2SCFGR PCMSYNC LL_I2S_SetStandard
NYX 0:85b3fd62ea1a 1479 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1480 * @param Standard This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1481 * @arg @ref LL_I2S_STANDARD_PHILIPS
NYX 0:85b3fd62ea1a 1482 * @arg @ref LL_I2S_STANDARD_MSB
NYX 0:85b3fd62ea1a 1483 * @arg @ref LL_I2S_STANDARD_LSB
NYX 0:85b3fd62ea1a 1484 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
NYX 0:85b3fd62ea1a 1485 * @arg @ref LL_I2S_STANDARD_PCM_LONG
NYX 0:85b3fd62ea1a 1486 * @retval None
NYX 0:85b3fd62ea1a 1487 */
NYX 0:85b3fd62ea1a 1488 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
NYX 0:85b3fd62ea1a 1489 {
NYX 0:85b3fd62ea1a 1490 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
NYX 0:85b3fd62ea1a 1491 }
NYX 0:85b3fd62ea1a 1492
NYX 0:85b3fd62ea1a 1493 /**
NYX 0:85b3fd62ea1a 1494 * @brief Get I2S standard protocol
NYX 0:85b3fd62ea1a 1495 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
NYX 0:85b3fd62ea1a 1496 * I2SCFGR PCMSYNC LL_I2S_GetStandard
NYX 0:85b3fd62ea1a 1497 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1498 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 1499 * @arg @ref LL_I2S_STANDARD_PHILIPS
NYX 0:85b3fd62ea1a 1500 * @arg @ref LL_I2S_STANDARD_MSB
NYX 0:85b3fd62ea1a 1501 * @arg @ref LL_I2S_STANDARD_LSB
NYX 0:85b3fd62ea1a 1502 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
NYX 0:85b3fd62ea1a 1503 * @arg @ref LL_I2S_STANDARD_PCM_LONG
NYX 0:85b3fd62ea1a 1504 */
NYX 0:85b3fd62ea1a 1505 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1506 {
NYX 0:85b3fd62ea1a 1507 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
NYX 0:85b3fd62ea1a 1508 }
NYX 0:85b3fd62ea1a 1509
NYX 0:85b3fd62ea1a 1510 /**
NYX 0:85b3fd62ea1a 1511 * @brief Set I2S transfer mode
NYX 0:85b3fd62ea1a 1512 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
NYX 0:85b3fd62ea1a 1513 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1514 * @param Mode This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1515 * @arg @ref LL_I2S_MODE_SLAVE_TX
NYX 0:85b3fd62ea1a 1516 * @arg @ref LL_I2S_MODE_SLAVE_RX
NYX 0:85b3fd62ea1a 1517 * @arg @ref LL_I2S_MODE_MASTER_TX
NYX 0:85b3fd62ea1a 1518 * @arg @ref LL_I2S_MODE_MASTER_RX
NYX 0:85b3fd62ea1a 1519 * @retval None
NYX 0:85b3fd62ea1a 1520 */
NYX 0:85b3fd62ea1a 1521 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
NYX 0:85b3fd62ea1a 1522 {
NYX 0:85b3fd62ea1a 1523 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
NYX 0:85b3fd62ea1a 1524 }
NYX 0:85b3fd62ea1a 1525
NYX 0:85b3fd62ea1a 1526 /**
NYX 0:85b3fd62ea1a 1527 * @brief Get I2S transfer mode
NYX 0:85b3fd62ea1a 1528 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
NYX 0:85b3fd62ea1a 1529 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1530 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 1531 * @arg @ref LL_I2S_MODE_SLAVE_TX
NYX 0:85b3fd62ea1a 1532 * @arg @ref LL_I2S_MODE_SLAVE_RX
NYX 0:85b3fd62ea1a 1533 * @arg @ref LL_I2S_MODE_MASTER_TX
NYX 0:85b3fd62ea1a 1534 * @arg @ref LL_I2S_MODE_MASTER_RX
NYX 0:85b3fd62ea1a 1535 */
NYX 0:85b3fd62ea1a 1536 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1537 {
NYX 0:85b3fd62ea1a 1538 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
NYX 0:85b3fd62ea1a 1539 }
NYX 0:85b3fd62ea1a 1540
NYX 0:85b3fd62ea1a 1541 /**
NYX 0:85b3fd62ea1a 1542 * @brief Set I2S linear prescaler
NYX 0:85b3fd62ea1a 1543 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
NYX 0:85b3fd62ea1a 1544 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1545 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
NYX 0:85b3fd62ea1a 1546 * @retval None
NYX 0:85b3fd62ea1a 1547 */
NYX 0:85b3fd62ea1a 1548 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
NYX 0:85b3fd62ea1a 1549 {
NYX 0:85b3fd62ea1a 1550 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
NYX 0:85b3fd62ea1a 1551 }
NYX 0:85b3fd62ea1a 1552
NYX 0:85b3fd62ea1a 1553 /**
NYX 0:85b3fd62ea1a 1554 * @brief Get I2S linear prescaler
NYX 0:85b3fd62ea1a 1555 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
NYX 0:85b3fd62ea1a 1556 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1557 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
NYX 0:85b3fd62ea1a 1558 */
NYX 0:85b3fd62ea1a 1559 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1560 {
NYX 0:85b3fd62ea1a 1561 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
NYX 0:85b3fd62ea1a 1562 }
NYX 0:85b3fd62ea1a 1563
NYX 0:85b3fd62ea1a 1564 /**
NYX 0:85b3fd62ea1a 1565 * @brief Set I2S parity prescaler
NYX 0:85b3fd62ea1a 1566 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
NYX 0:85b3fd62ea1a 1567 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1568 * @param PrescalerParity This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1569 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
NYX 0:85b3fd62ea1a 1570 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
NYX 0:85b3fd62ea1a 1571 * @retval None
NYX 0:85b3fd62ea1a 1572 */
NYX 0:85b3fd62ea1a 1573 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
NYX 0:85b3fd62ea1a 1574 {
NYX 0:85b3fd62ea1a 1575 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
NYX 0:85b3fd62ea1a 1576 }
NYX 0:85b3fd62ea1a 1577
NYX 0:85b3fd62ea1a 1578 /**
NYX 0:85b3fd62ea1a 1579 * @brief Get I2S parity prescaler
NYX 0:85b3fd62ea1a 1580 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
NYX 0:85b3fd62ea1a 1581 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1582 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 1583 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
NYX 0:85b3fd62ea1a 1584 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
NYX 0:85b3fd62ea1a 1585 */
NYX 0:85b3fd62ea1a 1586 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1587 {
NYX 0:85b3fd62ea1a 1588 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
NYX 0:85b3fd62ea1a 1589 }
NYX 0:85b3fd62ea1a 1590
NYX 0:85b3fd62ea1a 1591 /**
NYX 0:85b3fd62ea1a 1592 * @brief Enable the master clock ouput (Pin MCK)
NYX 0:85b3fd62ea1a 1593 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
NYX 0:85b3fd62ea1a 1594 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1595 * @retval None
NYX 0:85b3fd62ea1a 1596 */
NYX 0:85b3fd62ea1a 1597 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1598 {
NYX 0:85b3fd62ea1a 1599 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
NYX 0:85b3fd62ea1a 1600 }
NYX 0:85b3fd62ea1a 1601
NYX 0:85b3fd62ea1a 1602 /**
NYX 0:85b3fd62ea1a 1603 * @brief Disable the master clock ouput (Pin MCK)
NYX 0:85b3fd62ea1a 1604 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
NYX 0:85b3fd62ea1a 1605 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1606 * @retval None
NYX 0:85b3fd62ea1a 1607 */
NYX 0:85b3fd62ea1a 1608 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1609 {
NYX 0:85b3fd62ea1a 1610 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
NYX 0:85b3fd62ea1a 1611 }
NYX 0:85b3fd62ea1a 1612
NYX 0:85b3fd62ea1a 1613 /**
NYX 0:85b3fd62ea1a 1614 * @brief Check if the master clock ouput (Pin MCK) is enabled
NYX 0:85b3fd62ea1a 1615 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
NYX 0:85b3fd62ea1a 1616 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1617 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1618 */
NYX 0:85b3fd62ea1a 1619 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1620 {
NYX 0:85b3fd62ea1a 1621 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
NYX 0:85b3fd62ea1a 1622 }
NYX 0:85b3fd62ea1a 1623
NYX 0:85b3fd62ea1a 1624 #if defined(SPI_I2SCFGR_ASTRTEN)
NYX 0:85b3fd62ea1a 1625 /**
NYX 0:85b3fd62ea1a 1626 * @brief Enable asynchronous start
NYX 0:85b3fd62ea1a 1627 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
NYX 0:85b3fd62ea1a 1628 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1629 * @retval None
NYX 0:85b3fd62ea1a 1630 */
NYX 0:85b3fd62ea1a 1631 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1632 {
NYX 0:85b3fd62ea1a 1633 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
NYX 0:85b3fd62ea1a 1634 }
NYX 0:85b3fd62ea1a 1635
NYX 0:85b3fd62ea1a 1636 /**
NYX 0:85b3fd62ea1a 1637 * @brief Disable asynchronous start
NYX 0:85b3fd62ea1a 1638 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
NYX 0:85b3fd62ea1a 1639 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1640 * @retval None
NYX 0:85b3fd62ea1a 1641 */
NYX 0:85b3fd62ea1a 1642 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1643 {
NYX 0:85b3fd62ea1a 1644 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
NYX 0:85b3fd62ea1a 1645 }
NYX 0:85b3fd62ea1a 1646
NYX 0:85b3fd62ea1a 1647 /**
NYX 0:85b3fd62ea1a 1648 * @brief Check if asynchronous start is enabled
NYX 0:85b3fd62ea1a 1649 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
NYX 0:85b3fd62ea1a 1650 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1651 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1652 */
NYX 0:85b3fd62ea1a 1653 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1654 {
NYX 0:85b3fd62ea1a 1655 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
NYX 0:85b3fd62ea1a 1656 }
NYX 0:85b3fd62ea1a 1657 #endif /* SPI_I2SCFGR_ASTRTEN */
NYX 0:85b3fd62ea1a 1658
NYX 0:85b3fd62ea1a 1659 /**
NYX 0:85b3fd62ea1a 1660 * @}
NYX 0:85b3fd62ea1a 1661 */
NYX 0:85b3fd62ea1a 1662
NYX 0:85b3fd62ea1a 1663 /** @defgroup I2S_LL_EF_FLAG FLAG Management
NYX 0:85b3fd62ea1a 1664 * @{
NYX 0:85b3fd62ea1a 1665 */
NYX 0:85b3fd62ea1a 1666
NYX 0:85b3fd62ea1a 1667 /**
NYX 0:85b3fd62ea1a 1668 * @brief Check if Rx buffer is not empty
NYX 0:85b3fd62ea1a 1669 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
NYX 0:85b3fd62ea1a 1670 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1671 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1672 */
NYX 0:85b3fd62ea1a 1673 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1674 {
NYX 0:85b3fd62ea1a 1675 return LL_SPI_IsActiveFlag_RXNE(SPIx);
NYX 0:85b3fd62ea1a 1676 }
NYX 0:85b3fd62ea1a 1677
NYX 0:85b3fd62ea1a 1678 /**
NYX 0:85b3fd62ea1a 1679 * @brief Check if Tx buffer is empty
NYX 0:85b3fd62ea1a 1680 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
NYX 0:85b3fd62ea1a 1681 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1682 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1683 */
NYX 0:85b3fd62ea1a 1684 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1685 {
NYX 0:85b3fd62ea1a 1686 return LL_SPI_IsActiveFlag_TXE(SPIx);
NYX 0:85b3fd62ea1a 1687 }
NYX 0:85b3fd62ea1a 1688
NYX 0:85b3fd62ea1a 1689 /**
NYX 0:85b3fd62ea1a 1690 * @brief Get busy flag
NYX 0:85b3fd62ea1a 1691 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
NYX 0:85b3fd62ea1a 1692 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1693 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1694 */
NYX 0:85b3fd62ea1a 1695 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1696 {
NYX 0:85b3fd62ea1a 1697 return LL_SPI_IsActiveFlag_BSY(SPIx);
NYX 0:85b3fd62ea1a 1698 }
NYX 0:85b3fd62ea1a 1699
NYX 0:85b3fd62ea1a 1700 /**
NYX 0:85b3fd62ea1a 1701 * @brief Get overrun error flag
NYX 0:85b3fd62ea1a 1702 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
NYX 0:85b3fd62ea1a 1703 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1704 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1705 */
NYX 0:85b3fd62ea1a 1706 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1707 {
NYX 0:85b3fd62ea1a 1708 return LL_SPI_IsActiveFlag_OVR(SPIx);
NYX 0:85b3fd62ea1a 1709 }
NYX 0:85b3fd62ea1a 1710
NYX 0:85b3fd62ea1a 1711 /**
NYX 0:85b3fd62ea1a 1712 * @brief Get underrun error flag
NYX 0:85b3fd62ea1a 1713 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
NYX 0:85b3fd62ea1a 1714 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1715 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1716 */
NYX 0:85b3fd62ea1a 1717 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1718 {
NYX 0:85b3fd62ea1a 1719 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
NYX 0:85b3fd62ea1a 1720 }
NYX 0:85b3fd62ea1a 1721
NYX 0:85b3fd62ea1a 1722 /**
NYX 0:85b3fd62ea1a 1723 * @brief Get frame format error flag
NYX 0:85b3fd62ea1a 1724 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
NYX 0:85b3fd62ea1a 1725 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1726 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1727 */
NYX 0:85b3fd62ea1a 1728 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1729 {
NYX 0:85b3fd62ea1a 1730 return LL_SPI_IsActiveFlag_FRE(SPIx);
NYX 0:85b3fd62ea1a 1731 }
NYX 0:85b3fd62ea1a 1732
NYX 0:85b3fd62ea1a 1733 /**
NYX 0:85b3fd62ea1a 1734 * @brief Get channel side flag.
NYX 0:85b3fd62ea1a 1735 * @note 0: Channel Left has to be transmitted or has been received\n
NYX 0:85b3fd62ea1a 1736 * 1: Channel Right has to be transmitted or has been received\n
NYX 0:85b3fd62ea1a 1737 * It has no significance in PCM mode.
NYX 0:85b3fd62ea1a 1738 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
NYX 0:85b3fd62ea1a 1739 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1740 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1741 */
NYX 0:85b3fd62ea1a 1742 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1743 {
NYX 0:85b3fd62ea1a 1744 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
NYX 0:85b3fd62ea1a 1745 }
NYX 0:85b3fd62ea1a 1746
NYX 0:85b3fd62ea1a 1747 /**
NYX 0:85b3fd62ea1a 1748 * @brief Clear overrun error flag
NYX 0:85b3fd62ea1a 1749 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
NYX 0:85b3fd62ea1a 1750 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1751 * @retval None
NYX 0:85b3fd62ea1a 1752 */
NYX 0:85b3fd62ea1a 1753 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1754 {
NYX 0:85b3fd62ea1a 1755 LL_SPI_ClearFlag_OVR(SPIx);
NYX 0:85b3fd62ea1a 1756 }
NYX 0:85b3fd62ea1a 1757
NYX 0:85b3fd62ea1a 1758 /**
NYX 0:85b3fd62ea1a 1759 * @brief Clear underrun error flag
NYX 0:85b3fd62ea1a 1760 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
NYX 0:85b3fd62ea1a 1761 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1762 * @retval None
NYX 0:85b3fd62ea1a 1763 */
NYX 0:85b3fd62ea1a 1764 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1765 {
NYX 0:85b3fd62ea1a 1766 __IO uint32_t tmpreg;
NYX 0:85b3fd62ea1a 1767 tmpreg = SPIx->SR;
NYX 0:85b3fd62ea1a 1768 (void)tmpreg;
NYX 0:85b3fd62ea1a 1769 }
NYX 0:85b3fd62ea1a 1770
NYX 0:85b3fd62ea1a 1771 /**
NYX 0:85b3fd62ea1a 1772 * @brief Clear frame format error flag
NYX 0:85b3fd62ea1a 1773 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
NYX 0:85b3fd62ea1a 1774 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1775 * @retval None
NYX 0:85b3fd62ea1a 1776 */
NYX 0:85b3fd62ea1a 1777 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1778 {
NYX 0:85b3fd62ea1a 1779 LL_SPI_ClearFlag_FRE(SPIx);
NYX 0:85b3fd62ea1a 1780 }
NYX 0:85b3fd62ea1a 1781
NYX 0:85b3fd62ea1a 1782 /**
NYX 0:85b3fd62ea1a 1783 * @}
NYX 0:85b3fd62ea1a 1784 */
NYX 0:85b3fd62ea1a 1785
NYX 0:85b3fd62ea1a 1786 /** @defgroup I2S_LL_EF_IT Interrupt Management
NYX 0:85b3fd62ea1a 1787 * @{
NYX 0:85b3fd62ea1a 1788 */
NYX 0:85b3fd62ea1a 1789
NYX 0:85b3fd62ea1a 1790 /**
NYX 0:85b3fd62ea1a 1791 * @brief Enable error IT
NYX 0:85b3fd62ea1a 1792 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
NYX 0:85b3fd62ea1a 1793 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
NYX 0:85b3fd62ea1a 1794 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1795 * @retval None
NYX 0:85b3fd62ea1a 1796 */
NYX 0:85b3fd62ea1a 1797 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1798 {
NYX 0:85b3fd62ea1a 1799 LL_SPI_EnableIT_ERR(SPIx);
NYX 0:85b3fd62ea1a 1800 }
NYX 0:85b3fd62ea1a 1801
NYX 0:85b3fd62ea1a 1802 /**
NYX 0:85b3fd62ea1a 1803 * @brief Enable Rx buffer not empty IT
NYX 0:85b3fd62ea1a 1804 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
NYX 0:85b3fd62ea1a 1805 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1806 * @retval None
NYX 0:85b3fd62ea1a 1807 */
NYX 0:85b3fd62ea1a 1808 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1809 {
NYX 0:85b3fd62ea1a 1810 LL_SPI_EnableIT_RXNE(SPIx);
NYX 0:85b3fd62ea1a 1811 }
NYX 0:85b3fd62ea1a 1812
NYX 0:85b3fd62ea1a 1813 /**
NYX 0:85b3fd62ea1a 1814 * @brief Enable Tx buffer empty IT
NYX 0:85b3fd62ea1a 1815 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
NYX 0:85b3fd62ea1a 1816 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1817 * @retval None
NYX 0:85b3fd62ea1a 1818 */
NYX 0:85b3fd62ea1a 1819 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1820 {
NYX 0:85b3fd62ea1a 1821 LL_SPI_EnableIT_TXE(SPIx);
NYX 0:85b3fd62ea1a 1822 }
NYX 0:85b3fd62ea1a 1823
NYX 0:85b3fd62ea1a 1824 /**
NYX 0:85b3fd62ea1a 1825 * @brief Disable error IT
NYX 0:85b3fd62ea1a 1826 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
NYX 0:85b3fd62ea1a 1827 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
NYX 0:85b3fd62ea1a 1828 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1829 * @retval None
NYX 0:85b3fd62ea1a 1830 */
NYX 0:85b3fd62ea1a 1831 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1832 {
NYX 0:85b3fd62ea1a 1833 LL_SPI_DisableIT_ERR(SPIx);
NYX 0:85b3fd62ea1a 1834 }
NYX 0:85b3fd62ea1a 1835
NYX 0:85b3fd62ea1a 1836 /**
NYX 0:85b3fd62ea1a 1837 * @brief Disable Rx buffer not empty IT
NYX 0:85b3fd62ea1a 1838 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
NYX 0:85b3fd62ea1a 1839 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1840 * @retval None
NYX 0:85b3fd62ea1a 1841 */
NYX 0:85b3fd62ea1a 1842 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1843 {
NYX 0:85b3fd62ea1a 1844 LL_SPI_DisableIT_RXNE(SPIx);
NYX 0:85b3fd62ea1a 1845 }
NYX 0:85b3fd62ea1a 1846
NYX 0:85b3fd62ea1a 1847 /**
NYX 0:85b3fd62ea1a 1848 * @brief Disable Tx buffer empty IT
NYX 0:85b3fd62ea1a 1849 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
NYX 0:85b3fd62ea1a 1850 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1851 * @retval None
NYX 0:85b3fd62ea1a 1852 */
NYX 0:85b3fd62ea1a 1853 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1854 {
NYX 0:85b3fd62ea1a 1855 LL_SPI_DisableIT_TXE(SPIx);
NYX 0:85b3fd62ea1a 1856 }
NYX 0:85b3fd62ea1a 1857
NYX 0:85b3fd62ea1a 1858 /**
NYX 0:85b3fd62ea1a 1859 * @brief Check if ERR IT is enabled
NYX 0:85b3fd62ea1a 1860 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
NYX 0:85b3fd62ea1a 1861 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1862 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1863 */
NYX 0:85b3fd62ea1a 1864 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1865 {
NYX 0:85b3fd62ea1a 1866 return LL_SPI_IsEnabledIT_ERR(SPIx);
NYX 0:85b3fd62ea1a 1867 }
NYX 0:85b3fd62ea1a 1868
NYX 0:85b3fd62ea1a 1869 /**
NYX 0:85b3fd62ea1a 1870 * @brief Check if RXNE IT is enabled
NYX 0:85b3fd62ea1a 1871 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
NYX 0:85b3fd62ea1a 1872 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1873 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1874 */
NYX 0:85b3fd62ea1a 1875 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1876 {
NYX 0:85b3fd62ea1a 1877 return LL_SPI_IsEnabledIT_RXNE(SPIx);
NYX 0:85b3fd62ea1a 1878 }
NYX 0:85b3fd62ea1a 1879
NYX 0:85b3fd62ea1a 1880 /**
NYX 0:85b3fd62ea1a 1881 * @brief Check if TXE IT is enabled
NYX 0:85b3fd62ea1a 1882 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
NYX 0:85b3fd62ea1a 1883 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1884 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1885 */
NYX 0:85b3fd62ea1a 1886 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1887 {
NYX 0:85b3fd62ea1a 1888 return LL_SPI_IsEnabledIT_TXE(SPIx);
NYX 0:85b3fd62ea1a 1889 }
NYX 0:85b3fd62ea1a 1890
NYX 0:85b3fd62ea1a 1891 /**
NYX 0:85b3fd62ea1a 1892 * @}
NYX 0:85b3fd62ea1a 1893 */
NYX 0:85b3fd62ea1a 1894
NYX 0:85b3fd62ea1a 1895 /** @defgroup I2S_LL_EF_DMA DMA Management
NYX 0:85b3fd62ea1a 1896 * @{
NYX 0:85b3fd62ea1a 1897 */
NYX 0:85b3fd62ea1a 1898
NYX 0:85b3fd62ea1a 1899 /**
NYX 0:85b3fd62ea1a 1900 * @brief Enable DMA Rx
NYX 0:85b3fd62ea1a 1901 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
NYX 0:85b3fd62ea1a 1902 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1903 * @retval None
NYX 0:85b3fd62ea1a 1904 */
NYX 0:85b3fd62ea1a 1905 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1906 {
NYX 0:85b3fd62ea1a 1907 LL_SPI_EnableDMAReq_RX(SPIx);
NYX 0:85b3fd62ea1a 1908 }
NYX 0:85b3fd62ea1a 1909
NYX 0:85b3fd62ea1a 1910 /**
NYX 0:85b3fd62ea1a 1911 * @brief Disable DMA Rx
NYX 0:85b3fd62ea1a 1912 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
NYX 0:85b3fd62ea1a 1913 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1914 * @retval None
NYX 0:85b3fd62ea1a 1915 */
NYX 0:85b3fd62ea1a 1916 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1917 {
NYX 0:85b3fd62ea1a 1918 LL_SPI_DisableDMAReq_RX(SPIx);
NYX 0:85b3fd62ea1a 1919 }
NYX 0:85b3fd62ea1a 1920
NYX 0:85b3fd62ea1a 1921 /**
NYX 0:85b3fd62ea1a 1922 * @brief Check if DMA Rx is enabled
NYX 0:85b3fd62ea1a 1923 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
NYX 0:85b3fd62ea1a 1924 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1925 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1926 */
NYX 0:85b3fd62ea1a 1927 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1928 {
NYX 0:85b3fd62ea1a 1929 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
NYX 0:85b3fd62ea1a 1930 }
NYX 0:85b3fd62ea1a 1931
NYX 0:85b3fd62ea1a 1932 /**
NYX 0:85b3fd62ea1a 1933 * @brief Enable DMA Tx
NYX 0:85b3fd62ea1a 1934 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
NYX 0:85b3fd62ea1a 1935 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1936 * @retval None
NYX 0:85b3fd62ea1a 1937 */
NYX 0:85b3fd62ea1a 1938 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1939 {
NYX 0:85b3fd62ea1a 1940 LL_SPI_EnableDMAReq_TX(SPIx);
NYX 0:85b3fd62ea1a 1941 }
NYX 0:85b3fd62ea1a 1942
NYX 0:85b3fd62ea1a 1943 /**
NYX 0:85b3fd62ea1a 1944 * @brief Disable DMA Tx
NYX 0:85b3fd62ea1a 1945 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
NYX 0:85b3fd62ea1a 1946 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1947 * @retval None
NYX 0:85b3fd62ea1a 1948 */
NYX 0:85b3fd62ea1a 1949 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1950 {
NYX 0:85b3fd62ea1a 1951 LL_SPI_DisableDMAReq_TX(SPIx);
NYX 0:85b3fd62ea1a 1952 }
NYX 0:85b3fd62ea1a 1953
NYX 0:85b3fd62ea1a 1954 /**
NYX 0:85b3fd62ea1a 1955 * @brief Check if DMA Tx is enabled
NYX 0:85b3fd62ea1a 1956 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
NYX 0:85b3fd62ea1a 1957 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1958 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1959 */
NYX 0:85b3fd62ea1a 1960 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1961 {
NYX 0:85b3fd62ea1a 1962 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
NYX 0:85b3fd62ea1a 1963 }
NYX 0:85b3fd62ea1a 1964
NYX 0:85b3fd62ea1a 1965 /**
NYX 0:85b3fd62ea1a 1966 * @}
NYX 0:85b3fd62ea1a 1967 */
NYX 0:85b3fd62ea1a 1968
NYX 0:85b3fd62ea1a 1969 /** @defgroup I2S_LL_EF_DATA DATA Management
NYX 0:85b3fd62ea1a 1970 * @{
NYX 0:85b3fd62ea1a 1971 */
NYX 0:85b3fd62ea1a 1972
NYX 0:85b3fd62ea1a 1973 /**
NYX 0:85b3fd62ea1a 1974 * @brief Read 16-Bits in data register
NYX 0:85b3fd62ea1a 1975 * @rmtoll DR DR LL_I2S_ReceiveData16
NYX 0:85b3fd62ea1a 1976 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1977 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
NYX 0:85b3fd62ea1a 1978 */
NYX 0:85b3fd62ea1a 1979 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
NYX 0:85b3fd62ea1a 1980 {
NYX 0:85b3fd62ea1a 1981 return LL_SPI_ReceiveData16(SPIx);
NYX 0:85b3fd62ea1a 1982 }
NYX 0:85b3fd62ea1a 1983
NYX 0:85b3fd62ea1a 1984 /**
NYX 0:85b3fd62ea1a 1985 * @brief Write 16-Bits in data register
NYX 0:85b3fd62ea1a 1986 * @rmtoll DR DR LL_I2S_TransmitData16
NYX 0:85b3fd62ea1a 1987 * @param SPIx SPI Instance
NYX 0:85b3fd62ea1a 1988 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
NYX 0:85b3fd62ea1a 1989 * @retval None
NYX 0:85b3fd62ea1a 1990 */
NYX 0:85b3fd62ea1a 1991 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
NYX 0:85b3fd62ea1a 1992 {
NYX 0:85b3fd62ea1a 1993 LL_SPI_TransmitData16(SPIx, TxData);
NYX 0:85b3fd62ea1a 1994 }
NYX 0:85b3fd62ea1a 1995
NYX 0:85b3fd62ea1a 1996 /**
NYX 0:85b3fd62ea1a 1997 * @}
NYX 0:85b3fd62ea1a 1998 */
NYX 0:85b3fd62ea1a 1999
NYX 0:85b3fd62ea1a 2000 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 2001 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 2002 * @{
NYX 0:85b3fd62ea1a 2003 */
NYX 0:85b3fd62ea1a 2004
NYX 0:85b3fd62ea1a 2005 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
NYX 0:85b3fd62ea1a 2006 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
NYX 0:85b3fd62ea1a 2007 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
NYX 0:85b3fd62ea1a 2008 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
NYX 0:85b3fd62ea1a 2009 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
NYX 0:85b3fd62ea1a 2010 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
NYX 0:85b3fd62ea1a 2011 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
NYX 0:85b3fd62ea1a 2012
NYX 0:85b3fd62ea1a 2013 /**
NYX 0:85b3fd62ea1a 2014 * @}
NYX 0:85b3fd62ea1a 2015 */
NYX 0:85b3fd62ea1a 2016 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 2017
NYX 0:85b3fd62ea1a 2018 /**
NYX 0:85b3fd62ea1a 2019 * @}
NYX 0:85b3fd62ea1a 2020 */
NYX 0:85b3fd62ea1a 2021
NYX 0:85b3fd62ea1a 2022 /**
NYX 0:85b3fd62ea1a 2023 * @}
NYX 0:85b3fd62ea1a 2024 */
NYX 0:85b3fd62ea1a 2025
NYX 0:85b3fd62ea1a 2026 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
NYX 0:85b3fd62ea1a 2027
NYX 0:85b3fd62ea1a 2028 /**
NYX 0:85b3fd62ea1a 2029 * @}
NYX 0:85b3fd62ea1a 2030 */
NYX 0:85b3fd62ea1a 2031
NYX 0:85b3fd62ea1a 2032 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 2033 }
NYX 0:85b3fd62ea1a 2034 #endif
NYX 0:85b3fd62ea1a 2035
NYX 0:85b3fd62ea1a 2036 #endif /* __STM32F4xx_LL_SPI_H */
NYX 0:85b3fd62ea1a 2037
NYX 0:85b3fd62ea1a 2038 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/