mbed-dev - inport from local

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inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_ll_rcc.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of RCC LL module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_LL_RCC_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_LL_RCC_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	47	#include "stm32f4xx.h"
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_LL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	#if defined(RCC)
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/** @defgroup RCC_LL RCC
NYX	0:85b3fd62ea1a	56	* @{
NYX	0:85b3fd62ea1a	57	*/
NYX	0:85b3fd62ea1a	58
NYX	0:85b3fd62ea1a	59	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	60	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
NYX	0:85b3fd62ea1a	62	* @{
NYX	0:85b3fd62ea1a	63	*/
NYX	0:85b3fd62ea1a	64
NYX	0:85b3fd62ea1a	65	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
NYX	0:85b3fd62ea1a	66	static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
NYX	0:85b3fd62ea1a	67	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
NYX	0:85b3fd62ea1a	68
NYX	0:85b3fd62ea1a	69	/**
NYX	0:85b3fd62ea1a	70	* @}
NYX	0:85b3fd62ea1a	71	*/
NYX	0:85b3fd62ea1a	72	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	73	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	74	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	75	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
NYX	0:85b3fd62ea1a	76	* @{
NYX	0:85b3fd62ea1a	77	*/
NYX	0:85b3fd62ea1a	78	/**
NYX	0:85b3fd62ea1a	79	* @}
NYX	0:85b3fd62ea1a	80	*/
NYX	0:85b3fd62ea1a	81	#endif /USE_FULL_LL_DRIVER/
NYX	0:85b3fd62ea1a	82	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	83	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	84	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
NYX	0:85b3fd62ea1a	85	* @{
NYX	0:85b3fd62ea1a	86	*/
NYX	0:85b3fd62ea1a	87
NYX	0:85b3fd62ea1a	88	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
NYX	0:85b3fd62ea1a	89	* @{
NYX	0:85b3fd62ea1a	90	*/
NYX	0:85b3fd62ea1a	91
NYX	0:85b3fd62ea1a	92	/**
NYX	0:85b3fd62ea1a	93	* @brief RCC Clocks Frequency Structure
NYX	0:85b3fd62ea1a	94	*/
NYX	0:85b3fd62ea1a	95	typedef struct
NYX	0:85b3fd62ea1a	96	{
NYX	0:85b3fd62ea1a	97	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
NYX	0:85b3fd62ea1a	98	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
NYX	0:85b3fd62ea1a	99	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
NYX	0:85b3fd62ea1a	100	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
NYX	0:85b3fd62ea1a	101	} LL_RCC_ClocksTypeDef;
NYX	0:85b3fd62ea1a	102
NYX	0:85b3fd62ea1a	103	/**
NYX	0:85b3fd62ea1a	104	* @}
NYX	0:85b3fd62ea1a	105	*/
NYX	0:85b3fd62ea1a	106
NYX	0:85b3fd62ea1a	107	/**
NYX	0:85b3fd62ea1a	108	* @}
NYX	0:85b3fd62ea1a	109	*/
NYX	0:85b3fd62ea1a	110	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	111
NYX	0:85b3fd62ea1a	112	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	113	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
NYX	0:85b3fd62ea1a	114	* @{
NYX	0:85b3fd62ea1a	115	*/
NYX	0:85b3fd62ea1a	116
NYX	0:85b3fd62ea1a	117	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
NYX	0:85b3fd62ea1a	118	* @brief Defines used to adapt values of different oscillators
NYX	0:85b3fd62ea1a	119	* @note These values could be modified in the user environment according to
NYX	0:85b3fd62ea1a	120	* HW set-up.
NYX	0:85b3fd62ea1a	121	* @{
NYX	0:85b3fd62ea1a	122	*/
NYX	0:85b3fd62ea1a	123	#if !defined (HSE_VALUE)
NYX	0:85b3fd62ea1a	124	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
NYX	0:85b3fd62ea1a	125	#endif /* HSE_VALUE */
NYX	0:85b3fd62ea1a	126
NYX	0:85b3fd62ea1a	127	#if !defined (HSI_VALUE)
NYX	0:85b3fd62ea1a	128	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
NYX	0:85b3fd62ea1a	129	#endif /* HSI_VALUE */
NYX	0:85b3fd62ea1a	130
NYX	0:85b3fd62ea1a	131	#if !defined (LSE_VALUE)
NYX	0:85b3fd62ea1a	132	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
NYX	0:85b3fd62ea1a	133	#endif /* LSE_VALUE */
NYX	0:85b3fd62ea1a	134
NYX	0:85b3fd62ea1a	135	#if !defined (LSI_VALUE)
NYX	0:85b3fd62ea1a	136	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
NYX	0:85b3fd62ea1a	137	#endif /* LSI_VALUE */
NYX	0:85b3fd62ea1a	138
NYX	0:85b3fd62ea1a	139	#if !defined (EXTERNAL_CLOCK_VALUE)
NYX	0:85b3fd62ea1a	140	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
NYX	0:85b3fd62ea1a	141	#endif /* EXTERNAL_CLOCK_VALUE */
NYX	0:85b3fd62ea1a	142	/**
NYX	0:85b3fd62ea1a	143	* @}
NYX	0:85b3fd62ea1a	144	*/
NYX	0:85b3fd62ea1a	145
NYX	0:85b3fd62ea1a	146	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
NYX	0:85b3fd62ea1a	147	* @brief Flags defines which can be used with LL_RCC_WriteReg function
NYX	0:85b3fd62ea1a	148	* @{
NYX	0:85b3fd62ea1a	149	*/
NYX	0:85b3fd62ea1a	150	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
NYX	0:85b3fd62ea1a	151	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
NYX	0:85b3fd62ea1a	152	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
NYX	0:85b3fd62ea1a	153	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
NYX	0:85b3fd62ea1a	154	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
NYX	0:85b3fd62ea1a	155	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	156	#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /!< PLLI2S Ready Interrupt Clear /
NYX	0:85b3fd62ea1a	157	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	158	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	159	#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /!< PLLSAI Ready Interrupt Clear /
NYX	0:85b3fd62ea1a	160	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	161	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
NYX	0:85b3fd62ea1a	162	/**
NYX	0:85b3fd62ea1a	163	* @}
NYX	0:85b3fd62ea1a	164	*/
NYX	0:85b3fd62ea1a	165
NYX	0:85b3fd62ea1a	166	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
NYX	0:85b3fd62ea1a	167	* @brief Flags defines which can be used with LL_RCC_ReadReg function
NYX	0:85b3fd62ea1a	168	* @{
NYX	0:85b3fd62ea1a	169	*/
NYX	0:85b3fd62ea1a	170	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
NYX	0:85b3fd62ea1a	171	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
NYX	0:85b3fd62ea1a	172	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
NYX	0:85b3fd62ea1a	173	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
NYX	0:85b3fd62ea1a	174	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
NYX	0:85b3fd62ea1a	175	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	176	#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /!< PLLI2S Ready Interrupt flag /
NYX	0:85b3fd62ea1a	177	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	178	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	179	#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /!< PLLSAI Ready Interrupt flag /
NYX	0:85b3fd62ea1a	180	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	181	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
NYX	0:85b3fd62ea1a	182	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
NYX	0:85b3fd62ea1a	183	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
NYX	0:85b3fd62ea1a	184	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
NYX	0:85b3fd62ea1a	185	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
NYX	0:85b3fd62ea1a	186	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
NYX	0:85b3fd62ea1a	187	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
NYX	0:85b3fd62ea1a	188	#if defined(RCC_CSR_BORRSTF)
NYX	0:85b3fd62ea1a	189	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
NYX	0:85b3fd62ea1a	190	#endif /* RCC_CSR_BORRSTF */
NYX	0:85b3fd62ea1a	191	/**
NYX	0:85b3fd62ea1a	192	* @}
NYX	0:85b3fd62ea1a	193	*/
NYX	0:85b3fd62ea1a	194
NYX	0:85b3fd62ea1a	195	/** @defgroup RCC_LL_EC_IT IT Defines
NYX	0:85b3fd62ea1a	196	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
NYX	0:85b3fd62ea1a	197	* @{
NYX	0:85b3fd62ea1a	198	*/
NYX	0:85b3fd62ea1a	199	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
NYX	0:85b3fd62ea1a	200	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
NYX	0:85b3fd62ea1a	201	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
NYX	0:85b3fd62ea1a	202	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
NYX	0:85b3fd62ea1a	203	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
NYX	0:85b3fd62ea1a	204	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	205	#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /!< PLLI2S Ready Interrupt Enable /
NYX	0:85b3fd62ea1a	206	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	207	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	208	#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /!< PLLSAI Ready Interrupt Enable /
NYX	0:85b3fd62ea1a	209	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	210	/**
NYX	0:85b3fd62ea1a	211	* @}
NYX	0:85b3fd62ea1a	212	*/
NYX	0:85b3fd62ea1a	213
NYX	0:85b3fd62ea1a	214	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
NYX	0:85b3fd62ea1a	215	* @{
NYX	0:85b3fd62ea1a	216	*/
NYX	0:85b3fd62ea1a	217	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
NYX	0:85b3fd62ea1a	218	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
NYX	0:85b3fd62ea1a	219	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
NYX	0:85b3fd62ea1a	220	#if defined(RCC_CFGR_SW_PLLR)
NYX	0:85b3fd62ea1a	221	#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /!< PLLR selection as system clock /
NYX	0:85b3fd62ea1a	222	#endif /* RCC_CFGR_SW_PLLR */
NYX	0:85b3fd62ea1a	223	/**
NYX	0:85b3fd62ea1a	224	* @}
NYX	0:85b3fd62ea1a	225	*/
NYX	0:85b3fd62ea1a	226
NYX	0:85b3fd62ea1a	227	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
NYX	0:85b3fd62ea1a	228	* @{
NYX	0:85b3fd62ea1a	229	*/
NYX	0:85b3fd62ea1a	230	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
NYX	0:85b3fd62ea1a	231	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
NYX	0:85b3fd62ea1a	232	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
NYX	0:85b3fd62ea1a	233	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
NYX	0:85b3fd62ea1a	234	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /!< PLLR used as system clock /
NYX	0:85b3fd62ea1a	235	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
NYX	0:85b3fd62ea1a	236	/**
NYX	0:85b3fd62ea1a	237	* @}
NYX	0:85b3fd62ea1a	238	*/
NYX	0:85b3fd62ea1a	239
NYX	0:85b3fd62ea1a	240	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
NYX	0:85b3fd62ea1a	241	* @{
NYX	0:85b3fd62ea1a	242	*/
NYX	0:85b3fd62ea1a	243	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
NYX	0:85b3fd62ea1a	244	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
NYX	0:85b3fd62ea1a	245	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
NYX	0:85b3fd62ea1a	246	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
NYX	0:85b3fd62ea1a	247	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
NYX	0:85b3fd62ea1a	248	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
NYX	0:85b3fd62ea1a	249	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
NYX	0:85b3fd62ea1a	250	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
NYX	0:85b3fd62ea1a	251	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
NYX	0:85b3fd62ea1a	252	/**
NYX	0:85b3fd62ea1a	253	* @}
NYX	0:85b3fd62ea1a	254	*/
NYX	0:85b3fd62ea1a	255
NYX	0:85b3fd62ea1a	256	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
NYX	0:85b3fd62ea1a	257	* @{
NYX	0:85b3fd62ea1a	258	*/
NYX	0:85b3fd62ea1a	259	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
NYX	0:85b3fd62ea1a	260	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
NYX	0:85b3fd62ea1a	261	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
NYX	0:85b3fd62ea1a	262	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
NYX	0:85b3fd62ea1a	263	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
NYX	0:85b3fd62ea1a	264	/**
NYX	0:85b3fd62ea1a	265	* @}
NYX	0:85b3fd62ea1a	266	*/
NYX	0:85b3fd62ea1a	267
NYX	0:85b3fd62ea1a	268	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
NYX	0:85b3fd62ea1a	269	* @{
NYX	0:85b3fd62ea1a	270	*/
NYX	0:85b3fd62ea1a	271	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
NYX	0:85b3fd62ea1a	272	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
NYX	0:85b3fd62ea1a	273	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
NYX	0:85b3fd62ea1a	274	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
NYX	0:85b3fd62ea1a	275	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
NYX	0:85b3fd62ea1a	276	/**
NYX	0:85b3fd62ea1a	277	* @}
NYX	0:85b3fd62ea1a	278	*/
NYX	0:85b3fd62ea1a	279
NYX	0:85b3fd62ea1a	280	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
NYX	0:85b3fd62ea1a	281	* @{
NYX	0:85b3fd62ea1a	282	*/
NYX	0:85b3fd62ea1a	283	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1\|0x00000000U) /!< HSI selection as MCO1 source /
NYX	0:85b3fd62ea1a	284	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_0 >> 16U)) /!< LSE selection as MCO1 source /
NYX	0:85b3fd62ea1a	285	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_1 >> 16U)) /!< HSE selection as MCO1 source /
NYX	0:85b3fd62ea1a	286	#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1\|((RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0) >> 16U)) /!< PLLCLK selection as MCO1 source /
NYX	0:85b3fd62ea1a	287	#if defined(RCC_CFGR_MCO2)
NYX	0:85b3fd62ea1a	288	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2\|0x00000000U) /!< SYSCLK selection as MCO2 source /
NYX	0:85b3fd62ea1a	289	#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_0 >> 16U)) /!< PLLI2S selection as MCO2 source /
NYX	0:85b3fd62ea1a	290	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_1 >> 16U)) /!< HSE selection as MCO2 source /
NYX	0:85b3fd62ea1a	291	#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2\|((RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0) >> 16U)) /!< PLLCLK selection as MCO2 source /
NYX	0:85b3fd62ea1a	292	#endif /* RCC_CFGR_MCO2 */
NYX	0:85b3fd62ea1a	293	/**
NYX	0:85b3fd62ea1a	294	* @}
NYX	0:85b3fd62ea1a	295	*/
NYX	0:85b3fd62ea1a	296
NYX	0:85b3fd62ea1a	297	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
NYX	0:85b3fd62ea1a	298	* @{
NYX	0:85b3fd62ea1a	299	*/
NYX	0:85b3fd62ea1a	300	#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE\|0x00000000U) /!< MCO1 not divided /
NYX	0:85b3fd62ea1a	301	#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE_2 >> 16U)) /!< MCO1 divided by 2 /
NYX	0:85b3fd62ea1a	302	#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_0) >> 16U)) /!< MCO1 divided by 3 /
NYX	0:85b3fd62ea1a	303	#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_1) >> 16U)) /!< MCO1 divided by 4 /
NYX	0:85b3fd62ea1a	304	#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE >> 16U)) /!< MCO1 divided by 5 /
NYX	0:85b3fd62ea1a	305	#if defined(RCC_CFGR_MCO2PRE)
NYX	0:85b3fd62ea1a	306	#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE\|0x00000000U) /!< MCO2 not divided /
NYX	0:85b3fd62ea1a	307	#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE_2 >> 16U)) /!< MCO2 divided by 2 /
NYX	0:85b3fd62ea1a	308	#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_0) >> 16U)) /!< MCO2 divided by 3 /
NYX	0:85b3fd62ea1a	309	#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_1) >> 16U)) /!< MCO2 divided by 4 /
NYX	0:85b3fd62ea1a	310	#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE >> 16U)) /!< MCO2 divided by 5 /
NYX	0:85b3fd62ea1a	311	#endif /* RCC_CFGR_MCO2PRE */
NYX	0:85b3fd62ea1a	312	/**
NYX	0:85b3fd62ea1a	313	* @}
NYX	0:85b3fd62ea1a	314	*/
NYX	0:85b3fd62ea1a	315
NYX	0:85b3fd62ea1a	316	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
NYX	0:85b3fd62ea1a	317	* @{
NYX	0:85b3fd62ea1a	318	*/
NYX	0:85b3fd62ea1a	319	#define LL_RCC_RTC_NOCLOCK 0x00000000U /!< HSE not divided /
NYX	0:85b3fd62ea1a	320	#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /!< HSE clock divided by 2 /
NYX	0:85b3fd62ea1a	321	#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 3 /
NYX	0:85b3fd62ea1a	322	#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /!< HSE clock divided by 4 /
NYX	0:85b3fd62ea1a	323	#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 5 /
NYX	0:85b3fd62ea1a	324	#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 6 /
NYX	0:85b3fd62ea1a	325	#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 7 /
NYX	0:85b3fd62ea1a	326	#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /!< HSE clock divided by 8 /
NYX	0:85b3fd62ea1a	327	#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 9 /
NYX	0:85b3fd62ea1a	328	#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 10 /
NYX	0:85b3fd62ea1a	329	#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 11 /
NYX	0:85b3fd62ea1a	330	#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 12 /
NYX	0:85b3fd62ea1a	331	#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 13 /
NYX	0:85b3fd62ea1a	332	#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 14 /
NYX	0:85b3fd62ea1a	333	#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 15 /
NYX	0:85b3fd62ea1a	334	#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /!< HSE clock divided by 16 /
NYX	0:85b3fd62ea1a	335	#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 17 /
NYX	0:85b3fd62ea1a	336	#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 18 /
NYX	0:85b3fd62ea1a	337	#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 19 /
NYX	0:85b3fd62ea1a	338	#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 20 /
NYX	0:85b3fd62ea1a	339	#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 21 /
NYX	0:85b3fd62ea1a	340	#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 22 /
NYX	0:85b3fd62ea1a	341	#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 23 /
NYX	0:85b3fd62ea1a	342	#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3) /!< HSE clock divided by 24 /
NYX	0:85b3fd62ea1a	343	#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 25 /
NYX	0:85b3fd62ea1a	344	#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 26 /
NYX	0:85b3fd62ea1a	345	#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 27 /
NYX	0:85b3fd62ea1a	346	#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 28 /
NYX	0:85b3fd62ea1a	347	#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 29 /
NYX	0:85b3fd62ea1a	348	#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 30 /
NYX	0:85b3fd62ea1a	349	#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 31 /
NYX	0:85b3fd62ea1a	350	/**
NYX	0:85b3fd62ea1a	351	* @}
NYX	0:85b3fd62ea1a	352	*/
NYX	0:85b3fd62ea1a	353
NYX	0:85b3fd62ea1a	354	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	355	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
NYX	0:85b3fd62ea1a	356	* @{
NYX	0:85b3fd62ea1a	357	*/
NYX	0:85b3fd62ea1a	358	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
NYX	0:85b3fd62ea1a	359	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
NYX	0:85b3fd62ea1a	360	/**
NYX	0:85b3fd62ea1a	361	* @}
NYX	0:85b3fd62ea1a	362	*/
NYX	0:85b3fd62ea1a	363	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	364
NYX	0:85b3fd62ea1a	365	#if defined(FMPI2C1)
NYX	0:85b3fd62ea1a	366	/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
NYX	0:85b3fd62ea1a	367	* @{
NYX	0:85b3fd62ea1a	368	*/
NYX	0:85b3fd62ea1a	369	#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as FMPI2C1 clock source /
NYX	0:85b3fd62ea1a	370	#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /!< SYSCLK clock used as FMPI2C1 clock source /
NYX	0:85b3fd62ea1a	371	#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /!< HSI clock used as FMPI2C1 clock source /
NYX	0:85b3fd62ea1a	372	/**
NYX	0:85b3fd62ea1a	373	* @}
NYX	0:85b3fd62ea1a	374	*/
NYX	0:85b3fd62ea1a	375	#endif /* FMPI2C1 */
NYX	0:85b3fd62ea1a	376
NYX	0:85b3fd62ea1a	377	#if defined(LPTIM1)
NYX	0:85b3fd62ea1a	378	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
NYX	0:85b3fd62ea1a	379	* @{
NYX	0:85b3fd62ea1a	380	*/
NYX	0:85b3fd62ea1a	381	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPTIM1 clock /
NYX	0:85b3fd62ea1a	382	#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /!< LSI oscillator clock used as LPTIM1 clock /
NYX	0:85b3fd62ea1a	383	#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /!< HSI oscillator clock used as LPTIM1 clock /
NYX	0:85b3fd62ea1a	384	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 \| RCC_DCKCFGR2_LPTIM1SEL_0) /!< LSE oscillator clock used as LPTIM1 clock /
NYX	0:85b3fd62ea1a	385	/**
NYX	0:85b3fd62ea1a	386	* @}
NYX	0:85b3fd62ea1a	387	*/
NYX	0:85b3fd62ea1a	388	#endif /* LPTIM1 */
NYX	0:85b3fd62ea1a	389
NYX	0:85b3fd62ea1a	390	#if defined(SAI1)
NYX	0:85b3fd62ea1a	391	/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
NYX	0:85b3fd62ea1a	392	* @{
NYX	0:85b3fd62ea1a	393	*/
NYX	0:85b3fd62ea1a	394	#if defined(RCC_DCKCFGR_SAI1SRC)
NYX	0:85b3fd62ea1a	395	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 clock source /
NYX	0:85b3fd62ea1a	396	#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /!< PLLI2S clock used as SAI1 clock source /
NYX	0:85b3fd62ea1a	397	#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /!< PLL clock used as SAI1 clock source /
NYX	0:85b3fd62ea1a	398	#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC \| (RCC_DCKCFGR_SAI1SRC >> 16)) /!< External pin clock used as SAI1 clock source /
NYX	0:85b3fd62ea1a	399	#endif /* RCC_DCKCFGR_SAI1SRC */
NYX	0:85b3fd62ea1a	400	#if defined(RCC_DCKCFGR_SAI2SRC)
NYX	0:85b3fd62ea1a	401	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC \| 0x00000000U) /!< PLLSAI clock used as SAI2 clock source /
NYX	0:85b3fd62ea1a	402	#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /!< PLLI2S clock used as SAI2 clock source /
NYX	0:85b3fd62ea1a	403	#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /!< PLL clock used as SAI2 clock source /
NYX	0:85b3fd62ea1a	404	#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC \| (RCC_DCKCFGR_SAI2SRC >> 16)) /!< PLL Main clock used as SAI2 clock source /
NYX	0:85b3fd62ea1a	405	#endif /* RCC_DCKCFGR_SAI2SRC */
NYX	0:85b3fd62ea1a	406	#if defined(RCC_DCKCFGR_SAI1ASRC)
NYX	0:85b3fd62ea1a	407	#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
NYX	0:85b3fd62ea1a	408	#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| 0x00000000U) /!< PLLI2S clock used as SAI1 block A clock source /
NYX	0:85b3fd62ea1a	409	#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /!< External pin used as SAI1 block A clock source /
NYX	0:85b3fd62ea1a	410	#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /!< PLL clock used as SAI1 block A clock source /
NYX	0:85b3fd62ea1a	411	#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC >> 16)) /!< PLL Main clock used as SAI1 block A clock source /
NYX	0:85b3fd62ea1a	412	#else
NYX	0:85b3fd62ea1a	413	#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 block A clock source /
NYX	0:85b3fd62ea1a	414	#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /!< PLLI2S clock used as SAI1 block A clock source /
NYX	0:85b3fd62ea1a	415	#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC \| (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /!< External pin clock used as SAI1 block A clock source /
NYX	0:85b3fd62ea1a	416	#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
NYX	0:85b3fd62ea1a	417	#endif /* RCC_DCKCFGR_SAI1ASRC */
NYX	0:85b3fd62ea1a	418	#if defined(RCC_DCKCFGR_SAI1BSRC)
NYX	0:85b3fd62ea1a	419	#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
NYX	0:85b3fd62ea1a	420	#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| 0x00000000U) /!< PLLI2S clock used as SAI1 block B clock source /
NYX	0:85b3fd62ea1a	421	#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /!< External pin used as SAI1 block B clock source /
NYX	0:85b3fd62ea1a	422	#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /!< PLL clock used as SAI1 block B clock source /
NYX	0:85b3fd62ea1a	423	#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC >> 16)) /!< PLL Main clock used as SAI1 block B clock source /
NYX	0:85b3fd62ea1a	424	#else
NYX	0:85b3fd62ea1a	425	#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| 0x00000000U) /!< PLLSAI clock used as SAI1 block B clock source /
NYX	0:85b3fd62ea1a	426	#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /!< PLLI2S clock used as SAI1 block B clock source /
NYX	0:85b3fd62ea1a	427	#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC \| (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /!< External pin clock used as SAI1 block B clock source /
NYX	0:85b3fd62ea1a	428	#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
NYX	0:85b3fd62ea1a	429	#endif /* RCC_DCKCFGR_SAI1BSRC */
NYX	0:85b3fd62ea1a	430	/**
NYX	0:85b3fd62ea1a	431	* @}
NYX	0:85b3fd62ea1a	432	*/
NYX	0:85b3fd62ea1a	433	#endif /* SAI1 */
NYX	0:85b3fd62ea1a	434
NYX	0:85b3fd62ea1a	435	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
NYX	0:85b3fd62ea1a	436	/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
NYX	0:85b3fd62ea1a	437	* @{
NYX	0:85b3fd62ea1a	438	*/
NYX	0:85b3fd62ea1a	439	#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /!< PLL 48M domain clock used as SDIO clock /
NYX	0:85b3fd62ea1a	440	#if defined(RCC_DCKCFGR_SDIOSEL)
NYX	0:85b3fd62ea1a	441	#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /!< System clock clock used as SDIO clock /
NYX	0:85b3fd62ea1a	442	#else
NYX	0:85b3fd62ea1a	443	#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /!< System clock clock used as SDIO clock /
NYX	0:85b3fd62ea1a	444	#endif /* RCC_DCKCFGR_SDIOSEL */
NYX	0:85b3fd62ea1a	445	/**
NYX	0:85b3fd62ea1a	446	* @}
NYX	0:85b3fd62ea1a	447	*/
NYX	0:85b3fd62ea1a	448	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
NYX	0:85b3fd62ea1a	449
NYX	0:85b3fd62ea1a	450	#if defined(DSI)
NYX	0:85b3fd62ea1a	451	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
NYX	0:85b3fd62ea1a	452	* @{
NYX	0:85b3fd62ea1a	453	*/
NYX	0:85b3fd62ea1a	454	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
NYX	0:85b3fd62ea1a	455	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /!< PLL clock used as DSI byte lane clock source /
NYX	0:85b3fd62ea1a	456	/**
NYX	0:85b3fd62ea1a	457	* @}
NYX	0:85b3fd62ea1a	458	*/
NYX	0:85b3fd62ea1a	459	#endif /* DSI */
NYX	0:85b3fd62ea1a	460
NYX	0:85b3fd62ea1a	461	#if defined(CEC)
NYX	0:85b3fd62ea1a	462	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
NYX	0:85b3fd62ea1a	463	* @{
NYX	0:85b3fd62ea1a	464	*/
NYX	0:85b3fd62ea1a	465	#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /!< HSI oscillator clock divided by 488 used as CEC clock /
NYX	0:85b3fd62ea1a	466	#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /!< LSE oscillator clock used as CEC clock /
NYX	0:85b3fd62ea1a	467	/**
NYX	0:85b3fd62ea1a	468	* @}
NYX	0:85b3fd62ea1a	469	*/
NYX	0:85b3fd62ea1a	470	#endif /* CEC */
NYX	0:85b3fd62ea1a	471
NYX	0:85b3fd62ea1a	472	/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
NYX	0:85b3fd62ea1a	473	* @{
NYX	0:85b3fd62ea1a	474	*/
NYX	0:85b3fd62ea1a	475	#if defined(RCC_CFGR_I2SSRC)
NYX	0:85b3fd62ea1a	476	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /!< I2S oscillator clock used as I2S1 clock /
NYX	0:85b3fd62ea1a	477	#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /!< External pin clock used as I2S1 clock /
NYX	0:85b3fd62ea1a	478	#endif /* RCC_CFGR_I2SSRC */
NYX	0:85b3fd62ea1a	479	#if defined(RCC_DCKCFGR_I2SSRC)
NYX	0:85b3fd62ea1a	480	#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC \| 0x00000000U) /!< PLL clock used as I2S1 clock source /
NYX	0:85b3fd62ea1a	481	#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC \| (RCC_DCKCFGR_I2SSRC_0 >> 16)) /!< External pin used as I2S1 clock source /
NYX	0:85b3fd62ea1a	482	#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC \| (RCC_DCKCFGR_I2SSRC_1 >> 16)) /!< PLL Main clock used as I2S1 clock source /
NYX	0:85b3fd62ea1a	483	#endif /* RCC_DCKCFGR_I2SSRC */
NYX	0:85b3fd62ea1a	484	#if defined(RCC_DCKCFGR_I2S1SRC)
NYX	0:85b3fd62ea1a	485	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC \| 0x00000000U) /!< PLLI2S clock used as I2S1 clock source /
NYX	0:85b3fd62ea1a	486	#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /!< External pin used as I2S1 clock source /
NYX	0:85b3fd62ea1a	487	#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /!< PLL clock used as I2S1 clock source /
NYX	0:85b3fd62ea1a	488	#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC \| (RCC_DCKCFGR_I2S1SRC >> 16)) /!< PLL Main clock used as I2S1 clock source /
NYX	0:85b3fd62ea1a	489	#endif /* RCC_DCKCFGR_I2S1SRC */
NYX	0:85b3fd62ea1a	490	#if defined(RCC_DCKCFGR_I2S2SRC)
NYX	0:85b3fd62ea1a	491	#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC \| 0x00000000U) /!< PLLI2S clock used as I2S2 clock source /
NYX	0:85b3fd62ea1a	492	#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /!< External pin used as I2S2 clock source /
NYX	0:85b3fd62ea1a	493	#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /!< PLL clock used as I2S2 clock source /
NYX	0:85b3fd62ea1a	494	#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC \| (RCC_DCKCFGR_I2S2SRC >> 16)) /!< PLL Main clock used as I2S2 clock source /
NYX	0:85b3fd62ea1a	495	#endif /* RCC_DCKCFGR_I2S2SRC */
NYX	0:85b3fd62ea1a	496	/**
NYX	0:85b3fd62ea1a	497	* @}
NYX	0:85b3fd62ea1a	498	*/
NYX	0:85b3fd62ea1a	499
NYX	0:85b3fd62ea1a	500	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	501	/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
NYX	0:85b3fd62ea1a	502	* @{
NYX	0:85b3fd62ea1a	503	*/
NYX	0:85b3fd62ea1a	504	#if defined(RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	505	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
NYX	0:85b3fd62ea1a	506	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
NYX	0:85b3fd62ea1a	507	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	508	#if defined(RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	509	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
NYX	0:85b3fd62ea1a	510	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	511	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
NYX	0:85b3fd62ea1a	512	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	513	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	514	#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /!< PLLI2S oscillator clock used as 48Mhz domain clock /
NYX	0:85b3fd62ea1a	515	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	516	#endif /* RCC_DCKCFGR2_CK48MSEL */
NYX	0:85b3fd62ea1a	517	/**
NYX	0:85b3fd62ea1a	518	* @}
NYX	0:85b3fd62ea1a	519	*/
NYX	0:85b3fd62ea1a	520
NYX	0:85b3fd62ea1a	521	#if defined(RNG)
NYX	0:85b3fd62ea1a	522	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
NYX	0:85b3fd62ea1a	523	* @{
NYX	0:85b3fd62ea1a	524	*/
NYX	0:85b3fd62ea1a	525	#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /!< PLL clock used as RNG clock source /
NYX	0:85b3fd62ea1a	526	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	527	#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /!< PLLSAI clock used as RNG clock source /
NYX	0:85b3fd62ea1a	528	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	529	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	530	#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /!< PLLI2S clock used as RNG clock source /
NYX	0:85b3fd62ea1a	531	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	532	/**
NYX	0:85b3fd62ea1a	533	* @}
NYX	0:85b3fd62ea1a	534	*/
NYX	0:85b3fd62ea1a	535	#endif /* RNG */
NYX	0:85b3fd62ea1a	536
NYX	0:85b3fd62ea1a	537	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
NYX	0:85b3fd62ea1a	538	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
NYX	0:85b3fd62ea1a	539	* @{
NYX	0:85b3fd62ea1a	540	*/
NYX	0:85b3fd62ea1a	541	#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /!< PLL clock used as USB clock source /
NYX	0:85b3fd62ea1a	542	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	543	#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /!< PLLSAI clock used as USB clock source /
NYX	0:85b3fd62ea1a	544	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	545	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	546	#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /!< PLLI2S clock used as USB clock source /
NYX	0:85b3fd62ea1a	547	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	548	/**
NYX	0:85b3fd62ea1a	549	* @}
NYX	0:85b3fd62ea1a	550	*/
NYX	0:85b3fd62ea1a	551	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
NYX	0:85b3fd62ea1a	552
NYX	0:85b3fd62ea1a	553	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
NYX	0:85b3fd62ea1a	554
NYX	0:85b3fd62ea1a	555	#if defined(DFSDM1_Channel0) \|\| defined(DFSDM2_Channel0)
NYX	0:85b3fd62ea1a	556	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
NYX	0:85b3fd62ea1a	557	* @{
NYX	0:85b3fd62ea1a	558	*/
NYX	0:85b3fd62ea1a	559	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL \| 0x00000000U) /!< I2S1 clock used as DFSDM1 Audio clock source /
NYX	0:85b3fd62ea1a	560	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL \| (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /!< I2S2 clock used as DFSDM1 Audio clock source /
NYX	0:85b3fd62ea1a	561	#if defined(DFSDM2_Channel0)
NYX	0:85b3fd62ea1a	562	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL \| 0x00000000U) /!< I2S1 clock used as DFSDM2 Audio clock source /
NYX	0:85b3fd62ea1a	563	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL \| (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /!< I2S2 clock used as DFSDM2 Audio clock source /
NYX	0:85b3fd62ea1a	564	#endif /* DFSDM2_Channel0 */
NYX	0:85b3fd62ea1a	565	/**
NYX	0:85b3fd62ea1a	566	* @}
NYX	0:85b3fd62ea1a	567	*/
NYX	0:85b3fd62ea1a	568
NYX	0:85b3fd62ea1a	569	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
NYX	0:85b3fd62ea1a	570	* @{
NYX	0:85b3fd62ea1a	571	*/
NYX	0:85b3fd62ea1a	572	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM1 clock /
NYX	0:85b3fd62ea1a	573	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /!< System clock used as DFSDM1 clock /
NYX	0:85b3fd62ea1a	574	#if defined(DFSDM2_Channel0)
NYX	0:85b3fd62ea1a	575	#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM2 clock /
NYX	0:85b3fd62ea1a	576	#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /!< System clock used as DFSDM2 clock /
NYX	0:85b3fd62ea1a	577	#endif /* DFSDM2_Channel0 */
NYX	0:85b3fd62ea1a	578	/**
NYX	0:85b3fd62ea1a	579	* @}
NYX	0:85b3fd62ea1a	580	*/
NYX	0:85b3fd62ea1a	581	#endif /* DFSDM1_Channel0 \|\| DFSDM2_Channel0 */
NYX	0:85b3fd62ea1a	582
NYX	0:85b3fd62ea1a	583	#if defined(FMPI2C1)
NYX	0:85b3fd62ea1a	584	/** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
NYX	0:85b3fd62ea1a	585	* @{
NYX	0:85b3fd62ea1a	586	*/
NYX	0:85b3fd62ea1a	587	#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /!< FMPI2C1 Clock source selection /
NYX	0:85b3fd62ea1a	588	/**
NYX	0:85b3fd62ea1a	589	* @}
NYX	0:85b3fd62ea1a	590	*/
NYX	0:85b3fd62ea1a	591	#endif /* FMPI2C1 */
NYX	0:85b3fd62ea1a	592
NYX	0:85b3fd62ea1a	593	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	594	/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
NYX	0:85b3fd62ea1a	595	* @{
NYX	0:85b3fd62ea1a	596	*/
NYX	0:85b3fd62ea1a	597	#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /!< PLL clock used as SPDIFRX clock source /
NYX	0:85b3fd62ea1a	598	#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /!< PLLI2S clock used as SPDIFRX clock source /
NYX	0:85b3fd62ea1a	599	/**
NYX	0:85b3fd62ea1a	600	* @}
NYX	0:85b3fd62ea1a	601	*/
NYX	0:85b3fd62ea1a	602	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	603
NYX	0:85b3fd62ea1a	604	#if defined(LPTIM1)
NYX	0:85b3fd62ea1a	605	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
NYX	0:85b3fd62ea1a	606	* @{
NYX	0:85b3fd62ea1a	607	*/
NYX	0:85b3fd62ea1a	608	#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /!< LPTIM1 Clock source selection /
NYX	0:85b3fd62ea1a	609	/**
NYX	0:85b3fd62ea1a	610	* @}
NYX	0:85b3fd62ea1a	611	*/
NYX	0:85b3fd62ea1a	612	#endif /* LPTIM1 */
NYX	0:85b3fd62ea1a	613
NYX	0:85b3fd62ea1a	614	#if defined(SAI1)
NYX	0:85b3fd62ea1a	615	/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
NYX	0:85b3fd62ea1a	616	* @{
NYX	0:85b3fd62ea1a	617	*/
NYX	0:85b3fd62ea1a	618	#if defined(RCC_DCKCFGR_SAI1ASRC)
NYX	0:85b3fd62ea1a	619	#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /!< SAI1 block A Clock source selection /
NYX	0:85b3fd62ea1a	620	#endif /* RCC_DCKCFGR_SAI1ASRC */
NYX	0:85b3fd62ea1a	621	#if defined(RCC_DCKCFGR_SAI1BSRC)
NYX	0:85b3fd62ea1a	622	#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /!< SAI1 block B Clock source selection /
NYX	0:85b3fd62ea1a	623	#endif /* RCC_DCKCFGR_SAI1BSRC */
NYX	0:85b3fd62ea1a	624	#if defined(RCC_DCKCFGR_SAI1SRC)
NYX	0:85b3fd62ea1a	625	#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /!< SAI1 Clock source selection /
NYX	0:85b3fd62ea1a	626	#endif /* RCC_DCKCFGR_SAI1SRC */
NYX	0:85b3fd62ea1a	627	#if defined(RCC_DCKCFGR_SAI2SRC)
NYX	0:85b3fd62ea1a	628	#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /!< SAI2 Clock source selection /
NYX	0:85b3fd62ea1a	629	#endif /* RCC_DCKCFGR_SAI2SRC */
NYX	0:85b3fd62ea1a	630	/**
NYX	0:85b3fd62ea1a	631	* @}
NYX	0:85b3fd62ea1a	632	*/
NYX	0:85b3fd62ea1a	633	#endif /* SAI1 */
NYX	0:85b3fd62ea1a	634
NYX	0:85b3fd62ea1a	635	#if defined(SDIO)
NYX	0:85b3fd62ea1a	636	/** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
NYX	0:85b3fd62ea1a	637	* @{
NYX	0:85b3fd62ea1a	638	*/
NYX	0:85b3fd62ea1a	639	#if defined(RCC_DCKCFGR_SDIOSEL)
NYX	0:85b3fd62ea1a	640	#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /!< SDIO Clock source selection /
NYX	0:85b3fd62ea1a	641	#elif defined(RCC_DCKCFGR2_SDIOSEL)
NYX	0:85b3fd62ea1a	642	#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /!< SDIO Clock source selection /
NYX	0:85b3fd62ea1a	643	#else
NYX	0:85b3fd62ea1a	644	#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /!< SDIO Clock source selection /
NYX	0:85b3fd62ea1a	645	#endif
NYX	0:85b3fd62ea1a	646	/**
NYX	0:85b3fd62ea1a	647	* @}
NYX	0:85b3fd62ea1a	648	*/
NYX	0:85b3fd62ea1a	649	#endif /* SDIO */
NYX	0:85b3fd62ea1a	650
NYX	0:85b3fd62ea1a	651	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	652	/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
NYX	0:85b3fd62ea1a	653	* @{
NYX	0:85b3fd62ea1a	654	*/
NYX	0:85b3fd62ea1a	655	#if defined(RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	656	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /!< CK48M Domain clock source selection /
NYX	0:85b3fd62ea1a	657	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	658	#if defined(RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	659	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< CK48M Domain clock source selection /
NYX	0:85b3fd62ea1a	660	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	661	/**
NYX	0:85b3fd62ea1a	662	* @}
NYX	0:85b3fd62ea1a	663	*/
NYX	0:85b3fd62ea1a	664	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
NYX	0:85b3fd62ea1a	665
NYX	0:85b3fd62ea1a	666	#if defined(RNG)
NYX	0:85b3fd62ea1a	667	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
NYX	0:85b3fd62ea1a	668	* @{
NYX	0:85b3fd62ea1a	669	*/
NYX	0:85b3fd62ea1a	670	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	671	#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /!< RNG Clock source selection /
NYX	0:85b3fd62ea1a	672	#else
NYX	0:85b3fd62ea1a	673	#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /!< RNG Clock source selection /
NYX	0:85b3fd62ea1a	674	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
NYX	0:85b3fd62ea1a	675	/**
NYX	0:85b3fd62ea1a	676	* @}
NYX	0:85b3fd62ea1a	677	*/
NYX	0:85b3fd62ea1a	678	#endif /* RNG */
NYX	0:85b3fd62ea1a	679
NYX	0:85b3fd62ea1a	680	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
NYX	0:85b3fd62ea1a	681	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
NYX	0:85b3fd62ea1a	682	* @{
NYX	0:85b3fd62ea1a	683	*/
NYX	0:85b3fd62ea1a	684	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	685	#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /!< USB Clock source selection /
NYX	0:85b3fd62ea1a	686	#else
NYX	0:85b3fd62ea1a	687	#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /!< USB Clock source selection /
NYX	0:85b3fd62ea1a	688	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
NYX	0:85b3fd62ea1a	689	/**
NYX	0:85b3fd62ea1a	690	* @}
NYX	0:85b3fd62ea1a	691	*/
NYX	0:85b3fd62ea1a	692	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
NYX	0:85b3fd62ea1a	693
NYX	0:85b3fd62ea1a	694	#if defined(CEC)
NYX	0:85b3fd62ea1a	695	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
NYX	0:85b3fd62ea1a	696	* @{
NYX	0:85b3fd62ea1a	697	*/
NYX	0:85b3fd62ea1a	698	#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /!< CEC Clock source selection /
NYX	0:85b3fd62ea1a	699	/**
NYX	0:85b3fd62ea1a	700	* @}
NYX	0:85b3fd62ea1a	701	*/
NYX	0:85b3fd62ea1a	702	#endif /* CEC */
NYX	0:85b3fd62ea1a	703
NYX	0:85b3fd62ea1a	704	/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
NYX	0:85b3fd62ea1a	705	* @{
NYX	0:85b3fd62ea1a	706	*/
NYX	0:85b3fd62ea1a	707	#if defined(RCC_CFGR_I2SSRC)
NYX	0:85b3fd62ea1a	708	#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /!< I2S1 Clock source selection /
NYX	0:85b3fd62ea1a	709	#endif /* RCC_CFGR_I2SSRC */
NYX	0:85b3fd62ea1a	710	#if defined(RCC_DCKCFGR_I2SSRC)
NYX	0:85b3fd62ea1a	711	#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /!< I2S1 Clock source selection /
NYX	0:85b3fd62ea1a	712	#endif /* RCC_DCKCFGR_I2SSRC */
NYX	0:85b3fd62ea1a	713	#if defined(RCC_DCKCFGR_I2S1SRC)
NYX	0:85b3fd62ea1a	714	#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /!< I2S1 Clock source selection /
NYX	0:85b3fd62ea1a	715	#endif /* RCC_DCKCFGR_I2S1SRC */
NYX	0:85b3fd62ea1a	716	#if defined(RCC_DCKCFGR_I2S2SRC)
NYX	0:85b3fd62ea1a	717	#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /!< I2S2 Clock source selection /
NYX	0:85b3fd62ea1a	718	#endif /* RCC_DCKCFGR_I2S2SRC */
NYX	0:85b3fd62ea1a	719	/**
NYX	0:85b3fd62ea1a	720	* @}
NYX	0:85b3fd62ea1a	721	*/
NYX	0:85b3fd62ea1a	722
NYX	0:85b3fd62ea1a	723	#if defined(DFSDM1_Channel0) \|\| defined(DFSDM2_Channel0)
NYX	0:85b3fd62ea1a	724	/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
NYX	0:85b3fd62ea1a	725	* @{
NYX	0:85b3fd62ea1a	726	*/
NYX	0:85b3fd62ea1a	727	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /!< DFSDM1 Audio Clock source selection /
NYX	0:85b3fd62ea1a	728	#if defined(DFSDM2_Channel0)
NYX	0:85b3fd62ea1a	729	#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /!< DFSDM2 Audio Clock source selection /
NYX	0:85b3fd62ea1a	730	#endif /* DFSDM2_Channel0 */
NYX	0:85b3fd62ea1a	731	/**
NYX	0:85b3fd62ea1a	732	* @}
NYX	0:85b3fd62ea1a	733	*/
NYX	0:85b3fd62ea1a	734
NYX	0:85b3fd62ea1a	735	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
NYX	0:85b3fd62ea1a	736	* @{
NYX	0:85b3fd62ea1a	737	*/
NYX	0:85b3fd62ea1a	738	#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /!< DFSDM1 Clock source selection /
NYX	0:85b3fd62ea1a	739	#if defined(DFSDM2_Channel0)
NYX	0:85b3fd62ea1a	740	#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /!< DFSDM2 Clock source selection /
NYX	0:85b3fd62ea1a	741	#endif /* DFSDM2_Channel0 */
NYX	0:85b3fd62ea1a	742	/**
NYX	0:85b3fd62ea1a	743	* @}
NYX	0:85b3fd62ea1a	744	*/
NYX	0:85b3fd62ea1a	745	#endif /* DFSDM1_Channel0 \|\| DFSDM2_Channel0 */
NYX	0:85b3fd62ea1a	746
NYX	0:85b3fd62ea1a	747	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	748	/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
NYX	0:85b3fd62ea1a	749	* @{
NYX	0:85b3fd62ea1a	750	*/
NYX	0:85b3fd62ea1a	751	#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /!< SPDIFRX Clock source selection /
NYX	0:85b3fd62ea1a	752	/**
NYX	0:85b3fd62ea1a	753	* @}
NYX	0:85b3fd62ea1a	754	*/
NYX	0:85b3fd62ea1a	755	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	756
NYX	0:85b3fd62ea1a	757	#if defined(DSI)
NYX	0:85b3fd62ea1a	758	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
NYX	0:85b3fd62ea1a	759	* @{
NYX	0:85b3fd62ea1a	760	*/
NYX	0:85b3fd62ea1a	761	#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /!< DSI Clock source selection /
NYX	0:85b3fd62ea1a	762	/**
NYX	0:85b3fd62ea1a	763	* @}
NYX	0:85b3fd62ea1a	764	*/
NYX	0:85b3fd62ea1a	765	#endif /* DSI */
NYX	0:85b3fd62ea1a	766
NYX	0:85b3fd62ea1a	767	#if defined(LTDC)
NYX	0:85b3fd62ea1a	768	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
NYX	0:85b3fd62ea1a	769	* @{
NYX	0:85b3fd62ea1a	770	*/
NYX	0:85b3fd62ea1a	771	#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /!< LTDC Clock source selection /
NYX	0:85b3fd62ea1a	772	/**
NYX	0:85b3fd62ea1a	773	* @}
NYX	0:85b3fd62ea1a	774	*/
NYX	0:85b3fd62ea1a	775	#endif /* LTDC */
NYX	0:85b3fd62ea1a	776
NYX	0:85b3fd62ea1a	777
NYX	0:85b3fd62ea1a	778	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
NYX	0:85b3fd62ea1a	779	* @{
NYX	0:85b3fd62ea1a	780	*/
NYX	0:85b3fd62ea1a	781	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
NYX	0:85b3fd62ea1a	782	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
NYX	0:85b3fd62ea1a	783	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
NYX	0:85b3fd62ea1a	784	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by HSE prescaler used as RTC clock /
NYX	0:85b3fd62ea1a	785	/**
NYX	0:85b3fd62ea1a	786	* @}
NYX	0:85b3fd62ea1a	787	*/
NYX	0:85b3fd62ea1a	788
NYX	0:85b3fd62ea1a	789	#if defined(RCC_DCKCFGR_TIMPRE)
NYX	0:85b3fd62ea1a	790	/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
NYX	0:85b3fd62ea1a	791	* @{
NYX	0:85b3fd62ea1a	792	*/
NYX	0:85b3fd62ea1a	793	#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /!< Timers clock to twice PCLK /
NYX	0:85b3fd62ea1a	794	#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /!< Timers clock to four time PCLK /
NYX	0:85b3fd62ea1a	795	/**
NYX	0:85b3fd62ea1a	796	* @}
NYX	0:85b3fd62ea1a	797	*/
NYX	0:85b3fd62ea1a	798	#endif /* RCC_DCKCFGR_TIMPRE */
NYX	0:85b3fd62ea1a	799
NYX	0:85b3fd62ea1a	800	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
NYX	0:85b3fd62ea1a	801	* @{
NYX	0:85b3fd62ea1a	802	*/
NYX	0:85b3fd62ea1a	803	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
NYX	0:85b3fd62ea1a	804	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
NYX	0:85b3fd62ea1a	805	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
NYX	0:85b3fd62ea1a	806	#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC \| 0x80U) /!< I2S External pin input clock selected as PLLI2S entry clock source /
NYX	0:85b3fd62ea1a	807	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
NYX	0:85b3fd62ea1a	808	/**
NYX	0:85b3fd62ea1a	809	* @}
NYX	0:85b3fd62ea1a	810	*/
NYX	0:85b3fd62ea1a	811
NYX	0:85b3fd62ea1a	812	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
NYX	0:85b3fd62ea1a	813	* @{
NYX	0:85b3fd62ea1a	814	*/
NYX	0:85b3fd62ea1a	815	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 2 /
NYX	0:85b3fd62ea1a	816	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 3 /
NYX	0:85b3fd62ea1a	817	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 4 /
NYX	0:85b3fd62ea1a	818	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 5 /
NYX	0:85b3fd62ea1a	819	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 6 /
NYX	0:85b3fd62ea1a	820	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 7 /
NYX	0:85b3fd62ea1a	821	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 8 /
NYX	0:85b3fd62ea1a	822	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 9 /
NYX	0:85b3fd62ea1a	823	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 10 /
NYX	0:85b3fd62ea1a	824	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 11 /
NYX	0:85b3fd62ea1a	825	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 12 /
NYX	0:85b3fd62ea1a	826	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 13 /
NYX	0:85b3fd62ea1a	827	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 14 /
NYX	0:85b3fd62ea1a	828	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 15 /
NYX	0:85b3fd62ea1a	829	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 16 /
NYX	0:85b3fd62ea1a	830	#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 17 /
NYX	0:85b3fd62ea1a	831	#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 18 /
NYX	0:85b3fd62ea1a	832	#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 19 /
NYX	0:85b3fd62ea1a	833	#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 20 /
NYX	0:85b3fd62ea1a	834	#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 21 /
NYX	0:85b3fd62ea1a	835	#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 22 /
NYX	0:85b3fd62ea1a	836	#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 23 /
NYX	0:85b3fd62ea1a	837	#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 24 /
NYX	0:85b3fd62ea1a	838	#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 25 /
NYX	0:85b3fd62ea1a	839	#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 26 /
NYX	0:85b3fd62ea1a	840	#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 27 /
NYX	0:85b3fd62ea1a	841	#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 28 /
NYX	0:85b3fd62ea1a	842	#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 29 /
NYX	0:85b3fd62ea1a	843	#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 30 /
NYX	0:85b3fd62ea1a	844	#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 31 /
NYX	0:85b3fd62ea1a	845	#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /!< PLL, PLLI2S and PLLSAI division factor by 32 /
NYX	0:85b3fd62ea1a	846	#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 33 /
NYX	0:85b3fd62ea1a	847	#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 34 /
NYX	0:85b3fd62ea1a	848	#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 35 /
NYX	0:85b3fd62ea1a	849	#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 36 /
NYX	0:85b3fd62ea1a	850	#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 37 /
NYX	0:85b3fd62ea1a	851	#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 38 /
NYX	0:85b3fd62ea1a	852	#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 39 /
NYX	0:85b3fd62ea1a	853	#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 40 /
NYX	0:85b3fd62ea1a	854	#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 41 /
NYX	0:85b3fd62ea1a	855	#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 42 /
NYX	0:85b3fd62ea1a	856	#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 43 /
NYX	0:85b3fd62ea1a	857	#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 44 /
NYX	0:85b3fd62ea1a	858	#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 45 /
NYX	0:85b3fd62ea1a	859	#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 46 /
NYX	0:85b3fd62ea1a	860	#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 47 /
NYX	0:85b3fd62ea1a	861	#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 48 /
NYX	0:85b3fd62ea1a	862	#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 49 /
NYX	0:85b3fd62ea1a	863	#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 50 /
NYX	0:85b3fd62ea1a	864	#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 51 /
NYX	0:85b3fd62ea1a	865	#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 52 /
NYX	0:85b3fd62ea1a	866	#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 53 /
NYX	0:85b3fd62ea1a	867	#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 54 /
NYX	0:85b3fd62ea1a	868	#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 55 /
NYX	0:85b3fd62ea1a	869	#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 56 /
NYX	0:85b3fd62ea1a	870	#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 57 /
NYX	0:85b3fd62ea1a	871	#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 58 /
NYX	0:85b3fd62ea1a	872	#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 59 /
NYX	0:85b3fd62ea1a	873	#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 60 /
NYX	0:85b3fd62ea1a	874	#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 61 /
NYX	0:85b3fd62ea1a	875	#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 62 /
NYX	0:85b3fd62ea1a	876	#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 63 /
NYX	0:85b3fd62ea1a	877	/**
NYX	0:85b3fd62ea1a	878	* @}
NYX	0:85b3fd62ea1a	879	*/
NYX	0:85b3fd62ea1a	880
NYX	0:85b3fd62ea1a	881	#if defined(RCC_PLLCFGR_PLLR)
NYX	0:85b3fd62ea1a	882	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
NYX	0:85b3fd62ea1a	883	* @{
NYX	0:85b3fd62ea1a	884	*/
NYX	0:85b3fd62ea1a	885	#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 2 /
NYX	0:85b3fd62ea1a	886	#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 3 /
NYX	0:85b3fd62ea1a	887	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
NYX	0:85b3fd62ea1a	888	#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 5 /
NYX	0:85b3fd62ea1a	889	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
NYX	0:85b3fd62ea1a	890	#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 7 /
NYX	0:85b3fd62ea1a	891	/**
NYX	0:85b3fd62ea1a	892	* @}
NYX	0:85b3fd62ea1a	893	*/
NYX	0:85b3fd62ea1a	894	#endif /* RCC_PLLCFGR_PLLR */
NYX	0:85b3fd62ea1a	895
NYX	0:85b3fd62ea1a	896	#if defined(RCC_DCKCFGR_PLLDIVR)
NYX	0:85b3fd62ea1a	897	/** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
NYX	0:85b3fd62ea1a	898	* @{
NYX	0:85b3fd62ea1a	899	*/
NYX	0:85b3fd62ea1a	900	#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 1 /
NYX	0:85b3fd62ea1a	901	#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 2 /
NYX	0:85b3fd62ea1a	902	#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 3 /
NYX	0:85b3fd62ea1a	903	#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 4 /
NYX	0:85b3fd62ea1a	904	#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 5 /
NYX	0:85b3fd62ea1a	905	#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 6 /
NYX	0:85b3fd62ea1a	906	#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 7 /
NYX	0:85b3fd62ea1a	907	#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /!< PLL division factor for PLLDIVR output by 8 /
NYX	0:85b3fd62ea1a	908	#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 9 /
NYX	0:85b3fd62ea1a	909	#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 10 /
NYX	0:85b3fd62ea1a	910	#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 11 /
NYX	0:85b3fd62ea1a	911	#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 12 /
NYX	0:85b3fd62ea1a	912	#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 13 /
NYX	0:85b3fd62ea1a	913	#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 14 /
NYX	0:85b3fd62ea1a	914	#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 15 /
NYX	0:85b3fd62ea1a	915	#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /!< PLL division factor for PLLDIVR output by 16 /
NYX	0:85b3fd62ea1a	916	#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 17 /
NYX	0:85b3fd62ea1a	917	#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 18 /
NYX	0:85b3fd62ea1a	918	#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 19 /
NYX	0:85b3fd62ea1a	919	#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 20 /
NYX	0:85b3fd62ea1a	920	#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 21 /
NYX	0:85b3fd62ea1a	921	#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 22 /
NYX	0:85b3fd62ea1a	922	#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 23 /
NYX	0:85b3fd62ea1a	923	#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3) /!< PLL division factor for PLLDIVR output by 24 /
NYX	0:85b3fd62ea1a	924	#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 25 /
NYX	0:85b3fd62ea1a	925	#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 26 /
NYX	0:85b3fd62ea1a	926	#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 27 /
NYX	0:85b3fd62ea1a	927	#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2) /!< PLL division factor for PLLDIVR output by 28 /
NYX	0:85b3fd62ea1a	928	#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 29 /
NYX	0:85b3fd62ea1a	929	#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1) /!< PLL division factor for PLLDIVR output by 30 /
NYX	0:85b3fd62ea1a	930	#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 \| RCC_DCKCFGR_PLLDIVR_3 \| RCC_DCKCFGR_PLLDIVR_2 \| RCC_DCKCFGR_PLLDIVR_1 \| RCC_DCKCFGR_PLLDIVR_0) /!< PLL division factor for PLLDIVR output by 31 /
NYX	0:85b3fd62ea1a	931	/**
NYX	0:85b3fd62ea1a	932	* @}
NYX	0:85b3fd62ea1a	933	*/
NYX	0:85b3fd62ea1a	934	#endif /* RCC_DCKCFGR_PLLDIVR */
NYX	0:85b3fd62ea1a	935
NYX	0:85b3fd62ea1a	936	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
NYX	0:85b3fd62ea1a	937	* @{
NYX	0:85b3fd62ea1a	938	*/
NYX	0:85b3fd62ea1a	939	#define LL_RCC_PLLP_DIV_2 0x00000000U /!< Main PLL division factor for PLLP output by 2 /
NYX	0:85b3fd62ea1a	940	#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /!< Main PLL division factor for PLLP output by 4 /
NYX	0:85b3fd62ea1a	941	#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /!< Main PLL division factor for PLLP output by 6 /
NYX	0:85b3fd62ea1a	942	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 \| RCC_PLLCFGR_PLLP_0) /!< Main PLL division factor for PLLP output by 8 /
NYX	0:85b3fd62ea1a	943	/**
NYX	0:85b3fd62ea1a	944	* @}
NYX	0:85b3fd62ea1a	945	*/
NYX	0:85b3fd62ea1a	946
NYX	0:85b3fd62ea1a	947	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
NYX	0:85b3fd62ea1a	948	* @{
NYX	0:85b3fd62ea1a	949	*/
NYX	0:85b3fd62ea1a	950	#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /!< Main PLL division factor for PLLQ output by 2 /
NYX	0:85b3fd62ea1a	951	#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 3 /
NYX	0:85b3fd62ea1a	952	#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /!< Main PLL division factor for PLLQ output by 4 /
NYX	0:85b3fd62ea1a	953	#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 5 /
NYX	0:85b3fd62ea1a	954	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
NYX	0:85b3fd62ea1a	955	#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 7 /
NYX	0:85b3fd62ea1a	956	#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /!< Main PLL division factor for PLLQ output by 8 /
NYX	0:85b3fd62ea1a	957	#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 9 /
NYX	0:85b3fd62ea1a	958	#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 10 /
NYX	0:85b3fd62ea1a	959	#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 11 /
NYX	0:85b3fd62ea1a	960	#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2) /!< Main PLL division factor for PLLQ output by 12 /
NYX	0:85b3fd62ea1a	961	#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 13 /
NYX	0:85b3fd62ea1a	962	#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 14 /
NYX	0:85b3fd62ea1a	963	#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 15 /
NYX	0:85b3fd62ea1a	964	/**
NYX	0:85b3fd62ea1a	965	* @}
NYX	0:85b3fd62ea1a	966	*/
NYX	0:85b3fd62ea1a	967
NYX	0:85b3fd62ea1a	968	/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
NYX	0:85b3fd62ea1a	969	* @{
NYX	0:85b3fd62ea1a	970	*/
NYX	0:85b3fd62ea1a	971	#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /!< PLL center spread spectrum selection /
NYX	0:85b3fd62ea1a	972	#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /!< PLL down spread spectrum selection /
NYX	0:85b3fd62ea1a	973	/**
NYX	0:85b3fd62ea1a	974	* @}
NYX	0:85b3fd62ea1a	975	*/
NYX	0:85b3fd62ea1a	976
NYX	0:85b3fd62ea1a	977	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	978	/** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
NYX	0:85b3fd62ea1a	979	* @{
NYX	0:85b3fd62ea1a	980	*/
NYX	0:85b3fd62ea1a	981	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
NYX	0:85b3fd62ea1a	982	#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 2 /
NYX	0:85b3fd62ea1a	983	#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 3 /
NYX	0:85b3fd62ea1a	984	#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 4 /
NYX	0:85b3fd62ea1a	985	#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 5 /
NYX	0:85b3fd62ea1a	986	#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 6 /
NYX	0:85b3fd62ea1a	987	#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 7 /
NYX	0:85b3fd62ea1a	988	#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 8 /
NYX	0:85b3fd62ea1a	989	#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 9 /
NYX	0:85b3fd62ea1a	990	#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 10 /
NYX	0:85b3fd62ea1a	991	#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 11 /
NYX	0:85b3fd62ea1a	992	#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 12 /
NYX	0:85b3fd62ea1a	993	#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 13 /
NYX	0:85b3fd62ea1a	994	#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 14 /
NYX	0:85b3fd62ea1a	995	#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 15 /
NYX	0:85b3fd62ea1a	996	#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /!< PLLI2S division factor for PLLI2SM output by 16 /
NYX	0:85b3fd62ea1a	997	#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 17 /
NYX	0:85b3fd62ea1a	998	#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 18 /
NYX	0:85b3fd62ea1a	999	#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 19 /
NYX	0:85b3fd62ea1a	1000	#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 20 /
NYX	0:85b3fd62ea1a	1001	#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 21 /
NYX	0:85b3fd62ea1a	1002	#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 22 /
NYX	0:85b3fd62ea1a	1003	#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 23 /
NYX	0:85b3fd62ea1a	1004	#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 24 /
NYX	0:85b3fd62ea1a	1005	#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 25 /
NYX	0:85b3fd62ea1a	1006	#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 26 /
NYX	0:85b3fd62ea1a	1007	#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 27 /
NYX	0:85b3fd62ea1a	1008	#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 28 /
NYX	0:85b3fd62ea1a	1009	#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 29 /
NYX	0:85b3fd62ea1a	1010	#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 30 /
NYX	0:85b3fd62ea1a	1011	#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 31 /
NYX	0:85b3fd62ea1a	1012	#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /!< PLLI2S division factor for PLLI2SM output by 32 /
NYX	0:85b3fd62ea1a	1013	#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 33 /
NYX	0:85b3fd62ea1a	1014	#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 34 /
NYX	0:85b3fd62ea1a	1015	#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 35 /
NYX	0:85b3fd62ea1a	1016	#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 36 /
NYX	0:85b3fd62ea1a	1017	#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 37 /
NYX	0:85b3fd62ea1a	1018	#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 38 /
NYX	0:85b3fd62ea1a	1019	#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 39 /
NYX	0:85b3fd62ea1a	1020	#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 40 /
NYX	0:85b3fd62ea1a	1021	#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 41 /
NYX	0:85b3fd62ea1a	1022	#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 42 /
NYX	0:85b3fd62ea1a	1023	#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 43 /
NYX	0:85b3fd62ea1a	1024	#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 44 /
NYX	0:85b3fd62ea1a	1025	#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 45 /
NYX	0:85b3fd62ea1a	1026	#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 46 /
NYX	0:85b3fd62ea1a	1027	#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 47 /
NYX	0:85b3fd62ea1a	1028	#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4) /!< PLLI2S division factor for PLLI2SM output by 48 /
NYX	0:85b3fd62ea1a	1029	#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 49 /
NYX	0:85b3fd62ea1a	1030	#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 50 /
NYX	0:85b3fd62ea1a	1031	#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 51 /
NYX	0:85b3fd62ea1a	1032	#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 52 /
NYX	0:85b3fd62ea1a	1033	#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 53 /
NYX	0:85b3fd62ea1a	1034	#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 54 /
NYX	0:85b3fd62ea1a	1035	#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 55 /
NYX	0:85b3fd62ea1a	1036	#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3) /!< PLLI2S division factor for PLLI2SM output by 56 /
NYX	0:85b3fd62ea1a	1037	#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 57 /
NYX	0:85b3fd62ea1a	1038	#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 58 /
NYX	0:85b3fd62ea1a	1039	#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 59 /
NYX	0:85b3fd62ea1a	1040	#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2) /!< PLLI2S division factor for PLLI2SM output by 60 /
NYX	0:85b3fd62ea1a	1041	#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 61 /
NYX	0:85b3fd62ea1a	1042	#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1) /!< PLLI2S division factor for PLLI2SM output by 62 /
NYX	0:85b3fd62ea1a	1043	#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 \| RCC_PLLI2SCFGR_PLLI2SM_4 \| RCC_PLLI2SCFGR_PLLI2SM_3 \| RCC_PLLI2SCFGR_PLLI2SM_2 \| RCC_PLLI2SCFGR_PLLI2SM_1 \| RCC_PLLI2SCFGR_PLLI2SM_0) /!< PLLI2S division factor for PLLI2SM output by 63 /
NYX	0:85b3fd62ea1a	1044	#else
NYX	0:85b3fd62ea1a	1045	#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /!< PLLI2S division factor for PLLI2SM output by 2 /
NYX	0:85b3fd62ea1a	1046	#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /!< PLLI2S division factor for PLLI2SM output by 3 /
NYX	0:85b3fd62ea1a	1047	#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /!< PLLI2S division factor for PLLI2SM output by 4 /
NYX	0:85b3fd62ea1a	1048	#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /!< PLLI2S division factor for PLLI2SM output by 5 /
NYX	0:85b3fd62ea1a	1049	#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /!< PLLI2S division factor for PLLI2SM output by 6 /
NYX	0:85b3fd62ea1a	1050	#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /!< PLLI2S division factor for PLLI2SM output by 7 /
NYX	0:85b3fd62ea1a	1051	#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /!< PLLI2S division factor for PLLI2SM output by 8 /
NYX	0:85b3fd62ea1a	1052	#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /!< PLLI2S division factor for PLLI2SM output by 9 /
NYX	0:85b3fd62ea1a	1053	#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /!< PLLI2S division factor for PLLI2SM output by 10 /
NYX	0:85b3fd62ea1a	1054	#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /!< PLLI2S division factor for PLLI2SM output by 11 /
NYX	0:85b3fd62ea1a	1055	#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /!< PLLI2S division factor for PLLI2SM output by 12 /
NYX	0:85b3fd62ea1a	1056	#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /!< PLLI2S division factor for PLLI2SM output by 13 /
NYX	0:85b3fd62ea1a	1057	#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /!< PLLI2S division factor for PLLI2SM output by 14 /
NYX	0:85b3fd62ea1a	1058	#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /!< PLLI2S division factor for PLLI2SM output by 15 /
NYX	0:85b3fd62ea1a	1059	#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /!< PLLI2S division factor for PLLI2SM output by 16 /
NYX	0:85b3fd62ea1a	1060	#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /!< PLLI2S division factor for PLLI2SM output by 17 /
NYX	0:85b3fd62ea1a	1061	#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /!< PLLI2S division factor for PLLI2SM output by 18 /
NYX	0:85b3fd62ea1a	1062	#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /!< PLLI2S division factor for PLLI2SM output by 19 /
NYX	0:85b3fd62ea1a	1063	#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /!< PLLI2S division factor for PLLI2SM output by 20 /
NYX	0:85b3fd62ea1a	1064	#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /!< PLLI2S division factor for PLLI2SM output by 21 /
NYX	0:85b3fd62ea1a	1065	#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /!< PLLI2S division factor for PLLI2SM output by 22 /
NYX	0:85b3fd62ea1a	1066	#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /!< PLLI2S division factor for PLLI2SM output by 23 /
NYX	0:85b3fd62ea1a	1067	#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /!< PLLI2S division factor for PLLI2SM output by 24 /
NYX	0:85b3fd62ea1a	1068	#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /!< PLLI2S division factor for PLLI2SM output by 25 /
NYX	0:85b3fd62ea1a	1069	#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /!< PLLI2S division factor for PLLI2SM output by 26 /
NYX	0:85b3fd62ea1a	1070	#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /!< PLLI2S division factor for PLLI2SM output by 27 /
NYX	0:85b3fd62ea1a	1071	#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /!< PLLI2S division factor for PLLI2SM output by 28 /
NYX	0:85b3fd62ea1a	1072	#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /!< PLLI2S division factor for PLLI2SM output by 29 /
NYX	0:85b3fd62ea1a	1073	#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /!< PLLI2S division factor for PLLI2SM output by 30 /
NYX	0:85b3fd62ea1a	1074	#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /!< PLLI2S division factor for PLLI2SM output by 31 /
NYX	0:85b3fd62ea1a	1075	#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /!< PLLI2S division factor for PLLI2SM output by 32 /
NYX	0:85b3fd62ea1a	1076	#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /!< PLLI2S division factor for PLLI2SM output by 33 /
NYX	0:85b3fd62ea1a	1077	#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /!< PLLI2S division factor for PLLI2SM output by 34 /
NYX	0:85b3fd62ea1a	1078	#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /!< PLLI2S division factor for PLLI2SM output by 35 /
NYX	0:85b3fd62ea1a	1079	#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /!< PLLI2S division factor for PLLI2SM output by 36 /
NYX	0:85b3fd62ea1a	1080	#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /!< PLLI2S division factor for PLLI2SM output by 37 /
NYX	0:85b3fd62ea1a	1081	#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /!< PLLI2S division factor for PLLI2SM output by 38 /
NYX	0:85b3fd62ea1a	1082	#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /!< PLLI2S division factor for PLLI2SM output by 39 /
NYX	0:85b3fd62ea1a	1083	#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /!< PLLI2S division factor for PLLI2SM output by 40 /
NYX	0:85b3fd62ea1a	1084	#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /!< PLLI2S division factor for PLLI2SM output by 41 /
NYX	0:85b3fd62ea1a	1085	#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /!< PLLI2S division factor for PLLI2SM output by 42 /
NYX	0:85b3fd62ea1a	1086	#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /!< PLLI2S division factor for PLLI2SM output by 43 /
NYX	0:85b3fd62ea1a	1087	#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /!< PLLI2S division factor for PLLI2SM output by 44 /
NYX	0:85b3fd62ea1a	1088	#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /!< PLLI2S division factor for PLLI2SM output by 45 /
NYX	0:85b3fd62ea1a	1089	#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /!< PLLI2S division factor for PLLI2SM output by 46 /
NYX	0:85b3fd62ea1a	1090	#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /!< PLLI2S division factor for PLLI2SM output by 47 /
NYX	0:85b3fd62ea1a	1091	#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /!< PLLI2S division factor for PLLI2SM output by 48 /
NYX	0:85b3fd62ea1a	1092	#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /!< PLLI2S division factor for PLLI2SM output by 49 /
NYX	0:85b3fd62ea1a	1093	#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /!< PLLI2S division factor for PLLI2SM output by 50 /
NYX	0:85b3fd62ea1a	1094	#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /!< PLLI2S division factor for PLLI2SM output by 51 /
NYX	0:85b3fd62ea1a	1095	#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /!< PLLI2S division factor for PLLI2SM output by 52 /
NYX	0:85b3fd62ea1a	1096	#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /!< PLLI2S division factor for PLLI2SM output by 53 /
NYX	0:85b3fd62ea1a	1097	#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /!< PLLI2S division factor for PLLI2SM output by 54 /
NYX	0:85b3fd62ea1a	1098	#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /!< PLLI2S division factor for PLLI2SM output by 55 /
NYX	0:85b3fd62ea1a	1099	#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /!< PLLI2S division factor for PLLI2SM output by 56 /
NYX	0:85b3fd62ea1a	1100	#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /!< PLLI2S division factor for PLLI2SM output by 57 /
NYX	0:85b3fd62ea1a	1101	#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /!< PLLI2S division factor for PLLI2SM output by 58 /
NYX	0:85b3fd62ea1a	1102	#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /!< PLLI2S division factor for PLLI2SM output by 59 /
NYX	0:85b3fd62ea1a	1103	#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /!< PLLI2S division factor for PLLI2SM output by 60 /
NYX	0:85b3fd62ea1a	1104	#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /!< PLLI2S division factor for PLLI2SM output by 61 /
NYX	0:85b3fd62ea1a	1105	#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /!< PLLI2S division factor for PLLI2SM output by 62 /
NYX	0:85b3fd62ea1a	1106	#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /!< PLLI2S division factor for PLLI2SM output by 63 /
NYX	0:85b3fd62ea1a	1107	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
NYX	0:85b3fd62ea1a	1108	/**
NYX	0:85b3fd62ea1a	1109	* @}
NYX	0:85b3fd62ea1a	1110	*/
NYX	0:85b3fd62ea1a	1111
NYX	0:85b3fd62ea1a	1112	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
NYX	0:85b3fd62ea1a	1113	/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
NYX	0:85b3fd62ea1a	1114	* @{
NYX	0:85b3fd62ea1a	1115	*/
NYX	0:85b3fd62ea1a	1116	#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /!< PLLI2S division factor for PLLI2SQ output by 2 /
NYX	0:85b3fd62ea1a	1117	#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 3 /
NYX	0:85b3fd62ea1a	1118	#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /!< PLLI2S division factor for PLLI2SQ output by 4 /
NYX	0:85b3fd62ea1a	1119	#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 5 /
NYX	0:85b3fd62ea1a	1120	#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 6 /
NYX	0:85b3fd62ea1a	1121	#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 7 /
NYX	0:85b3fd62ea1a	1122	#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /!< PLLI2S division factor for PLLI2SQ output by 8 /
NYX	0:85b3fd62ea1a	1123	#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 9 /
NYX	0:85b3fd62ea1a	1124	#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 10 /
NYX	0:85b3fd62ea1a	1125	#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 11 /
NYX	0:85b3fd62ea1a	1126	#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2) /!< PLLI2S division factor for PLLI2SQ output by 12 /
NYX	0:85b3fd62ea1a	1127	#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 13 /
NYX	0:85b3fd62ea1a	1128	#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 14 /
NYX	0:85b3fd62ea1a	1129	#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 15 /
NYX	0:85b3fd62ea1a	1130	/**
NYX	0:85b3fd62ea1a	1131	* @}
NYX	0:85b3fd62ea1a	1132	*/
NYX	0:85b3fd62ea1a	1133	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
NYX	0:85b3fd62ea1a	1134
NYX	0:85b3fd62ea1a	1135	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	1136	/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	1137	* @{
NYX	0:85b3fd62ea1a	1138	*/
NYX	0:85b3fd62ea1a	1139	#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /!< PLLI2S division factor for PLLI2SDIVQ output by 1 /
NYX	0:85b3fd62ea1a	1140	#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /!< PLLI2S division factor for PLLI2SDIVQ output by 2 /
NYX	0:85b3fd62ea1a	1141	#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /!< PLLI2S division factor for PLLI2SDIVQ output by 3 /
NYX	0:85b3fd62ea1a	1142	#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 4 /
NYX	0:85b3fd62ea1a	1143	#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /!< PLLI2S division factor for PLLI2SDIVQ output by 5 /
NYX	0:85b3fd62ea1a	1144	#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 6 /
NYX	0:85b3fd62ea1a	1145	#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 7 /
NYX	0:85b3fd62ea1a	1146	#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 8 /
NYX	0:85b3fd62ea1a	1147	#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /!< PLLI2S division factor for PLLI2SDIVQ output by 9 /
NYX	0:85b3fd62ea1a	1148	#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 10 /
NYX	0:85b3fd62ea1a	1149	#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 11 /
NYX	0:85b3fd62ea1a	1150	#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 12 /
NYX	0:85b3fd62ea1a	1151	#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 13 /
NYX	0:85b3fd62ea1a	1152	#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 14 /
NYX	0:85b3fd62ea1a	1153	#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 15 /
NYX	0:85b3fd62ea1a	1154	#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 16 /
NYX	0:85b3fd62ea1a	1155	#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /!< PLLI2S division factor for PLLI2SDIVQ output by 17 /
NYX	0:85b3fd62ea1a	1156	#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 18 /
NYX	0:85b3fd62ea1a	1157	#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 19 /
NYX	0:85b3fd62ea1a	1158	#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 20 /
NYX	0:85b3fd62ea1a	1159	#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 21 /
NYX	0:85b3fd62ea1a	1160	#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 22 /
NYX	0:85b3fd62ea1a	1161	#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 23 /
NYX	0:85b3fd62ea1a	1162	#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 24 /
NYX	0:85b3fd62ea1a	1163	#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3) /!< PLLI2S division factor for PLLI2SDIVQ output by 25 /
NYX	0:85b3fd62ea1a	1164	#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 26 /
NYX	0:85b3fd62ea1a	1165	#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 27 /
NYX	0:85b3fd62ea1a	1166	#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 28 /
NYX	0:85b3fd62ea1a	1167	#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 29 /
NYX	0:85b3fd62ea1a	1168	#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 30 /
NYX	0:85b3fd62ea1a	1169	#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 31 /
NYX	0:85b3fd62ea1a	1170	#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 \| RCC_DCKCFGR_PLLI2SDIVQ_3 \| RCC_DCKCFGR_PLLI2SDIVQ_2 \| RCC_DCKCFGR_PLLI2SDIVQ_1 \| RCC_DCKCFGR_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 32 /
NYX	0:85b3fd62ea1a	1171	/**
NYX	0:85b3fd62ea1a	1172	* @}
NYX	0:85b3fd62ea1a	1173	*/
NYX	0:85b3fd62ea1a	1174	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	1175
NYX	0:85b3fd62ea1a	1176	#if defined(RCC_DCKCFGR_PLLI2SDIVR)
NYX	0:85b3fd62ea1a	1177	/** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
NYX	0:85b3fd62ea1a	1178	* @{
NYX	0:85b3fd62ea1a	1179	*/
NYX	0:85b3fd62ea1a	1180	#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 1 /
NYX	0:85b3fd62ea1a	1181	#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 2 /
NYX	0:85b3fd62ea1a	1182	#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 3 /
NYX	0:85b3fd62ea1a	1183	#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 4 /
NYX	0:85b3fd62ea1a	1184	#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 5 /
NYX	0:85b3fd62ea1a	1185	#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 6 /
NYX	0:85b3fd62ea1a	1186	#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 7 /
NYX	0:85b3fd62ea1a	1187	#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /!< PLLI2S division factor for PLLI2SDIVR output by 8 /
NYX	0:85b3fd62ea1a	1188	#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 9 /
NYX	0:85b3fd62ea1a	1189	#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 10 /
NYX	0:85b3fd62ea1a	1190	#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 11 /
NYX	0:85b3fd62ea1a	1191	#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 12 /
NYX	0:85b3fd62ea1a	1192	#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 13 /
NYX	0:85b3fd62ea1a	1193	#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 14 /
NYX	0:85b3fd62ea1a	1194	#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 15 /
NYX	0:85b3fd62ea1a	1195	#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /!< PLLI2S division factor for PLLI2SDIVR output by 16 /
NYX	0:85b3fd62ea1a	1196	#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 17 /
NYX	0:85b3fd62ea1a	1197	#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 18 /
NYX	0:85b3fd62ea1a	1198	#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 19 /
NYX	0:85b3fd62ea1a	1199	#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 20 /
NYX	0:85b3fd62ea1a	1200	#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 21 /
NYX	0:85b3fd62ea1a	1201	#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 22 /
NYX	0:85b3fd62ea1a	1202	#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 23 /
NYX	0:85b3fd62ea1a	1203	#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3) /!< PLLI2S division factor for PLLI2SDIVR output by 24 /
NYX	0:85b3fd62ea1a	1204	#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 25 /
NYX	0:85b3fd62ea1a	1205	#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 26 /
NYX	0:85b3fd62ea1a	1206	#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 27 /
NYX	0:85b3fd62ea1a	1207	#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2) /!< PLLI2S division factor for PLLI2SDIVR output by 28 /
NYX	0:85b3fd62ea1a	1208	#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 29 /
NYX	0:85b3fd62ea1a	1209	#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1) /!< PLLI2S division factor for PLLI2SDIVR output by 30 /
NYX	0:85b3fd62ea1a	1210	#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 \| RCC_DCKCFGR_PLLI2SDIVR_3 \| RCC_DCKCFGR_PLLI2SDIVR_2 \| RCC_DCKCFGR_PLLI2SDIVR_1 \| RCC_DCKCFGR_PLLI2SDIVR_0) /!< PLLI2S division factor for PLLI2SDIVR output by 31 /
NYX	0:85b3fd62ea1a	1211	/**
NYX	0:85b3fd62ea1a	1212	* @}
NYX	0:85b3fd62ea1a	1213	*/
NYX	0:85b3fd62ea1a	1214	#endif /* RCC_DCKCFGR_PLLI2SDIVR */
NYX	0:85b3fd62ea1a	1215
NYX	0:85b3fd62ea1a	1216	/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
NYX	0:85b3fd62ea1a	1217	* @{
NYX	0:85b3fd62ea1a	1218	*/
NYX	0:85b3fd62ea1a	1219	#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /!< PLLI2S division factor for PLLI2SR output by 2 /
NYX	0:85b3fd62ea1a	1220	#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 3 /
NYX	0:85b3fd62ea1a	1221	#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /!< PLLI2S division factor for PLLI2SR output by 4 /
NYX	0:85b3fd62ea1a	1222	#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 5 /
NYX	0:85b3fd62ea1a	1223	#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1) /!< PLLI2S division factor for PLLI2SR output by 6 /
NYX	0:85b3fd62ea1a	1224	#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 7 /
NYX	0:85b3fd62ea1a	1225	/**
NYX	0:85b3fd62ea1a	1226	* @}
NYX	0:85b3fd62ea1a	1227	*/
NYX	0:85b3fd62ea1a	1228
NYX	0:85b3fd62ea1a	1229	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
NYX	0:85b3fd62ea1a	1230	/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
NYX	0:85b3fd62ea1a	1231	* @{
NYX	0:85b3fd62ea1a	1232	*/
NYX	0:85b3fd62ea1a	1233	#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /!< PLLI2S division factor for PLLI2SP output by 2 /
NYX	0:85b3fd62ea1a	1234	#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /!< PLLI2S division factor for PLLI2SP output by 4 /
NYX	0:85b3fd62ea1a	1235	#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /!< PLLI2S division factor for PLLI2SP output by 6 /
NYX	0:85b3fd62ea1a	1236	#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 \| RCC_PLLI2SCFGR_PLLI2SP_0) /!< PLLI2S division factor for PLLI2SP output by 8 /
NYX	0:85b3fd62ea1a	1237	/**
NYX	0:85b3fd62ea1a	1238	* @}
NYX	0:85b3fd62ea1a	1239	*/
NYX	0:85b3fd62ea1a	1240	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
NYX	0:85b3fd62ea1a	1241	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	1242
NYX	0:85b3fd62ea1a	1243	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	1244	/** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
NYX	0:85b3fd62ea1a	1245	* @{
NYX	0:85b3fd62ea1a	1246	*/
NYX	0:85b3fd62ea1a	1247	#if defined(RCC_PLLSAICFGR_PLLSAIM)
NYX	0:85b3fd62ea1a	1248	#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 2 /
NYX	0:85b3fd62ea1a	1249	#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 3 /
NYX	0:85b3fd62ea1a	1250	#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 4 /
NYX	0:85b3fd62ea1a	1251	#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 5 /
NYX	0:85b3fd62ea1a	1252	#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 6 /
NYX	0:85b3fd62ea1a	1253	#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 7 /
NYX	0:85b3fd62ea1a	1254	#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 8 /
NYX	0:85b3fd62ea1a	1255	#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 9 /
NYX	0:85b3fd62ea1a	1256	#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 10 /
NYX	0:85b3fd62ea1a	1257	#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 11 /
NYX	0:85b3fd62ea1a	1258	#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 12 /
NYX	0:85b3fd62ea1a	1259	#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 13 /
NYX	0:85b3fd62ea1a	1260	#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 14 /
NYX	0:85b3fd62ea1a	1261	#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 15 /
NYX	0:85b3fd62ea1a	1262	#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /!< PLLSAI division factor for PLLSAIM output by 16 /
NYX	0:85b3fd62ea1a	1263	#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 17 /
NYX	0:85b3fd62ea1a	1264	#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 18 /
NYX	0:85b3fd62ea1a	1265	#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 19 /
NYX	0:85b3fd62ea1a	1266	#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 20 /
NYX	0:85b3fd62ea1a	1267	#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 21 /
NYX	0:85b3fd62ea1a	1268	#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 22 /
NYX	0:85b3fd62ea1a	1269	#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 23 /
NYX	0:85b3fd62ea1a	1270	#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 24 /
NYX	0:85b3fd62ea1a	1271	#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 25 /
NYX	0:85b3fd62ea1a	1272	#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 26 /
NYX	0:85b3fd62ea1a	1273	#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 27 /
NYX	0:85b3fd62ea1a	1274	#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 28 /
NYX	0:85b3fd62ea1a	1275	#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 29 /
NYX	0:85b3fd62ea1a	1276	#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 30 /
NYX	0:85b3fd62ea1a	1277	#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 31 /
NYX	0:85b3fd62ea1a	1278	#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /!< PLLSAI division factor for PLLSAIM output by 32 /
NYX	0:85b3fd62ea1a	1279	#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 33 /
NYX	0:85b3fd62ea1a	1280	#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 34 /
NYX	0:85b3fd62ea1a	1281	#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 35 /
NYX	0:85b3fd62ea1a	1282	#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 36 /
NYX	0:85b3fd62ea1a	1283	#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 37 /
NYX	0:85b3fd62ea1a	1284	#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 38 /
NYX	0:85b3fd62ea1a	1285	#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 39 /
NYX	0:85b3fd62ea1a	1286	#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 40 /
NYX	0:85b3fd62ea1a	1287	#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 41 /
NYX	0:85b3fd62ea1a	1288	#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 42 /
NYX	0:85b3fd62ea1a	1289	#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 43 /
NYX	0:85b3fd62ea1a	1290	#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 44 /
NYX	0:85b3fd62ea1a	1291	#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 45 /
NYX	0:85b3fd62ea1a	1292	#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 46 /
NYX	0:85b3fd62ea1a	1293	#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 47 /
NYX	0:85b3fd62ea1a	1294	#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4) /!< PLLSAI division factor for PLLSAIM output by 48 /
NYX	0:85b3fd62ea1a	1295	#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 49 /
NYX	0:85b3fd62ea1a	1296	#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 50 /
NYX	0:85b3fd62ea1a	1297	#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 51 /
NYX	0:85b3fd62ea1a	1298	#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 52 /
NYX	0:85b3fd62ea1a	1299	#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 53 /
NYX	0:85b3fd62ea1a	1300	#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 54 /
NYX	0:85b3fd62ea1a	1301	#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 55 /
NYX	0:85b3fd62ea1a	1302	#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3) /!< PLLSAI division factor for PLLSAIM output by 56 /
NYX	0:85b3fd62ea1a	1303	#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 57 /
NYX	0:85b3fd62ea1a	1304	#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 58 /
NYX	0:85b3fd62ea1a	1305	#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 59 /
NYX	0:85b3fd62ea1a	1306	#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2) /!< PLLSAI division factor for PLLSAIM output by 60 /
NYX	0:85b3fd62ea1a	1307	#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 61 /
NYX	0:85b3fd62ea1a	1308	#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1) /!< PLLSAI division factor for PLLSAIM output by 62 /
NYX	0:85b3fd62ea1a	1309	#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 \| RCC_PLLSAICFGR_PLLSAIM_4 \| RCC_PLLSAICFGR_PLLSAIM_3 \| RCC_PLLSAICFGR_PLLSAIM_2 \| RCC_PLLSAICFGR_PLLSAIM_1 \| RCC_PLLSAICFGR_PLLSAIM_0) /!< PLLSAI division factor for PLLSAIM output by 63 /
NYX	0:85b3fd62ea1a	1310	#else
NYX	0:85b3fd62ea1a	1311	#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /!< PLLSAI division factor for PLLSAIM output by 2 /
NYX	0:85b3fd62ea1a	1312	#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /!< PLLSAI division factor for PLLSAIM output by 3 /
NYX	0:85b3fd62ea1a	1313	#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /!< PLLSAI division factor for PLLSAIM output by 4 /
NYX	0:85b3fd62ea1a	1314	#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /!< PLLSAI division factor for PLLSAIM output by 5 /
NYX	0:85b3fd62ea1a	1315	#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /!< PLLSAI division factor for PLLSAIM output by 6 /
NYX	0:85b3fd62ea1a	1316	#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /!< PLLSAI division factor for PLLSAIM output by 7 /
NYX	0:85b3fd62ea1a	1317	#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /!< PLLSAI division factor for PLLSAIM output by 8 /
NYX	0:85b3fd62ea1a	1318	#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /!< PLLSAI division factor for PLLSAIM output by 9 /
NYX	0:85b3fd62ea1a	1319	#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /!< PLLSAI division factor for PLLSAIM output by 10 /
NYX	0:85b3fd62ea1a	1320	#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /!< PLLSAI division factor for PLLSAIM output by 11 /
NYX	0:85b3fd62ea1a	1321	#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /!< PLLSAI division factor for PLLSAIM output by 12 /
NYX	0:85b3fd62ea1a	1322	#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /!< PLLSAI division factor for PLLSAIM output by 13 /
NYX	0:85b3fd62ea1a	1323	#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /!< PLLSAI division factor for PLLSAIM output by 14 /
NYX	0:85b3fd62ea1a	1324	#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /!< PLLSAI division factor for PLLSAIM output by 15 /
NYX	0:85b3fd62ea1a	1325	#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /!< PLLSAI division factor for PLLSAIM output by 16 /
NYX	0:85b3fd62ea1a	1326	#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /!< PLLSAI division factor for PLLSAIM output by 17 /
NYX	0:85b3fd62ea1a	1327	#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /!< PLLSAI division factor for PLLSAIM output by 18 /
NYX	0:85b3fd62ea1a	1328	#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /!< PLLSAI division factor for PLLSAIM output by 19 /
NYX	0:85b3fd62ea1a	1329	#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /!< PLLSAI division factor for PLLSAIM output by 20 /
NYX	0:85b3fd62ea1a	1330	#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /!< PLLSAI division factor for PLLSAIM output by 21 /
NYX	0:85b3fd62ea1a	1331	#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /!< PLLSAI division factor for PLLSAIM output by 22 /
NYX	0:85b3fd62ea1a	1332	#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /!< PLLSAI division factor for PLLSAIM output by 23 /
NYX	0:85b3fd62ea1a	1333	#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /!< PLLSAI division factor for PLLSAIM output by 24 /
NYX	0:85b3fd62ea1a	1334	#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /!< PLLSAI division factor for PLLSAIM output by 25 /
NYX	0:85b3fd62ea1a	1335	#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /!< PLLSAI division factor for PLLSAIM output by 26 /
NYX	0:85b3fd62ea1a	1336	#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /!< PLLSAI division factor for PLLSAIM output by 27 /
NYX	0:85b3fd62ea1a	1337	#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /!< PLLSAI division factor for PLLSAIM output by 28 /
NYX	0:85b3fd62ea1a	1338	#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /!< PLLSAI division factor for PLLSAIM output by 29 /
NYX	0:85b3fd62ea1a	1339	#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /!< PLLSAI division factor for PLLSAIM output by 30 /
NYX	0:85b3fd62ea1a	1340	#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /!< PLLSAI division factor for PLLSAIM output by 31 /
NYX	0:85b3fd62ea1a	1341	#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /!< PLLSAI division factor for PLLSAIM output by 32 /
NYX	0:85b3fd62ea1a	1342	#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /!< PLLSAI division factor for PLLSAIM output by 33 /
NYX	0:85b3fd62ea1a	1343	#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /!< PLLSAI division factor for PLLSAIM output by 34 /
NYX	0:85b3fd62ea1a	1344	#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /!< PLLSAI division factor for PLLSAIM output by 35 /
NYX	0:85b3fd62ea1a	1345	#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /!< PLLSAI division factor for PLLSAIM output by 36 /
NYX	0:85b3fd62ea1a	1346	#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /!< PLLSAI division factor for PLLSAIM output by 37 /
NYX	0:85b3fd62ea1a	1347	#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /!< PLLSAI division factor for PLLSAIM output by 38 /
NYX	0:85b3fd62ea1a	1348	#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /!< PLLSAI division factor for PLLSAIM output by 39 /
NYX	0:85b3fd62ea1a	1349	#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /!< PLLSAI division factor for PLLSAIM output by 40 /
NYX	0:85b3fd62ea1a	1350	#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /!< PLLSAI division factor for PLLSAIM output by 41 /
NYX	0:85b3fd62ea1a	1351	#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /!< PLLSAI division factor for PLLSAIM output by 42 /
NYX	0:85b3fd62ea1a	1352	#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /!< PLLSAI division factor for PLLSAIM output by 43 /
NYX	0:85b3fd62ea1a	1353	#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /!< PLLSAI division factor for PLLSAIM output by 44 /
NYX	0:85b3fd62ea1a	1354	#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /!< PLLSAI division factor for PLLSAIM output by 45 /
NYX	0:85b3fd62ea1a	1355	#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /!< PLLSAI division factor for PLLSAIM output by 46 /
NYX	0:85b3fd62ea1a	1356	#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /!< PLLSAI division factor for PLLSAIM output by 47 /
NYX	0:85b3fd62ea1a	1357	#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /!< PLLSAI division factor for PLLSAIM output by 48 /
NYX	0:85b3fd62ea1a	1358	#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /!< PLLSAI division factor for PLLSAIM output by 49 /
NYX	0:85b3fd62ea1a	1359	#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /!< PLLSAI division factor for PLLSAIM output by 50 /
NYX	0:85b3fd62ea1a	1360	#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /!< PLLSAI division factor for PLLSAIM output by 51 /
NYX	0:85b3fd62ea1a	1361	#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /!< PLLSAI division factor for PLLSAIM output by 52 /
NYX	0:85b3fd62ea1a	1362	#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /!< PLLSAI division factor for PLLSAIM output by 53 /
NYX	0:85b3fd62ea1a	1363	#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /!< PLLSAI division factor for PLLSAIM output by 54 /
NYX	0:85b3fd62ea1a	1364	#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /!< PLLSAI division factor for PLLSAIM output by 55 /
NYX	0:85b3fd62ea1a	1365	#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /!< PLLSAI division factor for PLLSAIM output by 56 /
NYX	0:85b3fd62ea1a	1366	#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /!< PLLSAI division factor for PLLSAIM output by 57 /
NYX	0:85b3fd62ea1a	1367	#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /!< PLLSAI division factor for PLLSAIM output by 58 /
NYX	0:85b3fd62ea1a	1368	#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /!< PLLSAI division factor for PLLSAIM output by 59 /
NYX	0:85b3fd62ea1a	1369	#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /!< PLLSAI division factor for PLLSAIM output by 60 /
NYX	0:85b3fd62ea1a	1370	#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /!< PLLSAI division factor for PLLSAIM output by 61 /
NYX	0:85b3fd62ea1a	1371	#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /!< PLLSAI division factor for PLLSAIM output by 62 /
NYX	0:85b3fd62ea1a	1372	#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /!< PLLSAI division factor for PLLSAIM output by 63 /
NYX	0:85b3fd62ea1a	1373	#endif /* RCC_PLLSAICFGR_PLLSAIM */
NYX	0:85b3fd62ea1a	1374	/**
NYX	0:85b3fd62ea1a	1375	* @}
NYX	0:85b3fd62ea1a	1376	*/
NYX	0:85b3fd62ea1a	1377
NYX	0:85b3fd62ea1a	1378	/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
NYX	0:85b3fd62ea1a	1379	* @{
NYX	0:85b3fd62ea1a	1380	*/
NYX	0:85b3fd62ea1a	1381	#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /!< PLLSAI division factor for PLLSAIQ output by 2 /
NYX	0:85b3fd62ea1a	1382	#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 3 /
NYX	0:85b3fd62ea1a	1383	#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /!< PLLSAI division factor for PLLSAIQ output by 4 /
NYX	0:85b3fd62ea1a	1384	#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 5 /
NYX	0:85b3fd62ea1a	1385	#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 6 /
NYX	0:85b3fd62ea1a	1386	#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 7 /
NYX	0:85b3fd62ea1a	1387	#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /!< PLLSAI division factor for PLLSAIQ output by 8 /
NYX	0:85b3fd62ea1a	1388	#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 9 /
NYX	0:85b3fd62ea1a	1389	#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 10 /
NYX	0:85b3fd62ea1a	1390	#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 11 /
NYX	0:85b3fd62ea1a	1391	#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2) /!< PLLSAI division factor for PLLSAIQ output by 12 /
NYX	0:85b3fd62ea1a	1392	#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 13 /
NYX	0:85b3fd62ea1a	1393	#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 14 /
NYX	0:85b3fd62ea1a	1394	#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 15 /
NYX	0:85b3fd62ea1a	1395	/**
NYX	0:85b3fd62ea1a	1396	* @}
NYX	0:85b3fd62ea1a	1397	*/
NYX	0:85b3fd62ea1a	1398
NYX	0:85b3fd62ea1a	1399	#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
NYX	0:85b3fd62ea1a	1400	/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
NYX	0:85b3fd62ea1a	1401	* @{
NYX	0:85b3fd62ea1a	1402	*/
NYX	0:85b3fd62ea1a	1403	#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /!< PLLSAI division factor for PLLSAIDIVQ output by 1 /
NYX	0:85b3fd62ea1a	1404	#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /!< PLLSAI division factor for PLLSAIDIVQ output by 2 /
NYX	0:85b3fd62ea1a	1405	#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /!< PLLSAI division factor for PLLSAIDIVQ output by 3 /
NYX	0:85b3fd62ea1a	1406	#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 4 /
NYX	0:85b3fd62ea1a	1407	#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /!< PLLSAI division factor for PLLSAIDIVQ output by 5 /
NYX	0:85b3fd62ea1a	1408	#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 6 /
NYX	0:85b3fd62ea1a	1409	#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 7 /
NYX	0:85b3fd62ea1a	1410	#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 8 /
NYX	0:85b3fd62ea1a	1411	#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /!< PLLSAI division factor for PLLSAIDIVQ output by 9 /
NYX	0:85b3fd62ea1a	1412	#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 10 /
NYX	0:85b3fd62ea1a	1413	#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 11 /
NYX	0:85b3fd62ea1a	1414	#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 12 /
NYX	0:85b3fd62ea1a	1415	#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 13 /
NYX	0:85b3fd62ea1a	1416	#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 14 /
NYX	0:85b3fd62ea1a	1417	#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 15 /
NYX	0:85b3fd62ea1a	1418	#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 16 /
NYX	0:85b3fd62ea1a	1419	#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /!< PLLSAI division factor for PLLSAIDIVQ output by 17 /
NYX	0:85b3fd62ea1a	1420	#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 18 /
NYX	0:85b3fd62ea1a	1421	#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 19 /
NYX	0:85b3fd62ea1a	1422	#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 20 /
NYX	0:85b3fd62ea1a	1423	#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 21 /
NYX	0:85b3fd62ea1a	1424	#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 22 /
NYX	0:85b3fd62ea1a	1425	#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 23 /
NYX	0:85b3fd62ea1a	1426	#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 24 /
NYX	0:85b3fd62ea1a	1427	#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3) /!< PLLSAI division factor for PLLSAIDIVQ output by 25 /
NYX	0:85b3fd62ea1a	1428	#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 26 /
NYX	0:85b3fd62ea1a	1429	#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 27 /
NYX	0:85b3fd62ea1a	1430	#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 28 /
NYX	0:85b3fd62ea1a	1431	#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 29 /
NYX	0:85b3fd62ea1a	1432	#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 30 /
NYX	0:85b3fd62ea1a	1433	#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 31 /
NYX	0:85b3fd62ea1a	1434	#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 \| RCC_DCKCFGR_PLLSAIDIVQ_3 \| RCC_DCKCFGR_PLLSAIDIVQ_2 \| RCC_DCKCFGR_PLLSAIDIVQ_1 \| RCC_DCKCFGR_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 32 /
NYX	0:85b3fd62ea1a	1435	/**
NYX	0:85b3fd62ea1a	1436	* @}
NYX	0:85b3fd62ea1a	1437	*/
NYX	0:85b3fd62ea1a	1438	#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
NYX	0:85b3fd62ea1a	1439
NYX	0:85b3fd62ea1a	1440	#if defined(RCC_PLLSAICFGR_PLLSAIR)
NYX	0:85b3fd62ea1a	1441	/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
NYX	0:85b3fd62ea1a	1442	* @{
NYX	0:85b3fd62ea1a	1443	*/
NYX	0:85b3fd62ea1a	1444	#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /!< PLLSAI division factor for PLLSAIR output by 2 /
NYX	0:85b3fd62ea1a	1445	#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 3 /
NYX	0:85b3fd62ea1a	1446	#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /!< PLLSAI division factor for PLLSAIR output by 4 /
NYX	0:85b3fd62ea1a	1447	#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 5 /
NYX	0:85b3fd62ea1a	1448	#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1) /!< PLLSAI division factor for PLLSAIR output by 6 /
NYX	0:85b3fd62ea1a	1449	#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 7 /
NYX	0:85b3fd62ea1a	1450	/**
NYX	0:85b3fd62ea1a	1451	* @}
NYX	0:85b3fd62ea1a	1452	*/
NYX	0:85b3fd62ea1a	1453	#endif /* RCC_PLLSAICFGR_PLLSAIR */
NYX	0:85b3fd62ea1a	1454
NYX	0:85b3fd62ea1a	1455	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
NYX	0:85b3fd62ea1a	1456	/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
NYX	0:85b3fd62ea1a	1457	* @{
NYX	0:85b3fd62ea1a	1458	*/
NYX	0:85b3fd62ea1a	1459	#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIDIVR output by 2 /
NYX	0:85b3fd62ea1a	1460	#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /!< PLLSAI division factor for PLLSAIDIVR output by 4 /
NYX	0:85b3fd62ea1a	1461	#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /!< PLLSAI division factor for PLLSAIDIVR output by 8 /
NYX	0:85b3fd62ea1a	1462	#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 \| RCC_DCKCFGR_PLLSAIDIVR_0) /!< PLLSAI division factor for PLLSAIDIVR output by 16 /
NYX	0:85b3fd62ea1a	1463	/**
NYX	0:85b3fd62ea1a	1464	* @}
NYX	0:85b3fd62ea1a	1465	*/
NYX	0:85b3fd62ea1a	1466	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
NYX	0:85b3fd62ea1a	1467
NYX	0:85b3fd62ea1a	1468	#if defined(RCC_PLLSAICFGR_PLLSAIP)
NYX	0:85b3fd62ea1a	1469	/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
NYX	0:85b3fd62ea1a	1470	* @{
NYX	0:85b3fd62ea1a	1471	*/
NYX	0:85b3fd62ea1a	1472	#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIP output by 2 /
NYX	0:85b3fd62ea1a	1473	#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /!< PLLSAI division factor for PLLSAIP output by 4 /
NYX	0:85b3fd62ea1a	1474	#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /!< PLLSAI division factor for PLLSAIP output by 6 /
NYX	0:85b3fd62ea1a	1475	#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 \| RCC_PLLSAICFGR_PLLSAIP_0) /!< PLLSAI division factor for PLLSAIP output by 8 /
NYX	0:85b3fd62ea1a	1476	/**
NYX	0:85b3fd62ea1a	1477	* @}
NYX	0:85b3fd62ea1a	1478	*/
NYX	0:85b3fd62ea1a	1479	#endif /* RCC_PLLSAICFGR_PLLSAIP */
NYX	0:85b3fd62ea1a	1480	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	1481	/**
NYX	0:85b3fd62ea1a	1482	* @}
NYX	0:85b3fd62ea1a	1483	*/
NYX	0:85b3fd62ea1a	1484
NYX	0:85b3fd62ea1a	1485	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1486	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
NYX	0:85b3fd62ea1a	1487	* @{
NYX	0:85b3fd62ea1a	1488	*/
NYX	0:85b3fd62ea1a	1489
NYX	0:85b3fd62ea1a	1490	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
NYX	0:85b3fd62ea1a	1491	* @{
NYX	0:85b3fd62ea1a	1492	*/
NYX	0:85b3fd62ea1a	1493
NYX	0:85b3fd62ea1a	1494	/**
NYX	0:85b3fd62ea1a	1495	* @brief Write a value in RCC register
NYX	0:85b3fd62ea1a	1496	* @param __REG__ Register to be written
NYX	0:85b3fd62ea1a	1497	* @param __VALUE__ Value to be written in the register
NYX	0:85b3fd62ea1a	1498	* @retval None
NYX	0:85b3fd62ea1a	1499	*/
NYX	0:85b3fd62ea1a	1500	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
NYX	0:85b3fd62ea1a	1501
NYX	0:85b3fd62ea1a	1502	/**
NYX	0:85b3fd62ea1a	1503	* @brief Read a value in RCC register
NYX	0:85b3fd62ea1a	1504	* @param __REG__ Register to be read
NYX	0:85b3fd62ea1a	1505	* @retval Register value
NYX	0:85b3fd62ea1a	1506	*/
NYX	0:85b3fd62ea1a	1507	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
NYX	0:85b3fd62ea1a	1508	/**
NYX	0:85b3fd62ea1a	1509	* @}
NYX	0:85b3fd62ea1a	1510	*/
NYX	0:85b3fd62ea1a	1511
NYX	0:85b3fd62ea1a	1512	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
NYX	0:85b3fd62ea1a	1513	* @{
NYX	0:85b3fd62ea1a	1514	*/
NYX	0:85b3fd62ea1a	1515
NYX	0:85b3fd62ea1a	1516	/**
NYX	0:85b3fd62ea1a	1517	* @brief Helper macro to calculate the PLLCLK frequency on system domain
NYX	0:85b3fd62ea1a	1518	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
NYX	0:85b3fd62ea1a	1519	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
NYX	0:85b3fd62ea1a	1520	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	1521	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1522	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	1523	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	1524	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	1525	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	1526	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	1527	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	1528	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	1529	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	1530	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	1531	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	1532	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	1533	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	1534	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	1535	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	1536	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	1537	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	1538	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	1539	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	1540	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	1541	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	1542	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	1543	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	1544	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	1545	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	1546	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	1547	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	1548	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	1549	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	1550	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	1551	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	1552	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	1553	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	1554	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	1555	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	1556	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	1557	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	1558	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	1559	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	1560	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	1561	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	1562	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	1563	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	1564	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	1565	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	1566	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	1567	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	1568	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	1569	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	1570	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	1571	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	1572	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	1573	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	1574	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	1575	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	1576	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	1577	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	1578	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	1579	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	1580	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	1581	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	1582	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	1583	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	1584	* @param __PLLN__ Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	1585	*
NYX	0:85b3fd62ea1a	1586	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	1587	* @param __PLLP__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1588	* @arg @ref LL_RCC_PLLP_DIV_2
NYX	0:85b3fd62ea1a	1589	* @arg @ref LL_RCC_PLLP_DIV_4
NYX	0:85b3fd62ea1a	1590	* @arg @ref LL_RCC_PLLP_DIV_6
NYX	0:85b3fd62ea1a	1591	* @arg @ref LL_RCC_PLLP_DIV_8
NYX	0:85b3fd62ea1a	1592	* @retval PLL clock frequency (in Hz)
NYX	0:85b3fd62ea1a	1593	*/
NYX	0:85b3fd62ea1a	1594	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
NYX	0:85b3fd62ea1a	1595	((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
NYX	0:85b3fd62ea1a	1596
NYX	0:85b3fd62ea1a	1597	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
NYX	0:85b3fd62ea1a	1598	/**
NYX	0:85b3fd62ea1a	1599	* @brief Helper macro to calculate the PLLRCLK frequency on system domain
NYX	0:85b3fd62ea1a	1600	* @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
NYX	0:85b3fd62ea1a	1601	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
NYX	0:85b3fd62ea1a	1602	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	1603	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1604	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	1605	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	1606	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	1607	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	1608	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	1609	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	1610	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	1611	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	1612	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	1613	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	1614	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	1615	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	1616	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	1617	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	1618	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	1619	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	1620	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	1621	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	1622	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	1623	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	1624	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	1625	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	1626	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	1627	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	1628	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	1629	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	1630	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	1631	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	1632	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	1633	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	1634	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	1635	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	1636	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	1637	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	1638	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	1639	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	1640	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	1641	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	1642	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	1643	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	1644	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	1645	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	1646	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	1647	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	1648	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	1649	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	1650	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	1651	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	1652	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	1653	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	1654	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	1655	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	1656	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	1657	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	1658	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	1659	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	1660	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	1661	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	1662	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	1663	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	1664	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	1665	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	1666	* @param __PLLN__ Between 50 and 432
NYX	0:85b3fd62ea1a	1667	* @param __PLLR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1668	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	1669	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	1670	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	1671	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	1672	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	1673	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	1674	* @retval PLL clock frequency (in Hz)
NYX	0:85b3fd62ea1a	1675	*/
NYX	0:85b3fd62ea1a	1676	#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
NYX	0:85b3fd62ea1a	1677	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
NYX	0:85b3fd62ea1a	1678
NYX	0:85b3fd62ea1a	1679	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
NYX	0:85b3fd62ea1a	1680
NYX	0:85b3fd62ea1a	1681	/**
NYX	0:85b3fd62ea1a	1682	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
NYX	0:85b3fd62ea1a	1683	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
NYX	0:85b3fd62ea1a	1684	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
NYX	0:85b3fd62ea1a	1685	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	1686	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1687	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	1688	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	1689	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	1690	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	1691	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	1692	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	1693	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	1694	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	1695	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	1696	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	1697	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	1698	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	1699	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	1700	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	1701	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	1702	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	1703	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	1704	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	1705	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	1706	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	1707	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	1708	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	1709	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	1710	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	1711	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	1712	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	1713	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	1714	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	1715	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	1716	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	1717	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	1718	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	1719	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	1720	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	1721	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	1722	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	1723	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	1724	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	1725	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	1726	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	1727	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	1728	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	1729	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	1730	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	1731	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	1732	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	1733	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	1734	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	1735	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	1736	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	1737	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	1738	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	1739	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	1740	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	1741	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	1742	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	1743	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	1744	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	1745	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	1746	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	1747	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	1748	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	1749	* @param __PLLN__ Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	1750	*
NYX	0:85b3fd62ea1a	1751	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	1752	* @param __PLLQ__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1753	* @arg @ref LL_RCC_PLLQ_DIV_2
NYX	0:85b3fd62ea1a	1754	* @arg @ref LL_RCC_PLLQ_DIV_3
NYX	0:85b3fd62ea1a	1755	* @arg @ref LL_RCC_PLLQ_DIV_4
NYX	0:85b3fd62ea1a	1756	* @arg @ref LL_RCC_PLLQ_DIV_5
NYX	0:85b3fd62ea1a	1757	* @arg @ref LL_RCC_PLLQ_DIV_6
NYX	0:85b3fd62ea1a	1758	* @arg @ref LL_RCC_PLLQ_DIV_7
NYX	0:85b3fd62ea1a	1759	* @arg @ref LL_RCC_PLLQ_DIV_8
NYX	0:85b3fd62ea1a	1760	* @arg @ref LL_RCC_PLLQ_DIV_9
NYX	0:85b3fd62ea1a	1761	* @arg @ref LL_RCC_PLLQ_DIV_10
NYX	0:85b3fd62ea1a	1762	* @arg @ref LL_RCC_PLLQ_DIV_11
NYX	0:85b3fd62ea1a	1763	* @arg @ref LL_RCC_PLLQ_DIV_12
NYX	0:85b3fd62ea1a	1764	* @arg @ref LL_RCC_PLLQ_DIV_13
NYX	0:85b3fd62ea1a	1765	* @arg @ref LL_RCC_PLLQ_DIV_14
NYX	0:85b3fd62ea1a	1766	* @arg @ref LL_RCC_PLLQ_DIV_15
NYX	0:85b3fd62ea1a	1767	* @retval PLL clock frequency (in Hz)
NYX	0:85b3fd62ea1a	1768	*/
NYX	0:85b3fd62ea1a	1769	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
NYX	0:85b3fd62ea1a	1770	((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
NYX	0:85b3fd62ea1a	1771
NYX	0:85b3fd62ea1a	1772	#if defined(DSI)
NYX	0:85b3fd62ea1a	1773	/**
NYX	0:85b3fd62ea1a	1774	* @brief Helper macro to calculate the PLLCLK frequency used on DSI
NYX	0:85b3fd62ea1a	1775	* @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
NYX	0:85b3fd62ea1a	1776	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
NYX	0:85b3fd62ea1a	1777	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	1778	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1779	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	1780	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	1781	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	1782	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	1783	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	1784	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	1785	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	1786	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	1787	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	1788	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	1789	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	1790	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	1791	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	1792	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	1793	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	1794	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	1795	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	1796	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	1797	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	1798	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	1799	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	1800	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	1801	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	1802	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	1803	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	1804	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	1805	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	1806	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	1807	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	1808	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	1809	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	1810	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	1811	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	1812	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	1813	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	1814	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	1815	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	1816	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	1817	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	1818	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	1819	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	1820	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	1821	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	1822	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	1823	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	1824	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	1825	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	1826	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	1827	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	1828	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	1829	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	1830	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	1831	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	1832	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	1833	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	1834	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	1835	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	1836	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	1837	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	1838	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	1839	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	1840	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	1841	* @param __PLLN__ Between 50 and 432
NYX	0:85b3fd62ea1a	1842	* @param __PLLR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1843	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	1844	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	1845	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	1846	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	1847	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	1848	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	1849	* @retval PLL clock frequency (in Hz)
NYX	0:85b3fd62ea1a	1850	*/
NYX	0:85b3fd62ea1a	1851	#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
NYX	0:85b3fd62ea1a	1852	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
NYX	0:85b3fd62ea1a	1853	#endif /* DSI */
NYX	0:85b3fd62ea1a	1854
NYX	0:85b3fd62ea1a	1855	#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
NYX	0:85b3fd62ea1a	1856	/**
NYX	0:85b3fd62ea1a	1857	* @brief Helper macro to calculate the PLLCLK frequency used on I2S
NYX	0:85b3fd62ea1a	1858	* @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
NYX	0:85b3fd62ea1a	1859	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
NYX	0:85b3fd62ea1a	1860	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	1861	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1862	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	1863	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	1864	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	1865	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	1866	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	1867	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	1868	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	1869	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	1870	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	1871	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	1872	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	1873	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	1874	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	1875	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	1876	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	1877	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	1878	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	1879	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	1880	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	1881	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	1882	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	1883	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	1884	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	1885	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	1886	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	1887	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	1888	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	1889	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	1890	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	1891	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	1892	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	1893	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	1894	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	1895	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	1896	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	1897	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	1898	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	1899	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	1900	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	1901	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	1902	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	1903	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	1904	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	1905	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	1906	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	1907	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	1908	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	1909	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	1910	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	1911	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	1912	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	1913	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	1914	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	1915	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	1916	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	1917	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	1918	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	1919	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	1920	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	1921	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	1922	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	1923	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	1924	* @param __PLLN__ Between 50 and 432
NYX	0:85b3fd62ea1a	1925	* @param __PLLR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1926	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	1927	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	1928	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	1929	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	1930	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	1931	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	1932	* @retval PLL clock frequency (in Hz)
NYX	0:85b3fd62ea1a	1933	*/
NYX	0:85b3fd62ea1a	1934	#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
NYX	0:85b3fd62ea1a	1935	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
NYX	0:85b3fd62ea1a	1936	#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
NYX	0:85b3fd62ea1a	1937
NYX	0:85b3fd62ea1a	1938	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	1939	/**
NYX	0:85b3fd62ea1a	1940	* @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
NYX	0:85b3fd62ea1a	1941	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
NYX	0:85b3fd62ea1a	1942	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
NYX	0:85b3fd62ea1a	1943	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	1944	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1945	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	1946	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	1947	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	1948	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	1949	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	1950	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	1951	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	1952	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	1953	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	1954	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	1955	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	1956	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	1957	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	1958	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	1959	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	1960	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	1961	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	1962	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	1963	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	1964	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	1965	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	1966	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	1967	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	1968	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	1969	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	1970	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	1971	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	1972	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	1973	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	1974	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	1975	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	1976	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	1977	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	1978	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	1979	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	1980	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	1981	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	1982	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	1983	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	1984	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	1985	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	1986	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	1987	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	1988	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	1989	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	1990	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	1991	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	1992	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	1993	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	1994	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	1995	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	1996	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	1997	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	1998	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	1999	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	2000	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	2001	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	2002	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	2003	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	2004	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	2005	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	2006	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	2007	* @param __PLLN__ Between 50 and 432
NYX	0:85b3fd62ea1a	2008	* @param __PLLR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2009	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	2010	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	2011	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	2012	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	2013	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	2014	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	2015	* @retval PLL clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2016	*/
NYX	0:85b3fd62ea1a	2017	#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
NYX	0:85b3fd62ea1a	2018	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
NYX	0:85b3fd62ea1a	2019	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	2020
NYX	0:85b3fd62ea1a	2021	#if defined(RCC_PLLCFGR_PLLR)
NYX	0:85b3fd62ea1a	2022	#if defined(SAI1)
NYX	0:85b3fd62ea1a	2023	/**
NYX	0:85b3fd62ea1a	2024	* @brief Helper macro to calculate the PLLCLK frequency used on SAI
NYX	0:85b3fd62ea1a	2025	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
NYX	0:85b3fd62ea1a	2026	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
NYX	0:85b3fd62ea1a	2027	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	2028	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2029	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	2030	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	2031	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	2032	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	2033	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	2034	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	2035	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	2036	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	2037	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	2038	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	2039	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	2040	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	2041	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	2042	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	2043	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	2044	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	2045	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	2046	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	2047	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	2048	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	2049	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	2050	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	2051	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	2052	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	2053	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	2054	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	2055	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	2056	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	2057	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	2058	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	2059	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	2060	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	2061	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	2062	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	2063	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	2064	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	2065	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	2066	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	2067	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	2068	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	2069	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	2070	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	2071	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	2072	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	2073	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	2074	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	2075	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	2076	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	2077	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	2078	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	2079	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	2080	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	2081	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	2082	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	2083	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	2084	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	2085	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	2086	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	2087	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	2088	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	2089	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	2090	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	2091	* @param __PLLN__ Between 50 and 432
NYX	0:85b3fd62ea1a	2092	* @param __PLLR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2093	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	2094	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	2095	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	2096	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	2097	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	2098	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	2099	* @param __PLLDIVR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2100	* @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
NYX	0:85b3fd62ea1a	2101	* @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
NYX	0:85b3fd62ea1a	2102	* @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
NYX	0:85b3fd62ea1a	2103	* @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
NYX	0:85b3fd62ea1a	2104	* @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
NYX	0:85b3fd62ea1a	2105	* @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
NYX	0:85b3fd62ea1a	2106	* @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
NYX	0:85b3fd62ea1a	2107	* @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
NYX	0:85b3fd62ea1a	2108	* @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
NYX	0:85b3fd62ea1a	2109	* @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
NYX	0:85b3fd62ea1a	2110	* @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
NYX	0:85b3fd62ea1a	2111	* @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
NYX	0:85b3fd62ea1a	2112	* @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
NYX	0:85b3fd62ea1a	2113	* @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
NYX	0:85b3fd62ea1a	2114	* @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
NYX	0:85b3fd62ea1a	2115	* @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
NYX	0:85b3fd62ea1a	2116	* @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
NYX	0:85b3fd62ea1a	2117	* @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
NYX	0:85b3fd62ea1a	2118	* @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
NYX	0:85b3fd62ea1a	2119	* @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
NYX	0:85b3fd62ea1a	2120	* @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
NYX	0:85b3fd62ea1a	2121	* @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
NYX	0:85b3fd62ea1a	2122	* @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
NYX	0:85b3fd62ea1a	2123	* @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
NYX	0:85b3fd62ea1a	2124	* @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
NYX	0:85b3fd62ea1a	2125	* @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
NYX	0:85b3fd62ea1a	2126	* @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
NYX	0:85b3fd62ea1a	2127	* @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
NYX	0:85b3fd62ea1a	2128	* @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
NYX	0:85b3fd62ea1a	2129	* @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
NYX	0:85b3fd62ea1a	2130	* @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
NYX	0:85b3fd62ea1a	2131	*
NYX	0:85b3fd62ea1a	2132	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	2133	* @retval PLL clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2134	*/
NYX	0:85b3fd62ea1a	2135	#if defined(RCC_DCKCFGR_PLLDIVR)
NYX	0:85b3fd62ea1a	2136	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
NYX	0:85b3fd62ea1a	2137	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
NYX	0:85b3fd62ea1a	2138	#else
NYX	0:85b3fd62ea1a	2139	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
NYX	0:85b3fd62ea1a	2140	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
NYX	0:85b3fd62ea1a	2141	#endif /* RCC_DCKCFGR_PLLDIVR */
NYX	0:85b3fd62ea1a	2142	#endif /* SAI1 */
NYX	0:85b3fd62ea1a	2143	#endif /* RCC_PLLCFGR_PLLR */
NYX	0:85b3fd62ea1a	2144
NYX	0:85b3fd62ea1a	2145	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	2146	/**
NYX	0:85b3fd62ea1a	2147	* @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
NYX	0:85b3fd62ea1a	2148	* @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
NYX	0:85b3fd62ea1a	2149	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
NYX	0:85b3fd62ea1a	2150	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	2151	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2152	* @arg @ref LL_RCC_PLLSAIM_DIV_2
NYX	0:85b3fd62ea1a	2153	* @arg @ref LL_RCC_PLLSAIM_DIV_3
NYX	0:85b3fd62ea1a	2154	* @arg @ref LL_RCC_PLLSAIM_DIV_4
NYX	0:85b3fd62ea1a	2155	* @arg @ref LL_RCC_PLLSAIM_DIV_5
NYX	0:85b3fd62ea1a	2156	* @arg @ref LL_RCC_PLLSAIM_DIV_6
NYX	0:85b3fd62ea1a	2157	* @arg @ref LL_RCC_PLLSAIM_DIV_7
NYX	0:85b3fd62ea1a	2158	* @arg @ref LL_RCC_PLLSAIM_DIV_8
NYX	0:85b3fd62ea1a	2159	* @arg @ref LL_RCC_PLLSAIM_DIV_9
NYX	0:85b3fd62ea1a	2160	* @arg @ref LL_RCC_PLLSAIM_DIV_10
NYX	0:85b3fd62ea1a	2161	* @arg @ref LL_RCC_PLLSAIM_DIV_11
NYX	0:85b3fd62ea1a	2162	* @arg @ref LL_RCC_PLLSAIM_DIV_12
NYX	0:85b3fd62ea1a	2163	* @arg @ref LL_RCC_PLLSAIM_DIV_13
NYX	0:85b3fd62ea1a	2164	* @arg @ref LL_RCC_PLLSAIM_DIV_14
NYX	0:85b3fd62ea1a	2165	* @arg @ref LL_RCC_PLLSAIM_DIV_15
NYX	0:85b3fd62ea1a	2166	* @arg @ref LL_RCC_PLLSAIM_DIV_16
NYX	0:85b3fd62ea1a	2167	* @arg @ref LL_RCC_PLLSAIM_DIV_17
NYX	0:85b3fd62ea1a	2168	* @arg @ref LL_RCC_PLLSAIM_DIV_18
NYX	0:85b3fd62ea1a	2169	* @arg @ref LL_RCC_PLLSAIM_DIV_19
NYX	0:85b3fd62ea1a	2170	* @arg @ref LL_RCC_PLLSAIM_DIV_20
NYX	0:85b3fd62ea1a	2171	* @arg @ref LL_RCC_PLLSAIM_DIV_21
NYX	0:85b3fd62ea1a	2172	* @arg @ref LL_RCC_PLLSAIM_DIV_22
NYX	0:85b3fd62ea1a	2173	* @arg @ref LL_RCC_PLLSAIM_DIV_23
NYX	0:85b3fd62ea1a	2174	* @arg @ref LL_RCC_PLLSAIM_DIV_24
NYX	0:85b3fd62ea1a	2175	* @arg @ref LL_RCC_PLLSAIM_DIV_25
NYX	0:85b3fd62ea1a	2176	* @arg @ref LL_RCC_PLLSAIM_DIV_26
NYX	0:85b3fd62ea1a	2177	* @arg @ref LL_RCC_PLLSAIM_DIV_27
NYX	0:85b3fd62ea1a	2178	* @arg @ref LL_RCC_PLLSAIM_DIV_28
NYX	0:85b3fd62ea1a	2179	* @arg @ref LL_RCC_PLLSAIM_DIV_29
NYX	0:85b3fd62ea1a	2180	* @arg @ref LL_RCC_PLLSAIM_DIV_30
NYX	0:85b3fd62ea1a	2181	* @arg @ref LL_RCC_PLLSAIM_DIV_31
NYX	0:85b3fd62ea1a	2182	* @arg @ref LL_RCC_PLLSAIM_DIV_32
NYX	0:85b3fd62ea1a	2183	* @arg @ref LL_RCC_PLLSAIM_DIV_33
NYX	0:85b3fd62ea1a	2184	* @arg @ref LL_RCC_PLLSAIM_DIV_34
NYX	0:85b3fd62ea1a	2185	* @arg @ref LL_RCC_PLLSAIM_DIV_35
NYX	0:85b3fd62ea1a	2186	* @arg @ref LL_RCC_PLLSAIM_DIV_36
NYX	0:85b3fd62ea1a	2187	* @arg @ref LL_RCC_PLLSAIM_DIV_37
NYX	0:85b3fd62ea1a	2188	* @arg @ref LL_RCC_PLLSAIM_DIV_38
NYX	0:85b3fd62ea1a	2189	* @arg @ref LL_RCC_PLLSAIM_DIV_39
NYX	0:85b3fd62ea1a	2190	* @arg @ref LL_RCC_PLLSAIM_DIV_40
NYX	0:85b3fd62ea1a	2191	* @arg @ref LL_RCC_PLLSAIM_DIV_41
NYX	0:85b3fd62ea1a	2192	* @arg @ref LL_RCC_PLLSAIM_DIV_42
NYX	0:85b3fd62ea1a	2193	* @arg @ref LL_RCC_PLLSAIM_DIV_43
NYX	0:85b3fd62ea1a	2194	* @arg @ref LL_RCC_PLLSAIM_DIV_44
NYX	0:85b3fd62ea1a	2195	* @arg @ref LL_RCC_PLLSAIM_DIV_45
NYX	0:85b3fd62ea1a	2196	* @arg @ref LL_RCC_PLLSAIM_DIV_46
NYX	0:85b3fd62ea1a	2197	* @arg @ref LL_RCC_PLLSAIM_DIV_47
NYX	0:85b3fd62ea1a	2198	* @arg @ref LL_RCC_PLLSAIM_DIV_48
NYX	0:85b3fd62ea1a	2199	* @arg @ref LL_RCC_PLLSAIM_DIV_49
NYX	0:85b3fd62ea1a	2200	* @arg @ref LL_RCC_PLLSAIM_DIV_50
NYX	0:85b3fd62ea1a	2201	* @arg @ref LL_RCC_PLLSAIM_DIV_51
NYX	0:85b3fd62ea1a	2202	* @arg @ref LL_RCC_PLLSAIM_DIV_52
NYX	0:85b3fd62ea1a	2203	* @arg @ref LL_RCC_PLLSAIM_DIV_53
NYX	0:85b3fd62ea1a	2204	* @arg @ref LL_RCC_PLLSAIM_DIV_54
NYX	0:85b3fd62ea1a	2205	* @arg @ref LL_RCC_PLLSAIM_DIV_55
NYX	0:85b3fd62ea1a	2206	* @arg @ref LL_RCC_PLLSAIM_DIV_56
NYX	0:85b3fd62ea1a	2207	* @arg @ref LL_RCC_PLLSAIM_DIV_57
NYX	0:85b3fd62ea1a	2208	* @arg @ref LL_RCC_PLLSAIM_DIV_58
NYX	0:85b3fd62ea1a	2209	* @arg @ref LL_RCC_PLLSAIM_DIV_59
NYX	0:85b3fd62ea1a	2210	* @arg @ref LL_RCC_PLLSAIM_DIV_60
NYX	0:85b3fd62ea1a	2211	* @arg @ref LL_RCC_PLLSAIM_DIV_61
NYX	0:85b3fd62ea1a	2212	* @arg @ref LL_RCC_PLLSAIM_DIV_62
NYX	0:85b3fd62ea1a	2213	* @arg @ref LL_RCC_PLLSAIM_DIV_63
NYX	0:85b3fd62ea1a	2214	* @param __PLLSAIN__ Between 49/50(*) and 432
NYX	0:85b3fd62ea1a	2215	*
NYX	0:85b3fd62ea1a	2216	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	2217	* @param __PLLSAIQ__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2218	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
NYX	0:85b3fd62ea1a	2219	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
NYX	0:85b3fd62ea1a	2220	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
NYX	0:85b3fd62ea1a	2221	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
NYX	0:85b3fd62ea1a	2222	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
NYX	0:85b3fd62ea1a	2223	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
NYX	0:85b3fd62ea1a	2224	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
NYX	0:85b3fd62ea1a	2225	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
NYX	0:85b3fd62ea1a	2226	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
NYX	0:85b3fd62ea1a	2227	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
NYX	0:85b3fd62ea1a	2228	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
NYX	0:85b3fd62ea1a	2229	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
NYX	0:85b3fd62ea1a	2230	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
NYX	0:85b3fd62ea1a	2231	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
NYX	0:85b3fd62ea1a	2232	* @param __PLLSAIDIVQ__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2233	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
NYX	0:85b3fd62ea1a	2234	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
NYX	0:85b3fd62ea1a	2235	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
NYX	0:85b3fd62ea1a	2236	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
NYX	0:85b3fd62ea1a	2237	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
NYX	0:85b3fd62ea1a	2238	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
NYX	0:85b3fd62ea1a	2239	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
NYX	0:85b3fd62ea1a	2240	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
NYX	0:85b3fd62ea1a	2241	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
NYX	0:85b3fd62ea1a	2242	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
NYX	0:85b3fd62ea1a	2243	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
NYX	0:85b3fd62ea1a	2244	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
NYX	0:85b3fd62ea1a	2245	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
NYX	0:85b3fd62ea1a	2246	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
NYX	0:85b3fd62ea1a	2247	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
NYX	0:85b3fd62ea1a	2248	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
NYX	0:85b3fd62ea1a	2249	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
NYX	0:85b3fd62ea1a	2250	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
NYX	0:85b3fd62ea1a	2251	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
NYX	0:85b3fd62ea1a	2252	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
NYX	0:85b3fd62ea1a	2253	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
NYX	0:85b3fd62ea1a	2254	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
NYX	0:85b3fd62ea1a	2255	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
NYX	0:85b3fd62ea1a	2256	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
NYX	0:85b3fd62ea1a	2257	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
NYX	0:85b3fd62ea1a	2258	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
NYX	0:85b3fd62ea1a	2259	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
NYX	0:85b3fd62ea1a	2260	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
NYX	0:85b3fd62ea1a	2261	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
NYX	0:85b3fd62ea1a	2262	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
NYX	0:85b3fd62ea1a	2263	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
NYX	0:85b3fd62ea1a	2264	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
NYX	0:85b3fd62ea1a	2265	* @retval PLLSAI clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2266	*/
NYX	0:85b3fd62ea1a	2267	#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
NYX	0:85b3fd62ea1a	2268	(((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
NYX	0:85b3fd62ea1a	2269
NYX	0:85b3fd62ea1a	2270	#if defined(RCC_PLLSAICFGR_PLLSAIP)
NYX	0:85b3fd62ea1a	2271	/**
NYX	0:85b3fd62ea1a	2272	* @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
NYX	0:85b3fd62ea1a	2273	* @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
NYX	0:85b3fd62ea1a	2274	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
NYX	0:85b3fd62ea1a	2275	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	2276	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2277	* @arg @ref LL_RCC_PLLSAIM_DIV_2
NYX	0:85b3fd62ea1a	2278	* @arg @ref LL_RCC_PLLSAIM_DIV_3
NYX	0:85b3fd62ea1a	2279	* @arg @ref LL_RCC_PLLSAIM_DIV_4
NYX	0:85b3fd62ea1a	2280	* @arg @ref LL_RCC_PLLSAIM_DIV_5
NYX	0:85b3fd62ea1a	2281	* @arg @ref LL_RCC_PLLSAIM_DIV_6
NYX	0:85b3fd62ea1a	2282	* @arg @ref LL_RCC_PLLSAIM_DIV_7
NYX	0:85b3fd62ea1a	2283	* @arg @ref LL_RCC_PLLSAIM_DIV_8
NYX	0:85b3fd62ea1a	2284	* @arg @ref LL_RCC_PLLSAIM_DIV_9
NYX	0:85b3fd62ea1a	2285	* @arg @ref LL_RCC_PLLSAIM_DIV_10
NYX	0:85b3fd62ea1a	2286	* @arg @ref LL_RCC_PLLSAIM_DIV_11
NYX	0:85b3fd62ea1a	2287	* @arg @ref LL_RCC_PLLSAIM_DIV_12
NYX	0:85b3fd62ea1a	2288	* @arg @ref LL_RCC_PLLSAIM_DIV_13
NYX	0:85b3fd62ea1a	2289	* @arg @ref LL_RCC_PLLSAIM_DIV_14
NYX	0:85b3fd62ea1a	2290	* @arg @ref LL_RCC_PLLSAIM_DIV_15
NYX	0:85b3fd62ea1a	2291	* @arg @ref LL_RCC_PLLSAIM_DIV_16
NYX	0:85b3fd62ea1a	2292	* @arg @ref LL_RCC_PLLSAIM_DIV_17
NYX	0:85b3fd62ea1a	2293	* @arg @ref LL_RCC_PLLSAIM_DIV_18
NYX	0:85b3fd62ea1a	2294	* @arg @ref LL_RCC_PLLSAIM_DIV_19
NYX	0:85b3fd62ea1a	2295	* @arg @ref LL_RCC_PLLSAIM_DIV_20
NYX	0:85b3fd62ea1a	2296	* @arg @ref LL_RCC_PLLSAIM_DIV_21
NYX	0:85b3fd62ea1a	2297	* @arg @ref LL_RCC_PLLSAIM_DIV_22
NYX	0:85b3fd62ea1a	2298	* @arg @ref LL_RCC_PLLSAIM_DIV_23
NYX	0:85b3fd62ea1a	2299	* @arg @ref LL_RCC_PLLSAIM_DIV_24
NYX	0:85b3fd62ea1a	2300	* @arg @ref LL_RCC_PLLSAIM_DIV_25
NYX	0:85b3fd62ea1a	2301	* @arg @ref LL_RCC_PLLSAIM_DIV_26
NYX	0:85b3fd62ea1a	2302	* @arg @ref LL_RCC_PLLSAIM_DIV_27
NYX	0:85b3fd62ea1a	2303	* @arg @ref LL_RCC_PLLSAIM_DIV_28
NYX	0:85b3fd62ea1a	2304	* @arg @ref LL_RCC_PLLSAIM_DIV_29
NYX	0:85b3fd62ea1a	2305	* @arg @ref LL_RCC_PLLSAIM_DIV_30
NYX	0:85b3fd62ea1a	2306	* @arg @ref LL_RCC_PLLSAIM_DIV_31
NYX	0:85b3fd62ea1a	2307	* @arg @ref LL_RCC_PLLSAIM_DIV_32
NYX	0:85b3fd62ea1a	2308	* @arg @ref LL_RCC_PLLSAIM_DIV_33
NYX	0:85b3fd62ea1a	2309	* @arg @ref LL_RCC_PLLSAIM_DIV_34
NYX	0:85b3fd62ea1a	2310	* @arg @ref LL_RCC_PLLSAIM_DIV_35
NYX	0:85b3fd62ea1a	2311	* @arg @ref LL_RCC_PLLSAIM_DIV_36
NYX	0:85b3fd62ea1a	2312	* @arg @ref LL_RCC_PLLSAIM_DIV_37
NYX	0:85b3fd62ea1a	2313	* @arg @ref LL_RCC_PLLSAIM_DIV_38
NYX	0:85b3fd62ea1a	2314	* @arg @ref LL_RCC_PLLSAIM_DIV_39
NYX	0:85b3fd62ea1a	2315	* @arg @ref LL_RCC_PLLSAIM_DIV_40
NYX	0:85b3fd62ea1a	2316	* @arg @ref LL_RCC_PLLSAIM_DIV_41
NYX	0:85b3fd62ea1a	2317	* @arg @ref LL_RCC_PLLSAIM_DIV_42
NYX	0:85b3fd62ea1a	2318	* @arg @ref LL_RCC_PLLSAIM_DIV_43
NYX	0:85b3fd62ea1a	2319	* @arg @ref LL_RCC_PLLSAIM_DIV_44
NYX	0:85b3fd62ea1a	2320	* @arg @ref LL_RCC_PLLSAIM_DIV_45
NYX	0:85b3fd62ea1a	2321	* @arg @ref LL_RCC_PLLSAIM_DIV_46
NYX	0:85b3fd62ea1a	2322	* @arg @ref LL_RCC_PLLSAIM_DIV_47
NYX	0:85b3fd62ea1a	2323	* @arg @ref LL_RCC_PLLSAIM_DIV_48
NYX	0:85b3fd62ea1a	2324	* @arg @ref LL_RCC_PLLSAIM_DIV_49
NYX	0:85b3fd62ea1a	2325	* @arg @ref LL_RCC_PLLSAIM_DIV_50
NYX	0:85b3fd62ea1a	2326	* @arg @ref LL_RCC_PLLSAIM_DIV_51
NYX	0:85b3fd62ea1a	2327	* @arg @ref LL_RCC_PLLSAIM_DIV_52
NYX	0:85b3fd62ea1a	2328	* @arg @ref LL_RCC_PLLSAIM_DIV_53
NYX	0:85b3fd62ea1a	2329	* @arg @ref LL_RCC_PLLSAIM_DIV_54
NYX	0:85b3fd62ea1a	2330	* @arg @ref LL_RCC_PLLSAIM_DIV_55
NYX	0:85b3fd62ea1a	2331	* @arg @ref LL_RCC_PLLSAIM_DIV_56
NYX	0:85b3fd62ea1a	2332	* @arg @ref LL_RCC_PLLSAIM_DIV_57
NYX	0:85b3fd62ea1a	2333	* @arg @ref LL_RCC_PLLSAIM_DIV_58
NYX	0:85b3fd62ea1a	2334	* @arg @ref LL_RCC_PLLSAIM_DIV_59
NYX	0:85b3fd62ea1a	2335	* @arg @ref LL_RCC_PLLSAIM_DIV_60
NYX	0:85b3fd62ea1a	2336	* @arg @ref LL_RCC_PLLSAIM_DIV_61
NYX	0:85b3fd62ea1a	2337	* @arg @ref LL_RCC_PLLSAIM_DIV_62
NYX	0:85b3fd62ea1a	2338	* @arg @ref LL_RCC_PLLSAIM_DIV_63
NYX	0:85b3fd62ea1a	2339	* @param __PLLSAIN__ Between 50 and 432
NYX	0:85b3fd62ea1a	2340	* @param __PLLSAIP__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2341	* @arg @ref LL_RCC_PLLSAIP_DIV_2
NYX	0:85b3fd62ea1a	2342	* @arg @ref LL_RCC_PLLSAIP_DIV_4
NYX	0:85b3fd62ea1a	2343	* @arg @ref LL_RCC_PLLSAIP_DIV_6
NYX	0:85b3fd62ea1a	2344	* @arg @ref LL_RCC_PLLSAIP_DIV_8
NYX	0:85b3fd62ea1a	2345	* @retval PLLSAI clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2346	*/
NYX	0:85b3fd62ea1a	2347	#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
NYX	0:85b3fd62ea1a	2348	((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
NYX	0:85b3fd62ea1a	2349	#endif /* RCC_PLLSAICFGR_PLLSAIP */
NYX	0:85b3fd62ea1a	2350
NYX	0:85b3fd62ea1a	2351	#if defined(LTDC)
NYX	0:85b3fd62ea1a	2352	/**
NYX	0:85b3fd62ea1a	2353	* @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
NYX	0:85b3fd62ea1a	2354	* @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
NYX	0:85b3fd62ea1a	2355	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
NYX	0:85b3fd62ea1a	2356	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	2357	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2358	* @arg @ref LL_RCC_PLLSAIM_DIV_2
NYX	0:85b3fd62ea1a	2359	* @arg @ref LL_RCC_PLLSAIM_DIV_3
NYX	0:85b3fd62ea1a	2360	* @arg @ref LL_RCC_PLLSAIM_DIV_4
NYX	0:85b3fd62ea1a	2361	* @arg @ref LL_RCC_PLLSAIM_DIV_5
NYX	0:85b3fd62ea1a	2362	* @arg @ref LL_RCC_PLLSAIM_DIV_6
NYX	0:85b3fd62ea1a	2363	* @arg @ref LL_RCC_PLLSAIM_DIV_7
NYX	0:85b3fd62ea1a	2364	* @arg @ref LL_RCC_PLLSAIM_DIV_8
NYX	0:85b3fd62ea1a	2365	* @arg @ref LL_RCC_PLLSAIM_DIV_9
NYX	0:85b3fd62ea1a	2366	* @arg @ref LL_RCC_PLLSAIM_DIV_10
NYX	0:85b3fd62ea1a	2367	* @arg @ref LL_RCC_PLLSAIM_DIV_11
NYX	0:85b3fd62ea1a	2368	* @arg @ref LL_RCC_PLLSAIM_DIV_12
NYX	0:85b3fd62ea1a	2369	* @arg @ref LL_RCC_PLLSAIM_DIV_13
NYX	0:85b3fd62ea1a	2370	* @arg @ref LL_RCC_PLLSAIM_DIV_14
NYX	0:85b3fd62ea1a	2371	* @arg @ref LL_RCC_PLLSAIM_DIV_15
NYX	0:85b3fd62ea1a	2372	* @arg @ref LL_RCC_PLLSAIM_DIV_16
NYX	0:85b3fd62ea1a	2373	* @arg @ref LL_RCC_PLLSAIM_DIV_17
NYX	0:85b3fd62ea1a	2374	* @arg @ref LL_RCC_PLLSAIM_DIV_18
NYX	0:85b3fd62ea1a	2375	* @arg @ref LL_RCC_PLLSAIM_DIV_19
NYX	0:85b3fd62ea1a	2376	* @arg @ref LL_RCC_PLLSAIM_DIV_20
NYX	0:85b3fd62ea1a	2377	* @arg @ref LL_RCC_PLLSAIM_DIV_21
NYX	0:85b3fd62ea1a	2378	* @arg @ref LL_RCC_PLLSAIM_DIV_22
NYX	0:85b3fd62ea1a	2379	* @arg @ref LL_RCC_PLLSAIM_DIV_23
NYX	0:85b3fd62ea1a	2380	* @arg @ref LL_RCC_PLLSAIM_DIV_24
NYX	0:85b3fd62ea1a	2381	* @arg @ref LL_RCC_PLLSAIM_DIV_25
NYX	0:85b3fd62ea1a	2382	* @arg @ref LL_RCC_PLLSAIM_DIV_26
NYX	0:85b3fd62ea1a	2383	* @arg @ref LL_RCC_PLLSAIM_DIV_27
NYX	0:85b3fd62ea1a	2384	* @arg @ref LL_RCC_PLLSAIM_DIV_28
NYX	0:85b3fd62ea1a	2385	* @arg @ref LL_RCC_PLLSAIM_DIV_29
NYX	0:85b3fd62ea1a	2386	* @arg @ref LL_RCC_PLLSAIM_DIV_30
NYX	0:85b3fd62ea1a	2387	* @arg @ref LL_RCC_PLLSAIM_DIV_31
NYX	0:85b3fd62ea1a	2388	* @arg @ref LL_RCC_PLLSAIM_DIV_32
NYX	0:85b3fd62ea1a	2389	* @arg @ref LL_RCC_PLLSAIM_DIV_33
NYX	0:85b3fd62ea1a	2390	* @arg @ref LL_RCC_PLLSAIM_DIV_34
NYX	0:85b3fd62ea1a	2391	* @arg @ref LL_RCC_PLLSAIM_DIV_35
NYX	0:85b3fd62ea1a	2392	* @arg @ref LL_RCC_PLLSAIM_DIV_36
NYX	0:85b3fd62ea1a	2393	* @arg @ref LL_RCC_PLLSAIM_DIV_37
NYX	0:85b3fd62ea1a	2394	* @arg @ref LL_RCC_PLLSAIM_DIV_38
NYX	0:85b3fd62ea1a	2395	* @arg @ref LL_RCC_PLLSAIM_DIV_39
NYX	0:85b3fd62ea1a	2396	* @arg @ref LL_RCC_PLLSAIM_DIV_40
NYX	0:85b3fd62ea1a	2397	* @arg @ref LL_RCC_PLLSAIM_DIV_41
NYX	0:85b3fd62ea1a	2398	* @arg @ref LL_RCC_PLLSAIM_DIV_42
NYX	0:85b3fd62ea1a	2399	* @arg @ref LL_RCC_PLLSAIM_DIV_43
NYX	0:85b3fd62ea1a	2400	* @arg @ref LL_RCC_PLLSAIM_DIV_44
NYX	0:85b3fd62ea1a	2401	* @arg @ref LL_RCC_PLLSAIM_DIV_45
NYX	0:85b3fd62ea1a	2402	* @arg @ref LL_RCC_PLLSAIM_DIV_46
NYX	0:85b3fd62ea1a	2403	* @arg @ref LL_RCC_PLLSAIM_DIV_47
NYX	0:85b3fd62ea1a	2404	* @arg @ref LL_RCC_PLLSAIM_DIV_48
NYX	0:85b3fd62ea1a	2405	* @arg @ref LL_RCC_PLLSAIM_DIV_49
NYX	0:85b3fd62ea1a	2406	* @arg @ref LL_RCC_PLLSAIM_DIV_50
NYX	0:85b3fd62ea1a	2407	* @arg @ref LL_RCC_PLLSAIM_DIV_51
NYX	0:85b3fd62ea1a	2408	* @arg @ref LL_RCC_PLLSAIM_DIV_52
NYX	0:85b3fd62ea1a	2409	* @arg @ref LL_RCC_PLLSAIM_DIV_53
NYX	0:85b3fd62ea1a	2410	* @arg @ref LL_RCC_PLLSAIM_DIV_54
NYX	0:85b3fd62ea1a	2411	* @arg @ref LL_RCC_PLLSAIM_DIV_55
NYX	0:85b3fd62ea1a	2412	* @arg @ref LL_RCC_PLLSAIM_DIV_56
NYX	0:85b3fd62ea1a	2413	* @arg @ref LL_RCC_PLLSAIM_DIV_57
NYX	0:85b3fd62ea1a	2414	* @arg @ref LL_RCC_PLLSAIM_DIV_58
NYX	0:85b3fd62ea1a	2415	* @arg @ref LL_RCC_PLLSAIM_DIV_59
NYX	0:85b3fd62ea1a	2416	* @arg @ref LL_RCC_PLLSAIM_DIV_60
NYX	0:85b3fd62ea1a	2417	* @arg @ref LL_RCC_PLLSAIM_DIV_61
NYX	0:85b3fd62ea1a	2418	* @arg @ref LL_RCC_PLLSAIM_DIV_62
NYX	0:85b3fd62ea1a	2419	* @arg @ref LL_RCC_PLLSAIM_DIV_63
NYX	0:85b3fd62ea1a	2420	* @param __PLLSAIN__ Between 49/50(*) and 432
NYX	0:85b3fd62ea1a	2421	*
NYX	0:85b3fd62ea1a	2422	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	2423	* @param __PLLSAIR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2424	* @arg @ref LL_RCC_PLLSAIR_DIV_2
NYX	0:85b3fd62ea1a	2425	* @arg @ref LL_RCC_PLLSAIR_DIV_3
NYX	0:85b3fd62ea1a	2426	* @arg @ref LL_RCC_PLLSAIR_DIV_4
NYX	0:85b3fd62ea1a	2427	* @arg @ref LL_RCC_PLLSAIR_DIV_5
NYX	0:85b3fd62ea1a	2428	* @arg @ref LL_RCC_PLLSAIR_DIV_6
NYX	0:85b3fd62ea1a	2429	* @arg @ref LL_RCC_PLLSAIR_DIV_7
NYX	0:85b3fd62ea1a	2430	* @param __PLLSAIDIVR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2431	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
NYX	0:85b3fd62ea1a	2432	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
NYX	0:85b3fd62ea1a	2433	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
NYX	0:85b3fd62ea1a	2434	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
NYX	0:85b3fd62ea1a	2435	* @retval PLLSAI clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2436	*/
NYX	0:85b3fd62ea1a	2437	#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
NYX	0:85b3fd62ea1a	2438	(((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
NYX	0:85b3fd62ea1a	2439	#endif /* LTDC */
NYX	0:85b3fd62ea1a	2440	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	2441
NYX	0:85b3fd62ea1a	2442	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	2443	#if defined(RCC_DCKCFGR_PLLI2SDIVQ) \|\| defined(RCC_DCKCFGR_PLLI2SDIVR)
NYX	0:85b3fd62ea1a	2444	/**
NYX	0:85b3fd62ea1a	2445	* @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
NYX	0:85b3fd62ea1a	2446	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
NYX	0:85b3fd62ea1a	2447	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
NYX	0:85b3fd62ea1a	2448	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	2449	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2450	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	2451	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	2452	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	2453	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	2454	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	2455	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	2456	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	2457	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	2458	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	2459	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	2460	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	2461	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	2462	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	2463	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	2464	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	2465	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	2466	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	2467	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	2468	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	2469	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	2470	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	2471	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	2472	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	2473	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	2474	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	2475	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	2476	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	2477	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	2478	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	2479	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	2480	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	2481	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	2482	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	2483	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	2484	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	2485	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	2486	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	2487	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	2488	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	2489	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	2490	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	2491	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	2492	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	2493	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	2494	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	2495	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	2496	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	2497	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	2498	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	2499	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	2500	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	2501	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	2502	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	2503	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	2504	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	2505	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	2506	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	2507	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	2508	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	2509	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	2510	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	2511	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	2512	* @param __PLLI2SN__ Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	2513	*
NYX	0:85b3fd62ea1a	2514	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	2515	* @param __PLLI2SQ_R__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2516	* @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
NYX	0:85b3fd62ea1a	2517	* @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
NYX	0:85b3fd62ea1a	2518	* @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
NYX	0:85b3fd62ea1a	2519	* @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
NYX	0:85b3fd62ea1a	2520	* @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
NYX	0:85b3fd62ea1a	2521	* @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
NYX	0:85b3fd62ea1a	2522	* @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
NYX	0:85b3fd62ea1a	2523	* @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
NYX	0:85b3fd62ea1a	2524	* @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
NYX	0:85b3fd62ea1a	2525	* @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
NYX	0:85b3fd62ea1a	2526	* @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
NYX	0:85b3fd62ea1a	2527	* @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
NYX	0:85b3fd62ea1a	2528	* @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
NYX	0:85b3fd62ea1a	2529	* @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
NYX	0:85b3fd62ea1a	2530	* @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
NYX	0:85b3fd62ea1a	2531	* @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
NYX	0:85b3fd62ea1a	2532	* @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
NYX	0:85b3fd62ea1a	2533	* @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
NYX	0:85b3fd62ea1a	2534	* @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
NYX	0:85b3fd62ea1a	2535	* @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
NYX	0:85b3fd62ea1a	2536	*
NYX	0:85b3fd62ea1a	2537	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	2538	* @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2539	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
NYX	0:85b3fd62ea1a	2540	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
NYX	0:85b3fd62ea1a	2541	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
NYX	0:85b3fd62ea1a	2542	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
NYX	0:85b3fd62ea1a	2543	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
NYX	0:85b3fd62ea1a	2544	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
NYX	0:85b3fd62ea1a	2545	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
NYX	0:85b3fd62ea1a	2546	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
NYX	0:85b3fd62ea1a	2547	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
NYX	0:85b3fd62ea1a	2548	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
NYX	0:85b3fd62ea1a	2549	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
NYX	0:85b3fd62ea1a	2550	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
NYX	0:85b3fd62ea1a	2551	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
NYX	0:85b3fd62ea1a	2552	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
NYX	0:85b3fd62ea1a	2553	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
NYX	0:85b3fd62ea1a	2554	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
NYX	0:85b3fd62ea1a	2555	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
NYX	0:85b3fd62ea1a	2556	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
NYX	0:85b3fd62ea1a	2557	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
NYX	0:85b3fd62ea1a	2558	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
NYX	0:85b3fd62ea1a	2559	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
NYX	0:85b3fd62ea1a	2560	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
NYX	0:85b3fd62ea1a	2561	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
NYX	0:85b3fd62ea1a	2562	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
NYX	0:85b3fd62ea1a	2563	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
NYX	0:85b3fd62ea1a	2564	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
NYX	0:85b3fd62ea1a	2565	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
NYX	0:85b3fd62ea1a	2566	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
NYX	0:85b3fd62ea1a	2567	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
NYX	0:85b3fd62ea1a	2568	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
NYX	0:85b3fd62ea1a	2569	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
NYX	0:85b3fd62ea1a	2570	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
NYX	0:85b3fd62ea1a	2571	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
NYX	0:85b3fd62ea1a	2572	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
NYX	0:85b3fd62ea1a	2573	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
NYX	0:85b3fd62ea1a	2574	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
NYX	0:85b3fd62ea1a	2575	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
NYX	0:85b3fd62ea1a	2576	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
NYX	0:85b3fd62ea1a	2577	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
NYX	0:85b3fd62ea1a	2578	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
NYX	0:85b3fd62ea1a	2579	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
NYX	0:85b3fd62ea1a	2580	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
NYX	0:85b3fd62ea1a	2581	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
NYX	0:85b3fd62ea1a	2582	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
NYX	0:85b3fd62ea1a	2583	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
NYX	0:85b3fd62ea1a	2584	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
NYX	0:85b3fd62ea1a	2585	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
NYX	0:85b3fd62ea1a	2586	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
NYX	0:85b3fd62ea1a	2587	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
NYX	0:85b3fd62ea1a	2588	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
NYX	0:85b3fd62ea1a	2589	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
NYX	0:85b3fd62ea1a	2590	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
NYX	0:85b3fd62ea1a	2591	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
NYX	0:85b3fd62ea1a	2592	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
NYX	0:85b3fd62ea1a	2593	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
NYX	0:85b3fd62ea1a	2594	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
NYX	0:85b3fd62ea1a	2595	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
NYX	0:85b3fd62ea1a	2596	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
NYX	0:85b3fd62ea1a	2597	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
NYX	0:85b3fd62ea1a	2598	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
NYX	0:85b3fd62ea1a	2599	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
NYX	0:85b3fd62ea1a	2600	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
NYX	0:85b3fd62ea1a	2601	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
NYX	0:85b3fd62ea1a	2602	*
NYX	0:85b3fd62ea1a	2603	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	2604	* @retval PLLI2S clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2605	*/
NYX	0:85b3fd62ea1a	2606	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	2607	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
NYX	0:85b3fd62ea1a	2608	(((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
NYX	0:85b3fd62ea1a	2609	#else
NYX	0:85b3fd62ea1a	2610	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
NYX	0:85b3fd62ea1a	2611	(((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
NYX	0:85b3fd62ea1a	2612
NYX	0:85b3fd62ea1a	2613	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	2614	#endif /* RCC_DCKCFGR_PLLI2SDIVQ \|\| RCC_DCKCFGR_PLLI2SDIVR */
NYX	0:85b3fd62ea1a	2615
NYX	0:85b3fd62ea1a	2616	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	2617	/**
NYX	0:85b3fd62ea1a	2618	* @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
NYX	0:85b3fd62ea1a	2619	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
NYX	0:85b3fd62ea1a	2620	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
NYX	0:85b3fd62ea1a	2621	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	2622	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2623	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	2624	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	2625	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	2626	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	2627	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	2628	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	2629	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	2630	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	2631	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	2632	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	2633	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	2634	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	2635	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	2636	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	2637	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	2638	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	2639	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	2640	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	2641	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	2642	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	2643	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	2644	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	2645	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	2646	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	2647	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	2648	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	2649	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	2650	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	2651	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	2652	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	2653	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	2654	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	2655	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	2656	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	2657	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	2658	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	2659	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	2660	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	2661	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	2662	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	2663	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	2664	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	2665	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	2666	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	2667	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	2668	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	2669	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	2670	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	2671	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	2672	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	2673	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	2674	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	2675	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	2676	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	2677	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	2678	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	2679	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	2680	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	2681	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	2682	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	2683	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	2684	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	2685	* @param __PLLI2SN__ Between 50 and 432
NYX	0:85b3fd62ea1a	2686	* @param __PLLI2SP__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2687	* @arg @ref LL_RCC_PLLI2SP_DIV_2
NYX	0:85b3fd62ea1a	2688	* @arg @ref LL_RCC_PLLI2SP_DIV_4
NYX	0:85b3fd62ea1a	2689	* @arg @ref LL_RCC_PLLI2SP_DIV_6
NYX	0:85b3fd62ea1a	2690	* @arg @ref LL_RCC_PLLI2SP_DIV_8
NYX	0:85b3fd62ea1a	2691	* @retval PLLI2S clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2692	*/
NYX	0:85b3fd62ea1a	2693	#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
NYX	0:85b3fd62ea1a	2694	((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
NYX	0:85b3fd62ea1a	2695
NYX	0:85b3fd62ea1a	2696	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	2697
NYX	0:85b3fd62ea1a	2698	/**
NYX	0:85b3fd62ea1a	2699	* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
NYX	0:85b3fd62ea1a	2700	* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
NYX	0:85b3fd62ea1a	2701	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
NYX	0:85b3fd62ea1a	2702	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	2703	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2704	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	2705	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	2706	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	2707	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	2708	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	2709	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	2710	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	2711	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	2712	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	2713	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	2714	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	2715	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	2716	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	2717	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	2718	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	2719	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	2720	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	2721	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	2722	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	2723	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	2724	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	2725	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	2726	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	2727	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	2728	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	2729	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	2730	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	2731	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	2732	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	2733	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	2734	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	2735	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	2736	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	2737	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	2738	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	2739	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	2740	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	2741	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	2742	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	2743	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	2744	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	2745	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	2746	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	2747	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	2748	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	2749	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	2750	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	2751	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	2752	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	2753	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	2754	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	2755	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	2756	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	2757	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	2758	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	2759	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	2760	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	2761	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	2762	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	2763	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	2764	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	2765	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	2766	* @param __PLLI2SN__ Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	2767	*
NYX	0:85b3fd62ea1a	2768	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	2769	* @param __PLLI2SR__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2770	* @arg @ref LL_RCC_PLLI2SR_DIV_2
NYX	0:85b3fd62ea1a	2771	* @arg @ref LL_RCC_PLLI2SR_DIV_3
NYX	0:85b3fd62ea1a	2772	* @arg @ref LL_RCC_PLLI2SR_DIV_4
NYX	0:85b3fd62ea1a	2773	* @arg @ref LL_RCC_PLLI2SR_DIV_5
NYX	0:85b3fd62ea1a	2774	* @arg @ref LL_RCC_PLLI2SR_DIV_6
NYX	0:85b3fd62ea1a	2775	* @arg @ref LL_RCC_PLLI2SR_DIV_7
NYX	0:85b3fd62ea1a	2776	* @retval PLLI2S clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2777	*/
NYX	0:85b3fd62ea1a	2778	#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
NYX	0:85b3fd62ea1a	2779	((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
NYX	0:85b3fd62ea1a	2780
NYX	0:85b3fd62ea1a	2781	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	2782	/**
NYX	0:85b3fd62ea1a	2783	* @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
NYX	0:85b3fd62ea1a	2784	* @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
NYX	0:85b3fd62ea1a	2785	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
NYX	0:85b3fd62ea1a	2786	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
NYX	0:85b3fd62ea1a	2787	* @param __PLLM__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2788	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	2789	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	2790	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	2791	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	2792	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	2793	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	2794	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	2795	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	2796	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	2797	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	2798	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	2799	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	2800	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	2801	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	2802	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	2803	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	2804	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	2805	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	2806	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	2807	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	2808	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	2809	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	2810	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	2811	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	2812	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	2813	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	2814	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	2815	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	2816	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	2817	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	2818	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	2819	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	2820	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	2821	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	2822	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	2823	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	2824	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	2825	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	2826	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	2827	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	2828	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	2829	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	2830	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	2831	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	2832	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	2833	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	2834	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	2835	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	2836	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	2837	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	2838	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	2839	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	2840	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	2841	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	2842	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	2843	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	2844	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	2845	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	2846	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	2847	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	2848	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	2849	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	2850	* @param __PLLI2SN__ Between 50 and 432
NYX	0:85b3fd62ea1a	2851	* @param __PLLI2SQ__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2852	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
NYX	0:85b3fd62ea1a	2853	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
NYX	0:85b3fd62ea1a	2854	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
NYX	0:85b3fd62ea1a	2855	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
NYX	0:85b3fd62ea1a	2856	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
NYX	0:85b3fd62ea1a	2857	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
NYX	0:85b3fd62ea1a	2858	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
NYX	0:85b3fd62ea1a	2859	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
NYX	0:85b3fd62ea1a	2860	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
NYX	0:85b3fd62ea1a	2861	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
NYX	0:85b3fd62ea1a	2862	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
NYX	0:85b3fd62ea1a	2863	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
NYX	0:85b3fd62ea1a	2864	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
NYX	0:85b3fd62ea1a	2865	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
NYX	0:85b3fd62ea1a	2866	* @retval PLLI2S clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2867	*/
NYX	0:85b3fd62ea1a	2868	#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
NYX	0:85b3fd62ea1a	2869	((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
NYX	0:85b3fd62ea1a	2870
NYX	0:85b3fd62ea1a	2871	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	2872	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	2873
NYX	0:85b3fd62ea1a	2874	/**
NYX	0:85b3fd62ea1a	2875	* @brief Helper macro to calculate the HCLK frequency
NYX	0:85b3fd62ea1a	2876	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
NYX	0:85b3fd62ea1a	2877	* @param __AHBPRESCALER__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2878	* @arg @ref LL_RCC_SYSCLK_DIV_1
NYX	0:85b3fd62ea1a	2879	* @arg @ref LL_RCC_SYSCLK_DIV_2
NYX	0:85b3fd62ea1a	2880	* @arg @ref LL_RCC_SYSCLK_DIV_4
NYX	0:85b3fd62ea1a	2881	* @arg @ref LL_RCC_SYSCLK_DIV_8
NYX	0:85b3fd62ea1a	2882	* @arg @ref LL_RCC_SYSCLK_DIV_16
NYX	0:85b3fd62ea1a	2883	* @arg @ref LL_RCC_SYSCLK_DIV_64
NYX	0:85b3fd62ea1a	2884	* @arg @ref LL_RCC_SYSCLK_DIV_128
NYX	0:85b3fd62ea1a	2885	* @arg @ref LL_RCC_SYSCLK_DIV_256
NYX	0:85b3fd62ea1a	2886	* @arg @ref LL_RCC_SYSCLK_DIV_512
NYX	0:85b3fd62ea1a	2887	* @retval HCLK clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2888	*/
NYX	0:85b3fd62ea1a	2889	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
NYX	0:85b3fd62ea1a	2890
NYX	0:85b3fd62ea1a	2891	/**
NYX	0:85b3fd62ea1a	2892	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
NYX	0:85b3fd62ea1a	2893	* @param __HCLKFREQ__ HCLK frequency
NYX	0:85b3fd62ea1a	2894	* @param __APB1PRESCALER__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2895	* @arg @ref LL_RCC_APB1_DIV_1
NYX	0:85b3fd62ea1a	2896	* @arg @ref LL_RCC_APB1_DIV_2
NYX	0:85b3fd62ea1a	2897	* @arg @ref LL_RCC_APB1_DIV_4
NYX	0:85b3fd62ea1a	2898	* @arg @ref LL_RCC_APB1_DIV_8
NYX	0:85b3fd62ea1a	2899	* @arg @ref LL_RCC_APB1_DIV_16
NYX	0:85b3fd62ea1a	2900	* @retval PCLK1 clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2901	*/
NYX	0:85b3fd62ea1a	2902	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
NYX	0:85b3fd62ea1a	2903
NYX	0:85b3fd62ea1a	2904	/**
NYX	0:85b3fd62ea1a	2905	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
NYX	0:85b3fd62ea1a	2906	* @param __HCLKFREQ__ HCLK frequency
NYX	0:85b3fd62ea1a	2907	* @param __APB2PRESCALER__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2908	* @arg @ref LL_RCC_APB2_DIV_1
NYX	0:85b3fd62ea1a	2909	* @arg @ref LL_RCC_APB2_DIV_2
NYX	0:85b3fd62ea1a	2910	* @arg @ref LL_RCC_APB2_DIV_4
NYX	0:85b3fd62ea1a	2911	* @arg @ref LL_RCC_APB2_DIV_8
NYX	0:85b3fd62ea1a	2912	* @arg @ref LL_RCC_APB2_DIV_16
NYX	0:85b3fd62ea1a	2913	* @retval PCLK2 clock frequency (in Hz)
NYX	0:85b3fd62ea1a	2914	*/
NYX	0:85b3fd62ea1a	2915	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
NYX	0:85b3fd62ea1a	2916
NYX	0:85b3fd62ea1a	2917	/**
NYX	0:85b3fd62ea1a	2918	* @}
NYX	0:85b3fd62ea1a	2919	*/
NYX	0:85b3fd62ea1a	2920
NYX	0:85b3fd62ea1a	2921	/**
NYX	0:85b3fd62ea1a	2922	* @}
NYX	0:85b3fd62ea1a	2923	*/
NYX	0:85b3fd62ea1a	2924
NYX	0:85b3fd62ea1a	2925	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	2926	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
NYX	0:85b3fd62ea1a	2927	* @{
NYX	0:85b3fd62ea1a	2928	*/
NYX	0:85b3fd62ea1a	2929
NYX	0:85b3fd62ea1a	2930	/** @defgroup RCC_LL_EF_HSE HSE
NYX	0:85b3fd62ea1a	2931	* @{
NYX	0:85b3fd62ea1a	2932	*/
NYX	0:85b3fd62ea1a	2933
NYX	0:85b3fd62ea1a	2934	/**
NYX	0:85b3fd62ea1a	2935	* @brief Enable the Clock Security System.
NYX	0:85b3fd62ea1a	2936	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
NYX	0:85b3fd62ea1a	2937	* @retval None
NYX	0:85b3fd62ea1a	2938	*/
NYX	0:85b3fd62ea1a	2939	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
NYX	0:85b3fd62ea1a	2940	{
NYX	0:85b3fd62ea1a	2941	SET_BIT(RCC->CR, RCC_CR_CSSON);
NYX	0:85b3fd62ea1a	2942	}
NYX	0:85b3fd62ea1a	2943
NYX	0:85b3fd62ea1a	2944	/**
NYX	0:85b3fd62ea1a	2945	* @brief Enable HSE external oscillator (HSE Bypass)
NYX	0:85b3fd62ea1a	2946	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
NYX	0:85b3fd62ea1a	2947	* @retval None
NYX	0:85b3fd62ea1a	2948	*/
NYX	0:85b3fd62ea1a	2949	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
NYX	0:85b3fd62ea1a	2950	{
NYX	0:85b3fd62ea1a	2951	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
NYX	0:85b3fd62ea1a	2952	}
NYX	0:85b3fd62ea1a	2953
NYX	0:85b3fd62ea1a	2954	/**
NYX	0:85b3fd62ea1a	2955	* @brief Disable HSE external oscillator (HSE Bypass)
NYX	0:85b3fd62ea1a	2956	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
NYX	0:85b3fd62ea1a	2957	* @retval None
NYX	0:85b3fd62ea1a	2958	*/
NYX	0:85b3fd62ea1a	2959	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
NYX	0:85b3fd62ea1a	2960	{
NYX	0:85b3fd62ea1a	2961	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
NYX	0:85b3fd62ea1a	2962	}
NYX	0:85b3fd62ea1a	2963
NYX	0:85b3fd62ea1a	2964	/**
NYX	0:85b3fd62ea1a	2965	* @brief Enable HSE crystal oscillator (HSE ON)
NYX	0:85b3fd62ea1a	2966	* @rmtoll CR HSEON LL_RCC_HSE_Enable
NYX	0:85b3fd62ea1a	2967	* @retval None
NYX	0:85b3fd62ea1a	2968	*/
NYX	0:85b3fd62ea1a	2969	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
NYX	0:85b3fd62ea1a	2970	{
NYX	0:85b3fd62ea1a	2971	SET_BIT(RCC->CR, RCC_CR_HSEON);
NYX	0:85b3fd62ea1a	2972	}
NYX	0:85b3fd62ea1a	2973
NYX	0:85b3fd62ea1a	2974	/**
NYX	0:85b3fd62ea1a	2975	* @brief Disable HSE crystal oscillator (HSE ON)
NYX	0:85b3fd62ea1a	2976	* @rmtoll CR HSEON LL_RCC_HSE_Disable
NYX	0:85b3fd62ea1a	2977	* @retval None
NYX	0:85b3fd62ea1a	2978	*/
NYX	0:85b3fd62ea1a	2979	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
NYX	0:85b3fd62ea1a	2980	{
NYX	0:85b3fd62ea1a	2981	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
NYX	0:85b3fd62ea1a	2982	}
NYX	0:85b3fd62ea1a	2983
NYX	0:85b3fd62ea1a	2984	/**
NYX	0:85b3fd62ea1a	2985	* @brief Check if HSE oscillator Ready
NYX	0:85b3fd62ea1a	2986	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
NYX	0:85b3fd62ea1a	2987	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2988	*/
NYX	0:85b3fd62ea1a	2989	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
NYX	0:85b3fd62ea1a	2990	{
NYX	0:85b3fd62ea1a	2991	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
NYX	0:85b3fd62ea1a	2992	}
NYX	0:85b3fd62ea1a	2993
NYX	0:85b3fd62ea1a	2994	/**
NYX	0:85b3fd62ea1a	2995	* @}
NYX	0:85b3fd62ea1a	2996	*/
NYX	0:85b3fd62ea1a	2997
NYX	0:85b3fd62ea1a	2998	/** @defgroup RCC_LL_EF_HSI HSI
NYX	0:85b3fd62ea1a	2999	* @{
NYX	0:85b3fd62ea1a	3000	*/
NYX	0:85b3fd62ea1a	3001
NYX	0:85b3fd62ea1a	3002	/**
NYX	0:85b3fd62ea1a	3003	* @brief Enable HSI oscillator
NYX	0:85b3fd62ea1a	3004	* @rmtoll CR HSION LL_RCC_HSI_Enable
NYX	0:85b3fd62ea1a	3005	* @retval None
NYX	0:85b3fd62ea1a	3006	*/
NYX	0:85b3fd62ea1a	3007	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
NYX	0:85b3fd62ea1a	3008	{
NYX	0:85b3fd62ea1a	3009	SET_BIT(RCC->CR, RCC_CR_HSION);
NYX	0:85b3fd62ea1a	3010	}
NYX	0:85b3fd62ea1a	3011
NYX	0:85b3fd62ea1a	3012	/**
NYX	0:85b3fd62ea1a	3013	* @brief Disable HSI oscillator
NYX	0:85b3fd62ea1a	3014	* @rmtoll CR HSION LL_RCC_HSI_Disable
NYX	0:85b3fd62ea1a	3015	* @retval None
NYX	0:85b3fd62ea1a	3016	*/
NYX	0:85b3fd62ea1a	3017	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
NYX	0:85b3fd62ea1a	3018	{
NYX	0:85b3fd62ea1a	3019	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
NYX	0:85b3fd62ea1a	3020	}
NYX	0:85b3fd62ea1a	3021
NYX	0:85b3fd62ea1a	3022	/**
NYX	0:85b3fd62ea1a	3023	* @brief Check if HSI clock is ready
NYX	0:85b3fd62ea1a	3024	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
NYX	0:85b3fd62ea1a	3025	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3026	*/
NYX	0:85b3fd62ea1a	3027	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
NYX	0:85b3fd62ea1a	3028	{
NYX	0:85b3fd62ea1a	3029	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
NYX	0:85b3fd62ea1a	3030	}
NYX	0:85b3fd62ea1a	3031
NYX	0:85b3fd62ea1a	3032	/**
NYX	0:85b3fd62ea1a	3033	* @brief Get HSI Calibration value
NYX	0:85b3fd62ea1a	3034	* @note When HSITRIM is written, HSICAL is updated with the sum of
NYX	0:85b3fd62ea1a	3035	* HSITRIM and the factory trim value
NYX	0:85b3fd62ea1a	3036	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
NYX	0:85b3fd62ea1a	3037	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
NYX	0:85b3fd62ea1a	3038	*/
NYX	0:85b3fd62ea1a	3039	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
NYX	0:85b3fd62ea1a	3040	{
NYX	0:85b3fd62ea1a	3041	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
NYX	0:85b3fd62ea1a	3042	}
NYX	0:85b3fd62ea1a	3043
NYX	0:85b3fd62ea1a	3044	/**
NYX	0:85b3fd62ea1a	3045	* @brief Set HSI Calibration trimming
NYX	0:85b3fd62ea1a	3046	* @note user-programmable trimming value that is added to the HSICAL
NYX	0:85b3fd62ea1a	3047	* @note Default value is 16, which, when added to the HSICAL value,
NYX	0:85b3fd62ea1a	3048	* should trim the HSI to 16 MHz +/- 1 %
NYX	0:85b3fd62ea1a	3049	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
NYX	0:85b3fd62ea1a	3050	* @param Value Between Min_Data = 0 and Max_Data = 31
NYX	0:85b3fd62ea1a	3051	* @retval None
NYX	0:85b3fd62ea1a	3052	*/
NYX	0:85b3fd62ea1a	3053	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
NYX	0:85b3fd62ea1a	3054	{
NYX	0:85b3fd62ea1a	3055	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
NYX	0:85b3fd62ea1a	3056	}
NYX	0:85b3fd62ea1a	3057
NYX	0:85b3fd62ea1a	3058	/**
NYX	0:85b3fd62ea1a	3059	* @brief Get HSI Calibration trimming
NYX	0:85b3fd62ea1a	3060	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
NYX	0:85b3fd62ea1a	3061	* @retval Between Min_Data = 0 and Max_Data = 31
NYX	0:85b3fd62ea1a	3062	*/
NYX	0:85b3fd62ea1a	3063	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
NYX	0:85b3fd62ea1a	3064	{
NYX	0:85b3fd62ea1a	3065	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
NYX	0:85b3fd62ea1a	3066	}
NYX	0:85b3fd62ea1a	3067
NYX	0:85b3fd62ea1a	3068	/**
NYX	0:85b3fd62ea1a	3069	* @}
NYX	0:85b3fd62ea1a	3070	*/
NYX	0:85b3fd62ea1a	3071
NYX	0:85b3fd62ea1a	3072	/** @defgroup RCC_LL_EF_LSE LSE
NYX	0:85b3fd62ea1a	3073	* @{
NYX	0:85b3fd62ea1a	3074	*/
NYX	0:85b3fd62ea1a	3075
NYX	0:85b3fd62ea1a	3076	/**
NYX	0:85b3fd62ea1a	3077	* @brief Enable Low Speed External (LSE) crystal.
NYX	0:85b3fd62ea1a	3078	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
NYX	0:85b3fd62ea1a	3079	* @retval None
NYX	0:85b3fd62ea1a	3080	*/
NYX	0:85b3fd62ea1a	3081	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
NYX	0:85b3fd62ea1a	3082	{
NYX	0:85b3fd62ea1a	3083	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
NYX	0:85b3fd62ea1a	3084	}
NYX	0:85b3fd62ea1a	3085
NYX	0:85b3fd62ea1a	3086	/**
NYX	0:85b3fd62ea1a	3087	* @brief Disable Low Speed External (LSE) crystal.
NYX	0:85b3fd62ea1a	3088	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
NYX	0:85b3fd62ea1a	3089	* @retval None
NYX	0:85b3fd62ea1a	3090	*/
NYX	0:85b3fd62ea1a	3091	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
NYX	0:85b3fd62ea1a	3092	{
NYX	0:85b3fd62ea1a	3093	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
NYX	0:85b3fd62ea1a	3094	}
NYX	0:85b3fd62ea1a	3095
NYX	0:85b3fd62ea1a	3096	/**
NYX	0:85b3fd62ea1a	3097	* @brief Enable external clock source (LSE bypass).
NYX	0:85b3fd62ea1a	3098	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
NYX	0:85b3fd62ea1a	3099	* @retval None
NYX	0:85b3fd62ea1a	3100	*/
NYX	0:85b3fd62ea1a	3101	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
NYX	0:85b3fd62ea1a	3102	{
NYX	0:85b3fd62ea1a	3103	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
NYX	0:85b3fd62ea1a	3104	}
NYX	0:85b3fd62ea1a	3105
NYX	0:85b3fd62ea1a	3106	/**
NYX	0:85b3fd62ea1a	3107	* @brief Disable external clock source (LSE bypass).
NYX	0:85b3fd62ea1a	3108	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
NYX	0:85b3fd62ea1a	3109	* @retval None
NYX	0:85b3fd62ea1a	3110	*/
NYX	0:85b3fd62ea1a	3111	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
NYX	0:85b3fd62ea1a	3112	{
NYX	0:85b3fd62ea1a	3113	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
NYX	0:85b3fd62ea1a	3114	}
NYX	0:85b3fd62ea1a	3115
NYX	0:85b3fd62ea1a	3116	/**
NYX	0:85b3fd62ea1a	3117	* @brief Check if LSE oscillator Ready
NYX	0:85b3fd62ea1a	3118	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
NYX	0:85b3fd62ea1a	3119	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3120	*/
NYX	0:85b3fd62ea1a	3121	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
NYX	0:85b3fd62ea1a	3122	{
NYX	0:85b3fd62ea1a	3123	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
NYX	0:85b3fd62ea1a	3124	}
NYX	0:85b3fd62ea1a	3125
NYX	0:85b3fd62ea1a	3126	#if defined(RCC_BDCR_LSEMOD)
NYX	0:85b3fd62ea1a	3127	/**
NYX	0:85b3fd62ea1a	3128	* @brief Enable LSE high drive mode.
NYX	0:85b3fd62ea1a	3129	* @note LSE high drive mode can be enabled only when the LSE clock is disabled
NYX	0:85b3fd62ea1a	3130	* @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
NYX	0:85b3fd62ea1a	3131	* @retval None
NYX	0:85b3fd62ea1a	3132	*/
NYX	0:85b3fd62ea1a	3133	__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
NYX	0:85b3fd62ea1a	3134	{
NYX	0:85b3fd62ea1a	3135	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
NYX	0:85b3fd62ea1a	3136	}
NYX	0:85b3fd62ea1a	3137
NYX	0:85b3fd62ea1a	3138	/**
NYX	0:85b3fd62ea1a	3139	* @brief Disable LSE high drive mode.
NYX	0:85b3fd62ea1a	3140	* @note LSE high drive mode can be disabled only when the LSE clock is disabled
NYX	0:85b3fd62ea1a	3141	* @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
NYX	0:85b3fd62ea1a	3142	* @retval None
NYX	0:85b3fd62ea1a	3143	*/
NYX	0:85b3fd62ea1a	3144	__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
NYX	0:85b3fd62ea1a	3145	{
NYX	0:85b3fd62ea1a	3146	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
NYX	0:85b3fd62ea1a	3147	}
NYX	0:85b3fd62ea1a	3148	#endif /* RCC_BDCR_LSEMOD */
NYX	0:85b3fd62ea1a	3149
NYX	0:85b3fd62ea1a	3150	/**
NYX	0:85b3fd62ea1a	3151	* @}
NYX	0:85b3fd62ea1a	3152	*/
NYX	0:85b3fd62ea1a	3153
NYX	0:85b3fd62ea1a	3154	/** @defgroup RCC_LL_EF_LSI LSI
NYX	0:85b3fd62ea1a	3155	* @{
NYX	0:85b3fd62ea1a	3156	*/
NYX	0:85b3fd62ea1a	3157
NYX	0:85b3fd62ea1a	3158	/**
NYX	0:85b3fd62ea1a	3159	* @brief Enable LSI Oscillator
NYX	0:85b3fd62ea1a	3160	* @rmtoll CSR LSION LL_RCC_LSI_Enable
NYX	0:85b3fd62ea1a	3161	* @retval None
NYX	0:85b3fd62ea1a	3162	*/
NYX	0:85b3fd62ea1a	3163	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
NYX	0:85b3fd62ea1a	3164	{
NYX	0:85b3fd62ea1a	3165	SET_BIT(RCC->CSR, RCC_CSR_LSION);
NYX	0:85b3fd62ea1a	3166	}
NYX	0:85b3fd62ea1a	3167
NYX	0:85b3fd62ea1a	3168	/**
NYX	0:85b3fd62ea1a	3169	* @brief Disable LSI Oscillator
NYX	0:85b3fd62ea1a	3170	* @rmtoll CSR LSION LL_RCC_LSI_Disable
NYX	0:85b3fd62ea1a	3171	* @retval None
NYX	0:85b3fd62ea1a	3172	*/
NYX	0:85b3fd62ea1a	3173	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
NYX	0:85b3fd62ea1a	3174	{
NYX	0:85b3fd62ea1a	3175	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
NYX	0:85b3fd62ea1a	3176	}
NYX	0:85b3fd62ea1a	3177
NYX	0:85b3fd62ea1a	3178	/**
NYX	0:85b3fd62ea1a	3179	* @brief Check if LSI is Ready
NYX	0:85b3fd62ea1a	3180	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
NYX	0:85b3fd62ea1a	3181	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	3182	*/
NYX	0:85b3fd62ea1a	3183	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
NYX	0:85b3fd62ea1a	3184	{
NYX	0:85b3fd62ea1a	3185	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
NYX	0:85b3fd62ea1a	3186	}
NYX	0:85b3fd62ea1a	3187
NYX	0:85b3fd62ea1a	3188	/**
NYX	0:85b3fd62ea1a	3189	* @}
NYX	0:85b3fd62ea1a	3190	*/
NYX	0:85b3fd62ea1a	3191
NYX	0:85b3fd62ea1a	3192	/** @defgroup RCC_LL_EF_System System
NYX	0:85b3fd62ea1a	3193	* @{
NYX	0:85b3fd62ea1a	3194	*/
NYX	0:85b3fd62ea1a	3195
NYX	0:85b3fd62ea1a	3196	/**
NYX	0:85b3fd62ea1a	3197	* @brief Configure the system clock source
NYX	0:85b3fd62ea1a	3198	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
NYX	0:85b3fd62ea1a	3199	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3200	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
NYX	0:85b3fd62ea1a	3201	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
NYX	0:85b3fd62ea1a	3202	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3203	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
NYX	0:85b3fd62ea1a	3204	*
NYX	0:85b3fd62ea1a	3205	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3206	* @retval None
NYX	0:85b3fd62ea1a	3207	*/
NYX	0:85b3fd62ea1a	3208	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
NYX	0:85b3fd62ea1a	3209	{
NYX	0:85b3fd62ea1a	3210	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
NYX	0:85b3fd62ea1a	3211	}
NYX	0:85b3fd62ea1a	3212
NYX	0:85b3fd62ea1a	3213	/**
NYX	0:85b3fd62ea1a	3214	* @brief Get the system clock source
NYX	0:85b3fd62ea1a	3215	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
NYX	0:85b3fd62ea1a	3216	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3217	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
NYX	0:85b3fd62ea1a	3218	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
NYX	0:85b3fd62ea1a	3219	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
NYX	0:85b3fd62ea1a	3220	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
NYX	0:85b3fd62ea1a	3221	*
NYX	0:85b3fd62ea1a	3222	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3223	*/
NYX	0:85b3fd62ea1a	3224	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
NYX	0:85b3fd62ea1a	3225	{
NYX	0:85b3fd62ea1a	3226	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
NYX	0:85b3fd62ea1a	3227	}
NYX	0:85b3fd62ea1a	3228
NYX	0:85b3fd62ea1a	3229	/**
NYX	0:85b3fd62ea1a	3230	* @brief Set AHB prescaler
NYX	0:85b3fd62ea1a	3231	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
NYX	0:85b3fd62ea1a	3232	* @param Prescaler This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3233	* @arg @ref LL_RCC_SYSCLK_DIV_1
NYX	0:85b3fd62ea1a	3234	* @arg @ref LL_RCC_SYSCLK_DIV_2
NYX	0:85b3fd62ea1a	3235	* @arg @ref LL_RCC_SYSCLK_DIV_4
NYX	0:85b3fd62ea1a	3236	* @arg @ref LL_RCC_SYSCLK_DIV_8
NYX	0:85b3fd62ea1a	3237	* @arg @ref LL_RCC_SYSCLK_DIV_16
NYX	0:85b3fd62ea1a	3238	* @arg @ref LL_RCC_SYSCLK_DIV_64
NYX	0:85b3fd62ea1a	3239	* @arg @ref LL_RCC_SYSCLK_DIV_128
NYX	0:85b3fd62ea1a	3240	* @arg @ref LL_RCC_SYSCLK_DIV_256
NYX	0:85b3fd62ea1a	3241	* @arg @ref LL_RCC_SYSCLK_DIV_512
NYX	0:85b3fd62ea1a	3242	* @retval None
NYX	0:85b3fd62ea1a	3243	*/
NYX	0:85b3fd62ea1a	3244	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
NYX	0:85b3fd62ea1a	3245	{
NYX	0:85b3fd62ea1a	3246	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
NYX	0:85b3fd62ea1a	3247	}
NYX	0:85b3fd62ea1a	3248
NYX	0:85b3fd62ea1a	3249	/**
NYX	0:85b3fd62ea1a	3250	* @brief Set APB1 prescaler
NYX	0:85b3fd62ea1a	3251	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
NYX	0:85b3fd62ea1a	3252	* @param Prescaler This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3253	* @arg @ref LL_RCC_APB1_DIV_1
NYX	0:85b3fd62ea1a	3254	* @arg @ref LL_RCC_APB1_DIV_2
NYX	0:85b3fd62ea1a	3255	* @arg @ref LL_RCC_APB1_DIV_4
NYX	0:85b3fd62ea1a	3256	* @arg @ref LL_RCC_APB1_DIV_8
NYX	0:85b3fd62ea1a	3257	* @arg @ref LL_RCC_APB1_DIV_16
NYX	0:85b3fd62ea1a	3258	* @retval None
NYX	0:85b3fd62ea1a	3259	*/
NYX	0:85b3fd62ea1a	3260	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
NYX	0:85b3fd62ea1a	3261	{
NYX	0:85b3fd62ea1a	3262	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
NYX	0:85b3fd62ea1a	3263	}
NYX	0:85b3fd62ea1a	3264
NYX	0:85b3fd62ea1a	3265	/**
NYX	0:85b3fd62ea1a	3266	* @brief Set APB2 prescaler
NYX	0:85b3fd62ea1a	3267	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
NYX	0:85b3fd62ea1a	3268	* @param Prescaler This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3269	* @arg @ref LL_RCC_APB2_DIV_1
NYX	0:85b3fd62ea1a	3270	* @arg @ref LL_RCC_APB2_DIV_2
NYX	0:85b3fd62ea1a	3271	* @arg @ref LL_RCC_APB2_DIV_4
NYX	0:85b3fd62ea1a	3272	* @arg @ref LL_RCC_APB2_DIV_8
NYX	0:85b3fd62ea1a	3273	* @arg @ref LL_RCC_APB2_DIV_16
NYX	0:85b3fd62ea1a	3274	* @retval None
NYX	0:85b3fd62ea1a	3275	*/
NYX	0:85b3fd62ea1a	3276	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
NYX	0:85b3fd62ea1a	3277	{
NYX	0:85b3fd62ea1a	3278	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
NYX	0:85b3fd62ea1a	3279	}
NYX	0:85b3fd62ea1a	3280
NYX	0:85b3fd62ea1a	3281	/**
NYX	0:85b3fd62ea1a	3282	* @brief Get AHB prescaler
NYX	0:85b3fd62ea1a	3283	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
NYX	0:85b3fd62ea1a	3284	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3285	* @arg @ref LL_RCC_SYSCLK_DIV_1
NYX	0:85b3fd62ea1a	3286	* @arg @ref LL_RCC_SYSCLK_DIV_2
NYX	0:85b3fd62ea1a	3287	* @arg @ref LL_RCC_SYSCLK_DIV_4
NYX	0:85b3fd62ea1a	3288	* @arg @ref LL_RCC_SYSCLK_DIV_8
NYX	0:85b3fd62ea1a	3289	* @arg @ref LL_RCC_SYSCLK_DIV_16
NYX	0:85b3fd62ea1a	3290	* @arg @ref LL_RCC_SYSCLK_DIV_64
NYX	0:85b3fd62ea1a	3291	* @arg @ref LL_RCC_SYSCLK_DIV_128
NYX	0:85b3fd62ea1a	3292	* @arg @ref LL_RCC_SYSCLK_DIV_256
NYX	0:85b3fd62ea1a	3293	* @arg @ref LL_RCC_SYSCLK_DIV_512
NYX	0:85b3fd62ea1a	3294	*/
NYX	0:85b3fd62ea1a	3295	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
NYX	0:85b3fd62ea1a	3296	{
NYX	0:85b3fd62ea1a	3297	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
NYX	0:85b3fd62ea1a	3298	}
NYX	0:85b3fd62ea1a	3299
NYX	0:85b3fd62ea1a	3300	/**
NYX	0:85b3fd62ea1a	3301	* @brief Get APB1 prescaler
NYX	0:85b3fd62ea1a	3302	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
NYX	0:85b3fd62ea1a	3303	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3304	* @arg @ref LL_RCC_APB1_DIV_1
NYX	0:85b3fd62ea1a	3305	* @arg @ref LL_RCC_APB1_DIV_2
NYX	0:85b3fd62ea1a	3306	* @arg @ref LL_RCC_APB1_DIV_4
NYX	0:85b3fd62ea1a	3307	* @arg @ref LL_RCC_APB1_DIV_8
NYX	0:85b3fd62ea1a	3308	* @arg @ref LL_RCC_APB1_DIV_16
NYX	0:85b3fd62ea1a	3309	*/
NYX	0:85b3fd62ea1a	3310	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
NYX	0:85b3fd62ea1a	3311	{
NYX	0:85b3fd62ea1a	3312	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
NYX	0:85b3fd62ea1a	3313	}
NYX	0:85b3fd62ea1a	3314
NYX	0:85b3fd62ea1a	3315	/**
NYX	0:85b3fd62ea1a	3316	* @brief Get APB2 prescaler
NYX	0:85b3fd62ea1a	3317	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
NYX	0:85b3fd62ea1a	3318	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3319	* @arg @ref LL_RCC_APB2_DIV_1
NYX	0:85b3fd62ea1a	3320	* @arg @ref LL_RCC_APB2_DIV_2
NYX	0:85b3fd62ea1a	3321	* @arg @ref LL_RCC_APB2_DIV_4
NYX	0:85b3fd62ea1a	3322	* @arg @ref LL_RCC_APB2_DIV_8
NYX	0:85b3fd62ea1a	3323	* @arg @ref LL_RCC_APB2_DIV_16
NYX	0:85b3fd62ea1a	3324	*/
NYX	0:85b3fd62ea1a	3325	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
NYX	0:85b3fd62ea1a	3326	{
NYX	0:85b3fd62ea1a	3327	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
NYX	0:85b3fd62ea1a	3328	}
NYX	0:85b3fd62ea1a	3329
NYX	0:85b3fd62ea1a	3330	/**
NYX	0:85b3fd62ea1a	3331	* @}
NYX	0:85b3fd62ea1a	3332	*/
NYX	0:85b3fd62ea1a	3333
NYX	0:85b3fd62ea1a	3334	/** @defgroup RCC_LL_EF_MCO MCO
NYX	0:85b3fd62ea1a	3335	* @{
NYX	0:85b3fd62ea1a	3336	*/
NYX	0:85b3fd62ea1a	3337
NYX	0:85b3fd62ea1a	3338	#if defined(RCC_CFGR_MCO1EN)
NYX	0:85b3fd62ea1a	3339	/**
NYX	0:85b3fd62ea1a	3340	* @brief Enable MCO1 output
NYX	0:85b3fd62ea1a	3341	* @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
NYX	0:85b3fd62ea1a	3342	* @retval None
NYX	0:85b3fd62ea1a	3343	*/
NYX	0:85b3fd62ea1a	3344	__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
NYX	0:85b3fd62ea1a	3345	{
NYX	0:85b3fd62ea1a	3346	SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
NYX	0:85b3fd62ea1a	3347	}
NYX	0:85b3fd62ea1a	3348
NYX	0:85b3fd62ea1a	3349	/**
NYX	0:85b3fd62ea1a	3350	* @brief Disable MCO1 output
NYX	0:85b3fd62ea1a	3351	* @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
NYX	0:85b3fd62ea1a	3352	* @retval None
NYX	0:85b3fd62ea1a	3353	*/
NYX	0:85b3fd62ea1a	3354	__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
NYX	0:85b3fd62ea1a	3355	{
NYX	0:85b3fd62ea1a	3356	CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
NYX	0:85b3fd62ea1a	3357	}
NYX	0:85b3fd62ea1a	3358	#endif /* RCC_CFGR_MCO1EN */
NYX	0:85b3fd62ea1a	3359
NYX	0:85b3fd62ea1a	3360	#if defined(RCC_CFGR_MCO2EN)
NYX	0:85b3fd62ea1a	3361	/**
NYX	0:85b3fd62ea1a	3362	* @brief Enable MCO2 output
NYX	0:85b3fd62ea1a	3363	* @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
NYX	0:85b3fd62ea1a	3364	* @retval None
NYX	0:85b3fd62ea1a	3365	*/
NYX	0:85b3fd62ea1a	3366	__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
NYX	0:85b3fd62ea1a	3367	{
NYX	0:85b3fd62ea1a	3368	SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
NYX	0:85b3fd62ea1a	3369	}
NYX	0:85b3fd62ea1a	3370
NYX	0:85b3fd62ea1a	3371	/**
NYX	0:85b3fd62ea1a	3372	* @brief Disable MCO2 output
NYX	0:85b3fd62ea1a	3373	* @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
NYX	0:85b3fd62ea1a	3374	* @retval None
NYX	0:85b3fd62ea1a	3375	*/
NYX	0:85b3fd62ea1a	3376	__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
NYX	0:85b3fd62ea1a	3377	{
NYX	0:85b3fd62ea1a	3378	CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
NYX	0:85b3fd62ea1a	3379	}
NYX	0:85b3fd62ea1a	3380	#endif /* RCC_CFGR_MCO2EN */
NYX	0:85b3fd62ea1a	3381
NYX	0:85b3fd62ea1a	3382	/**
NYX	0:85b3fd62ea1a	3383	* @brief Configure MCOx
NYX	0:85b3fd62ea1a	3384	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
NYX	0:85b3fd62ea1a	3385	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
NYX	0:85b3fd62ea1a	3386	* CFGR MCO2 LL_RCC_ConfigMCO\n
NYX	0:85b3fd62ea1a	3387	* CFGR MCO2PRE LL_RCC_ConfigMCO
NYX	0:85b3fd62ea1a	3388	* @param MCOxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3389	* @arg @ref LL_RCC_MCO1SOURCE_HSI
NYX	0:85b3fd62ea1a	3390	* @arg @ref LL_RCC_MCO1SOURCE_LSE
NYX	0:85b3fd62ea1a	3391	* @arg @ref LL_RCC_MCO1SOURCE_HSE
NYX	0:85b3fd62ea1a	3392	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
NYX	0:85b3fd62ea1a	3393	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
NYX	0:85b3fd62ea1a	3394	* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
NYX	0:85b3fd62ea1a	3395	* @arg @ref LL_RCC_MCO2SOURCE_HSE
NYX	0:85b3fd62ea1a	3396	* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
NYX	0:85b3fd62ea1a	3397	* @param MCOxPrescaler This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3398	* @arg @ref LL_RCC_MCO1_DIV_1
NYX	0:85b3fd62ea1a	3399	* @arg @ref LL_RCC_MCO1_DIV_2
NYX	0:85b3fd62ea1a	3400	* @arg @ref LL_RCC_MCO1_DIV_3
NYX	0:85b3fd62ea1a	3401	* @arg @ref LL_RCC_MCO1_DIV_4
NYX	0:85b3fd62ea1a	3402	* @arg @ref LL_RCC_MCO1_DIV_5
NYX	0:85b3fd62ea1a	3403	* @arg @ref LL_RCC_MCO2_DIV_1
NYX	0:85b3fd62ea1a	3404	* @arg @ref LL_RCC_MCO2_DIV_2
NYX	0:85b3fd62ea1a	3405	* @arg @ref LL_RCC_MCO2_DIV_3
NYX	0:85b3fd62ea1a	3406	* @arg @ref LL_RCC_MCO2_DIV_4
NYX	0:85b3fd62ea1a	3407	* @arg @ref LL_RCC_MCO2_DIV_5
NYX	0:85b3fd62ea1a	3408	* @retval None
NYX	0:85b3fd62ea1a	3409	*/
NYX	0:85b3fd62ea1a	3410	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
NYX	0:85b3fd62ea1a	3411	{
NYX	0:85b3fd62ea1a	3412	MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) \| (MCOxPrescaler << 16U));
NYX	0:85b3fd62ea1a	3413	}
NYX	0:85b3fd62ea1a	3414
NYX	0:85b3fd62ea1a	3415	/**
NYX	0:85b3fd62ea1a	3416	* @}
NYX	0:85b3fd62ea1a	3417	*/
NYX	0:85b3fd62ea1a	3418
NYX	0:85b3fd62ea1a	3419	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
NYX	0:85b3fd62ea1a	3420	* @{
NYX	0:85b3fd62ea1a	3421	*/
NYX	0:85b3fd62ea1a	3422	#if defined(FMPI2C1)
NYX	0:85b3fd62ea1a	3423	/**
NYX	0:85b3fd62ea1a	3424	* @brief Configure FMPI2C clock source
NYX	0:85b3fd62ea1a	3425	* @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
NYX	0:85b3fd62ea1a	3426	* @param FMPI2CxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3427	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
NYX	0:85b3fd62ea1a	3428	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	3429	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
NYX	0:85b3fd62ea1a	3430	* @retval None
NYX	0:85b3fd62ea1a	3431	*/
NYX	0:85b3fd62ea1a	3432	__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
NYX	0:85b3fd62ea1a	3433	{
NYX	0:85b3fd62ea1a	3434	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
NYX	0:85b3fd62ea1a	3435	}
NYX	0:85b3fd62ea1a	3436	#endif /* FMPI2C1 */
NYX	0:85b3fd62ea1a	3437
NYX	0:85b3fd62ea1a	3438	#if defined(LPTIM1)
NYX	0:85b3fd62ea1a	3439	/**
NYX	0:85b3fd62ea1a	3440	* @brief Configure LPTIMx clock source
NYX	0:85b3fd62ea1a	3441	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
NYX	0:85b3fd62ea1a	3442	* @param LPTIMxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3443	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
NYX	0:85b3fd62ea1a	3444	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
NYX	0:85b3fd62ea1a	3445	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
NYX	0:85b3fd62ea1a	3446	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
NYX	0:85b3fd62ea1a	3447	* @retval None
NYX	0:85b3fd62ea1a	3448	*/
NYX	0:85b3fd62ea1a	3449	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
NYX	0:85b3fd62ea1a	3450	{
NYX	0:85b3fd62ea1a	3451	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
NYX	0:85b3fd62ea1a	3452	}
NYX	0:85b3fd62ea1a	3453	#endif /* LPTIM1 */
NYX	0:85b3fd62ea1a	3454
NYX	0:85b3fd62ea1a	3455	#if defined(SAI1)
NYX	0:85b3fd62ea1a	3456	/**
NYX	0:85b3fd62ea1a	3457	* @brief Configure SAIx clock source
NYX	0:85b3fd62ea1a	3458	* @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
NYX	0:85b3fd62ea1a	3459	* DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
NYX	0:85b3fd62ea1a	3460	* DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
NYX	0:85b3fd62ea1a	3461	* DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
NYX	0:85b3fd62ea1a	3462	* @param SAIxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3463	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3464	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3465	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3466	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	3467	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3468	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3469	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3470	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3471	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3472	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3473	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	3474	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3475	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3476	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3477	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3478	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	3479	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3480	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3481	*
NYX	0:85b3fd62ea1a	3482	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3483	* @retval None
NYX	0:85b3fd62ea1a	3484	*/
NYX	0:85b3fd62ea1a	3485	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
NYX	0:85b3fd62ea1a	3486	{
NYX	0:85b3fd62ea1a	3487	MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
NYX	0:85b3fd62ea1a	3488	}
NYX	0:85b3fd62ea1a	3489	#endif /* SAI1 */
NYX	0:85b3fd62ea1a	3490
NYX	0:85b3fd62ea1a	3491	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
NYX	0:85b3fd62ea1a	3492	/**
NYX	0:85b3fd62ea1a	3493	* @brief Configure SDIO clock source
NYX	0:85b3fd62ea1a	3494	* @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
NYX	0:85b3fd62ea1a	3495	* DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
NYX	0:85b3fd62ea1a	3496	* @param SDIOxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3497	* @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
NYX	0:85b3fd62ea1a	3498	* @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	3499	* @retval None
NYX	0:85b3fd62ea1a	3500	*/
NYX	0:85b3fd62ea1a	3501	__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
NYX	0:85b3fd62ea1a	3502	{
NYX	0:85b3fd62ea1a	3503	#if defined(RCC_DCKCFGR_SDIOSEL)
NYX	0:85b3fd62ea1a	3504	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
NYX	0:85b3fd62ea1a	3505	#else
NYX	0:85b3fd62ea1a	3506	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
NYX	0:85b3fd62ea1a	3507	#endif /* RCC_DCKCFGR_SDIOSEL */
NYX	0:85b3fd62ea1a	3508	}
NYX	0:85b3fd62ea1a	3509	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
NYX	0:85b3fd62ea1a	3510
NYX	0:85b3fd62ea1a	3511	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	3512	/**
NYX	0:85b3fd62ea1a	3513	* @brief Configure 48Mhz domain clock source
NYX	0:85b3fd62ea1a	3514	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
NYX	0:85b3fd62ea1a	3515	* DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
NYX	0:85b3fd62ea1a	3516	* @param CK48MxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3517	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3518	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3519	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3520	*
NYX	0:85b3fd62ea1a	3521	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3522	* @retval None
NYX	0:85b3fd62ea1a	3523	*/
NYX	0:85b3fd62ea1a	3524	__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
NYX	0:85b3fd62ea1a	3525	{
NYX	0:85b3fd62ea1a	3526	#if defined(RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	3527	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
NYX	0:85b3fd62ea1a	3528	#else
NYX	0:85b3fd62ea1a	3529	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
NYX	0:85b3fd62ea1a	3530	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	3531	}
NYX	0:85b3fd62ea1a	3532
NYX	0:85b3fd62ea1a	3533	#if defined(RNG)
NYX	0:85b3fd62ea1a	3534	/**
NYX	0:85b3fd62ea1a	3535	* @brief Configure RNG clock source
NYX	0:85b3fd62ea1a	3536	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
NYX	0:85b3fd62ea1a	3537	* DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
NYX	0:85b3fd62ea1a	3538	* @param RNGxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3539	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3540	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3541	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3542	*
NYX	0:85b3fd62ea1a	3543	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3544	* @retval None
NYX	0:85b3fd62ea1a	3545	*/
NYX	0:85b3fd62ea1a	3546	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
NYX	0:85b3fd62ea1a	3547	{
NYX	0:85b3fd62ea1a	3548	#if defined(RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	3549	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
NYX	0:85b3fd62ea1a	3550	#else
NYX	0:85b3fd62ea1a	3551	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
NYX	0:85b3fd62ea1a	3552	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	3553	}
NYX	0:85b3fd62ea1a	3554	#endif /* RNG */
NYX	0:85b3fd62ea1a	3555
NYX	0:85b3fd62ea1a	3556	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
NYX	0:85b3fd62ea1a	3557	/**
NYX	0:85b3fd62ea1a	3558	* @brief Configure USB clock source
NYX	0:85b3fd62ea1a	3559	* @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
NYX	0:85b3fd62ea1a	3560	* DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
NYX	0:85b3fd62ea1a	3561	* @param USBxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3562	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3563	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3564	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3565	*
NYX	0:85b3fd62ea1a	3566	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3567	* @retval None
NYX	0:85b3fd62ea1a	3568	*/
NYX	0:85b3fd62ea1a	3569	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
NYX	0:85b3fd62ea1a	3570	{
NYX	0:85b3fd62ea1a	3571	#if defined(RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	3572	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
NYX	0:85b3fd62ea1a	3573	#else
NYX	0:85b3fd62ea1a	3574	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
NYX	0:85b3fd62ea1a	3575	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	3576	}
NYX	0:85b3fd62ea1a	3577	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
NYX	0:85b3fd62ea1a	3578	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
NYX	0:85b3fd62ea1a	3579
NYX	0:85b3fd62ea1a	3580	#if defined(CEC)
NYX	0:85b3fd62ea1a	3581	/**
NYX	0:85b3fd62ea1a	3582	* @brief Configure CEC clock source
NYX	0:85b3fd62ea1a	3583	* @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
NYX	0:85b3fd62ea1a	3584	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3585	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
NYX	0:85b3fd62ea1a	3586	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
NYX	0:85b3fd62ea1a	3587	* @retval None
NYX	0:85b3fd62ea1a	3588	*/
NYX	0:85b3fd62ea1a	3589	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
NYX	0:85b3fd62ea1a	3590	{
NYX	0:85b3fd62ea1a	3591	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
NYX	0:85b3fd62ea1a	3592	}
NYX	0:85b3fd62ea1a	3593	#endif /* CEC */
NYX	0:85b3fd62ea1a	3594
NYX	0:85b3fd62ea1a	3595	/**
NYX	0:85b3fd62ea1a	3596	* @brief Configure I2S clock source
NYX	0:85b3fd62ea1a	3597	* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
NYX	0:85b3fd62ea1a	3598	* DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
NYX	0:85b3fd62ea1a	3599	* DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
NYX	0:85b3fd62ea1a	3600	* DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
NYX	0:85b3fd62ea1a	3601	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3602	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3603	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
NYX	0:85b3fd62ea1a	3604	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3605	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3606	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3607	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	3608	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3609	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3610	*
NYX	0:85b3fd62ea1a	3611	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3612	* @retval None
NYX	0:85b3fd62ea1a	3613	*/
NYX	0:85b3fd62ea1a	3614	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
NYX	0:85b3fd62ea1a	3615	{
NYX	0:85b3fd62ea1a	3616	#if defined(RCC_CFGR_I2SSRC)
NYX	0:85b3fd62ea1a	3617	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
NYX	0:85b3fd62ea1a	3618	#else
NYX	0:85b3fd62ea1a	3619	MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
NYX	0:85b3fd62ea1a	3620	#endif /* RCC_CFGR_I2SSRC */
NYX	0:85b3fd62ea1a	3621	}
NYX	0:85b3fd62ea1a	3622
NYX	0:85b3fd62ea1a	3623	#if defined(DSI)
NYX	0:85b3fd62ea1a	3624	/**
NYX	0:85b3fd62ea1a	3625	* @brief Configure DSI clock source
NYX	0:85b3fd62ea1a	3626	* @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
NYX	0:85b3fd62ea1a	3627	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3628	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
NYX	0:85b3fd62ea1a	3629	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3630	* @retval None
NYX	0:85b3fd62ea1a	3631	*/
NYX	0:85b3fd62ea1a	3632	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
NYX	0:85b3fd62ea1a	3633	{
NYX	0:85b3fd62ea1a	3634	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
NYX	0:85b3fd62ea1a	3635	}
NYX	0:85b3fd62ea1a	3636	#endif /* DSI */
NYX	0:85b3fd62ea1a	3637
NYX	0:85b3fd62ea1a	3638	#if defined(DFSDM1_Channel0)
NYX	0:85b3fd62ea1a	3639	/**
NYX	0:85b3fd62ea1a	3640	* @brief Configure DFSDM Audio clock source
NYX	0:85b3fd62ea1a	3641	* @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
NYX	0:85b3fd62ea1a	3642	* DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
NYX	0:85b3fd62ea1a	3643	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3644	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
NYX	0:85b3fd62ea1a	3645	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
NYX	0:85b3fd62ea1a	3646	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
NYX	0:85b3fd62ea1a	3647	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
NYX	0:85b3fd62ea1a	3648	*
NYX	0:85b3fd62ea1a	3649	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3650	* @retval None
NYX	0:85b3fd62ea1a	3651	*/
NYX	0:85b3fd62ea1a	3652	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
NYX	0:85b3fd62ea1a	3653	{
NYX	0:85b3fd62ea1a	3654	MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
NYX	0:85b3fd62ea1a	3655	}
NYX	0:85b3fd62ea1a	3656
NYX	0:85b3fd62ea1a	3657	/**
NYX	0:85b3fd62ea1a	3658	* @brief Configure DFSDM Kernel clock source
NYX	0:85b3fd62ea1a	3659	* @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
NYX	0:85b3fd62ea1a	3660	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3661	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
NYX	0:85b3fd62ea1a	3662	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	3663	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
NYX	0:85b3fd62ea1a	3664	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
NYX	0:85b3fd62ea1a	3665	*
NYX	0:85b3fd62ea1a	3666	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3667	* @retval None
NYX	0:85b3fd62ea1a	3668	*/
NYX	0:85b3fd62ea1a	3669	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
NYX	0:85b3fd62ea1a	3670	{
NYX	0:85b3fd62ea1a	3671	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
NYX	0:85b3fd62ea1a	3672	}
NYX	0:85b3fd62ea1a	3673	#endif /* DFSDM1_Channel0 */
NYX	0:85b3fd62ea1a	3674
NYX	0:85b3fd62ea1a	3675	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	3676	/**
NYX	0:85b3fd62ea1a	3677	* @brief Configure SPDIFRX clock source
NYX	0:85b3fd62ea1a	3678	* @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
NYX	0:85b3fd62ea1a	3679	* @param SPDIFRXxSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3680	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3681	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
NYX	0:85b3fd62ea1a	3682	*
NYX	0:85b3fd62ea1a	3683	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3684	* @retval None
NYX	0:85b3fd62ea1a	3685	*/
NYX	0:85b3fd62ea1a	3686	__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
NYX	0:85b3fd62ea1a	3687	{
NYX	0:85b3fd62ea1a	3688	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
NYX	0:85b3fd62ea1a	3689	}
NYX	0:85b3fd62ea1a	3690	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	3691
NYX	0:85b3fd62ea1a	3692	#if defined(FMPI2C1)
NYX	0:85b3fd62ea1a	3693	/**
NYX	0:85b3fd62ea1a	3694	* @brief Get FMPI2C clock source
NYX	0:85b3fd62ea1a	3695	* @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
NYX	0:85b3fd62ea1a	3696	* @param FMPI2Cx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3697	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
NYX	0:85b3fd62ea1a	3698	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3699	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
NYX	0:85b3fd62ea1a	3700	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	3701	* @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
NYX	0:85b3fd62ea1a	3702	*/
NYX	0:85b3fd62ea1a	3703	__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
NYX	0:85b3fd62ea1a	3704	{
NYX	0:85b3fd62ea1a	3705	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
NYX	0:85b3fd62ea1a	3706	}
NYX	0:85b3fd62ea1a	3707	#endif /* FMPI2C1 */
NYX	0:85b3fd62ea1a	3708
NYX	0:85b3fd62ea1a	3709	#if defined(LPTIM1)
NYX	0:85b3fd62ea1a	3710	/**
NYX	0:85b3fd62ea1a	3711	* @brief Get LPTIMx clock source
NYX	0:85b3fd62ea1a	3712	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
NYX	0:85b3fd62ea1a	3713	* @param LPTIMx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3714	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
NYX	0:85b3fd62ea1a	3715	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3716	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
NYX	0:85b3fd62ea1a	3717	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
NYX	0:85b3fd62ea1a	3718	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
NYX	0:85b3fd62ea1a	3719	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
NYX	0:85b3fd62ea1a	3720	*/
NYX	0:85b3fd62ea1a	3721	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
NYX	0:85b3fd62ea1a	3722	{
NYX	0:85b3fd62ea1a	3723	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
NYX	0:85b3fd62ea1a	3724	}
NYX	0:85b3fd62ea1a	3725	#endif /* LPTIM1 */
NYX	0:85b3fd62ea1a	3726
NYX	0:85b3fd62ea1a	3727	#if defined(SAI1)
NYX	0:85b3fd62ea1a	3728	/**
NYX	0:85b3fd62ea1a	3729	* @brief Get SAIx clock source
NYX	0:85b3fd62ea1a	3730	* @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
NYX	0:85b3fd62ea1a	3731	* DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
NYX	0:85b3fd62ea1a	3732	* DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
NYX	0:85b3fd62ea1a	3733	* DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
NYX	0:85b3fd62ea1a	3734	* @param SAIx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3735	* @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
NYX	0:85b3fd62ea1a	3736	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
NYX	0:85b3fd62ea1a	3737	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
NYX	0:85b3fd62ea1a	3738	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
NYX	0:85b3fd62ea1a	3739	*
NYX	0:85b3fd62ea1a	3740	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3741	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3742	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3743	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3744	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3745	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	3746	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3747	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3748	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3749	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3750	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3751	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3752	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	3753	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3754	* @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3755	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3756	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3757	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	3758	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3759	* @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3760	*
NYX	0:85b3fd62ea1a	3761	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3762	*/
NYX	0:85b3fd62ea1a	3763	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
NYX	0:85b3fd62ea1a	3764	{
NYX	0:85b3fd62ea1a	3765	return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U \| SAIx);
NYX	0:85b3fd62ea1a	3766	}
NYX	0:85b3fd62ea1a	3767	#endif /* SAI1 */
NYX	0:85b3fd62ea1a	3768
NYX	0:85b3fd62ea1a	3769	#if defined(RCC_DCKCFGR_SDIOSEL) \|\| defined(RCC_DCKCFGR2_SDIOSEL)
NYX	0:85b3fd62ea1a	3770	/**
NYX	0:85b3fd62ea1a	3771	* @brief Get SDIOx clock source
NYX	0:85b3fd62ea1a	3772	* @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
NYX	0:85b3fd62ea1a	3773	* DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
NYX	0:85b3fd62ea1a	3774	* @param SDIOx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3775	* @arg @ref LL_RCC_SDIO_CLKSOURCE
NYX	0:85b3fd62ea1a	3776	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3777	* @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
NYX	0:85b3fd62ea1a	3778	* @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	3779	*/
NYX	0:85b3fd62ea1a	3780	__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
NYX	0:85b3fd62ea1a	3781	{
NYX	0:85b3fd62ea1a	3782	#if defined(RCC_DCKCFGR_SDIOSEL)
NYX	0:85b3fd62ea1a	3783	return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
NYX	0:85b3fd62ea1a	3784	#else
NYX	0:85b3fd62ea1a	3785	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
NYX	0:85b3fd62ea1a	3786	#endif /* RCC_DCKCFGR_SDIOSEL */
NYX	0:85b3fd62ea1a	3787	}
NYX	0:85b3fd62ea1a	3788	#endif /* RCC_DCKCFGR_SDIOSEL \|\| RCC_DCKCFGR2_SDIOSEL */
NYX	0:85b3fd62ea1a	3789
NYX	0:85b3fd62ea1a	3790	#if defined(RCC_DCKCFGR_CK48MSEL) \|\| defined(RCC_DCKCFGR2_CK48MSEL)
NYX	0:85b3fd62ea1a	3791	/**
NYX	0:85b3fd62ea1a	3792	* @brief Get 48Mhz domain clock source
NYX	0:85b3fd62ea1a	3793	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
NYX	0:85b3fd62ea1a	3794	* DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
NYX	0:85b3fd62ea1a	3795	* @param CK48Mx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3796	* @arg @ref LL_RCC_CK48M_CLKSOURCE
NYX	0:85b3fd62ea1a	3797	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3798	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3799	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3800	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3801	*
NYX	0:85b3fd62ea1a	3802	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3803	*/
NYX	0:85b3fd62ea1a	3804	__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
NYX	0:85b3fd62ea1a	3805	{
NYX	0:85b3fd62ea1a	3806	#if defined(RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	3807	return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
NYX	0:85b3fd62ea1a	3808	#else
NYX	0:85b3fd62ea1a	3809	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
NYX	0:85b3fd62ea1a	3810	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	3811	}
NYX	0:85b3fd62ea1a	3812
NYX	0:85b3fd62ea1a	3813	#if defined(RNG)
NYX	0:85b3fd62ea1a	3814	/**
NYX	0:85b3fd62ea1a	3815	* @brief Get RNGx clock source
NYX	0:85b3fd62ea1a	3816	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
NYX	0:85b3fd62ea1a	3817	* DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
NYX	0:85b3fd62ea1a	3818	* @param RNGx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3819	* @arg @ref LL_RCC_RNG_CLKSOURCE
NYX	0:85b3fd62ea1a	3820	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3821	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3822	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3823	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3824	*
NYX	0:85b3fd62ea1a	3825	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3826	*/
NYX	0:85b3fd62ea1a	3827	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
NYX	0:85b3fd62ea1a	3828	{
NYX	0:85b3fd62ea1a	3829	#if defined(RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	3830	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
NYX	0:85b3fd62ea1a	3831	#else
NYX	0:85b3fd62ea1a	3832	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
NYX	0:85b3fd62ea1a	3833	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	3834	}
NYX	0:85b3fd62ea1a	3835	#endif /* RNG */
NYX	0:85b3fd62ea1a	3836
NYX	0:85b3fd62ea1a	3837	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
NYX	0:85b3fd62ea1a	3838	/**
NYX	0:85b3fd62ea1a	3839	* @brief Get USBx clock source
NYX	0:85b3fd62ea1a	3840	* @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
NYX	0:85b3fd62ea1a	3841	* DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
NYX	0:85b3fd62ea1a	3842	* @param USBx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3843	* @arg @ref LL_RCC_USB_CLKSOURCE
NYX	0:85b3fd62ea1a	3844	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3845	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3846	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
NYX	0:85b3fd62ea1a	3847	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3848	*
NYX	0:85b3fd62ea1a	3849	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3850	*/
NYX	0:85b3fd62ea1a	3851	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
NYX	0:85b3fd62ea1a	3852	{
NYX	0:85b3fd62ea1a	3853	#if defined(RCC_DCKCFGR_CK48MSEL)
NYX	0:85b3fd62ea1a	3854	return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
NYX	0:85b3fd62ea1a	3855	#else
NYX	0:85b3fd62ea1a	3856	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
NYX	0:85b3fd62ea1a	3857	#endif /* RCC_DCKCFGR_CK48MSEL */
NYX	0:85b3fd62ea1a	3858	}
NYX	0:85b3fd62ea1a	3859	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
NYX	0:85b3fd62ea1a	3860	#endif /* RCC_DCKCFGR_CK48MSEL \|\| RCC_DCKCFGR2_CK48MSEL */
NYX	0:85b3fd62ea1a	3861
NYX	0:85b3fd62ea1a	3862	#if defined(CEC)
NYX	0:85b3fd62ea1a	3863	/**
NYX	0:85b3fd62ea1a	3864	* @brief Get CEC Clock Source
NYX	0:85b3fd62ea1a	3865	* @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
NYX	0:85b3fd62ea1a	3866	* @param CECx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3867	* @arg @ref LL_RCC_CEC_CLKSOURCE
NYX	0:85b3fd62ea1a	3868	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3869	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
NYX	0:85b3fd62ea1a	3870	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
NYX	0:85b3fd62ea1a	3871	*/
NYX	0:85b3fd62ea1a	3872	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
NYX	0:85b3fd62ea1a	3873	{
NYX	0:85b3fd62ea1a	3874	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
NYX	0:85b3fd62ea1a	3875	}
NYX	0:85b3fd62ea1a	3876	#endif /* CEC */
NYX	0:85b3fd62ea1a	3877
NYX	0:85b3fd62ea1a	3878	/**
NYX	0:85b3fd62ea1a	3879	* @brief Get I2S Clock Source
NYX	0:85b3fd62ea1a	3880	* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
NYX	0:85b3fd62ea1a	3881	* DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
NYX	0:85b3fd62ea1a	3882	* DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
NYX	0:85b3fd62ea1a	3883	* DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
NYX	0:85b3fd62ea1a	3884	* @param I2Sx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3885	* @arg @ref LL_RCC_I2S1_CLKSOURCE
NYX	0:85b3fd62ea1a	3886	* @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
NYX	0:85b3fd62ea1a	3887	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3888	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3889	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
NYX	0:85b3fd62ea1a	3890	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3891	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3892	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
NYX	0:85b3fd62ea1a	3893	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	3894	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
NYX	0:85b3fd62ea1a	3895	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
NYX	0:85b3fd62ea1a	3896	*
NYX	0:85b3fd62ea1a	3897	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3898	*/
NYX	0:85b3fd62ea1a	3899	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
NYX	0:85b3fd62ea1a	3900	{
NYX	0:85b3fd62ea1a	3901	#if defined(RCC_CFGR_I2SSRC)
NYX	0:85b3fd62ea1a	3902	return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
NYX	0:85b3fd62ea1a	3903	#else
NYX	0:85b3fd62ea1a	3904	return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U \| I2Sx);
NYX	0:85b3fd62ea1a	3905	#endif /* RCC_CFGR_I2SSRC */
NYX	0:85b3fd62ea1a	3906	}
NYX	0:85b3fd62ea1a	3907
NYX	0:85b3fd62ea1a	3908	#if defined(DFSDM1_Channel0)
NYX	0:85b3fd62ea1a	3909	/**
NYX	0:85b3fd62ea1a	3910	* @brief Get DFSDM Audio Clock Source
NYX	0:85b3fd62ea1a	3911	* @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
NYX	0:85b3fd62ea1a	3912	* DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
NYX	0:85b3fd62ea1a	3913	* @param DFSDMx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3914	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
NYX	0:85b3fd62ea1a	3915	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
NYX	0:85b3fd62ea1a	3916	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3917	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
NYX	0:85b3fd62ea1a	3918	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
NYX	0:85b3fd62ea1a	3919	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
NYX	0:85b3fd62ea1a	3920	* @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
NYX	0:85b3fd62ea1a	3921	*
NYX	0:85b3fd62ea1a	3922	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3923	*/
NYX	0:85b3fd62ea1a	3924	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
NYX	0:85b3fd62ea1a	3925	{
NYX	0:85b3fd62ea1a	3926	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U \| DFSDMx);
NYX	0:85b3fd62ea1a	3927	}
NYX	0:85b3fd62ea1a	3928
NYX	0:85b3fd62ea1a	3929	/**
NYX	0:85b3fd62ea1a	3930	* @brief Get DFSDM Audio Clock Source
NYX	0:85b3fd62ea1a	3931	* @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
NYX	0:85b3fd62ea1a	3932	* @param DFSDMx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3933	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
NYX	0:85b3fd62ea1a	3934	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
NYX	0:85b3fd62ea1a	3935	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3936	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
NYX	0:85b3fd62ea1a	3937	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
NYX	0:85b3fd62ea1a	3938	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
NYX	0:85b3fd62ea1a	3939	* @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
NYX	0:85b3fd62ea1a	3940	*
NYX	0:85b3fd62ea1a	3941	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3942	*/
NYX	0:85b3fd62ea1a	3943	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
NYX	0:85b3fd62ea1a	3944	{
NYX	0:85b3fd62ea1a	3945	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
NYX	0:85b3fd62ea1a	3946	}
NYX	0:85b3fd62ea1a	3947	#endif /* DFSDM1_Channel0 */
NYX	0:85b3fd62ea1a	3948
NYX	0:85b3fd62ea1a	3949	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	3950	/**
NYX	0:85b3fd62ea1a	3951	* @brief Get SPDIFRX clock source
NYX	0:85b3fd62ea1a	3952	* @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
NYX	0:85b3fd62ea1a	3953	* @param SPDIFRXx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3954	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
NYX	0:85b3fd62ea1a	3955	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3956	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3957	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
NYX	0:85b3fd62ea1a	3958	*
NYX	0:85b3fd62ea1a	3959	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	3960	*/
NYX	0:85b3fd62ea1a	3961	__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
NYX	0:85b3fd62ea1a	3962	{
NYX	0:85b3fd62ea1a	3963	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
NYX	0:85b3fd62ea1a	3964	}
NYX	0:85b3fd62ea1a	3965	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	3966
NYX	0:85b3fd62ea1a	3967	#if defined(DSI)
NYX	0:85b3fd62ea1a	3968	/**
NYX	0:85b3fd62ea1a	3969	* @brief Get DSI Clock Source
NYX	0:85b3fd62ea1a	3970	* @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
NYX	0:85b3fd62ea1a	3971	* @param DSIx This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3972	* @arg @ref LL_RCC_DSI_CLKSOURCE
NYX	0:85b3fd62ea1a	3973	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	3974	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
NYX	0:85b3fd62ea1a	3975	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
NYX	0:85b3fd62ea1a	3976	*/
NYX	0:85b3fd62ea1a	3977	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
NYX	0:85b3fd62ea1a	3978	{
NYX	0:85b3fd62ea1a	3979	return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
NYX	0:85b3fd62ea1a	3980	}
NYX	0:85b3fd62ea1a	3981	#endif /* DSI */
NYX	0:85b3fd62ea1a	3982
NYX	0:85b3fd62ea1a	3983	/**
NYX	0:85b3fd62ea1a	3984	* @}
NYX	0:85b3fd62ea1a	3985	*/
NYX	0:85b3fd62ea1a	3986
NYX	0:85b3fd62ea1a	3987	/** @defgroup RCC_LL_EF_RTC RTC
NYX	0:85b3fd62ea1a	3988	* @{
NYX	0:85b3fd62ea1a	3989	*/
NYX	0:85b3fd62ea1a	3990
NYX	0:85b3fd62ea1a	3991	/**
NYX	0:85b3fd62ea1a	3992	* @brief Set RTC Clock Source
NYX	0:85b3fd62ea1a	3993	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
NYX	0:85b3fd62ea1a	3994	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
NYX	0:85b3fd62ea1a	3995	* set). The BDRST bit can be used to reset them.
NYX	0:85b3fd62ea1a	3996	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
NYX	0:85b3fd62ea1a	3997	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	3998	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
NYX	0:85b3fd62ea1a	3999	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
NYX	0:85b3fd62ea1a	4000	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
NYX	0:85b3fd62ea1a	4001	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
NYX	0:85b3fd62ea1a	4002	* @retval None
NYX	0:85b3fd62ea1a	4003	*/
NYX	0:85b3fd62ea1a	4004	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
NYX	0:85b3fd62ea1a	4005	{
NYX	0:85b3fd62ea1a	4006	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
NYX	0:85b3fd62ea1a	4007	}
NYX	0:85b3fd62ea1a	4008
NYX	0:85b3fd62ea1a	4009	/**
NYX	0:85b3fd62ea1a	4010	* @brief Get RTC Clock Source
NYX	0:85b3fd62ea1a	4011	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
NYX	0:85b3fd62ea1a	4012	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4013	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
NYX	0:85b3fd62ea1a	4014	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
NYX	0:85b3fd62ea1a	4015	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
NYX	0:85b3fd62ea1a	4016	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
NYX	0:85b3fd62ea1a	4017	*/
NYX	0:85b3fd62ea1a	4018	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
NYX	0:85b3fd62ea1a	4019	{
NYX	0:85b3fd62ea1a	4020	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
NYX	0:85b3fd62ea1a	4021	}
NYX	0:85b3fd62ea1a	4022
NYX	0:85b3fd62ea1a	4023	/**
NYX	0:85b3fd62ea1a	4024	* @brief Enable RTC
NYX	0:85b3fd62ea1a	4025	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
NYX	0:85b3fd62ea1a	4026	* @retval None
NYX	0:85b3fd62ea1a	4027	*/
NYX	0:85b3fd62ea1a	4028	__STATIC_INLINE void LL_RCC_EnableRTC(void)
NYX	0:85b3fd62ea1a	4029	{
NYX	0:85b3fd62ea1a	4030	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
NYX	0:85b3fd62ea1a	4031	}
NYX	0:85b3fd62ea1a	4032
NYX	0:85b3fd62ea1a	4033	/**
NYX	0:85b3fd62ea1a	4034	* @brief Disable RTC
NYX	0:85b3fd62ea1a	4035	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
NYX	0:85b3fd62ea1a	4036	* @retval None
NYX	0:85b3fd62ea1a	4037	*/
NYX	0:85b3fd62ea1a	4038	__STATIC_INLINE void LL_RCC_DisableRTC(void)
NYX	0:85b3fd62ea1a	4039	{
NYX	0:85b3fd62ea1a	4040	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
NYX	0:85b3fd62ea1a	4041	}
NYX	0:85b3fd62ea1a	4042
NYX	0:85b3fd62ea1a	4043	/**
NYX	0:85b3fd62ea1a	4044	* @brief Check if RTC has been enabled or not
NYX	0:85b3fd62ea1a	4045	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
NYX	0:85b3fd62ea1a	4046	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	4047	*/
NYX	0:85b3fd62ea1a	4048	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
NYX	0:85b3fd62ea1a	4049	{
NYX	0:85b3fd62ea1a	4050	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
NYX	0:85b3fd62ea1a	4051	}
NYX	0:85b3fd62ea1a	4052
NYX	0:85b3fd62ea1a	4053	/**
NYX	0:85b3fd62ea1a	4054	* @brief Force the Backup domain reset
NYX	0:85b3fd62ea1a	4055	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
NYX	0:85b3fd62ea1a	4056	* @retval None
NYX	0:85b3fd62ea1a	4057	*/
NYX	0:85b3fd62ea1a	4058	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
NYX	0:85b3fd62ea1a	4059	{
NYX	0:85b3fd62ea1a	4060	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
NYX	0:85b3fd62ea1a	4061	}
NYX	0:85b3fd62ea1a	4062
NYX	0:85b3fd62ea1a	4063	/**
NYX	0:85b3fd62ea1a	4064	* @brief Release the Backup domain reset
NYX	0:85b3fd62ea1a	4065	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
NYX	0:85b3fd62ea1a	4066	* @retval None
NYX	0:85b3fd62ea1a	4067	*/
NYX	0:85b3fd62ea1a	4068	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
NYX	0:85b3fd62ea1a	4069	{
NYX	0:85b3fd62ea1a	4070	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
NYX	0:85b3fd62ea1a	4071	}
NYX	0:85b3fd62ea1a	4072
NYX	0:85b3fd62ea1a	4073	/**
NYX	0:85b3fd62ea1a	4074	* @brief Set HSE Prescalers for RTC Clock
NYX	0:85b3fd62ea1a	4075	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
NYX	0:85b3fd62ea1a	4076	* @param Prescaler This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4077	* @arg @ref LL_RCC_RTC_NOCLOCK
NYX	0:85b3fd62ea1a	4078	* @arg @ref LL_RCC_RTC_HSE_DIV_2
NYX	0:85b3fd62ea1a	4079	* @arg @ref LL_RCC_RTC_HSE_DIV_3
NYX	0:85b3fd62ea1a	4080	* @arg @ref LL_RCC_RTC_HSE_DIV_4
NYX	0:85b3fd62ea1a	4081	* @arg @ref LL_RCC_RTC_HSE_DIV_5
NYX	0:85b3fd62ea1a	4082	* @arg @ref LL_RCC_RTC_HSE_DIV_6
NYX	0:85b3fd62ea1a	4083	* @arg @ref LL_RCC_RTC_HSE_DIV_7
NYX	0:85b3fd62ea1a	4084	* @arg @ref LL_RCC_RTC_HSE_DIV_8
NYX	0:85b3fd62ea1a	4085	* @arg @ref LL_RCC_RTC_HSE_DIV_9
NYX	0:85b3fd62ea1a	4086	* @arg @ref LL_RCC_RTC_HSE_DIV_10
NYX	0:85b3fd62ea1a	4087	* @arg @ref LL_RCC_RTC_HSE_DIV_11
NYX	0:85b3fd62ea1a	4088	* @arg @ref LL_RCC_RTC_HSE_DIV_12
NYX	0:85b3fd62ea1a	4089	* @arg @ref LL_RCC_RTC_HSE_DIV_13
NYX	0:85b3fd62ea1a	4090	* @arg @ref LL_RCC_RTC_HSE_DIV_14
NYX	0:85b3fd62ea1a	4091	* @arg @ref LL_RCC_RTC_HSE_DIV_15
NYX	0:85b3fd62ea1a	4092	* @arg @ref LL_RCC_RTC_HSE_DIV_16
NYX	0:85b3fd62ea1a	4093	* @arg @ref LL_RCC_RTC_HSE_DIV_17
NYX	0:85b3fd62ea1a	4094	* @arg @ref LL_RCC_RTC_HSE_DIV_18
NYX	0:85b3fd62ea1a	4095	* @arg @ref LL_RCC_RTC_HSE_DIV_19
NYX	0:85b3fd62ea1a	4096	* @arg @ref LL_RCC_RTC_HSE_DIV_20
NYX	0:85b3fd62ea1a	4097	* @arg @ref LL_RCC_RTC_HSE_DIV_21
NYX	0:85b3fd62ea1a	4098	* @arg @ref LL_RCC_RTC_HSE_DIV_22
NYX	0:85b3fd62ea1a	4099	* @arg @ref LL_RCC_RTC_HSE_DIV_23
NYX	0:85b3fd62ea1a	4100	* @arg @ref LL_RCC_RTC_HSE_DIV_24
NYX	0:85b3fd62ea1a	4101	* @arg @ref LL_RCC_RTC_HSE_DIV_25
NYX	0:85b3fd62ea1a	4102	* @arg @ref LL_RCC_RTC_HSE_DIV_26
NYX	0:85b3fd62ea1a	4103	* @arg @ref LL_RCC_RTC_HSE_DIV_27
NYX	0:85b3fd62ea1a	4104	* @arg @ref LL_RCC_RTC_HSE_DIV_28
NYX	0:85b3fd62ea1a	4105	* @arg @ref LL_RCC_RTC_HSE_DIV_29
NYX	0:85b3fd62ea1a	4106	* @arg @ref LL_RCC_RTC_HSE_DIV_30
NYX	0:85b3fd62ea1a	4107	* @arg @ref LL_RCC_RTC_HSE_DIV_31
NYX	0:85b3fd62ea1a	4108	* @retval None
NYX	0:85b3fd62ea1a	4109	*/
NYX	0:85b3fd62ea1a	4110	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
NYX	0:85b3fd62ea1a	4111	{
NYX	0:85b3fd62ea1a	4112	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
NYX	0:85b3fd62ea1a	4113	}
NYX	0:85b3fd62ea1a	4114
NYX	0:85b3fd62ea1a	4115	/**
NYX	0:85b3fd62ea1a	4116	* @brief Get HSE Prescalers for RTC Clock
NYX	0:85b3fd62ea1a	4117	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
NYX	0:85b3fd62ea1a	4118	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4119	* @arg @ref LL_RCC_RTC_NOCLOCK
NYX	0:85b3fd62ea1a	4120	* @arg @ref LL_RCC_RTC_HSE_DIV_2
NYX	0:85b3fd62ea1a	4121	* @arg @ref LL_RCC_RTC_HSE_DIV_3
NYX	0:85b3fd62ea1a	4122	* @arg @ref LL_RCC_RTC_HSE_DIV_4
NYX	0:85b3fd62ea1a	4123	* @arg @ref LL_RCC_RTC_HSE_DIV_5
NYX	0:85b3fd62ea1a	4124	* @arg @ref LL_RCC_RTC_HSE_DIV_6
NYX	0:85b3fd62ea1a	4125	* @arg @ref LL_RCC_RTC_HSE_DIV_7
NYX	0:85b3fd62ea1a	4126	* @arg @ref LL_RCC_RTC_HSE_DIV_8
NYX	0:85b3fd62ea1a	4127	* @arg @ref LL_RCC_RTC_HSE_DIV_9
NYX	0:85b3fd62ea1a	4128	* @arg @ref LL_RCC_RTC_HSE_DIV_10
NYX	0:85b3fd62ea1a	4129	* @arg @ref LL_RCC_RTC_HSE_DIV_11
NYX	0:85b3fd62ea1a	4130	* @arg @ref LL_RCC_RTC_HSE_DIV_12
NYX	0:85b3fd62ea1a	4131	* @arg @ref LL_RCC_RTC_HSE_DIV_13
NYX	0:85b3fd62ea1a	4132	* @arg @ref LL_RCC_RTC_HSE_DIV_14
NYX	0:85b3fd62ea1a	4133	* @arg @ref LL_RCC_RTC_HSE_DIV_15
NYX	0:85b3fd62ea1a	4134	* @arg @ref LL_RCC_RTC_HSE_DIV_16
NYX	0:85b3fd62ea1a	4135	* @arg @ref LL_RCC_RTC_HSE_DIV_17
NYX	0:85b3fd62ea1a	4136	* @arg @ref LL_RCC_RTC_HSE_DIV_18
NYX	0:85b3fd62ea1a	4137	* @arg @ref LL_RCC_RTC_HSE_DIV_19
NYX	0:85b3fd62ea1a	4138	* @arg @ref LL_RCC_RTC_HSE_DIV_20
NYX	0:85b3fd62ea1a	4139	* @arg @ref LL_RCC_RTC_HSE_DIV_21
NYX	0:85b3fd62ea1a	4140	* @arg @ref LL_RCC_RTC_HSE_DIV_22
NYX	0:85b3fd62ea1a	4141	* @arg @ref LL_RCC_RTC_HSE_DIV_23
NYX	0:85b3fd62ea1a	4142	* @arg @ref LL_RCC_RTC_HSE_DIV_24
NYX	0:85b3fd62ea1a	4143	* @arg @ref LL_RCC_RTC_HSE_DIV_25
NYX	0:85b3fd62ea1a	4144	* @arg @ref LL_RCC_RTC_HSE_DIV_26
NYX	0:85b3fd62ea1a	4145	* @arg @ref LL_RCC_RTC_HSE_DIV_27
NYX	0:85b3fd62ea1a	4146	* @arg @ref LL_RCC_RTC_HSE_DIV_28
NYX	0:85b3fd62ea1a	4147	* @arg @ref LL_RCC_RTC_HSE_DIV_29
NYX	0:85b3fd62ea1a	4148	* @arg @ref LL_RCC_RTC_HSE_DIV_30
NYX	0:85b3fd62ea1a	4149	* @arg @ref LL_RCC_RTC_HSE_DIV_31
NYX	0:85b3fd62ea1a	4150	*/
NYX	0:85b3fd62ea1a	4151	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
NYX	0:85b3fd62ea1a	4152	{
NYX	0:85b3fd62ea1a	4153	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
NYX	0:85b3fd62ea1a	4154	}
NYX	0:85b3fd62ea1a	4155
NYX	0:85b3fd62ea1a	4156	/**
NYX	0:85b3fd62ea1a	4157	* @}
NYX	0:85b3fd62ea1a	4158	*/
NYX	0:85b3fd62ea1a	4159
NYX	0:85b3fd62ea1a	4160	#if defined(RCC_DCKCFGR_TIMPRE)
NYX	0:85b3fd62ea1a	4161	/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
NYX	0:85b3fd62ea1a	4162	* @{
NYX	0:85b3fd62ea1a	4163	*/
NYX	0:85b3fd62ea1a	4164
NYX	0:85b3fd62ea1a	4165	/**
NYX	0:85b3fd62ea1a	4166	* @brief Set Timers Clock Prescalers
NYX	0:85b3fd62ea1a	4167	* @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
NYX	0:85b3fd62ea1a	4168	* @param Prescaler This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4169	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
NYX	0:85b3fd62ea1a	4170	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
NYX	0:85b3fd62ea1a	4171	* @retval None
NYX	0:85b3fd62ea1a	4172	*/
NYX	0:85b3fd62ea1a	4173	__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
NYX	0:85b3fd62ea1a	4174	{
NYX	0:85b3fd62ea1a	4175	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
NYX	0:85b3fd62ea1a	4176	}
NYX	0:85b3fd62ea1a	4177
NYX	0:85b3fd62ea1a	4178	/**
NYX	0:85b3fd62ea1a	4179	* @brief Get Timers Clock Prescalers
NYX	0:85b3fd62ea1a	4180	* @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
NYX	0:85b3fd62ea1a	4181	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4182	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
NYX	0:85b3fd62ea1a	4183	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
NYX	0:85b3fd62ea1a	4184	*/
NYX	0:85b3fd62ea1a	4185	__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
NYX	0:85b3fd62ea1a	4186	{
NYX	0:85b3fd62ea1a	4187	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
NYX	0:85b3fd62ea1a	4188	}
NYX	0:85b3fd62ea1a	4189
NYX	0:85b3fd62ea1a	4190	/**
NYX	0:85b3fd62ea1a	4191	* @}
NYX	0:85b3fd62ea1a	4192	*/
NYX	0:85b3fd62ea1a	4193	#endif /* RCC_DCKCFGR_TIMPRE */
NYX	0:85b3fd62ea1a	4194
NYX	0:85b3fd62ea1a	4195	/** @defgroup RCC_LL_EF_PLL PLL
NYX	0:85b3fd62ea1a	4196	* @{
NYX	0:85b3fd62ea1a	4197	*/
NYX	0:85b3fd62ea1a	4198
NYX	0:85b3fd62ea1a	4199	/**
NYX	0:85b3fd62ea1a	4200	* @brief Enable PLL
NYX	0:85b3fd62ea1a	4201	* @rmtoll CR PLLON LL_RCC_PLL_Enable
NYX	0:85b3fd62ea1a	4202	* @retval None
NYX	0:85b3fd62ea1a	4203	*/
NYX	0:85b3fd62ea1a	4204	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
NYX	0:85b3fd62ea1a	4205	{
NYX	0:85b3fd62ea1a	4206	SET_BIT(RCC->CR, RCC_CR_PLLON);
NYX	0:85b3fd62ea1a	4207	}
NYX	0:85b3fd62ea1a	4208
NYX	0:85b3fd62ea1a	4209	/**
NYX	0:85b3fd62ea1a	4210	* @brief Disable PLL
NYX	0:85b3fd62ea1a	4211	* @note Cannot be disabled if the PLL clock is used as the system clock
NYX	0:85b3fd62ea1a	4212	* @rmtoll CR PLLON LL_RCC_PLL_Disable
NYX	0:85b3fd62ea1a	4213	* @retval None
NYX	0:85b3fd62ea1a	4214	*/
NYX	0:85b3fd62ea1a	4215	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
NYX	0:85b3fd62ea1a	4216	{
NYX	0:85b3fd62ea1a	4217	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
NYX	0:85b3fd62ea1a	4218	}
NYX	0:85b3fd62ea1a	4219
NYX	0:85b3fd62ea1a	4220	/**
NYX	0:85b3fd62ea1a	4221	* @brief Check if PLL Ready
NYX	0:85b3fd62ea1a	4222	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
NYX	0:85b3fd62ea1a	4223	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	4224	*/
NYX	0:85b3fd62ea1a	4225	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
NYX	0:85b3fd62ea1a	4226	{
NYX	0:85b3fd62ea1a	4227	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
NYX	0:85b3fd62ea1a	4228	}
NYX	0:85b3fd62ea1a	4229
NYX	0:85b3fd62ea1a	4230	/**
NYX	0:85b3fd62ea1a	4231	* @brief Configure PLL used for SYSCLK Domain
NYX	0:85b3fd62ea1a	4232	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	4233	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	4234	* @note PLLN/PLLP can be written only when PLL is disabled
NYX	0:85b3fd62ea1a	4235	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
NYX	0:85b3fd62ea1a	4236	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
NYX	0:85b3fd62ea1a	4237	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
NYX	0:85b3fd62ea1a	4238	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
NYX	0:85b3fd62ea1a	4239	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
NYX	0:85b3fd62ea1a	4240	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4241	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	4242	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	4243	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4244	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	4245	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	4246	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	4247	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	4248	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	4249	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	4250	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	4251	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	4252	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	4253	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	4254	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	4255	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	4256	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	4257	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	4258	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	4259	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	4260	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	4261	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	4262	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	4263	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	4264	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	4265	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	4266	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	4267	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	4268	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	4269	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	4270	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	4271	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	4272	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	4273	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	4274	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	4275	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	4276	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	4277	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	4278	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	4279	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	4280	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	4281	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	4282	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	4283	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	4284	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	4285	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	4286	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	4287	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	4288	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	4289	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	4290	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	4291	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	4292	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	4293	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	4294	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	4295	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	4296	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	4297	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	4298	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	4299	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	4300	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	4301	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	4302	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	4303	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	4304	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	4305	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	4306	* @param PLLN Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	4307	*
NYX	0:85b3fd62ea1a	4308	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	4309	* @param PLLP_R This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4310	* @arg @ref LL_RCC_PLLP_DIV_2
NYX	0:85b3fd62ea1a	4311	* @arg @ref LL_RCC_PLLP_DIV_4
NYX	0:85b3fd62ea1a	4312	* @arg @ref LL_RCC_PLLP_DIV_6
NYX	0:85b3fd62ea1a	4313	* @arg @ref LL_RCC_PLLP_DIV_8
NYX	0:85b3fd62ea1a	4314	* @arg @ref LL_RCC_PLLR_DIV_2 (*)
NYX	0:85b3fd62ea1a	4315	* @arg @ref LL_RCC_PLLR_DIV_3 (*)
NYX	0:85b3fd62ea1a	4316	* @arg @ref LL_RCC_PLLR_DIV_4 (*)
NYX	0:85b3fd62ea1a	4317	* @arg @ref LL_RCC_PLLR_DIV_5 (*)
NYX	0:85b3fd62ea1a	4318	* @arg @ref LL_RCC_PLLR_DIV_6 (*)
NYX	0:85b3fd62ea1a	4319	* @arg @ref LL_RCC_PLLR_DIV_7 (*)
NYX	0:85b3fd62ea1a	4320	*
NYX	0:85b3fd62ea1a	4321	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	4322	* @retval None
NYX	0:85b3fd62ea1a	4323	*/
NYX	0:85b3fd62ea1a	4324	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
NYX	0:85b3fd62ea1a	4325	{
NYX	0:85b3fd62ea1a	4326	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN,
NYX	0:85b3fd62ea1a	4327	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos);
NYX	0:85b3fd62ea1a	4328	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
NYX	0:85b3fd62ea1a	4329	#if defined(RCC_PLLR_SYSCLK_SUPPORT)
NYX	0:85b3fd62ea1a	4330	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
NYX	0:85b3fd62ea1a	4331	#endif /* RCC_PLLR_SYSCLK_SUPPORT */
NYX	0:85b3fd62ea1a	4332	}
NYX	0:85b3fd62ea1a	4333
NYX	0:85b3fd62ea1a	4334	/**
NYX	0:85b3fd62ea1a	4335	* @brief Configure PLL used for 48Mhz domain clock
NYX	0:85b3fd62ea1a	4336	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	4337	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	4338	* @note PLLN/PLLQ can be written only when PLL is disabled
NYX	0:85b3fd62ea1a	4339	* @note This can be selected for USB, RNG, SDIO
NYX	0:85b3fd62ea1a	4340	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	4341	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	4342	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	4343	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
NYX	0:85b3fd62ea1a	4344	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4345	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	4346	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	4347	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4348	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	4349	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	4350	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	4351	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	4352	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	4353	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	4354	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	4355	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	4356	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	4357	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	4358	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	4359	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	4360	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	4361	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	4362	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	4363	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	4364	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	4365	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	4366	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	4367	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	4368	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	4369	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	4370	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	4371	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	4372	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	4373	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	4374	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	4375	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	4376	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	4377	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	4378	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	4379	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	4380	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	4381	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	4382	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	4383	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	4384	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	4385	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	4386	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	4387	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	4388	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	4389	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	4390	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	4391	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	4392	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	4393	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	4394	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	4395	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	4396	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	4397	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	4398	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	4399	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	4400	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	4401	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	4402	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	4403	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	4404	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	4405	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	4406	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	4407	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	4408	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	4409	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	4410	* @param PLLN Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	4411	*
NYX	0:85b3fd62ea1a	4412	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	4413	* @param PLLQ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4414	* @arg @ref LL_RCC_PLLQ_DIV_2
NYX	0:85b3fd62ea1a	4415	* @arg @ref LL_RCC_PLLQ_DIV_3
NYX	0:85b3fd62ea1a	4416	* @arg @ref LL_RCC_PLLQ_DIV_4
NYX	0:85b3fd62ea1a	4417	* @arg @ref LL_RCC_PLLQ_DIV_5
NYX	0:85b3fd62ea1a	4418	* @arg @ref LL_RCC_PLLQ_DIV_6
NYX	0:85b3fd62ea1a	4419	* @arg @ref LL_RCC_PLLQ_DIV_7
NYX	0:85b3fd62ea1a	4420	* @arg @ref LL_RCC_PLLQ_DIV_8
NYX	0:85b3fd62ea1a	4421	* @arg @ref LL_RCC_PLLQ_DIV_9
NYX	0:85b3fd62ea1a	4422	* @arg @ref LL_RCC_PLLQ_DIV_10
NYX	0:85b3fd62ea1a	4423	* @arg @ref LL_RCC_PLLQ_DIV_11
NYX	0:85b3fd62ea1a	4424	* @arg @ref LL_RCC_PLLQ_DIV_12
NYX	0:85b3fd62ea1a	4425	* @arg @ref LL_RCC_PLLQ_DIV_13
NYX	0:85b3fd62ea1a	4426	* @arg @ref LL_RCC_PLLQ_DIV_14
NYX	0:85b3fd62ea1a	4427	* @arg @ref LL_RCC_PLLQ_DIV_15
NYX	0:85b3fd62ea1a	4428	* @retval None
NYX	0:85b3fd62ea1a	4429	*/
NYX	0:85b3fd62ea1a	4430	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
NYX	0:85b3fd62ea1a	4431	{
NYX	0:85b3fd62ea1a	4432	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
NYX	0:85b3fd62ea1a	4433	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
NYX	0:85b3fd62ea1a	4434	}
NYX	0:85b3fd62ea1a	4435
NYX	0:85b3fd62ea1a	4436	#if defined(DSI)
NYX	0:85b3fd62ea1a	4437	/**
NYX	0:85b3fd62ea1a	4438	* @brief Configure PLL used for DSI clock
NYX	0:85b3fd62ea1a	4439	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	4440	* PLLI2S and PLLSAI are disabled
NYX	0:85b3fd62ea1a	4441	* @note PLLN/PLLR can be written only when PLL is disabled
NYX	0:85b3fd62ea1a	4442	* @note This can be selected for DSI
NYX	0:85b3fd62ea1a	4443	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
NYX	0:85b3fd62ea1a	4444	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
NYX	0:85b3fd62ea1a	4445	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
NYX	0:85b3fd62ea1a	4446	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
NYX	0:85b3fd62ea1a	4447	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4448	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	4449	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	4450	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4451	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	4452	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	4453	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	4454	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	4455	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	4456	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	4457	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	4458	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	4459	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	4460	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	4461	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	4462	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	4463	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	4464	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	4465	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	4466	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	4467	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	4468	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	4469	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	4470	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	4471	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	4472	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	4473	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	4474	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	4475	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	4476	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	4477	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	4478	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	4479	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	4480	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	4481	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	4482	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	4483	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	4484	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	4485	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	4486	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	4487	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	4488	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	4489	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	4490	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	4491	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	4492	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	4493	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	4494	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	4495	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	4496	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	4497	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	4498	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	4499	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	4500	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	4501	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	4502	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	4503	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	4504	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	4505	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	4506	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	4507	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	4508	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	4509	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	4510	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	4511	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	4512	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	4513	* @param PLLN Between 50 and 432
NYX	0:85b3fd62ea1a	4514	* @param PLLR This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4515	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	4516	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	4517	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	4518	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	4519	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	4520	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	4521	* @retval None
NYX	0:85b3fd62ea1a	4522	*/
NYX	0:85b3fd62ea1a	4523	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
NYX	0:85b3fd62ea1a	4524	{
NYX	0:85b3fd62ea1a	4525	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
NYX	0:85b3fd62ea1a	4526	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
NYX	0:85b3fd62ea1a	4527	}
NYX	0:85b3fd62ea1a	4528	#endif /* DSI */
NYX	0:85b3fd62ea1a	4529
NYX	0:85b3fd62ea1a	4530	#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
NYX	0:85b3fd62ea1a	4531	/**
NYX	0:85b3fd62ea1a	4532	* @brief Configure PLL used for I2S clock
NYX	0:85b3fd62ea1a	4533	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	4534	* PLLI2S and PLLSAI are disabled
NYX	0:85b3fd62ea1a	4535	* @note PLLN/PLLR can be written only when PLL is disabled
NYX	0:85b3fd62ea1a	4536	* @note This can be selected for I2S
NYX	0:85b3fd62ea1a	4537	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
NYX	0:85b3fd62ea1a	4538	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
NYX	0:85b3fd62ea1a	4539	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
NYX	0:85b3fd62ea1a	4540	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
NYX	0:85b3fd62ea1a	4541	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4542	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	4543	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	4544	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4545	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	4546	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	4547	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	4548	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	4549	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	4550	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	4551	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	4552	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	4553	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	4554	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	4555	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	4556	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	4557	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	4558	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	4559	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	4560	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	4561	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	4562	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	4563	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	4564	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	4565	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	4566	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	4567	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	4568	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	4569	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	4570	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	4571	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	4572	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	4573	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	4574	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	4575	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	4576	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	4577	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	4578	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	4579	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	4580	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	4581	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	4582	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	4583	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	4584	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	4585	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	4586	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	4587	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	4588	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	4589	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	4590	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	4591	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	4592	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	4593	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	4594	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	4595	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	4596	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	4597	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	4598	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	4599	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	4600	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	4601	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	4602	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	4603	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	4604	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	4605	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	4606	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	4607	* @param PLLN Between 50 and 432
NYX	0:85b3fd62ea1a	4608	* @param PLLR This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4609	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	4610	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	4611	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	4612	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	4613	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	4614	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	4615	* @retval None
NYX	0:85b3fd62ea1a	4616	*/
NYX	0:85b3fd62ea1a	4617	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
NYX	0:85b3fd62ea1a	4618	{
NYX	0:85b3fd62ea1a	4619	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
NYX	0:85b3fd62ea1a	4620	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
NYX	0:85b3fd62ea1a	4621	}
NYX	0:85b3fd62ea1a	4622	#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
NYX	0:85b3fd62ea1a	4623
NYX	0:85b3fd62ea1a	4624	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	4625	/**
NYX	0:85b3fd62ea1a	4626	* @brief Configure PLL used for SPDIFRX clock
NYX	0:85b3fd62ea1a	4627	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	4628	* PLLI2S and PLLSAI are disabled
NYX	0:85b3fd62ea1a	4629	* @note PLLN/PLLR can be written only when PLL is disabled
NYX	0:85b3fd62ea1a	4630	* @note This can be selected for SPDIFRX
NYX	0:85b3fd62ea1a	4631	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
NYX	0:85b3fd62ea1a	4632	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
NYX	0:85b3fd62ea1a	4633	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
NYX	0:85b3fd62ea1a	4634	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
NYX	0:85b3fd62ea1a	4635	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4636	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	4637	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	4638	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4639	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	4640	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	4641	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	4642	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	4643	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	4644	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	4645	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	4646	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	4647	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	4648	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	4649	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	4650	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	4651	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	4652	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	4653	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	4654	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	4655	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	4656	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	4657	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	4658	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	4659	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	4660	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	4661	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	4662	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	4663	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	4664	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	4665	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	4666	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	4667	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	4668	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	4669	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	4670	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	4671	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	4672	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	4673	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	4674	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	4675	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	4676	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	4677	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	4678	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	4679	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	4680	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	4681	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	4682	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	4683	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	4684	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	4685	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	4686	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	4687	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	4688	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	4689	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	4690	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	4691	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	4692	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	4693	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	4694	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	4695	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	4696	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	4697	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	4698	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	4699	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	4700	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	4701	* @param PLLN Between 50 and 432
NYX	0:85b3fd62ea1a	4702	* @param PLLR This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4703	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	4704	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	4705	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	4706	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	4707	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	4708	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	4709	* @retval None
NYX	0:85b3fd62ea1a	4710	*/
NYX	0:85b3fd62ea1a	4711	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
NYX	0:85b3fd62ea1a	4712	{
NYX	0:85b3fd62ea1a	4713	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
NYX	0:85b3fd62ea1a	4714	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
NYX	0:85b3fd62ea1a	4715	}
NYX	0:85b3fd62ea1a	4716	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	4717
NYX	0:85b3fd62ea1a	4718	#if defined(RCC_PLLCFGR_PLLR)
NYX	0:85b3fd62ea1a	4719	#if defined(SAI1)
NYX	0:85b3fd62ea1a	4720	/**
NYX	0:85b3fd62ea1a	4721	* @brief Configure PLL used for SAI clock
NYX	0:85b3fd62ea1a	4722	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	4723	* PLLI2S and PLLSAI are disabled
NYX	0:85b3fd62ea1a	4724	* @note PLLN/PLLR can be written only when PLL is disabled
NYX	0:85b3fd62ea1a	4725	* @note This can be selected for SAI
NYX	0:85b3fd62ea1a	4726	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	4727	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	4728	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	4729	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	4730	* DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
NYX	0:85b3fd62ea1a	4731	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4732	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	4733	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	4734	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4735	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	4736	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	4737	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	4738	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	4739	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	4740	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	4741	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	4742	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	4743	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	4744	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	4745	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	4746	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	4747	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	4748	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	4749	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	4750	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	4751	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	4752	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	4753	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	4754	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	4755	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	4756	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	4757	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	4758	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	4759	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	4760	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	4761	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	4762	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	4763	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	4764	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	4765	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	4766	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	4767	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	4768	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	4769	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	4770	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	4771	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	4772	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	4773	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	4774	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	4775	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	4776	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	4777	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	4778	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	4779	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	4780	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	4781	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	4782	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	4783	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	4784	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	4785	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	4786	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	4787	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	4788	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	4789	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	4790	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	4791	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	4792	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	4793	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	4794	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	4795	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	4796	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	4797	* @param PLLN Between 50 and 432
NYX	0:85b3fd62ea1a	4798	* @param PLLR This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4799	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	4800	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	4801	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	4802	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	4803	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	4804	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	4805	* @param PLLDIVR This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	4806	* @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
NYX	0:85b3fd62ea1a	4807	* @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
NYX	0:85b3fd62ea1a	4808	* @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
NYX	0:85b3fd62ea1a	4809	* @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
NYX	0:85b3fd62ea1a	4810	* @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
NYX	0:85b3fd62ea1a	4811	* @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
NYX	0:85b3fd62ea1a	4812	* @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
NYX	0:85b3fd62ea1a	4813	* @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
NYX	0:85b3fd62ea1a	4814	* @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
NYX	0:85b3fd62ea1a	4815	* @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
NYX	0:85b3fd62ea1a	4816	* @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
NYX	0:85b3fd62ea1a	4817	* @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
NYX	0:85b3fd62ea1a	4818	* @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
NYX	0:85b3fd62ea1a	4819	* @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
NYX	0:85b3fd62ea1a	4820	* @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
NYX	0:85b3fd62ea1a	4821	* @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
NYX	0:85b3fd62ea1a	4822	* @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
NYX	0:85b3fd62ea1a	4823	* @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
NYX	0:85b3fd62ea1a	4824	* @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
NYX	0:85b3fd62ea1a	4825	* @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
NYX	0:85b3fd62ea1a	4826	* @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
NYX	0:85b3fd62ea1a	4827	* @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
NYX	0:85b3fd62ea1a	4828	* @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
NYX	0:85b3fd62ea1a	4829	* @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
NYX	0:85b3fd62ea1a	4830	* @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
NYX	0:85b3fd62ea1a	4831	* @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
NYX	0:85b3fd62ea1a	4832	* @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
NYX	0:85b3fd62ea1a	4833	* @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
NYX	0:85b3fd62ea1a	4834	* @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
NYX	0:85b3fd62ea1a	4835	* @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
NYX	0:85b3fd62ea1a	4836	* @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
NYX	0:85b3fd62ea1a	4837	*
NYX	0:85b3fd62ea1a	4838	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	4839	* @retval None
NYX	0:85b3fd62ea1a	4840	*/
NYX	0:85b3fd62ea1a	4841	#if defined(RCC_DCKCFGR_PLLDIVR)
NYX	0:85b3fd62ea1a	4842	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
NYX	0:85b3fd62ea1a	4843	#else
NYX	0:85b3fd62ea1a	4844	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
NYX	0:85b3fd62ea1a	4845	#endif /* RCC_DCKCFGR_PLLDIVR */
NYX	0:85b3fd62ea1a	4846	{
NYX	0:85b3fd62ea1a	4847	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
NYX	0:85b3fd62ea1a	4848	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
NYX	0:85b3fd62ea1a	4849	#if defined(RCC_DCKCFGR_PLLDIVR)
NYX	0:85b3fd62ea1a	4850	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
NYX	0:85b3fd62ea1a	4851	#endif /* RCC_DCKCFGR_PLLDIVR */
NYX	0:85b3fd62ea1a	4852	}
NYX	0:85b3fd62ea1a	4853	#endif /* SAI1 */
NYX	0:85b3fd62ea1a	4854	#endif /* RCC_PLLCFGR_PLLR */
NYX	0:85b3fd62ea1a	4855
NYX	0:85b3fd62ea1a	4856	/**
NYX	0:85b3fd62ea1a	4857	* @brief Get Main PLL multiplication factor for VCO
NYX	0:85b3fd62ea1a	4858	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
NYX	0:85b3fd62ea1a	4859	* @retval Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	4860	*
NYX	0:85b3fd62ea1a	4861	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	4862	*/
NYX	0:85b3fd62ea1a	4863	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
NYX	0:85b3fd62ea1a	4864	{
NYX	0:85b3fd62ea1a	4865	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
NYX	0:85b3fd62ea1a	4866	}
NYX	0:85b3fd62ea1a	4867
NYX	0:85b3fd62ea1a	4868	/**
NYX	0:85b3fd62ea1a	4869	* @brief Get Main PLL division factor for PLLP
NYX	0:85b3fd62ea1a	4870	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
NYX	0:85b3fd62ea1a	4871	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4872	* @arg @ref LL_RCC_PLLP_DIV_2
NYX	0:85b3fd62ea1a	4873	* @arg @ref LL_RCC_PLLP_DIV_4
NYX	0:85b3fd62ea1a	4874	* @arg @ref LL_RCC_PLLP_DIV_6
NYX	0:85b3fd62ea1a	4875	* @arg @ref LL_RCC_PLLP_DIV_8
NYX	0:85b3fd62ea1a	4876	*/
NYX	0:85b3fd62ea1a	4877	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
NYX	0:85b3fd62ea1a	4878	{
NYX	0:85b3fd62ea1a	4879	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
NYX	0:85b3fd62ea1a	4880	}
NYX	0:85b3fd62ea1a	4881
NYX	0:85b3fd62ea1a	4882	/**
NYX	0:85b3fd62ea1a	4883	* @brief Get Main PLL division factor for PLLQ
NYX	0:85b3fd62ea1a	4884	* @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
NYX	0:85b3fd62ea1a	4885	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
NYX	0:85b3fd62ea1a	4886	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4887	* @arg @ref LL_RCC_PLLQ_DIV_2
NYX	0:85b3fd62ea1a	4888	* @arg @ref LL_RCC_PLLQ_DIV_3
NYX	0:85b3fd62ea1a	4889	* @arg @ref LL_RCC_PLLQ_DIV_4
NYX	0:85b3fd62ea1a	4890	* @arg @ref LL_RCC_PLLQ_DIV_5
NYX	0:85b3fd62ea1a	4891	* @arg @ref LL_RCC_PLLQ_DIV_6
NYX	0:85b3fd62ea1a	4892	* @arg @ref LL_RCC_PLLQ_DIV_7
NYX	0:85b3fd62ea1a	4893	* @arg @ref LL_RCC_PLLQ_DIV_8
NYX	0:85b3fd62ea1a	4894	* @arg @ref LL_RCC_PLLQ_DIV_9
NYX	0:85b3fd62ea1a	4895	* @arg @ref LL_RCC_PLLQ_DIV_10
NYX	0:85b3fd62ea1a	4896	* @arg @ref LL_RCC_PLLQ_DIV_11
NYX	0:85b3fd62ea1a	4897	* @arg @ref LL_RCC_PLLQ_DIV_12
NYX	0:85b3fd62ea1a	4898	* @arg @ref LL_RCC_PLLQ_DIV_13
NYX	0:85b3fd62ea1a	4899	* @arg @ref LL_RCC_PLLQ_DIV_14
NYX	0:85b3fd62ea1a	4900	* @arg @ref LL_RCC_PLLQ_DIV_15
NYX	0:85b3fd62ea1a	4901	*/
NYX	0:85b3fd62ea1a	4902	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
NYX	0:85b3fd62ea1a	4903	{
NYX	0:85b3fd62ea1a	4904	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
NYX	0:85b3fd62ea1a	4905	}
NYX	0:85b3fd62ea1a	4906
NYX	0:85b3fd62ea1a	4907	#if defined(RCC_PLLCFGR_PLLR)
NYX	0:85b3fd62ea1a	4908	/**
NYX	0:85b3fd62ea1a	4909	* @brief Get Main PLL division factor for PLLR
NYX	0:85b3fd62ea1a	4910	* @note used for PLLCLK (system clock)
NYX	0:85b3fd62ea1a	4911	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
NYX	0:85b3fd62ea1a	4912	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4913	* @arg @ref LL_RCC_PLLR_DIV_2
NYX	0:85b3fd62ea1a	4914	* @arg @ref LL_RCC_PLLR_DIV_3
NYX	0:85b3fd62ea1a	4915	* @arg @ref LL_RCC_PLLR_DIV_4
NYX	0:85b3fd62ea1a	4916	* @arg @ref LL_RCC_PLLR_DIV_5
NYX	0:85b3fd62ea1a	4917	* @arg @ref LL_RCC_PLLR_DIV_6
NYX	0:85b3fd62ea1a	4918	* @arg @ref LL_RCC_PLLR_DIV_7
NYX	0:85b3fd62ea1a	4919	*/
NYX	0:85b3fd62ea1a	4920	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
NYX	0:85b3fd62ea1a	4921	{
NYX	0:85b3fd62ea1a	4922	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
NYX	0:85b3fd62ea1a	4923	}
NYX	0:85b3fd62ea1a	4924	#endif /* RCC_PLLCFGR_PLLR */
NYX	0:85b3fd62ea1a	4925
NYX	0:85b3fd62ea1a	4926	#if defined(RCC_DCKCFGR_PLLDIVR)
NYX	0:85b3fd62ea1a	4927	/**
NYX	0:85b3fd62ea1a	4928	* @brief Get Main PLL division factor for PLLDIVR
NYX	0:85b3fd62ea1a	4929	* @note used for PLLSAICLK (SAI1 and SAI2 clock)
NYX	0:85b3fd62ea1a	4930	* @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
NYX	0:85b3fd62ea1a	4931	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4932	* @arg @ref LL_RCC_PLLDIVR_DIV_1
NYX	0:85b3fd62ea1a	4933	* @arg @ref LL_RCC_PLLDIVR_DIV_2
NYX	0:85b3fd62ea1a	4934	* @arg @ref LL_RCC_PLLDIVR_DIV_3
NYX	0:85b3fd62ea1a	4935	* @arg @ref LL_RCC_PLLDIVR_DIV_4
NYX	0:85b3fd62ea1a	4936	* @arg @ref LL_RCC_PLLDIVR_DIV_5
NYX	0:85b3fd62ea1a	4937	* @arg @ref LL_RCC_PLLDIVR_DIV_6
NYX	0:85b3fd62ea1a	4938	* @arg @ref LL_RCC_PLLDIVR_DIV_7
NYX	0:85b3fd62ea1a	4939	* @arg @ref LL_RCC_PLLDIVR_DIV_8
NYX	0:85b3fd62ea1a	4940	* @arg @ref LL_RCC_PLLDIVR_DIV_9
NYX	0:85b3fd62ea1a	4941	* @arg @ref LL_RCC_PLLDIVR_DIV_10
NYX	0:85b3fd62ea1a	4942	* @arg @ref LL_RCC_PLLDIVR_DIV_11
NYX	0:85b3fd62ea1a	4943	* @arg @ref LL_RCC_PLLDIVR_DIV_12
NYX	0:85b3fd62ea1a	4944	* @arg @ref LL_RCC_PLLDIVR_DIV_13
NYX	0:85b3fd62ea1a	4945	* @arg @ref LL_RCC_PLLDIVR_DIV_14
NYX	0:85b3fd62ea1a	4946	* @arg @ref LL_RCC_PLLDIVR_DIV_15
NYX	0:85b3fd62ea1a	4947	* @arg @ref LL_RCC_PLLDIVR_DIV_16
NYX	0:85b3fd62ea1a	4948	* @arg @ref LL_RCC_PLLDIVR_DIV_17
NYX	0:85b3fd62ea1a	4949	* @arg @ref LL_RCC_PLLDIVR_DIV_18
NYX	0:85b3fd62ea1a	4950	* @arg @ref LL_RCC_PLLDIVR_DIV_19
NYX	0:85b3fd62ea1a	4951	* @arg @ref LL_RCC_PLLDIVR_DIV_20
NYX	0:85b3fd62ea1a	4952	* @arg @ref LL_RCC_PLLDIVR_DIV_21
NYX	0:85b3fd62ea1a	4953	* @arg @ref LL_RCC_PLLDIVR_DIV_22
NYX	0:85b3fd62ea1a	4954	* @arg @ref LL_RCC_PLLDIVR_DIV_23
NYX	0:85b3fd62ea1a	4955	* @arg @ref LL_RCC_PLLDIVR_DIV_24
NYX	0:85b3fd62ea1a	4956	* @arg @ref LL_RCC_PLLDIVR_DIV_25
NYX	0:85b3fd62ea1a	4957	* @arg @ref LL_RCC_PLLDIVR_DIV_26
NYX	0:85b3fd62ea1a	4958	* @arg @ref LL_RCC_PLLDIVR_DIV_27
NYX	0:85b3fd62ea1a	4959	* @arg @ref LL_RCC_PLLDIVR_DIV_28
NYX	0:85b3fd62ea1a	4960	* @arg @ref LL_RCC_PLLDIVR_DIV_29
NYX	0:85b3fd62ea1a	4961	* @arg @ref LL_RCC_PLLDIVR_DIV_30
NYX	0:85b3fd62ea1a	4962	* @arg @ref LL_RCC_PLLDIVR_DIV_31
NYX	0:85b3fd62ea1a	4963	*/
NYX	0:85b3fd62ea1a	4964	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
NYX	0:85b3fd62ea1a	4965	{
NYX	0:85b3fd62ea1a	4966	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
NYX	0:85b3fd62ea1a	4967	}
NYX	0:85b3fd62ea1a	4968	#endif /* RCC_DCKCFGR_PLLDIVR */
NYX	0:85b3fd62ea1a	4969
NYX	0:85b3fd62ea1a	4970	/**
NYX	0:85b3fd62ea1a	4971	* @brief Get the oscillator used as PLL clock source.
NYX	0:85b3fd62ea1a	4972	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
NYX	0:85b3fd62ea1a	4973	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4974	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	4975	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	4976	*/
NYX	0:85b3fd62ea1a	4977	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
NYX	0:85b3fd62ea1a	4978	{
NYX	0:85b3fd62ea1a	4979	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
NYX	0:85b3fd62ea1a	4980	}
NYX	0:85b3fd62ea1a	4981
NYX	0:85b3fd62ea1a	4982	/**
NYX	0:85b3fd62ea1a	4983	* @brief Get Division factor for the main PLL and other PLL
NYX	0:85b3fd62ea1a	4984	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
NYX	0:85b3fd62ea1a	4985	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	4986	* @arg @ref LL_RCC_PLLM_DIV_2
NYX	0:85b3fd62ea1a	4987	* @arg @ref LL_RCC_PLLM_DIV_3
NYX	0:85b3fd62ea1a	4988	* @arg @ref LL_RCC_PLLM_DIV_4
NYX	0:85b3fd62ea1a	4989	* @arg @ref LL_RCC_PLLM_DIV_5
NYX	0:85b3fd62ea1a	4990	* @arg @ref LL_RCC_PLLM_DIV_6
NYX	0:85b3fd62ea1a	4991	* @arg @ref LL_RCC_PLLM_DIV_7
NYX	0:85b3fd62ea1a	4992	* @arg @ref LL_RCC_PLLM_DIV_8
NYX	0:85b3fd62ea1a	4993	* @arg @ref LL_RCC_PLLM_DIV_9
NYX	0:85b3fd62ea1a	4994	* @arg @ref LL_RCC_PLLM_DIV_10
NYX	0:85b3fd62ea1a	4995	* @arg @ref LL_RCC_PLLM_DIV_11
NYX	0:85b3fd62ea1a	4996	* @arg @ref LL_RCC_PLLM_DIV_12
NYX	0:85b3fd62ea1a	4997	* @arg @ref LL_RCC_PLLM_DIV_13
NYX	0:85b3fd62ea1a	4998	* @arg @ref LL_RCC_PLLM_DIV_14
NYX	0:85b3fd62ea1a	4999	* @arg @ref LL_RCC_PLLM_DIV_15
NYX	0:85b3fd62ea1a	5000	* @arg @ref LL_RCC_PLLM_DIV_16
NYX	0:85b3fd62ea1a	5001	* @arg @ref LL_RCC_PLLM_DIV_17
NYX	0:85b3fd62ea1a	5002	* @arg @ref LL_RCC_PLLM_DIV_18
NYX	0:85b3fd62ea1a	5003	* @arg @ref LL_RCC_PLLM_DIV_19
NYX	0:85b3fd62ea1a	5004	* @arg @ref LL_RCC_PLLM_DIV_20
NYX	0:85b3fd62ea1a	5005	* @arg @ref LL_RCC_PLLM_DIV_21
NYX	0:85b3fd62ea1a	5006	* @arg @ref LL_RCC_PLLM_DIV_22
NYX	0:85b3fd62ea1a	5007	* @arg @ref LL_RCC_PLLM_DIV_23
NYX	0:85b3fd62ea1a	5008	* @arg @ref LL_RCC_PLLM_DIV_24
NYX	0:85b3fd62ea1a	5009	* @arg @ref LL_RCC_PLLM_DIV_25
NYX	0:85b3fd62ea1a	5010	* @arg @ref LL_RCC_PLLM_DIV_26
NYX	0:85b3fd62ea1a	5011	* @arg @ref LL_RCC_PLLM_DIV_27
NYX	0:85b3fd62ea1a	5012	* @arg @ref LL_RCC_PLLM_DIV_28
NYX	0:85b3fd62ea1a	5013	* @arg @ref LL_RCC_PLLM_DIV_29
NYX	0:85b3fd62ea1a	5014	* @arg @ref LL_RCC_PLLM_DIV_30
NYX	0:85b3fd62ea1a	5015	* @arg @ref LL_RCC_PLLM_DIV_31
NYX	0:85b3fd62ea1a	5016	* @arg @ref LL_RCC_PLLM_DIV_32
NYX	0:85b3fd62ea1a	5017	* @arg @ref LL_RCC_PLLM_DIV_33
NYX	0:85b3fd62ea1a	5018	* @arg @ref LL_RCC_PLLM_DIV_34
NYX	0:85b3fd62ea1a	5019	* @arg @ref LL_RCC_PLLM_DIV_35
NYX	0:85b3fd62ea1a	5020	* @arg @ref LL_RCC_PLLM_DIV_36
NYX	0:85b3fd62ea1a	5021	* @arg @ref LL_RCC_PLLM_DIV_37
NYX	0:85b3fd62ea1a	5022	* @arg @ref LL_RCC_PLLM_DIV_38
NYX	0:85b3fd62ea1a	5023	* @arg @ref LL_RCC_PLLM_DIV_39
NYX	0:85b3fd62ea1a	5024	* @arg @ref LL_RCC_PLLM_DIV_40
NYX	0:85b3fd62ea1a	5025	* @arg @ref LL_RCC_PLLM_DIV_41
NYX	0:85b3fd62ea1a	5026	* @arg @ref LL_RCC_PLLM_DIV_42
NYX	0:85b3fd62ea1a	5027	* @arg @ref LL_RCC_PLLM_DIV_43
NYX	0:85b3fd62ea1a	5028	* @arg @ref LL_RCC_PLLM_DIV_44
NYX	0:85b3fd62ea1a	5029	* @arg @ref LL_RCC_PLLM_DIV_45
NYX	0:85b3fd62ea1a	5030	* @arg @ref LL_RCC_PLLM_DIV_46
NYX	0:85b3fd62ea1a	5031	* @arg @ref LL_RCC_PLLM_DIV_47
NYX	0:85b3fd62ea1a	5032	* @arg @ref LL_RCC_PLLM_DIV_48
NYX	0:85b3fd62ea1a	5033	* @arg @ref LL_RCC_PLLM_DIV_49
NYX	0:85b3fd62ea1a	5034	* @arg @ref LL_RCC_PLLM_DIV_50
NYX	0:85b3fd62ea1a	5035	* @arg @ref LL_RCC_PLLM_DIV_51
NYX	0:85b3fd62ea1a	5036	* @arg @ref LL_RCC_PLLM_DIV_52
NYX	0:85b3fd62ea1a	5037	* @arg @ref LL_RCC_PLLM_DIV_53
NYX	0:85b3fd62ea1a	5038	* @arg @ref LL_RCC_PLLM_DIV_54
NYX	0:85b3fd62ea1a	5039	* @arg @ref LL_RCC_PLLM_DIV_55
NYX	0:85b3fd62ea1a	5040	* @arg @ref LL_RCC_PLLM_DIV_56
NYX	0:85b3fd62ea1a	5041	* @arg @ref LL_RCC_PLLM_DIV_57
NYX	0:85b3fd62ea1a	5042	* @arg @ref LL_RCC_PLLM_DIV_58
NYX	0:85b3fd62ea1a	5043	* @arg @ref LL_RCC_PLLM_DIV_59
NYX	0:85b3fd62ea1a	5044	* @arg @ref LL_RCC_PLLM_DIV_60
NYX	0:85b3fd62ea1a	5045	* @arg @ref LL_RCC_PLLM_DIV_61
NYX	0:85b3fd62ea1a	5046	* @arg @ref LL_RCC_PLLM_DIV_62
NYX	0:85b3fd62ea1a	5047	* @arg @ref LL_RCC_PLLM_DIV_63
NYX	0:85b3fd62ea1a	5048	*/
NYX	0:85b3fd62ea1a	5049	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
NYX	0:85b3fd62ea1a	5050	{
NYX	0:85b3fd62ea1a	5051	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	5052	}
NYX	0:85b3fd62ea1a	5053
NYX	0:85b3fd62ea1a	5054	/**
NYX	0:85b3fd62ea1a	5055	* @brief Configure Spread Spectrum used for PLL
NYX	0:85b3fd62ea1a	5056	* @note These bits must be written before enabling PLL
NYX	0:85b3fd62ea1a	5057	* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
NYX	0:85b3fd62ea1a	5058	* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
NYX	0:85b3fd62ea1a	5059	* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
NYX	0:85b3fd62ea1a	5060	* @param Mod Between Min_Data=0 and Max_Data=8191
NYX	0:85b3fd62ea1a	5061	* @param Inc Between Min_Data=0 and Max_Data=32767
NYX	0:85b3fd62ea1a	5062	* @param Sel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5063	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
NYX	0:85b3fd62ea1a	5064	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
NYX	0:85b3fd62ea1a	5065	* @retval None
NYX	0:85b3fd62ea1a	5066	*/
NYX	0:85b3fd62ea1a	5067	__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
NYX	0:85b3fd62ea1a	5068	{
NYX	0:85b3fd62ea1a	5069	MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER \| RCC_SSCGR_INCSTEP \| RCC_SSCGR_SPREADSEL, Mod \| (Inc << RCC_SSCGR_INCSTEP_Pos) \| Sel);
NYX	0:85b3fd62ea1a	5070	}
NYX	0:85b3fd62ea1a	5071
NYX	0:85b3fd62ea1a	5072	/**
NYX	0:85b3fd62ea1a	5073	* @brief Get Spread Spectrum Modulation Period for PLL
NYX	0:85b3fd62ea1a	5074	* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
NYX	0:85b3fd62ea1a	5075	* @retval Between Min_Data=0 and Max_Data=8191
NYX	0:85b3fd62ea1a	5076	*/
NYX	0:85b3fd62ea1a	5077	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
NYX	0:85b3fd62ea1a	5078	{
NYX	0:85b3fd62ea1a	5079	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
NYX	0:85b3fd62ea1a	5080	}
NYX	0:85b3fd62ea1a	5081
NYX	0:85b3fd62ea1a	5082	/**
NYX	0:85b3fd62ea1a	5083	* @brief Get Spread Spectrum Incrementation Step for PLL
NYX	0:85b3fd62ea1a	5084	* @note Must be written before enabling PLL
NYX	0:85b3fd62ea1a	5085	* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
NYX	0:85b3fd62ea1a	5086	* @retval Between Min_Data=0 and Max_Data=32767
NYX	0:85b3fd62ea1a	5087	*/
NYX	0:85b3fd62ea1a	5088	__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
NYX	0:85b3fd62ea1a	5089	{
NYX	0:85b3fd62ea1a	5090	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
NYX	0:85b3fd62ea1a	5091	}
NYX	0:85b3fd62ea1a	5092
NYX	0:85b3fd62ea1a	5093	/**
NYX	0:85b3fd62ea1a	5094	* @brief Get Spread Spectrum Selection for PLL
NYX	0:85b3fd62ea1a	5095	* @note Must be written before enabling PLL
NYX	0:85b3fd62ea1a	5096	* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
NYX	0:85b3fd62ea1a	5097	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	5098	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
NYX	0:85b3fd62ea1a	5099	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
NYX	0:85b3fd62ea1a	5100	*/
NYX	0:85b3fd62ea1a	5101	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
NYX	0:85b3fd62ea1a	5102	{
NYX	0:85b3fd62ea1a	5103	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
NYX	0:85b3fd62ea1a	5104	}
NYX	0:85b3fd62ea1a	5105
NYX	0:85b3fd62ea1a	5106	/**
NYX	0:85b3fd62ea1a	5107	* @brief Enable Spread Spectrum for PLL.
NYX	0:85b3fd62ea1a	5108	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
NYX	0:85b3fd62ea1a	5109	* @retval None
NYX	0:85b3fd62ea1a	5110	*/
NYX	0:85b3fd62ea1a	5111	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
NYX	0:85b3fd62ea1a	5112	{
NYX	0:85b3fd62ea1a	5113	SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
NYX	0:85b3fd62ea1a	5114	}
NYX	0:85b3fd62ea1a	5115
NYX	0:85b3fd62ea1a	5116	/**
NYX	0:85b3fd62ea1a	5117	* @brief Disable Spread Spectrum for PLL.
NYX	0:85b3fd62ea1a	5118	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
NYX	0:85b3fd62ea1a	5119	* @retval None
NYX	0:85b3fd62ea1a	5120	*/
NYX	0:85b3fd62ea1a	5121	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
NYX	0:85b3fd62ea1a	5122	{
NYX	0:85b3fd62ea1a	5123	CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
NYX	0:85b3fd62ea1a	5124	}
NYX	0:85b3fd62ea1a	5125
NYX	0:85b3fd62ea1a	5126	/**
NYX	0:85b3fd62ea1a	5127	* @}
NYX	0:85b3fd62ea1a	5128	*/
NYX	0:85b3fd62ea1a	5129
NYX	0:85b3fd62ea1a	5130	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	5131	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
NYX	0:85b3fd62ea1a	5132	* @{
NYX	0:85b3fd62ea1a	5133	*/
NYX	0:85b3fd62ea1a	5134
NYX	0:85b3fd62ea1a	5135	/**
NYX	0:85b3fd62ea1a	5136	* @brief Enable PLLI2S
NYX	0:85b3fd62ea1a	5137	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
NYX	0:85b3fd62ea1a	5138	* @retval None
NYX	0:85b3fd62ea1a	5139	*/
NYX	0:85b3fd62ea1a	5140	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
NYX	0:85b3fd62ea1a	5141	{
NYX	0:85b3fd62ea1a	5142	SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
NYX	0:85b3fd62ea1a	5143	}
NYX	0:85b3fd62ea1a	5144
NYX	0:85b3fd62ea1a	5145	/**
NYX	0:85b3fd62ea1a	5146	* @brief Disable PLLI2S
NYX	0:85b3fd62ea1a	5147	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
NYX	0:85b3fd62ea1a	5148	* @retval None
NYX	0:85b3fd62ea1a	5149	*/
NYX	0:85b3fd62ea1a	5150	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
NYX	0:85b3fd62ea1a	5151	{
NYX	0:85b3fd62ea1a	5152	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
NYX	0:85b3fd62ea1a	5153	}
NYX	0:85b3fd62ea1a	5154
NYX	0:85b3fd62ea1a	5155	/**
NYX	0:85b3fd62ea1a	5156	* @brief Check if PLLI2S Ready
NYX	0:85b3fd62ea1a	5157	* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
NYX	0:85b3fd62ea1a	5158	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	5159	*/
NYX	0:85b3fd62ea1a	5160	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
NYX	0:85b3fd62ea1a	5161	{
NYX	0:85b3fd62ea1a	5162	return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
NYX	0:85b3fd62ea1a	5163	}
NYX	0:85b3fd62ea1a	5164
NYX	0:85b3fd62ea1a	5165	#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) \|\| defined(RCC_DCKCFGR_PLLI2SDIVR))
NYX	0:85b3fd62ea1a	5166	/**
NYX	0:85b3fd62ea1a	5167	* @brief Configure PLLI2S used for SAI domain clock
NYX	0:85b3fd62ea1a	5168	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	5169	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	5170	* @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
NYX	0:85b3fd62ea1a	5171	* @note This can be selected for SAI
NYX	0:85b3fd62ea1a	5172	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5173	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5174	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5175	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5176	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5177	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5178	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5179	* DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5180	* DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
NYX	0:85b3fd62ea1a	5181	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5182	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	5183	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	5184	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	5185	*
NYX	0:85b3fd62ea1a	5186	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5187	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5188	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	5189	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	5190	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	5191	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	5192	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	5193	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	5194	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	5195	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	5196	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	5197	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	5198	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	5199	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	5200	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	5201	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	5202	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	5203	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	5204	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	5205	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	5206	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	5207	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	5208	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	5209	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	5210	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	5211	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	5212	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	5213	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	5214	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	5215	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	5216	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	5217	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	5218	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	5219	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	5220	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	5221	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	5222	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	5223	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	5224	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	5225	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	5226	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	5227	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	5228	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	5229	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	5230	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	5231	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	5232	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	5233	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	5234	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	5235	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	5236	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	5237	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	5238	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	5239	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	5240	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	5241	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	5242	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	5243	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	5244	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	5245	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	5246	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	5247	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	5248	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	5249	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	5250	* @param PLLN Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	5251	*
NYX	0:85b3fd62ea1a	5252	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5253	* @param PLLQ_R This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5254	* @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
NYX	0:85b3fd62ea1a	5255	* @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
NYX	0:85b3fd62ea1a	5256	* @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
NYX	0:85b3fd62ea1a	5257	* @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
NYX	0:85b3fd62ea1a	5258	* @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
NYX	0:85b3fd62ea1a	5259	* @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
NYX	0:85b3fd62ea1a	5260	* @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
NYX	0:85b3fd62ea1a	5261	* @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
NYX	0:85b3fd62ea1a	5262	* @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
NYX	0:85b3fd62ea1a	5263	* @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
NYX	0:85b3fd62ea1a	5264	* @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
NYX	0:85b3fd62ea1a	5265	* @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
NYX	0:85b3fd62ea1a	5266	* @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
NYX	0:85b3fd62ea1a	5267	* @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
NYX	0:85b3fd62ea1a	5268	* @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
NYX	0:85b3fd62ea1a	5269	* @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
NYX	0:85b3fd62ea1a	5270	* @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
NYX	0:85b3fd62ea1a	5271	* @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
NYX	0:85b3fd62ea1a	5272	* @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
NYX	0:85b3fd62ea1a	5273	* @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
NYX	0:85b3fd62ea1a	5274	*
NYX	0:85b3fd62ea1a	5275	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5276	* @param PLLDIVQ_R This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5277	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
NYX	0:85b3fd62ea1a	5278	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
NYX	0:85b3fd62ea1a	5279	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
NYX	0:85b3fd62ea1a	5280	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
NYX	0:85b3fd62ea1a	5281	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
NYX	0:85b3fd62ea1a	5282	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
NYX	0:85b3fd62ea1a	5283	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
NYX	0:85b3fd62ea1a	5284	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
NYX	0:85b3fd62ea1a	5285	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
NYX	0:85b3fd62ea1a	5286	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
NYX	0:85b3fd62ea1a	5287	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
NYX	0:85b3fd62ea1a	5288	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
NYX	0:85b3fd62ea1a	5289	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
NYX	0:85b3fd62ea1a	5290	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
NYX	0:85b3fd62ea1a	5291	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
NYX	0:85b3fd62ea1a	5292	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
NYX	0:85b3fd62ea1a	5293	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
NYX	0:85b3fd62ea1a	5294	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
NYX	0:85b3fd62ea1a	5295	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
NYX	0:85b3fd62ea1a	5296	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
NYX	0:85b3fd62ea1a	5297	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
NYX	0:85b3fd62ea1a	5298	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
NYX	0:85b3fd62ea1a	5299	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
NYX	0:85b3fd62ea1a	5300	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
NYX	0:85b3fd62ea1a	5301	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
NYX	0:85b3fd62ea1a	5302	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
NYX	0:85b3fd62ea1a	5303	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
NYX	0:85b3fd62ea1a	5304	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
NYX	0:85b3fd62ea1a	5305	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
NYX	0:85b3fd62ea1a	5306	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
NYX	0:85b3fd62ea1a	5307	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
NYX	0:85b3fd62ea1a	5308	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
NYX	0:85b3fd62ea1a	5309	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
NYX	0:85b3fd62ea1a	5310	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
NYX	0:85b3fd62ea1a	5311	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
NYX	0:85b3fd62ea1a	5312	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
NYX	0:85b3fd62ea1a	5313	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
NYX	0:85b3fd62ea1a	5314	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
NYX	0:85b3fd62ea1a	5315	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
NYX	0:85b3fd62ea1a	5316	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
NYX	0:85b3fd62ea1a	5317	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
NYX	0:85b3fd62ea1a	5318	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
NYX	0:85b3fd62ea1a	5319	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
NYX	0:85b3fd62ea1a	5320	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
NYX	0:85b3fd62ea1a	5321	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
NYX	0:85b3fd62ea1a	5322	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
NYX	0:85b3fd62ea1a	5323	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
NYX	0:85b3fd62ea1a	5324	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
NYX	0:85b3fd62ea1a	5325	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
NYX	0:85b3fd62ea1a	5326	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
NYX	0:85b3fd62ea1a	5327	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
NYX	0:85b3fd62ea1a	5328	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
NYX	0:85b3fd62ea1a	5329	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
NYX	0:85b3fd62ea1a	5330	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
NYX	0:85b3fd62ea1a	5331	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
NYX	0:85b3fd62ea1a	5332	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
NYX	0:85b3fd62ea1a	5333	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
NYX	0:85b3fd62ea1a	5334	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
NYX	0:85b3fd62ea1a	5335	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
NYX	0:85b3fd62ea1a	5336	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
NYX	0:85b3fd62ea1a	5337	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
NYX	0:85b3fd62ea1a	5338	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
NYX	0:85b3fd62ea1a	5339	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
NYX	0:85b3fd62ea1a	5340	*
NYX	0:85b3fd62ea1a	5341	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5342	* @retval None
NYX	0:85b3fd62ea1a	5343	*/
NYX	0:85b3fd62ea1a	5344	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
NYX	0:85b3fd62ea1a	5345	{
NYX	0:85b3fd62ea1a	5346	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
NYX	0:85b3fd62ea1a	5347	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
NYX	0:85b3fd62ea1a	5348	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
NYX	0:85b3fd62ea1a	5349	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
NYX	0:85b3fd62ea1a	5350	#else
NYX	0:85b3fd62ea1a	5351	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
NYX	0:85b3fd62ea1a	5352	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
NYX	0:85b3fd62ea1a	5353	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
NYX	0:85b3fd62ea1a	5354	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	5355	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
NYX	0:85b3fd62ea1a	5356	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
NYX	0:85b3fd62ea1a	5357	#else
NYX	0:85b3fd62ea1a	5358	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
NYX	0:85b3fd62ea1a	5359	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
NYX	0:85b3fd62ea1a	5360	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	5361	}
NYX	0:85b3fd62ea1a	5362	#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
NYX	0:85b3fd62ea1a	5363
NYX	0:85b3fd62ea1a	5364	#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	5365	/**
NYX	0:85b3fd62ea1a	5366	* @brief Configure PLLI2S used for 48Mhz domain clock
NYX	0:85b3fd62ea1a	5367	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	5368	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	5369	* @note PLLN/PLLQ can be written only when PLLI2S is disabled
NYX	0:85b3fd62ea1a	5370	* @note This can be selected for RNG, USB, SDIO
NYX	0:85b3fd62ea1a	5371	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	5372	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	5373	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	5374	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	5375	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	5376	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
NYX	0:85b3fd62ea1a	5377	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5378	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	5379	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	5380	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	5381	*
NYX	0:85b3fd62ea1a	5382	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5383	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5384	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	5385	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	5386	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	5387	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	5388	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	5389	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	5390	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	5391	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	5392	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	5393	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	5394	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	5395	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	5396	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	5397	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	5398	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	5399	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	5400	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	5401	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	5402	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	5403	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	5404	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	5405	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	5406	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	5407	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	5408	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	5409	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	5410	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	5411	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	5412	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	5413	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	5414	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	5415	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	5416	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	5417	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	5418	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	5419	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	5420	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	5421	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	5422	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	5423	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	5424	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	5425	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	5426	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	5427	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	5428	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	5429	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	5430	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	5431	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	5432	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	5433	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	5434	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	5435	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	5436	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	5437	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	5438	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	5439	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	5440	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	5441	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	5442	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	5443	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	5444	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	5445	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	5446	* @param PLLN Between 50 and 432
NYX	0:85b3fd62ea1a	5447	* @param PLLQ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5448	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
NYX	0:85b3fd62ea1a	5449	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
NYX	0:85b3fd62ea1a	5450	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
NYX	0:85b3fd62ea1a	5451	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
NYX	0:85b3fd62ea1a	5452	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
NYX	0:85b3fd62ea1a	5453	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
NYX	0:85b3fd62ea1a	5454	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
NYX	0:85b3fd62ea1a	5455	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
NYX	0:85b3fd62ea1a	5456	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
NYX	0:85b3fd62ea1a	5457	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
NYX	0:85b3fd62ea1a	5458	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
NYX	0:85b3fd62ea1a	5459	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
NYX	0:85b3fd62ea1a	5460	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
NYX	0:85b3fd62ea1a	5461	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
NYX	0:85b3fd62ea1a	5462	* @retval None
NYX	0:85b3fd62ea1a	5463	*/
NYX	0:85b3fd62ea1a	5464	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
NYX	0:85b3fd62ea1a	5465	{
NYX	0:85b3fd62ea1a	5466	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
NYX	0:85b3fd62ea1a	5467	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
NYX	0:85b3fd62ea1a	5468	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
NYX	0:85b3fd62ea1a	5469	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
NYX	0:85b3fd62ea1a	5470	#else
NYX	0:85b3fd62ea1a	5471	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
NYX	0:85b3fd62ea1a	5472	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
NYX	0:85b3fd62ea1a	5473	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLQ);
NYX	0:85b3fd62ea1a	5474	}
NYX	0:85b3fd62ea1a	5475	#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	5476
NYX	0:85b3fd62ea1a	5477	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	5478	/**
NYX	0:85b3fd62ea1a	5479	* @brief Configure PLLI2S used for SPDIFRX domain clock
NYX	0:85b3fd62ea1a	5480	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	5481	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	5482	* @note PLLN/PLLP can be written only when PLLI2S is disabled
NYX	0:85b3fd62ea1a	5483	* @note This can be selected for SPDIFRX
NYX	0:85b3fd62ea1a	5484	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
NYX	0:85b3fd62ea1a	5485	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
NYX	0:85b3fd62ea1a	5486	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
NYX	0:85b3fd62ea1a	5487	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
NYX	0:85b3fd62ea1a	5488	* PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
NYX	0:85b3fd62ea1a	5489	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5490	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	5491	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	5492	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5493	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	5494	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	5495	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	5496	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	5497	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	5498	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	5499	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	5500	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	5501	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	5502	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	5503	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	5504	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	5505	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	5506	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	5507	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	5508	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	5509	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	5510	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	5511	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	5512	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	5513	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	5514	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	5515	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	5516	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	5517	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	5518	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	5519	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	5520	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	5521	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	5522	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	5523	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	5524	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	5525	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	5526	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	5527	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	5528	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	5529	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	5530	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	5531	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	5532	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	5533	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	5534	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	5535	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	5536	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	5537	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	5538	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	5539	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	5540	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	5541	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	5542	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	5543	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	5544	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	5545	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	5546	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	5547	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	5548	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	5549	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	5550	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	5551	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	5552	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	5553	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	5554	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	5555	* @param PLLN Between 50 and 432
NYX	0:85b3fd62ea1a	5556	* @param PLLP This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5557	* @arg @ref LL_RCC_PLLI2SP_DIV_2
NYX	0:85b3fd62ea1a	5558	* @arg @ref LL_RCC_PLLI2SP_DIV_4
NYX	0:85b3fd62ea1a	5559	* @arg @ref LL_RCC_PLLI2SP_DIV_6
NYX	0:85b3fd62ea1a	5560	* @arg @ref LL_RCC_PLLI2SP_DIV_8
NYX	0:85b3fd62ea1a	5561	* @retval None
NYX	0:85b3fd62ea1a	5562	*/
NYX	0:85b3fd62ea1a	5563	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
NYX	0:85b3fd62ea1a	5564	{
NYX	0:85b3fd62ea1a	5565	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
NYX	0:85b3fd62ea1a	5566	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
NYX	0:85b3fd62ea1a	5567	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
NYX	0:85b3fd62ea1a	5568	#else
NYX	0:85b3fd62ea1a	5569	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
NYX	0:85b3fd62ea1a	5570	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
NYX	0:85b3fd62ea1a	5571	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLP);
NYX	0:85b3fd62ea1a	5572	}
NYX	0:85b3fd62ea1a	5573	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	5574
NYX	0:85b3fd62ea1a	5575	/**
NYX	0:85b3fd62ea1a	5576	* @brief Configure PLLI2S used for I2S1 domain clock
NYX	0:85b3fd62ea1a	5577	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	5578	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	5579	* @note PLLN/PLLR can be written only when PLLI2S is disabled
NYX	0:85b3fd62ea1a	5580	* @note This can be selected for I2S
NYX	0:85b3fd62ea1a	5581	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
NYX	0:85b3fd62ea1a	5582	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
NYX	0:85b3fd62ea1a	5583	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
NYX	0:85b3fd62ea1a	5584	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
NYX	0:85b3fd62ea1a	5585	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
NYX	0:85b3fd62ea1a	5586	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
NYX	0:85b3fd62ea1a	5587	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5588	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	5589	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	5590	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	5591	*
NYX	0:85b3fd62ea1a	5592	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5593	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5594	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	5595	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	5596	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	5597	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	5598	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	5599	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	5600	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	5601	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	5602	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	5603	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	5604	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	5605	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	5606	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	5607	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	5608	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	5609	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	5610	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	5611	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	5612	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	5613	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	5614	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	5615	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	5616	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	5617	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	5618	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	5619	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	5620	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	5621	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	5622	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	5623	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	5624	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	5625	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	5626	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	5627	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	5628	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	5629	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	5630	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	5631	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	5632	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	5633	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	5634	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	5635	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	5636	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	5637	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	5638	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	5639	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	5640	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	5641	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	5642	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	5643	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	5644	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	5645	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	5646	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	5647	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	5648	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	5649	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	5650	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	5651	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	5652	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	5653	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	5654	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	5655	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	5656	* @param PLLN Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	5657	*
NYX	0:85b3fd62ea1a	5658	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5659	* @param PLLR This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5660	* @arg @ref LL_RCC_PLLI2SR_DIV_2
NYX	0:85b3fd62ea1a	5661	* @arg @ref LL_RCC_PLLI2SR_DIV_3
NYX	0:85b3fd62ea1a	5662	* @arg @ref LL_RCC_PLLI2SR_DIV_4
NYX	0:85b3fd62ea1a	5663	* @arg @ref LL_RCC_PLLI2SR_DIV_5
NYX	0:85b3fd62ea1a	5664	* @arg @ref LL_RCC_PLLI2SR_DIV_6
NYX	0:85b3fd62ea1a	5665	* @arg @ref LL_RCC_PLLI2SR_DIV_7
NYX	0:85b3fd62ea1a	5666	* @retval None
NYX	0:85b3fd62ea1a	5667	*/
NYX	0:85b3fd62ea1a	5668	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
NYX	0:85b3fd62ea1a	5669	{
NYX	0:85b3fd62ea1a	5670	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
NYX	0:85b3fd62ea1a	5671	MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
NYX	0:85b3fd62ea1a	5672	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
NYX	0:85b3fd62ea1a	5673	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
NYX	0:85b3fd62ea1a	5674	#else
NYX	0:85b3fd62ea1a	5675	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
NYX	0:85b3fd62ea1a	5676	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
NYX	0:85b3fd62ea1a	5677	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLR);
NYX	0:85b3fd62ea1a	5678	}
NYX	0:85b3fd62ea1a	5679
NYX	0:85b3fd62ea1a	5680	/**
NYX	0:85b3fd62ea1a	5681	* @brief Get I2SPLL multiplication factor for VCO
NYX	0:85b3fd62ea1a	5682	* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
NYX	0:85b3fd62ea1a	5683	* @retval Between 50/192(*) and 432
NYX	0:85b3fd62ea1a	5684	*
NYX	0:85b3fd62ea1a	5685	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5686	*/
NYX	0:85b3fd62ea1a	5687	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
NYX	0:85b3fd62ea1a	5688	{
NYX	0:85b3fd62ea1a	5689	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
NYX	0:85b3fd62ea1a	5690	}
NYX	0:85b3fd62ea1a	5691
NYX	0:85b3fd62ea1a	5692	#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
NYX	0:85b3fd62ea1a	5693	/**
NYX	0:85b3fd62ea1a	5694	* @brief Get I2SPLL division factor for PLLI2SQ
NYX	0:85b3fd62ea1a	5695	* @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
NYX	0:85b3fd62ea1a	5696	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	5697	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
NYX	0:85b3fd62ea1a	5698	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
NYX	0:85b3fd62ea1a	5699	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
NYX	0:85b3fd62ea1a	5700	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
NYX	0:85b3fd62ea1a	5701	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
NYX	0:85b3fd62ea1a	5702	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
NYX	0:85b3fd62ea1a	5703	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
NYX	0:85b3fd62ea1a	5704	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
NYX	0:85b3fd62ea1a	5705	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
NYX	0:85b3fd62ea1a	5706	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
NYX	0:85b3fd62ea1a	5707	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
NYX	0:85b3fd62ea1a	5708	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
NYX	0:85b3fd62ea1a	5709	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
NYX	0:85b3fd62ea1a	5710	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
NYX	0:85b3fd62ea1a	5711	*/
NYX	0:85b3fd62ea1a	5712	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
NYX	0:85b3fd62ea1a	5713	{
NYX	0:85b3fd62ea1a	5714	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
NYX	0:85b3fd62ea1a	5715	}
NYX	0:85b3fd62ea1a	5716	#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
NYX	0:85b3fd62ea1a	5717
NYX	0:85b3fd62ea1a	5718	/**
NYX	0:85b3fd62ea1a	5719	* @brief Get I2SPLL division factor for PLLI2SR
NYX	0:85b3fd62ea1a	5720	* @note used for PLLI2SCLK (I2S clock)
NYX	0:85b3fd62ea1a	5721	* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
NYX	0:85b3fd62ea1a	5722	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	5723	* @arg @ref LL_RCC_PLLI2SR_DIV_2
NYX	0:85b3fd62ea1a	5724	* @arg @ref LL_RCC_PLLI2SR_DIV_3
NYX	0:85b3fd62ea1a	5725	* @arg @ref LL_RCC_PLLI2SR_DIV_4
NYX	0:85b3fd62ea1a	5726	* @arg @ref LL_RCC_PLLI2SR_DIV_5
NYX	0:85b3fd62ea1a	5727	* @arg @ref LL_RCC_PLLI2SR_DIV_6
NYX	0:85b3fd62ea1a	5728	* @arg @ref LL_RCC_PLLI2SR_DIV_7
NYX	0:85b3fd62ea1a	5729	*/
NYX	0:85b3fd62ea1a	5730	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
NYX	0:85b3fd62ea1a	5731	{
NYX	0:85b3fd62ea1a	5732	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
NYX	0:85b3fd62ea1a	5733	}
NYX	0:85b3fd62ea1a	5734
NYX	0:85b3fd62ea1a	5735	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
NYX	0:85b3fd62ea1a	5736	/**
NYX	0:85b3fd62ea1a	5737	* @brief Get I2SPLL division factor for PLLI2SP
NYX	0:85b3fd62ea1a	5738	* @note used for PLLSPDIFRXCLK (SPDIFRX clock)
NYX	0:85b3fd62ea1a	5739	* @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
NYX	0:85b3fd62ea1a	5740	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	5741	* @arg @ref LL_RCC_PLLI2SP_DIV_2
NYX	0:85b3fd62ea1a	5742	* @arg @ref LL_RCC_PLLI2SP_DIV_4
NYX	0:85b3fd62ea1a	5743	* @arg @ref LL_RCC_PLLI2SP_DIV_6
NYX	0:85b3fd62ea1a	5744	* @arg @ref LL_RCC_PLLI2SP_DIV_8
NYX	0:85b3fd62ea1a	5745	*/
NYX	0:85b3fd62ea1a	5746	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
NYX	0:85b3fd62ea1a	5747	{
NYX	0:85b3fd62ea1a	5748	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
NYX	0:85b3fd62ea1a	5749	}
NYX	0:85b3fd62ea1a	5750	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
NYX	0:85b3fd62ea1a	5751
NYX	0:85b3fd62ea1a	5752	#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX	0:85b3fd62ea1a	5753	/**
NYX	0:85b3fd62ea1a	5754	* @brief Get I2SPLL division factor for PLLI2SDIVQ
NYX	0:85b3fd62ea1a	5755	* @note used PLLSAICLK selected (SAI clock)
NYX	0:85b3fd62ea1a	5756	* @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
NYX	0:85b3fd62ea1a	5757	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	5758	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
NYX	0:85b3fd62ea1a	5759	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
NYX	0:85b3fd62ea1a	5760	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
NYX	0:85b3fd62ea1a	5761	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
NYX	0:85b3fd62ea1a	5762	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
NYX	0:85b3fd62ea1a	5763	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
NYX	0:85b3fd62ea1a	5764	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
NYX	0:85b3fd62ea1a	5765	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
NYX	0:85b3fd62ea1a	5766	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
NYX	0:85b3fd62ea1a	5767	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
NYX	0:85b3fd62ea1a	5768	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
NYX	0:85b3fd62ea1a	5769	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
NYX	0:85b3fd62ea1a	5770	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
NYX	0:85b3fd62ea1a	5771	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
NYX	0:85b3fd62ea1a	5772	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
NYX	0:85b3fd62ea1a	5773	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
NYX	0:85b3fd62ea1a	5774	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
NYX	0:85b3fd62ea1a	5775	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
NYX	0:85b3fd62ea1a	5776	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
NYX	0:85b3fd62ea1a	5777	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
NYX	0:85b3fd62ea1a	5778	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
NYX	0:85b3fd62ea1a	5779	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
NYX	0:85b3fd62ea1a	5780	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
NYX	0:85b3fd62ea1a	5781	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
NYX	0:85b3fd62ea1a	5782	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
NYX	0:85b3fd62ea1a	5783	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
NYX	0:85b3fd62ea1a	5784	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
NYX	0:85b3fd62ea1a	5785	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
NYX	0:85b3fd62ea1a	5786	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
NYX	0:85b3fd62ea1a	5787	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
NYX	0:85b3fd62ea1a	5788	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
NYX	0:85b3fd62ea1a	5789	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
NYX	0:85b3fd62ea1a	5790	*/
NYX	0:85b3fd62ea1a	5791	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
NYX	0:85b3fd62ea1a	5792	{
NYX	0:85b3fd62ea1a	5793	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
NYX	0:85b3fd62ea1a	5794	}
NYX	0:85b3fd62ea1a	5795	#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
NYX	0:85b3fd62ea1a	5796
NYX	0:85b3fd62ea1a	5797	#if defined(RCC_DCKCFGR_PLLI2SDIVR)
NYX	0:85b3fd62ea1a	5798	/**
NYX	0:85b3fd62ea1a	5799	* @brief Get I2SPLL division factor for PLLI2SDIVR
NYX	0:85b3fd62ea1a	5800	* @note used PLLSAICLK selected (SAI clock)
NYX	0:85b3fd62ea1a	5801	* @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
NYX	0:85b3fd62ea1a	5802	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	5803	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
NYX	0:85b3fd62ea1a	5804	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
NYX	0:85b3fd62ea1a	5805	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
NYX	0:85b3fd62ea1a	5806	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
NYX	0:85b3fd62ea1a	5807	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
NYX	0:85b3fd62ea1a	5808	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
NYX	0:85b3fd62ea1a	5809	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
NYX	0:85b3fd62ea1a	5810	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
NYX	0:85b3fd62ea1a	5811	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
NYX	0:85b3fd62ea1a	5812	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
NYX	0:85b3fd62ea1a	5813	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
NYX	0:85b3fd62ea1a	5814	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
NYX	0:85b3fd62ea1a	5815	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
NYX	0:85b3fd62ea1a	5816	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
NYX	0:85b3fd62ea1a	5817	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
NYX	0:85b3fd62ea1a	5818	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
NYX	0:85b3fd62ea1a	5819	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
NYX	0:85b3fd62ea1a	5820	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
NYX	0:85b3fd62ea1a	5821	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
NYX	0:85b3fd62ea1a	5822	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
NYX	0:85b3fd62ea1a	5823	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
NYX	0:85b3fd62ea1a	5824	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
NYX	0:85b3fd62ea1a	5825	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
NYX	0:85b3fd62ea1a	5826	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
NYX	0:85b3fd62ea1a	5827	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
NYX	0:85b3fd62ea1a	5828	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
NYX	0:85b3fd62ea1a	5829	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
NYX	0:85b3fd62ea1a	5830	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
NYX	0:85b3fd62ea1a	5831	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
NYX	0:85b3fd62ea1a	5832	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
NYX	0:85b3fd62ea1a	5833	* @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
NYX	0:85b3fd62ea1a	5834	*/
NYX	0:85b3fd62ea1a	5835	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
NYX	0:85b3fd62ea1a	5836	{
NYX	0:85b3fd62ea1a	5837	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
NYX	0:85b3fd62ea1a	5838	}
NYX	0:85b3fd62ea1a	5839	#endif /* RCC_DCKCFGR_PLLI2SDIVR */
NYX	0:85b3fd62ea1a	5840
NYX	0:85b3fd62ea1a	5841	/**
NYX	0:85b3fd62ea1a	5842	* @brief Get division factor for PLLI2S input clock
NYX	0:85b3fd62ea1a	5843	* @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
NYX	0:85b3fd62ea1a	5844	* PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
NYX	0:85b3fd62ea1a	5845	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	5846	* @arg @ref LL_RCC_PLLI2SM_DIV_2
NYX	0:85b3fd62ea1a	5847	* @arg @ref LL_RCC_PLLI2SM_DIV_3
NYX	0:85b3fd62ea1a	5848	* @arg @ref LL_RCC_PLLI2SM_DIV_4
NYX	0:85b3fd62ea1a	5849	* @arg @ref LL_RCC_PLLI2SM_DIV_5
NYX	0:85b3fd62ea1a	5850	* @arg @ref LL_RCC_PLLI2SM_DIV_6
NYX	0:85b3fd62ea1a	5851	* @arg @ref LL_RCC_PLLI2SM_DIV_7
NYX	0:85b3fd62ea1a	5852	* @arg @ref LL_RCC_PLLI2SM_DIV_8
NYX	0:85b3fd62ea1a	5853	* @arg @ref LL_RCC_PLLI2SM_DIV_9
NYX	0:85b3fd62ea1a	5854	* @arg @ref LL_RCC_PLLI2SM_DIV_10
NYX	0:85b3fd62ea1a	5855	* @arg @ref LL_RCC_PLLI2SM_DIV_11
NYX	0:85b3fd62ea1a	5856	* @arg @ref LL_RCC_PLLI2SM_DIV_12
NYX	0:85b3fd62ea1a	5857	* @arg @ref LL_RCC_PLLI2SM_DIV_13
NYX	0:85b3fd62ea1a	5858	* @arg @ref LL_RCC_PLLI2SM_DIV_14
NYX	0:85b3fd62ea1a	5859	* @arg @ref LL_RCC_PLLI2SM_DIV_15
NYX	0:85b3fd62ea1a	5860	* @arg @ref LL_RCC_PLLI2SM_DIV_16
NYX	0:85b3fd62ea1a	5861	* @arg @ref LL_RCC_PLLI2SM_DIV_17
NYX	0:85b3fd62ea1a	5862	* @arg @ref LL_RCC_PLLI2SM_DIV_18
NYX	0:85b3fd62ea1a	5863	* @arg @ref LL_RCC_PLLI2SM_DIV_19
NYX	0:85b3fd62ea1a	5864	* @arg @ref LL_RCC_PLLI2SM_DIV_20
NYX	0:85b3fd62ea1a	5865	* @arg @ref LL_RCC_PLLI2SM_DIV_21
NYX	0:85b3fd62ea1a	5866	* @arg @ref LL_RCC_PLLI2SM_DIV_22
NYX	0:85b3fd62ea1a	5867	* @arg @ref LL_RCC_PLLI2SM_DIV_23
NYX	0:85b3fd62ea1a	5868	* @arg @ref LL_RCC_PLLI2SM_DIV_24
NYX	0:85b3fd62ea1a	5869	* @arg @ref LL_RCC_PLLI2SM_DIV_25
NYX	0:85b3fd62ea1a	5870	* @arg @ref LL_RCC_PLLI2SM_DIV_26
NYX	0:85b3fd62ea1a	5871	* @arg @ref LL_RCC_PLLI2SM_DIV_27
NYX	0:85b3fd62ea1a	5872	* @arg @ref LL_RCC_PLLI2SM_DIV_28
NYX	0:85b3fd62ea1a	5873	* @arg @ref LL_RCC_PLLI2SM_DIV_29
NYX	0:85b3fd62ea1a	5874	* @arg @ref LL_RCC_PLLI2SM_DIV_30
NYX	0:85b3fd62ea1a	5875	* @arg @ref LL_RCC_PLLI2SM_DIV_31
NYX	0:85b3fd62ea1a	5876	* @arg @ref LL_RCC_PLLI2SM_DIV_32
NYX	0:85b3fd62ea1a	5877	* @arg @ref LL_RCC_PLLI2SM_DIV_33
NYX	0:85b3fd62ea1a	5878	* @arg @ref LL_RCC_PLLI2SM_DIV_34
NYX	0:85b3fd62ea1a	5879	* @arg @ref LL_RCC_PLLI2SM_DIV_35
NYX	0:85b3fd62ea1a	5880	* @arg @ref LL_RCC_PLLI2SM_DIV_36
NYX	0:85b3fd62ea1a	5881	* @arg @ref LL_RCC_PLLI2SM_DIV_37
NYX	0:85b3fd62ea1a	5882	* @arg @ref LL_RCC_PLLI2SM_DIV_38
NYX	0:85b3fd62ea1a	5883	* @arg @ref LL_RCC_PLLI2SM_DIV_39
NYX	0:85b3fd62ea1a	5884	* @arg @ref LL_RCC_PLLI2SM_DIV_40
NYX	0:85b3fd62ea1a	5885	* @arg @ref LL_RCC_PLLI2SM_DIV_41
NYX	0:85b3fd62ea1a	5886	* @arg @ref LL_RCC_PLLI2SM_DIV_42
NYX	0:85b3fd62ea1a	5887	* @arg @ref LL_RCC_PLLI2SM_DIV_43
NYX	0:85b3fd62ea1a	5888	* @arg @ref LL_RCC_PLLI2SM_DIV_44
NYX	0:85b3fd62ea1a	5889	* @arg @ref LL_RCC_PLLI2SM_DIV_45
NYX	0:85b3fd62ea1a	5890	* @arg @ref LL_RCC_PLLI2SM_DIV_46
NYX	0:85b3fd62ea1a	5891	* @arg @ref LL_RCC_PLLI2SM_DIV_47
NYX	0:85b3fd62ea1a	5892	* @arg @ref LL_RCC_PLLI2SM_DIV_48
NYX	0:85b3fd62ea1a	5893	* @arg @ref LL_RCC_PLLI2SM_DIV_49
NYX	0:85b3fd62ea1a	5894	* @arg @ref LL_RCC_PLLI2SM_DIV_50
NYX	0:85b3fd62ea1a	5895	* @arg @ref LL_RCC_PLLI2SM_DIV_51
NYX	0:85b3fd62ea1a	5896	* @arg @ref LL_RCC_PLLI2SM_DIV_52
NYX	0:85b3fd62ea1a	5897	* @arg @ref LL_RCC_PLLI2SM_DIV_53
NYX	0:85b3fd62ea1a	5898	* @arg @ref LL_RCC_PLLI2SM_DIV_54
NYX	0:85b3fd62ea1a	5899	* @arg @ref LL_RCC_PLLI2SM_DIV_55
NYX	0:85b3fd62ea1a	5900	* @arg @ref LL_RCC_PLLI2SM_DIV_56
NYX	0:85b3fd62ea1a	5901	* @arg @ref LL_RCC_PLLI2SM_DIV_57
NYX	0:85b3fd62ea1a	5902	* @arg @ref LL_RCC_PLLI2SM_DIV_58
NYX	0:85b3fd62ea1a	5903	* @arg @ref LL_RCC_PLLI2SM_DIV_59
NYX	0:85b3fd62ea1a	5904	* @arg @ref LL_RCC_PLLI2SM_DIV_60
NYX	0:85b3fd62ea1a	5905	* @arg @ref LL_RCC_PLLI2SM_DIV_61
NYX	0:85b3fd62ea1a	5906	* @arg @ref LL_RCC_PLLI2SM_DIV_62
NYX	0:85b3fd62ea1a	5907	* @arg @ref LL_RCC_PLLI2SM_DIV_63
NYX	0:85b3fd62ea1a	5908	*/
NYX	0:85b3fd62ea1a	5909	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
NYX	0:85b3fd62ea1a	5910	{
NYX	0:85b3fd62ea1a	5911	#if defined(RCC_PLLI2SCFGR_PLLI2SM)
NYX	0:85b3fd62ea1a	5912	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
NYX	0:85b3fd62ea1a	5913	#else
NYX	0:85b3fd62ea1a	5914	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	5915	#endif /* RCC_PLLI2SCFGR_PLLI2SM */
NYX	0:85b3fd62ea1a	5916	}
NYX	0:85b3fd62ea1a	5917
NYX	0:85b3fd62ea1a	5918	/**
NYX	0:85b3fd62ea1a	5919	* @brief Get the oscillator used as PLL clock source.
NYX	0:85b3fd62ea1a	5920	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
NYX	0:85b3fd62ea1a	5921	* PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
NYX	0:85b3fd62ea1a	5922	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	5923	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	5924	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	5925	* @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
NYX	0:85b3fd62ea1a	5926	*
NYX	0:85b3fd62ea1a	5927	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	5928	*/
NYX	0:85b3fd62ea1a	5929	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
NYX	0:85b3fd62ea1a	5930	{
NYX	0:85b3fd62ea1a	5931	#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
NYX	0:85b3fd62ea1a	5932	register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
NYX	0:85b3fd62ea1a	5933	register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
NYX	0:85b3fd62ea1a	5934	register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
NYX	0:85b3fd62ea1a	5935	return (uint32_t)(pllsrc \| plli2sssrc0 \| plli2sssrc1);
NYX	0:85b3fd62ea1a	5936	#else
NYX	0:85b3fd62ea1a	5937	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
NYX	0:85b3fd62ea1a	5938	#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
NYX	0:85b3fd62ea1a	5939	}
NYX	0:85b3fd62ea1a	5940
NYX	0:85b3fd62ea1a	5941	/**
NYX	0:85b3fd62ea1a	5942	* @}
NYX	0:85b3fd62ea1a	5943	*/
NYX	0:85b3fd62ea1a	5944	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	5945
NYX	0:85b3fd62ea1a	5946	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	5947	/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
NYX	0:85b3fd62ea1a	5948	* @{
NYX	0:85b3fd62ea1a	5949	*/
NYX	0:85b3fd62ea1a	5950
NYX	0:85b3fd62ea1a	5951	/**
NYX	0:85b3fd62ea1a	5952	* @brief Enable PLLSAI
NYX	0:85b3fd62ea1a	5953	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
NYX	0:85b3fd62ea1a	5954	* @retval None
NYX	0:85b3fd62ea1a	5955	*/
NYX	0:85b3fd62ea1a	5956	__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
NYX	0:85b3fd62ea1a	5957	{
NYX	0:85b3fd62ea1a	5958	SET_BIT(RCC->CR, RCC_CR_PLLSAION);
NYX	0:85b3fd62ea1a	5959	}
NYX	0:85b3fd62ea1a	5960
NYX	0:85b3fd62ea1a	5961	/**
NYX	0:85b3fd62ea1a	5962	* @brief Disable PLLSAI
NYX	0:85b3fd62ea1a	5963	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
NYX	0:85b3fd62ea1a	5964	* @retval None
NYX	0:85b3fd62ea1a	5965	*/
NYX	0:85b3fd62ea1a	5966	__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
NYX	0:85b3fd62ea1a	5967	{
NYX	0:85b3fd62ea1a	5968	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
NYX	0:85b3fd62ea1a	5969	}
NYX	0:85b3fd62ea1a	5970
NYX	0:85b3fd62ea1a	5971	/**
NYX	0:85b3fd62ea1a	5972	* @brief Check if PLLSAI Ready
NYX	0:85b3fd62ea1a	5973	* @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
NYX	0:85b3fd62ea1a	5974	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	5975	*/
NYX	0:85b3fd62ea1a	5976	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
NYX	0:85b3fd62ea1a	5977	{
NYX	0:85b3fd62ea1a	5978	return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
NYX	0:85b3fd62ea1a	5979	}
NYX	0:85b3fd62ea1a	5980
NYX	0:85b3fd62ea1a	5981	/**
NYX	0:85b3fd62ea1a	5982	* @brief Configure PLLSAI used for SAI domain clock
NYX	0:85b3fd62ea1a	5983	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	5984	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	5985	* @note PLLN/PLLQ can be written only when PLLSAI is disabled
NYX	0:85b3fd62ea1a	5986	* @note This can be selected for SAI
NYX	0:85b3fd62ea1a	5987	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5988	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5989	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5990	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5991	* PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
NYX	0:85b3fd62ea1a	5992	* DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
NYX	0:85b3fd62ea1a	5993	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5994	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	5995	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	5996	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	5997	* @arg @ref LL_RCC_PLLSAIM_DIV_2
NYX	0:85b3fd62ea1a	5998	* @arg @ref LL_RCC_PLLSAIM_DIV_3
NYX	0:85b3fd62ea1a	5999	* @arg @ref LL_RCC_PLLSAIM_DIV_4
NYX	0:85b3fd62ea1a	6000	* @arg @ref LL_RCC_PLLSAIM_DIV_5
NYX	0:85b3fd62ea1a	6001	* @arg @ref LL_RCC_PLLSAIM_DIV_6
NYX	0:85b3fd62ea1a	6002	* @arg @ref LL_RCC_PLLSAIM_DIV_7
NYX	0:85b3fd62ea1a	6003	* @arg @ref LL_RCC_PLLSAIM_DIV_8
NYX	0:85b3fd62ea1a	6004	* @arg @ref LL_RCC_PLLSAIM_DIV_9
NYX	0:85b3fd62ea1a	6005	* @arg @ref LL_RCC_PLLSAIM_DIV_10
NYX	0:85b3fd62ea1a	6006	* @arg @ref LL_RCC_PLLSAIM_DIV_11
NYX	0:85b3fd62ea1a	6007	* @arg @ref LL_RCC_PLLSAIM_DIV_12
NYX	0:85b3fd62ea1a	6008	* @arg @ref LL_RCC_PLLSAIM_DIV_13
NYX	0:85b3fd62ea1a	6009	* @arg @ref LL_RCC_PLLSAIM_DIV_14
NYX	0:85b3fd62ea1a	6010	* @arg @ref LL_RCC_PLLSAIM_DIV_15
NYX	0:85b3fd62ea1a	6011	* @arg @ref LL_RCC_PLLSAIM_DIV_16
NYX	0:85b3fd62ea1a	6012	* @arg @ref LL_RCC_PLLSAIM_DIV_17
NYX	0:85b3fd62ea1a	6013	* @arg @ref LL_RCC_PLLSAIM_DIV_18
NYX	0:85b3fd62ea1a	6014	* @arg @ref LL_RCC_PLLSAIM_DIV_19
NYX	0:85b3fd62ea1a	6015	* @arg @ref LL_RCC_PLLSAIM_DIV_20
NYX	0:85b3fd62ea1a	6016	* @arg @ref LL_RCC_PLLSAIM_DIV_21
NYX	0:85b3fd62ea1a	6017	* @arg @ref LL_RCC_PLLSAIM_DIV_22
NYX	0:85b3fd62ea1a	6018	* @arg @ref LL_RCC_PLLSAIM_DIV_23
NYX	0:85b3fd62ea1a	6019	* @arg @ref LL_RCC_PLLSAIM_DIV_24
NYX	0:85b3fd62ea1a	6020	* @arg @ref LL_RCC_PLLSAIM_DIV_25
NYX	0:85b3fd62ea1a	6021	* @arg @ref LL_RCC_PLLSAIM_DIV_26
NYX	0:85b3fd62ea1a	6022	* @arg @ref LL_RCC_PLLSAIM_DIV_27
NYX	0:85b3fd62ea1a	6023	* @arg @ref LL_RCC_PLLSAIM_DIV_28
NYX	0:85b3fd62ea1a	6024	* @arg @ref LL_RCC_PLLSAIM_DIV_29
NYX	0:85b3fd62ea1a	6025	* @arg @ref LL_RCC_PLLSAIM_DIV_30
NYX	0:85b3fd62ea1a	6026	* @arg @ref LL_RCC_PLLSAIM_DIV_31
NYX	0:85b3fd62ea1a	6027	* @arg @ref LL_RCC_PLLSAIM_DIV_32
NYX	0:85b3fd62ea1a	6028	* @arg @ref LL_RCC_PLLSAIM_DIV_33
NYX	0:85b3fd62ea1a	6029	* @arg @ref LL_RCC_PLLSAIM_DIV_34
NYX	0:85b3fd62ea1a	6030	* @arg @ref LL_RCC_PLLSAIM_DIV_35
NYX	0:85b3fd62ea1a	6031	* @arg @ref LL_RCC_PLLSAIM_DIV_36
NYX	0:85b3fd62ea1a	6032	* @arg @ref LL_RCC_PLLSAIM_DIV_37
NYX	0:85b3fd62ea1a	6033	* @arg @ref LL_RCC_PLLSAIM_DIV_38
NYX	0:85b3fd62ea1a	6034	* @arg @ref LL_RCC_PLLSAIM_DIV_39
NYX	0:85b3fd62ea1a	6035	* @arg @ref LL_RCC_PLLSAIM_DIV_40
NYX	0:85b3fd62ea1a	6036	* @arg @ref LL_RCC_PLLSAIM_DIV_41
NYX	0:85b3fd62ea1a	6037	* @arg @ref LL_RCC_PLLSAIM_DIV_42
NYX	0:85b3fd62ea1a	6038	* @arg @ref LL_RCC_PLLSAIM_DIV_43
NYX	0:85b3fd62ea1a	6039	* @arg @ref LL_RCC_PLLSAIM_DIV_44
NYX	0:85b3fd62ea1a	6040	* @arg @ref LL_RCC_PLLSAIM_DIV_45
NYX	0:85b3fd62ea1a	6041	* @arg @ref LL_RCC_PLLSAIM_DIV_46
NYX	0:85b3fd62ea1a	6042	* @arg @ref LL_RCC_PLLSAIM_DIV_47
NYX	0:85b3fd62ea1a	6043	* @arg @ref LL_RCC_PLLSAIM_DIV_48
NYX	0:85b3fd62ea1a	6044	* @arg @ref LL_RCC_PLLSAIM_DIV_49
NYX	0:85b3fd62ea1a	6045	* @arg @ref LL_RCC_PLLSAIM_DIV_50
NYX	0:85b3fd62ea1a	6046	* @arg @ref LL_RCC_PLLSAIM_DIV_51
NYX	0:85b3fd62ea1a	6047	* @arg @ref LL_RCC_PLLSAIM_DIV_52
NYX	0:85b3fd62ea1a	6048	* @arg @ref LL_RCC_PLLSAIM_DIV_53
NYX	0:85b3fd62ea1a	6049	* @arg @ref LL_RCC_PLLSAIM_DIV_54
NYX	0:85b3fd62ea1a	6050	* @arg @ref LL_RCC_PLLSAIM_DIV_55
NYX	0:85b3fd62ea1a	6051	* @arg @ref LL_RCC_PLLSAIM_DIV_56
NYX	0:85b3fd62ea1a	6052	* @arg @ref LL_RCC_PLLSAIM_DIV_57
NYX	0:85b3fd62ea1a	6053	* @arg @ref LL_RCC_PLLSAIM_DIV_58
NYX	0:85b3fd62ea1a	6054	* @arg @ref LL_RCC_PLLSAIM_DIV_59
NYX	0:85b3fd62ea1a	6055	* @arg @ref LL_RCC_PLLSAIM_DIV_60
NYX	0:85b3fd62ea1a	6056	* @arg @ref LL_RCC_PLLSAIM_DIV_61
NYX	0:85b3fd62ea1a	6057	* @arg @ref LL_RCC_PLLSAIM_DIV_62
NYX	0:85b3fd62ea1a	6058	* @arg @ref LL_RCC_PLLSAIM_DIV_63
NYX	0:85b3fd62ea1a	6059	* @param PLLN Between 49/50(*) and 432
NYX	0:85b3fd62ea1a	6060	*
NYX	0:85b3fd62ea1a	6061	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	6062	* @param PLLQ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6063	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
NYX	0:85b3fd62ea1a	6064	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
NYX	0:85b3fd62ea1a	6065	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
NYX	0:85b3fd62ea1a	6066	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
NYX	0:85b3fd62ea1a	6067	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
NYX	0:85b3fd62ea1a	6068	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
NYX	0:85b3fd62ea1a	6069	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
NYX	0:85b3fd62ea1a	6070	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
NYX	0:85b3fd62ea1a	6071	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
NYX	0:85b3fd62ea1a	6072	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
NYX	0:85b3fd62ea1a	6073	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
NYX	0:85b3fd62ea1a	6074	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
NYX	0:85b3fd62ea1a	6075	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
NYX	0:85b3fd62ea1a	6076	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
NYX	0:85b3fd62ea1a	6077	* @param PLLDIVQ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6078	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
NYX	0:85b3fd62ea1a	6079	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
NYX	0:85b3fd62ea1a	6080	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
NYX	0:85b3fd62ea1a	6081	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
NYX	0:85b3fd62ea1a	6082	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
NYX	0:85b3fd62ea1a	6083	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
NYX	0:85b3fd62ea1a	6084	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
NYX	0:85b3fd62ea1a	6085	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
NYX	0:85b3fd62ea1a	6086	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
NYX	0:85b3fd62ea1a	6087	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
NYX	0:85b3fd62ea1a	6088	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
NYX	0:85b3fd62ea1a	6089	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
NYX	0:85b3fd62ea1a	6090	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
NYX	0:85b3fd62ea1a	6091	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
NYX	0:85b3fd62ea1a	6092	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
NYX	0:85b3fd62ea1a	6093	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
NYX	0:85b3fd62ea1a	6094	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
NYX	0:85b3fd62ea1a	6095	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
NYX	0:85b3fd62ea1a	6096	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
NYX	0:85b3fd62ea1a	6097	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
NYX	0:85b3fd62ea1a	6098	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
NYX	0:85b3fd62ea1a	6099	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
NYX	0:85b3fd62ea1a	6100	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
NYX	0:85b3fd62ea1a	6101	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
NYX	0:85b3fd62ea1a	6102	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
NYX	0:85b3fd62ea1a	6103	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
NYX	0:85b3fd62ea1a	6104	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
NYX	0:85b3fd62ea1a	6105	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
NYX	0:85b3fd62ea1a	6106	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
NYX	0:85b3fd62ea1a	6107	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
NYX	0:85b3fd62ea1a	6108	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
NYX	0:85b3fd62ea1a	6109	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
NYX	0:85b3fd62ea1a	6110	* @retval None
NYX	0:85b3fd62ea1a	6111	*/
NYX	0:85b3fd62ea1a	6112	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
NYX	0:85b3fd62ea1a	6113	{
NYX	0:85b3fd62ea1a	6114	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
NYX	0:85b3fd62ea1a	6115	#if defined(RCC_PLLSAICFGR_PLLSAIM)
NYX	0:85b3fd62ea1a	6116	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
NYX	0:85b3fd62ea1a	6117	#else
NYX	0:85b3fd62ea1a	6118	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
NYX	0:85b3fd62ea1a	6119	#endif /* RCC_PLLSAICFGR_PLLSAIM */
NYX	0:85b3fd62ea1a	6120	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLQ);
NYX	0:85b3fd62ea1a	6121	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
NYX	0:85b3fd62ea1a	6122	}
NYX	0:85b3fd62ea1a	6123
NYX	0:85b3fd62ea1a	6124	#if defined(RCC_PLLSAICFGR_PLLSAIP)
NYX	0:85b3fd62ea1a	6125	/**
NYX	0:85b3fd62ea1a	6126	* @brief Configure PLLSAI used for 48Mhz domain clock
NYX	0:85b3fd62ea1a	6127	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	6128	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	6129	* @note PLLN/PLLP can be written only when PLLSAI is disabled
NYX	0:85b3fd62ea1a	6130	* @note This can be selected for USB, RNG, SDIO
NYX	0:85b3fd62ea1a	6131	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	6132	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	6133	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	6134	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
NYX	0:85b3fd62ea1a	6135	* PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
NYX	0:85b3fd62ea1a	6136	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6137	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	6138	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	6139	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6140	* @arg @ref LL_RCC_PLLSAIM_DIV_2
NYX	0:85b3fd62ea1a	6141	* @arg @ref LL_RCC_PLLSAIM_DIV_3
NYX	0:85b3fd62ea1a	6142	* @arg @ref LL_RCC_PLLSAIM_DIV_4
NYX	0:85b3fd62ea1a	6143	* @arg @ref LL_RCC_PLLSAIM_DIV_5
NYX	0:85b3fd62ea1a	6144	* @arg @ref LL_RCC_PLLSAIM_DIV_6
NYX	0:85b3fd62ea1a	6145	* @arg @ref LL_RCC_PLLSAIM_DIV_7
NYX	0:85b3fd62ea1a	6146	* @arg @ref LL_RCC_PLLSAIM_DIV_8
NYX	0:85b3fd62ea1a	6147	* @arg @ref LL_RCC_PLLSAIM_DIV_9
NYX	0:85b3fd62ea1a	6148	* @arg @ref LL_RCC_PLLSAIM_DIV_10
NYX	0:85b3fd62ea1a	6149	* @arg @ref LL_RCC_PLLSAIM_DIV_11
NYX	0:85b3fd62ea1a	6150	* @arg @ref LL_RCC_PLLSAIM_DIV_12
NYX	0:85b3fd62ea1a	6151	* @arg @ref LL_RCC_PLLSAIM_DIV_13
NYX	0:85b3fd62ea1a	6152	* @arg @ref LL_RCC_PLLSAIM_DIV_14
NYX	0:85b3fd62ea1a	6153	* @arg @ref LL_RCC_PLLSAIM_DIV_15
NYX	0:85b3fd62ea1a	6154	* @arg @ref LL_RCC_PLLSAIM_DIV_16
NYX	0:85b3fd62ea1a	6155	* @arg @ref LL_RCC_PLLSAIM_DIV_17
NYX	0:85b3fd62ea1a	6156	* @arg @ref LL_RCC_PLLSAIM_DIV_18
NYX	0:85b3fd62ea1a	6157	* @arg @ref LL_RCC_PLLSAIM_DIV_19
NYX	0:85b3fd62ea1a	6158	* @arg @ref LL_RCC_PLLSAIM_DIV_20
NYX	0:85b3fd62ea1a	6159	* @arg @ref LL_RCC_PLLSAIM_DIV_21
NYX	0:85b3fd62ea1a	6160	* @arg @ref LL_RCC_PLLSAIM_DIV_22
NYX	0:85b3fd62ea1a	6161	* @arg @ref LL_RCC_PLLSAIM_DIV_23
NYX	0:85b3fd62ea1a	6162	* @arg @ref LL_RCC_PLLSAIM_DIV_24
NYX	0:85b3fd62ea1a	6163	* @arg @ref LL_RCC_PLLSAIM_DIV_25
NYX	0:85b3fd62ea1a	6164	* @arg @ref LL_RCC_PLLSAIM_DIV_26
NYX	0:85b3fd62ea1a	6165	* @arg @ref LL_RCC_PLLSAIM_DIV_27
NYX	0:85b3fd62ea1a	6166	* @arg @ref LL_RCC_PLLSAIM_DIV_28
NYX	0:85b3fd62ea1a	6167	* @arg @ref LL_RCC_PLLSAIM_DIV_29
NYX	0:85b3fd62ea1a	6168	* @arg @ref LL_RCC_PLLSAIM_DIV_30
NYX	0:85b3fd62ea1a	6169	* @arg @ref LL_RCC_PLLSAIM_DIV_31
NYX	0:85b3fd62ea1a	6170	* @arg @ref LL_RCC_PLLSAIM_DIV_32
NYX	0:85b3fd62ea1a	6171	* @arg @ref LL_RCC_PLLSAIM_DIV_33
NYX	0:85b3fd62ea1a	6172	* @arg @ref LL_RCC_PLLSAIM_DIV_34
NYX	0:85b3fd62ea1a	6173	* @arg @ref LL_RCC_PLLSAIM_DIV_35
NYX	0:85b3fd62ea1a	6174	* @arg @ref LL_RCC_PLLSAIM_DIV_36
NYX	0:85b3fd62ea1a	6175	* @arg @ref LL_RCC_PLLSAIM_DIV_37
NYX	0:85b3fd62ea1a	6176	* @arg @ref LL_RCC_PLLSAIM_DIV_38
NYX	0:85b3fd62ea1a	6177	* @arg @ref LL_RCC_PLLSAIM_DIV_39
NYX	0:85b3fd62ea1a	6178	* @arg @ref LL_RCC_PLLSAIM_DIV_40
NYX	0:85b3fd62ea1a	6179	* @arg @ref LL_RCC_PLLSAIM_DIV_41
NYX	0:85b3fd62ea1a	6180	* @arg @ref LL_RCC_PLLSAIM_DIV_42
NYX	0:85b3fd62ea1a	6181	* @arg @ref LL_RCC_PLLSAIM_DIV_43
NYX	0:85b3fd62ea1a	6182	* @arg @ref LL_RCC_PLLSAIM_DIV_44
NYX	0:85b3fd62ea1a	6183	* @arg @ref LL_RCC_PLLSAIM_DIV_45
NYX	0:85b3fd62ea1a	6184	* @arg @ref LL_RCC_PLLSAIM_DIV_46
NYX	0:85b3fd62ea1a	6185	* @arg @ref LL_RCC_PLLSAIM_DIV_47
NYX	0:85b3fd62ea1a	6186	* @arg @ref LL_RCC_PLLSAIM_DIV_48
NYX	0:85b3fd62ea1a	6187	* @arg @ref LL_RCC_PLLSAIM_DIV_49
NYX	0:85b3fd62ea1a	6188	* @arg @ref LL_RCC_PLLSAIM_DIV_50
NYX	0:85b3fd62ea1a	6189	* @arg @ref LL_RCC_PLLSAIM_DIV_51
NYX	0:85b3fd62ea1a	6190	* @arg @ref LL_RCC_PLLSAIM_DIV_52
NYX	0:85b3fd62ea1a	6191	* @arg @ref LL_RCC_PLLSAIM_DIV_53
NYX	0:85b3fd62ea1a	6192	* @arg @ref LL_RCC_PLLSAIM_DIV_54
NYX	0:85b3fd62ea1a	6193	* @arg @ref LL_RCC_PLLSAIM_DIV_55
NYX	0:85b3fd62ea1a	6194	* @arg @ref LL_RCC_PLLSAIM_DIV_56
NYX	0:85b3fd62ea1a	6195	* @arg @ref LL_RCC_PLLSAIM_DIV_57
NYX	0:85b3fd62ea1a	6196	* @arg @ref LL_RCC_PLLSAIM_DIV_58
NYX	0:85b3fd62ea1a	6197	* @arg @ref LL_RCC_PLLSAIM_DIV_59
NYX	0:85b3fd62ea1a	6198	* @arg @ref LL_RCC_PLLSAIM_DIV_60
NYX	0:85b3fd62ea1a	6199	* @arg @ref LL_RCC_PLLSAIM_DIV_61
NYX	0:85b3fd62ea1a	6200	* @arg @ref LL_RCC_PLLSAIM_DIV_62
NYX	0:85b3fd62ea1a	6201	* @arg @ref LL_RCC_PLLSAIM_DIV_63
NYX	0:85b3fd62ea1a	6202	* @param PLLN Between 50 and 432
NYX	0:85b3fd62ea1a	6203	* @param PLLP This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6204	* @arg @ref LL_RCC_PLLSAIP_DIV_2
NYX	0:85b3fd62ea1a	6205	* @arg @ref LL_RCC_PLLSAIP_DIV_4
NYX	0:85b3fd62ea1a	6206	* @arg @ref LL_RCC_PLLSAIP_DIV_6
NYX	0:85b3fd62ea1a	6207	* @arg @ref LL_RCC_PLLSAIP_DIV_8
NYX	0:85b3fd62ea1a	6208	* @retval None
NYX	0:85b3fd62ea1a	6209	*/
NYX	0:85b3fd62ea1a	6210	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
NYX	0:85b3fd62ea1a	6211	{
NYX	0:85b3fd62ea1a	6212	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
NYX	0:85b3fd62ea1a	6213	#if defined(RCC_PLLSAICFGR_PLLSAIM)
NYX	0:85b3fd62ea1a	6214	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
NYX	0:85b3fd62ea1a	6215	#else
NYX	0:85b3fd62ea1a	6216	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
NYX	0:85b3fd62ea1a	6217	#endif /* RCC_PLLSAICFGR_PLLSAIM */
NYX	0:85b3fd62ea1a	6218	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLP);
NYX	0:85b3fd62ea1a	6219	}
NYX	0:85b3fd62ea1a	6220	#endif /* RCC_PLLSAICFGR_PLLSAIP */
NYX	0:85b3fd62ea1a	6221
NYX	0:85b3fd62ea1a	6222	#if defined(LTDC)
NYX	0:85b3fd62ea1a	6223	/**
NYX	0:85b3fd62ea1a	6224	* @brief Configure PLLSAI used for LTDC domain clock
NYX	0:85b3fd62ea1a	6225	* @note PLL Source and PLLM Divider can be written only when PLL,
NYX	0:85b3fd62ea1a	6226	* PLLI2S and PLLSAI(*) are disabled
NYX	0:85b3fd62ea1a	6227	* @note PLLN/PLLR can be written only when PLLSAI is disabled
NYX	0:85b3fd62ea1a	6228	* @note This can be selected for LTDC
NYX	0:85b3fd62ea1a	6229	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
NYX	0:85b3fd62ea1a	6230	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
NYX	0:85b3fd62ea1a	6231	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
NYX	0:85b3fd62ea1a	6232	* PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
NYX	0:85b3fd62ea1a	6233	* DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
NYX	0:85b3fd62ea1a	6234	* @param Source This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6235	* @arg @ref LL_RCC_PLLSOURCE_HSI
NYX	0:85b3fd62ea1a	6236	* @arg @ref LL_RCC_PLLSOURCE_HSE
NYX	0:85b3fd62ea1a	6237	* @param PLLM This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6238	* @arg @ref LL_RCC_PLLSAIM_DIV_2
NYX	0:85b3fd62ea1a	6239	* @arg @ref LL_RCC_PLLSAIM_DIV_3
NYX	0:85b3fd62ea1a	6240	* @arg @ref LL_RCC_PLLSAIM_DIV_4
NYX	0:85b3fd62ea1a	6241	* @arg @ref LL_RCC_PLLSAIM_DIV_5
NYX	0:85b3fd62ea1a	6242	* @arg @ref LL_RCC_PLLSAIM_DIV_6
NYX	0:85b3fd62ea1a	6243	* @arg @ref LL_RCC_PLLSAIM_DIV_7
NYX	0:85b3fd62ea1a	6244	* @arg @ref LL_RCC_PLLSAIM_DIV_8
NYX	0:85b3fd62ea1a	6245	* @arg @ref LL_RCC_PLLSAIM_DIV_9
NYX	0:85b3fd62ea1a	6246	* @arg @ref LL_RCC_PLLSAIM_DIV_10
NYX	0:85b3fd62ea1a	6247	* @arg @ref LL_RCC_PLLSAIM_DIV_11
NYX	0:85b3fd62ea1a	6248	* @arg @ref LL_RCC_PLLSAIM_DIV_12
NYX	0:85b3fd62ea1a	6249	* @arg @ref LL_RCC_PLLSAIM_DIV_13
NYX	0:85b3fd62ea1a	6250	* @arg @ref LL_RCC_PLLSAIM_DIV_14
NYX	0:85b3fd62ea1a	6251	* @arg @ref LL_RCC_PLLSAIM_DIV_15
NYX	0:85b3fd62ea1a	6252	* @arg @ref LL_RCC_PLLSAIM_DIV_16
NYX	0:85b3fd62ea1a	6253	* @arg @ref LL_RCC_PLLSAIM_DIV_17
NYX	0:85b3fd62ea1a	6254	* @arg @ref LL_RCC_PLLSAIM_DIV_18
NYX	0:85b3fd62ea1a	6255	* @arg @ref LL_RCC_PLLSAIM_DIV_19
NYX	0:85b3fd62ea1a	6256	* @arg @ref LL_RCC_PLLSAIM_DIV_20
NYX	0:85b3fd62ea1a	6257	* @arg @ref LL_RCC_PLLSAIM_DIV_21
NYX	0:85b3fd62ea1a	6258	* @arg @ref LL_RCC_PLLSAIM_DIV_22
NYX	0:85b3fd62ea1a	6259	* @arg @ref LL_RCC_PLLSAIM_DIV_23
NYX	0:85b3fd62ea1a	6260	* @arg @ref LL_RCC_PLLSAIM_DIV_24
NYX	0:85b3fd62ea1a	6261	* @arg @ref LL_RCC_PLLSAIM_DIV_25
NYX	0:85b3fd62ea1a	6262	* @arg @ref LL_RCC_PLLSAIM_DIV_26
NYX	0:85b3fd62ea1a	6263	* @arg @ref LL_RCC_PLLSAIM_DIV_27
NYX	0:85b3fd62ea1a	6264	* @arg @ref LL_RCC_PLLSAIM_DIV_28
NYX	0:85b3fd62ea1a	6265	* @arg @ref LL_RCC_PLLSAIM_DIV_29
NYX	0:85b3fd62ea1a	6266	* @arg @ref LL_RCC_PLLSAIM_DIV_30
NYX	0:85b3fd62ea1a	6267	* @arg @ref LL_RCC_PLLSAIM_DIV_31
NYX	0:85b3fd62ea1a	6268	* @arg @ref LL_RCC_PLLSAIM_DIV_32
NYX	0:85b3fd62ea1a	6269	* @arg @ref LL_RCC_PLLSAIM_DIV_33
NYX	0:85b3fd62ea1a	6270	* @arg @ref LL_RCC_PLLSAIM_DIV_34
NYX	0:85b3fd62ea1a	6271	* @arg @ref LL_RCC_PLLSAIM_DIV_35
NYX	0:85b3fd62ea1a	6272	* @arg @ref LL_RCC_PLLSAIM_DIV_36
NYX	0:85b3fd62ea1a	6273	* @arg @ref LL_RCC_PLLSAIM_DIV_37
NYX	0:85b3fd62ea1a	6274	* @arg @ref LL_RCC_PLLSAIM_DIV_38
NYX	0:85b3fd62ea1a	6275	* @arg @ref LL_RCC_PLLSAIM_DIV_39
NYX	0:85b3fd62ea1a	6276	* @arg @ref LL_RCC_PLLSAIM_DIV_40
NYX	0:85b3fd62ea1a	6277	* @arg @ref LL_RCC_PLLSAIM_DIV_41
NYX	0:85b3fd62ea1a	6278	* @arg @ref LL_RCC_PLLSAIM_DIV_42
NYX	0:85b3fd62ea1a	6279	* @arg @ref LL_RCC_PLLSAIM_DIV_43
NYX	0:85b3fd62ea1a	6280	* @arg @ref LL_RCC_PLLSAIM_DIV_44
NYX	0:85b3fd62ea1a	6281	* @arg @ref LL_RCC_PLLSAIM_DIV_45
NYX	0:85b3fd62ea1a	6282	* @arg @ref LL_RCC_PLLSAIM_DIV_46
NYX	0:85b3fd62ea1a	6283	* @arg @ref LL_RCC_PLLSAIM_DIV_47
NYX	0:85b3fd62ea1a	6284	* @arg @ref LL_RCC_PLLSAIM_DIV_48
NYX	0:85b3fd62ea1a	6285	* @arg @ref LL_RCC_PLLSAIM_DIV_49
NYX	0:85b3fd62ea1a	6286	* @arg @ref LL_RCC_PLLSAIM_DIV_50
NYX	0:85b3fd62ea1a	6287	* @arg @ref LL_RCC_PLLSAIM_DIV_51
NYX	0:85b3fd62ea1a	6288	* @arg @ref LL_RCC_PLLSAIM_DIV_52
NYX	0:85b3fd62ea1a	6289	* @arg @ref LL_RCC_PLLSAIM_DIV_53
NYX	0:85b3fd62ea1a	6290	* @arg @ref LL_RCC_PLLSAIM_DIV_54
NYX	0:85b3fd62ea1a	6291	* @arg @ref LL_RCC_PLLSAIM_DIV_55
NYX	0:85b3fd62ea1a	6292	* @arg @ref LL_RCC_PLLSAIM_DIV_56
NYX	0:85b3fd62ea1a	6293	* @arg @ref LL_RCC_PLLSAIM_DIV_57
NYX	0:85b3fd62ea1a	6294	* @arg @ref LL_RCC_PLLSAIM_DIV_58
NYX	0:85b3fd62ea1a	6295	* @arg @ref LL_RCC_PLLSAIM_DIV_59
NYX	0:85b3fd62ea1a	6296	* @arg @ref LL_RCC_PLLSAIM_DIV_60
NYX	0:85b3fd62ea1a	6297	* @arg @ref LL_RCC_PLLSAIM_DIV_61
NYX	0:85b3fd62ea1a	6298	* @arg @ref LL_RCC_PLLSAIM_DIV_62
NYX	0:85b3fd62ea1a	6299	* @arg @ref LL_RCC_PLLSAIM_DIV_63
NYX	0:85b3fd62ea1a	6300	* @param PLLN Between 49/50(*) and 432
NYX	0:85b3fd62ea1a	6301	*
NYX	0:85b3fd62ea1a	6302	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	6303	* @param PLLR This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6304	* @arg @ref LL_RCC_PLLSAIR_DIV_2
NYX	0:85b3fd62ea1a	6305	* @arg @ref LL_RCC_PLLSAIR_DIV_3
NYX	0:85b3fd62ea1a	6306	* @arg @ref LL_RCC_PLLSAIR_DIV_4
NYX	0:85b3fd62ea1a	6307	* @arg @ref LL_RCC_PLLSAIR_DIV_5
NYX	0:85b3fd62ea1a	6308	* @arg @ref LL_RCC_PLLSAIR_DIV_6
NYX	0:85b3fd62ea1a	6309	* @arg @ref LL_RCC_PLLSAIR_DIV_7
NYX	0:85b3fd62ea1a	6310	* @param PLLDIVR This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	6311	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
NYX	0:85b3fd62ea1a	6312	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
NYX	0:85b3fd62ea1a	6313	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
NYX	0:85b3fd62ea1a	6314	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
NYX	0:85b3fd62ea1a	6315	* @retval None
NYX	0:85b3fd62ea1a	6316	*/
NYX	0:85b3fd62ea1a	6317	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
NYX	0:85b3fd62ea1a	6318	{
NYX	0:85b3fd62ea1a	6319	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
NYX	0:85b3fd62ea1a	6320	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLR);
NYX	0:85b3fd62ea1a	6321	MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
NYX	0:85b3fd62ea1a	6322	}
NYX	0:85b3fd62ea1a	6323	#endif /* LTDC */
NYX	0:85b3fd62ea1a	6324
NYX	0:85b3fd62ea1a	6325	/**
NYX	0:85b3fd62ea1a	6326	* @brief Get division factor for PLLSAI input clock
NYX	0:85b3fd62ea1a	6327	* @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
NYX	0:85b3fd62ea1a	6328	* PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
NYX	0:85b3fd62ea1a	6329	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	6330	* @arg @ref LL_RCC_PLLSAIM_DIV_2
NYX	0:85b3fd62ea1a	6331	* @arg @ref LL_RCC_PLLSAIM_DIV_3
NYX	0:85b3fd62ea1a	6332	* @arg @ref LL_RCC_PLLSAIM_DIV_4
NYX	0:85b3fd62ea1a	6333	* @arg @ref LL_RCC_PLLSAIM_DIV_5
NYX	0:85b3fd62ea1a	6334	* @arg @ref LL_RCC_PLLSAIM_DIV_6
NYX	0:85b3fd62ea1a	6335	* @arg @ref LL_RCC_PLLSAIM_DIV_7
NYX	0:85b3fd62ea1a	6336	* @arg @ref LL_RCC_PLLSAIM_DIV_8
NYX	0:85b3fd62ea1a	6337	* @arg @ref LL_RCC_PLLSAIM_DIV_9
NYX	0:85b3fd62ea1a	6338	* @arg @ref LL_RCC_PLLSAIM_DIV_10
NYX	0:85b3fd62ea1a	6339	* @arg @ref LL_RCC_PLLSAIM_DIV_11
NYX	0:85b3fd62ea1a	6340	* @arg @ref LL_RCC_PLLSAIM_DIV_12
NYX	0:85b3fd62ea1a	6341	* @arg @ref LL_RCC_PLLSAIM_DIV_13
NYX	0:85b3fd62ea1a	6342	* @arg @ref LL_RCC_PLLSAIM_DIV_14
NYX	0:85b3fd62ea1a	6343	* @arg @ref LL_RCC_PLLSAIM_DIV_15
NYX	0:85b3fd62ea1a	6344	* @arg @ref LL_RCC_PLLSAIM_DIV_16
NYX	0:85b3fd62ea1a	6345	* @arg @ref LL_RCC_PLLSAIM_DIV_17
NYX	0:85b3fd62ea1a	6346	* @arg @ref LL_RCC_PLLSAIM_DIV_18
NYX	0:85b3fd62ea1a	6347	* @arg @ref LL_RCC_PLLSAIM_DIV_19
NYX	0:85b3fd62ea1a	6348	* @arg @ref LL_RCC_PLLSAIM_DIV_20
NYX	0:85b3fd62ea1a	6349	* @arg @ref LL_RCC_PLLSAIM_DIV_21
NYX	0:85b3fd62ea1a	6350	* @arg @ref LL_RCC_PLLSAIM_DIV_22
NYX	0:85b3fd62ea1a	6351	* @arg @ref LL_RCC_PLLSAIM_DIV_23
NYX	0:85b3fd62ea1a	6352	* @arg @ref LL_RCC_PLLSAIM_DIV_24
NYX	0:85b3fd62ea1a	6353	* @arg @ref LL_RCC_PLLSAIM_DIV_25
NYX	0:85b3fd62ea1a	6354	* @arg @ref LL_RCC_PLLSAIM_DIV_26
NYX	0:85b3fd62ea1a	6355	* @arg @ref LL_RCC_PLLSAIM_DIV_27
NYX	0:85b3fd62ea1a	6356	* @arg @ref LL_RCC_PLLSAIM_DIV_28
NYX	0:85b3fd62ea1a	6357	* @arg @ref LL_RCC_PLLSAIM_DIV_29
NYX	0:85b3fd62ea1a	6358	* @arg @ref LL_RCC_PLLSAIM_DIV_30
NYX	0:85b3fd62ea1a	6359	* @arg @ref LL_RCC_PLLSAIM_DIV_31
NYX	0:85b3fd62ea1a	6360	* @arg @ref LL_RCC_PLLSAIM_DIV_32
NYX	0:85b3fd62ea1a	6361	* @arg @ref LL_RCC_PLLSAIM_DIV_33
NYX	0:85b3fd62ea1a	6362	* @arg @ref LL_RCC_PLLSAIM_DIV_34
NYX	0:85b3fd62ea1a	6363	* @arg @ref LL_RCC_PLLSAIM_DIV_35
NYX	0:85b3fd62ea1a	6364	* @arg @ref LL_RCC_PLLSAIM_DIV_36
NYX	0:85b3fd62ea1a	6365	* @arg @ref LL_RCC_PLLSAIM_DIV_37
NYX	0:85b3fd62ea1a	6366	* @arg @ref LL_RCC_PLLSAIM_DIV_38
NYX	0:85b3fd62ea1a	6367	* @arg @ref LL_RCC_PLLSAIM_DIV_39
NYX	0:85b3fd62ea1a	6368	* @arg @ref LL_RCC_PLLSAIM_DIV_40
NYX	0:85b3fd62ea1a	6369	* @arg @ref LL_RCC_PLLSAIM_DIV_41
NYX	0:85b3fd62ea1a	6370	* @arg @ref LL_RCC_PLLSAIM_DIV_42
NYX	0:85b3fd62ea1a	6371	* @arg @ref LL_RCC_PLLSAIM_DIV_43
NYX	0:85b3fd62ea1a	6372	* @arg @ref LL_RCC_PLLSAIM_DIV_44
NYX	0:85b3fd62ea1a	6373	* @arg @ref LL_RCC_PLLSAIM_DIV_45
NYX	0:85b3fd62ea1a	6374	* @arg @ref LL_RCC_PLLSAIM_DIV_46
NYX	0:85b3fd62ea1a	6375	* @arg @ref LL_RCC_PLLSAIM_DIV_47
NYX	0:85b3fd62ea1a	6376	* @arg @ref LL_RCC_PLLSAIM_DIV_48
NYX	0:85b3fd62ea1a	6377	* @arg @ref LL_RCC_PLLSAIM_DIV_49
NYX	0:85b3fd62ea1a	6378	* @arg @ref LL_RCC_PLLSAIM_DIV_50
NYX	0:85b3fd62ea1a	6379	* @arg @ref LL_RCC_PLLSAIM_DIV_51
NYX	0:85b3fd62ea1a	6380	* @arg @ref LL_RCC_PLLSAIM_DIV_52
NYX	0:85b3fd62ea1a	6381	* @arg @ref LL_RCC_PLLSAIM_DIV_53
NYX	0:85b3fd62ea1a	6382	* @arg @ref LL_RCC_PLLSAIM_DIV_54
NYX	0:85b3fd62ea1a	6383	* @arg @ref LL_RCC_PLLSAIM_DIV_55
NYX	0:85b3fd62ea1a	6384	* @arg @ref LL_RCC_PLLSAIM_DIV_56
NYX	0:85b3fd62ea1a	6385	* @arg @ref LL_RCC_PLLSAIM_DIV_57
NYX	0:85b3fd62ea1a	6386	* @arg @ref LL_RCC_PLLSAIM_DIV_58
NYX	0:85b3fd62ea1a	6387	* @arg @ref LL_RCC_PLLSAIM_DIV_59
NYX	0:85b3fd62ea1a	6388	* @arg @ref LL_RCC_PLLSAIM_DIV_60
NYX	0:85b3fd62ea1a	6389	* @arg @ref LL_RCC_PLLSAIM_DIV_61
NYX	0:85b3fd62ea1a	6390	* @arg @ref LL_RCC_PLLSAIM_DIV_62
NYX	0:85b3fd62ea1a	6391	* @arg @ref LL_RCC_PLLSAIM_DIV_63
NYX	0:85b3fd62ea1a	6392	*/
NYX	0:85b3fd62ea1a	6393	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
NYX	0:85b3fd62ea1a	6394	{
NYX	0:85b3fd62ea1a	6395	#if defined(RCC_PLLSAICFGR_PLLSAIM)
NYX	0:85b3fd62ea1a	6396	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
NYX	0:85b3fd62ea1a	6397	#else
NYX	0:85b3fd62ea1a	6398	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
NYX	0:85b3fd62ea1a	6399	#endif /* RCC_PLLSAICFGR_PLLSAIM */
NYX	0:85b3fd62ea1a	6400	}
NYX	0:85b3fd62ea1a	6401
NYX	0:85b3fd62ea1a	6402	/**
NYX	0:85b3fd62ea1a	6403	* @brief Get SAIPLL multiplication factor for VCO
NYX	0:85b3fd62ea1a	6404	* @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
NYX	0:85b3fd62ea1a	6405	* @retval Between 49/50(*) and 432
NYX	0:85b3fd62ea1a	6406	*
NYX	0:85b3fd62ea1a	6407	* (*) value not defined in all devices.
NYX	0:85b3fd62ea1a	6408	*/
NYX	0:85b3fd62ea1a	6409	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
NYX	0:85b3fd62ea1a	6410	{
NYX	0:85b3fd62ea1a	6411	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
NYX	0:85b3fd62ea1a	6412	}
NYX	0:85b3fd62ea1a	6413
NYX	0:85b3fd62ea1a	6414	/**
NYX	0:85b3fd62ea1a	6415	* @brief Get SAIPLL division factor for PLLSAIQ
NYX	0:85b3fd62ea1a	6416	* @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
NYX	0:85b3fd62ea1a	6417	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	6418	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
NYX	0:85b3fd62ea1a	6419	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
NYX	0:85b3fd62ea1a	6420	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
NYX	0:85b3fd62ea1a	6421	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
NYX	0:85b3fd62ea1a	6422	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
NYX	0:85b3fd62ea1a	6423	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
NYX	0:85b3fd62ea1a	6424	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
NYX	0:85b3fd62ea1a	6425	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
NYX	0:85b3fd62ea1a	6426	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
NYX	0:85b3fd62ea1a	6427	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
NYX	0:85b3fd62ea1a	6428	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
NYX	0:85b3fd62ea1a	6429	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
NYX	0:85b3fd62ea1a	6430	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
NYX	0:85b3fd62ea1a	6431	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
NYX	0:85b3fd62ea1a	6432	*/
NYX	0:85b3fd62ea1a	6433	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
NYX	0:85b3fd62ea1a	6434	{
NYX	0:85b3fd62ea1a	6435	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
NYX	0:85b3fd62ea1a	6436	}
NYX	0:85b3fd62ea1a	6437
NYX	0:85b3fd62ea1a	6438	#if defined(RCC_PLLSAICFGR_PLLSAIR)
NYX	0:85b3fd62ea1a	6439	/**
NYX	0:85b3fd62ea1a	6440	* @brief Get SAIPLL division factor for PLLSAIR
NYX	0:85b3fd62ea1a	6441	* @note used for PLLSAICLK (SAI clock)
NYX	0:85b3fd62ea1a	6442	* @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
NYX	0:85b3fd62ea1a	6443	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	6444	* @arg @ref LL_RCC_PLLSAIR_DIV_2
NYX	0:85b3fd62ea1a	6445	* @arg @ref LL_RCC_PLLSAIR_DIV_3
NYX	0:85b3fd62ea1a	6446	* @arg @ref LL_RCC_PLLSAIR_DIV_4
NYX	0:85b3fd62ea1a	6447	* @arg @ref LL_RCC_PLLSAIR_DIV_5
NYX	0:85b3fd62ea1a	6448	* @arg @ref LL_RCC_PLLSAIR_DIV_6
NYX	0:85b3fd62ea1a	6449	* @arg @ref LL_RCC_PLLSAIR_DIV_7
NYX	0:85b3fd62ea1a	6450	*/
NYX	0:85b3fd62ea1a	6451	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
NYX	0:85b3fd62ea1a	6452	{
NYX	0:85b3fd62ea1a	6453	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
NYX	0:85b3fd62ea1a	6454	}
NYX	0:85b3fd62ea1a	6455	#endif /* RCC_PLLSAICFGR_PLLSAIR */
NYX	0:85b3fd62ea1a	6456
NYX	0:85b3fd62ea1a	6457	#if defined(RCC_PLLSAICFGR_PLLSAIP)
NYX	0:85b3fd62ea1a	6458	/**
NYX	0:85b3fd62ea1a	6459	* @brief Get SAIPLL division factor for PLLSAIP
NYX	0:85b3fd62ea1a	6460	* @note used for PLL48MCLK (48M domain clock)
NYX	0:85b3fd62ea1a	6461	* @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
NYX	0:85b3fd62ea1a	6462	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	6463	* @arg @ref LL_RCC_PLLSAIP_DIV_2
NYX	0:85b3fd62ea1a	6464	* @arg @ref LL_RCC_PLLSAIP_DIV_4
NYX	0:85b3fd62ea1a	6465	* @arg @ref LL_RCC_PLLSAIP_DIV_6
NYX	0:85b3fd62ea1a	6466	* @arg @ref LL_RCC_PLLSAIP_DIV_8
NYX	0:85b3fd62ea1a	6467	*/
NYX	0:85b3fd62ea1a	6468	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
NYX	0:85b3fd62ea1a	6469	{
NYX	0:85b3fd62ea1a	6470	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
NYX	0:85b3fd62ea1a	6471	}
NYX	0:85b3fd62ea1a	6472	#endif /* RCC_PLLSAICFGR_PLLSAIP */
NYX	0:85b3fd62ea1a	6473
NYX	0:85b3fd62ea1a	6474	/**
NYX	0:85b3fd62ea1a	6475	* @brief Get SAIPLL division factor for PLLSAIDIVQ
NYX	0:85b3fd62ea1a	6476	* @note used PLLSAICLK selected (SAI clock)
NYX	0:85b3fd62ea1a	6477	* @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
NYX	0:85b3fd62ea1a	6478	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	6479	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
NYX	0:85b3fd62ea1a	6480	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
NYX	0:85b3fd62ea1a	6481	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
NYX	0:85b3fd62ea1a	6482	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
NYX	0:85b3fd62ea1a	6483	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
NYX	0:85b3fd62ea1a	6484	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
NYX	0:85b3fd62ea1a	6485	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
NYX	0:85b3fd62ea1a	6486	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
NYX	0:85b3fd62ea1a	6487	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
NYX	0:85b3fd62ea1a	6488	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
NYX	0:85b3fd62ea1a	6489	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
NYX	0:85b3fd62ea1a	6490	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
NYX	0:85b3fd62ea1a	6491	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
NYX	0:85b3fd62ea1a	6492	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
NYX	0:85b3fd62ea1a	6493	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
NYX	0:85b3fd62ea1a	6494	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
NYX	0:85b3fd62ea1a	6495	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
NYX	0:85b3fd62ea1a	6496	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
NYX	0:85b3fd62ea1a	6497	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
NYX	0:85b3fd62ea1a	6498	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
NYX	0:85b3fd62ea1a	6499	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
NYX	0:85b3fd62ea1a	6500	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
NYX	0:85b3fd62ea1a	6501	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
NYX	0:85b3fd62ea1a	6502	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
NYX	0:85b3fd62ea1a	6503	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
NYX	0:85b3fd62ea1a	6504	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
NYX	0:85b3fd62ea1a	6505	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
NYX	0:85b3fd62ea1a	6506	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
NYX	0:85b3fd62ea1a	6507	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
NYX	0:85b3fd62ea1a	6508	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
NYX	0:85b3fd62ea1a	6509	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
NYX	0:85b3fd62ea1a	6510	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
NYX	0:85b3fd62ea1a	6511	*/
NYX	0:85b3fd62ea1a	6512	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
NYX	0:85b3fd62ea1a	6513	{
NYX	0:85b3fd62ea1a	6514	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
NYX	0:85b3fd62ea1a	6515	}
NYX	0:85b3fd62ea1a	6516
NYX	0:85b3fd62ea1a	6517	#if defined(RCC_DCKCFGR_PLLSAIDIVR)
NYX	0:85b3fd62ea1a	6518	/**
NYX	0:85b3fd62ea1a	6519	* @brief Get SAIPLL division factor for PLLSAIDIVR
NYX	0:85b3fd62ea1a	6520	* @note used for LTDC domain clock
NYX	0:85b3fd62ea1a	6521	* @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
NYX	0:85b3fd62ea1a	6522	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	6523	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
NYX	0:85b3fd62ea1a	6524	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
NYX	0:85b3fd62ea1a	6525	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
NYX	0:85b3fd62ea1a	6526	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
NYX	0:85b3fd62ea1a	6527	*/
NYX	0:85b3fd62ea1a	6528	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
NYX	0:85b3fd62ea1a	6529	{
NYX	0:85b3fd62ea1a	6530	return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
NYX	0:85b3fd62ea1a	6531	}
NYX	0:85b3fd62ea1a	6532	#endif /* RCC_DCKCFGR_PLLSAIDIVR */
NYX	0:85b3fd62ea1a	6533
NYX	0:85b3fd62ea1a	6534	/**
NYX	0:85b3fd62ea1a	6535	* @}
NYX	0:85b3fd62ea1a	6536	*/
NYX	0:85b3fd62ea1a	6537	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	6538
NYX	0:85b3fd62ea1a	6539	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
NYX	0:85b3fd62ea1a	6540	* @{
NYX	0:85b3fd62ea1a	6541	*/
NYX	0:85b3fd62ea1a	6542
NYX	0:85b3fd62ea1a	6543	/**
NYX	0:85b3fd62ea1a	6544	* @brief Clear LSI ready interrupt flag
NYX	0:85b3fd62ea1a	6545	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
NYX	0:85b3fd62ea1a	6546	* @retval None
NYX	0:85b3fd62ea1a	6547	*/
NYX	0:85b3fd62ea1a	6548	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
NYX	0:85b3fd62ea1a	6549	{
NYX	0:85b3fd62ea1a	6550	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
NYX	0:85b3fd62ea1a	6551	}
NYX	0:85b3fd62ea1a	6552
NYX	0:85b3fd62ea1a	6553	/**
NYX	0:85b3fd62ea1a	6554	* @brief Clear LSE ready interrupt flag
NYX	0:85b3fd62ea1a	6555	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
NYX	0:85b3fd62ea1a	6556	* @retval None
NYX	0:85b3fd62ea1a	6557	*/
NYX	0:85b3fd62ea1a	6558	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
NYX	0:85b3fd62ea1a	6559	{
NYX	0:85b3fd62ea1a	6560	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
NYX	0:85b3fd62ea1a	6561	}
NYX	0:85b3fd62ea1a	6562
NYX	0:85b3fd62ea1a	6563	/**
NYX	0:85b3fd62ea1a	6564	* @brief Clear HSI ready interrupt flag
NYX	0:85b3fd62ea1a	6565	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
NYX	0:85b3fd62ea1a	6566	* @retval None
NYX	0:85b3fd62ea1a	6567	*/
NYX	0:85b3fd62ea1a	6568	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
NYX	0:85b3fd62ea1a	6569	{
NYX	0:85b3fd62ea1a	6570	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
NYX	0:85b3fd62ea1a	6571	}
NYX	0:85b3fd62ea1a	6572
NYX	0:85b3fd62ea1a	6573	/**
NYX	0:85b3fd62ea1a	6574	* @brief Clear HSE ready interrupt flag
NYX	0:85b3fd62ea1a	6575	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
NYX	0:85b3fd62ea1a	6576	* @retval None
NYX	0:85b3fd62ea1a	6577	*/
NYX	0:85b3fd62ea1a	6578	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
NYX	0:85b3fd62ea1a	6579	{
NYX	0:85b3fd62ea1a	6580	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
NYX	0:85b3fd62ea1a	6581	}
NYX	0:85b3fd62ea1a	6582
NYX	0:85b3fd62ea1a	6583	/**
NYX	0:85b3fd62ea1a	6584	* @brief Clear PLL ready interrupt flag
NYX	0:85b3fd62ea1a	6585	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
NYX	0:85b3fd62ea1a	6586	* @retval None
NYX	0:85b3fd62ea1a	6587	*/
NYX	0:85b3fd62ea1a	6588	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
NYX	0:85b3fd62ea1a	6589	{
NYX	0:85b3fd62ea1a	6590	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
NYX	0:85b3fd62ea1a	6591	}
NYX	0:85b3fd62ea1a	6592
NYX	0:85b3fd62ea1a	6593	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	6594	/**
NYX	0:85b3fd62ea1a	6595	* @brief Clear PLLI2S ready interrupt flag
NYX	0:85b3fd62ea1a	6596	* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
NYX	0:85b3fd62ea1a	6597	* @retval None
NYX	0:85b3fd62ea1a	6598	*/
NYX	0:85b3fd62ea1a	6599	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
NYX	0:85b3fd62ea1a	6600	{
NYX	0:85b3fd62ea1a	6601	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
NYX	0:85b3fd62ea1a	6602	}
NYX	0:85b3fd62ea1a	6603
NYX	0:85b3fd62ea1a	6604	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	6605
NYX	0:85b3fd62ea1a	6606	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	6607	/**
NYX	0:85b3fd62ea1a	6608	* @brief Clear PLLSAI ready interrupt flag
NYX	0:85b3fd62ea1a	6609	* @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
NYX	0:85b3fd62ea1a	6610	* @retval None
NYX	0:85b3fd62ea1a	6611	*/
NYX	0:85b3fd62ea1a	6612	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
NYX	0:85b3fd62ea1a	6613	{
NYX	0:85b3fd62ea1a	6614	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
NYX	0:85b3fd62ea1a	6615	}
NYX	0:85b3fd62ea1a	6616
NYX	0:85b3fd62ea1a	6617	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	6618
NYX	0:85b3fd62ea1a	6619	/**
NYX	0:85b3fd62ea1a	6620	* @brief Clear Clock security system interrupt flag
NYX	0:85b3fd62ea1a	6621	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
NYX	0:85b3fd62ea1a	6622	* @retval None
NYX	0:85b3fd62ea1a	6623	*/
NYX	0:85b3fd62ea1a	6624	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
NYX	0:85b3fd62ea1a	6625	{
NYX	0:85b3fd62ea1a	6626	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
NYX	0:85b3fd62ea1a	6627	}
NYX	0:85b3fd62ea1a	6628
NYX	0:85b3fd62ea1a	6629	/**
NYX	0:85b3fd62ea1a	6630	* @brief Check if LSI ready interrupt occurred or not
NYX	0:85b3fd62ea1a	6631	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
NYX	0:85b3fd62ea1a	6632	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6633	*/
NYX	0:85b3fd62ea1a	6634	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
NYX	0:85b3fd62ea1a	6635	{
NYX	0:85b3fd62ea1a	6636	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
NYX	0:85b3fd62ea1a	6637	}
NYX	0:85b3fd62ea1a	6638
NYX	0:85b3fd62ea1a	6639	/**
NYX	0:85b3fd62ea1a	6640	* @brief Check if LSE ready interrupt occurred or not
NYX	0:85b3fd62ea1a	6641	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
NYX	0:85b3fd62ea1a	6642	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6643	*/
NYX	0:85b3fd62ea1a	6644	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
NYX	0:85b3fd62ea1a	6645	{
NYX	0:85b3fd62ea1a	6646	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
NYX	0:85b3fd62ea1a	6647	}
NYX	0:85b3fd62ea1a	6648
NYX	0:85b3fd62ea1a	6649	/**
NYX	0:85b3fd62ea1a	6650	* @brief Check if HSI ready interrupt occurred or not
NYX	0:85b3fd62ea1a	6651	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
NYX	0:85b3fd62ea1a	6652	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6653	*/
NYX	0:85b3fd62ea1a	6654	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
NYX	0:85b3fd62ea1a	6655	{
NYX	0:85b3fd62ea1a	6656	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
NYX	0:85b3fd62ea1a	6657	}
NYX	0:85b3fd62ea1a	6658
NYX	0:85b3fd62ea1a	6659	/**
NYX	0:85b3fd62ea1a	6660	* @brief Check if HSE ready interrupt occurred or not
NYX	0:85b3fd62ea1a	6661	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
NYX	0:85b3fd62ea1a	6662	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6663	*/
NYX	0:85b3fd62ea1a	6664	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
NYX	0:85b3fd62ea1a	6665	{
NYX	0:85b3fd62ea1a	6666	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
NYX	0:85b3fd62ea1a	6667	}
NYX	0:85b3fd62ea1a	6668
NYX	0:85b3fd62ea1a	6669	/**
NYX	0:85b3fd62ea1a	6670	* @brief Check if PLL ready interrupt occurred or not
NYX	0:85b3fd62ea1a	6671	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
NYX	0:85b3fd62ea1a	6672	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6673	*/
NYX	0:85b3fd62ea1a	6674	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
NYX	0:85b3fd62ea1a	6675	{
NYX	0:85b3fd62ea1a	6676	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
NYX	0:85b3fd62ea1a	6677	}
NYX	0:85b3fd62ea1a	6678
NYX	0:85b3fd62ea1a	6679	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	6680	/**
NYX	0:85b3fd62ea1a	6681	* @brief Check if PLLI2S ready interrupt occurred or not
NYX	0:85b3fd62ea1a	6682	* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
NYX	0:85b3fd62ea1a	6683	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6684	*/
NYX	0:85b3fd62ea1a	6685	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
NYX	0:85b3fd62ea1a	6686	{
NYX	0:85b3fd62ea1a	6687	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
NYX	0:85b3fd62ea1a	6688	}
NYX	0:85b3fd62ea1a	6689	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	6690
NYX	0:85b3fd62ea1a	6691	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	6692	/**
NYX	0:85b3fd62ea1a	6693	* @brief Check if PLLSAI ready interrupt occurred or not
NYX	0:85b3fd62ea1a	6694	* @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
NYX	0:85b3fd62ea1a	6695	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6696	*/
NYX	0:85b3fd62ea1a	6697	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
NYX	0:85b3fd62ea1a	6698	{
NYX	0:85b3fd62ea1a	6699	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
NYX	0:85b3fd62ea1a	6700	}
NYX	0:85b3fd62ea1a	6701	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	6702
NYX	0:85b3fd62ea1a	6703	/**
NYX	0:85b3fd62ea1a	6704	* @brief Check if Clock security system interrupt occurred or not
NYX	0:85b3fd62ea1a	6705	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
NYX	0:85b3fd62ea1a	6706	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6707	*/
NYX	0:85b3fd62ea1a	6708	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
NYX	0:85b3fd62ea1a	6709	{
NYX	0:85b3fd62ea1a	6710	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
NYX	0:85b3fd62ea1a	6711	}
NYX	0:85b3fd62ea1a	6712
NYX	0:85b3fd62ea1a	6713	/**
NYX	0:85b3fd62ea1a	6714	* @brief Check if RCC flag Independent Watchdog reset is set or not.
NYX	0:85b3fd62ea1a	6715	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
NYX	0:85b3fd62ea1a	6716	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6717	*/
NYX	0:85b3fd62ea1a	6718	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
NYX	0:85b3fd62ea1a	6719	{
NYX	0:85b3fd62ea1a	6720	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
NYX	0:85b3fd62ea1a	6721	}
NYX	0:85b3fd62ea1a	6722
NYX	0:85b3fd62ea1a	6723	/**
NYX	0:85b3fd62ea1a	6724	* @brief Check if RCC flag Low Power reset is set or not.
NYX	0:85b3fd62ea1a	6725	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
NYX	0:85b3fd62ea1a	6726	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6727	*/
NYX	0:85b3fd62ea1a	6728	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
NYX	0:85b3fd62ea1a	6729	{
NYX	0:85b3fd62ea1a	6730	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
NYX	0:85b3fd62ea1a	6731	}
NYX	0:85b3fd62ea1a	6732
NYX	0:85b3fd62ea1a	6733	/**
NYX	0:85b3fd62ea1a	6734	* @brief Check if RCC flag Pin reset is set or not.
NYX	0:85b3fd62ea1a	6735	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
NYX	0:85b3fd62ea1a	6736	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6737	*/
NYX	0:85b3fd62ea1a	6738	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
NYX	0:85b3fd62ea1a	6739	{
NYX	0:85b3fd62ea1a	6740	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
NYX	0:85b3fd62ea1a	6741	}
NYX	0:85b3fd62ea1a	6742
NYX	0:85b3fd62ea1a	6743	/**
NYX	0:85b3fd62ea1a	6744	* @brief Check if RCC flag POR/PDR reset is set or not.
NYX	0:85b3fd62ea1a	6745	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
NYX	0:85b3fd62ea1a	6746	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6747	*/
NYX	0:85b3fd62ea1a	6748	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
NYX	0:85b3fd62ea1a	6749	{
NYX	0:85b3fd62ea1a	6750	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
NYX	0:85b3fd62ea1a	6751	}
NYX	0:85b3fd62ea1a	6752
NYX	0:85b3fd62ea1a	6753	/**
NYX	0:85b3fd62ea1a	6754	* @brief Check if RCC flag Software reset is set or not.
NYX	0:85b3fd62ea1a	6755	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
NYX	0:85b3fd62ea1a	6756	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6757	*/
NYX	0:85b3fd62ea1a	6758	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
NYX	0:85b3fd62ea1a	6759	{
NYX	0:85b3fd62ea1a	6760	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
NYX	0:85b3fd62ea1a	6761	}
NYX	0:85b3fd62ea1a	6762
NYX	0:85b3fd62ea1a	6763	/**
NYX	0:85b3fd62ea1a	6764	* @brief Check if RCC flag Window Watchdog reset is set or not.
NYX	0:85b3fd62ea1a	6765	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
NYX	0:85b3fd62ea1a	6766	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6767	*/
NYX	0:85b3fd62ea1a	6768	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
NYX	0:85b3fd62ea1a	6769	{
NYX	0:85b3fd62ea1a	6770	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
NYX	0:85b3fd62ea1a	6771	}
NYX	0:85b3fd62ea1a	6772
NYX	0:85b3fd62ea1a	6773	#if defined(RCC_CSR_BORRSTF)
NYX	0:85b3fd62ea1a	6774	/**
NYX	0:85b3fd62ea1a	6775	* @brief Check if RCC flag BOR reset is set or not.
NYX	0:85b3fd62ea1a	6776	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
NYX	0:85b3fd62ea1a	6777	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6778	*/
NYX	0:85b3fd62ea1a	6779	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
NYX	0:85b3fd62ea1a	6780	{
NYX	0:85b3fd62ea1a	6781	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
NYX	0:85b3fd62ea1a	6782	}
NYX	0:85b3fd62ea1a	6783	#endif /* RCC_CSR_BORRSTF */
NYX	0:85b3fd62ea1a	6784
NYX	0:85b3fd62ea1a	6785	/**
NYX	0:85b3fd62ea1a	6786	* @brief Set RMVF bit to clear the reset flags.
NYX	0:85b3fd62ea1a	6787	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
NYX	0:85b3fd62ea1a	6788	* @retval None
NYX	0:85b3fd62ea1a	6789	*/
NYX	0:85b3fd62ea1a	6790	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
NYX	0:85b3fd62ea1a	6791	{
NYX	0:85b3fd62ea1a	6792	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
NYX	0:85b3fd62ea1a	6793	}
NYX	0:85b3fd62ea1a	6794
NYX	0:85b3fd62ea1a	6795	/**
NYX	0:85b3fd62ea1a	6796	* @}
NYX	0:85b3fd62ea1a	6797	*/
NYX	0:85b3fd62ea1a	6798
NYX	0:85b3fd62ea1a	6799	/** @defgroup RCC_LL_EF_IT_Management IT Management
NYX	0:85b3fd62ea1a	6800	* @{
NYX	0:85b3fd62ea1a	6801	*/
NYX	0:85b3fd62ea1a	6802
NYX	0:85b3fd62ea1a	6803	/**
NYX	0:85b3fd62ea1a	6804	* @brief Enable LSI ready interrupt
NYX	0:85b3fd62ea1a	6805	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
NYX	0:85b3fd62ea1a	6806	* @retval None
NYX	0:85b3fd62ea1a	6807	*/
NYX	0:85b3fd62ea1a	6808	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
NYX	0:85b3fd62ea1a	6809	{
NYX	0:85b3fd62ea1a	6810	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
NYX	0:85b3fd62ea1a	6811	}
NYX	0:85b3fd62ea1a	6812
NYX	0:85b3fd62ea1a	6813	/**
NYX	0:85b3fd62ea1a	6814	* @brief Enable LSE ready interrupt
NYX	0:85b3fd62ea1a	6815	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
NYX	0:85b3fd62ea1a	6816	* @retval None
NYX	0:85b3fd62ea1a	6817	*/
NYX	0:85b3fd62ea1a	6818	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
NYX	0:85b3fd62ea1a	6819	{
NYX	0:85b3fd62ea1a	6820	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
NYX	0:85b3fd62ea1a	6821	}
NYX	0:85b3fd62ea1a	6822
NYX	0:85b3fd62ea1a	6823	/**
NYX	0:85b3fd62ea1a	6824	* @brief Enable HSI ready interrupt
NYX	0:85b3fd62ea1a	6825	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
NYX	0:85b3fd62ea1a	6826	* @retval None
NYX	0:85b3fd62ea1a	6827	*/
NYX	0:85b3fd62ea1a	6828	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
NYX	0:85b3fd62ea1a	6829	{
NYX	0:85b3fd62ea1a	6830	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
NYX	0:85b3fd62ea1a	6831	}
NYX	0:85b3fd62ea1a	6832
NYX	0:85b3fd62ea1a	6833	/**
NYX	0:85b3fd62ea1a	6834	* @brief Enable HSE ready interrupt
NYX	0:85b3fd62ea1a	6835	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
NYX	0:85b3fd62ea1a	6836	* @retval None
NYX	0:85b3fd62ea1a	6837	*/
NYX	0:85b3fd62ea1a	6838	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
NYX	0:85b3fd62ea1a	6839	{
NYX	0:85b3fd62ea1a	6840	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
NYX	0:85b3fd62ea1a	6841	}
NYX	0:85b3fd62ea1a	6842
NYX	0:85b3fd62ea1a	6843	/**
NYX	0:85b3fd62ea1a	6844	* @brief Enable PLL ready interrupt
NYX	0:85b3fd62ea1a	6845	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
NYX	0:85b3fd62ea1a	6846	* @retval None
NYX	0:85b3fd62ea1a	6847	*/
NYX	0:85b3fd62ea1a	6848	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
NYX	0:85b3fd62ea1a	6849	{
NYX	0:85b3fd62ea1a	6850	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
NYX	0:85b3fd62ea1a	6851	}
NYX	0:85b3fd62ea1a	6852
NYX	0:85b3fd62ea1a	6853	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	6854	/**
NYX	0:85b3fd62ea1a	6855	* @brief Enable PLLI2S ready interrupt
NYX	0:85b3fd62ea1a	6856	* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
NYX	0:85b3fd62ea1a	6857	* @retval None
NYX	0:85b3fd62ea1a	6858	*/
NYX	0:85b3fd62ea1a	6859	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
NYX	0:85b3fd62ea1a	6860	{
NYX	0:85b3fd62ea1a	6861	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
NYX	0:85b3fd62ea1a	6862	}
NYX	0:85b3fd62ea1a	6863	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	6864
NYX	0:85b3fd62ea1a	6865	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	6866	/**
NYX	0:85b3fd62ea1a	6867	* @brief Enable PLLSAI ready interrupt
NYX	0:85b3fd62ea1a	6868	* @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
NYX	0:85b3fd62ea1a	6869	* @retval None
NYX	0:85b3fd62ea1a	6870	*/
NYX	0:85b3fd62ea1a	6871	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
NYX	0:85b3fd62ea1a	6872	{
NYX	0:85b3fd62ea1a	6873	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
NYX	0:85b3fd62ea1a	6874	}
NYX	0:85b3fd62ea1a	6875	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	6876
NYX	0:85b3fd62ea1a	6877	/**
NYX	0:85b3fd62ea1a	6878	* @brief Disable LSI ready interrupt
NYX	0:85b3fd62ea1a	6879	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
NYX	0:85b3fd62ea1a	6880	* @retval None
NYX	0:85b3fd62ea1a	6881	*/
NYX	0:85b3fd62ea1a	6882	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
NYX	0:85b3fd62ea1a	6883	{
NYX	0:85b3fd62ea1a	6884	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
NYX	0:85b3fd62ea1a	6885	}
NYX	0:85b3fd62ea1a	6886
NYX	0:85b3fd62ea1a	6887	/**
NYX	0:85b3fd62ea1a	6888	* @brief Disable LSE ready interrupt
NYX	0:85b3fd62ea1a	6889	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
NYX	0:85b3fd62ea1a	6890	* @retval None
NYX	0:85b3fd62ea1a	6891	*/
NYX	0:85b3fd62ea1a	6892	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
NYX	0:85b3fd62ea1a	6893	{
NYX	0:85b3fd62ea1a	6894	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
NYX	0:85b3fd62ea1a	6895	}
NYX	0:85b3fd62ea1a	6896
NYX	0:85b3fd62ea1a	6897	/**
NYX	0:85b3fd62ea1a	6898	* @brief Disable HSI ready interrupt
NYX	0:85b3fd62ea1a	6899	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
NYX	0:85b3fd62ea1a	6900	* @retval None
NYX	0:85b3fd62ea1a	6901	*/
NYX	0:85b3fd62ea1a	6902	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
NYX	0:85b3fd62ea1a	6903	{
NYX	0:85b3fd62ea1a	6904	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
NYX	0:85b3fd62ea1a	6905	}
NYX	0:85b3fd62ea1a	6906
NYX	0:85b3fd62ea1a	6907	/**
NYX	0:85b3fd62ea1a	6908	* @brief Disable HSE ready interrupt
NYX	0:85b3fd62ea1a	6909	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
NYX	0:85b3fd62ea1a	6910	* @retval None
NYX	0:85b3fd62ea1a	6911	*/
NYX	0:85b3fd62ea1a	6912	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
NYX	0:85b3fd62ea1a	6913	{
NYX	0:85b3fd62ea1a	6914	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
NYX	0:85b3fd62ea1a	6915	}
NYX	0:85b3fd62ea1a	6916
NYX	0:85b3fd62ea1a	6917	/**
NYX	0:85b3fd62ea1a	6918	* @brief Disable PLL ready interrupt
NYX	0:85b3fd62ea1a	6919	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
NYX	0:85b3fd62ea1a	6920	* @retval None
NYX	0:85b3fd62ea1a	6921	*/
NYX	0:85b3fd62ea1a	6922	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
NYX	0:85b3fd62ea1a	6923	{
NYX	0:85b3fd62ea1a	6924	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
NYX	0:85b3fd62ea1a	6925	}
NYX	0:85b3fd62ea1a	6926
NYX	0:85b3fd62ea1a	6927	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	6928	/**
NYX	0:85b3fd62ea1a	6929	* @brief Disable PLLI2S ready interrupt
NYX	0:85b3fd62ea1a	6930	* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
NYX	0:85b3fd62ea1a	6931	* @retval None
NYX	0:85b3fd62ea1a	6932	*/
NYX	0:85b3fd62ea1a	6933	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
NYX	0:85b3fd62ea1a	6934	{
NYX	0:85b3fd62ea1a	6935	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
NYX	0:85b3fd62ea1a	6936	}
NYX	0:85b3fd62ea1a	6937
NYX	0:85b3fd62ea1a	6938	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	6939
NYX	0:85b3fd62ea1a	6940	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	6941	/**
NYX	0:85b3fd62ea1a	6942	* @brief Disable PLLSAI ready interrupt
NYX	0:85b3fd62ea1a	6943	* @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
NYX	0:85b3fd62ea1a	6944	* @retval None
NYX	0:85b3fd62ea1a	6945	*/
NYX	0:85b3fd62ea1a	6946	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
NYX	0:85b3fd62ea1a	6947	{
NYX	0:85b3fd62ea1a	6948	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
NYX	0:85b3fd62ea1a	6949	}
NYX	0:85b3fd62ea1a	6950	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	6951
NYX	0:85b3fd62ea1a	6952	/**
NYX	0:85b3fd62ea1a	6953	* @brief Checks if LSI ready interrupt source is enabled or disabled.
NYX	0:85b3fd62ea1a	6954	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
NYX	0:85b3fd62ea1a	6955	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6956	*/
NYX	0:85b3fd62ea1a	6957	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
NYX	0:85b3fd62ea1a	6958	{
NYX	0:85b3fd62ea1a	6959	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
NYX	0:85b3fd62ea1a	6960	}
NYX	0:85b3fd62ea1a	6961
NYX	0:85b3fd62ea1a	6962	/**
NYX	0:85b3fd62ea1a	6963	* @brief Checks if LSE ready interrupt source is enabled or disabled.
NYX	0:85b3fd62ea1a	6964	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
NYX	0:85b3fd62ea1a	6965	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6966	*/
NYX	0:85b3fd62ea1a	6967	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
NYX	0:85b3fd62ea1a	6968	{
NYX	0:85b3fd62ea1a	6969	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
NYX	0:85b3fd62ea1a	6970	}
NYX	0:85b3fd62ea1a	6971
NYX	0:85b3fd62ea1a	6972	/**
NYX	0:85b3fd62ea1a	6973	* @brief Checks if HSI ready interrupt source is enabled or disabled.
NYX	0:85b3fd62ea1a	6974	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
NYX	0:85b3fd62ea1a	6975	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6976	*/
NYX	0:85b3fd62ea1a	6977	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
NYX	0:85b3fd62ea1a	6978	{
NYX	0:85b3fd62ea1a	6979	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
NYX	0:85b3fd62ea1a	6980	}
NYX	0:85b3fd62ea1a	6981
NYX	0:85b3fd62ea1a	6982	/**
NYX	0:85b3fd62ea1a	6983	* @brief Checks if HSE ready interrupt source is enabled or disabled.
NYX	0:85b3fd62ea1a	6984	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
NYX	0:85b3fd62ea1a	6985	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6986	*/
NYX	0:85b3fd62ea1a	6987	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
NYX	0:85b3fd62ea1a	6988	{
NYX	0:85b3fd62ea1a	6989	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
NYX	0:85b3fd62ea1a	6990	}
NYX	0:85b3fd62ea1a	6991
NYX	0:85b3fd62ea1a	6992	/**
NYX	0:85b3fd62ea1a	6993	* @brief Checks if PLL ready interrupt source is enabled or disabled.
NYX	0:85b3fd62ea1a	6994	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
NYX	0:85b3fd62ea1a	6995	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	6996	*/
NYX	0:85b3fd62ea1a	6997	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
NYX	0:85b3fd62ea1a	6998	{
NYX	0:85b3fd62ea1a	6999	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
NYX	0:85b3fd62ea1a	7000	}
NYX	0:85b3fd62ea1a	7001
NYX	0:85b3fd62ea1a	7002	#if defined(RCC_PLLI2S_SUPPORT)
NYX	0:85b3fd62ea1a	7003	/**
NYX	0:85b3fd62ea1a	7004	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
NYX	0:85b3fd62ea1a	7005	* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
NYX	0:85b3fd62ea1a	7006	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	7007	*/
NYX	0:85b3fd62ea1a	7008	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
NYX	0:85b3fd62ea1a	7009	{
NYX	0:85b3fd62ea1a	7010	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
NYX	0:85b3fd62ea1a	7011	}
NYX	0:85b3fd62ea1a	7012
NYX	0:85b3fd62ea1a	7013	#endif /* RCC_PLLI2S_SUPPORT */
NYX	0:85b3fd62ea1a	7014
NYX	0:85b3fd62ea1a	7015	#if defined(RCC_PLLSAI_SUPPORT)
NYX	0:85b3fd62ea1a	7016	/**
NYX	0:85b3fd62ea1a	7017	* @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
NYX	0:85b3fd62ea1a	7018	* @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
NYX	0:85b3fd62ea1a	7019	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	7020	*/
NYX	0:85b3fd62ea1a	7021	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
NYX	0:85b3fd62ea1a	7022	{
NYX	0:85b3fd62ea1a	7023	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
NYX	0:85b3fd62ea1a	7024	}
NYX	0:85b3fd62ea1a	7025	#endif /* RCC_PLLSAI_SUPPORT */
NYX	0:85b3fd62ea1a	7026
NYX	0:85b3fd62ea1a	7027	/**
NYX	0:85b3fd62ea1a	7028	* @}
NYX	0:85b3fd62ea1a	7029	*/
NYX	0:85b3fd62ea1a	7030
NYX	0:85b3fd62ea1a	7031	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	7032	/** @defgroup RCC_LL_EF_Init De-initialization function
NYX	0:85b3fd62ea1a	7033	* @{
NYX	0:85b3fd62ea1a	7034	*/
NYX	0:85b3fd62ea1a	7035	ErrorStatus LL_RCC_DeInit(void);
NYX	0:85b3fd62ea1a	7036	/**
NYX	0:85b3fd62ea1a	7037	* @}
NYX	0:85b3fd62ea1a	7038	*/
NYX	0:85b3fd62ea1a	7039
NYX	0:85b3fd62ea1a	7040	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
NYX	0:85b3fd62ea1a	7041	* @{
NYX	0:85b3fd62ea1a	7042	*/
NYX	0:85b3fd62ea1a	7043	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
NYX	0:85b3fd62ea1a	7044	#if defined(FMPI2C1)
NYX	0:85b3fd62ea1a	7045	uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
NYX	0:85b3fd62ea1a	7046	#endif /* FMPI2C1 */
NYX	0:85b3fd62ea1a	7047	#if defined(LPTIM1)
NYX	0:85b3fd62ea1a	7048	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
NYX	0:85b3fd62ea1a	7049	#endif /* LPTIM1 */
NYX	0:85b3fd62ea1a	7050	#if defined(SAI1)
NYX	0:85b3fd62ea1a	7051	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
NYX	0:85b3fd62ea1a	7052	#endif /* SAI1 */
NYX	0:85b3fd62ea1a	7053	#if defined(SDIO)
NYX	0:85b3fd62ea1a	7054	uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
NYX	0:85b3fd62ea1a	7055	#endif /* SDIO */
NYX	0:85b3fd62ea1a	7056	#if defined(RNG)
NYX	0:85b3fd62ea1a	7057	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
NYX	0:85b3fd62ea1a	7058	#endif /* RNG */
NYX	0:85b3fd62ea1a	7059	#if defined(USB_OTG_FS) \|\| defined(USB_OTG_HS)
NYX	0:85b3fd62ea1a	7060	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
NYX	0:85b3fd62ea1a	7061	#endif /* USB_OTG_FS \|\| USB_OTG_HS */
NYX	0:85b3fd62ea1a	7062	#if defined(DFSDM1_Channel0)
NYX	0:85b3fd62ea1a	7063	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
NYX	0:85b3fd62ea1a	7064	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
NYX	0:85b3fd62ea1a	7065	#endif /* DFSDM1_Channel0 */
NYX	0:85b3fd62ea1a	7066	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
NYX	0:85b3fd62ea1a	7067	#if defined(CEC)
NYX	0:85b3fd62ea1a	7068	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
NYX	0:85b3fd62ea1a	7069	#endif /* CEC */
NYX	0:85b3fd62ea1a	7070	#if defined(LTDC)
NYX	0:85b3fd62ea1a	7071	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
NYX	0:85b3fd62ea1a	7072	#endif /* LTDC */
NYX	0:85b3fd62ea1a	7073	#if defined(SPDIFRX)
NYX	0:85b3fd62ea1a	7074	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
NYX	0:85b3fd62ea1a	7075	#endif /* SPDIFRX */
NYX	0:85b3fd62ea1a	7076	#if defined(DSI)
NYX	0:85b3fd62ea1a	7077	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
NYX	0:85b3fd62ea1a	7078	#endif /* DSI */
NYX	0:85b3fd62ea1a	7079	/**
NYX	0:85b3fd62ea1a	7080	* @}
NYX	0:85b3fd62ea1a	7081	*/
NYX	0:85b3fd62ea1a	7082	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	7083
NYX	0:85b3fd62ea1a	7084	/**
NYX	0:85b3fd62ea1a	7085	* @}
NYX	0:85b3fd62ea1a	7086	*/
NYX	0:85b3fd62ea1a	7087
NYX	0:85b3fd62ea1a	7088	/**
NYX	0:85b3fd62ea1a	7089	* @}
NYX	0:85b3fd62ea1a	7090	*/
NYX	0:85b3fd62ea1a	7091
NYX	0:85b3fd62ea1a	7092	#endif /* defined(RCC) */
NYX	0:85b3fd62ea1a	7093
NYX	0:85b3fd62ea1a	7094	/**
NYX	0:85b3fd62ea1a	7095	* @}
NYX	0:85b3fd62ea1a	7096	*/
NYX	0:85b3fd62ea1a	7097
NYX	0:85b3fd62ea1a	7098	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	7099	}
NYX	0:85b3fd62ea1a	7100	#endif
NYX	0:85b3fd62ea1a	7101
NYX	0:85b3fd62ea1a	7102	#endif /* __STM32F4xx_LL_RCC_H */
NYX	0:85b3fd62ea1a	7103
NYX	0:85b3fd62ea1a	7104	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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