Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_rcc.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief RCC LL module driver.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 38
NYX 0:85b3fd62ea1a 39 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 40 #include "stm32f4xx_ll_rcc.h"
NYX 0:85b3fd62ea1a 41 #ifdef USE_FULL_ASSERT
NYX 0:85b3fd62ea1a 42 #include "stm32_assert.h"
NYX 0:85b3fd62ea1a 43 #else
NYX 0:85b3fd62ea1a 44 #define assert_param(expr) ((void)0U)
NYX 0:85b3fd62ea1a 45 #endif
NYX 0:85b3fd62ea1a 46 /** @addtogroup STM32F4xx_LL_Driver
NYX 0:85b3fd62ea1a 47 * @{
NYX 0:85b3fd62ea1a 48 */
NYX 0:85b3fd62ea1a 49
NYX 0:85b3fd62ea1a 50 #if defined(RCC)
NYX 0:85b3fd62ea1a 51
NYX 0:85b3fd62ea1a 52 /** @addtogroup RCC_LL
NYX 0:85b3fd62ea1a 53 * @{
NYX 0:85b3fd62ea1a 54 */
NYX 0:85b3fd62ea1a 55
NYX 0:85b3fd62ea1a 56 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 57 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 58 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 59 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /** @addtogroup RCC_LL_Private_Macros
NYX 0:85b3fd62ea1a 61 * @{
NYX 0:85b3fd62ea1a 62 */
NYX 0:85b3fd62ea1a 63 #if defined(FMPI2C1)
NYX 0:85b3fd62ea1a 64 #define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
NYX 0:85b3fd62ea1a 65 #endif /* FMPI2C1 */
NYX 0:85b3fd62ea1a 66
NYX 0:85b3fd62ea1a 67 #if defined(LPTIM1)
NYX 0:85b3fd62ea1a 68 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
NYX 0:85b3fd62ea1a 69 #endif /* LPTIM1 */
NYX 0:85b3fd62ea1a 70
NYX 0:85b3fd62ea1a 71 #if defined(SAI1)
NYX 0:85b3fd62ea1a 72 #if defined(RCC_DCKCFGR_SAI1SRC)
NYX 0:85b3fd62ea1a 73 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
NYX 0:85b3fd62ea1a 74 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
NYX 0:85b3fd62ea1a 75 #elif defined(RCC_DCKCFGR_SAI1ASRC)
NYX 0:85b3fd62ea1a 76 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
NYX 0:85b3fd62ea1a 77 || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
NYX 0:85b3fd62ea1a 78 #endif /* RCC_DCKCFGR_SAI1SRC */
NYX 0:85b3fd62ea1a 79 #endif /* SAI1 */
NYX 0:85b3fd62ea1a 80
NYX 0:85b3fd62ea1a 81 #if defined(SDIO)
NYX 0:85b3fd62ea1a 82 #define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
NYX 0:85b3fd62ea1a 83 #endif /* SDIO */
NYX 0:85b3fd62ea1a 84
NYX 0:85b3fd62ea1a 85 #if defined(RNG)
NYX 0:85b3fd62ea1a 86 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
NYX 0:85b3fd62ea1a 87 #endif /* RNG */
NYX 0:85b3fd62ea1a 88
NYX 0:85b3fd62ea1a 89 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
NYX 0:85b3fd62ea1a 90 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
NYX 0:85b3fd62ea1a 91 #endif /* USB_OTG_FS || USB_OTG_HS */
NYX 0:85b3fd62ea1a 92
NYX 0:85b3fd62ea1a 93 #if defined(DFSDM2_Channel0)
NYX 0:85b3fd62ea1a 94 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
NYX 0:85b3fd62ea1a 97 || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
NYX 0:85b3fd62ea1a 98 #elif defined(DFSDM1_Channel0)
NYX 0:85b3fd62ea1a 99 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
NYX 0:85b3fd62ea1a 102 #endif /* DFSDM2_Channel0 */
NYX 0:85b3fd62ea1a 103
NYX 0:85b3fd62ea1a 104 #if defined(RCC_DCKCFGR_I2S2SRC)
NYX 0:85b3fd62ea1a 105 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
NYX 0:85b3fd62ea1a 106 || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
NYX 0:85b3fd62ea1a 107 #else
NYX 0:85b3fd62ea1a 108 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
NYX 0:85b3fd62ea1a 109 #endif /* RCC_DCKCFGR_I2S2SRC */
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 #if defined(CEC)
NYX 0:85b3fd62ea1a 112 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
NYX 0:85b3fd62ea1a 113 #endif /* CEC */
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115 #if defined(DSI)
NYX 0:85b3fd62ea1a 116 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
NYX 0:85b3fd62ea1a 117 #endif /* DSI */
NYX 0:85b3fd62ea1a 118
NYX 0:85b3fd62ea1a 119 #if defined(LTDC)
NYX 0:85b3fd62ea1a 120 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
NYX 0:85b3fd62ea1a 121 #endif /* LTDC */
NYX 0:85b3fd62ea1a 122
NYX 0:85b3fd62ea1a 123 #if defined(SPDIFRX)
NYX 0:85b3fd62ea1a 124 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
NYX 0:85b3fd62ea1a 125 #endif /* SPDIFRX */
NYX 0:85b3fd62ea1a 126 /**
NYX 0:85b3fd62ea1a 127 * @}
NYX 0:85b3fd62ea1a 128 */
NYX 0:85b3fd62ea1a 129
NYX 0:85b3fd62ea1a 130 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 131 /** @defgroup RCC_LL_Private_Functions RCC Private functions
NYX 0:85b3fd62ea1a 132 * @{
NYX 0:85b3fd62ea1a 133 */
NYX 0:85b3fd62ea1a 134 uint32_t RCC_GetSystemClockFreq(void);
NYX 0:85b3fd62ea1a 135 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
NYX 0:85b3fd62ea1a 136 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
NYX 0:85b3fd62ea1a 137 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
NYX 0:85b3fd62ea1a 138 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
NYX 0:85b3fd62ea1a 139 uint32_t RCC_PLL_GetFreqDomain_48M(void);
NYX 0:85b3fd62ea1a 140 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
NYX 0:85b3fd62ea1a 141 uint32_t RCC_PLL_GetFreqDomain_I2S(void);
NYX 0:85b3fd62ea1a 142 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
NYX 0:85b3fd62ea1a 143 #if defined(SPDIFRX)
NYX 0:85b3fd62ea1a 144 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
NYX 0:85b3fd62ea1a 145 #endif /* SPDIFRX */
NYX 0:85b3fd62ea1a 146 #if defined(RCC_PLLCFGR_PLLR)
NYX 0:85b3fd62ea1a 147 #if defined(SAI1)
NYX 0:85b3fd62ea1a 148 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
NYX 0:85b3fd62ea1a 149 #endif /* SAI1 */
NYX 0:85b3fd62ea1a 150 #endif /* RCC_PLLCFGR_PLLR */
NYX 0:85b3fd62ea1a 151 #if defined(DSI)
NYX 0:85b3fd62ea1a 152 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
NYX 0:85b3fd62ea1a 153 #endif /* DSI */
NYX 0:85b3fd62ea1a 154 #if defined(RCC_PLLSAI_SUPPORT)
NYX 0:85b3fd62ea1a 155 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
NYX 0:85b3fd62ea1a 156 #if defined(RCC_PLLSAICFGR_PLLSAIP)
NYX 0:85b3fd62ea1a 157 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
NYX 0:85b3fd62ea1a 158 #endif /* RCC_PLLSAICFGR_PLLSAIP */
NYX 0:85b3fd62ea1a 159 #if defined(LTDC)
NYX 0:85b3fd62ea1a 160 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
NYX 0:85b3fd62ea1a 161 #endif /* LTDC */
NYX 0:85b3fd62ea1a 162 #endif /* RCC_PLLSAI_SUPPORT */
NYX 0:85b3fd62ea1a 163 #if defined(RCC_PLLI2S_SUPPORT)
NYX 0:85b3fd62ea1a 164 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
NYX 0:85b3fd62ea1a 165 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX 0:85b3fd62ea1a 166 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
NYX 0:85b3fd62ea1a 167 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX 0:85b3fd62ea1a 168 #if defined(SAI1)
NYX 0:85b3fd62ea1a 169 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
NYX 0:85b3fd62ea1a 170 #endif /* SAI1 */
NYX 0:85b3fd62ea1a 171 #if defined(SPDIFRX)
NYX 0:85b3fd62ea1a 172 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
NYX 0:85b3fd62ea1a 173 #endif /* SPDIFRX */
NYX 0:85b3fd62ea1a 174 #endif /* RCC_PLLI2S_SUPPORT */
NYX 0:85b3fd62ea1a 175 /**
NYX 0:85b3fd62ea1a 176 * @}
NYX 0:85b3fd62ea1a 177 */
NYX 0:85b3fd62ea1a 178
NYX 0:85b3fd62ea1a 179
NYX 0:85b3fd62ea1a 180 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 181 /** @addtogroup RCC_LL_Exported_Functions
NYX 0:85b3fd62ea1a 182 * @{
NYX 0:85b3fd62ea1a 183 */
NYX 0:85b3fd62ea1a 184
NYX 0:85b3fd62ea1a 185 /** @addtogroup RCC_LL_EF_Init
NYX 0:85b3fd62ea1a 186 * @{
NYX 0:85b3fd62ea1a 187 */
NYX 0:85b3fd62ea1a 188
NYX 0:85b3fd62ea1a 189 /**
NYX 0:85b3fd62ea1a 190 * @brief Reset the RCC clock configuration to the default reset state.
NYX 0:85b3fd62ea1a 191 * @note The default reset state of the clock configuration is given below:
NYX 0:85b3fd62ea1a 192 * - HSI ON and used as system clock source
NYX 0:85b3fd62ea1a 193 * - HSE and PLL OFF
NYX 0:85b3fd62ea1a 194 * - AHB, APB1 and APB2 prescaler set to 1.
NYX 0:85b3fd62ea1a 195 * - CSS, MCO OFF
NYX 0:85b3fd62ea1a 196 * - All interrupts disabled
NYX 0:85b3fd62ea1a 197 * @note This function doesn't modify the configuration of the
NYX 0:85b3fd62ea1a 198 * - Peripheral clocks
NYX 0:85b3fd62ea1a 199 * - LSI, LSE and RTC clocks
NYX 0:85b3fd62ea1a 200 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 201 * - SUCCESS: RCC registers are de-initialized
NYX 0:85b3fd62ea1a 202 * - ERROR: not applicable
NYX 0:85b3fd62ea1a 203 */
NYX 0:85b3fd62ea1a 204 ErrorStatus LL_RCC_DeInit(void)
NYX 0:85b3fd62ea1a 205 {
NYX 0:85b3fd62ea1a 206 uint32_t vl_mask = 0U;
NYX 0:85b3fd62ea1a 207
NYX 0:85b3fd62ea1a 208 /* Set HSION bit */
NYX 0:85b3fd62ea1a 209 LL_RCC_HSI_Enable();
NYX 0:85b3fd62ea1a 210
NYX 0:85b3fd62ea1a 211 /* Reset CFGR register */
NYX 0:85b3fd62ea1a 212 LL_RCC_WriteReg(CFGR, 0x00000000U);
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 vl_mask = 0xFFFFFFFFU;
NYX 0:85b3fd62ea1a 215
NYX 0:85b3fd62ea1a 216 /* Reset HSEON, PLLSYSON bits */
NYX 0:85b3fd62ea1a 217 CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
NYX 0:85b3fd62ea1a 218
NYX 0:85b3fd62ea1a 219 #if defined(RCC_PLLSAI_SUPPORT)
NYX 0:85b3fd62ea1a 220 /* Reset PLLSAION bit */
NYX 0:85b3fd62ea1a 221 CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
NYX 0:85b3fd62ea1a 222 #endif /* RCC_PLLSAI_SUPPORT */
NYX 0:85b3fd62ea1a 223
NYX 0:85b3fd62ea1a 224 #if defined(RCC_PLLI2S_SUPPORT)
NYX 0:85b3fd62ea1a 225 /* Reset PLLI2SON bit */
NYX 0:85b3fd62ea1a 226 CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
NYX 0:85b3fd62ea1a 227 #endif /* RCC_PLLI2S_SUPPORT */
NYX 0:85b3fd62ea1a 228
NYX 0:85b3fd62ea1a 229 /* Write new mask in CR register */
NYX 0:85b3fd62ea1a 230 LL_RCC_WriteReg(CR, vl_mask);
NYX 0:85b3fd62ea1a 231
NYX 0:85b3fd62ea1a 232 /* Set HSITRIM bits to the reset value*/
NYX 0:85b3fd62ea1a 233 LL_RCC_HSI_SetCalibTrimming(0x10U);
NYX 0:85b3fd62ea1a 234
NYX 0:85b3fd62ea1a 235 /* Reset PLLCFGR register */
NYX 0:85b3fd62ea1a 236 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
NYX 0:85b3fd62ea1a 237
NYX 0:85b3fd62ea1a 238 #if defined(RCC_PLLI2S_SUPPORT)
NYX 0:85b3fd62ea1a 239 /* Reset PLLI2SCFGR register */
NYX 0:85b3fd62ea1a 240 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
NYX 0:85b3fd62ea1a 241 #endif /* RCC_PLLI2S_SUPPORT */
NYX 0:85b3fd62ea1a 242
NYX 0:85b3fd62ea1a 243 #if defined(RCC_PLLSAI_SUPPORT)
NYX 0:85b3fd62ea1a 244 /* Reset PLLSAICFGR register */
NYX 0:85b3fd62ea1a 245 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
NYX 0:85b3fd62ea1a 246 #endif /* RCC_PLLSAI_SUPPORT */
NYX 0:85b3fd62ea1a 247
NYX 0:85b3fd62ea1a 248 /* Reset HSEBYP bit */
NYX 0:85b3fd62ea1a 249 LL_RCC_HSE_DisableBypass();
NYX 0:85b3fd62ea1a 250
NYX 0:85b3fd62ea1a 251 /* Disable all interrupts */
NYX 0:85b3fd62ea1a 252 LL_RCC_WriteReg(CIR, 0x00000000U);
NYX 0:85b3fd62ea1a 253
NYX 0:85b3fd62ea1a 254 return SUCCESS;
NYX 0:85b3fd62ea1a 255 }
NYX 0:85b3fd62ea1a 256
NYX 0:85b3fd62ea1a 257 /**
NYX 0:85b3fd62ea1a 258 * @}
NYX 0:85b3fd62ea1a 259 */
NYX 0:85b3fd62ea1a 260
NYX 0:85b3fd62ea1a 261 /** @addtogroup RCC_LL_EF_Get_Freq
NYX 0:85b3fd62ea1a 262 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
NYX 0:85b3fd62ea1a 263 * and different peripheral clocks available on the device.
NYX 0:85b3fd62ea1a 264 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
NYX 0:85b3fd62ea1a 265 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
NYX 0:85b3fd62ea1a 266 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
NYX 0:85b3fd62ea1a 267 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
NYX 0:85b3fd62ea1a 268 * @note (**) HSI_VALUE is a constant defined in this file (default value
NYX 0:85b3fd62ea1a 269 * 16 MHz) but the real value may vary depending on the variations
NYX 0:85b3fd62ea1a 270 * in voltage and temperature.
NYX 0:85b3fd62ea1a 271 * @note (***) HSE_VALUE is a constant defined in this file (default value
NYX 0:85b3fd62ea1a 272 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
NYX 0:85b3fd62ea1a 273 * frequency of the crystal used. Otherwise, this function may
NYX 0:85b3fd62ea1a 274 * have wrong result.
NYX 0:85b3fd62ea1a 275 * @note The result of this function could be incorrect when using fractional
NYX 0:85b3fd62ea1a 276 * value for HSE crystal.
NYX 0:85b3fd62ea1a 277 * @note This function can be used by the user application to compute the
NYX 0:85b3fd62ea1a 278 * baud-rate for the communication peripherals or configure other parameters.
NYX 0:85b3fd62ea1a 279 * @{
NYX 0:85b3fd62ea1a 280 */
NYX 0:85b3fd62ea1a 281
NYX 0:85b3fd62ea1a 282 /**
NYX 0:85b3fd62ea1a 283 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
NYX 0:85b3fd62ea1a 284 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
NYX 0:85b3fd62ea1a 285 * must be called to update structure fields. Otherwise, any
NYX 0:85b3fd62ea1a 286 * configuration based on this function will be incorrect.
NYX 0:85b3fd62ea1a 287 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
NYX 0:85b3fd62ea1a 288 * @retval None
NYX 0:85b3fd62ea1a 289 */
NYX 0:85b3fd62ea1a 290 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
NYX 0:85b3fd62ea1a 291 {
NYX 0:85b3fd62ea1a 292 /* Get SYSCLK frequency */
NYX 0:85b3fd62ea1a 293 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /* HCLK clock frequency */
NYX 0:85b3fd62ea1a 296 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
NYX 0:85b3fd62ea1a 297
NYX 0:85b3fd62ea1a 298 /* PCLK1 clock frequency */
NYX 0:85b3fd62ea1a 299 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
NYX 0:85b3fd62ea1a 300
NYX 0:85b3fd62ea1a 301 /* PCLK2 clock frequency */
NYX 0:85b3fd62ea1a 302 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
NYX 0:85b3fd62ea1a 303 }
NYX 0:85b3fd62ea1a 304
NYX 0:85b3fd62ea1a 305 #if defined(FMPI2C1)
NYX 0:85b3fd62ea1a 306 /**
NYX 0:85b3fd62ea1a 307 * @brief Return FMPI2Cx clock frequency
NYX 0:85b3fd62ea1a 308 * @param FMPI2CxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 309 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
NYX 0:85b3fd62ea1a 310 * @retval FMPI2C clock frequency (in Hz)
NYX 0:85b3fd62ea1a 311 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
NYX 0:85b3fd62ea1a 312 */
NYX 0:85b3fd62ea1a 313 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
NYX 0:85b3fd62ea1a 314 {
NYX 0:85b3fd62ea1a 315 uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 316
NYX 0:85b3fd62ea1a 317 /* Check parameter */
NYX 0:85b3fd62ea1a 318 assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
NYX 0:85b3fd62ea1a 319
NYX 0:85b3fd62ea1a 320 if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
NYX 0:85b3fd62ea1a 321 {
NYX 0:85b3fd62ea1a 322 /* FMPI2C1 CLK clock frequency */
NYX 0:85b3fd62ea1a 323 switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
NYX 0:85b3fd62ea1a 324 {
NYX 0:85b3fd62ea1a 325 case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
NYX 0:85b3fd62ea1a 326 FMPI2C_frequency = RCC_GetSystemClockFreq();
NYX 0:85b3fd62ea1a 327 break;
NYX 0:85b3fd62ea1a 328
NYX 0:85b3fd62ea1a 329 case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
NYX 0:85b3fd62ea1a 330 if (LL_RCC_HSI_IsReady())
NYX 0:85b3fd62ea1a 331 {
NYX 0:85b3fd62ea1a 332 FMPI2C_frequency = HSI_VALUE;
NYX 0:85b3fd62ea1a 333 }
NYX 0:85b3fd62ea1a 334 break;
NYX 0:85b3fd62ea1a 335
NYX 0:85b3fd62ea1a 336 case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
NYX 0:85b3fd62ea1a 337 default:
NYX 0:85b3fd62ea1a 338 FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
NYX 0:85b3fd62ea1a 339 break;
NYX 0:85b3fd62ea1a 340 }
NYX 0:85b3fd62ea1a 341 }
NYX 0:85b3fd62ea1a 342
NYX 0:85b3fd62ea1a 343 return FMPI2C_frequency;
NYX 0:85b3fd62ea1a 344 }
NYX 0:85b3fd62ea1a 345 #endif /* FMPI2C1 */
NYX 0:85b3fd62ea1a 346
NYX 0:85b3fd62ea1a 347 /**
NYX 0:85b3fd62ea1a 348 * @brief Return I2Sx clock frequency
NYX 0:85b3fd62ea1a 349 * @param I2SxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 350 * @arg @ref LL_RCC_I2S1_CLKSOURCE
NYX 0:85b3fd62ea1a 351 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
NYX 0:85b3fd62ea1a 352 *
NYX 0:85b3fd62ea1a 353 * (*) value not defined in all devices.
NYX 0:85b3fd62ea1a 354 * @retval I2S clock frequency (in Hz)
NYX 0:85b3fd62ea1a 355 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
NYX 0:85b3fd62ea1a 356 */
NYX 0:85b3fd62ea1a 357 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
NYX 0:85b3fd62ea1a 358 {
NYX 0:85b3fd62ea1a 359 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 360
NYX 0:85b3fd62ea1a 361 /* Check parameter */
NYX 0:85b3fd62ea1a 362 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
NYX 0:85b3fd62ea1a 363
NYX 0:85b3fd62ea1a 364 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
NYX 0:85b3fd62ea1a 365 {
NYX 0:85b3fd62ea1a 366 /* I2S1 CLK clock frequency */
NYX 0:85b3fd62ea1a 367 switch (LL_RCC_GetI2SClockSource(I2SxSource))
NYX 0:85b3fd62ea1a 368 {
NYX 0:85b3fd62ea1a 369 #if defined(RCC_PLLI2S_SUPPORT)
NYX 0:85b3fd62ea1a 370 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
NYX 0:85b3fd62ea1a 371 if (LL_RCC_PLLI2S_IsReady())
NYX 0:85b3fd62ea1a 372 {
NYX 0:85b3fd62ea1a 373 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
NYX 0:85b3fd62ea1a 374 }
NYX 0:85b3fd62ea1a 375 break;
NYX 0:85b3fd62ea1a 376 #endif /* RCC_PLLI2S_SUPPORT */
NYX 0:85b3fd62ea1a 377
NYX 0:85b3fd62ea1a 378 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
NYX 0:85b3fd62ea1a 379 case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
NYX 0:85b3fd62ea1a 380 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 381 {
NYX 0:85b3fd62ea1a 382 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
NYX 0:85b3fd62ea1a 383 }
NYX 0:85b3fd62ea1a 384 break;
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
NYX 0:85b3fd62ea1a 387 switch (LL_RCC_PLL_GetMainSource())
NYX 0:85b3fd62ea1a 388 {
NYX 0:85b3fd62ea1a 389 case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
NYX 0:85b3fd62ea1a 390 if (LL_RCC_HSE_IsReady())
NYX 0:85b3fd62ea1a 391 {
NYX 0:85b3fd62ea1a 392 i2s_frequency = HSE_VALUE;
NYX 0:85b3fd62ea1a 393 }
NYX 0:85b3fd62ea1a 394 break;
NYX 0:85b3fd62ea1a 395
NYX 0:85b3fd62ea1a 396 case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
NYX 0:85b3fd62ea1a 397 default:
NYX 0:85b3fd62ea1a 398 if (LL_RCC_HSI_IsReady())
NYX 0:85b3fd62ea1a 399 {
NYX 0:85b3fd62ea1a 400 i2s_frequency = HSI_VALUE;
NYX 0:85b3fd62ea1a 401 }
NYX 0:85b3fd62ea1a 402 break;
NYX 0:85b3fd62ea1a 403 }
NYX 0:85b3fd62ea1a 404 break;
NYX 0:85b3fd62ea1a 405 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
NYX 0:85b3fd62ea1a 406
NYX 0:85b3fd62ea1a 407 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
NYX 0:85b3fd62ea1a 408 default:
NYX 0:85b3fd62ea1a 409 i2s_frequency = EXTERNAL_CLOCK_VALUE;
NYX 0:85b3fd62ea1a 410 break;
NYX 0:85b3fd62ea1a 411 }
NYX 0:85b3fd62ea1a 412 }
NYX 0:85b3fd62ea1a 413 #if defined(RCC_DCKCFGR_I2S2SRC)
NYX 0:85b3fd62ea1a 414 else
NYX 0:85b3fd62ea1a 415 {
NYX 0:85b3fd62ea1a 416 /* I2S2 CLK clock frequency */
NYX 0:85b3fd62ea1a 417 switch (LL_RCC_GetI2SClockSource(I2SxSource))
NYX 0:85b3fd62ea1a 418 {
NYX 0:85b3fd62ea1a 419 case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
NYX 0:85b3fd62ea1a 420 if (LL_RCC_PLLI2S_IsReady())
NYX 0:85b3fd62ea1a 421 {
NYX 0:85b3fd62ea1a 422 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
NYX 0:85b3fd62ea1a 423 }
NYX 0:85b3fd62ea1a 424 break;
NYX 0:85b3fd62ea1a 425
NYX 0:85b3fd62ea1a 426 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
NYX 0:85b3fd62ea1a 427 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 428 {
NYX 0:85b3fd62ea1a 429 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
NYX 0:85b3fd62ea1a 430 }
NYX 0:85b3fd62ea1a 431 break;
NYX 0:85b3fd62ea1a 432
NYX 0:85b3fd62ea1a 433 case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
NYX 0:85b3fd62ea1a 434 switch (LL_RCC_PLL_GetMainSource())
NYX 0:85b3fd62ea1a 435 {
NYX 0:85b3fd62ea1a 436 case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
NYX 0:85b3fd62ea1a 437 if (LL_RCC_HSE_IsReady())
NYX 0:85b3fd62ea1a 438 {
NYX 0:85b3fd62ea1a 439 i2s_frequency = HSE_VALUE;
NYX 0:85b3fd62ea1a 440 }
NYX 0:85b3fd62ea1a 441 break;
NYX 0:85b3fd62ea1a 442
NYX 0:85b3fd62ea1a 443 case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
NYX 0:85b3fd62ea1a 444 default:
NYX 0:85b3fd62ea1a 445 if (LL_RCC_HSI_IsReady())
NYX 0:85b3fd62ea1a 446 {
NYX 0:85b3fd62ea1a 447 i2s_frequency = HSI_VALUE;
NYX 0:85b3fd62ea1a 448 }
NYX 0:85b3fd62ea1a 449 break;
NYX 0:85b3fd62ea1a 450 }
NYX 0:85b3fd62ea1a 451 break;
NYX 0:85b3fd62ea1a 452
NYX 0:85b3fd62ea1a 453 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
NYX 0:85b3fd62ea1a 454 default:
NYX 0:85b3fd62ea1a 455 i2s_frequency = EXTERNAL_CLOCK_VALUE;
NYX 0:85b3fd62ea1a 456 break;
NYX 0:85b3fd62ea1a 457 }
NYX 0:85b3fd62ea1a 458 }
NYX 0:85b3fd62ea1a 459 #endif /* RCC_DCKCFGR_I2S2SRC */
NYX 0:85b3fd62ea1a 460
NYX 0:85b3fd62ea1a 461 return i2s_frequency;
NYX 0:85b3fd62ea1a 462 }
NYX 0:85b3fd62ea1a 463
NYX 0:85b3fd62ea1a 464 #if defined(LPTIM1)
NYX 0:85b3fd62ea1a 465 /**
NYX 0:85b3fd62ea1a 466 * @brief Return LPTIMx clock frequency
NYX 0:85b3fd62ea1a 467 * @param LPTIMxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 468 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
NYX 0:85b3fd62ea1a 469 * @retval LPTIM clock frequency (in Hz)
NYX 0:85b3fd62ea1a 470 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
NYX 0:85b3fd62ea1a 471 */
NYX 0:85b3fd62ea1a 472 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
NYX 0:85b3fd62ea1a 473 {
NYX 0:85b3fd62ea1a 474 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 475
NYX 0:85b3fd62ea1a 476 /* Check parameter */
NYX 0:85b3fd62ea1a 477 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
NYX 0:85b3fd62ea1a 478
NYX 0:85b3fd62ea1a 479 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
NYX 0:85b3fd62ea1a 480 {
NYX 0:85b3fd62ea1a 481 /* LPTIM1CLK clock frequency */
NYX 0:85b3fd62ea1a 482 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
NYX 0:85b3fd62ea1a 483 {
NYX 0:85b3fd62ea1a 484 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
NYX 0:85b3fd62ea1a 485 if (LL_RCC_LSI_IsReady())
NYX 0:85b3fd62ea1a 486 {
NYX 0:85b3fd62ea1a 487 lptim_frequency = LSI_VALUE;
NYX 0:85b3fd62ea1a 488 }
NYX 0:85b3fd62ea1a 489 break;
NYX 0:85b3fd62ea1a 490
NYX 0:85b3fd62ea1a 491 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
NYX 0:85b3fd62ea1a 492 if (LL_RCC_HSI_IsReady())
NYX 0:85b3fd62ea1a 493 {
NYX 0:85b3fd62ea1a 494 lptim_frequency = HSI_VALUE;
NYX 0:85b3fd62ea1a 495 }
NYX 0:85b3fd62ea1a 496 break;
NYX 0:85b3fd62ea1a 497
NYX 0:85b3fd62ea1a 498 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
NYX 0:85b3fd62ea1a 499 if (LL_RCC_LSE_IsReady())
NYX 0:85b3fd62ea1a 500 {
NYX 0:85b3fd62ea1a 501 lptim_frequency = LSE_VALUE;
NYX 0:85b3fd62ea1a 502 }
NYX 0:85b3fd62ea1a 503 break;
NYX 0:85b3fd62ea1a 504
NYX 0:85b3fd62ea1a 505 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
NYX 0:85b3fd62ea1a 506 default:
NYX 0:85b3fd62ea1a 507 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
NYX 0:85b3fd62ea1a 508 break;
NYX 0:85b3fd62ea1a 509 }
NYX 0:85b3fd62ea1a 510 }
NYX 0:85b3fd62ea1a 511
NYX 0:85b3fd62ea1a 512 return lptim_frequency;
NYX 0:85b3fd62ea1a 513 }
NYX 0:85b3fd62ea1a 514 #endif /* LPTIM1 */
NYX 0:85b3fd62ea1a 515
NYX 0:85b3fd62ea1a 516 #if defined(SAI1)
NYX 0:85b3fd62ea1a 517 /**
NYX 0:85b3fd62ea1a 518 * @brief Return SAIx clock frequency
NYX 0:85b3fd62ea1a 519 * @param SAIxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 520 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
NYX 0:85b3fd62ea1a 521 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
NYX 0:85b3fd62ea1a 522 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
NYX 0:85b3fd62ea1a 523 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
NYX 0:85b3fd62ea1a 524 *
NYX 0:85b3fd62ea1a 525 * (*) value not defined in all devices.
NYX 0:85b3fd62ea1a 526 * @retval SAI clock frequency (in Hz)
NYX 0:85b3fd62ea1a 527 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
NYX 0:85b3fd62ea1a 528 */
NYX 0:85b3fd62ea1a 529 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
NYX 0:85b3fd62ea1a 530 {
NYX 0:85b3fd62ea1a 531 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 532
NYX 0:85b3fd62ea1a 533 /* Check parameter */
NYX 0:85b3fd62ea1a 534 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 #if defined(RCC_DCKCFGR_SAI1SRC)
NYX 0:85b3fd62ea1a 537 if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
NYX 0:85b3fd62ea1a 538 {
NYX 0:85b3fd62ea1a 539 /* SAI1CLK clock frequency */
NYX 0:85b3fd62ea1a 540 switch (LL_RCC_GetSAIClockSource(SAIxSource))
NYX 0:85b3fd62ea1a 541 {
NYX 0:85b3fd62ea1a 542 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
NYX 0:85b3fd62ea1a 543 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
NYX 0:85b3fd62ea1a 544 if (LL_RCC_PLLSAI_IsReady())
NYX 0:85b3fd62ea1a 545 {
NYX 0:85b3fd62ea1a 546 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
NYX 0:85b3fd62ea1a 547 }
NYX 0:85b3fd62ea1a 548 break;
NYX 0:85b3fd62ea1a 549
NYX 0:85b3fd62ea1a 550 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
NYX 0:85b3fd62ea1a 551 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
NYX 0:85b3fd62ea1a 552 if (LL_RCC_PLLI2S_IsReady())
NYX 0:85b3fd62ea1a 553 {
NYX 0:85b3fd62ea1a 554 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
NYX 0:85b3fd62ea1a 555 }
NYX 0:85b3fd62ea1a 556 break;
NYX 0:85b3fd62ea1a 557
NYX 0:85b3fd62ea1a 558 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
NYX 0:85b3fd62ea1a 559 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
NYX 0:85b3fd62ea1a 560 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 561 {
NYX 0:85b3fd62ea1a 562 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
NYX 0:85b3fd62ea1a 563 }
NYX 0:85b3fd62ea1a 564 break;
NYX 0:85b3fd62ea1a 565
NYX 0:85b3fd62ea1a 566 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
NYX 0:85b3fd62ea1a 567 switch (LL_RCC_PLL_GetMainSource())
NYX 0:85b3fd62ea1a 568 {
NYX 0:85b3fd62ea1a 569 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
NYX 0:85b3fd62ea1a 570 if (LL_RCC_HSE_IsReady())
NYX 0:85b3fd62ea1a 571 {
NYX 0:85b3fd62ea1a 572 sai_frequency = HSE_VALUE;
NYX 0:85b3fd62ea1a 573 }
NYX 0:85b3fd62ea1a 574 break;
NYX 0:85b3fd62ea1a 575
NYX 0:85b3fd62ea1a 576 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
NYX 0:85b3fd62ea1a 577 default:
NYX 0:85b3fd62ea1a 578 if (LL_RCC_HSI_IsReady())
NYX 0:85b3fd62ea1a 579 {
NYX 0:85b3fd62ea1a 580 sai_frequency = HSI_VALUE;
NYX 0:85b3fd62ea1a 581 }
NYX 0:85b3fd62ea1a 582 break;
NYX 0:85b3fd62ea1a 583 }
NYX 0:85b3fd62ea1a 584 break;
NYX 0:85b3fd62ea1a 585
NYX 0:85b3fd62ea1a 586 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
NYX 0:85b3fd62ea1a 587 default:
NYX 0:85b3fd62ea1a 588 sai_frequency = EXTERNAL_CLOCK_VALUE;
NYX 0:85b3fd62ea1a 589 break;
NYX 0:85b3fd62ea1a 590 }
NYX 0:85b3fd62ea1a 591 }
NYX 0:85b3fd62ea1a 592 #endif /* RCC_DCKCFGR_SAI1SRC */
NYX 0:85b3fd62ea1a 593 #if defined(RCC_DCKCFGR_SAI1ASRC)
NYX 0:85b3fd62ea1a 594 if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
NYX 0:85b3fd62ea1a 595 {
NYX 0:85b3fd62ea1a 596 /* SAI1CLK clock frequency */
NYX 0:85b3fd62ea1a 597 switch (LL_RCC_GetSAIClockSource(SAIxSource))
NYX 0:85b3fd62ea1a 598 {
NYX 0:85b3fd62ea1a 599 #if defined(RCC_PLLSAI_SUPPORT)
NYX 0:85b3fd62ea1a 600 case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
NYX 0:85b3fd62ea1a 601 case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
NYX 0:85b3fd62ea1a 602 if (LL_RCC_PLLSAI_IsReady())
NYX 0:85b3fd62ea1a 603 {
NYX 0:85b3fd62ea1a 604 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
NYX 0:85b3fd62ea1a 605 }
NYX 0:85b3fd62ea1a 606 break;
NYX 0:85b3fd62ea1a 607 #endif /* RCC_PLLSAI_SUPPORT */
NYX 0:85b3fd62ea1a 608
NYX 0:85b3fd62ea1a 609 case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
NYX 0:85b3fd62ea1a 610 case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
NYX 0:85b3fd62ea1a 611 if (LL_RCC_PLLI2S_IsReady())
NYX 0:85b3fd62ea1a 612 {
NYX 0:85b3fd62ea1a 613 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
NYX 0:85b3fd62ea1a 614 }
NYX 0:85b3fd62ea1a 615 break;
NYX 0:85b3fd62ea1a 616
NYX 0:85b3fd62ea1a 617 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
NYX 0:85b3fd62ea1a 618 case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
NYX 0:85b3fd62ea1a 619 case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
NYX 0:85b3fd62ea1a 620 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 621 {
NYX 0:85b3fd62ea1a 622 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
NYX 0:85b3fd62ea1a 623 }
NYX 0:85b3fd62ea1a 624 break;
NYX 0:85b3fd62ea1a 625
NYX 0:85b3fd62ea1a 626 case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
NYX 0:85b3fd62ea1a 627 case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
NYX 0:85b3fd62ea1a 628 switch (LL_RCC_PLL_GetMainSource())
NYX 0:85b3fd62ea1a 629 {
NYX 0:85b3fd62ea1a 630 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
NYX 0:85b3fd62ea1a 631 if (LL_RCC_HSE_IsReady())
NYX 0:85b3fd62ea1a 632 {
NYX 0:85b3fd62ea1a 633 sai_frequency = HSE_VALUE;
NYX 0:85b3fd62ea1a 634 }
NYX 0:85b3fd62ea1a 635 break;
NYX 0:85b3fd62ea1a 636
NYX 0:85b3fd62ea1a 637 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
NYX 0:85b3fd62ea1a 638 default:
NYX 0:85b3fd62ea1a 639 if (LL_RCC_HSI_IsReady())
NYX 0:85b3fd62ea1a 640 {
NYX 0:85b3fd62ea1a 641 sai_frequency = HSI_VALUE;
NYX 0:85b3fd62ea1a 642 }
NYX 0:85b3fd62ea1a 643 break;
NYX 0:85b3fd62ea1a 644 }
NYX 0:85b3fd62ea1a 645 break;
NYX 0:85b3fd62ea1a 646 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
NYX 0:85b3fd62ea1a 647
NYX 0:85b3fd62ea1a 648 case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
NYX 0:85b3fd62ea1a 649 case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
NYX 0:85b3fd62ea1a 650 default:
NYX 0:85b3fd62ea1a 651 sai_frequency = EXTERNAL_CLOCK_VALUE;
NYX 0:85b3fd62ea1a 652 break;
NYX 0:85b3fd62ea1a 653 }
NYX 0:85b3fd62ea1a 654 }
NYX 0:85b3fd62ea1a 655 #endif /* RCC_DCKCFGR_SAI1ASRC */
NYX 0:85b3fd62ea1a 656
NYX 0:85b3fd62ea1a 657 return sai_frequency;
NYX 0:85b3fd62ea1a 658 }
NYX 0:85b3fd62ea1a 659 #endif /* SAI1 */
NYX 0:85b3fd62ea1a 660
NYX 0:85b3fd62ea1a 661 #if defined(SDIO)
NYX 0:85b3fd62ea1a 662 /**
NYX 0:85b3fd62ea1a 663 * @brief Return SDIOx clock frequency
NYX 0:85b3fd62ea1a 664 * @param SDIOxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 665 * @arg @ref LL_RCC_SDIO_CLKSOURCE
NYX 0:85b3fd62ea1a 666 * @retval SDIO clock frequency (in Hz)
NYX 0:85b3fd62ea1a 667 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
NYX 0:85b3fd62ea1a 668 */
NYX 0:85b3fd62ea1a 669 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
NYX 0:85b3fd62ea1a 670 {
NYX 0:85b3fd62ea1a 671 uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 672
NYX 0:85b3fd62ea1a 673 /* Check parameter */
NYX 0:85b3fd62ea1a 674 assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
NYX 0:85b3fd62ea1a 675
NYX 0:85b3fd62ea1a 676 if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
NYX 0:85b3fd62ea1a 677 {
NYX 0:85b3fd62ea1a 678 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
NYX 0:85b3fd62ea1a 679 /* SDIOCLK clock frequency */
NYX 0:85b3fd62ea1a 680 switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
NYX 0:85b3fd62ea1a 681 {
NYX 0:85b3fd62ea1a 682 case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
NYX 0:85b3fd62ea1a 683 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
NYX 0:85b3fd62ea1a 684 {
NYX 0:85b3fd62ea1a 685 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
NYX 0:85b3fd62ea1a 686 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 687 {
NYX 0:85b3fd62ea1a 688 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 689 }
NYX 0:85b3fd62ea1a 690 break;
NYX 0:85b3fd62ea1a 691
NYX 0:85b3fd62ea1a 692 #if defined(RCC_PLLSAI_SUPPORT)
NYX 0:85b3fd62ea1a 693 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
NYX 0:85b3fd62ea1a 694 default:
NYX 0:85b3fd62ea1a 695 if (LL_RCC_PLLSAI_IsReady())
NYX 0:85b3fd62ea1a 696 {
NYX 0:85b3fd62ea1a 697 SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 698 }
NYX 0:85b3fd62ea1a 699 break;
NYX 0:85b3fd62ea1a 700 #endif /* RCC_PLLSAI_SUPPORT */
NYX 0:85b3fd62ea1a 701
NYX 0:85b3fd62ea1a 702 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX 0:85b3fd62ea1a 703 case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
NYX 0:85b3fd62ea1a 704 default:
NYX 0:85b3fd62ea1a 705 if (LL_RCC_PLLI2S_IsReady())
NYX 0:85b3fd62ea1a 706 {
NYX 0:85b3fd62ea1a 707 SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 708 }
NYX 0:85b3fd62ea1a 709 break;
NYX 0:85b3fd62ea1a 710 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX 0:85b3fd62ea1a 711 }
NYX 0:85b3fd62ea1a 712 break;
NYX 0:85b3fd62ea1a 713
NYX 0:85b3fd62ea1a 714 case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
NYX 0:85b3fd62ea1a 715 default:
NYX 0:85b3fd62ea1a 716 SDIO_frequency = RCC_GetSystemClockFreq();
NYX 0:85b3fd62ea1a 717 break;
NYX 0:85b3fd62ea1a 718 }
NYX 0:85b3fd62ea1a 719 #else
NYX 0:85b3fd62ea1a 720 /* PLL clock used as 48Mhz domain clock */
NYX 0:85b3fd62ea1a 721 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 722 {
NYX 0:85b3fd62ea1a 723 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 724 }
NYX 0:85b3fd62ea1a 725 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
NYX 0:85b3fd62ea1a 726 }
NYX 0:85b3fd62ea1a 727
NYX 0:85b3fd62ea1a 728 return SDIO_frequency;
NYX 0:85b3fd62ea1a 729 }
NYX 0:85b3fd62ea1a 730 #endif /* SDIO */
NYX 0:85b3fd62ea1a 731
NYX 0:85b3fd62ea1a 732 #if defined(RNG)
NYX 0:85b3fd62ea1a 733 /**
NYX 0:85b3fd62ea1a 734 * @brief Return RNGx clock frequency
NYX 0:85b3fd62ea1a 735 * @param RNGxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 736 * @arg @ref LL_RCC_RNG_CLKSOURCE
NYX 0:85b3fd62ea1a 737 * @retval RNG clock frequency (in Hz)
NYX 0:85b3fd62ea1a 738 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
NYX 0:85b3fd62ea1a 739 */
NYX 0:85b3fd62ea1a 740 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
NYX 0:85b3fd62ea1a 741 {
NYX 0:85b3fd62ea1a 742 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 743
NYX 0:85b3fd62ea1a 744 /* Check parameter */
NYX 0:85b3fd62ea1a 745 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
NYX 0:85b3fd62ea1a 746
NYX 0:85b3fd62ea1a 747 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
NYX 0:85b3fd62ea1a 748 /* RNGCLK clock frequency */
NYX 0:85b3fd62ea1a 749 switch (LL_RCC_GetRNGClockSource(RNGxSource))
NYX 0:85b3fd62ea1a 750 {
NYX 0:85b3fd62ea1a 751 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX 0:85b3fd62ea1a 752 case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
NYX 0:85b3fd62ea1a 753 if (LL_RCC_PLLI2S_IsReady())
NYX 0:85b3fd62ea1a 754 {
NYX 0:85b3fd62ea1a 755 rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 756 }
NYX 0:85b3fd62ea1a 757 break;
NYX 0:85b3fd62ea1a 758 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX 0:85b3fd62ea1a 759
NYX 0:85b3fd62ea1a 760 #if defined(RCC_PLLSAI_SUPPORT)
NYX 0:85b3fd62ea1a 761 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
NYX 0:85b3fd62ea1a 762 if (LL_RCC_PLLSAI_IsReady())
NYX 0:85b3fd62ea1a 763 {
NYX 0:85b3fd62ea1a 764 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 765 }
NYX 0:85b3fd62ea1a 766 break;
NYX 0:85b3fd62ea1a 767 #endif /* RCC_PLLSAI_SUPPORT */
NYX 0:85b3fd62ea1a 768
NYX 0:85b3fd62ea1a 769 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
NYX 0:85b3fd62ea1a 770 default:
NYX 0:85b3fd62ea1a 771 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 772 {
NYX 0:85b3fd62ea1a 773 rng_frequency = RCC_PLL_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 774 }
NYX 0:85b3fd62ea1a 775 break;
NYX 0:85b3fd62ea1a 776 }
NYX 0:85b3fd62ea1a 777 #else
NYX 0:85b3fd62ea1a 778 /* PLL clock used as RNG clock source */
NYX 0:85b3fd62ea1a 779 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 780 {
NYX 0:85b3fd62ea1a 781 rng_frequency = RCC_PLL_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 782 }
NYX 0:85b3fd62ea1a 783 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
NYX 0:85b3fd62ea1a 784
NYX 0:85b3fd62ea1a 785 return rng_frequency;
NYX 0:85b3fd62ea1a 786 }
NYX 0:85b3fd62ea1a 787 #endif /* RNG */
NYX 0:85b3fd62ea1a 788
NYX 0:85b3fd62ea1a 789 #if defined(CEC)
NYX 0:85b3fd62ea1a 790 /**
NYX 0:85b3fd62ea1a 791 * @brief Return CEC clock frequency
NYX 0:85b3fd62ea1a 792 * @param CECxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 793 * @arg @ref LL_RCC_CEC_CLKSOURCE
NYX 0:85b3fd62ea1a 794 * @retval CEC clock frequency (in Hz)
NYX 0:85b3fd62ea1a 795 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
NYX 0:85b3fd62ea1a 796 */
NYX 0:85b3fd62ea1a 797 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
NYX 0:85b3fd62ea1a 798 {
NYX 0:85b3fd62ea1a 799 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 800
NYX 0:85b3fd62ea1a 801 /* Check parameter */
NYX 0:85b3fd62ea1a 802 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
NYX 0:85b3fd62ea1a 803
NYX 0:85b3fd62ea1a 804 /* CECCLK clock frequency */
NYX 0:85b3fd62ea1a 805 switch (LL_RCC_GetCECClockSource(CECxSource))
NYX 0:85b3fd62ea1a 806 {
NYX 0:85b3fd62ea1a 807 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
NYX 0:85b3fd62ea1a 808 if (LL_RCC_LSE_IsReady())
NYX 0:85b3fd62ea1a 809 {
NYX 0:85b3fd62ea1a 810 cec_frequency = LSE_VALUE;
NYX 0:85b3fd62ea1a 811 }
NYX 0:85b3fd62ea1a 812 break;
NYX 0:85b3fd62ea1a 813
NYX 0:85b3fd62ea1a 814 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
NYX 0:85b3fd62ea1a 815 default:
NYX 0:85b3fd62ea1a 816 if (LL_RCC_HSI_IsReady())
NYX 0:85b3fd62ea1a 817 {
NYX 0:85b3fd62ea1a 818 cec_frequency = HSI_VALUE/488U;
NYX 0:85b3fd62ea1a 819 }
NYX 0:85b3fd62ea1a 820 break;
NYX 0:85b3fd62ea1a 821 }
NYX 0:85b3fd62ea1a 822
NYX 0:85b3fd62ea1a 823 return cec_frequency;
NYX 0:85b3fd62ea1a 824 }
NYX 0:85b3fd62ea1a 825 #endif /* CEC */
NYX 0:85b3fd62ea1a 826
NYX 0:85b3fd62ea1a 827 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
NYX 0:85b3fd62ea1a 828 /**
NYX 0:85b3fd62ea1a 829 * @brief Return USBx clock frequency
NYX 0:85b3fd62ea1a 830 * @param USBxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 831 * @arg @ref LL_RCC_USB_CLKSOURCE
NYX 0:85b3fd62ea1a 832 * @retval USB clock frequency (in Hz)
NYX 0:85b3fd62ea1a 833 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
NYX 0:85b3fd62ea1a 834 */
NYX 0:85b3fd62ea1a 835 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
NYX 0:85b3fd62ea1a 836 {
NYX 0:85b3fd62ea1a 837 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 838
NYX 0:85b3fd62ea1a 839 /* Check parameter */
NYX 0:85b3fd62ea1a 840 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
NYX 0:85b3fd62ea1a 841
NYX 0:85b3fd62ea1a 842 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
NYX 0:85b3fd62ea1a 843 /* USBCLK clock frequency */
NYX 0:85b3fd62ea1a 844 switch (LL_RCC_GetUSBClockSource(USBxSource))
NYX 0:85b3fd62ea1a 845 {
NYX 0:85b3fd62ea1a 846 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX 0:85b3fd62ea1a 847 case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
NYX 0:85b3fd62ea1a 848 if (LL_RCC_PLLI2S_IsReady())
NYX 0:85b3fd62ea1a 849 {
NYX 0:85b3fd62ea1a 850 usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 851 }
NYX 0:85b3fd62ea1a 852 break;
NYX 0:85b3fd62ea1a 853
NYX 0:85b3fd62ea1a 854 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX 0:85b3fd62ea1a 855
NYX 0:85b3fd62ea1a 856 #if defined(RCC_PLLSAI_SUPPORT)
NYX 0:85b3fd62ea1a 857 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
NYX 0:85b3fd62ea1a 858 if (LL_RCC_PLLSAI_IsReady())
NYX 0:85b3fd62ea1a 859 {
NYX 0:85b3fd62ea1a 860 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 861 }
NYX 0:85b3fd62ea1a 862 break;
NYX 0:85b3fd62ea1a 863 #endif /* RCC_PLLSAI_SUPPORT */
NYX 0:85b3fd62ea1a 864
NYX 0:85b3fd62ea1a 865 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
NYX 0:85b3fd62ea1a 866 default:
NYX 0:85b3fd62ea1a 867 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 868 {
NYX 0:85b3fd62ea1a 869 usb_frequency = RCC_PLL_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 870 }
NYX 0:85b3fd62ea1a 871 break;
NYX 0:85b3fd62ea1a 872 }
NYX 0:85b3fd62ea1a 873 #else
NYX 0:85b3fd62ea1a 874 /* PLL clock used as USB clock source */
NYX 0:85b3fd62ea1a 875 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 876 {
NYX 0:85b3fd62ea1a 877 usb_frequency = RCC_PLL_GetFreqDomain_48M();
NYX 0:85b3fd62ea1a 878 }
NYX 0:85b3fd62ea1a 879 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
NYX 0:85b3fd62ea1a 880
NYX 0:85b3fd62ea1a 881 return usb_frequency;
NYX 0:85b3fd62ea1a 882 }
NYX 0:85b3fd62ea1a 883 #endif /* USB_OTG_FS || USB_OTG_HS */
NYX 0:85b3fd62ea1a 884
NYX 0:85b3fd62ea1a 885 #if defined(DFSDM1_Channel0)
NYX 0:85b3fd62ea1a 886 /**
NYX 0:85b3fd62ea1a 887 * @brief Return DFSDMx clock frequency
NYX 0:85b3fd62ea1a 888 * @param DFSDMxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 889 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
NYX 0:85b3fd62ea1a 890 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
NYX 0:85b3fd62ea1a 891 *
NYX 0:85b3fd62ea1a 892 * (*) value not defined in all devices.
NYX 0:85b3fd62ea1a 893 * @retval DFSDM clock frequency (in Hz)
NYX 0:85b3fd62ea1a 894 */
NYX 0:85b3fd62ea1a 895 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
NYX 0:85b3fd62ea1a 896 {
NYX 0:85b3fd62ea1a 897 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 898
NYX 0:85b3fd62ea1a 899 /* Check parameter */
NYX 0:85b3fd62ea1a 900 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
NYX 0:85b3fd62ea1a 901
NYX 0:85b3fd62ea1a 902 if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
NYX 0:85b3fd62ea1a 903 {
NYX 0:85b3fd62ea1a 904 /* DFSDM1CLK clock frequency */
NYX 0:85b3fd62ea1a 905 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
NYX 0:85b3fd62ea1a 906 {
NYX 0:85b3fd62ea1a 907 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
NYX 0:85b3fd62ea1a 908 dfsdm_frequency = RCC_GetSystemClockFreq();
NYX 0:85b3fd62ea1a 909 break;
NYX 0:85b3fd62ea1a 910
NYX 0:85b3fd62ea1a 911 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
NYX 0:85b3fd62ea1a 912 default:
NYX 0:85b3fd62ea1a 913 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
NYX 0:85b3fd62ea1a 914 break;
NYX 0:85b3fd62ea1a 915 }
NYX 0:85b3fd62ea1a 916 }
NYX 0:85b3fd62ea1a 917 #if defined(DFSDM2_Channel0)
NYX 0:85b3fd62ea1a 918 else
NYX 0:85b3fd62ea1a 919 {
NYX 0:85b3fd62ea1a 920 /* DFSDM2CLK clock frequency */
NYX 0:85b3fd62ea1a 921 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
NYX 0:85b3fd62ea1a 922 {
NYX 0:85b3fd62ea1a 923 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
NYX 0:85b3fd62ea1a 924 dfsdm_frequency = RCC_GetSystemClockFreq();
NYX 0:85b3fd62ea1a 925 break;
NYX 0:85b3fd62ea1a 926
NYX 0:85b3fd62ea1a 927 case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
NYX 0:85b3fd62ea1a 928 default:
NYX 0:85b3fd62ea1a 929 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
NYX 0:85b3fd62ea1a 930 break;
NYX 0:85b3fd62ea1a 931 }
NYX 0:85b3fd62ea1a 932 }
NYX 0:85b3fd62ea1a 933 #endif /* DFSDM2_Channel0 */
NYX 0:85b3fd62ea1a 934
NYX 0:85b3fd62ea1a 935 return dfsdm_frequency;
NYX 0:85b3fd62ea1a 936 }
NYX 0:85b3fd62ea1a 937
NYX 0:85b3fd62ea1a 938 /**
NYX 0:85b3fd62ea1a 939 * @brief Return DFSDMx Audio clock frequency
NYX 0:85b3fd62ea1a 940 * @param DFSDMxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 941 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
NYX 0:85b3fd62ea1a 942 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
NYX 0:85b3fd62ea1a 943 *
NYX 0:85b3fd62ea1a 944 * (*) value not defined in all devices.
NYX 0:85b3fd62ea1a 945 * @retval DFSDM clock frequency (in Hz)
NYX 0:85b3fd62ea1a 946 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
NYX 0:85b3fd62ea1a 947 */
NYX 0:85b3fd62ea1a 948 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
NYX 0:85b3fd62ea1a 949 {
NYX 0:85b3fd62ea1a 950 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 951
NYX 0:85b3fd62ea1a 952 /* Check parameter */
NYX 0:85b3fd62ea1a 953 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
NYX 0:85b3fd62ea1a 954
NYX 0:85b3fd62ea1a 955 if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
NYX 0:85b3fd62ea1a 956 {
NYX 0:85b3fd62ea1a 957 /* DFSDM1CLK clock frequency */
NYX 0:85b3fd62ea1a 958 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
NYX 0:85b3fd62ea1a 959 {
NYX 0:85b3fd62ea1a 960 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
NYX 0:85b3fd62ea1a 961 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
NYX 0:85b3fd62ea1a 962 break;
NYX 0:85b3fd62ea1a 963
NYX 0:85b3fd62ea1a 964 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
NYX 0:85b3fd62ea1a 965 default:
NYX 0:85b3fd62ea1a 966 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
NYX 0:85b3fd62ea1a 967 break;
NYX 0:85b3fd62ea1a 968 }
NYX 0:85b3fd62ea1a 969 }
NYX 0:85b3fd62ea1a 970 #if defined(DFSDM2_Channel0)
NYX 0:85b3fd62ea1a 971 else
NYX 0:85b3fd62ea1a 972 {
NYX 0:85b3fd62ea1a 973 /* DFSDM2CLK clock frequency */
NYX 0:85b3fd62ea1a 974 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
NYX 0:85b3fd62ea1a 975 {
NYX 0:85b3fd62ea1a 976 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
NYX 0:85b3fd62ea1a 977 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
NYX 0:85b3fd62ea1a 978 break;
NYX 0:85b3fd62ea1a 979
NYX 0:85b3fd62ea1a 980 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
NYX 0:85b3fd62ea1a 981 default:
NYX 0:85b3fd62ea1a 982 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
NYX 0:85b3fd62ea1a 983 break;
NYX 0:85b3fd62ea1a 984 }
NYX 0:85b3fd62ea1a 985 }
NYX 0:85b3fd62ea1a 986 #endif /* DFSDM2_Channel0 */
NYX 0:85b3fd62ea1a 987
NYX 0:85b3fd62ea1a 988 return dfsdm_frequency;
NYX 0:85b3fd62ea1a 989 }
NYX 0:85b3fd62ea1a 990 #endif /* DFSDM1_Channel0 */
NYX 0:85b3fd62ea1a 991
NYX 0:85b3fd62ea1a 992 #if defined(DSI)
NYX 0:85b3fd62ea1a 993 /**
NYX 0:85b3fd62ea1a 994 * @brief Return DSI clock frequency
NYX 0:85b3fd62ea1a 995 * @param DSIxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 996 * @arg @ref LL_RCC_DSI_CLKSOURCE
NYX 0:85b3fd62ea1a 997 * @retval DSI clock frequency (in Hz)
NYX 0:85b3fd62ea1a 998 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
NYX 0:85b3fd62ea1a 999 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
NYX 0:85b3fd62ea1a 1000 */
NYX 0:85b3fd62ea1a 1001 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
NYX 0:85b3fd62ea1a 1002 {
NYX 0:85b3fd62ea1a 1003 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 1004
NYX 0:85b3fd62ea1a 1005 /* Check parameter */
NYX 0:85b3fd62ea1a 1006 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
NYX 0:85b3fd62ea1a 1007
NYX 0:85b3fd62ea1a 1008 /* DSICLK clock frequency */
NYX 0:85b3fd62ea1a 1009 switch (LL_RCC_GetDSIClockSource(DSIxSource))
NYX 0:85b3fd62ea1a 1010 {
NYX 0:85b3fd62ea1a 1011 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
NYX 0:85b3fd62ea1a 1012 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 1013 {
NYX 0:85b3fd62ea1a 1014 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
NYX 0:85b3fd62ea1a 1015 }
NYX 0:85b3fd62ea1a 1016 break;
NYX 0:85b3fd62ea1a 1017
NYX 0:85b3fd62ea1a 1018 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
NYX 0:85b3fd62ea1a 1019 default:
NYX 0:85b3fd62ea1a 1020 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
NYX 0:85b3fd62ea1a 1021 break;
NYX 0:85b3fd62ea1a 1022 }
NYX 0:85b3fd62ea1a 1023
NYX 0:85b3fd62ea1a 1024 return dsi_frequency;
NYX 0:85b3fd62ea1a 1025 }
NYX 0:85b3fd62ea1a 1026 #endif /* DSI */
NYX 0:85b3fd62ea1a 1027
NYX 0:85b3fd62ea1a 1028 #if defined(LTDC)
NYX 0:85b3fd62ea1a 1029 /**
NYX 0:85b3fd62ea1a 1030 * @brief Return LTDC clock frequency
NYX 0:85b3fd62ea1a 1031 * @param LTDCxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1032 * @arg @ref LL_RCC_LTDC_CLKSOURCE
NYX 0:85b3fd62ea1a 1033 * @retval LTDC clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1034 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
NYX 0:85b3fd62ea1a 1035 */
NYX 0:85b3fd62ea1a 1036 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
NYX 0:85b3fd62ea1a 1037 {
NYX 0:85b3fd62ea1a 1038 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 1039
NYX 0:85b3fd62ea1a 1040 /* Check parameter */
NYX 0:85b3fd62ea1a 1041 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
NYX 0:85b3fd62ea1a 1042
NYX 0:85b3fd62ea1a 1043 if (LL_RCC_PLLSAI_IsReady())
NYX 0:85b3fd62ea1a 1044 {
NYX 0:85b3fd62ea1a 1045 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
NYX 0:85b3fd62ea1a 1046 }
NYX 0:85b3fd62ea1a 1047
NYX 0:85b3fd62ea1a 1048 return ltdc_frequency;
NYX 0:85b3fd62ea1a 1049 }
NYX 0:85b3fd62ea1a 1050 #endif /* LTDC */
NYX 0:85b3fd62ea1a 1051
NYX 0:85b3fd62ea1a 1052 #if defined(SPDIFRX)
NYX 0:85b3fd62ea1a 1053 /**
NYX 0:85b3fd62ea1a 1054 * @brief Return SPDIFRX clock frequency
NYX 0:85b3fd62ea1a 1055 * @param SPDIFRXxSource This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1056 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
NYX 0:85b3fd62ea1a 1057 * @retval SPDIFRX clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1058 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
NYX 0:85b3fd62ea1a 1059 */
NYX 0:85b3fd62ea1a 1060 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
NYX 0:85b3fd62ea1a 1061 {
NYX 0:85b3fd62ea1a 1062 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
NYX 0:85b3fd62ea1a 1063
NYX 0:85b3fd62ea1a 1064 /* Check parameter */
NYX 0:85b3fd62ea1a 1065 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
NYX 0:85b3fd62ea1a 1066
NYX 0:85b3fd62ea1a 1067 /* SPDIFRX1CLK clock frequency */
NYX 0:85b3fd62ea1a 1068 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
NYX 0:85b3fd62ea1a 1069 {
NYX 0:85b3fd62ea1a 1070 case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
NYX 0:85b3fd62ea1a 1071 if (LL_RCC_PLLI2S_IsReady())
NYX 0:85b3fd62ea1a 1072 {
NYX 0:85b3fd62ea1a 1073 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
NYX 0:85b3fd62ea1a 1074 }
NYX 0:85b3fd62ea1a 1075 break;
NYX 0:85b3fd62ea1a 1076
NYX 0:85b3fd62ea1a 1077 case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
NYX 0:85b3fd62ea1a 1078 default:
NYX 0:85b3fd62ea1a 1079 if (LL_RCC_PLL_IsReady())
NYX 0:85b3fd62ea1a 1080 {
NYX 0:85b3fd62ea1a 1081 spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
NYX 0:85b3fd62ea1a 1082 }
NYX 0:85b3fd62ea1a 1083 break;
NYX 0:85b3fd62ea1a 1084 }
NYX 0:85b3fd62ea1a 1085
NYX 0:85b3fd62ea1a 1086 return spdifrx_frequency;
NYX 0:85b3fd62ea1a 1087 }
NYX 0:85b3fd62ea1a 1088 #endif /* SPDIFRX */
NYX 0:85b3fd62ea1a 1089
NYX 0:85b3fd62ea1a 1090 /**
NYX 0:85b3fd62ea1a 1091 * @}
NYX 0:85b3fd62ea1a 1092 */
NYX 0:85b3fd62ea1a 1093
NYX 0:85b3fd62ea1a 1094 /**
NYX 0:85b3fd62ea1a 1095 * @}
NYX 0:85b3fd62ea1a 1096 */
NYX 0:85b3fd62ea1a 1097
NYX 0:85b3fd62ea1a 1098 /** @addtogroup RCC_LL_Private_Functions
NYX 0:85b3fd62ea1a 1099 * @{
NYX 0:85b3fd62ea1a 1100 */
NYX 0:85b3fd62ea1a 1101
NYX 0:85b3fd62ea1a 1102 /**
NYX 0:85b3fd62ea1a 1103 * @brief Return SYSTEM clock frequency
NYX 0:85b3fd62ea1a 1104 * @retval SYSTEM clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1105 */
NYX 0:85b3fd62ea1a 1106 uint32_t RCC_GetSystemClockFreq(void)
NYX 0:85b3fd62ea1a 1107 {
NYX 0:85b3fd62ea1a 1108 uint32_t frequency = 0U;
NYX 0:85b3fd62ea1a 1109
NYX 0:85b3fd62ea1a 1110 /* Get SYSCLK source -------------------------------------------------------*/
NYX 0:85b3fd62ea1a 1111 switch (LL_RCC_GetSysClkSource())
NYX 0:85b3fd62ea1a 1112 {
NYX 0:85b3fd62ea1a 1113 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
NYX 0:85b3fd62ea1a 1114 frequency = HSI_VALUE;
NYX 0:85b3fd62ea1a 1115 break;
NYX 0:85b3fd62ea1a 1116
NYX 0:85b3fd62ea1a 1117 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
NYX 0:85b3fd62ea1a 1118 frequency = HSE_VALUE;
NYX 0:85b3fd62ea1a 1119 break;
NYX 0:85b3fd62ea1a 1120
NYX 0:85b3fd62ea1a 1121 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
NYX 0:85b3fd62ea1a 1122 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
NYX 0:85b3fd62ea1a 1123 break;
NYX 0:85b3fd62ea1a 1124
NYX 0:85b3fd62ea1a 1125 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
NYX 0:85b3fd62ea1a 1126 case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
NYX 0:85b3fd62ea1a 1127 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
NYX 0:85b3fd62ea1a 1128 break;
NYX 0:85b3fd62ea1a 1129 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
NYX 0:85b3fd62ea1a 1130
NYX 0:85b3fd62ea1a 1131 default:
NYX 0:85b3fd62ea1a 1132 frequency = HSI_VALUE;
NYX 0:85b3fd62ea1a 1133 break;
NYX 0:85b3fd62ea1a 1134 }
NYX 0:85b3fd62ea1a 1135
NYX 0:85b3fd62ea1a 1136 return frequency;
NYX 0:85b3fd62ea1a 1137 }
NYX 0:85b3fd62ea1a 1138
NYX 0:85b3fd62ea1a 1139 /**
NYX 0:85b3fd62ea1a 1140 * @brief Return HCLK clock frequency
NYX 0:85b3fd62ea1a 1141 * @param SYSCLK_Frequency SYSCLK clock frequency
NYX 0:85b3fd62ea1a 1142 * @retval HCLK clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1143 */
NYX 0:85b3fd62ea1a 1144 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
NYX 0:85b3fd62ea1a 1145 {
NYX 0:85b3fd62ea1a 1146 /* HCLK clock frequency */
NYX 0:85b3fd62ea1a 1147 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
NYX 0:85b3fd62ea1a 1148 }
NYX 0:85b3fd62ea1a 1149
NYX 0:85b3fd62ea1a 1150 /**
NYX 0:85b3fd62ea1a 1151 * @brief Return PCLK1 clock frequency
NYX 0:85b3fd62ea1a 1152 * @param HCLK_Frequency HCLK clock frequency
NYX 0:85b3fd62ea1a 1153 * @retval PCLK1 clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1154 */
NYX 0:85b3fd62ea1a 1155 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
NYX 0:85b3fd62ea1a 1156 {
NYX 0:85b3fd62ea1a 1157 /* PCLK1 clock frequency */
NYX 0:85b3fd62ea1a 1158 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
NYX 0:85b3fd62ea1a 1159 }
NYX 0:85b3fd62ea1a 1160
NYX 0:85b3fd62ea1a 1161 /**
NYX 0:85b3fd62ea1a 1162 * @brief Return PCLK2 clock frequency
NYX 0:85b3fd62ea1a 1163 * @param HCLK_Frequency HCLK clock frequency
NYX 0:85b3fd62ea1a 1164 * @retval PCLK2 clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1165 */
NYX 0:85b3fd62ea1a 1166 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
NYX 0:85b3fd62ea1a 1167 {
NYX 0:85b3fd62ea1a 1168 /* PCLK2 clock frequency */
NYX 0:85b3fd62ea1a 1169 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
NYX 0:85b3fd62ea1a 1170 }
NYX 0:85b3fd62ea1a 1171
NYX 0:85b3fd62ea1a 1172 /**
NYX 0:85b3fd62ea1a 1173 * @brief Return PLL clock frequency used for system domain
NYX 0:85b3fd62ea1a 1174 * @param SYSCLK_Source System clock source
NYX 0:85b3fd62ea1a 1175 * @retval PLL clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1176 */
NYX 0:85b3fd62ea1a 1177 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
NYX 0:85b3fd62ea1a 1178 {
NYX 0:85b3fd62ea1a 1179 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
NYX 0:85b3fd62ea1a 1180
NYX 0:85b3fd62ea1a 1181 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
NYX 0:85b3fd62ea1a 1182 SYSCLK = PLL_VCO / (PLLP or PLLR)
NYX 0:85b3fd62ea1a 1183 */
NYX 0:85b3fd62ea1a 1184 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1185
NYX 0:85b3fd62ea1a 1186 switch (pllsource)
NYX 0:85b3fd62ea1a 1187 {
NYX 0:85b3fd62ea1a 1188 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
NYX 0:85b3fd62ea1a 1189 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1190 break;
NYX 0:85b3fd62ea1a 1191
NYX 0:85b3fd62ea1a 1192 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
NYX 0:85b3fd62ea1a 1193 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1194 break;
NYX 0:85b3fd62ea1a 1195
NYX 0:85b3fd62ea1a 1196 default:
NYX 0:85b3fd62ea1a 1197 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1198 break;
NYX 0:85b3fd62ea1a 1199 }
NYX 0:85b3fd62ea1a 1200
NYX 0:85b3fd62ea1a 1201 if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
NYX 0:85b3fd62ea1a 1202 {
NYX 0:85b3fd62ea1a 1203 plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
NYX 0:85b3fd62ea1a 1204 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
NYX 0:85b3fd62ea1a 1205 }
NYX 0:85b3fd62ea1a 1206 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
NYX 0:85b3fd62ea1a 1207 else
NYX 0:85b3fd62ea1a 1208 {
NYX 0:85b3fd62ea1a 1209 plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
NYX 0:85b3fd62ea1a 1210 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
NYX 0:85b3fd62ea1a 1211 }
NYX 0:85b3fd62ea1a 1212 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
NYX 0:85b3fd62ea1a 1213
NYX 0:85b3fd62ea1a 1214 return plloutputfreq;
NYX 0:85b3fd62ea1a 1215 }
NYX 0:85b3fd62ea1a 1216
NYX 0:85b3fd62ea1a 1217 /**
NYX 0:85b3fd62ea1a 1218 * @brief Return PLL clock frequency used for 48 MHz domain
NYX 0:85b3fd62ea1a 1219 * @retval PLL clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1220 */
NYX 0:85b3fd62ea1a 1221 uint32_t RCC_PLL_GetFreqDomain_48M(void)
NYX 0:85b3fd62ea1a 1222 {
NYX 0:85b3fd62ea1a 1223 uint32_t pllinputfreq = 0U, pllsource = 0U;
NYX 0:85b3fd62ea1a 1224
NYX 0:85b3fd62ea1a 1225 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
NYX 0:85b3fd62ea1a 1226 48M Domain clock = PLL_VCO / PLLQ
NYX 0:85b3fd62ea1a 1227 */
NYX 0:85b3fd62ea1a 1228 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1229
NYX 0:85b3fd62ea1a 1230 switch (pllsource)
NYX 0:85b3fd62ea1a 1231 {
NYX 0:85b3fd62ea1a 1232 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
NYX 0:85b3fd62ea1a 1233 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1234 break;
NYX 0:85b3fd62ea1a 1235
NYX 0:85b3fd62ea1a 1236 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
NYX 0:85b3fd62ea1a 1237 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1238 break;
NYX 0:85b3fd62ea1a 1239
NYX 0:85b3fd62ea1a 1240 default:
NYX 0:85b3fd62ea1a 1241 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1242 break;
NYX 0:85b3fd62ea1a 1243 }
NYX 0:85b3fd62ea1a 1244 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
NYX 0:85b3fd62ea1a 1245 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
NYX 0:85b3fd62ea1a 1246 }
NYX 0:85b3fd62ea1a 1247
NYX 0:85b3fd62ea1a 1248 #if defined(DSI)
NYX 0:85b3fd62ea1a 1249 /**
NYX 0:85b3fd62ea1a 1250 * @brief Return PLL clock frequency used for DSI clock
NYX 0:85b3fd62ea1a 1251 * @retval PLL clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1252 */
NYX 0:85b3fd62ea1a 1253 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
NYX 0:85b3fd62ea1a 1254 {
NYX 0:85b3fd62ea1a 1255 uint32_t pllinputfreq = 0U, pllsource = 0U;
NYX 0:85b3fd62ea1a 1256
NYX 0:85b3fd62ea1a 1257 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
NYX 0:85b3fd62ea1a 1258 DSICLK = PLL_VCO / PLLR
NYX 0:85b3fd62ea1a 1259 */
NYX 0:85b3fd62ea1a 1260 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1261
NYX 0:85b3fd62ea1a 1262 switch (pllsource)
NYX 0:85b3fd62ea1a 1263 {
NYX 0:85b3fd62ea1a 1264 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
NYX 0:85b3fd62ea1a 1265 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1266 break;
NYX 0:85b3fd62ea1a 1267
NYX 0:85b3fd62ea1a 1268 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
NYX 0:85b3fd62ea1a 1269 default:
NYX 0:85b3fd62ea1a 1270 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1271 break;
NYX 0:85b3fd62ea1a 1272 }
NYX 0:85b3fd62ea1a 1273 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
NYX 0:85b3fd62ea1a 1274 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
NYX 0:85b3fd62ea1a 1275 }
NYX 0:85b3fd62ea1a 1276 #endif /* DSI */
NYX 0:85b3fd62ea1a 1277
NYX 0:85b3fd62ea1a 1278 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
NYX 0:85b3fd62ea1a 1279 /**
NYX 0:85b3fd62ea1a 1280 * @brief Return PLL clock frequency used for I2S clock
NYX 0:85b3fd62ea1a 1281 * @retval PLL clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1282 */
NYX 0:85b3fd62ea1a 1283 uint32_t RCC_PLL_GetFreqDomain_I2S(void)
NYX 0:85b3fd62ea1a 1284 {
NYX 0:85b3fd62ea1a 1285 uint32_t pllinputfreq = 0U, pllsource = 0U;
NYX 0:85b3fd62ea1a 1286
NYX 0:85b3fd62ea1a 1287 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
NYX 0:85b3fd62ea1a 1288 I2SCLK = PLL_VCO / PLLR
NYX 0:85b3fd62ea1a 1289 */
NYX 0:85b3fd62ea1a 1290 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1291
NYX 0:85b3fd62ea1a 1292 switch (pllsource)
NYX 0:85b3fd62ea1a 1293 {
NYX 0:85b3fd62ea1a 1294 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
NYX 0:85b3fd62ea1a 1295 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1296 break;
NYX 0:85b3fd62ea1a 1297
NYX 0:85b3fd62ea1a 1298 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
NYX 0:85b3fd62ea1a 1299 default:
NYX 0:85b3fd62ea1a 1300 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1301 break;
NYX 0:85b3fd62ea1a 1302 }
NYX 0:85b3fd62ea1a 1303 return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
NYX 0:85b3fd62ea1a 1304 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
NYX 0:85b3fd62ea1a 1305 }
NYX 0:85b3fd62ea1a 1306 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
NYX 0:85b3fd62ea1a 1307
NYX 0:85b3fd62ea1a 1308 #if defined(SPDIFRX)
NYX 0:85b3fd62ea1a 1309 /**
NYX 0:85b3fd62ea1a 1310 * @brief Return PLL clock frequency used for SPDIFRX clock
NYX 0:85b3fd62ea1a 1311 * @retval PLL clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1312 */
NYX 0:85b3fd62ea1a 1313 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
NYX 0:85b3fd62ea1a 1314 {
NYX 0:85b3fd62ea1a 1315 uint32_t pllinputfreq = 0U, pllsource = 0U;
NYX 0:85b3fd62ea1a 1316
NYX 0:85b3fd62ea1a 1317 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
NYX 0:85b3fd62ea1a 1318 SPDIFRXCLK = PLL_VCO / PLLR
NYX 0:85b3fd62ea1a 1319 */
NYX 0:85b3fd62ea1a 1320 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1321
NYX 0:85b3fd62ea1a 1322 switch (pllsource)
NYX 0:85b3fd62ea1a 1323 {
NYX 0:85b3fd62ea1a 1324 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
NYX 0:85b3fd62ea1a 1325 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1326 break;
NYX 0:85b3fd62ea1a 1327
NYX 0:85b3fd62ea1a 1328 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
NYX 0:85b3fd62ea1a 1329 default:
NYX 0:85b3fd62ea1a 1330 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1331 break;
NYX 0:85b3fd62ea1a 1332 }
NYX 0:85b3fd62ea1a 1333 return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
NYX 0:85b3fd62ea1a 1334 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
NYX 0:85b3fd62ea1a 1335 }
NYX 0:85b3fd62ea1a 1336 #endif /* SPDIFRX */
NYX 0:85b3fd62ea1a 1337
NYX 0:85b3fd62ea1a 1338 #if defined(RCC_PLLCFGR_PLLR)
NYX 0:85b3fd62ea1a 1339 #if defined(SAI1)
NYX 0:85b3fd62ea1a 1340 /**
NYX 0:85b3fd62ea1a 1341 * @brief Return PLL clock frequency used for SAI clock
NYX 0:85b3fd62ea1a 1342 * @retval PLL clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1343 */
NYX 0:85b3fd62ea1a 1344 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
NYX 0:85b3fd62ea1a 1345 {
NYX 0:85b3fd62ea1a 1346 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
NYX 0:85b3fd62ea1a 1347
NYX 0:85b3fd62ea1a 1348 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
NYX 0:85b3fd62ea1a 1349 SAICLK = (PLL_VCO / PLLR) / PLLDIVR
NYX 0:85b3fd62ea1a 1350 or
NYX 0:85b3fd62ea1a 1351 SAICLK = PLL_VCO / PLLR
NYX 0:85b3fd62ea1a 1352 */
NYX 0:85b3fd62ea1a 1353 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1354
NYX 0:85b3fd62ea1a 1355 switch (pllsource)
NYX 0:85b3fd62ea1a 1356 {
NYX 0:85b3fd62ea1a 1357 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
NYX 0:85b3fd62ea1a 1358 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1359 break;
NYX 0:85b3fd62ea1a 1360
NYX 0:85b3fd62ea1a 1361 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
NYX 0:85b3fd62ea1a 1362 default:
NYX 0:85b3fd62ea1a 1363 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1364 break;
NYX 0:85b3fd62ea1a 1365 }
NYX 0:85b3fd62ea1a 1366
NYX 0:85b3fd62ea1a 1367 #if defined(RCC_DCKCFGR_PLLDIVR)
NYX 0:85b3fd62ea1a 1368 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
NYX 0:85b3fd62ea1a 1369 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
NYX 0:85b3fd62ea1a 1370 #else
NYX 0:85b3fd62ea1a 1371 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
NYX 0:85b3fd62ea1a 1372 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
NYX 0:85b3fd62ea1a 1373 #endif /* RCC_DCKCFGR_PLLDIVR */
NYX 0:85b3fd62ea1a 1374
NYX 0:85b3fd62ea1a 1375 return plloutputfreq;
NYX 0:85b3fd62ea1a 1376 }
NYX 0:85b3fd62ea1a 1377 #endif /* SAI1 */
NYX 0:85b3fd62ea1a 1378 #endif /* RCC_PLLCFGR_PLLR */
NYX 0:85b3fd62ea1a 1379
NYX 0:85b3fd62ea1a 1380 #if defined(RCC_PLLSAI_SUPPORT)
NYX 0:85b3fd62ea1a 1381 /**
NYX 0:85b3fd62ea1a 1382 * @brief Return PLLSAI clock frequency used for SAI domain
NYX 0:85b3fd62ea1a 1383 * @retval PLLSAI clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1384 */
NYX 0:85b3fd62ea1a 1385 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
NYX 0:85b3fd62ea1a 1386 {
NYX 0:85b3fd62ea1a 1387 uint32_t pllinputfreq = 0U, pllsource = 0U;
NYX 0:85b3fd62ea1a 1388
NYX 0:85b3fd62ea1a 1389 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
NYX 0:85b3fd62ea1a 1390 SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
NYX 0:85b3fd62ea1a 1391 */
NYX 0:85b3fd62ea1a 1392 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1393
NYX 0:85b3fd62ea1a 1394 switch (pllsource)
NYX 0:85b3fd62ea1a 1395 {
NYX 0:85b3fd62ea1a 1396 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
NYX 0:85b3fd62ea1a 1397 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1398 break;
NYX 0:85b3fd62ea1a 1399
NYX 0:85b3fd62ea1a 1400 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
NYX 0:85b3fd62ea1a 1401 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1402 break;
NYX 0:85b3fd62ea1a 1403
NYX 0:85b3fd62ea1a 1404 default:
NYX 0:85b3fd62ea1a 1405 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1406 break;
NYX 0:85b3fd62ea1a 1407 }
NYX 0:85b3fd62ea1a 1408 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
NYX 0:85b3fd62ea1a 1409 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
NYX 0:85b3fd62ea1a 1410 }
NYX 0:85b3fd62ea1a 1411
NYX 0:85b3fd62ea1a 1412 #if defined(RCC_PLLSAICFGR_PLLSAIP)
NYX 0:85b3fd62ea1a 1413 /**
NYX 0:85b3fd62ea1a 1414 * @brief Return PLLSAI clock frequency used for 48Mhz domain
NYX 0:85b3fd62ea1a 1415 * @retval PLLSAI clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1416 */
NYX 0:85b3fd62ea1a 1417 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
NYX 0:85b3fd62ea1a 1418 {
NYX 0:85b3fd62ea1a 1419 uint32_t pllinputfreq = 0U, pllsource = 0U;
NYX 0:85b3fd62ea1a 1420
NYX 0:85b3fd62ea1a 1421 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
NYX 0:85b3fd62ea1a 1422 48M Domain clock = PLLSAI_VCO / PLLSAIP
NYX 0:85b3fd62ea1a 1423 */
NYX 0:85b3fd62ea1a 1424 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1425
NYX 0:85b3fd62ea1a 1426 switch (pllsource)
NYX 0:85b3fd62ea1a 1427 {
NYX 0:85b3fd62ea1a 1428 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
NYX 0:85b3fd62ea1a 1429 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1430 break;
NYX 0:85b3fd62ea1a 1431
NYX 0:85b3fd62ea1a 1432 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
NYX 0:85b3fd62ea1a 1433 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1434 break;
NYX 0:85b3fd62ea1a 1435
NYX 0:85b3fd62ea1a 1436 default:
NYX 0:85b3fd62ea1a 1437 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1438 break;
NYX 0:85b3fd62ea1a 1439 }
NYX 0:85b3fd62ea1a 1440 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
NYX 0:85b3fd62ea1a 1441 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
NYX 0:85b3fd62ea1a 1442 }
NYX 0:85b3fd62ea1a 1443 #endif /* RCC_PLLSAICFGR_PLLSAIP */
NYX 0:85b3fd62ea1a 1444
NYX 0:85b3fd62ea1a 1445 #if defined(LTDC)
NYX 0:85b3fd62ea1a 1446 /**
NYX 0:85b3fd62ea1a 1447 * @brief Return PLLSAI clock frequency used for LTDC domain
NYX 0:85b3fd62ea1a 1448 * @retval PLLSAI clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1449 */
NYX 0:85b3fd62ea1a 1450 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
NYX 0:85b3fd62ea1a 1451 {
NYX 0:85b3fd62ea1a 1452 uint32_t pllinputfreq = 0U, pllsource = 0U;
NYX 0:85b3fd62ea1a 1453
NYX 0:85b3fd62ea1a 1454 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
NYX 0:85b3fd62ea1a 1455 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
NYX 0:85b3fd62ea1a 1456 */
NYX 0:85b3fd62ea1a 1457 pllsource = LL_RCC_PLL_GetMainSource();
NYX 0:85b3fd62ea1a 1458
NYX 0:85b3fd62ea1a 1459 switch (pllsource)
NYX 0:85b3fd62ea1a 1460 {
NYX 0:85b3fd62ea1a 1461 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
NYX 0:85b3fd62ea1a 1462 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1463 break;
NYX 0:85b3fd62ea1a 1464
NYX 0:85b3fd62ea1a 1465 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
NYX 0:85b3fd62ea1a 1466 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1467 break;
NYX 0:85b3fd62ea1a 1468
NYX 0:85b3fd62ea1a 1469 default:
NYX 0:85b3fd62ea1a 1470 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1471 break;
NYX 0:85b3fd62ea1a 1472 }
NYX 0:85b3fd62ea1a 1473 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
NYX 0:85b3fd62ea1a 1474 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
NYX 0:85b3fd62ea1a 1475 }
NYX 0:85b3fd62ea1a 1476 #endif /* LTDC */
NYX 0:85b3fd62ea1a 1477 #endif /* RCC_PLLSAI_SUPPORT */
NYX 0:85b3fd62ea1a 1478
NYX 0:85b3fd62ea1a 1479 #if defined(RCC_PLLI2S_SUPPORT)
NYX 0:85b3fd62ea1a 1480 #if defined(SAI1)
NYX 0:85b3fd62ea1a 1481 /**
NYX 0:85b3fd62ea1a 1482 * @brief Return PLLI2S clock frequency used for SAI domains
NYX 0:85b3fd62ea1a 1483 * @retval PLLI2S clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1484 */
NYX 0:85b3fd62ea1a 1485 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
NYX 0:85b3fd62ea1a 1486 {
NYX 0:85b3fd62ea1a 1487 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
NYX 0:85b3fd62ea1a 1488
NYX 0:85b3fd62ea1a 1489 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
NYX 0:85b3fd62ea1a 1490 SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
NYX 0:85b3fd62ea1a 1491 or
NYX 0:85b3fd62ea1a 1492 SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
NYX 0:85b3fd62ea1a 1493 */
NYX 0:85b3fd62ea1a 1494 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
NYX 0:85b3fd62ea1a 1495
NYX 0:85b3fd62ea1a 1496 switch (plli2ssource)
NYX 0:85b3fd62ea1a 1497 {
NYX 0:85b3fd62ea1a 1498 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1499 plli2sinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1500 break;
NYX 0:85b3fd62ea1a 1501
NYX 0:85b3fd62ea1a 1502 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
NYX 0:85b3fd62ea1a 1503 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1504 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
NYX 0:85b3fd62ea1a 1505 break;
NYX 0:85b3fd62ea1a 1506 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
NYX 0:85b3fd62ea1a 1507
NYX 0:85b3fd62ea1a 1508 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1509 default:
NYX 0:85b3fd62ea1a 1510 plli2sinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1511 break;
NYX 0:85b3fd62ea1a 1512 }
NYX 0:85b3fd62ea1a 1513
NYX 0:85b3fd62ea1a 1514 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX 0:85b3fd62ea1a 1515 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
NYX 0:85b3fd62ea1a 1516 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
NYX 0:85b3fd62ea1a 1517 #else
NYX 0:85b3fd62ea1a 1518 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
NYX 0:85b3fd62ea1a 1519 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
NYX 0:85b3fd62ea1a 1520 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
NYX 0:85b3fd62ea1a 1521
NYX 0:85b3fd62ea1a 1522 return plli2soutputfreq;
NYX 0:85b3fd62ea1a 1523 }
NYX 0:85b3fd62ea1a 1524 #endif /* SAI1 */
NYX 0:85b3fd62ea1a 1525
NYX 0:85b3fd62ea1a 1526 #if defined(SPDIFRX)
NYX 0:85b3fd62ea1a 1527 /**
NYX 0:85b3fd62ea1a 1528 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
NYX 0:85b3fd62ea1a 1529 * @retval PLLI2S clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1530 */
NYX 0:85b3fd62ea1a 1531 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
NYX 0:85b3fd62ea1a 1532 {
NYX 0:85b3fd62ea1a 1533 uint32_t pllinputfreq = 0U, pllsource = 0U;
NYX 0:85b3fd62ea1a 1534
NYX 0:85b3fd62ea1a 1535 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
NYX 0:85b3fd62ea1a 1536 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
NYX 0:85b3fd62ea1a 1537 */
NYX 0:85b3fd62ea1a 1538 pllsource = LL_RCC_PLLI2S_GetMainSource();
NYX 0:85b3fd62ea1a 1539
NYX 0:85b3fd62ea1a 1540 switch (pllsource)
NYX 0:85b3fd62ea1a 1541 {
NYX 0:85b3fd62ea1a 1542 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1543 pllinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1544 break;
NYX 0:85b3fd62ea1a 1545
NYX 0:85b3fd62ea1a 1546 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1547 default:
NYX 0:85b3fd62ea1a 1548 pllinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1549 break;
NYX 0:85b3fd62ea1a 1550 }
NYX 0:85b3fd62ea1a 1551
NYX 0:85b3fd62ea1a 1552 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
NYX 0:85b3fd62ea1a 1553 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
NYX 0:85b3fd62ea1a 1554 }
NYX 0:85b3fd62ea1a 1555 #endif /* SPDIFRX */
NYX 0:85b3fd62ea1a 1556
NYX 0:85b3fd62ea1a 1557 /**
NYX 0:85b3fd62ea1a 1558 * @brief Return PLLI2S clock frequency used for I2S domain
NYX 0:85b3fd62ea1a 1559 * @retval PLLI2S clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1560 */
NYX 0:85b3fd62ea1a 1561 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
NYX 0:85b3fd62ea1a 1562 {
NYX 0:85b3fd62ea1a 1563 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
NYX 0:85b3fd62ea1a 1564
NYX 0:85b3fd62ea1a 1565 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
NYX 0:85b3fd62ea1a 1566 I2S Domain clock = PLLI2S_VCO / PLLI2SR
NYX 0:85b3fd62ea1a 1567 */
NYX 0:85b3fd62ea1a 1568 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
NYX 0:85b3fd62ea1a 1569
NYX 0:85b3fd62ea1a 1570 switch (plli2ssource)
NYX 0:85b3fd62ea1a 1571 {
NYX 0:85b3fd62ea1a 1572 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1573 plli2sinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1574 break;
NYX 0:85b3fd62ea1a 1575
NYX 0:85b3fd62ea1a 1576 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
NYX 0:85b3fd62ea1a 1577 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1578 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
NYX 0:85b3fd62ea1a 1579 break;
NYX 0:85b3fd62ea1a 1580 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
NYX 0:85b3fd62ea1a 1581
NYX 0:85b3fd62ea1a 1582 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1583 default:
NYX 0:85b3fd62ea1a 1584 plli2sinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1585 break;
NYX 0:85b3fd62ea1a 1586 }
NYX 0:85b3fd62ea1a 1587
NYX 0:85b3fd62ea1a 1588 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
NYX 0:85b3fd62ea1a 1589 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
NYX 0:85b3fd62ea1a 1590
NYX 0:85b3fd62ea1a 1591 return plli2soutputfreq;
NYX 0:85b3fd62ea1a 1592 }
NYX 0:85b3fd62ea1a 1593
NYX 0:85b3fd62ea1a 1594 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
NYX 0:85b3fd62ea1a 1595 /**
NYX 0:85b3fd62ea1a 1596 * @brief Return PLLI2S clock frequency used for 48Mhz domain
NYX 0:85b3fd62ea1a 1597 * @retval PLLI2S clock frequency (in Hz)
NYX 0:85b3fd62ea1a 1598 */
NYX 0:85b3fd62ea1a 1599 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
NYX 0:85b3fd62ea1a 1600 {
NYX 0:85b3fd62ea1a 1601 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
NYX 0:85b3fd62ea1a 1602
NYX 0:85b3fd62ea1a 1603 /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
NYX 0:85b3fd62ea1a 1604 48M Domain clock = PLLI2S_VCO / PLLI2SQ
NYX 0:85b3fd62ea1a 1605 */
NYX 0:85b3fd62ea1a 1606 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
NYX 0:85b3fd62ea1a 1607
NYX 0:85b3fd62ea1a 1608 switch (plli2ssource)
NYX 0:85b3fd62ea1a 1609 {
NYX 0:85b3fd62ea1a 1610 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1611 plli2sinputfreq = HSE_VALUE;
NYX 0:85b3fd62ea1a 1612 break;
NYX 0:85b3fd62ea1a 1613
NYX 0:85b3fd62ea1a 1614 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
NYX 0:85b3fd62ea1a 1615 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1616 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
NYX 0:85b3fd62ea1a 1617 break;
NYX 0:85b3fd62ea1a 1618 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
NYX 0:85b3fd62ea1a 1619
NYX 0:85b3fd62ea1a 1620 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
NYX 0:85b3fd62ea1a 1621 default:
NYX 0:85b3fd62ea1a 1622 plli2sinputfreq = HSI_VALUE;
NYX 0:85b3fd62ea1a 1623 break;
NYX 0:85b3fd62ea1a 1624 }
NYX 0:85b3fd62ea1a 1625
NYX 0:85b3fd62ea1a 1626 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
NYX 0:85b3fd62ea1a 1627 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
NYX 0:85b3fd62ea1a 1628
NYX 0:85b3fd62ea1a 1629 return plli2soutputfreq;
NYX 0:85b3fd62ea1a 1630 }
NYX 0:85b3fd62ea1a 1631 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
NYX 0:85b3fd62ea1a 1632 #endif /* RCC_PLLI2S_SUPPORT */
NYX 0:85b3fd62ea1a 1633 /**
NYX 0:85b3fd62ea1a 1634 * @}
NYX 0:85b3fd62ea1a 1635 */
NYX 0:85b3fd62ea1a 1636
NYX 0:85b3fd62ea1a 1637 /**
NYX 0:85b3fd62ea1a 1638 * @}
NYX 0:85b3fd62ea1a 1639 */
NYX 0:85b3fd62ea1a 1640
NYX 0:85b3fd62ea1a 1641 #endif /* defined(RCC) */
NYX 0:85b3fd62ea1a 1642
NYX 0:85b3fd62ea1a 1643 /**
NYX 0:85b3fd62ea1a 1644 * @}
NYX 0:85b3fd62ea1a 1645 */
NYX 0:85b3fd62ea1a 1646
NYX 0:85b3fd62ea1a 1647 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 1648
NYX 0:85b3fd62ea1a 1649 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/