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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

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NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_pwr.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of PWR LL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_LL_PWR_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_LL_PWR_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #include "stm32f4xx.h"
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /** @addtogroup STM32F4xx_LL_Driver
NYX 0:85b3fd62ea1a 50 * @{
NYX 0:85b3fd62ea1a 51 */
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 #if defined(PWR)
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 /** @defgroup PWR_LL PWR
NYX 0:85b3fd62ea1a 56 * @{
NYX 0:85b3fd62ea1a 57 */
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 61 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 62 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 63 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 64 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 65 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
NYX 0:85b3fd62ea1a 66 * @{
NYX 0:85b3fd62ea1a 67 */
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
NYX 0:85b3fd62ea1a 70 * @brief Flags defines which can be used with LL_PWR_WriteReg function
NYX 0:85b3fd62ea1a 71 * @{
NYX 0:85b3fd62ea1a 72 */
NYX 0:85b3fd62ea1a 73 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
NYX 0:85b3fd62ea1a 74 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
NYX 0:85b3fd62ea1a 75 /**
NYX 0:85b3fd62ea1a 76 * @}
NYX 0:85b3fd62ea1a 77 */
NYX 0:85b3fd62ea1a 78
NYX 0:85b3fd62ea1a 79 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
NYX 0:85b3fd62ea1a 80 * @brief Flags defines which can be used with LL_PWR_ReadReg function
NYX 0:85b3fd62ea1a 81 * @{
NYX 0:85b3fd62ea1a 82 */
NYX 0:85b3fd62ea1a 83 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
NYX 0:85b3fd62ea1a 84 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
NYX 0:85b3fd62ea1a 85 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
NYX 0:85b3fd62ea1a 86 #define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */
NYX 0:85b3fd62ea1a 87 #if defined(PWR_CSR_EWUP)
NYX 0:85b3fd62ea1a 88 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */
NYX 0:85b3fd62ea1a 89 #elif defined(PWR_CSR_EWUP1)
NYX 0:85b3fd62ea1a 90 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
NYX 0:85b3fd62ea1a 91 #endif /* PWR_CSR_EWUP */
NYX 0:85b3fd62ea1a 92 #if defined(PWR_CSR_EWUP2)
NYX 0:85b3fd62ea1a 93 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
NYX 0:85b3fd62ea1a 94 #endif /* PWR_CSR_EWUP2 */
NYX 0:85b3fd62ea1a 95 #if defined(PWR_CSR_EWUP3)
NYX 0:85b3fd62ea1a 96 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
NYX 0:85b3fd62ea1a 97 #endif /* PWR_CSR_EWUP3 */
NYX 0:85b3fd62ea1a 98 /**
NYX 0:85b3fd62ea1a 99 * @}
NYX 0:85b3fd62ea1a 100 */
NYX 0:85b3fd62ea1a 101
NYX 0:85b3fd62ea1a 102 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
NYX 0:85b3fd62ea1a 103 * @{
NYX 0:85b3fd62ea1a 104 */
NYX 0:85b3fd62ea1a 105 #if defined(PWR_CR_VOS_0)
NYX 0:85b3fd62ea1a 106 #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
NYX 0:85b3fd62ea1a 107 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
NYX 0:85b3fd62ea1a 108 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
NYX 0:85b3fd62ea1a 109 #else
NYX 0:85b3fd62ea1a 110 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
NYX 0:85b3fd62ea1a 111 #define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
NYX 0:85b3fd62ea1a 112 #endif /* PWR_CR_VOS_0 */
NYX 0:85b3fd62ea1a 113 /**
NYX 0:85b3fd62ea1a 114 * @}
NYX 0:85b3fd62ea1a 115 */
NYX 0:85b3fd62ea1a 116
NYX 0:85b3fd62ea1a 117 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
NYX 0:85b3fd62ea1a 118 * @{
NYX 0:85b3fd62ea1a 119 */
NYX 0:85b3fd62ea1a 120 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
NYX 0:85b3fd62ea1a 121 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
NYX 0:85b3fd62ea1a 122 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
NYX 0:85b3fd62ea1a 123 #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
NYX 0:85b3fd62ea1a 124 #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
NYX 0:85b3fd62ea1a 125 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
NYX 0:85b3fd62ea1a 126 #if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
NYX 0:85b3fd62ea1a 127 #define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
NYX 0:85b3fd62ea1a 128 #define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
NYX 0:85b3fd62ea1a 129 #endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
NYX 0:85b3fd62ea1a 130 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
NYX 0:85b3fd62ea1a 131 /**
NYX 0:85b3fd62ea1a 132 * @}
NYX 0:85b3fd62ea1a 133 */
NYX 0:85b3fd62ea1a 134
NYX 0:85b3fd62ea1a 135 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
NYX 0:85b3fd62ea1a 136 * @{
NYX 0:85b3fd62ea1a 137 */
NYX 0:85b3fd62ea1a 138 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
NYX 0:85b3fd62ea1a 139 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
NYX 0:85b3fd62ea1a 140 /**
NYX 0:85b3fd62ea1a 141 * @}
NYX 0:85b3fd62ea1a 142 */
NYX 0:85b3fd62ea1a 143
NYX 0:85b3fd62ea1a 144 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
NYX 0:85b3fd62ea1a 145 * @{
NYX 0:85b3fd62ea1a 146 */
NYX 0:85b3fd62ea1a 147 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
NYX 0:85b3fd62ea1a 148 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
NYX 0:85b3fd62ea1a 149 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
NYX 0:85b3fd62ea1a 150 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
NYX 0:85b3fd62ea1a 151 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
NYX 0:85b3fd62ea1a 152 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
NYX 0:85b3fd62ea1a 153 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
NYX 0:85b3fd62ea1a 154 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
NYX 0:85b3fd62ea1a 155 /**
NYX 0:85b3fd62ea1a 156 * @}
NYX 0:85b3fd62ea1a 157 */
NYX 0:85b3fd62ea1a 158 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
NYX 0:85b3fd62ea1a 159 * @{
NYX 0:85b3fd62ea1a 160 */
NYX 0:85b3fd62ea1a 161 #if defined(PWR_CSR_EWUP)
NYX 0:85b3fd62ea1a 162 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */
NYX 0:85b3fd62ea1a 163 #endif /* PWR_CSR_EWUP */
NYX 0:85b3fd62ea1a 164 #if defined(PWR_CSR_EWUP1)
NYX 0:85b3fd62ea1a 165 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
NYX 0:85b3fd62ea1a 166 #endif /* PWR_CSR_EWUP1 */
NYX 0:85b3fd62ea1a 167 #if defined(PWR_CSR_EWUP2)
NYX 0:85b3fd62ea1a 168 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */
NYX 0:85b3fd62ea1a 169 #endif /* PWR_CSR_EWUP2 */
NYX 0:85b3fd62ea1a 170 #if defined(PWR_CSR_EWUP3)
NYX 0:85b3fd62ea1a 171 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */
NYX 0:85b3fd62ea1a 172 #endif /* PWR_CSR_EWUP3 */
NYX 0:85b3fd62ea1a 173 /**
NYX 0:85b3fd62ea1a 174 * @}
NYX 0:85b3fd62ea1a 175 */
NYX 0:85b3fd62ea1a 176
NYX 0:85b3fd62ea1a 177 /**
NYX 0:85b3fd62ea1a 178 * @}
NYX 0:85b3fd62ea1a 179 */
NYX 0:85b3fd62ea1a 180
NYX 0:85b3fd62ea1a 181
NYX 0:85b3fd62ea1a 182 /* Exported macro ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 183 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
NYX 0:85b3fd62ea1a 184 * @{
NYX 0:85b3fd62ea1a 185 */
NYX 0:85b3fd62ea1a 186
NYX 0:85b3fd62ea1a 187 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
NYX 0:85b3fd62ea1a 188 * @{
NYX 0:85b3fd62ea1a 189 */
NYX 0:85b3fd62ea1a 190
NYX 0:85b3fd62ea1a 191 /**
NYX 0:85b3fd62ea1a 192 * @brief Write a value in PWR register
NYX 0:85b3fd62ea1a 193 * @param __REG__ Register to be written
NYX 0:85b3fd62ea1a 194 * @param __VALUE__ Value to be written in the register
NYX 0:85b3fd62ea1a 195 * @retval None
NYX 0:85b3fd62ea1a 196 */
NYX 0:85b3fd62ea1a 197 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
NYX 0:85b3fd62ea1a 198
NYX 0:85b3fd62ea1a 199 /**
NYX 0:85b3fd62ea1a 200 * @brief Read a value in PWR register
NYX 0:85b3fd62ea1a 201 * @param __REG__ Register to be read
NYX 0:85b3fd62ea1a 202 * @retval Register value
NYX 0:85b3fd62ea1a 203 */
NYX 0:85b3fd62ea1a 204 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
NYX 0:85b3fd62ea1a 205 /**
NYX 0:85b3fd62ea1a 206 * @}
NYX 0:85b3fd62ea1a 207 */
NYX 0:85b3fd62ea1a 208
NYX 0:85b3fd62ea1a 209 /**
NYX 0:85b3fd62ea1a 210 * @}
NYX 0:85b3fd62ea1a 211 */
NYX 0:85b3fd62ea1a 212
NYX 0:85b3fd62ea1a 213 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 214 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
NYX 0:85b3fd62ea1a 215 * @{
NYX 0:85b3fd62ea1a 216 */
NYX 0:85b3fd62ea1a 217
NYX 0:85b3fd62ea1a 218 /** @defgroup PWR_LL_EF_Configuration Configuration
NYX 0:85b3fd62ea1a 219 * @{
NYX 0:85b3fd62ea1a 220 */
NYX 0:85b3fd62ea1a 221 #if defined(PWR_CR_FISSR)
NYX 0:85b3fd62ea1a 222 /**
NYX 0:85b3fd62ea1a 223 * @brief Enable FLASH interface STOP while system Run is ON
NYX 0:85b3fd62ea1a 224 * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP
NYX 0:85b3fd62ea1a 225 * @note This mode is enabled only with STOP low power mode.
NYX 0:85b3fd62ea1a 226 * @retval None
NYX 0:85b3fd62ea1a 227 */
NYX 0:85b3fd62ea1a 228 __STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
NYX 0:85b3fd62ea1a 229 {
NYX 0:85b3fd62ea1a 230 SET_BIT(PWR->CR, PWR_CR_FISSR);
NYX 0:85b3fd62ea1a 231 }
NYX 0:85b3fd62ea1a 232
NYX 0:85b3fd62ea1a 233 /**
NYX 0:85b3fd62ea1a 234 * @brief Disable FLASH Interface STOP while system Run is ON
NYX 0:85b3fd62ea1a 235 * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP
NYX 0:85b3fd62ea1a 236 * @retval None
NYX 0:85b3fd62ea1a 237 */
NYX 0:85b3fd62ea1a 238 __STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
NYX 0:85b3fd62ea1a 239 {
NYX 0:85b3fd62ea1a 240 CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
NYX 0:85b3fd62ea1a 241 }
NYX 0:85b3fd62ea1a 242
NYX 0:85b3fd62ea1a 243 /**
NYX 0:85b3fd62ea1a 244 * @brief Check if FLASH Interface STOP while system Run feature is enabled
NYX 0:85b3fd62ea1a 245 * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP
NYX 0:85b3fd62ea1a 246 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 247 */
NYX 0:85b3fd62ea1a 248 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
NYX 0:85b3fd62ea1a 249 {
NYX 0:85b3fd62ea1a 250 return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
NYX 0:85b3fd62ea1a 251 }
NYX 0:85b3fd62ea1a 252 #endif /* PWR_CR_FISSR */
NYX 0:85b3fd62ea1a 253
NYX 0:85b3fd62ea1a 254 #if defined(PWR_CR_FMSSR)
NYX 0:85b3fd62ea1a 255 /**
NYX 0:85b3fd62ea1a 256 * @brief Enable FLASH Memory STOP while system Run is ON
NYX 0:85b3fd62ea1a 257 * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP
NYX 0:85b3fd62ea1a 258 * @note This mode is enabled only with STOP low power mode.
NYX 0:85b3fd62ea1a 259 * @retval None
NYX 0:85b3fd62ea1a 260 */
NYX 0:85b3fd62ea1a 261 __STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
NYX 0:85b3fd62ea1a 262 {
NYX 0:85b3fd62ea1a 263 SET_BIT(PWR->CR, PWR_CR_FMSSR);
NYX 0:85b3fd62ea1a 264 }
NYX 0:85b3fd62ea1a 265
NYX 0:85b3fd62ea1a 266 /**
NYX 0:85b3fd62ea1a 267 * @brief Disable FLASH Memory STOP while system Run is ON
NYX 0:85b3fd62ea1a 268 * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP
NYX 0:85b3fd62ea1a 269 * @retval None
NYX 0:85b3fd62ea1a 270 */
NYX 0:85b3fd62ea1a 271 __STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
NYX 0:85b3fd62ea1a 272 {
NYX 0:85b3fd62ea1a 273 CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
NYX 0:85b3fd62ea1a 274 }
NYX 0:85b3fd62ea1a 275
NYX 0:85b3fd62ea1a 276 /**
NYX 0:85b3fd62ea1a 277 * @brief Check if FLASH Memory STOP while system Run feature is enabled
NYX 0:85b3fd62ea1a 278 * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP
NYX 0:85b3fd62ea1a 279 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 280 */
NYX 0:85b3fd62ea1a 281 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
NYX 0:85b3fd62ea1a 282 {
NYX 0:85b3fd62ea1a 283 return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
NYX 0:85b3fd62ea1a 284 }
NYX 0:85b3fd62ea1a 285 #endif /* PWR_CR_FMSSR */
NYX 0:85b3fd62ea1a 286 #if defined(PWR_CR_UDEN)
NYX 0:85b3fd62ea1a 287 /**
NYX 0:85b3fd62ea1a 288 * @brief Enable Under Drive Mode
NYX 0:85b3fd62ea1a 289 * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
NYX 0:85b3fd62ea1a 290 * @note This mode is enabled only with STOP low power mode.
NYX 0:85b3fd62ea1a 291 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
NYX 0:85b3fd62ea1a 292 * mode is only available when the main Regulator or the low power Regulator
NYX 0:85b3fd62ea1a 293 * is in low voltage mode.
NYX 0:85b3fd62ea1a 294 * @note If the Under-drive mode was enabled, it is automatically disabled after
NYX 0:85b3fd62ea1a 295 * exiting Stop mode.
NYX 0:85b3fd62ea1a 296 * When the voltage Regulator operates in Under-drive mode, an additional
NYX 0:85b3fd62ea1a 297 * startup delay is induced when waking up from Stop mode.
NYX 0:85b3fd62ea1a 298 * @retval None
NYX 0:85b3fd62ea1a 299 */
NYX 0:85b3fd62ea1a 300 __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
NYX 0:85b3fd62ea1a 301 {
NYX 0:85b3fd62ea1a 302 SET_BIT(PWR->CR, PWR_CR_UDEN);
NYX 0:85b3fd62ea1a 303 }
NYX 0:85b3fd62ea1a 304
NYX 0:85b3fd62ea1a 305 /**
NYX 0:85b3fd62ea1a 306 * @brief Disable Under Drive Mode
NYX 0:85b3fd62ea1a 307 * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode
NYX 0:85b3fd62ea1a 308 * @retval None
NYX 0:85b3fd62ea1a 309 */
NYX 0:85b3fd62ea1a 310 __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
NYX 0:85b3fd62ea1a 311 {
NYX 0:85b3fd62ea1a 312 CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
NYX 0:85b3fd62ea1a 313 }
NYX 0:85b3fd62ea1a 314
NYX 0:85b3fd62ea1a 315 /**
NYX 0:85b3fd62ea1a 316 * @brief Check if Under Drive Mode is enabled
NYX 0:85b3fd62ea1a 317 * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode
NYX 0:85b3fd62ea1a 318 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 319 */
NYX 0:85b3fd62ea1a 320 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
NYX 0:85b3fd62ea1a 321 {
NYX 0:85b3fd62ea1a 322 return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
NYX 0:85b3fd62ea1a 323 }
NYX 0:85b3fd62ea1a 324 #endif /* PWR_CR_UDEN */
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326 #if defined(PWR_CR_ODSWEN)
NYX 0:85b3fd62ea1a 327 /**
NYX 0:85b3fd62ea1a 328 * @brief Enable Over drive switching
NYX 0:85b3fd62ea1a 329 * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching
NYX 0:85b3fd62ea1a 330 * @retval None
NYX 0:85b3fd62ea1a 331 */
NYX 0:85b3fd62ea1a 332 __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
NYX 0:85b3fd62ea1a 333 {
NYX 0:85b3fd62ea1a 334 SET_BIT(PWR->CR, PWR_CR_ODSWEN);
NYX 0:85b3fd62ea1a 335 }
NYX 0:85b3fd62ea1a 336
NYX 0:85b3fd62ea1a 337 /**
NYX 0:85b3fd62ea1a 338 * @brief Disable Over drive switching
NYX 0:85b3fd62ea1a 339 * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching
NYX 0:85b3fd62ea1a 340 * @retval None
NYX 0:85b3fd62ea1a 341 */
NYX 0:85b3fd62ea1a 342 __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
NYX 0:85b3fd62ea1a 343 {
NYX 0:85b3fd62ea1a 344 CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
NYX 0:85b3fd62ea1a 345 }
NYX 0:85b3fd62ea1a 346
NYX 0:85b3fd62ea1a 347 /**
NYX 0:85b3fd62ea1a 348 * @brief Check if Over drive switching is enabled
NYX 0:85b3fd62ea1a 349 * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching
NYX 0:85b3fd62ea1a 350 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 351 */
NYX 0:85b3fd62ea1a 352 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
NYX 0:85b3fd62ea1a 353 {
NYX 0:85b3fd62ea1a 354 return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
NYX 0:85b3fd62ea1a 355 }
NYX 0:85b3fd62ea1a 356 #endif /* PWR_CR_ODSWEN */
NYX 0:85b3fd62ea1a 357 #if defined(PWR_CR_ODEN)
NYX 0:85b3fd62ea1a 358 /**
NYX 0:85b3fd62ea1a 359 * @brief Enable Over drive Mode
NYX 0:85b3fd62ea1a 360 * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode
NYX 0:85b3fd62ea1a 361 * @retval None
NYX 0:85b3fd62ea1a 362 */
NYX 0:85b3fd62ea1a 363 __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
NYX 0:85b3fd62ea1a 364 {
NYX 0:85b3fd62ea1a 365 SET_BIT(PWR->CR, PWR_CR_ODEN);
NYX 0:85b3fd62ea1a 366 }
NYX 0:85b3fd62ea1a 367
NYX 0:85b3fd62ea1a 368 /**
NYX 0:85b3fd62ea1a 369 * @brief Disable Over drive Mode
NYX 0:85b3fd62ea1a 370 * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode
NYX 0:85b3fd62ea1a 371 * @retval None
NYX 0:85b3fd62ea1a 372 */
NYX 0:85b3fd62ea1a 373 __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
NYX 0:85b3fd62ea1a 374 {
NYX 0:85b3fd62ea1a 375 CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
NYX 0:85b3fd62ea1a 376 }
NYX 0:85b3fd62ea1a 377
NYX 0:85b3fd62ea1a 378 /**
NYX 0:85b3fd62ea1a 379 * @brief Check if Over drive switching is enabled
NYX 0:85b3fd62ea1a 380 * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode
NYX 0:85b3fd62ea1a 381 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 382 */
NYX 0:85b3fd62ea1a 383 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
NYX 0:85b3fd62ea1a 384 {
NYX 0:85b3fd62ea1a 385 return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
NYX 0:85b3fd62ea1a 386 }
NYX 0:85b3fd62ea1a 387 #endif /* PWR_CR_ODEN */
NYX 0:85b3fd62ea1a 388 #if defined(PWR_CR_MRUDS)
NYX 0:85b3fd62ea1a 389 /**
NYX 0:85b3fd62ea1a 390 * @brief Enable Main Regulator in deepsleep under-drive Mode
NYX 0:85b3fd62ea1a 391 * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
NYX 0:85b3fd62ea1a 392 * @retval None
NYX 0:85b3fd62ea1a 393 */
NYX 0:85b3fd62ea1a 394 __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
NYX 0:85b3fd62ea1a 395 {
NYX 0:85b3fd62ea1a 396 SET_BIT(PWR->CR, PWR_CR_MRUDS);
NYX 0:85b3fd62ea1a 397 }
NYX 0:85b3fd62ea1a 398
NYX 0:85b3fd62ea1a 399 /**
NYX 0:85b3fd62ea1a 400 * @brief Disable Main Regulator in deepsleep under-drive Mode
NYX 0:85b3fd62ea1a 401 * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
NYX 0:85b3fd62ea1a 402 * @retval None
NYX 0:85b3fd62ea1a 403 */
NYX 0:85b3fd62ea1a 404 __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
NYX 0:85b3fd62ea1a 405 {
NYX 0:85b3fd62ea1a 406 CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
NYX 0:85b3fd62ea1a 407 }
NYX 0:85b3fd62ea1a 408
NYX 0:85b3fd62ea1a 409 /**
NYX 0:85b3fd62ea1a 410 * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
NYX 0:85b3fd62ea1a 411 * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
NYX 0:85b3fd62ea1a 412 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 413 */
NYX 0:85b3fd62ea1a 414 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
NYX 0:85b3fd62ea1a 415 {
NYX 0:85b3fd62ea1a 416 return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
NYX 0:85b3fd62ea1a 417 }
NYX 0:85b3fd62ea1a 418 #endif /* PWR_CR_MRUDS */
NYX 0:85b3fd62ea1a 419
NYX 0:85b3fd62ea1a 420 #if defined(PWR_CR_LPUDS)
NYX 0:85b3fd62ea1a 421 /**
NYX 0:85b3fd62ea1a 422 * @brief Enable Low Power Regulator in deepsleep under-drive Mode
NYX 0:85b3fd62ea1a 423 * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
NYX 0:85b3fd62ea1a 424 * @retval None
NYX 0:85b3fd62ea1a 425 */
NYX 0:85b3fd62ea1a 426 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
NYX 0:85b3fd62ea1a 427 {
NYX 0:85b3fd62ea1a 428 SET_BIT(PWR->CR, PWR_CR_LPUDS);
NYX 0:85b3fd62ea1a 429 }
NYX 0:85b3fd62ea1a 430
NYX 0:85b3fd62ea1a 431 /**
NYX 0:85b3fd62ea1a 432 * @brief Disable Low Power Regulator in deepsleep under-drive Mode
NYX 0:85b3fd62ea1a 433 * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
NYX 0:85b3fd62ea1a 434 * @retval None
NYX 0:85b3fd62ea1a 435 */
NYX 0:85b3fd62ea1a 436 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
NYX 0:85b3fd62ea1a 437 {
NYX 0:85b3fd62ea1a 438 CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
NYX 0:85b3fd62ea1a 439 }
NYX 0:85b3fd62ea1a 440
NYX 0:85b3fd62ea1a 441 /**
NYX 0:85b3fd62ea1a 442 * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
NYX 0:85b3fd62ea1a 443 * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
NYX 0:85b3fd62ea1a 444 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 445 */
NYX 0:85b3fd62ea1a 446 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
NYX 0:85b3fd62ea1a 447 {
NYX 0:85b3fd62ea1a 448 return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
NYX 0:85b3fd62ea1a 449 }
NYX 0:85b3fd62ea1a 450 #endif /* PWR_CR_LPUDS */
NYX 0:85b3fd62ea1a 451
NYX 0:85b3fd62ea1a 452 #if defined(PWR_CR_MRLVDS)
NYX 0:85b3fd62ea1a 453 /**
NYX 0:85b3fd62ea1a 454 * @brief Enable Main Regulator low voltage Mode
NYX 0:85b3fd62ea1a 455 * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode
NYX 0:85b3fd62ea1a 456 * @retval None
NYX 0:85b3fd62ea1a 457 */
NYX 0:85b3fd62ea1a 458 __STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
NYX 0:85b3fd62ea1a 459 {
NYX 0:85b3fd62ea1a 460 SET_BIT(PWR->CR, PWR_CR_MRLVDS);
NYX 0:85b3fd62ea1a 461 }
NYX 0:85b3fd62ea1a 462
NYX 0:85b3fd62ea1a 463 /**
NYX 0:85b3fd62ea1a 464 * @brief Disable Main Regulator low voltage Mode
NYX 0:85b3fd62ea1a 465 * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode
NYX 0:85b3fd62ea1a 466 * @retval None
NYX 0:85b3fd62ea1a 467 */
NYX 0:85b3fd62ea1a 468 __STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
NYX 0:85b3fd62ea1a 469 {
NYX 0:85b3fd62ea1a 470 CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
NYX 0:85b3fd62ea1a 471 }
NYX 0:85b3fd62ea1a 472
NYX 0:85b3fd62ea1a 473 /**
NYX 0:85b3fd62ea1a 474 * @brief Check if Main Regulator low voltage Mode is enabled
NYX 0:85b3fd62ea1a 475 * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode
NYX 0:85b3fd62ea1a 476 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 477 */
NYX 0:85b3fd62ea1a 478 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
NYX 0:85b3fd62ea1a 479 {
NYX 0:85b3fd62ea1a 480 return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
NYX 0:85b3fd62ea1a 481 }
NYX 0:85b3fd62ea1a 482 #endif /* PWR_CR_MRLVDS */
NYX 0:85b3fd62ea1a 483
NYX 0:85b3fd62ea1a 484 #if defined(PWR_CR_LPLVDS)
NYX 0:85b3fd62ea1a 485 /**
NYX 0:85b3fd62ea1a 486 * @brief Enable Low Power Regulator low voltage Mode
NYX 0:85b3fd62ea1a 487 * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode
NYX 0:85b3fd62ea1a 488 * @retval None
NYX 0:85b3fd62ea1a 489 */
NYX 0:85b3fd62ea1a 490 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
NYX 0:85b3fd62ea1a 491 {
NYX 0:85b3fd62ea1a 492 SET_BIT(PWR->CR, PWR_CR_LPLVDS);
NYX 0:85b3fd62ea1a 493 }
NYX 0:85b3fd62ea1a 494
NYX 0:85b3fd62ea1a 495 /**
NYX 0:85b3fd62ea1a 496 * @brief Disable Low Power Regulator low voltage Mode
NYX 0:85b3fd62ea1a 497 * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode
NYX 0:85b3fd62ea1a 498 * @retval None
NYX 0:85b3fd62ea1a 499 */
NYX 0:85b3fd62ea1a 500 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
NYX 0:85b3fd62ea1a 501 {
NYX 0:85b3fd62ea1a 502 CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
NYX 0:85b3fd62ea1a 503 }
NYX 0:85b3fd62ea1a 504
NYX 0:85b3fd62ea1a 505 /**
NYX 0:85b3fd62ea1a 506 * @brief Check if Low Power Regulator low voltage Mode is enabled
NYX 0:85b3fd62ea1a 507 * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
NYX 0:85b3fd62ea1a 508 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 509 */
NYX 0:85b3fd62ea1a 510 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
NYX 0:85b3fd62ea1a 511 {
NYX 0:85b3fd62ea1a 512 return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
NYX 0:85b3fd62ea1a 513 }
NYX 0:85b3fd62ea1a 514 #endif /* PWR_CR_LPLVDS */
NYX 0:85b3fd62ea1a 515 /**
NYX 0:85b3fd62ea1a 516 * @brief Set the main internal Regulator output voltage
NYX 0:85b3fd62ea1a 517 * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
NYX 0:85b3fd62ea1a 518 * @param VoltageScaling This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 519 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
NYX 0:85b3fd62ea1a 520 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
NYX 0:85b3fd62ea1a 521 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
NYX 0:85b3fd62ea1a 522 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
NYX 0:85b3fd62ea1a 523 * @retval None
NYX 0:85b3fd62ea1a 524 */
NYX 0:85b3fd62ea1a 525 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
NYX 0:85b3fd62ea1a 526 {
NYX 0:85b3fd62ea1a 527 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
NYX 0:85b3fd62ea1a 528 }
NYX 0:85b3fd62ea1a 529
NYX 0:85b3fd62ea1a 530 /**
NYX 0:85b3fd62ea1a 531 * @brief Get the main internal Regulator output voltage
NYX 0:85b3fd62ea1a 532 * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
NYX 0:85b3fd62ea1a 533 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 534 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
NYX 0:85b3fd62ea1a 535 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
NYX 0:85b3fd62ea1a 536 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
NYX 0:85b3fd62ea1a 537 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
NYX 0:85b3fd62ea1a 538 */
NYX 0:85b3fd62ea1a 539 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
NYX 0:85b3fd62ea1a 540 {
NYX 0:85b3fd62ea1a 541 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
NYX 0:85b3fd62ea1a 542 }
NYX 0:85b3fd62ea1a 543 /**
NYX 0:85b3fd62ea1a 544 * @brief Enable the Flash Power Down in Stop Mode
NYX 0:85b3fd62ea1a 545 * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
NYX 0:85b3fd62ea1a 546 * @retval None
NYX 0:85b3fd62ea1a 547 */
NYX 0:85b3fd62ea1a 548 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
NYX 0:85b3fd62ea1a 549 {
NYX 0:85b3fd62ea1a 550 SET_BIT(PWR->CR, PWR_CR_FPDS);
NYX 0:85b3fd62ea1a 551 }
NYX 0:85b3fd62ea1a 552
NYX 0:85b3fd62ea1a 553 /**
NYX 0:85b3fd62ea1a 554 * @brief Disable the Flash Power Down in Stop Mode
NYX 0:85b3fd62ea1a 555 * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
NYX 0:85b3fd62ea1a 556 * @retval None
NYX 0:85b3fd62ea1a 557 */
NYX 0:85b3fd62ea1a 558 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
NYX 0:85b3fd62ea1a 559 {
NYX 0:85b3fd62ea1a 560 CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
NYX 0:85b3fd62ea1a 561 }
NYX 0:85b3fd62ea1a 562
NYX 0:85b3fd62ea1a 563 /**
NYX 0:85b3fd62ea1a 564 * @brief Check if the Flash Power Down in Stop Mode is enabled
NYX 0:85b3fd62ea1a 565 * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
NYX 0:85b3fd62ea1a 566 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 567 */
NYX 0:85b3fd62ea1a 568 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
NYX 0:85b3fd62ea1a 569 {
NYX 0:85b3fd62ea1a 570 return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
NYX 0:85b3fd62ea1a 571 }
NYX 0:85b3fd62ea1a 572
NYX 0:85b3fd62ea1a 573 /**
NYX 0:85b3fd62ea1a 574 * @brief Enable access to the backup domain
NYX 0:85b3fd62ea1a 575 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
NYX 0:85b3fd62ea1a 576 * @retval None
NYX 0:85b3fd62ea1a 577 */
NYX 0:85b3fd62ea1a 578 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
NYX 0:85b3fd62ea1a 579 {
NYX 0:85b3fd62ea1a 580 SET_BIT(PWR->CR, PWR_CR_DBP);
NYX 0:85b3fd62ea1a 581 }
NYX 0:85b3fd62ea1a 582
NYX 0:85b3fd62ea1a 583 /**
NYX 0:85b3fd62ea1a 584 * @brief Disable access to the backup domain
NYX 0:85b3fd62ea1a 585 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
NYX 0:85b3fd62ea1a 586 * @retval None
NYX 0:85b3fd62ea1a 587 */
NYX 0:85b3fd62ea1a 588 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
NYX 0:85b3fd62ea1a 589 {
NYX 0:85b3fd62ea1a 590 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
NYX 0:85b3fd62ea1a 591 }
NYX 0:85b3fd62ea1a 592
NYX 0:85b3fd62ea1a 593 /**
NYX 0:85b3fd62ea1a 594 * @brief Check if the backup domain is enabled
NYX 0:85b3fd62ea1a 595 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
NYX 0:85b3fd62ea1a 596 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 597 */
NYX 0:85b3fd62ea1a 598 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
NYX 0:85b3fd62ea1a 599 {
NYX 0:85b3fd62ea1a 600 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
NYX 0:85b3fd62ea1a 601 }
NYX 0:85b3fd62ea1a 602 /**
NYX 0:85b3fd62ea1a 603 * @brief Enable the backup Regulator
NYX 0:85b3fd62ea1a 604 * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
NYX 0:85b3fd62ea1a 605 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
NYX 0:85b3fd62ea1a 606 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
NYX 0:85b3fd62ea1a 607 * @retval None
NYX 0:85b3fd62ea1a 608 */
NYX 0:85b3fd62ea1a 609 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
NYX 0:85b3fd62ea1a 610 {
NYX 0:85b3fd62ea1a 611 SET_BIT(PWR->CSR, PWR_CSR_BRE);
NYX 0:85b3fd62ea1a 612 }
NYX 0:85b3fd62ea1a 613
NYX 0:85b3fd62ea1a 614 /**
NYX 0:85b3fd62ea1a 615 * @brief Disable the backup Regulator
NYX 0:85b3fd62ea1a 616 * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
NYX 0:85b3fd62ea1a 617 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
NYX 0:85b3fd62ea1a 618 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
NYX 0:85b3fd62ea1a 619 * @retval None
NYX 0:85b3fd62ea1a 620 */
NYX 0:85b3fd62ea1a 621 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
NYX 0:85b3fd62ea1a 622 {
NYX 0:85b3fd62ea1a 623 CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
NYX 0:85b3fd62ea1a 624 }
NYX 0:85b3fd62ea1a 625
NYX 0:85b3fd62ea1a 626 /**
NYX 0:85b3fd62ea1a 627 * @brief Check if the backup Regulator is enabled
NYX 0:85b3fd62ea1a 628 * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
NYX 0:85b3fd62ea1a 629 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 630 */
NYX 0:85b3fd62ea1a 631 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
NYX 0:85b3fd62ea1a 632 {
NYX 0:85b3fd62ea1a 633 return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
NYX 0:85b3fd62ea1a 634 }
NYX 0:85b3fd62ea1a 635
NYX 0:85b3fd62ea1a 636 /**
NYX 0:85b3fd62ea1a 637 * @brief Set voltage Regulator mode during deep sleep mode
NYX 0:85b3fd62ea1a 638 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
NYX 0:85b3fd62ea1a 639 * @param RegulMode This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 640 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
NYX 0:85b3fd62ea1a 641 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
NYX 0:85b3fd62ea1a 642 * @retval None
NYX 0:85b3fd62ea1a 643 */
NYX 0:85b3fd62ea1a 644 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
NYX 0:85b3fd62ea1a 645 {
NYX 0:85b3fd62ea1a 646 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
NYX 0:85b3fd62ea1a 647 }
NYX 0:85b3fd62ea1a 648
NYX 0:85b3fd62ea1a 649 /**
NYX 0:85b3fd62ea1a 650 * @brief Get voltage Regulator mode during deep sleep mode
NYX 0:85b3fd62ea1a 651 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
NYX 0:85b3fd62ea1a 652 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 653 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
NYX 0:85b3fd62ea1a 654 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
NYX 0:85b3fd62ea1a 655 */
NYX 0:85b3fd62ea1a 656 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
NYX 0:85b3fd62ea1a 657 {
NYX 0:85b3fd62ea1a 658 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
NYX 0:85b3fd62ea1a 659 }
NYX 0:85b3fd62ea1a 660
NYX 0:85b3fd62ea1a 661 /**
NYX 0:85b3fd62ea1a 662 * @brief Set Power Down mode when CPU enters deepsleep
NYX 0:85b3fd62ea1a 663 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
NYX 0:85b3fd62ea1a 664 * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n
NYX 0:85b3fd62ea1a 665 * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n
NYX 0:85b3fd62ea1a 666 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
NYX 0:85b3fd62ea1a 667 * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n
NYX 0:85b3fd62ea1a 668 * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n
NYX 0:85b3fd62ea1a 669 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
NYX 0:85b3fd62ea1a 670 * @rmtoll CR LPDS LL_PWR_SetPowerMode
NYX 0:85b3fd62ea1a 671 * @param PDMode This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 672 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
NYX 0:85b3fd62ea1a 673 * @arg @ref LL_PWR_MODE_STOP_LPREGU
NYX 0:85b3fd62ea1a 674 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
NYX 0:85b3fd62ea1a 675 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
NYX 0:85b3fd62ea1a 676 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
NYX 0:85b3fd62ea1a 677 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
NYX 0:85b3fd62ea1a 678 *
NYX 0:85b3fd62ea1a 679 * (*) not available on all devices
NYX 0:85b3fd62ea1a 680 * @arg @ref LL_PWR_MODE_STANDBY
NYX 0:85b3fd62ea1a 681 * @retval None
NYX 0:85b3fd62ea1a 682 */
NYX 0:85b3fd62ea1a 683 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
NYX 0:85b3fd62ea1a 684 {
NYX 0:85b3fd62ea1a 685 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
NYX 0:85b3fd62ea1a 686 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
NYX 0:85b3fd62ea1a 687 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
NYX 0:85b3fd62ea1a 688 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
NYX 0:85b3fd62ea1a 689 #else
NYX 0:85b3fd62ea1a 690 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
NYX 0:85b3fd62ea1a 691 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
NYX 0:85b3fd62ea1a 692 }
NYX 0:85b3fd62ea1a 693
NYX 0:85b3fd62ea1a 694 /**
NYX 0:85b3fd62ea1a 695 * @brief Get Power Down mode when CPU enters deepsleep
NYX 0:85b3fd62ea1a 696 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
NYX 0:85b3fd62ea1a 697 * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n
NYX 0:85b3fd62ea1a 698 * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n
NYX 0:85b3fd62ea1a 699 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
NYX 0:85b3fd62ea1a 700 * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n
NYX 0:85b3fd62ea1a 701 * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n
NYX 0:85b3fd62ea1a 702 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
NYX 0:85b3fd62ea1a 703 * @rmtoll CR LPDS LL_PWR_GetPowerMode
NYX 0:85b3fd62ea1a 704 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 705 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
NYX 0:85b3fd62ea1a 706 * @arg @ref LL_PWR_MODE_STOP_LPREGU
NYX 0:85b3fd62ea1a 707 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
NYX 0:85b3fd62ea1a 708 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
NYX 0:85b3fd62ea1a 709 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
NYX 0:85b3fd62ea1a 710 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
NYX 0:85b3fd62ea1a 711 *
NYX 0:85b3fd62ea1a 712 * (*) not available on all devices
NYX 0:85b3fd62ea1a 713 * @arg @ref LL_PWR_MODE_STANDBY
NYX 0:85b3fd62ea1a 714 */
NYX 0:85b3fd62ea1a 715 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
NYX 0:85b3fd62ea1a 716 {
NYX 0:85b3fd62ea1a 717 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
NYX 0:85b3fd62ea1a 718 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
NYX 0:85b3fd62ea1a 719 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
NYX 0:85b3fd62ea1a 720 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
NYX 0:85b3fd62ea1a 721 #else
NYX 0:85b3fd62ea1a 722 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
NYX 0:85b3fd62ea1a 723 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
NYX 0:85b3fd62ea1a 724 }
NYX 0:85b3fd62ea1a 725
NYX 0:85b3fd62ea1a 726 /**
NYX 0:85b3fd62ea1a 727 * @brief Configure the voltage threshold detected by the Power Voltage Detector
NYX 0:85b3fd62ea1a 728 * @rmtoll CR PLS LL_PWR_SetPVDLevel
NYX 0:85b3fd62ea1a 729 * @param PVDLevel This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 730 * @arg @ref LL_PWR_PVDLEVEL_0
NYX 0:85b3fd62ea1a 731 * @arg @ref LL_PWR_PVDLEVEL_1
NYX 0:85b3fd62ea1a 732 * @arg @ref LL_PWR_PVDLEVEL_2
NYX 0:85b3fd62ea1a 733 * @arg @ref LL_PWR_PVDLEVEL_3
NYX 0:85b3fd62ea1a 734 * @arg @ref LL_PWR_PVDLEVEL_4
NYX 0:85b3fd62ea1a 735 * @arg @ref LL_PWR_PVDLEVEL_5
NYX 0:85b3fd62ea1a 736 * @arg @ref LL_PWR_PVDLEVEL_6
NYX 0:85b3fd62ea1a 737 * @arg @ref LL_PWR_PVDLEVEL_7
NYX 0:85b3fd62ea1a 738 * @retval None
NYX 0:85b3fd62ea1a 739 */
NYX 0:85b3fd62ea1a 740 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
NYX 0:85b3fd62ea1a 741 {
NYX 0:85b3fd62ea1a 742 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
NYX 0:85b3fd62ea1a 743 }
NYX 0:85b3fd62ea1a 744
NYX 0:85b3fd62ea1a 745 /**
NYX 0:85b3fd62ea1a 746 * @brief Get the voltage threshold detection
NYX 0:85b3fd62ea1a 747 * @rmtoll CR PLS LL_PWR_GetPVDLevel
NYX 0:85b3fd62ea1a 748 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 749 * @arg @ref LL_PWR_PVDLEVEL_0
NYX 0:85b3fd62ea1a 750 * @arg @ref LL_PWR_PVDLEVEL_1
NYX 0:85b3fd62ea1a 751 * @arg @ref LL_PWR_PVDLEVEL_2
NYX 0:85b3fd62ea1a 752 * @arg @ref LL_PWR_PVDLEVEL_3
NYX 0:85b3fd62ea1a 753 * @arg @ref LL_PWR_PVDLEVEL_4
NYX 0:85b3fd62ea1a 754 * @arg @ref LL_PWR_PVDLEVEL_5
NYX 0:85b3fd62ea1a 755 * @arg @ref LL_PWR_PVDLEVEL_6
NYX 0:85b3fd62ea1a 756 * @arg @ref LL_PWR_PVDLEVEL_7
NYX 0:85b3fd62ea1a 757 */
NYX 0:85b3fd62ea1a 758 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
NYX 0:85b3fd62ea1a 759 {
NYX 0:85b3fd62ea1a 760 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
NYX 0:85b3fd62ea1a 761 }
NYX 0:85b3fd62ea1a 762
NYX 0:85b3fd62ea1a 763 /**
NYX 0:85b3fd62ea1a 764 * @brief Enable Power Voltage Detector
NYX 0:85b3fd62ea1a 765 * @rmtoll CR PVDE LL_PWR_EnablePVD
NYX 0:85b3fd62ea1a 766 * @retval None
NYX 0:85b3fd62ea1a 767 */
NYX 0:85b3fd62ea1a 768 __STATIC_INLINE void LL_PWR_EnablePVD(void)
NYX 0:85b3fd62ea1a 769 {
NYX 0:85b3fd62ea1a 770 SET_BIT(PWR->CR, PWR_CR_PVDE);
NYX 0:85b3fd62ea1a 771 }
NYX 0:85b3fd62ea1a 772
NYX 0:85b3fd62ea1a 773 /**
NYX 0:85b3fd62ea1a 774 * @brief Disable Power Voltage Detector
NYX 0:85b3fd62ea1a 775 * @rmtoll CR PVDE LL_PWR_DisablePVD
NYX 0:85b3fd62ea1a 776 * @retval None
NYX 0:85b3fd62ea1a 777 */
NYX 0:85b3fd62ea1a 778 __STATIC_INLINE void LL_PWR_DisablePVD(void)
NYX 0:85b3fd62ea1a 779 {
NYX 0:85b3fd62ea1a 780 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
NYX 0:85b3fd62ea1a 781 }
NYX 0:85b3fd62ea1a 782
NYX 0:85b3fd62ea1a 783 /**
NYX 0:85b3fd62ea1a 784 * @brief Check if Power Voltage Detector is enabled
NYX 0:85b3fd62ea1a 785 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
NYX 0:85b3fd62ea1a 786 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 787 */
NYX 0:85b3fd62ea1a 788 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
NYX 0:85b3fd62ea1a 789 {
NYX 0:85b3fd62ea1a 790 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
NYX 0:85b3fd62ea1a 791 }
NYX 0:85b3fd62ea1a 792
NYX 0:85b3fd62ea1a 793 /**
NYX 0:85b3fd62ea1a 794 * @brief Enable the WakeUp PINx functionality
NYX 0:85b3fd62ea1a 795 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n
NYX 0:85b3fd62ea1a 796 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
NYX 0:85b3fd62ea1a 797 * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
NYX 0:85b3fd62ea1a 798 * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
NYX 0:85b3fd62ea1a 799 * @param WakeUpPin This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 800 * @arg @ref LL_PWR_WAKEUP_PIN1
NYX 0:85b3fd62ea1a 801 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
NYX 0:85b3fd62ea1a 802 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
NYX 0:85b3fd62ea1a 803 *
NYX 0:85b3fd62ea1a 804 * (*) not available on all devices
NYX 0:85b3fd62ea1a 805 * @retval None
NYX 0:85b3fd62ea1a 806 */
NYX 0:85b3fd62ea1a 807 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
NYX 0:85b3fd62ea1a 808 {
NYX 0:85b3fd62ea1a 809 SET_BIT(PWR->CSR, WakeUpPin);
NYX 0:85b3fd62ea1a 810 }
NYX 0:85b3fd62ea1a 811
NYX 0:85b3fd62ea1a 812 /**
NYX 0:85b3fd62ea1a 813 * @brief Disable the WakeUp PINx functionality
NYX 0:85b3fd62ea1a 814 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n
NYX 0:85b3fd62ea1a 815 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
NYX 0:85b3fd62ea1a 816 * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
NYX 0:85b3fd62ea1a 817 * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
NYX 0:85b3fd62ea1a 818 * @param WakeUpPin This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 819 * @arg @ref LL_PWR_WAKEUP_PIN1
NYX 0:85b3fd62ea1a 820 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
NYX 0:85b3fd62ea1a 821 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
NYX 0:85b3fd62ea1a 822 *
NYX 0:85b3fd62ea1a 823 * (*) not available on all devices
NYX 0:85b3fd62ea1a 824 * @retval None
NYX 0:85b3fd62ea1a 825 */
NYX 0:85b3fd62ea1a 826 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
NYX 0:85b3fd62ea1a 827 {
NYX 0:85b3fd62ea1a 828 CLEAR_BIT(PWR->CSR, WakeUpPin);
NYX 0:85b3fd62ea1a 829 }
NYX 0:85b3fd62ea1a 830
NYX 0:85b3fd62ea1a 831 /**
NYX 0:85b3fd62ea1a 832 * @brief Check if the WakeUp PINx functionality is enabled
NYX 0:85b3fd62ea1a 833 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n
NYX 0:85b3fd62ea1a 834 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
NYX 0:85b3fd62ea1a 835 * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
NYX 0:85b3fd62ea1a 836 * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
NYX 0:85b3fd62ea1a 837 * @param WakeUpPin This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 838 * @arg @ref LL_PWR_WAKEUP_PIN1
NYX 0:85b3fd62ea1a 839 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
NYX 0:85b3fd62ea1a 840 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
NYX 0:85b3fd62ea1a 841 *
NYX 0:85b3fd62ea1a 842 * (*) not available on all devices
NYX 0:85b3fd62ea1a 843 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 844 */
NYX 0:85b3fd62ea1a 845 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
NYX 0:85b3fd62ea1a 846 {
NYX 0:85b3fd62ea1a 847 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
NYX 0:85b3fd62ea1a 848 }
NYX 0:85b3fd62ea1a 849
NYX 0:85b3fd62ea1a 850
NYX 0:85b3fd62ea1a 851 /**
NYX 0:85b3fd62ea1a 852 * @}
NYX 0:85b3fd62ea1a 853 */
NYX 0:85b3fd62ea1a 854
NYX 0:85b3fd62ea1a 855 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
NYX 0:85b3fd62ea1a 856 * @{
NYX 0:85b3fd62ea1a 857 */
NYX 0:85b3fd62ea1a 858
NYX 0:85b3fd62ea1a 859 /**
NYX 0:85b3fd62ea1a 860 * @brief Get Wake-up Flag
NYX 0:85b3fd62ea1a 861 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
NYX 0:85b3fd62ea1a 862 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 863 */
NYX 0:85b3fd62ea1a 864 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
NYX 0:85b3fd62ea1a 865 {
NYX 0:85b3fd62ea1a 866 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
NYX 0:85b3fd62ea1a 867 }
NYX 0:85b3fd62ea1a 868
NYX 0:85b3fd62ea1a 869 /**
NYX 0:85b3fd62ea1a 870 * @brief Get Standby Flag
NYX 0:85b3fd62ea1a 871 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
NYX 0:85b3fd62ea1a 872 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 873 */
NYX 0:85b3fd62ea1a 874 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
NYX 0:85b3fd62ea1a 875 {
NYX 0:85b3fd62ea1a 876 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
NYX 0:85b3fd62ea1a 877 }
NYX 0:85b3fd62ea1a 878
NYX 0:85b3fd62ea1a 879 /**
NYX 0:85b3fd62ea1a 880 * @brief Get Backup Regulator ready Flag
NYX 0:85b3fd62ea1a 881 * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
NYX 0:85b3fd62ea1a 882 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 883 */
NYX 0:85b3fd62ea1a 884 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
NYX 0:85b3fd62ea1a 885 {
NYX 0:85b3fd62ea1a 886 return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
NYX 0:85b3fd62ea1a 887 }
NYX 0:85b3fd62ea1a 888 /**
NYX 0:85b3fd62ea1a 889 * @brief Indicate whether VDD voltage is below the selected PVD threshold
NYX 0:85b3fd62ea1a 890 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
NYX 0:85b3fd62ea1a 891 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 892 */
NYX 0:85b3fd62ea1a 893 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
NYX 0:85b3fd62ea1a 894 {
NYX 0:85b3fd62ea1a 895 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
NYX 0:85b3fd62ea1a 896 }
NYX 0:85b3fd62ea1a 897
NYX 0:85b3fd62ea1a 898 /**
NYX 0:85b3fd62ea1a 899 * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
NYX 0:85b3fd62ea1a 900 * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS
NYX 0:85b3fd62ea1a 901 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 902 */
NYX 0:85b3fd62ea1a 903 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
NYX 0:85b3fd62ea1a 904 {
NYX 0:85b3fd62ea1a 905 return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
NYX 0:85b3fd62ea1a 906 }
NYX 0:85b3fd62ea1a 907 #if defined(PWR_CR_ODEN)
NYX 0:85b3fd62ea1a 908 /**
NYX 0:85b3fd62ea1a 909 * @brief Indicate whether the Over-Drive mode is ready or not
NYX 0:85b3fd62ea1a 910 * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD
NYX 0:85b3fd62ea1a 911 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 912 */
NYX 0:85b3fd62ea1a 913 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
NYX 0:85b3fd62ea1a 914 {
NYX 0:85b3fd62ea1a 915 return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
NYX 0:85b3fd62ea1a 916 }
NYX 0:85b3fd62ea1a 917 #endif /* PWR_CR_ODEN */
NYX 0:85b3fd62ea1a 918
NYX 0:85b3fd62ea1a 919 #if defined(PWR_CR_ODSWEN)
NYX 0:85b3fd62ea1a 920 /**
NYX 0:85b3fd62ea1a 921 * @brief Indicate whether the Over-Drive mode switching is ready or not
NYX 0:85b3fd62ea1a 922 * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW
NYX 0:85b3fd62ea1a 923 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 924 */
NYX 0:85b3fd62ea1a 925 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
NYX 0:85b3fd62ea1a 926 {
NYX 0:85b3fd62ea1a 927 return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
NYX 0:85b3fd62ea1a 928 }
NYX 0:85b3fd62ea1a 929 #endif /* PWR_CR_ODSWEN */
NYX 0:85b3fd62ea1a 930
NYX 0:85b3fd62ea1a 931 #if defined(PWR_CR_UDEN)
NYX 0:85b3fd62ea1a 932 /**
NYX 0:85b3fd62ea1a 933 * @brief Indicate whether the Under-Drive mode is ready or not
NYX 0:85b3fd62ea1a 934 * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD
NYX 0:85b3fd62ea1a 935 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 936 */
NYX 0:85b3fd62ea1a 937 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
NYX 0:85b3fd62ea1a 938 {
NYX 0:85b3fd62ea1a 939 return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
NYX 0:85b3fd62ea1a 940 }
NYX 0:85b3fd62ea1a 941 #endif /* PWR_CR_UDEN */
NYX 0:85b3fd62ea1a 942 /**
NYX 0:85b3fd62ea1a 943 * @brief Clear Standby Flag
NYX 0:85b3fd62ea1a 944 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
NYX 0:85b3fd62ea1a 945 * @retval None
NYX 0:85b3fd62ea1a 946 */
NYX 0:85b3fd62ea1a 947 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
NYX 0:85b3fd62ea1a 948 {
NYX 0:85b3fd62ea1a 949 SET_BIT(PWR->CR, PWR_CR_CSBF);
NYX 0:85b3fd62ea1a 950 }
NYX 0:85b3fd62ea1a 951
NYX 0:85b3fd62ea1a 952 /**
NYX 0:85b3fd62ea1a 953 * @brief Clear Wake-up Flags
NYX 0:85b3fd62ea1a 954 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
NYX 0:85b3fd62ea1a 955 * @retval None
NYX 0:85b3fd62ea1a 956 */
NYX 0:85b3fd62ea1a 957 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
NYX 0:85b3fd62ea1a 958 {
NYX 0:85b3fd62ea1a 959 SET_BIT(PWR->CR, PWR_CR_CWUF);
NYX 0:85b3fd62ea1a 960 }
NYX 0:85b3fd62ea1a 961 #if defined(PWR_CSR_UDRDY)
NYX 0:85b3fd62ea1a 962 /**
NYX 0:85b3fd62ea1a 963 * @brief Clear Under-Drive ready Flag
NYX 0:85b3fd62ea1a 964 * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD
NYX 0:85b3fd62ea1a 965 * @retval None
NYX 0:85b3fd62ea1a 966 */
NYX 0:85b3fd62ea1a 967 __STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
NYX 0:85b3fd62ea1a 968 {
NYX 0:85b3fd62ea1a 969 WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
NYX 0:85b3fd62ea1a 970 }
NYX 0:85b3fd62ea1a 971 #endif /* PWR_CSR_UDRDY */
NYX 0:85b3fd62ea1a 972
NYX 0:85b3fd62ea1a 973 /**
NYX 0:85b3fd62ea1a 974 * @}
NYX 0:85b3fd62ea1a 975 */
NYX 0:85b3fd62ea1a 976
NYX 0:85b3fd62ea1a 977 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 978 /** @defgroup PWR_LL_EF_Init De-initialization function
NYX 0:85b3fd62ea1a 979 * @{
NYX 0:85b3fd62ea1a 980 */
NYX 0:85b3fd62ea1a 981 ErrorStatus LL_PWR_DeInit(void);
NYX 0:85b3fd62ea1a 982 /**
NYX 0:85b3fd62ea1a 983 * @}
NYX 0:85b3fd62ea1a 984 */
NYX 0:85b3fd62ea1a 985 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 986
NYX 0:85b3fd62ea1a 987 /**
NYX 0:85b3fd62ea1a 988 * @}
NYX 0:85b3fd62ea1a 989 */
NYX 0:85b3fd62ea1a 990
NYX 0:85b3fd62ea1a 991 /**
NYX 0:85b3fd62ea1a 992 * @}
NYX 0:85b3fd62ea1a 993 */
NYX 0:85b3fd62ea1a 994
NYX 0:85b3fd62ea1a 995 #endif /* defined(PWR) */
NYX 0:85b3fd62ea1a 996
NYX 0:85b3fd62ea1a 997 /**
NYX 0:85b3fd62ea1a 998 * @}
NYX 0:85b3fd62ea1a 999 */
NYX 0:85b3fd62ea1a 1000
NYX 0:85b3fd62ea1a 1001 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 1002 }
NYX 0:85b3fd62ea1a 1003 #endif
NYX 0:85b3fd62ea1a 1004
NYX 0:85b3fd62ea1a 1005 #endif /* __STM32F4xx_LL_PWR_H */
NYX 0:85b3fd62ea1a 1006
NYX 0:85b3fd62ea1a 1007 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/