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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_i2c.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of I2C LL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_LL_I2C_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_LL_I2C_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #include "stm32f4xx.h"
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /** @addtogroup STM32F4xx_LL_Driver
NYX 0:85b3fd62ea1a 50 * @{
NYX 0:85b3fd62ea1a 51 */
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 /** @defgroup I2C_LL I2C
NYX 0:85b3fd62ea1a 56 * @{
NYX 0:85b3fd62ea1a 57 */
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 61
NYX 0:85b3fd62ea1a 62 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 63 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
NYX 0:85b3fd62ea1a 64 * @{
NYX 0:85b3fd62ea1a 65 */
NYX 0:85b3fd62ea1a 66
NYX 0:85b3fd62ea1a 67 /* Defines used to perform compute and check in the macros */
NYX 0:85b3fd62ea1a 68 #define LL_I2C_MAX_SPEED_STANDARD 100000U
NYX 0:85b3fd62ea1a 69 #define LL_I2C_MAX_SPEED_FAST 400000U
NYX 0:85b3fd62ea1a 70 /**
NYX 0:85b3fd62ea1a 71 * @}
NYX 0:85b3fd62ea1a 72 */
NYX 0:85b3fd62ea1a 73
NYX 0:85b3fd62ea1a 74 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 75 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 76 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
NYX 0:85b3fd62ea1a 77 * @{
NYX 0:85b3fd62ea1a 78 */
NYX 0:85b3fd62ea1a 79 /**
NYX 0:85b3fd62ea1a 80 * @}
NYX 0:85b3fd62ea1a 81 */
NYX 0:85b3fd62ea1a 82 #endif /*USE_FULL_LL_DRIVER*/
NYX 0:85b3fd62ea1a 83
NYX 0:85b3fd62ea1a 84 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 85 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 86 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
NYX 0:85b3fd62ea1a 87 * @{
NYX 0:85b3fd62ea1a 88 */
NYX 0:85b3fd62ea1a 89 typedef struct
NYX 0:85b3fd62ea1a 90 {
NYX 0:85b3fd62ea1a 91 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
NYX 0:85b3fd62ea1a 92 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
NYX 0:85b3fd62ea1a 93
NYX 0:85b3fd62ea1a 94 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
NYX 0:85b3fd62ea1a 97 This parameter must be set to a value lower than 400kHz (in Hz)
NYX 0:85b3fd62ea1a 98
NYX 0:85b3fd62ea1a 99 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
NYX 0:85b3fd62ea1a 100 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
NYX 0:85b3fd62ea1a 101
NYX 0:85b3fd62ea1a 102 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
NYX 0:85b3fd62ea1a 103 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
NYX 0:85b3fd62ea1a 104
NYX 0:85b3fd62ea1a 105 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
NYX 0:85b3fd62ea1a 108 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
NYX 0:85b3fd62ea1a 109 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
NYX 0:85b3fd62ea1a 114 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
NYX 0:85b3fd62ea1a 115
NYX 0:85b3fd62ea1a 116 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 #endif
NYX 0:85b3fd62ea1a 119 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
NYX 0:85b3fd62ea1a 120 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
NYX 0:85b3fd62ea1a 121
NYX 0:85b3fd62ea1a 122 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
NYX 0:85b3fd62ea1a 123
NYX 0:85b3fd62ea1a 124 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
NYX 0:85b3fd62ea1a 125 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
NYX 0:85b3fd62ea1a 128
NYX 0:85b3fd62ea1a 129 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
NYX 0:85b3fd62ea1a 130 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
NYX 0:85b3fd62ea1a 131
NYX 0:85b3fd62ea1a 132 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
NYX 0:85b3fd62ea1a 133 } LL_I2C_InitTypeDef;
NYX 0:85b3fd62ea1a 134 /**
NYX 0:85b3fd62ea1a 135 * @}
NYX 0:85b3fd62ea1a 136 */
NYX 0:85b3fd62ea1a 137 #endif /*USE_FULL_LL_DRIVER*/
NYX 0:85b3fd62ea1a 138
NYX 0:85b3fd62ea1a 139 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 140 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
NYX 0:85b3fd62ea1a 141 * @{
NYX 0:85b3fd62ea1a 142 */
NYX 0:85b3fd62ea1a 143
NYX 0:85b3fd62ea1a 144 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
NYX 0:85b3fd62ea1a 145 * @brief Flags defines which can be used with LL_I2C_ReadReg function
NYX 0:85b3fd62ea1a 146 * @{
NYX 0:85b3fd62ea1a 147 */
NYX 0:85b3fd62ea1a 148 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
NYX 0:85b3fd62ea1a 149 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
NYX 0:85b3fd62ea1a 150 Address matched flag (slave mode) */
NYX 0:85b3fd62ea1a 151 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
NYX 0:85b3fd62ea1a 152 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
NYX 0:85b3fd62ea1a 153 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
NYX 0:85b3fd62ea1a 154 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
NYX 0:85b3fd62ea1a 155 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
NYX 0:85b3fd62ea1a 156 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
NYX 0:85b3fd62ea1a 157 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
NYX 0:85b3fd62ea1a 158 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
NYX 0:85b3fd62ea1a 159 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
NYX 0:85b3fd62ea1a 160 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
NYX 0:85b3fd62ea1a 161 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
NYX 0:85b3fd62ea1a 162 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
NYX 0:85b3fd62ea1a 163 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
NYX 0:85b3fd62ea1a 164 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
NYX 0:85b3fd62ea1a 165 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
NYX 0:85b3fd62ea1a 166 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
NYX 0:85b3fd62ea1a 167 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
NYX 0:85b3fd62ea1a 168 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
NYX 0:85b3fd62ea1a 169 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
NYX 0:85b3fd62ea1a 170 /**
NYX 0:85b3fd62ea1a 171 * @}
NYX 0:85b3fd62ea1a 172 */
NYX 0:85b3fd62ea1a 173
NYX 0:85b3fd62ea1a 174 /** @defgroup I2C_LL_EC_IT IT Defines
NYX 0:85b3fd62ea1a 175 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
NYX 0:85b3fd62ea1a 176 * @{
NYX 0:85b3fd62ea1a 177 */
NYX 0:85b3fd62ea1a 178 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
NYX 0:85b3fd62ea1a 179 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
NYX 0:85b3fd62ea1a 180 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
NYX 0:85b3fd62ea1a 181 /**
NYX 0:85b3fd62ea1a 182 * @}
NYX 0:85b3fd62ea1a 183 */
NYX 0:85b3fd62ea1a 184
NYX 0:85b3fd62ea1a 185 #if defined(I2C_FLTR_ANOFF)
NYX 0:85b3fd62ea1a 186 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
NYX 0:85b3fd62ea1a 187 * @{
NYX 0:85b3fd62ea1a 188 */
NYX 0:85b3fd62ea1a 189 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
NYX 0:85b3fd62ea1a 190 #define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/
NYX 0:85b3fd62ea1a 191 /**
NYX 0:85b3fd62ea1a 192 * @}
NYX 0:85b3fd62ea1a 193 */
NYX 0:85b3fd62ea1a 194
NYX 0:85b3fd62ea1a 195 #endif
NYX 0:85b3fd62ea1a 196 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
NYX 0:85b3fd62ea1a 197 * @{
NYX 0:85b3fd62ea1a 198 */
NYX 0:85b3fd62ea1a 199 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
NYX 0:85b3fd62ea1a 200 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
NYX 0:85b3fd62ea1a 201 /**
NYX 0:85b3fd62ea1a 202 * @}
NYX 0:85b3fd62ea1a 203 */
NYX 0:85b3fd62ea1a 204
NYX 0:85b3fd62ea1a 205 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
NYX 0:85b3fd62ea1a 206 * @{
NYX 0:85b3fd62ea1a 207 */
NYX 0:85b3fd62ea1a 208 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
NYX 0:85b3fd62ea1a 209 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
NYX 0:85b3fd62ea1a 210 /**
NYX 0:85b3fd62ea1a 211 * @}
NYX 0:85b3fd62ea1a 212 */
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
NYX 0:85b3fd62ea1a 215 * @{
NYX 0:85b3fd62ea1a 216 */
NYX 0:85b3fd62ea1a 217 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
NYX 0:85b3fd62ea1a 218 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
NYX 0:85b3fd62ea1a 219 /**
NYX 0:85b3fd62ea1a 220 * @}
NYX 0:85b3fd62ea1a 221 */
NYX 0:85b3fd62ea1a 222
NYX 0:85b3fd62ea1a 223 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
NYX 0:85b3fd62ea1a 224 * @{
NYX 0:85b3fd62ea1a 225 */
NYX 0:85b3fd62ea1a 226 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
NYX 0:85b3fd62ea1a 227 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
NYX 0:85b3fd62ea1a 228 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
NYX 0:85b3fd62ea1a 229 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
NYX 0:85b3fd62ea1a 230 /**
NYX 0:85b3fd62ea1a 231 * @}
NYX 0:85b3fd62ea1a 232 */
NYX 0:85b3fd62ea1a 233
NYX 0:85b3fd62ea1a 234 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
NYX 0:85b3fd62ea1a 235 * @{
NYX 0:85b3fd62ea1a 236 */
NYX 0:85b3fd62ea1a 237 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
NYX 0:85b3fd62ea1a 238 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
NYX 0:85b3fd62ea1a 239 /**
NYX 0:85b3fd62ea1a 240 * @}
NYX 0:85b3fd62ea1a 241 */
NYX 0:85b3fd62ea1a 242
NYX 0:85b3fd62ea1a 243 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
NYX 0:85b3fd62ea1a 244 * @{
NYX 0:85b3fd62ea1a 245 */
NYX 0:85b3fd62ea1a 246 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
NYX 0:85b3fd62ea1a 247 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
NYX 0:85b3fd62ea1a 248 /**
NYX 0:85b3fd62ea1a 249 * @}
NYX 0:85b3fd62ea1a 250 */
NYX 0:85b3fd62ea1a 251
NYX 0:85b3fd62ea1a 252 /**
NYX 0:85b3fd62ea1a 253 * @}
NYX 0:85b3fd62ea1a 254 */
NYX 0:85b3fd62ea1a 255
NYX 0:85b3fd62ea1a 256 /* Exported macro ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 257 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
NYX 0:85b3fd62ea1a 258 * @{
NYX 0:85b3fd62ea1a 259 */
NYX 0:85b3fd62ea1a 260
NYX 0:85b3fd62ea1a 261 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
NYX 0:85b3fd62ea1a 262 * @{
NYX 0:85b3fd62ea1a 263 */
NYX 0:85b3fd62ea1a 264
NYX 0:85b3fd62ea1a 265 /**
NYX 0:85b3fd62ea1a 266 * @brief Write a value in I2C register
NYX 0:85b3fd62ea1a 267 * @param __INSTANCE__ I2C Instance
NYX 0:85b3fd62ea1a 268 * @param __REG__ Register to be written
NYX 0:85b3fd62ea1a 269 * @param __VALUE__ Value to be written in the register
NYX 0:85b3fd62ea1a 270 * @retval None
NYX 0:85b3fd62ea1a 271 */
NYX 0:85b3fd62ea1a 272 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
NYX 0:85b3fd62ea1a 273
NYX 0:85b3fd62ea1a 274 /**
NYX 0:85b3fd62ea1a 275 * @brief Read a value in I2C register
NYX 0:85b3fd62ea1a 276 * @param __INSTANCE__ I2C Instance
NYX 0:85b3fd62ea1a 277 * @param __REG__ Register to be read
NYX 0:85b3fd62ea1a 278 * @retval Register value
NYX 0:85b3fd62ea1a 279 */
NYX 0:85b3fd62ea1a 280 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
NYX 0:85b3fd62ea1a 281 /**
NYX 0:85b3fd62ea1a 282 * @}
NYX 0:85b3fd62ea1a 283 */
NYX 0:85b3fd62ea1a 284
NYX 0:85b3fd62ea1a 285 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
NYX 0:85b3fd62ea1a 286 * @{
NYX 0:85b3fd62ea1a 287 */
NYX 0:85b3fd62ea1a 288
NYX 0:85b3fd62ea1a 289 /**
NYX 0:85b3fd62ea1a 290 * @brief Convert Peripheral Clock Frequency in Mhz.
NYX 0:85b3fd62ea1a 291 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
NYX 0:85b3fd62ea1a 292 * @retval Value of peripheral clock (in Mhz)
NYX 0:85b3fd62ea1a 293 */
NYX 0:85b3fd62ea1a 294 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
NYX 0:85b3fd62ea1a 295
NYX 0:85b3fd62ea1a 296 /**
NYX 0:85b3fd62ea1a 297 * @brief Convert Peripheral Clock Frequency in Hz.
NYX 0:85b3fd62ea1a 298 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
NYX 0:85b3fd62ea1a 299 * @retval Value of peripheral clock (in Hz)
NYX 0:85b3fd62ea1a 300 */
NYX 0:85b3fd62ea1a 301 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
NYX 0:85b3fd62ea1a 302
NYX 0:85b3fd62ea1a 303 /**
NYX 0:85b3fd62ea1a 304 * @brief Compute I2C Clock rising time.
NYX 0:85b3fd62ea1a 305 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
NYX 0:85b3fd62ea1a 306 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
NYX 0:85b3fd62ea1a 307 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
NYX 0:85b3fd62ea1a 308 */
NYX 0:85b3fd62ea1a 309 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
NYX 0:85b3fd62ea1a 310
NYX 0:85b3fd62ea1a 311 /**
NYX 0:85b3fd62ea1a 312 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
NYX 0:85b3fd62ea1a 313 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
NYX 0:85b3fd62ea1a 314 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
NYX 0:85b3fd62ea1a 315 * @param __DUTYCYCLE__ This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 316 * @arg @ref LL_I2C_DUTYCYCLE_2
NYX 0:85b3fd62ea1a 317 * @arg @ref LL_I2C_DUTYCYCLE_16_9
NYX 0:85b3fd62ea1a 318 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
NYX 0:85b3fd62ea1a 319 */
NYX 0:85b3fd62ea1a 320 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
NYX 0:85b3fd62ea1a 321 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
NYX 0:85b3fd62ea1a 322 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
NYX 0:85b3fd62ea1a 323
NYX 0:85b3fd62ea1a 324 /**
NYX 0:85b3fd62ea1a 325 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
NYX 0:85b3fd62ea1a 326 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
NYX 0:85b3fd62ea1a 327 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
NYX 0:85b3fd62ea1a 328 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
NYX 0:85b3fd62ea1a 329 */
NYX 0:85b3fd62ea1a 330 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
NYX 0:85b3fd62ea1a 331
NYX 0:85b3fd62ea1a 332 /**
NYX 0:85b3fd62ea1a 333 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
NYX 0:85b3fd62ea1a 334 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
NYX 0:85b3fd62ea1a 335 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
NYX 0:85b3fd62ea1a 336 * @param __DUTYCYCLE__ This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 337 * @arg @ref LL_I2C_DUTYCYCLE_2
NYX 0:85b3fd62ea1a 338 * @arg @ref LL_I2C_DUTYCYCLE_16_9
NYX 0:85b3fd62ea1a 339 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
NYX 0:85b3fd62ea1a 340 */
NYX 0:85b3fd62ea1a 341 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
NYX 0:85b3fd62ea1a 342 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
NYX 0:85b3fd62ea1a 343 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
NYX 0:85b3fd62ea1a 344
NYX 0:85b3fd62ea1a 345 /**
NYX 0:85b3fd62ea1a 346 * @brief Get the Least significant bits of a 10-Bits address.
NYX 0:85b3fd62ea1a 347 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
NYX 0:85b3fd62ea1a 348 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
NYX 0:85b3fd62ea1a 349 */
NYX 0:85b3fd62ea1a 350 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
NYX 0:85b3fd62ea1a 351
NYX 0:85b3fd62ea1a 352 /**
NYX 0:85b3fd62ea1a 353 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
NYX 0:85b3fd62ea1a 354 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
NYX 0:85b3fd62ea1a 355 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
NYX 0:85b3fd62ea1a 356 */
NYX 0:85b3fd62ea1a 357 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
NYX 0:85b3fd62ea1a 358
NYX 0:85b3fd62ea1a 359 /**
NYX 0:85b3fd62ea1a 360 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
NYX 0:85b3fd62ea1a 361 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
NYX 0:85b3fd62ea1a 362 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
NYX 0:85b3fd62ea1a 363 */
NYX 0:85b3fd62ea1a 364 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
NYX 0:85b3fd62ea1a 365
NYX 0:85b3fd62ea1a 366 /**
NYX 0:85b3fd62ea1a 367 * @}
NYX 0:85b3fd62ea1a 368 */
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 /**
NYX 0:85b3fd62ea1a 371 * @}
NYX 0:85b3fd62ea1a 372 */
NYX 0:85b3fd62ea1a 373
NYX 0:85b3fd62ea1a 374 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 375
NYX 0:85b3fd62ea1a 376 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
NYX 0:85b3fd62ea1a 377 * @{
NYX 0:85b3fd62ea1a 378 */
NYX 0:85b3fd62ea1a 379
NYX 0:85b3fd62ea1a 380 /** @defgroup I2C_LL_EF_Configuration Configuration
NYX 0:85b3fd62ea1a 381 * @{
NYX 0:85b3fd62ea1a 382 */
NYX 0:85b3fd62ea1a 383
NYX 0:85b3fd62ea1a 384 /**
NYX 0:85b3fd62ea1a 385 * @brief Enable I2C peripheral (PE = 1).
NYX 0:85b3fd62ea1a 386 * @rmtoll CR1 PE LL_I2C_Enable
NYX 0:85b3fd62ea1a 387 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 388 * @retval None
NYX 0:85b3fd62ea1a 389 */
NYX 0:85b3fd62ea1a 390 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 391 {
NYX 0:85b3fd62ea1a 392 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
NYX 0:85b3fd62ea1a 393 }
NYX 0:85b3fd62ea1a 394
NYX 0:85b3fd62ea1a 395 /**
NYX 0:85b3fd62ea1a 396 * @brief Disable I2C peripheral (PE = 0).
NYX 0:85b3fd62ea1a 397 * @rmtoll CR1 PE LL_I2C_Disable
NYX 0:85b3fd62ea1a 398 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 399 * @retval None
NYX 0:85b3fd62ea1a 400 */
NYX 0:85b3fd62ea1a 401 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 402 {
NYX 0:85b3fd62ea1a 403 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
NYX 0:85b3fd62ea1a 404 }
NYX 0:85b3fd62ea1a 405
NYX 0:85b3fd62ea1a 406 /**
NYX 0:85b3fd62ea1a 407 * @brief Check if the I2C peripheral is enabled or disabled.
NYX 0:85b3fd62ea1a 408 * @rmtoll CR1 PE LL_I2C_IsEnabled
NYX 0:85b3fd62ea1a 409 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 410 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 411 */
NYX 0:85b3fd62ea1a 412 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 413 {
NYX 0:85b3fd62ea1a 414 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
NYX 0:85b3fd62ea1a 415 }
NYX 0:85b3fd62ea1a 416
NYX 0:85b3fd62ea1a 417 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
NYX 0:85b3fd62ea1a 418 /**
NYX 0:85b3fd62ea1a 419 * @brief Configure Noise Filters (Analog and Digital).
NYX 0:85b3fd62ea1a 420 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
NYX 0:85b3fd62ea1a 421 * The filters can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 422 * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n
NYX 0:85b3fd62ea1a 423 * FLTR DNF LL_I2C_ConfigFilters
NYX 0:85b3fd62ea1a 424 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 425 * @param AnalogFilter This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 426 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
NYX 0:85b3fd62ea1a 427 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
NYX 0:85b3fd62ea1a 428 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
NYX 0:85b3fd62ea1a 429 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
NYX 0:85b3fd62ea1a 430 * @retval None
NYX 0:85b3fd62ea1a 431 */
NYX 0:85b3fd62ea1a 432 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
NYX 0:85b3fd62ea1a 433 {
NYX 0:85b3fd62ea1a 434 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter);
NYX 0:85b3fd62ea1a 435 }
NYX 0:85b3fd62ea1a 436 #endif
NYX 0:85b3fd62ea1a 437 #if defined(I2C_FLTR_DNF)
NYX 0:85b3fd62ea1a 438
NYX 0:85b3fd62ea1a 439 /**
NYX 0:85b3fd62ea1a 440 * @brief Configure Digital Noise Filter.
NYX 0:85b3fd62ea1a 441 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
NYX 0:85b3fd62ea1a 442 * This filter can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 443 * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter
NYX 0:85b3fd62ea1a 444 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 445 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1)
NYX 0:85b3fd62ea1a 446 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1.
NYX 0:85b3fd62ea1a 447 * @retval None
NYX 0:85b3fd62ea1a 448 */
NYX 0:85b3fd62ea1a 449 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
NYX 0:85b3fd62ea1a 450 {
NYX 0:85b3fd62ea1a 451 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
NYX 0:85b3fd62ea1a 452 }
NYX 0:85b3fd62ea1a 453
NYX 0:85b3fd62ea1a 454 /**
NYX 0:85b3fd62ea1a 455 * @brief Get the current Digital Noise Filter configuration.
NYX 0:85b3fd62ea1a 456 * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter
NYX 0:85b3fd62ea1a 457 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 458 * @retval Value between Min_Data=0x0 and Max_Data=0xF
NYX 0:85b3fd62ea1a 459 */
NYX 0:85b3fd62ea1a 460 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 461 {
NYX 0:85b3fd62ea1a 462 return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
NYX 0:85b3fd62ea1a 463 }
NYX 0:85b3fd62ea1a 464 #endif
NYX 0:85b3fd62ea1a 465 #if defined(I2C_FLTR_ANOFF)
NYX 0:85b3fd62ea1a 466
NYX 0:85b3fd62ea1a 467 /**
NYX 0:85b3fd62ea1a 468 * @brief Enable Analog Noise Filter.
NYX 0:85b3fd62ea1a 469 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 470 * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter
NYX 0:85b3fd62ea1a 471 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 472 * @retval None
NYX 0:85b3fd62ea1a 473 */
NYX 0:85b3fd62ea1a 474 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 475 {
NYX 0:85b3fd62ea1a 476 CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
NYX 0:85b3fd62ea1a 477 }
NYX 0:85b3fd62ea1a 478
NYX 0:85b3fd62ea1a 479 /**
NYX 0:85b3fd62ea1a 480 * @brief Disable Analog Noise Filter.
NYX 0:85b3fd62ea1a 481 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 482 * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter
NYX 0:85b3fd62ea1a 483 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 484 * @retval None
NYX 0:85b3fd62ea1a 485 */
NYX 0:85b3fd62ea1a 486 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 487 {
NYX 0:85b3fd62ea1a 488 SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
NYX 0:85b3fd62ea1a 489 }
NYX 0:85b3fd62ea1a 490
NYX 0:85b3fd62ea1a 491 /**
NYX 0:85b3fd62ea1a 492 * @brief Check if Analog Noise Filter is enabled or disabled.
NYX 0:85b3fd62ea1a 493 * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter
NYX 0:85b3fd62ea1a 494 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 495 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 496 */
NYX 0:85b3fd62ea1a 497 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 498 {
NYX 0:85b3fd62ea1a 499 return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
NYX 0:85b3fd62ea1a 500 }
NYX 0:85b3fd62ea1a 501 #endif
NYX 0:85b3fd62ea1a 502
NYX 0:85b3fd62ea1a 503 /**
NYX 0:85b3fd62ea1a 504 * @brief Enable DMA transmission requests.
NYX 0:85b3fd62ea1a 505 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
NYX 0:85b3fd62ea1a 506 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 507 * @retval None
NYX 0:85b3fd62ea1a 508 */
NYX 0:85b3fd62ea1a 509 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 510 {
NYX 0:85b3fd62ea1a 511 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
NYX 0:85b3fd62ea1a 512 }
NYX 0:85b3fd62ea1a 513
NYX 0:85b3fd62ea1a 514 /**
NYX 0:85b3fd62ea1a 515 * @brief Disable DMA transmission requests.
NYX 0:85b3fd62ea1a 516 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
NYX 0:85b3fd62ea1a 517 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 518 * @retval None
NYX 0:85b3fd62ea1a 519 */
NYX 0:85b3fd62ea1a 520 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 521 {
NYX 0:85b3fd62ea1a 522 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
NYX 0:85b3fd62ea1a 523 }
NYX 0:85b3fd62ea1a 524
NYX 0:85b3fd62ea1a 525 /**
NYX 0:85b3fd62ea1a 526 * @brief Check if DMA transmission requests are enabled or disabled.
NYX 0:85b3fd62ea1a 527 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
NYX 0:85b3fd62ea1a 528 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 529 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 530 */
NYX 0:85b3fd62ea1a 531 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 532 {
NYX 0:85b3fd62ea1a 533 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
NYX 0:85b3fd62ea1a 534 }
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 /**
NYX 0:85b3fd62ea1a 537 * @brief Enable DMA reception requests.
NYX 0:85b3fd62ea1a 538 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
NYX 0:85b3fd62ea1a 539 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 540 * @retval None
NYX 0:85b3fd62ea1a 541 */
NYX 0:85b3fd62ea1a 542 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 543 {
NYX 0:85b3fd62ea1a 544 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
NYX 0:85b3fd62ea1a 545 }
NYX 0:85b3fd62ea1a 546
NYX 0:85b3fd62ea1a 547 /**
NYX 0:85b3fd62ea1a 548 * @brief Disable DMA reception requests.
NYX 0:85b3fd62ea1a 549 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
NYX 0:85b3fd62ea1a 550 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 551 * @retval None
NYX 0:85b3fd62ea1a 552 */
NYX 0:85b3fd62ea1a 553 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 554 {
NYX 0:85b3fd62ea1a 555 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
NYX 0:85b3fd62ea1a 556 }
NYX 0:85b3fd62ea1a 557
NYX 0:85b3fd62ea1a 558 /**
NYX 0:85b3fd62ea1a 559 * @brief Check if DMA reception requests are enabled or disabled.
NYX 0:85b3fd62ea1a 560 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
NYX 0:85b3fd62ea1a 561 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 562 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 563 */
NYX 0:85b3fd62ea1a 564 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 565 {
NYX 0:85b3fd62ea1a 566 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
NYX 0:85b3fd62ea1a 567 }
NYX 0:85b3fd62ea1a 568
NYX 0:85b3fd62ea1a 569 /**
NYX 0:85b3fd62ea1a 570 * @brief Get the data register address used for DMA transfer.
NYX 0:85b3fd62ea1a 571 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
NYX 0:85b3fd62ea1a 572 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 573 * @retval Address of data register
NYX 0:85b3fd62ea1a 574 */
NYX 0:85b3fd62ea1a 575 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 576 {
NYX 0:85b3fd62ea1a 577 return (uint32_t) & (I2Cx->DR);
NYX 0:85b3fd62ea1a 578 }
NYX 0:85b3fd62ea1a 579
NYX 0:85b3fd62ea1a 580 /**
NYX 0:85b3fd62ea1a 581 * @brief Enable Clock stretching.
NYX 0:85b3fd62ea1a 582 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 583 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
NYX 0:85b3fd62ea1a 584 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 585 * @retval None
NYX 0:85b3fd62ea1a 586 */
NYX 0:85b3fd62ea1a 587 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 588 {
NYX 0:85b3fd62ea1a 589 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
NYX 0:85b3fd62ea1a 590 }
NYX 0:85b3fd62ea1a 591
NYX 0:85b3fd62ea1a 592 /**
NYX 0:85b3fd62ea1a 593 * @brief Disable Clock stretching.
NYX 0:85b3fd62ea1a 594 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 595 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
NYX 0:85b3fd62ea1a 596 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 597 * @retval None
NYX 0:85b3fd62ea1a 598 */
NYX 0:85b3fd62ea1a 599 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 600 {
NYX 0:85b3fd62ea1a 601 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
NYX 0:85b3fd62ea1a 602 }
NYX 0:85b3fd62ea1a 603
NYX 0:85b3fd62ea1a 604 /**
NYX 0:85b3fd62ea1a 605 * @brief Check if Clock stretching is enabled or disabled.
NYX 0:85b3fd62ea1a 606 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
NYX 0:85b3fd62ea1a 607 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 608 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 609 */
NYX 0:85b3fd62ea1a 610 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 611 {
NYX 0:85b3fd62ea1a 612 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
NYX 0:85b3fd62ea1a 613 }
NYX 0:85b3fd62ea1a 614
NYX 0:85b3fd62ea1a 615 /**
NYX 0:85b3fd62ea1a 616 * @brief Enable General Call.
NYX 0:85b3fd62ea1a 617 * @note When enabled the Address 0x00 is ACKed.
NYX 0:85b3fd62ea1a 618 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
NYX 0:85b3fd62ea1a 619 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 620 * @retval None
NYX 0:85b3fd62ea1a 621 */
NYX 0:85b3fd62ea1a 622 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 623 {
NYX 0:85b3fd62ea1a 624 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
NYX 0:85b3fd62ea1a 625 }
NYX 0:85b3fd62ea1a 626
NYX 0:85b3fd62ea1a 627 /**
NYX 0:85b3fd62ea1a 628 * @brief Disable General Call.
NYX 0:85b3fd62ea1a 629 * @note When disabled the Address 0x00 is NACKed.
NYX 0:85b3fd62ea1a 630 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
NYX 0:85b3fd62ea1a 631 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 632 * @retval None
NYX 0:85b3fd62ea1a 633 */
NYX 0:85b3fd62ea1a 634 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 635 {
NYX 0:85b3fd62ea1a 636 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
NYX 0:85b3fd62ea1a 637 }
NYX 0:85b3fd62ea1a 638
NYX 0:85b3fd62ea1a 639 /**
NYX 0:85b3fd62ea1a 640 * @brief Check if General Call is enabled or disabled.
NYX 0:85b3fd62ea1a 641 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
NYX 0:85b3fd62ea1a 642 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 643 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 644 */
NYX 0:85b3fd62ea1a 645 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 646 {
NYX 0:85b3fd62ea1a 647 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
NYX 0:85b3fd62ea1a 648 }
NYX 0:85b3fd62ea1a 649
NYX 0:85b3fd62ea1a 650 /**
NYX 0:85b3fd62ea1a 651 * @brief Set the Own Address1.
NYX 0:85b3fd62ea1a 652 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
NYX 0:85b3fd62ea1a 653 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
NYX 0:85b3fd62ea1a 654 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
NYX 0:85b3fd62ea1a 655 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
NYX 0:85b3fd62ea1a 656 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 657 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
NYX 0:85b3fd62ea1a 658 * @param OwnAddrSize This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 659 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
NYX 0:85b3fd62ea1a 660 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
NYX 0:85b3fd62ea1a 661 * @retval None
NYX 0:85b3fd62ea1a 662 */
NYX 0:85b3fd62ea1a 663 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
NYX 0:85b3fd62ea1a 664 {
NYX 0:85b3fd62ea1a 665 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
NYX 0:85b3fd62ea1a 666 }
NYX 0:85b3fd62ea1a 667
NYX 0:85b3fd62ea1a 668 /**
NYX 0:85b3fd62ea1a 669 * @brief Set the 7bits Own Address2.
NYX 0:85b3fd62ea1a 670 * @note This action has no effect if own address2 is enabled.
NYX 0:85b3fd62ea1a 671 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
NYX 0:85b3fd62ea1a 672 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 673 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
NYX 0:85b3fd62ea1a 674 * @retval None
NYX 0:85b3fd62ea1a 675 */
NYX 0:85b3fd62ea1a 676 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
NYX 0:85b3fd62ea1a 677 {
NYX 0:85b3fd62ea1a 678 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
NYX 0:85b3fd62ea1a 679 }
NYX 0:85b3fd62ea1a 680
NYX 0:85b3fd62ea1a 681 /**
NYX 0:85b3fd62ea1a 682 * @brief Enable acknowledge on Own Address2 match address.
NYX 0:85b3fd62ea1a 683 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
NYX 0:85b3fd62ea1a 684 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 685 * @retval None
NYX 0:85b3fd62ea1a 686 */
NYX 0:85b3fd62ea1a 687 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 688 {
NYX 0:85b3fd62ea1a 689 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
NYX 0:85b3fd62ea1a 690 }
NYX 0:85b3fd62ea1a 691
NYX 0:85b3fd62ea1a 692 /**
NYX 0:85b3fd62ea1a 693 * @brief Disable acknowledge on Own Address2 match address.
NYX 0:85b3fd62ea1a 694 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
NYX 0:85b3fd62ea1a 695 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 696 * @retval None
NYX 0:85b3fd62ea1a 697 */
NYX 0:85b3fd62ea1a 698 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 699 {
NYX 0:85b3fd62ea1a 700 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
NYX 0:85b3fd62ea1a 701 }
NYX 0:85b3fd62ea1a 702
NYX 0:85b3fd62ea1a 703 /**
NYX 0:85b3fd62ea1a 704 * @brief Check if Own Address1 acknowledge is enabled or disabled.
NYX 0:85b3fd62ea1a 705 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
NYX 0:85b3fd62ea1a 706 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 707 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 708 */
NYX 0:85b3fd62ea1a 709 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 710 {
NYX 0:85b3fd62ea1a 711 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
NYX 0:85b3fd62ea1a 712 }
NYX 0:85b3fd62ea1a 713
NYX 0:85b3fd62ea1a 714 /**
NYX 0:85b3fd62ea1a 715 * @brief Configure the Peripheral clock frequency.
NYX 0:85b3fd62ea1a 716 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
NYX 0:85b3fd62ea1a 717 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 718 * @param PeriphClock Peripheral Clock (in Hz)
NYX 0:85b3fd62ea1a 719 * @retval None
NYX 0:85b3fd62ea1a 720 */
NYX 0:85b3fd62ea1a 721 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
NYX 0:85b3fd62ea1a 722 {
NYX 0:85b3fd62ea1a 723 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
NYX 0:85b3fd62ea1a 724 }
NYX 0:85b3fd62ea1a 725
NYX 0:85b3fd62ea1a 726 /**
NYX 0:85b3fd62ea1a 727 * @brief Get the Peripheral clock frequency.
NYX 0:85b3fd62ea1a 728 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
NYX 0:85b3fd62ea1a 729 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 730 * @retval Value of Peripheral Clock (in Hz)
NYX 0:85b3fd62ea1a 731 */
NYX 0:85b3fd62ea1a 732 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 733 {
NYX 0:85b3fd62ea1a 734 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
NYX 0:85b3fd62ea1a 735 }
NYX 0:85b3fd62ea1a 736
NYX 0:85b3fd62ea1a 737 /**
NYX 0:85b3fd62ea1a 738 * @brief Configure the Duty cycle (Fast mode only).
NYX 0:85b3fd62ea1a 739 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
NYX 0:85b3fd62ea1a 740 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 741 * @param DutyCycle This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 742 * @arg @ref LL_I2C_DUTYCYCLE_2
NYX 0:85b3fd62ea1a 743 * @arg @ref LL_I2C_DUTYCYCLE_16_9
NYX 0:85b3fd62ea1a 744 * @retval None
NYX 0:85b3fd62ea1a 745 */
NYX 0:85b3fd62ea1a 746 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
NYX 0:85b3fd62ea1a 747 {
NYX 0:85b3fd62ea1a 748 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
NYX 0:85b3fd62ea1a 749 }
NYX 0:85b3fd62ea1a 750
NYX 0:85b3fd62ea1a 751 /**
NYX 0:85b3fd62ea1a 752 * @brief Get the Duty cycle (Fast mode only).
NYX 0:85b3fd62ea1a 753 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
NYX 0:85b3fd62ea1a 754 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 755 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 756 * @arg @ref LL_I2C_DUTYCYCLE_2
NYX 0:85b3fd62ea1a 757 * @arg @ref LL_I2C_DUTYCYCLE_16_9
NYX 0:85b3fd62ea1a 758 */
NYX 0:85b3fd62ea1a 759 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 760 {
NYX 0:85b3fd62ea1a 761 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
NYX 0:85b3fd62ea1a 762 }
NYX 0:85b3fd62ea1a 763
NYX 0:85b3fd62ea1a 764 /**
NYX 0:85b3fd62ea1a 765 * @brief Configure the I2C master clock speed mode.
NYX 0:85b3fd62ea1a 766 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
NYX 0:85b3fd62ea1a 767 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 768 * @param ClockSpeedMode This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 769 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
NYX 0:85b3fd62ea1a 770 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
NYX 0:85b3fd62ea1a 771 * @retval None
NYX 0:85b3fd62ea1a 772 */
NYX 0:85b3fd62ea1a 773 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
NYX 0:85b3fd62ea1a 774 {
NYX 0:85b3fd62ea1a 775 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
NYX 0:85b3fd62ea1a 776 }
NYX 0:85b3fd62ea1a 777
NYX 0:85b3fd62ea1a 778 /**
NYX 0:85b3fd62ea1a 779 * @brief Get the the I2C master speed mode.
NYX 0:85b3fd62ea1a 780 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
NYX 0:85b3fd62ea1a 781 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 782 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 783 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
NYX 0:85b3fd62ea1a 784 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
NYX 0:85b3fd62ea1a 785 */
NYX 0:85b3fd62ea1a 786 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 787 {
NYX 0:85b3fd62ea1a 788 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
NYX 0:85b3fd62ea1a 789 }
NYX 0:85b3fd62ea1a 790
NYX 0:85b3fd62ea1a 791 /**
NYX 0:85b3fd62ea1a 792 * @brief Configure the SCL, SDA rising time.
NYX 0:85b3fd62ea1a 793 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 794 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
NYX 0:85b3fd62ea1a 795 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 796 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
NYX 0:85b3fd62ea1a 797 * @retval None
NYX 0:85b3fd62ea1a 798 */
NYX 0:85b3fd62ea1a 799 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
NYX 0:85b3fd62ea1a 800 {
NYX 0:85b3fd62ea1a 801 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
NYX 0:85b3fd62ea1a 802 }
NYX 0:85b3fd62ea1a 803
NYX 0:85b3fd62ea1a 804 /**
NYX 0:85b3fd62ea1a 805 * @brief Get the SCL, SDA rising time.
NYX 0:85b3fd62ea1a 806 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
NYX 0:85b3fd62ea1a 807 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 808 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
NYX 0:85b3fd62ea1a 809 */
NYX 0:85b3fd62ea1a 810 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 811 {
NYX 0:85b3fd62ea1a 812 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
NYX 0:85b3fd62ea1a 813 }
NYX 0:85b3fd62ea1a 814
NYX 0:85b3fd62ea1a 815 /**
NYX 0:85b3fd62ea1a 816 * @brief Configure the SCL high and low period.
NYX 0:85b3fd62ea1a 817 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 818 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
NYX 0:85b3fd62ea1a 819 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 820 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
NYX 0:85b3fd62ea1a 821 * @retval None
NYX 0:85b3fd62ea1a 822 */
NYX 0:85b3fd62ea1a 823 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
NYX 0:85b3fd62ea1a 824 {
NYX 0:85b3fd62ea1a 825 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
NYX 0:85b3fd62ea1a 826 }
NYX 0:85b3fd62ea1a 827
NYX 0:85b3fd62ea1a 828 /**
NYX 0:85b3fd62ea1a 829 * @brief Get the SCL high and low period.
NYX 0:85b3fd62ea1a 830 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
NYX 0:85b3fd62ea1a 831 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 832 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
NYX 0:85b3fd62ea1a 833 */
NYX 0:85b3fd62ea1a 834 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 835 {
NYX 0:85b3fd62ea1a 836 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
NYX 0:85b3fd62ea1a 837 }
NYX 0:85b3fd62ea1a 838
NYX 0:85b3fd62ea1a 839 /**
NYX 0:85b3fd62ea1a 840 * @brief Configure the SCL speed.
NYX 0:85b3fd62ea1a 841 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
NYX 0:85b3fd62ea1a 842 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
NYX 0:85b3fd62ea1a 843 * TRISE TRISE LL_I2C_ConfigSpeed\n
NYX 0:85b3fd62ea1a 844 * CCR FS LL_I2C_ConfigSpeed\n
NYX 0:85b3fd62ea1a 845 * CCR DUTY LL_I2C_ConfigSpeed\n
NYX 0:85b3fd62ea1a 846 * CCR CCR LL_I2C_ConfigSpeed
NYX 0:85b3fd62ea1a 847 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 848 * @param PeriphClock Peripheral Clock (in Hz)
NYX 0:85b3fd62ea1a 849 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
NYX 0:85b3fd62ea1a 850 * @param DutyCycle This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 851 * @arg @ref LL_I2C_DUTYCYCLE_2
NYX 0:85b3fd62ea1a 852 * @arg @ref LL_I2C_DUTYCYCLE_16_9
NYX 0:85b3fd62ea1a 853 * @retval None
NYX 0:85b3fd62ea1a 854 */
NYX 0:85b3fd62ea1a 855 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
NYX 0:85b3fd62ea1a 856 uint32_t DutyCycle)
NYX 0:85b3fd62ea1a 857 {
NYX 0:85b3fd62ea1a 858 register uint32_t freqrange = 0x0U;
NYX 0:85b3fd62ea1a 859 register uint32_t clockconfig = 0x0U;
NYX 0:85b3fd62ea1a 860
NYX 0:85b3fd62ea1a 861 /* Compute frequency range */
NYX 0:85b3fd62ea1a 862 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
NYX 0:85b3fd62ea1a 863
NYX 0:85b3fd62ea1a 864 /* Configure I2Cx: Frequency range register */
NYX 0:85b3fd62ea1a 865 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
NYX 0:85b3fd62ea1a 866
NYX 0:85b3fd62ea1a 867 /* Configure I2Cx: Rise Time register */
NYX 0:85b3fd62ea1a 868 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
NYX 0:85b3fd62ea1a 869
NYX 0:85b3fd62ea1a 870 /* Configure Speed mode, Duty Cycle and Clock control register value */
NYX 0:85b3fd62ea1a 871 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
NYX 0:85b3fd62ea1a 872 {
NYX 0:85b3fd62ea1a 873 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
NYX 0:85b3fd62ea1a 874 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
NYX 0:85b3fd62ea1a 875 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
NYX 0:85b3fd62ea1a 876 DutyCycle;
NYX 0:85b3fd62ea1a 877 }
NYX 0:85b3fd62ea1a 878 else
NYX 0:85b3fd62ea1a 879 {
NYX 0:85b3fd62ea1a 880 /* Set Speed mode at standard for Clock Speed request in standard clock range */
NYX 0:85b3fd62ea1a 881 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
NYX 0:85b3fd62ea1a 882 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
NYX 0:85b3fd62ea1a 883 }
NYX 0:85b3fd62ea1a 884
NYX 0:85b3fd62ea1a 885 /* Configure I2Cx: Clock control register */
NYX 0:85b3fd62ea1a 886 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
NYX 0:85b3fd62ea1a 887 }
NYX 0:85b3fd62ea1a 888
NYX 0:85b3fd62ea1a 889 /**
NYX 0:85b3fd62ea1a 890 * @brief Configure peripheral mode.
NYX 0:85b3fd62ea1a 891 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 892 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 893 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
NYX 0:85b3fd62ea1a 894 * CR1 SMBTYPE LL_I2C_SetMode\n
NYX 0:85b3fd62ea1a 895 * CR1 ENARP LL_I2C_SetMode
NYX 0:85b3fd62ea1a 896 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 897 * @param PeripheralMode This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 898 * @arg @ref LL_I2C_MODE_I2C
NYX 0:85b3fd62ea1a 899 * @arg @ref LL_I2C_MODE_SMBUS_HOST
NYX 0:85b3fd62ea1a 900 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
NYX 0:85b3fd62ea1a 901 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
NYX 0:85b3fd62ea1a 902 * @retval None
NYX 0:85b3fd62ea1a 903 */
NYX 0:85b3fd62ea1a 904 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
NYX 0:85b3fd62ea1a 905 {
NYX 0:85b3fd62ea1a 906 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
NYX 0:85b3fd62ea1a 907 }
NYX 0:85b3fd62ea1a 908
NYX 0:85b3fd62ea1a 909 /**
NYX 0:85b3fd62ea1a 910 * @brief Get peripheral mode.
NYX 0:85b3fd62ea1a 911 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 912 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 913 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
NYX 0:85b3fd62ea1a 914 * CR1 SMBTYPE LL_I2C_GetMode\n
NYX 0:85b3fd62ea1a 915 * CR1 ENARP LL_I2C_GetMode
NYX 0:85b3fd62ea1a 916 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 917 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 918 * @arg @ref LL_I2C_MODE_I2C
NYX 0:85b3fd62ea1a 919 * @arg @ref LL_I2C_MODE_SMBUS_HOST
NYX 0:85b3fd62ea1a 920 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
NYX 0:85b3fd62ea1a 921 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
NYX 0:85b3fd62ea1a 922 */
NYX 0:85b3fd62ea1a 923 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 924 {
NYX 0:85b3fd62ea1a 925 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
NYX 0:85b3fd62ea1a 926 }
NYX 0:85b3fd62ea1a 927
NYX 0:85b3fd62ea1a 928 /**
NYX 0:85b3fd62ea1a 929 * @brief Enable SMBus alert (Host or Device mode)
NYX 0:85b3fd62ea1a 930 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 931 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 932 * @note SMBus Device mode:
NYX 0:85b3fd62ea1a 933 * - SMBus Alert pin is drived low and
NYX 0:85b3fd62ea1a 934 * Alert Response Address Header acknowledge is enabled.
NYX 0:85b3fd62ea1a 935 * SMBus Host mode:
NYX 0:85b3fd62ea1a 936 * - SMBus Alert pin management is supported.
NYX 0:85b3fd62ea1a 937 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
NYX 0:85b3fd62ea1a 938 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 939 * @retval None
NYX 0:85b3fd62ea1a 940 */
NYX 0:85b3fd62ea1a 941 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 942 {
NYX 0:85b3fd62ea1a 943 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
NYX 0:85b3fd62ea1a 944 }
NYX 0:85b3fd62ea1a 945
NYX 0:85b3fd62ea1a 946 /**
NYX 0:85b3fd62ea1a 947 * @brief Disable SMBus alert (Host or Device mode)
NYX 0:85b3fd62ea1a 948 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 949 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 950 * @note SMBus Device mode:
NYX 0:85b3fd62ea1a 951 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
NYX 0:85b3fd62ea1a 952 * Alert Response Address Header acknowledge is disabled.
NYX 0:85b3fd62ea1a 953 * SMBus Host mode:
NYX 0:85b3fd62ea1a 954 * - SMBus Alert pin management is not supported.
NYX 0:85b3fd62ea1a 955 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
NYX 0:85b3fd62ea1a 956 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 957 * @retval None
NYX 0:85b3fd62ea1a 958 */
NYX 0:85b3fd62ea1a 959 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 960 {
NYX 0:85b3fd62ea1a 961 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
NYX 0:85b3fd62ea1a 962 }
NYX 0:85b3fd62ea1a 963
NYX 0:85b3fd62ea1a 964 /**
NYX 0:85b3fd62ea1a 965 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
NYX 0:85b3fd62ea1a 966 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 967 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 968 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
NYX 0:85b3fd62ea1a 969 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 970 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 971 */
NYX 0:85b3fd62ea1a 972 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 973 {
NYX 0:85b3fd62ea1a 974 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
NYX 0:85b3fd62ea1a 975 }
NYX 0:85b3fd62ea1a 976
NYX 0:85b3fd62ea1a 977 /**
NYX 0:85b3fd62ea1a 978 * @brief Enable SMBus Packet Error Calculation (PEC).
NYX 0:85b3fd62ea1a 979 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 980 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 981 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
NYX 0:85b3fd62ea1a 982 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 983 * @retval None
NYX 0:85b3fd62ea1a 984 */
NYX 0:85b3fd62ea1a 985 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 986 {
NYX 0:85b3fd62ea1a 987 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
NYX 0:85b3fd62ea1a 988 }
NYX 0:85b3fd62ea1a 989
NYX 0:85b3fd62ea1a 990 /**
NYX 0:85b3fd62ea1a 991 * @brief Disable SMBus Packet Error Calculation (PEC).
NYX 0:85b3fd62ea1a 992 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 993 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 994 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
NYX 0:85b3fd62ea1a 995 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 996 * @retval None
NYX 0:85b3fd62ea1a 997 */
NYX 0:85b3fd62ea1a 998 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 999 {
NYX 0:85b3fd62ea1a 1000 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
NYX 0:85b3fd62ea1a 1001 }
NYX 0:85b3fd62ea1a 1002
NYX 0:85b3fd62ea1a 1003 /**
NYX 0:85b3fd62ea1a 1004 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
NYX 0:85b3fd62ea1a 1005 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1006 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1007 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
NYX 0:85b3fd62ea1a 1008 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1009 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1010 */
NYX 0:85b3fd62ea1a 1011 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1012 {
NYX 0:85b3fd62ea1a 1013 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
NYX 0:85b3fd62ea1a 1014 }
NYX 0:85b3fd62ea1a 1015
NYX 0:85b3fd62ea1a 1016 /**
NYX 0:85b3fd62ea1a 1017 * @}
NYX 0:85b3fd62ea1a 1018 */
NYX 0:85b3fd62ea1a 1019
NYX 0:85b3fd62ea1a 1020 /** @defgroup I2C_LL_EF_IT_Management IT_Management
NYX 0:85b3fd62ea1a 1021 * @{
NYX 0:85b3fd62ea1a 1022 */
NYX 0:85b3fd62ea1a 1023
NYX 0:85b3fd62ea1a 1024 /**
NYX 0:85b3fd62ea1a 1025 * @brief Enable TXE interrupt.
NYX 0:85b3fd62ea1a 1026 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
NYX 0:85b3fd62ea1a 1027 * CR2 ITBUFEN LL_I2C_EnableIT_TX
NYX 0:85b3fd62ea1a 1028 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1029 * @retval None
NYX 0:85b3fd62ea1a 1030 */
NYX 0:85b3fd62ea1a 1031 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1032 {
NYX 0:85b3fd62ea1a 1033 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
NYX 0:85b3fd62ea1a 1034 }
NYX 0:85b3fd62ea1a 1035
NYX 0:85b3fd62ea1a 1036 /**
NYX 0:85b3fd62ea1a 1037 * @brief Disable TXE interrupt.
NYX 0:85b3fd62ea1a 1038 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
NYX 0:85b3fd62ea1a 1039 * CR2 ITBUFEN LL_I2C_DisableIT_TX
NYX 0:85b3fd62ea1a 1040 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1041 * @retval None
NYX 0:85b3fd62ea1a 1042 */
NYX 0:85b3fd62ea1a 1043 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1044 {
NYX 0:85b3fd62ea1a 1045 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
NYX 0:85b3fd62ea1a 1046 }
NYX 0:85b3fd62ea1a 1047
NYX 0:85b3fd62ea1a 1048 /**
NYX 0:85b3fd62ea1a 1049 * @brief Check if the TXE Interrupt is enabled or disabled.
NYX 0:85b3fd62ea1a 1050 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
NYX 0:85b3fd62ea1a 1051 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
NYX 0:85b3fd62ea1a 1052 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1053 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1054 */
NYX 0:85b3fd62ea1a 1055 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1056 {
NYX 0:85b3fd62ea1a 1057 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
NYX 0:85b3fd62ea1a 1058 }
NYX 0:85b3fd62ea1a 1059
NYX 0:85b3fd62ea1a 1060 /**
NYX 0:85b3fd62ea1a 1061 * @brief Enable RXNE interrupt.
NYX 0:85b3fd62ea1a 1062 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
NYX 0:85b3fd62ea1a 1063 * CR2 ITBUFEN LL_I2C_EnableIT_RX
NYX 0:85b3fd62ea1a 1064 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1065 * @retval None
NYX 0:85b3fd62ea1a 1066 */
NYX 0:85b3fd62ea1a 1067 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1068 {
NYX 0:85b3fd62ea1a 1069 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
NYX 0:85b3fd62ea1a 1070 }
NYX 0:85b3fd62ea1a 1071
NYX 0:85b3fd62ea1a 1072 /**
NYX 0:85b3fd62ea1a 1073 * @brief Disable RXNE interrupt.
NYX 0:85b3fd62ea1a 1074 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
NYX 0:85b3fd62ea1a 1075 * CR2 ITBUFEN LL_I2C_DisableIT_RX
NYX 0:85b3fd62ea1a 1076 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1077 * @retval None
NYX 0:85b3fd62ea1a 1078 */
NYX 0:85b3fd62ea1a 1079 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1080 {
NYX 0:85b3fd62ea1a 1081 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
NYX 0:85b3fd62ea1a 1082 }
NYX 0:85b3fd62ea1a 1083
NYX 0:85b3fd62ea1a 1084 /**
NYX 0:85b3fd62ea1a 1085 * @brief Check if the RXNE Interrupt is enabled or disabled.
NYX 0:85b3fd62ea1a 1086 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
NYX 0:85b3fd62ea1a 1087 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
NYX 0:85b3fd62ea1a 1088 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1089 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1090 */
NYX 0:85b3fd62ea1a 1091 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1092 {
NYX 0:85b3fd62ea1a 1093 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
NYX 0:85b3fd62ea1a 1094 }
NYX 0:85b3fd62ea1a 1095
NYX 0:85b3fd62ea1a 1096 /**
NYX 0:85b3fd62ea1a 1097 * @brief Enable Events interrupts.
NYX 0:85b3fd62ea1a 1098 * @note Any of these events will generate interrupt :
NYX 0:85b3fd62ea1a 1099 * Start Bit (SB)
NYX 0:85b3fd62ea1a 1100 * Address sent, Address matched (ADDR)
NYX 0:85b3fd62ea1a 1101 * 10-bit header sent (ADD10)
NYX 0:85b3fd62ea1a 1102 * Stop detection (STOPF)
NYX 0:85b3fd62ea1a 1103 * Byte transfer finished (BTF)
NYX 0:85b3fd62ea1a 1104 *
NYX 0:85b3fd62ea1a 1105 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
NYX 0:85b3fd62ea1a 1106 * Receive buffer not empty (RXNE)
NYX 0:85b3fd62ea1a 1107 * Transmit buffer empty (TXE)
NYX 0:85b3fd62ea1a 1108 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
NYX 0:85b3fd62ea1a 1109 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1110 * @retval None
NYX 0:85b3fd62ea1a 1111 */
NYX 0:85b3fd62ea1a 1112 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1113 {
NYX 0:85b3fd62ea1a 1114 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
NYX 0:85b3fd62ea1a 1115 }
NYX 0:85b3fd62ea1a 1116
NYX 0:85b3fd62ea1a 1117 /**
NYX 0:85b3fd62ea1a 1118 * @brief Disable Events interrupts.
NYX 0:85b3fd62ea1a 1119 * @note Any of these events will generate interrupt :
NYX 0:85b3fd62ea1a 1120 * Start Bit (SB)
NYX 0:85b3fd62ea1a 1121 * Address sent, Address matched (ADDR)
NYX 0:85b3fd62ea1a 1122 * 10-bit header sent (ADD10)
NYX 0:85b3fd62ea1a 1123 * Stop detection (STOPF)
NYX 0:85b3fd62ea1a 1124 * Byte transfer finished (BTF)
NYX 0:85b3fd62ea1a 1125 * Receive buffer not empty (RXNE)
NYX 0:85b3fd62ea1a 1126 * Transmit buffer empty (TXE)
NYX 0:85b3fd62ea1a 1127 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
NYX 0:85b3fd62ea1a 1128 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1129 * @retval None
NYX 0:85b3fd62ea1a 1130 */
NYX 0:85b3fd62ea1a 1131 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1132 {
NYX 0:85b3fd62ea1a 1133 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
NYX 0:85b3fd62ea1a 1134 }
NYX 0:85b3fd62ea1a 1135
NYX 0:85b3fd62ea1a 1136 /**
NYX 0:85b3fd62ea1a 1137 * @brief Check if Events interrupts are enabled or disabled.
NYX 0:85b3fd62ea1a 1138 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
NYX 0:85b3fd62ea1a 1139 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1140 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1141 */
NYX 0:85b3fd62ea1a 1142 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1143 {
NYX 0:85b3fd62ea1a 1144 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
NYX 0:85b3fd62ea1a 1145 }
NYX 0:85b3fd62ea1a 1146
NYX 0:85b3fd62ea1a 1147 /**
NYX 0:85b3fd62ea1a 1148 * @brief Enable Buffer interrupts.
NYX 0:85b3fd62ea1a 1149 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
NYX 0:85b3fd62ea1a 1150 * Receive buffer not empty (RXNE)
NYX 0:85b3fd62ea1a 1151 * Transmit buffer empty (TXE)
NYX 0:85b3fd62ea1a 1152 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
NYX 0:85b3fd62ea1a 1153 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1154 * @retval None
NYX 0:85b3fd62ea1a 1155 */
NYX 0:85b3fd62ea1a 1156 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1157 {
NYX 0:85b3fd62ea1a 1158 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
NYX 0:85b3fd62ea1a 1159 }
NYX 0:85b3fd62ea1a 1160
NYX 0:85b3fd62ea1a 1161 /**
NYX 0:85b3fd62ea1a 1162 * @brief Disable Buffer interrupts.
NYX 0:85b3fd62ea1a 1163 * @note Any of these Buffer events will generate interrupt :
NYX 0:85b3fd62ea1a 1164 * Receive buffer not empty (RXNE)
NYX 0:85b3fd62ea1a 1165 * Transmit buffer empty (TXE)
NYX 0:85b3fd62ea1a 1166 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
NYX 0:85b3fd62ea1a 1167 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1168 * @retval None
NYX 0:85b3fd62ea1a 1169 */
NYX 0:85b3fd62ea1a 1170 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1171 {
NYX 0:85b3fd62ea1a 1172 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
NYX 0:85b3fd62ea1a 1173 }
NYX 0:85b3fd62ea1a 1174
NYX 0:85b3fd62ea1a 1175 /**
NYX 0:85b3fd62ea1a 1176 * @brief Check if Buffer interrupts are enabled or disabled.
NYX 0:85b3fd62ea1a 1177 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
NYX 0:85b3fd62ea1a 1178 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1179 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1180 */
NYX 0:85b3fd62ea1a 1181 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1182 {
NYX 0:85b3fd62ea1a 1183 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
NYX 0:85b3fd62ea1a 1184 }
NYX 0:85b3fd62ea1a 1185
NYX 0:85b3fd62ea1a 1186 /**
NYX 0:85b3fd62ea1a 1187 * @brief Enable Error interrupts.
NYX 0:85b3fd62ea1a 1188 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1189 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1190 * @note Any of these errors will generate interrupt :
NYX 0:85b3fd62ea1a 1191 * Bus Error detection (BERR)
NYX 0:85b3fd62ea1a 1192 * Arbitration Loss (ARLO)
NYX 0:85b3fd62ea1a 1193 * Acknowledge Failure(AF)
NYX 0:85b3fd62ea1a 1194 * Overrun/Underrun (OVR)
NYX 0:85b3fd62ea1a 1195 * SMBus Timeout detection (TIMEOUT)
NYX 0:85b3fd62ea1a 1196 * SMBus PEC error detection (PECERR)
NYX 0:85b3fd62ea1a 1197 * SMBus Alert pin event detection (SMBALERT)
NYX 0:85b3fd62ea1a 1198 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
NYX 0:85b3fd62ea1a 1199 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1200 * @retval None
NYX 0:85b3fd62ea1a 1201 */
NYX 0:85b3fd62ea1a 1202 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1203 {
NYX 0:85b3fd62ea1a 1204 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
NYX 0:85b3fd62ea1a 1205 }
NYX 0:85b3fd62ea1a 1206
NYX 0:85b3fd62ea1a 1207 /**
NYX 0:85b3fd62ea1a 1208 * @brief Disable Error interrupts.
NYX 0:85b3fd62ea1a 1209 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1210 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1211 * @note Any of these errors will generate interrupt :
NYX 0:85b3fd62ea1a 1212 * Bus Error detection (BERR)
NYX 0:85b3fd62ea1a 1213 * Arbitration Loss (ARLO)
NYX 0:85b3fd62ea1a 1214 * Acknowledge Failure(AF)
NYX 0:85b3fd62ea1a 1215 * Overrun/Underrun (OVR)
NYX 0:85b3fd62ea1a 1216 * SMBus Timeout detection (TIMEOUT)
NYX 0:85b3fd62ea1a 1217 * SMBus PEC error detection (PECERR)
NYX 0:85b3fd62ea1a 1218 * SMBus Alert pin event detection (SMBALERT)
NYX 0:85b3fd62ea1a 1219 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
NYX 0:85b3fd62ea1a 1220 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1221 * @retval None
NYX 0:85b3fd62ea1a 1222 */
NYX 0:85b3fd62ea1a 1223 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1224 {
NYX 0:85b3fd62ea1a 1225 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
NYX 0:85b3fd62ea1a 1226 }
NYX 0:85b3fd62ea1a 1227
NYX 0:85b3fd62ea1a 1228 /**
NYX 0:85b3fd62ea1a 1229 * @brief Check if Error interrupts are enabled or disabled.
NYX 0:85b3fd62ea1a 1230 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
NYX 0:85b3fd62ea1a 1231 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1232 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1233 */
NYX 0:85b3fd62ea1a 1234 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1235 {
NYX 0:85b3fd62ea1a 1236 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
NYX 0:85b3fd62ea1a 1237 }
NYX 0:85b3fd62ea1a 1238
NYX 0:85b3fd62ea1a 1239 /**
NYX 0:85b3fd62ea1a 1240 * @}
NYX 0:85b3fd62ea1a 1241 */
NYX 0:85b3fd62ea1a 1242
NYX 0:85b3fd62ea1a 1243 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
NYX 0:85b3fd62ea1a 1244 * @{
NYX 0:85b3fd62ea1a 1245 */
NYX 0:85b3fd62ea1a 1246
NYX 0:85b3fd62ea1a 1247 /**
NYX 0:85b3fd62ea1a 1248 * @brief Indicate the status of Transmit data register empty flag.
NYX 0:85b3fd62ea1a 1249 * @note RESET: When next data is written in Transmit data register.
NYX 0:85b3fd62ea1a 1250 * SET: When Transmit data register is empty.
NYX 0:85b3fd62ea1a 1251 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
NYX 0:85b3fd62ea1a 1252 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1253 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1254 */
NYX 0:85b3fd62ea1a 1255 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1256 {
NYX 0:85b3fd62ea1a 1257 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
NYX 0:85b3fd62ea1a 1258 }
NYX 0:85b3fd62ea1a 1259
NYX 0:85b3fd62ea1a 1260 /**
NYX 0:85b3fd62ea1a 1261 * @brief Indicate the status of Byte Transfer Finished flag.
NYX 0:85b3fd62ea1a 1262 * RESET: When Data byte transfer not done.
NYX 0:85b3fd62ea1a 1263 * SET: When Data byte transfer succeeded.
NYX 0:85b3fd62ea1a 1264 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
NYX 0:85b3fd62ea1a 1265 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1266 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1267 */
NYX 0:85b3fd62ea1a 1268 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1269 {
NYX 0:85b3fd62ea1a 1270 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
NYX 0:85b3fd62ea1a 1271 }
NYX 0:85b3fd62ea1a 1272
NYX 0:85b3fd62ea1a 1273 /**
NYX 0:85b3fd62ea1a 1274 * @brief Indicate the status of Receive data register not empty flag.
NYX 0:85b3fd62ea1a 1275 * @note RESET: When Receive data register is read.
NYX 0:85b3fd62ea1a 1276 * SET: When the received data is copied in Receive data register.
NYX 0:85b3fd62ea1a 1277 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
NYX 0:85b3fd62ea1a 1278 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1279 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1280 */
NYX 0:85b3fd62ea1a 1281 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1282 {
NYX 0:85b3fd62ea1a 1283 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
NYX 0:85b3fd62ea1a 1284 }
NYX 0:85b3fd62ea1a 1285
NYX 0:85b3fd62ea1a 1286 /**
NYX 0:85b3fd62ea1a 1287 * @brief Indicate the status of Start Bit (master mode).
NYX 0:85b3fd62ea1a 1288 * @note RESET: When No Start condition.
NYX 0:85b3fd62ea1a 1289 * SET: When Start condition is generated.
NYX 0:85b3fd62ea1a 1290 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
NYX 0:85b3fd62ea1a 1291 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1292 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1293 */
NYX 0:85b3fd62ea1a 1294 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1295 {
NYX 0:85b3fd62ea1a 1296 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
NYX 0:85b3fd62ea1a 1297 }
NYX 0:85b3fd62ea1a 1298
NYX 0:85b3fd62ea1a 1299 /**
NYX 0:85b3fd62ea1a 1300 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
NYX 0:85b3fd62ea1a 1301 * @note RESET: Clear default value.
NYX 0:85b3fd62ea1a 1302 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
NYX 0:85b3fd62ea1a 1303 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
NYX 0:85b3fd62ea1a 1304 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1305 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1306 */
NYX 0:85b3fd62ea1a 1307 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1308 {
NYX 0:85b3fd62ea1a 1309 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
NYX 0:85b3fd62ea1a 1310 }
NYX 0:85b3fd62ea1a 1311
NYX 0:85b3fd62ea1a 1312 /**
NYX 0:85b3fd62ea1a 1313 * @brief Indicate the status of 10-bit header sent (master mode).
NYX 0:85b3fd62ea1a 1314 * @note RESET: When no ADD10 event occured.
NYX 0:85b3fd62ea1a 1315 * SET: When the master has sent the first address byte (header).
NYX 0:85b3fd62ea1a 1316 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
NYX 0:85b3fd62ea1a 1317 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1318 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1319 */
NYX 0:85b3fd62ea1a 1320 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1321 {
NYX 0:85b3fd62ea1a 1322 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
NYX 0:85b3fd62ea1a 1323 }
NYX 0:85b3fd62ea1a 1324
NYX 0:85b3fd62ea1a 1325 /**
NYX 0:85b3fd62ea1a 1326 * @brief Indicate the status of Acknowledge failure flag.
NYX 0:85b3fd62ea1a 1327 * @note RESET: No acknowledge failure.
NYX 0:85b3fd62ea1a 1328 * SET: When an acknowledge failure is received after a byte transmission.
NYX 0:85b3fd62ea1a 1329 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
NYX 0:85b3fd62ea1a 1330 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1331 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1332 */
NYX 0:85b3fd62ea1a 1333 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1334 {
NYX 0:85b3fd62ea1a 1335 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
NYX 0:85b3fd62ea1a 1336 }
NYX 0:85b3fd62ea1a 1337
NYX 0:85b3fd62ea1a 1338 /**
NYX 0:85b3fd62ea1a 1339 * @brief Indicate the status of Stop detection flag (slave mode).
NYX 0:85b3fd62ea1a 1340 * @note RESET: Clear default value.
NYX 0:85b3fd62ea1a 1341 * SET: When a Stop condition is detected.
NYX 0:85b3fd62ea1a 1342 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
NYX 0:85b3fd62ea1a 1343 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1344 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1345 */
NYX 0:85b3fd62ea1a 1346 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1347 {
NYX 0:85b3fd62ea1a 1348 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
NYX 0:85b3fd62ea1a 1349 }
NYX 0:85b3fd62ea1a 1350
NYX 0:85b3fd62ea1a 1351 /**
NYX 0:85b3fd62ea1a 1352 * @brief Indicate the status of Bus error flag.
NYX 0:85b3fd62ea1a 1353 * @note RESET: Clear default value.
NYX 0:85b3fd62ea1a 1354 * SET: When a misplaced Start or Stop condition is detected.
NYX 0:85b3fd62ea1a 1355 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
NYX 0:85b3fd62ea1a 1356 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1357 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1358 */
NYX 0:85b3fd62ea1a 1359 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1360 {
NYX 0:85b3fd62ea1a 1361 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
NYX 0:85b3fd62ea1a 1362 }
NYX 0:85b3fd62ea1a 1363
NYX 0:85b3fd62ea1a 1364 /**
NYX 0:85b3fd62ea1a 1365 * @brief Indicate the status of Arbitration lost flag.
NYX 0:85b3fd62ea1a 1366 * @note RESET: Clear default value.
NYX 0:85b3fd62ea1a 1367 * SET: When arbitration lost.
NYX 0:85b3fd62ea1a 1368 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
NYX 0:85b3fd62ea1a 1369 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1370 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1371 */
NYX 0:85b3fd62ea1a 1372 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1373 {
NYX 0:85b3fd62ea1a 1374 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
NYX 0:85b3fd62ea1a 1375 }
NYX 0:85b3fd62ea1a 1376
NYX 0:85b3fd62ea1a 1377 /**
NYX 0:85b3fd62ea1a 1378 * @brief Indicate the status of Overrun/Underrun flag.
NYX 0:85b3fd62ea1a 1379 * @note RESET: Clear default value.
NYX 0:85b3fd62ea1a 1380 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
NYX 0:85b3fd62ea1a 1381 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
NYX 0:85b3fd62ea1a 1382 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1383 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1384 */
NYX 0:85b3fd62ea1a 1385 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1386 {
NYX 0:85b3fd62ea1a 1387 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
NYX 0:85b3fd62ea1a 1388 }
NYX 0:85b3fd62ea1a 1389
NYX 0:85b3fd62ea1a 1390 /**
NYX 0:85b3fd62ea1a 1391 * @brief Indicate the status of SMBus PEC error flag in reception.
NYX 0:85b3fd62ea1a 1392 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1393 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1394 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
NYX 0:85b3fd62ea1a 1395 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1396 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1397 */
NYX 0:85b3fd62ea1a 1398 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1399 {
NYX 0:85b3fd62ea1a 1400 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
NYX 0:85b3fd62ea1a 1401 }
NYX 0:85b3fd62ea1a 1402
NYX 0:85b3fd62ea1a 1403 /**
NYX 0:85b3fd62ea1a 1404 * @brief Indicate the status of SMBus Timeout detection flag.
NYX 0:85b3fd62ea1a 1405 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1406 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1407 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
NYX 0:85b3fd62ea1a 1408 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1409 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1410 */
NYX 0:85b3fd62ea1a 1411 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1412 {
NYX 0:85b3fd62ea1a 1413 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
NYX 0:85b3fd62ea1a 1414 }
NYX 0:85b3fd62ea1a 1415
NYX 0:85b3fd62ea1a 1416 /**
NYX 0:85b3fd62ea1a 1417 * @brief Indicate the status of SMBus alert flag.
NYX 0:85b3fd62ea1a 1418 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1419 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1420 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
NYX 0:85b3fd62ea1a 1421 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1422 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1423 */
NYX 0:85b3fd62ea1a 1424 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1425 {
NYX 0:85b3fd62ea1a 1426 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
NYX 0:85b3fd62ea1a 1427 }
NYX 0:85b3fd62ea1a 1428
NYX 0:85b3fd62ea1a 1429 /**
NYX 0:85b3fd62ea1a 1430 * @brief Indicate the status of Bus Busy flag.
NYX 0:85b3fd62ea1a 1431 * @note RESET: Clear default value.
NYX 0:85b3fd62ea1a 1432 * SET: When a Start condition is detected.
NYX 0:85b3fd62ea1a 1433 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
NYX 0:85b3fd62ea1a 1434 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1435 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1436 */
NYX 0:85b3fd62ea1a 1437 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1438 {
NYX 0:85b3fd62ea1a 1439 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
NYX 0:85b3fd62ea1a 1440 }
NYX 0:85b3fd62ea1a 1441
NYX 0:85b3fd62ea1a 1442 /**
NYX 0:85b3fd62ea1a 1443 * @brief Indicate the status of Dual flag.
NYX 0:85b3fd62ea1a 1444 * @note RESET: Received address matched with OAR1.
NYX 0:85b3fd62ea1a 1445 * SET: Received address matched with OAR2.
NYX 0:85b3fd62ea1a 1446 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
NYX 0:85b3fd62ea1a 1447 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1448 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1449 */
NYX 0:85b3fd62ea1a 1450 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1451 {
NYX 0:85b3fd62ea1a 1452 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
NYX 0:85b3fd62ea1a 1453 }
NYX 0:85b3fd62ea1a 1454
NYX 0:85b3fd62ea1a 1455 /**
NYX 0:85b3fd62ea1a 1456 * @brief Indicate the status of SMBus Host address reception (Slave mode).
NYX 0:85b3fd62ea1a 1457 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1458 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1459 * @note RESET: No SMBus Host address
NYX 0:85b3fd62ea1a 1460 * SET: SMBus Host address received.
NYX 0:85b3fd62ea1a 1461 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
NYX 0:85b3fd62ea1a 1462 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
NYX 0:85b3fd62ea1a 1463 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1464 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1465 */
NYX 0:85b3fd62ea1a 1466 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1467 {
NYX 0:85b3fd62ea1a 1468 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
NYX 0:85b3fd62ea1a 1469 }
NYX 0:85b3fd62ea1a 1470
NYX 0:85b3fd62ea1a 1471 /**
NYX 0:85b3fd62ea1a 1472 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
NYX 0:85b3fd62ea1a 1473 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1474 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1475 * @note RESET: No SMBus Device default address
NYX 0:85b3fd62ea1a 1476 * SET: SMBus Device default address received.
NYX 0:85b3fd62ea1a 1477 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
NYX 0:85b3fd62ea1a 1478 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
NYX 0:85b3fd62ea1a 1479 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1480 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1481 */
NYX 0:85b3fd62ea1a 1482 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1483 {
NYX 0:85b3fd62ea1a 1484 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
NYX 0:85b3fd62ea1a 1485 }
NYX 0:85b3fd62ea1a 1486
NYX 0:85b3fd62ea1a 1487 /**
NYX 0:85b3fd62ea1a 1488 * @brief Indicate the status of General call address reception (Slave mode).
NYX 0:85b3fd62ea1a 1489 * @note RESET: No Generall call address
NYX 0:85b3fd62ea1a 1490 * SET: General call address received.
NYX 0:85b3fd62ea1a 1491 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
NYX 0:85b3fd62ea1a 1492 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
NYX 0:85b3fd62ea1a 1493 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1494 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1495 */
NYX 0:85b3fd62ea1a 1496 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1497 {
NYX 0:85b3fd62ea1a 1498 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
NYX 0:85b3fd62ea1a 1499 }
NYX 0:85b3fd62ea1a 1500
NYX 0:85b3fd62ea1a 1501 /**
NYX 0:85b3fd62ea1a 1502 * @brief Indicate the status of Master/Slave flag.
NYX 0:85b3fd62ea1a 1503 * @note RESET: Slave Mode.
NYX 0:85b3fd62ea1a 1504 * SET: Master Mode.
NYX 0:85b3fd62ea1a 1505 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
NYX 0:85b3fd62ea1a 1506 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1507 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1508 */
NYX 0:85b3fd62ea1a 1509 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1510 {
NYX 0:85b3fd62ea1a 1511 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
NYX 0:85b3fd62ea1a 1512 }
NYX 0:85b3fd62ea1a 1513
NYX 0:85b3fd62ea1a 1514 /**
NYX 0:85b3fd62ea1a 1515 * @brief Clear Address Matched flag.
NYX 0:85b3fd62ea1a 1516 * @note Clearing this flag is done by a read access to the I2Cx_SR1
NYX 0:85b3fd62ea1a 1517 * register followed by a read access to the I2Cx_SR2 register.
NYX 0:85b3fd62ea1a 1518 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
NYX 0:85b3fd62ea1a 1519 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1520 * @retval None
NYX 0:85b3fd62ea1a 1521 */
NYX 0:85b3fd62ea1a 1522 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1523 {
NYX 0:85b3fd62ea1a 1524 __IO uint32_t tmpreg;
NYX 0:85b3fd62ea1a 1525 tmpreg = I2Cx->SR1;
NYX 0:85b3fd62ea1a 1526 (void) tmpreg;
NYX 0:85b3fd62ea1a 1527 tmpreg = I2Cx->SR2;
NYX 0:85b3fd62ea1a 1528 (void) tmpreg;
NYX 0:85b3fd62ea1a 1529 }
NYX 0:85b3fd62ea1a 1530
NYX 0:85b3fd62ea1a 1531 /**
NYX 0:85b3fd62ea1a 1532 * @brief Clear Acknowledge failure flag.
NYX 0:85b3fd62ea1a 1533 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
NYX 0:85b3fd62ea1a 1534 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1535 * @retval None
NYX 0:85b3fd62ea1a 1536 */
NYX 0:85b3fd62ea1a 1537 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1538 {
NYX 0:85b3fd62ea1a 1539 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
NYX 0:85b3fd62ea1a 1540 }
NYX 0:85b3fd62ea1a 1541
NYX 0:85b3fd62ea1a 1542 /**
NYX 0:85b3fd62ea1a 1543 * @brief Clear Stop detection flag.
NYX 0:85b3fd62ea1a 1544 * @note Clearing this flag is done by a read access to the I2Cx_SR1
NYX 0:85b3fd62ea1a 1545 * register followed by a write access to I2Cx_CR1 register.
NYX 0:85b3fd62ea1a 1546 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
NYX 0:85b3fd62ea1a 1547 * CR1 PE LL_I2C_ClearFlag_STOP
NYX 0:85b3fd62ea1a 1548 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1549 * @retval None
NYX 0:85b3fd62ea1a 1550 */
NYX 0:85b3fd62ea1a 1551 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1552 {
NYX 0:85b3fd62ea1a 1553 __IO uint32_t tmpreg;
NYX 0:85b3fd62ea1a 1554 tmpreg = I2Cx->SR1;
NYX 0:85b3fd62ea1a 1555 (void) tmpreg;
NYX 0:85b3fd62ea1a 1556 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
NYX 0:85b3fd62ea1a 1557 }
NYX 0:85b3fd62ea1a 1558
NYX 0:85b3fd62ea1a 1559 /**
NYX 0:85b3fd62ea1a 1560 * @brief Clear Bus error flag.
NYX 0:85b3fd62ea1a 1561 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
NYX 0:85b3fd62ea1a 1562 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1563 * @retval None
NYX 0:85b3fd62ea1a 1564 */
NYX 0:85b3fd62ea1a 1565 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1566 {
NYX 0:85b3fd62ea1a 1567 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
NYX 0:85b3fd62ea1a 1568 }
NYX 0:85b3fd62ea1a 1569
NYX 0:85b3fd62ea1a 1570 /**
NYX 0:85b3fd62ea1a 1571 * @brief Clear Arbitration lost flag.
NYX 0:85b3fd62ea1a 1572 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
NYX 0:85b3fd62ea1a 1573 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1574 * @retval None
NYX 0:85b3fd62ea1a 1575 */
NYX 0:85b3fd62ea1a 1576 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1577 {
NYX 0:85b3fd62ea1a 1578 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
NYX 0:85b3fd62ea1a 1579 }
NYX 0:85b3fd62ea1a 1580
NYX 0:85b3fd62ea1a 1581 /**
NYX 0:85b3fd62ea1a 1582 * @brief Clear Overrun/Underrun flag.
NYX 0:85b3fd62ea1a 1583 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
NYX 0:85b3fd62ea1a 1584 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1585 * @retval None
NYX 0:85b3fd62ea1a 1586 */
NYX 0:85b3fd62ea1a 1587 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1588 {
NYX 0:85b3fd62ea1a 1589 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
NYX 0:85b3fd62ea1a 1590 }
NYX 0:85b3fd62ea1a 1591
NYX 0:85b3fd62ea1a 1592 /**
NYX 0:85b3fd62ea1a 1593 * @brief Clear SMBus PEC error flag.
NYX 0:85b3fd62ea1a 1594 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
NYX 0:85b3fd62ea1a 1595 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1596 * @retval None
NYX 0:85b3fd62ea1a 1597 */
NYX 0:85b3fd62ea1a 1598 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1599 {
NYX 0:85b3fd62ea1a 1600 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
NYX 0:85b3fd62ea1a 1601 }
NYX 0:85b3fd62ea1a 1602
NYX 0:85b3fd62ea1a 1603 /**
NYX 0:85b3fd62ea1a 1604 * @brief Clear SMBus Timeout detection flag.
NYX 0:85b3fd62ea1a 1605 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1606 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1607 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
NYX 0:85b3fd62ea1a 1608 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1609 * @retval None
NYX 0:85b3fd62ea1a 1610 */
NYX 0:85b3fd62ea1a 1611 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1612 {
NYX 0:85b3fd62ea1a 1613 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
NYX 0:85b3fd62ea1a 1614 }
NYX 0:85b3fd62ea1a 1615
NYX 0:85b3fd62ea1a 1616 /**
NYX 0:85b3fd62ea1a 1617 * @brief Clear SMBus Alert flag.
NYX 0:85b3fd62ea1a 1618 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1619 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1620 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
NYX 0:85b3fd62ea1a 1621 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1622 * @retval None
NYX 0:85b3fd62ea1a 1623 */
NYX 0:85b3fd62ea1a 1624 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1625 {
NYX 0:85b3fd62ea1a 1626 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
NYX 0:85b3fd62ea1a 1627 }
NYX 0:85b3fd62ea1a 1628
NYX 0:85b3fd62ea1a 1629 /**
NYX 0:85b3fd62ea1a 1630 * @}
NYX 0:85b3fd62ea1a 1631 */
NYX 0:85b3fd62ea1a 1632
NYX 0:85b3fd62ea1a 1633 /** @defgroup I2C_LL_EF_Data_Management Data_Management
NYX 0:85b3fd62ea1a 1634 * @{
NYX 0:85b3fd62ea1a 1635 */
NYX 0:85b3fd62ea1a 1636
NYX 0:85b3fd62ea1a 1637 /**
NYX 0:85b3fd62ea1a 1638 * @brief Enable Reset of I2C peripheral.
NYX 0:85b3fd62ea1a 1639 * @rmtoll CR1 SWRST LL_I2C_EnableReset
NYX 0:85b3fd62ea1a 1640 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1641 * @retval None
NYX 0:85b3fd62ea1a 1642 */
NYX 0:85b3fd62ea1a 1643 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1644 {
NYX 0:85b3fd62ea1a 1645 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
NYX 0:85b3fd62ea1a 1646 }
NYX 0:85b3fd62ea1a 1647
NYX 0:85b3fd62ea1a 1648 /**
NYX 0:85b3fd62ea1a 1649 * @brief Disable Reset of I2C peripheral.
NYX 0:85b3fd62ea1a 1650 * @rmtoll CR1 SWRST LL_I2C_DisableReset
NYX 0:85b3fd62ea1a 1651 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1652 * @retval None
NYX 0:85b3fd62ea1a 1653 */
NYX 0:85b3fd62ea1a 1654 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1655 {
NYX 0:85b3fd62ea1a 1656 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
NYX 0:85b3fd62ea1a 1657 }
NYX 0:85b3fd62ea1a 1658
NYX 0:85b3fd62ea1a 1659 /**
NYX 0:85b3fd62ea1a 1660 * @brief Check if the I2C peripheral is under reset state or not.
NYX 0:85b3fd62ea1a 1661 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
NYX 0:85b3fd62ea1a 1662 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1663 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1664 */
NYX 0:85b3fd62ea1a 1665 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1666 {
NYX 0:85b3fd62ea1a 1667 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
NYX 0:85b3fd62ea1a 1668 }
NYX 0:85b3fd62ea1a 1669
NYX 0:85b3fd62ea1a 1670 /**
NYX 0:85b3fd62ea1a 1671 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
NYX 0:85b3fd62ea1a 1672 * @note Usage in Slave or Master mode.
NYX 0:85b3fd62ea1a 1673 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
NYX 0:85b3fd62ea1a 1674 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1675 * @param TypeAcknowledge This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1676 * @arg @ref LL_I2C_ACK
NYX 0:85b3fd62ea1a 1677 * @arg @ref LL_I2C_NACK
NYX 0:85b3fd62ea1a 1678 * @retval None
NYX 0:85b3fd62ea1a 1679 */
NYX 0:85b3fd62ea1a 1680 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
NYX 0:85b3fd62ea1a 1681 {
NYX 0:85b3fd62ea1a 1682 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
NYX 0:85b3fd62ea1a 1683 }
NYX 0:85b3fd62ea1a 1684
NYX 0:85b3fd62ea1a 1685 /**
NYX 0:85b3fd62ea1a 1686 * @brief Generate a START or RESTART condition
NYX 0:85b3fd62ea1a 1687 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
NYX 0:85b3fd62ea1a 1688 * This action has no effect when RELOAD is set.
NYX 0:85b3fd62ea1a 1689 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
NYX 0:85b3fd62ea1a 1690 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1691 * @retval None
NYX 0:85b3fd62ea1a 1692 */
NYX 0:85b3fd62ea1a 1693 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1694 {
NYX 0:85b3fd62ea1a 1695 SET_BIT(I2Cx->CR1, I2C_CR1_START);
NYX 0:85b3fd62ea1a 1696 }
NYX 0:85b3fd62ea1a 1697
NYX 0:85b3fd62ea1a 1698 /**
NYX 0:85b3fd62ea1a 1699 * @brief Generate a STOP condition after the current byte transfer (master mode).
NYX 0:85b3fd62ea1a 1700 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
NYX 0:85b3fd62ea1a 1701 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1702 * @retval None
NYX 0:85b3fd62ea1a 1703 */
NYX 0:85b3fd62ea1a 1704 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1705 {
NYX 0:85b3fd62ea1a 1706 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
NYX 0:85b3fd62ea1a 1707 }
NYX 0:85b3fd62ea1a 1708
NYX 0:85b3fd62ea1a 1709 /**
NYX 0:85b3fd62ea1a 1710 * @brief Enable bit POS (master/host mode).
NYX 0:85b3fd62ea1a 1711 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
NYX 0:85b3fd62ea1a 1712 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
NYX 0:85b3fd62ea1a 1713 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1714 * @retval None
NYX 0:85b3fd62ea1a 1715 */
NYX 0:85b3fd62ea1a 1716 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1717 {
NYX 0:85b3fd62ea1a 1718 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
NYX 0:85b3fd62ea1a 1719 }
NYX 0:85b3fd62ea1a 1720
NYX 0:85b3fd62ea1a 1721 /**
NYX 0:85b3fd62ea1a 1722 * @brief Disable bit POS (master/host mode).
NYX 0:85b3fd62ea1a 1723 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
NYX 0:85b3fd62ea1a 1724 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
NYX 0:85b3fd62ea1a 1725 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1726 * @retval None
NYX 0:85b3fd62ea1a 1727 */
NYX 0:85b3fd62ea1a 1728 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1729 {
NYX 0:85b3fd62ea1a 1730 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
NYX 0:85b3fd62ea1a 1731 }
NYX 0:85b3fd62ea1a 1732
NYX 0:85b3fd62ea1a 1733 /**
NYX 0:85b3fd62ea1a 1734 * @brief Check if bit POS is enabled or disabled.
NYX 0:85b3fd62ea1a 1735 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
NYX 0:85b3fd62ea1a 1736 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1737 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1738 */
NYX 0:85b3fd62ea1a 1739 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1740 {
NYX 0:85b3fd62ea1a 1741 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
NYX 0:85b3fd62ea1a 1742 }
NYX 0:85b3fd62ea1a 1743
NYX 0:85b3fd62ea1a 1744 /**
NYX 0:85b3fd62ea1a 1745 * @brief Indicate the value of transfer direction.
NYX 0:85b3fd62ea1a 1746 * @note RESET: Bus is in read transfer (peripheral point of view).
NYX 0:85b3fd62ea1a 1747 * SET: Bus is in write transfer (peripheral point of view).
NYX 0:85b3fd62ea1a 1748 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
NYX 0:85b3fd62ea1a 1749 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1750 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 1751 * @arg @ref LL_I2C_DIRECTION_WRITE
NYX 0:85b3fd62ea1a 1752 * @arg @ref LL_I2C_DIRECTION_READ
NYX 0:85b3fd62ea1a 1753 */
NYX 0:85b3fd62ea1a 1754 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1755 {
NYX 0:85b3fd62ea1a 1756 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
NYX 0:85b3fd62ea1a 1757 }
NYX 0:85b3fd62ea1a 1758
NYX 0:85b3fd62ea1a 1759 /**
NYX 0:85b3fd62ea1a 1760 * @brief Enable DMA last transfer.
NYX 0:85b3fd62ea1a 1761 * @note This action mean that next DMA EOT is the last transfer.
NYX 0:85b3fd62ea1a 1762 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
NYX 0:85b3fd62ea1a 1763 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1764 * @retval None
NYX 0:85b3fd62ea1a 1765 */
NYX 0:85b3fd62ea1a 1766 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1767 {
NYX 0:85b3fd62ea1a 1768 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
NYX 0:85b3fd62ea1a 1769 }
NYX 0:85b3fd62ea1a 1770
NYX 0:85b3fd62ea1a 1771 /**
NYX 0:85b3fd62ea1a 1772 * @brief Disable DMA last transfer.
NYX 0:85b3fd62ea1a 1773 * @note This action mean that next DMA EOT is not the last transfer.
NYX 0:85b3fd62ea1a 1774 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
NYX 0:85b3fd62ea1a 1775 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1776 * @retval None
NYX 0:85b3fd62ea1a 1777 */
NYX 0:85b3fd62ea1a 1778 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1779 {
NYX 0:85b3fd62ea1a 1780 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
NYX 0:85b3fd62ea1a 1781 }
NYX 0:85b3fd62ea1a 1782
NYX 0:85b3fd62ea1a 1783 /**
NYX 0:85b3fd62ea1a 1784 * @brief Check if DMA last transfer is enabled or disabled.
NYX 0:85b3fd62ea1a 1785 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
NYX 0:85b3fd62ea1a 1786 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1787 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1788 */
NYX 0:85b3fd62ea1a 1789 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1790 {
NYX 0:85b3fd62ea1a 1791 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
NYX 0:85b3fd62ea1a 1792 }
NYX 0:85b3fd62ea1a 1793
NYX 0:85b3fd62ea1a 1794 /**
NYX 0:85b3fd62ea1a 1795 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
NYX 0:85b3fd62ea1a 1796 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1797 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1798 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
NYX 0:85b3fd62ea1a 1799 * or by a START or STOP condition, it is also cleared by software.
NYX 0:85b3fd62ea1a 1800 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
NYX 0:85b3fd62ea1a 1801 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1802 * @retval None
NYX 0:85b3fd62ea1a 1803 */
NYX 0:85b3fd62ea1a 1804 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1805 {
NYX 0:85b3fd62ea1a 1806 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
NYX 0:85b3fd62ea1a 1807 }
NYX 0:85b3fd62ea1a 1808
NYX 0:85b3fd62ea1a 1809 /**
NYX 0:85b3fd62ea1a 1810 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
NYX 0:85b3fd62ea1a 1811 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1812 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1813 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
NYX 0:85b3fd62ea1a 1814 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1815 * @retval None
NYX 0:85b3fd62ea1a 1816 */
NYX 0:85b3fd62ea1a 1817 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1818 {
NYX 0:85b3fd62ea1a 1819 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
NYX 0:85b3fd62ea1a 1820 }
NYX 0:85b3fd62ea1a 1821
NYX 0:85b3fd62ea1a 1822 /**
NYX 0:85b3fd62ea1a 1823 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
NYX 0:85b3fd62ea1a 1824 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1825 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1826 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
NYX 0:85b3fd62ea1a 1827 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1828 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 1829 */
NYX 0:85b3fd62ea1a 1830 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1831 {
NYX 0:85b3fd62ea1a 1832 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
NYX 0:85b3fd62ea1a 1833 }
NYX 0:85b3fd62ea1a 1834
NYX 0:85b3fd62ea1a 1835 /**
NYX 0:85b3fd62ea1a 1836 * @brief Get the SMBus Packet Error byte calculated.
NYX 0:85b3fd62ea1a 1837 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
NYX 0:85b3fd62ea1a 1838 * SMBus feature is supported by the I2Cx Instance.
NYX 0:85b3fd62ea1a 1839 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
NYX 0:85b3fd62ea1a 1840 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1841 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
NYX 0:85b3fd62ea1a 1842 */
NYX 0:85b3fd62ea1a 1843 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1844 {
NYX 0:85b3fd62ea1a 1845 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
NYX 0:85b3fd62ea1a 1846 }
NYX 0:85b3fd62ea1a 1847
NYX 0:85b3fd62ea1a 1848 /**
NYX 0:85b3fd62ea1a 1849 * @brief Read Receive Data register.
NYX 0:85b3fd62ea1a 1850 * @rmtoll DR DR LL_I2C_ReceiveData8
NYX 0:85b3fd62ea1a 1851 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1852 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
NYX 0:85b3fd62ea1a 1853 */
NYX 0:85b3fd62ea1a 1854 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
NYX 0:85b3fd62ea1a 1855 {
NYX 0:85b3fd62ea1a 1856 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
NYX 0:85b3fd62ea1a 1857 }
NYX 0:85b3fd62ea1a 1858
NYX 0:85b3fd62ea1a 1859 /**
NYX 0:85b3fd62ea1a 1860 * @brief Write in Transmit Data Register .
NYX 0:85b3fd62ea1a 1861 * @rmtoll DR DR LL_I2C_TransmitData8
NYX 0:85b3fd62ea1a 1862 * @param I2Cx I2C Instance.
NYX 0:85b3fd62ea1a 1863 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
NYX 0:85b3fd62ea1a 1864 * @retval None
NYX 0:85b3fd62ea1a 1865 */
NYX 0:85b3fd62ea1a 1866 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
NYX 0:85b3fd62ea1a 1867 {
NYX 0:85b3fd62ea1a 1868 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
NYX 0:85b3fd62ea1a 1869 }
NYX 0:85b3fd62ea1a 1870
NYX 0:85b3fd62ea1a 1871 /**
NYX 0:85b3fd62ea1a 1872 * @}
NYX 0:85b3fd62ea1a 1873 */
NYX 0:85b3fd62ea1a 1874
NYX 0:85b3fd62ea1a 1875 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 1876 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 1877 * @{
NYX 0:85b3fd62ea1a 1878 */
NYX 0:85b3fd62ea1a 1879
NYX 0:85b3fd62ea1a 1880 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
NYX 0:85b3fd62ea1a 1881 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
NYX 0:85b3fd62ea1a 1882 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
NYX 0:85b3fd62ea1a 1883
NYX 0:85b3fd62ea1a 1884
NYX 0:85b3fd62ea1a 1885 /**
NYX 0:85b3fd62ea1a 1886 * @}
NYX 0:85b3fd62ea1a 1887 */
NYX 0:85b3fd62ea1a 1888 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 1889
NYX 0:85b3fd62ea1a 1890 /**
NYX 0:85b3fd62ea1a 1891 * @}
NYX 0:85b3fd62ea1a 1892 */
NYX 0:85b3fd62ea1a 1893
NYX 0:85b3fd62ea1a 1894 /**
NYX 0:85b3fd62ea1a 1895 * @}
NYX 0:85b3fd62ea1a 1896 */
NYX 0:85b3fd62ea1a 1897
NYX 0:85b3fd62ea1a 1898 #endif /* I2C1 || I2C2 || I2C3 */
NYX 0:85b3fd62ea1a 1899
NYX 0:85b3fd62ea1a 1900 /**
NYX 0:85b3fd62ea1a 1901 * @}
NYX 0:85b3fd62ea1a 1902 */
NYX 0:85b3fd62ea1a 1903
NYX 0:85b3fd62ea1a 1904 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 1905 }
NYX 0:85b3fd62ea1a 1906 #endif
NYX 0:85b3fd62ea1a 1907
NYX 0:85b3fd62ea1a 1908 #endif /* __STM32F4xx_LL_I2C_H */
NYX 0:85b3fd62ea1a 1909
NYX 0:85b3fd62ea1a 1910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/