Takaaki Numai / mbed-dev

inport from local

Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_fsmc.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of FSMC HAL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_LL_FSMC_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_LL_FSMC_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #include "stm32f4xx_hal_def.h"
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 50 * @{
NYX 0:85b3fd62ea1a 51 */
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 /** @addtogroup FSMC_LL
NYX 0:85b3fd62ea1a 54 * @{
NYX 0:85b3fd62ea1a 55 */
NYX 0:85b3fd62ea1a 56
NYX 0:85b3fd62ea1a 57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
NYX 0:85b3fd62ea1a 58 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 59 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
NYX 0:85b3fd62ea1a 61 * @{
NYX 0:85b3fd62ea1a 62 */
NYX 0:85b3fd62ea1a 63
NYX 0:85b3fd62ea1a 64 /**
NYX 0:85b3fd62ea1a 65 * @brief FSMC NORSRAM Configuration Structure definition
NYX 0:85b3fd62ea1a 66 */
NYX 0:85b3fd62ea1a 67 typedef struct
NYX 0:85b3fd62ea1a 68 {
NYX 0:85b3fd62ea1a 69 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
NYX 0:85b3fd62ea1a 70 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
NYX 0:85b3fd62ea1a 71
NYX 0:85b3fd62ea1a 72 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
NYX 0:85b3fd62ea1a 73 multiplexed on the data bus or not.
NYX 0:85b3fd62ea1a 74 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
NYX 0:85b3fd62ea1a 75
NYX 0:85b3fd62ea1a 76 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
NYX 0:85b3fd62ea1a 77 the corresponding memory device.
NYX 0:85b3fd62ea1a 78 This parameter can be a value of @ref FSMC_Memory_Type */
NYX 0:85b3fd62ea1a 79
NYX 0:85b3fd62ea1a 80 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
NYX 0:85b3fd62ea1a 81 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
NYX 0:85b3fd62ea1a 82
NYX 0:85b3fd62ea1a 83 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
NYX 0:85b3fd62ea1a 84 valid only with synchronous burst Flash memories.
NYX 0:85b3fd62ea1a 85 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
NYX 0:85b3fd62ea1a 86
NYX 0:85b3fd62ea1a 87 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
NYX 0:85b3fd62ea1a 88 the Flash memory in burst mode.
NYX 0:85b3fd62ea1a 89 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
NYX 0:85b3fd62ea1a 90
NYX 0:85b3fd62ea1a 91 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
NYX 0:85b3fd62ea1a 92 memory, valid only when accessing Flash memories in burst mode.
NYX 0:85b3fd62ea1a 93 This parameter can be a value of @ref FSMC_Wrap_Mode
NYX 0:85b3fd62ea1a 94 This mode is available only for the STM32F405/407/4015/417xx devices */
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
NYX 0:85b3fd62ea1a 97 clock cycle before the wait state or during the wait state,
NYX 0:85b3fd62ea1a 98 valid only when accessing memories in burst mode.
NYX 0:85b3fd62ea1a 99 This parameter can be a value of @ref FSMC_Wait_Timing */
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
NYX 0:85b3fd62ea1a 102 This parameter can be a value of @ref FSMC_Write_Operation */
NYX 0:85b3fd62ea1a 103
NYX 0:85b3fd62ea1a 104 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
NYX 0:85b3fd62ea1a 105 signal, valid for Flash memory access in burst mode.
NYX 0:85b3fd62ea1a 106 This parameter can be a value of @ref FSMC_Wait_Signal */
NYX 0:85b3fd62ea1a 107
NYX 0:85b3fd62ea1a 108 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
NYX 0:85b3fd62ea1a 109 This parameter can be a value of @ref FSMC_Extended_Mode */
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
NYX 0:85b3fd62ea1a 112 valid only with asynchronous Flash memories.
NYX 0:85b3fd62ea1a 113 This parameter can be a value of @ref FSMC_AsynchronousWait */
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
NYX 0:85b3fd62ea1a 116 This parameter can be a value of @ref FSMC_Write_Burst */
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
NYX 0:85b3fd62ea1a 119 This parameter is only enabled through the FMC_BCR1 register, and don't care
NYX 0:85b3fd62ea1a 120 through FMC_BCR2..4 registers.
NYX 0:85b3fd62ea1a 121 This parameter can be a value of @ref FMC_Continous_Clock
NYX 0:85b3fd62ea1a 122 This mode is available only for the STM32F412Vx/Zx/Rx devices */
NYX 0:85b3fd62ea1a 123
NYX 0:85b3fd62ea1a 124 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
NYX 0:85b3fd62ea1a 125 This parameter is only enabled through the FMC_BCR1 register, and don't care
NYX 0:85b3fd62ea1a 126 through FMC_BCR2..4 registers.
NYX 0:85b3fd62ea1a 127 This parameter can be a value of @ref FMC_Write_FIFO
NYX 0:85b3fd62ea1a 128 This mode is available only for the STM32F412Vx/Vx devices */
NYX 0:85b3fd62ea1a 129
NYX 0:85b3fd62ea1a 130 uint32_t PageSize; /*!< Specifies the memory page size.
NYX 0:85b3fd62ea1a 131 This parameter can be a value of @ref FMC_Page_Size */
NYX 0:85b3fd62ea1a 132 }FSMC_NORSRAM_InitTypeDef;
NYX 0:85b3fd62ea1a 133
NYX 0:85b3fd62ea1a 134 /**
NYX 0:85b3fd62ea1a 135 * @brief FSMC NORSRAM Timing parameters structure definition
NYX 0:85b3fd62ea1a 136 */
NYX 0:85b3fd62ea1a 137 typedef struct
NYX 0:85b3fd62ea1a 138 {
NYX 0:85b3fd62ea1a 139 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
NYX 0:85b3fd62ea1a 140 the duration of the address setup time.
NYX 0:85b3fd62ea1a 141 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
NYX 0:85b3fd62ea1a 142 @note This parameter is not used with synchronous NOR Flash memories. */
NYX 0:85b3fd62ea1a 143
NYX 0:85b3fd62ea1a 144 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
NYX 0:85b3fd62ea1a 145 the duration of the address hold time.
NYX 0:85b3fd62ea1a 146 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
NYX 0:85b3fd62ea1a 147 @note This parameter is not used with synchronous NOR Flash memories. */
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
NYX 0:85b3fd62ea1a 150 the duration of the data setup time.
NYX 0:85b3fd62ea1a 151 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
NYX 0:85b3fd62ea1a 152 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NYX 0:85b3fd62ea1a 153 NOR Flash memories. */
NYX 0:85b3fd62ea1a 154
NYX 0:85b3fd62ea1a 155 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
NYX 0:85b3fd62ea1a 156 the duration of the bus turnaround.
NYX 0:85b3fd62ea1a 157 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
NYX 0:85b3fd62ea1a 158 @note This parameter is only used for multiplexed NOR Flash memories. */
NYX 0:85b3fd62ea1a 159
NYX 0:85b3fd62ea1a 160 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
NYX 0:85b3fd62ea1a 161 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
NYX 0:85b3fd62ea1a 162 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
NYX 0:85b3fd62ea1a 163 accesses. */
NYX 0:85b3fd62ea1a 164
NYX 0:85b3fd62ea1a 165 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
NYX 0:85b3fd62ea1a 166 to the memory before getting the first data.
NYX 0:85b3fd62ea1a 167 The parameter value depends on the memory type as shown below:
NYX 0:85b3fd62ea1a 168 - It must be set to 0 in case of a CRAM
NYX 0:85b3fd62ea1a 169 - It is don't care in asynchronous NOR, SRAM or ROM accesses
NYX 0:85b3fd62ea1a 170 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
NYX 0:85b3fd62ea1a 171 with synchronous burst mode enable */
NYX 0:85b3fd62ea1a 172
NYX 0:85b3fd62ea1a 173 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
NYX 0:85b3fd62ea1a 174 This parameter can be a value of @ref FSMC_Access_Mode */
NYX 0:85b3fd62ea1a 175
NYX 0:85b3fd62ea1a 176 }FSMC_NORSRAM_TimingTypeDef;
NYX 0:85b3fd62ea1a 177
NYX 0:85b3fd62ea1a 178 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 179 /**
NYX 0:85b3fd62ea1a 180 * @brief FSMC NAND Configuration Structure definition
NYX 0:85b3fd62ea1a 181 */
NYX 0:85b3fd62ea1a 182 typedef struct
NYX 0:85b3fd62ea1a 183 {
NYX 0:85b3fd62ea1a 184 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
NYX 0:85b3fd62ea1a 185 This parameter can be a value of @ref FSMC_NAND_Bank */
NYX 0:85b3fd62ea1a 186
NYX 0:85b3fd62ea1a 187 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
NYX 0:85b3fd62ea1a 188 This parameter can be any value of @ref FSMC_Wait_feature */
NYX 0:85b3fd62ea1a 189
NYX 0:85b3fd62ea1a 190 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
NYX 0:85b3fd62ea1a 191 This parameter can be any value of @ref FSMC_NAND_Data_Width */
NYX 0:85b3fd62ea1a 192
NYX 0:85b3fd62ea1a 193 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
NYX 0:85b3fd62ea1a 194 This parameter can be any value of @ref FSMC_ECC */
NYX 0:85b3fd62ea1a 195
NYX 0:85b3fd62ea1a 196 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
NYX 0:85b3fd62ea1a 197 This parameter can be any value of @ref FSMC_ECC_Page_Size */
NYX 0:85b3fd62ea1a 198
NYX 0:85b3fd62ea1a 199 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
NYX 0:85b3fd62ea1a 200 delay between CLE low and RE low.
NYX 0:85b3fd62ea1a 201 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
NYX 0:85b3fd62ea1a 202
NYX 0:85b3fd62ea1a 203 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
NYX 0:85b3fd62ea1a 204 delay between ALE low and RE low.
NYX 0:85b3fd62ea1a 205 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX 0:85b3fd62ea1a 206
NYX 0:85b3fd62ea1a 207 }FSMC_NAND_InitTypeDef;
NYX 0:85b3fd62ea1a 208
NYX 0:85b3fd62ea1a 209 /**
NYX 0:85b3fd62ea1a 210 * @brief FSMC NAND/PCCARD Timing parameters structure definition
NYX 0:85b3fd62ea1a 211 */
NYX 0:85b3fd62ea1a 212 typedef struct
NYX 0:85b3fd62ea1a 213 {
NYX 0:85b3fd62ea1a 214 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
NYX 0:85b3fd62ea1a 215 the command assertion for NAND-Flash read or write access
NYX 0:85b3fd62ea1a 216 to common/Attribute or I/O memory space (depending on
NYX 0:85b3fd62ea1a 217 the memory space timing to be configured).
NYX 0:85b3fd62ea1a 218 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
NYX 0:85b3fd62ea1a 219
NYX 0:85b3fd62ea1a 220 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
NYX 0:85b3fd62ea1a 221 command for NAND-Flash read or write access to
NYX 0:85b3fd62ea1a 222 common/Attribute or I/O memory space (depending on the
NYX 0:85b3fd62ea1a 223 memory space timing to be configured).
NYX 0:85b3fd62ea1a 224 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX 0:85b3fd62ea1a 225
NYX 0:85b3fd62ea1a 226 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
NYX 0:85b3fd62ea1a 227 (and data for write access) after the command de-assertion
NYX 0:85b3fd62ea1a 228 for NAND-Flash read or write access to common/Attribute
NYX 0:85b3fd62ea1a 229 or I/O memory space (depending on the memory space timing
NYX 0:85b3fd62ea1a 230 to be configured).
NYX 0:85b3fd62ea1a 231 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX 0:85b3fd62ea1a 232
NYX 0:85b3fd62ea1a 233 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
NYX 0:85b3fd62ea1a 234 data bus is kept in HiZ after the start of a NAND-Flash
NYX 0:85b3fd62ea1a 235 write access to common/Attribute or I/O memory space (depending
NYX 0:85b3fd62ea1a 236 on the memory space timing to be configured).
NYX 0:85b3fd62ea1a 237 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX 0:85b3fd62ea1a 238
NYX 0:85b3fd62ea1a 239 }FSMC_NAND_PCC_TimingTypeDef;
NYX 0:85b3fd62ea1a 240
NYX 0:85b3fd62ea1a 241 /**
NYX 0:85b3fd62ea1a 242 * @brief FSMC NAND Configuration Structure definition
NYX 0:85b3fd62ea1a 243 */
NYX 0:85b3fd62ea1a 244 typedef struct
NYX 0:85b3fd62ea1a 245 {
NYX 0:85b3fd62ea1a 246 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
NYX 0:85b3fd62ea1a 247 This parameter can be any value of @ref FSMC_Wait_feature */
NYX 0:85b3fd62ea1a 248
NYX 0:85b3fd62ea1a 249 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
NYX 0:85b3fd62ea1a 250 delay between CLE low and RE low.
NYX 0:85b3fd62ea1a 251 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
NYX 0:85b3fd62ea1a 252
NYX 0:85b3fd62ea1a 253 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
NYX 0:85b3fd62ea1a 254 delay between ALE low and RE low.
NYX 0:85b3fd62ea1a 255 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX 0:85b3fd62ea1a 256
NYX 0:85b3fd62ea1a 257 }FSMC_PCCARD_InitTypeDef;
NYX 0:85b3fd62ea1a 258 /**
NYX 0:85b3fd62ea1a 259 * @}
NYX 0:85b3fd62ea1a 260 */
NYX 0:85b3fd62ea1a 261 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 262
NYX 0:85b3fd62ea1a 263 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 264 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
NYX 0:85b3fd62ea1a 265 * @{
NYX 0:85b3fd62ea1a 266 */
NYX 0:85b3fd62ea1a 267
NYX 0:85b3fd62ea1a 268 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
NYX 0:85b3fd62ea1a 269 * @{
NYX 0:85b3fd62ea1a 270 */
NYX 0:85b3fd62ea1a 271 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
NYX 0:85b3fd62ea1a 272 * @{
NYX 0:85b3fd62ea1a 273 */
NYX 0:85b3fd62ea1a 274 #define FSMC_NORSRAM_BANK1 0x00000000U
NYX 0:85b3fd62ea1a 275 #define FSMC_NORSRAM_BANK2 0x00000002U
NYX 0:85b3fd62ea1a 276 #define FSMC_NORSRAM_BANK3 0x00000004U
NYX 0:85b3fd62ea1a 277 #define FSMC_NORSRAM_BANK4 0x00000006U
NYX 0:85b3fd62ea1a 278 /**
NYX 0:85b3fd62ea1a 279 * @}
NYX 0:85b3fd62ea1a 280 */
NYX 0:85b3fd62ea1a 281
NYX 0:85b3fd62ea1a 282 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
NYX 0:85b3fd62ea1a 283 * @{
NYX 0:85b3fd62ea1a 284 */
NYX 0:85b3fd62ea1a 285 #define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 286 #define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
NYX 0:85b3fd62ea1a 287 /**
NYX 0:85b3fd62ea1a 288 * @}
NYX 0:85b3fd62ea1a 289 */
NYX 0:85b3fd62ea1a 290
NYX 0:85b3fd62ea1a 291 /** @defgroup FSMC_Memory_Type FSMC Memory Type
NYX 0:85b3fd62ea1a 292 * @{
NYX 0:85b3fd62ea1a 293 */
NYX 0:85b3fd62ea1a 294 #define FSMC_MEMORY_TYPE_SRAM 0x00000000U
NYX 0:85b3fd62ea1a 295 #define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
NYX 0:85b3fd62ea1a 296 #define FSMC_MEMORY_TYPE_NOR 0x00000008U
NYX 0:85b3fd62ea1a 297 /**
NYX 0:85b3fd62ea1a 298 * @}
NYX 0:85b3fd62ea1a 299 */
NYX 0:85b3fd62ea1a 300
NYX 0:85b3fd62ea1a 301 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
NYX 0:85b3fd62ea1a 302 * @{
NYX 0:85b3fd62ea1a 303 */
NYX 0:85b3fd62ea1a 304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
NYX 0:85b3fd62ea1a 305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
NYX 0:85b3fd62ea1a 306 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
NYX 0:85b3fd62ea1a 307 /**
NYX 0:85b3fd62ea1a 308 * @}
NYX 0:85b3fd62ea1a 309 */
NYX 0:85b3fd62ea1a 310
NYX 0:85b3fd62ea1a 311 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
NYX 0:85b3fd62ea1a 312 * @{
NYX 0:85b3fd62ea1a 313 */
NYX 0:85b3fd62ea1a 314 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
NYX 0:85b3fd62ea1a 315 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 316 /**
NYX 0:85b3fd62ea1a 317 * @}
NYX 0:85b3fd62ea1a 318 */
NYX 0:85b3fd62ea1a 319
NYX 0:85b3fd62ea1a 320 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
NYX 0:85b3fd62ea1a 321 * @{
NYX 0:85b3fd62ea1a 322 */
NYX 0:85b3fd62ea1a 323 #define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 324 #define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
NYX 0:85b3fd62ea1a 325 /**
NYX 0:85b3fd62ea1a 326 * @}
NYX 0:85b3fd62ea1a 327 */
NYX 0:85b3fd62ea1a 328
NYX 0:85b3fd62ea1a 329 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
NYX 0:85b3fd62ea1a 330 * @{
NYX 0:85b3fd62ea1a 331 */
NYX 0:85b3fd62ea1a 332 #define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
NYX 0:85b3fd62ea1a 333 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
NYX 0:85b3fd62ea1a 334 /**
NYX 0:85b3fd62ea1a 335 * @}
NYX 0:85b3fd62ea1a 336 */
NYX 0:85b3fd62ea1a 337
NYX 0:85b3fd62ea1a 338 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
NYX 0:85b3fd62ea1a 339 * @note These values are available only for the STM32F405/415/407/417xx devices.
NYX 0:85b3fd62ea1a 340 * @{
NYX 0:85b3fd62ea1a 341 */
NYX 0:85b3fd62ea1a 342 #define FSMC_WRAP_MODE_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 343 #define FSMC_WRAP_MODE_ENABLE 0x00000400U
NYX 0:85b3fd62ea1a 344 /**
NYX 0:85b3fd62ea1a 345 * @}
NYX 0:85b3fd62ea1a 346 */
NYX 0:85b3fd62ea1a 347
NYX 0:85b3fd62ea1a 348 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
NYX 0:85b3fd62ea1a 349 * @{
NYX 0:85b3fd62ea1a 350 */
NYX 0:85b3fd62ea1a 351 #define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
NYX 0:85b3fd62ea1a 352 #define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
NYX 0:85b3fd62ea1a 353 /**
NYX 0:85b3fd62ea1a 354 * @}
NYX 0:85b3fd62ea1a 355 */
NYX 0:85b3fd62ea1a 356
NYX 0:85b3fd62ea1a 357 /** @defgroup FSMC_Write_Operation FSMC Write Operation
NYX 0:85b3fd62ea1a 358 * @{
NYX 0:85b3fd62ea1a 359 */
NYX 0:85b3fd62ea1a 360 #define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 361 #define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
NYX 0:85b3fd62ea1a 362 /**
NYX 0:85b3fd62ea1a 363 * @}
NYX 0:85b3fd62ea1a 364 */
NYX 0:85b3fd62ea1a 365
NYX 0:85b3fd62ea1a 366 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
NYX 0:85b3fd62ea1a 367 * @{
NYX 0:85b3fd62ea1a 368 */
NYX 0:85b3fd62ea1a 369 #define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 370 #define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
NYX 0:85b3fd62ea1a 371 /**
NYX 0:85b3fd62ea1a 372 * @}
NYX 0:85b3fd62ea1a 373 */
NYX 0:85b3fd62ea1a 374
NYX 0:85b3fd62ea1a 375 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
NYX 0:85b3fd62ea1a 376 * @{
NYX 0:85b3fd62ea1a 377 */
NYX 0:85b3fd62ea1a 378 #define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 379 #define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
NYX 0:85b3fd62ea1a 380 /**
NYX 0:85b3fd62ea1a 381 * @}
NYX 0:85b3fd62ea1a 382 */
NYX 0:85b3fd62ea1a 383
NYX 0:85b3fd62ea1a 384 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
NYX 0:85b3fd62ea1a 385 * @{
NYX 0:85b3fd62ea1a 386 */
NYX 0:85b3fd62ea1a 387 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 388 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
NYX 0:85b3fd62ea1a 389 /**
NYX 0:85b3fd62ea1a 390 * @}
NYX 0:85b3fd62ea1a 391 */
NYX 0:85b3fd62ea1a 392
NYX 0:85b3fd62ea1a 393 /** @defgroup FSMC_Page_Size FSMC Page Size
NYX 0:85b3fd62ea1a 394 * @{
NYX 0:85b3fd62ea1a 395 */
NYX 0:85b3fd62ea1a 396 #define FSMC_PAGE_SIZE_NONE 0x00000000U
NYX 0:85b3fd62ea1a 397 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
NYX 0:85b3fd62ea1a 398 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
NYX 0:85b3fd62ea1a 399 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
NYX 0:85b3fd62ea1a 400 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
NYX 0:85b3fd62ea1a 401 /**
NYX 0:85b3fd62ea1a 402 * @}
NYX 0:85b3fd62ea1a 403 */
NYX 0:85b3fd62ea1a 404
NYX 0:85b3fd62ea1a 405 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO
NYX 0:85b3fd62ea1a 406 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
NYX 0:85b3fd62ea1a 407 * @{
NYX 0:85b3fd62ea1a 408 */
NYX 0:85b3fd62ea1a 409 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
NYX 0:85b3fd62ea1a 410 #define FSMC_WRITE_FIFO_ENABLE 0x00000000U
NYX 0:85b3fd62ea1a 411 /**
NYX 0:85b3fd62ea1a 412 * @}
NYX 0:85b3fd62ea1a 413 */
NYX 0:85b3fd62ea1a 414
NYX 0:85b3fd62ea1a 415 /** @defgroup FSMC_Write_Burst FSMC Write Burst
NYX 0:85b3fd62ea1a 416 * @{
NYX 0:85b3fd62ea1a 417 */
NYX 0:85b3fd62ea1a 418 #define FSMC_WRITE_BURST_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 419 #define FSMC_WRITE_BURST_ENABLE 0x00080000U
NYX 0:85b3fd62ea1a 420 /**
NYX 0:85b3fd62ea1a 421 * @}
NYX 0:85b3fd62ea1a 422 */
NYX 0:85b3fd62ea1a 423
NYX 0:85b3fd62ea1a 424 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
NYX 0:85b3fd62ea1a 425 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
NYX 0:85b3fd62ea1a 426 * @{
NYX 0:85b3fd62ea1a 427 */
NYX 0:85b3fd62ea1a 428 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
NYX 0:85b3fd62ea1a 429 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
NYX 0:85b3fd62ea1a 430 /**
NYX 0:85b3fd62ea1a 431 * @}
NYX 0:85b3fd62ea1a 432 */
NYX 0:85b3fd62ea1a 433
NYX 0:85b3fd62ea1a 434 /** @defgroup FSMC_Access_Mode FSMC Access Mode
NYX 0:85b3fd62ea1a 435 * @{
NYX 0:85b3fd62ea1a 436 */
NYX 0:85b3fd62ea1a 437 #define FSMC_ACCESS_MODE_A 0x00000000U
NYX 0:85b3fd62ea1a 438 #define FSMC_ACCESS_MODE_B 0x10000000U
NYX 0:85b3fd62ea1a 439 #define FSMC_ACCESS_MODE_C 0x20000000U
NYX 0:85b3fd62ea1a 440 #define FSMC_ACCESS_MODE_D 0x30000000U
NYX 0:85b3fd62ea1a 441 /**
NYX 0:85b3fd62ea1a 442 * @}
NYX 0:85b3fd62ea1a 443 */
NYX 0:85b3fd62ea1a 444 /**
NYX 0:85b3fd62ea1a 445 * @}
NYX 0:85b3fd62ea1a 446 */
NYX 0:85b3fd62ea1a 447
NYX 0:85b3fd62ea1a 448 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 449 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
NYX 0:85b3fd62ea1a 450 * @{
NYX 0:85b3fd62ea1a 451 */
NYX 0:85b3fd62ea1a 452 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
NYX 0:85b3fd62ea1a 453 * @{
NYX 0:85b3fd62ea1a 454 */
NYX 0:85b3fd62ea1a 455 #define FSMC_NAND_BANK2 0x00000010U
NYX 0:85b3fd62ea1a 456 #define FSMC_NAND_BANK3 0x00000100U
NYX 0:85b3fd62ea1a 457 /**
NYX 0:85b3fd62ea1a 458 * @}
NYX 0:85b3fd62ea1a 459 */
NYX 0:85b3fd62ea1a 460
NYX 0:85b3fd62ea1a 461 /** @defgroup FSMC_Wait_feature FSMC Wait feature
NYX 0:85b3fd62ea1a 462 * @{
NYX 0:85b3fd62ea1a 463 */
NYX 0:85b3fd62ea1a 464 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 465 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
NYX 0:85b3fd62ea1a 466 /**
NYX 0:85b3fd62ea1a 467 * @}
NYX 0:85b3fd62ea1a 468 */
NYX 0:85b3fd62ea1a 469
NYX 0:85b3fd62ea1a 470 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
NYX 0:85b3fd62ea1a 471 * @{
NYX 0:85b3fd62ea1a 472 */
NYX 0:85b3fd62ea1a 473 #define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
NYX 0:85b3fd62ea1a 474 #define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
NYX 0:85b3fd62ea1a 475 /**
NYX 0:85b3fd62ea1a 476 * @}
NYX 0:85b3fd62ea1a 477 */
NYX 0:85b3fd62ea1a 478
NYX 0:85b3fd62ea1a 479 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
NYX 0:85b3fd62ea1a 480 * @{
NYX 0:85b3fd62ea1a 481 */
NYX 0:85b3fd62ea1a 482 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
NYX 0:85b3fd62ea1a 483 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
NYX 0:85b3fd62ea1a 484 /**
NYX 0:85b3fd62ea1a 485 * @}
NYX 0:85b3fd62ea1a 486 */
NYX 0:85b3fd62ea1a 487
NYX 0:85b3fd62ea1a 488 /** @defgroup FSMC_ECC FSMC ECC
NYX 0:85b3fd62ea1a 489 * @{
NYX 0:85b3fd62ea1a 490 */
NYX 0:85b3fd62ea1a 491 #define FSMC_NAND_ECC_DISABLE 0x00000000U
NYX 0:85b3fd62ea1a 492 #define FSMC_NAND_ECC_ENABLE 0x00000040U
NYX 0:85b3fd62ea1a 493 /**
NYX 0:85b3fd62ea1a 494 * @}
NYX 0:85b3fd62ea1a 495 */
NYX 0:85b3fd62ea1a 496
NYX 0:85b3fd62ea1a 497 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
NYX 0:85b3fd62ea1a 498 * @{
NYX 0:85b3fd62ea1a 499 */
NYX 0:85b3fd62ea1a 500 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
NYX 0:85b3fd62ea1a 501 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
NYX 0:85b3fd62ea1a 502 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
NYX 0:85b3fd62ea1a 503 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
NYX 0:85b3fd62ea1a 504 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
NYX 0:85b3fd62ea1a 505 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
NYX 0:85b3fd62ea1a 506 /**
NYX 0:85b3fd62ea1a 507 * @}
NYX 0:85b3fd62ea1a 508 */
NYX 0:85b3fd62ea1a 509 /**
NYX 0:85b3fd62ea1a 510 * @}
NYX 0:85b3fd62ea1a 511 */
NYX 0:85b3fd62ea1a 512 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 513
NYX 0:85b3fd62ea1a 514 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
NYX 0:85b3fd62ea1a 515 * @{
NYX 0:85b3fd62ea1a 516 */
NYX 0:85b3fd62ea1a 517 #define FSMC_IT_RISING_EDGE 0x00000008U
NYX 0:85b3fd62ea1a 518 #define FSMC_IT_LEVEL 0x00000010U
NYX 0:85b3fd62ea1a 519 #define FSMC_IT_FALLING_EDGE 0x00000020U
NYX 0:85b3fd62ea1a 520 #define FSMC_IT_REFRESH_ERROR 0x00004000U
NYX 0:85b3fd62ea1a 521 /**
NYX 0:85b3fd62ea1a 522 * @}
NYX 0:85b3fd62ea1a 523 */
NYX 0:85b3fd62ea1a 524
NYX 0:85b3fd62ea1a 525 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
NYX 0:85b3fd62ea1a 526 * @{
NYX 0:85b3fd62ea1a 527 */
NYX 0:85b3fd62ea1a 528 #define FSMC_FLAG_RISING_EDGE 0x00000001U
NYX 0:85b3fd62ea1a 529 #define FSMC_FLAG_LEVEL 0x00000002U
NYX 0:85b3fd62ea1a 530 #define FSMC_FLAG_FALLING_EDGE 0x00000004U
NYX 0:85b3fd62ea1a 531 #define FSMC_FLAG_FEMPT 0x00000040U
NYX 0:85b3fd62ea1a 532 /**
NYX 0:85b3fd62ea1a 533 * @}
NYX 0:85b3fd62ea1a 534 */
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
NYX 0:85b3fd62ea1a 537 * @{
NYX 0:85b3fd62ea1a 538 */
NYX 0:85b3fd62ea1a 539 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
NYX 0:85b3fd62ea1a 540 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
NYX 0:85b3fd62ea1a 541 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 542 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
NYX 0:85b3fd62ea1a 543 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
NYX 0:85b3fd62ea1a 544 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 545
NYX 0:85b3fd62ea1a 546 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
NYX 0:85b3fd62ea1a 547 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
NYX 0:85b3fd62ea1a 548 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 549 #define FSMC_NAND_DEVICE FSMC_Bank2_3
NYX 0:85b3fd62ea1a 550 #define FSMC_PCCARD_DEVICE FSMC_Bank4
NYX 0:85b3fd62ea1a 551 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 552
NYX 0:85b3fd62ea1a 553 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
NYX 0:85b3fd62ea1a 554 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
NYX 0:85b3fd62ea1a 555 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
NYX 0:85b3fd62ea1a 556
NYX 0:85b3fd62ea1a 557 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
NYX 0:85b3fd62ea1a 558 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
NYX 0:85b3fd62ea1a 559 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
NYX 0:85b3fd62ea1a 560 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
NYX 0:85b3fd62ea1a 561
NYX 0:85b3fd62ea1a 562 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
NYX 0:85b3fd62ea1a 563 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
NYX 0:85b3fd62ea1a 564 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
NYX 0:85b3fd62ea1a 565 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
NYX 0:85b3fd62ea1a 566 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
NYX 0:85b3fd62ea1a 567 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
NYX 0:85b3fd62ea1a 568
NYX 0:85b3fd62ea1a 569 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
NYX 0:85b3fd62ea1a 570 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
NYX 0:85b3fd62ea1a 571
NYX 0:85b3fd62ea1a 572 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 573 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
NYX 0:85b3fd62ea1a 574 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
NYX 0:85b3fd62ea1a 575 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 576
NYX 0:85b3fd62ea1a 577 #define FMC_NAND_Init FSMC_NAND_Init
NYX 0:85b3fd62ea1a 578 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
NYX 0:85b3fd62ea1a 579 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
NYX 0:85b3fd62ea1a 580 #define FMC_NAND_DeInit FSMC_NAND_DeInit
NYX 0:85b3fd62ea1a 581 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
NYX 0:85b3fd62ea1a 582 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
NYX 0:85b3fd62ea1a 583 #define FMC_NAND_GetECC FSMC_NAND_GetECC
NYX 0:85b3fd62ea1a 584 #define FMC_PCCARD_Init FSMC_PCCARD_Init
NYX 0:85b3fd62ea1a 585 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
NYX 0:85b3fd62ea1a 586 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
NYX 0:85b3fd62ea1a 587 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
NYX 0:85b3fd62ea1a 588 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
NYX 0:85b3fd62ea1a 589
NYX 0:85b3fd62ea1a 590 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
NYX 0:85b3fd62ea1a 591 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
NYX 0:85b3fd62ea1a 592 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
NYX 0:85b3fd62ea1a 593 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
NYX 0:85b3fd62ea1a 594 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
NYX 0:85b3fd62ea1a 595 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
NYX 0:85b3fd62ea1a 596 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
NYX 0:85b3fd62ea1a 597 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
NYX 0:85b3fd62ea1a 598 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
NYX 0:85b3fd62ea1a 599 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
NYX 0:85b3fd62ea1a 600 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
NYX 0:85b3fd62ea1a 601 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
NYX 0:85b3fd62ea1a 602 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 603
NYX 0:85b3fd62ea1a 604 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
NYX 0:85b3fd62ea1a 605 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
NYX 0:85b3fd62ea1a 606 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 607 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
NYX 0:85b3fd62ea1a 608 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
NYX 0:85b3fd62ea1a 609 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 610
NYX 0:85b3fd62ea1a 611 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
NYX 0:85b3fd62ea1a 612 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
NYX 0:85b3fd62ea1a 613 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 614 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
NYX 0:85b3fd62ea1a 615 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
NYX 0:85b3fd62ea1a 616
NYX 0:85b3fd62ea1a 617 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
NYX 0:85b3fd62ea1a 618 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 619
NYX 0:85b3fd62ea1a 620 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
NYX 0:85b3fd62ea1a 621 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
NYX 0:85b3fd62ea1a 622 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
NYX 0:85b3fd62ea1a 623
NYX 0:85b3fd62ea1a 624 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
NYX 0:85b3fd62ea1a 625 #define FMC_IT_LEVEL FSMC_IT_LEVEL
NYX 0:85b3fd62ea1a 626 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
NYX 0:85b3fd62ea1a 627 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
NYX 0:85b3fd62ea1a 628
NYX 0:85b3fd62ea1a 629 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
NYX 0:85b3fd62ea1a 630 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
NYX 0:85b3fd62ea1a 631 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
NYX 0:85b3fd62ea1a 632 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
NYX 0:85b3fd62ea1a 633 /**
NYX 0:85b3fd62ea1a 634 * @}
NYX 0:85b3fd62ea1a 635 */
NYX 0:85b3fd62ea1a 636
NYX 0:85b3fd62ea1a 637 /**
NYX 0:85b3fd62ea1a 638 * @}
NYX 0:85b3fd62ea1a 639 */
NYX 0:85b3fd62ea1a 640
NYX 0:85b3fd62ea1a 641 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 642 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
NYX 0:85b3fd62ea1a 643 * @{
NYX 0:85b3fd62ea1a 644 */
NYX 0:85b3fd62ea1a 645
NYX 0:85b3fd62ea1a 646 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
NYX 0:85b3fd62ea1a 647 * @brief macros to handle NOR device enable/disable and read/write operations
NYX 0:85b3fd62ea1a 648 * @{
NYX 0:85b3fd62ea1a 649 */
NYX 0:85b3fd62ea1a 650 /**
NYX 0:85b3fd62ea1a 651 * @brief Enable the NORSRAM device access.
NYX 0:85b3fd62ea1a 652 * @param __INSTANCE__: FSMC_NORSRAM Instance
NYX 0:85b3fd62ea1a 653 * @param __BANK__: FSMC_NORSRAM Bank
NYX 0:85b3fd62ea1a 654 * @retval none
NYX 0:85b3fd62ea1a 655 */
NYX 0:85b3fd62ea1a 656 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
NYX 0:85b3fd62ea1a 657
NYX 0:85b3fd62ea1a 658 /**
NYX 0:85b3fd62ea1a 659 * @brief Disable the NORSRAM device access.
NYX 0:85b3fd62ea1a 660 * @param __INSTANCE__: FSMC_NORSRAM Instance
NYX 0:85b3fd62ea1a 661 * @param __BANK__: FSMC_NORSRAM Bank
NYX 0:85b3fd62ea1a 662 * @retval none
NYX 0:85b3fd62ea1a 663 */
NYX 0:85b3fd62ea1a 664 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
NYX 0:85b3fd62ea1a 665 /**
NYX 0:85b3fd62ea1a 666 * @}
NYX 0:85b3fd62ea1a 667 */
NYX 0:85b3fd62ea1a 668
NYX 0:85b3fd62ea1a 669 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
NYX 0:85b3fd62ea1a 670 * @brief macros to handle NAND device enable/disable
NYX 0:85b3fd62ea1a 671 * @{
NYX 0:85b3fd62ea1a 672 */
NYX 0:85b3fd62ea1a 673 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 674 /**
NYX 0:85b3fd62ea1a 675 * @brief Enable the NAND device access.
NYX 0:85b3fd62ea1a 676 * @param __INSTANCE__: FSMC_NAND Instance
NYX 0:85b3fd62ea1a 677 * @param __BANK__: FSMC_NAND Bank
NYX 0:85b3fd62ea1a 678 * @retval none
NYX 0:85b3fd62ea1a 679 */
NYX 0:85b3fd62ea1a 680 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
NYX 0:85b3fd62ea1a 681 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
NYX 0:85b3fd62ea1a 682
NYX 0:85b3fd62ea1a 683 /**
NYX 0:85b3fd62ea1a 684 * @brief Disable the NAND device access.
NYX 0:85b3fd62ea1a 685 * @param __INSTANCE__: FSMC_NAND Instance
NYX 0:85b3fd62ea1a 686 * @param __BANK__: FSMC_NAND Bank
NYX 0:85b3fd62ea1a 687 * @retval none
NYX 0:85b3fd62ea1a 688 */
NYX 0:85b3fd62ea1a 689 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
NYX 0:85b3fd62ea1a 690 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
NYX 0:85b3fd62ea1a 691 /**
NYX 0:85b3fd62ea1a 692 * @}
NYX 0:85b3fd62ea1a 693 */
NYX 0:85b3fd62ea1a 694
NYX 0:85b3fd62ea1a 695 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
NYX 0:85b3fd62ea1a 696 * @brief macros to handle SRAM read/write operations
NYX 0:85b3fd62ea1a 697 * @{
NYX 0:85b3fd62ea1a 698 */
NYX 0:85b3fd62ea1a 699 /**
NYX 0:85b3fd62ea1a 700 * @brief Enable the PCCARD device access.
NYX 0:85b3fd62ea1a 701 * @param __INSTANCE__: FSMC_PCCARD Instance
NYX 0:85b3fd62ea1a 702 * @retval none
NYX 0:85b3fd62ea1a 703 */
NYX 0:85b3fd62ea1a 704 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
NYX 0:85b3fd62ea1a 705
NYX 0:85b3fd62ea1a 706 /**
NYX 0:85b3fd62ea1a 707 * @brief Disable the PCCARD device access.
NYX 0:85b3fd62ea1a 708 * @param __INSTANCE__: FSMC_PCCARD Instance
NYX 0:85b3fd62ea1a 709 * @retval none
NYX 0:85b3fd62ea1a 710 */
NYX 0:85b3fd62ea1a 711 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
NYX 0:85b3fd62ea1a 712 /**
NYX 0:85b3fd62ea1a 713 * @}
NYX 0:85b3fd62ea1a 714 */
NYX 0:85b3fd62ea1a 715
NYX 0:85b3fd62ea1a 716 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
NYX 0:85b3fd62ea1a 717 * @brief macros to handle FSMC flags and interrupts
NYX 0:85b3fd62ea1a 718 * @{
NYX 0:85b3fd62ea1a 719 */
NYX 0:85b3fd62ea1a 720 /**
NYX 0:85b3fd62ea1a 721 * @brief Enable the NAND device interrupt.
NYX 0:85b3fd62ea1a 722 * @param __INSTANCE__: FSMC_NAND Instance
NYX 0:85b3fd62ea1a 723 * @param __BANK__: FSMC_NAND Bank
NYX 0:85b3fd62ea1a 724 * @param __INTERRUPT__: FSMC_NAND interrupt
NYX 0:85b3fd62ea1a 725 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 726 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
NYX 0:85b3fd62ea1a 727 * @arg FSMC_IT_LEVEL: Interrupt level.
NYX 0:85b3fd62ea1a 728 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX 0:85b3fd62ea1a 729 * @retval None
NYX 0:85b3fd62ea1a 730 */
NYX 0:85b3fd62ea1a 731 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
NYX 0:85b3fd62ea1a 732 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
NYX 0:85b3fd62ea1a 733
NYX 0:85b3fd62ea1a 734 /**
NYX 0:85b3fd62ea1a 735 * @brief Disable the NAND device interrupt.
NYX 0:85b3fd62ea1a 736 * @param __INSTANCE__: FSMC_NAND Instance
NYX 0:85b3fd62ea1a 737 * @param __BANK__: FSMC_NAND Bank
NYX 0:85b3fd62ea1a 738 * @param __INTERRUPT__: FSMC_NAND interrupt
NYX 0:85b3fd62ea1a 739 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 740 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
NYX 0:85b3fd62ea1a 741 * @arg FSMC_IT_LEVEL: Interrupt level.
NYX 0:85b3fd62ea1a 742 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX 0:85b3fd62ea1a 743 * @retval None
NYX 0:85b3fd62ea1a 744 */
NYX 0:85b3fd62ea1a 745 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
NYX 0:85b3fd62ea1a 746 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
NYX 0:85b3fd62ea1a 747
NYX 0:85b3fd62ea1a 748 /**
NYX 0:85b3fd62ea1a 749 * @brief Get flag status of the NAND device.
NYX 0:85b3fd62ea1a 750 * @param __INSTANCE__: FSMC_NAND Instance
NYX 0:85b3fd62ea1a 751 * @param __BANK__ : FSMC_NAND Bank
NYX 0:85b3fd62ea1a 752 * @param __FLAG__ : FSMC_NAND flag
NYX 0:85b3fd62ea1a 753 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 754 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX 0:85b3fd62ea1a 755 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
NYX 0:85b3fd62ea1a 756 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX 0:85b3fd62ea1a 757 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
NYX 0:85b3fd62ea1a 758 * @retval The state of FLAG (SET or RESET).
NYX 0:85b3fd62ea1a 759 */
NYX 0:85b3fd62ea1a 760 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
NYX 0:85b3fd62ea1a 761 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
NYX 0:85b3fd62ea1a 762
NYX 0:85b3fd62ea1a 763 /**
NYX 0:85b3fd62ea1a 764 * @brief Clear flag status of the NAND device.
NYX 0:85b3fd62ea1a 765 * @param __INSTANCE__: FSMC_NAND Instance
NYX 0:85b3fd62ea1a 766 * @param __BANK__: FSMC_NAND Bank
NYX 0:85b3fd62ea1a 767 * @param __FLAG__: FSMC_NAND flag
NYX 0:85b3fd62ea1a 768 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 769 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX 0:85b3fd62ea1a 770 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
NYX 0:85b3fd62ea1a 771 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX 0:85b3fd62ea1a 772 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
NYX 0:85b3fd62ea1a 773 * @retval None
NYX 0:85b3fd62ea1a 774 */
NYX 0:85b3fd62ea1a 775 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
NYX 0:85b3fd62ea1a 776 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
NYX 0:85b3fd62ea1a 777
NYX 0:85b3fd62ea1a 778 /**
NYX 0:85b3fd62ea1a 779 * @brief Enable the PCCARD device interrupt.
NYX 0:85b3fd62ea1a 780 * @param __INSTANCE__: FSMC_PCCARD Instance
NYX 0:85b3fd62ea1a 781 * @param __INTERRUPT__: FSMC_PCCARD interrupt
NYX 0:85b3fd62ea1a 782 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 783 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
NYX 0:85b3fd62ea1a 784 * @arg FSMC_IT_LEVEL: Interrupt level.
NYX 0:85b3fd62ea1a 785 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX 0:85b3fd62ea1a 786 * @retval None
NYX 0:85b3fd62ea1a 787 */
NYX 0:85b3fd62ea1a 788 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
NYX 0:85b3fd62ea1a 789
NYX 0:85b3fd62ea1a 790 /**
NYX 0:85b3fd62ea1a 791 * @brief Disable the PCCARD device interrupt.
NYX 0:85b3fd62ea1a 792 * @param __INSTANCE__: FSMC_PCCARD Instance
NYX 0:85b3fd62ea1a 793 * @param __INTERRUPT__: FSMC_PCCARD interrupt
NYX 0:85b3fd62ea1a 794 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 795 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
NYX 0:85b3fd62ea1a 796 * @arg FSMC_IT_LEVEL: Interrupt level.
NYX 0:85b3fd62ea1a 797 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX 0:85b3fd62ea1a 798 * @retval None
NYX 0:85b3fd62ea1a 799 */
NYX 0:85b3fd62ea1a 800 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
NYX 0:85b3fd62ea1a 801
NYX 0:85b3fd62ea1a 802 /**
NYX 0:85b3fd62ea1a 803 * @brief Get flag status of the PCCARD device.
NYX 0:85b3fd62ea1a 804 * @param __INSTANCE__: FSMC_PCCARD Instance
NYX 0:85b3fd62ea1a 805 * @param __FLAG__: FSMC_PCCARD flag
NYX 0:85b3fd62ea1a 806 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 807 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX 0:85b3fd62ea1a 808 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
NYX 0:85b3fd62ea1a 809 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX 0:85b3fd62ea1a 810 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
NYX 0:85b3fd62ea1a 811 * @retval The state of FLAG (SET or RESET).
NYX 0:85b3fd62ea1a 812 */
NYX 0:85b3fd62ea1a 813 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
NYX 0:85b3fd62ea1a 814
NYX 0:85b3fd62ea1a 815 /**
NYX 0:85b3fd62ea1a 816 * @brief Clear flag status of the PCCARD device.
NYX 0:85b3fd62ea1a 817 * @param __INSTANCE__: FSMC_PCCARD Instance
NYX 0:85b3fd62ea1a 818 * @param __FLAG__: FSMC_PCCARD flag
NYX 0:85b3fd62ea1a 819 * This parameter can be any combination of the following values:
NYX 0:85b3fd62ea1a 820 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX 0:85b3fd62ea1a 821 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
NYX 0:85b3fd62ea1a 822 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX 0:85b3fd62ea1a 823 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
NYX 0:85b3fd62ea1a 824 * @retval None
NYX 0:85b3fd62ea1a 825 */
NYX 0:85b3fd62ea1a 826 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
NYX 0:85b3fd62ea1a 827 /**
NYX 0:85b3fd62ea1a 828 * @}
NYX 0:85b3fd62ea1a 829 */
NYX 0:85b3fd62ea1a 830 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 831
NYX 0:85b3fd62ea1a 832 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
NYX 0:85b3fd62ea1a 833 * @{
NYX 0:85b3fd62ea1a 834 */
NYX 0:85b3fd62ea1a 835 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
NYX 0:85b3fd62ea1a 836 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
NYX 0:85b3fd62ea1a 837 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
NYX 0:85b3fd62ea1a 838 ((__BANK__) == FSMC_NORSRAM_BANK4))
NYX 0:85b3fd62ea1a 839
NYX 0:85b3fd62ea1a 840 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
NYX 0:85b3fd62ea1a 841 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
NYX 0:85b3fd62ea1a 842
NYX 0:85b3fd62ea1a 843 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
NYX 0:85b3fd62ea1a 844 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
NYX 0:85b3fd62ea1a 845 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
NYX 0:85b3fd62ea1a 846
NYX 0:85b3fd62ea1a 847 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
NYX 0:85b3fd62ea1a 848 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
NYX 0:85b3fd62ea1a 849 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
NYX 0:85b3fd62ea1a 850
NYX 0:85b3fd62ea1a 851 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
NYX 0:85b3fd62ea1a 852 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
NYX 0:85b3fd62ea1a 853 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
NYX 0:85b3fd62ea1a 854 ((__MODE__) == FSMC_ACCESS_MODE_D))
NYX 0:85b3fd62ea1a 855
NYX 0:85b3fd62ea1a 856 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
NYX 0:85b3fd62ea1a 857 ((BANK) == FSMC_NAND_BANK3))
NYX 0:85b3fd62ea1a 858
NYX 0:85b3fd62ea1a 859 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
NYX 0:85b3fd62ea1a 860 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
NYX 0:85b3fd62ea1a 861
NYX 0:85b3fd62ea1a 862 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
NYX 0:85b3fd62ea1a 863 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
NYX 0:85b3fd62ea1a 864
NYX 0:85b3fd62ea1a 865 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
NYX 0:85b3fd62ea1a 866 ((STATE) == FSMC_NAND_ECC_ENABLE))
NYX 0:85b3fd62ea1a 867
NYX 0:85b3fd62ea1a 868 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
NYX 0:85b3fd62ea1a 869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
NYX 0:85b3fd62ea1a 870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
NYX 0:85b3fd62ea1a 871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
NYX 0:85b3fd62ea1a 872 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
NYX 0:85b3fd62ea1a 873 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
NYX 0:85b3fd62ea1a 874
NYX 0:85b3fd62ea1a 875 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
NYX 0:85b3fd62ea1a 876
NYX 0:85b3fd62ea1a 877 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
NYX 0:85b3fd62ea1a 878
NYX 0:85b3fd62ea1a 879 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
NYX 0:85b3fd62ea1a 880
NYX 0:85b3fd62ea1a 881 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
NYX 0:85b3fd62ea1a 882
NYX 0:85b3fd62ea1a 883 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
NYX 0:85b3fd62ea1a 884
NYX 0:85b3fd62ea1a 885 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
NYX 0:85b3fd62ea1a 886
NYX 0:85b3fd62ea1a 887 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
NYX 0:85b3fd62ea1a 888
NYX 0:85b3fd62ea1a 889 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
NYX 0:85b3fd62ea1a 890
NYX 0:85b3fd62ea1a 891 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
NYX 0:85b3fd62ea1a 892
NYX 0:85b3fd62ea1a 893 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
NYX 0:85b3fd62ea1a 894
NYX 0:85b3fd62ea1a 895 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
NYX 0:85b3fd62ea1a 896 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
NYX 0:85b3fd62ea1a 897
NYX 0:85b3fd62ea1a 898 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
NYX 0:85b3fd62ea1a 899 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
NYX 0:85b3fd62ea1a 900
NYX 0:85b3fd62ea1a 901 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
NYX 0:85b3fd62ea1a 902 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
NYX 0:85b3fd62ea1a 903
NYX 0:85b3fd62ea1a 904 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
NYX 0:85b3fd62ea1a 905 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
NYX 0:85b3fd62ea1a 906
NYX 0:85b3fd62ea1a 907 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
NYX 0:85b3fd62ea1a 908 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
NYX 0:85b3fd62ea1a 909
NYX 0:85b3fd62ea1a 910 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
NYX 0:85b3fd62ea1a 911 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
NYX 0:85b3fd62ea1a 912
NYX 0:85b3fd62ea1a 913 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
NYX 0:85b3fd62ea1a 914 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
NYX 0:85b3fd62ea1a 915
NYX 0:85b3fd62ea1a 916 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
NYX 0:85b3fd62ea1a 917 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
NYX 0:85b3fd62ea1a 918
NYX 0:85b3fd62ea1a 919 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
NYX 0:85b3fd62ea1a 920
NYX 0:85b3fd62ea1a 921 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
NYX 0:85b3fd62ea1a 922 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
NYX 0:85b3fd62ea1a 923
NYX 0:85b3fd62ea1a 924 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
NYX 0:85b3fd62ea1a 925
NYX 0:85b3fd62ea1a 926 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
NYX 0:85b3fd62ea1a 927
NYX 0:85b3fd62ea1a 928 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
NYX 0:85b3fd62ea1a 929
NYX 0:85b3fd62ea1a 930 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
NYX 0:85b3fd62ea1a 931
NYX 0:85b3fd62ea1a 932 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
NYX 0:85b3fd62ea1a 933 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
NYX 0:85b3fd62ea1a 934
NYX 0:85b3fd62ea1a 935 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
NYX 0:85b3fd62ea1a 936
NYX 0:85b3fd62ea1a 937 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
NYX 0:85b3fd62ea1a 938 ((SIZE) == FSMC_PAGE_SIZE_128) || \
NYX 0:85b3fd62ea1a 939 ((SIZE) == FSMC_PAGE_SIZE_256) || \
NYX 0:85b3fd62ea1a 940 ((SIZE) == FSMC_PAGE_SIZE_512) || \
NYX 0:85b3fd62ea1a 941 ((SIZE) == FSMC_PAGE_SIZE_1024))
NYX 0:85b3fd62ea1a 942
NYX 0:85b3fd62ea1a 943 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
NYX 0:85b3fd62ea1a 944 ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
NYX 0:85b3fd62ea1a 945
NYX 0:85b3fd62ea1a 946 /**
NYX 0:85b3fd62ea1a 947 * @}
NYX 0:85b3fd62ea1a 948 */
NYX 0:85b3fd62ea1a 949 /**
NYX 0:85b3fd62ea1a 950 * @}
NYX 0:85b3fd62ea1a 951 */
NYX 0:85b3fd62ea1a 952
NYX 0:85b3fd62ea1a 953 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 954 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
NYX 0:85b3fd62ea1a 955 * @{
NYX 0:85b3fd62ea1a 956 */
NYX 0:85b3fd62ea1a 957
NYX 0:85b3fd62ea1a 958 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
NYX 0:85b3fd62ea1a 959 * @{
NYX 0:85b3fd62ea1a 960 */
NYX 0:85b3fd62ea1a 961
NYX 0:85b3fd62ea1a 962 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
NYX 0:85b3fd62ea1a 963 * @{
NYX 0:85b3fd62ea1a 964 */
NYX 0:85b3fd62ea1a 965 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
NYX 0:85b3fd62ea1a 966 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
NYX 0:85b3fd62ea1a 967 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
NYX 0:85b3fd62ea1a 968 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
NYX 0:85b3fd62ea1a 969 /**
NYX 0:85b3fd62ea1a 970 * @}
NYX 0:85b3fd62ea1a 971 */
NYX 0:85b3fd62ea1a 972
NYX 0:85b3fd62ea1a 973 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
NYX 0:85b3fd62ea1a 974 * @{
NYX 0:85b3fd62ea1a 975 */
NYX 0:85b3fd62ea1a 976 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
NYX 0:85b3fd62ea1a 977 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
NYX 0:85b3fd62ea1a 978 /**
NYX 0:85b3fd62ea1a 979 * @}
NYX 0:85b3fd62ea1a 980 */
NYX 0:85b3fd62ea1a 981 /**
NYX 0:85b3fd62ea1a 982 * @}
NYX 0:85b3fd62ea1a 983 */
NYX 0:85b3fd62ea1a 984
NYX 0:85b3fd62ea1a 985 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 986 /** @defgroup FSMC_LL_NAND NAND
NYX 0:85b3fd62ea1a 987 * @{
NYX 0:85b3fd62ea1a 988 */
NYX 0:85b3fd62ea1a 989 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
NYX 0:85b3fd62ea1a 990 * @{
NYX 0:85b3fd62ea1a 991 */
NYX 0:85b3fd62ea1a 992 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
NYX 0:85b3fd62ea1a 993 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
NYX 0:85b3fd62ea1a 994 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
NYX 0:85b3fd62ea1a 995 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
NYX 0:85b3fd62ea1a 996 /**
NYX 0:85b3fd62ea1a 997 * @}
NYX 0:85b3fd62ea1a 998 */
NYX 0:85b3fd62ea1a 999
NYX 0:85b3fd62ea1a 1000 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
NYX 0:85b3fd62ea1a 1001 * @{
NYX 0:85b3fd62ea1a 1002 */
NYX 0:85b3fd62ea1a 1003 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
NYX 0:85b3fd62ea1a 1004 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
NYX 0:85b3fd62ea1a 1005 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
NYX 0:85b3fd62ea1a 1006 /**
NYX 0:85b3fd62ea1a 1007 * @}
NYX 0:85b3fd62ea1a 1008 */
NYX 0:85b3fd62ea1a 1009 /**
NYX 0:85b3fd62ea1a 1010 * @}
NYX 0:85b3fd62ea1a 1011 */
NYX 0:85b3fd62ea1a 1012
NYX 0:85b3fd62ea1a 1013 /** @defgroup FSMC_LL_PCCARD PCCARD
NYX 0:85b3fd62ea1a 1014 * @{
NYX 0:85b3fd62ea1a 1015 */
NYX 0:85b3fd62ea1a 1016 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
NYX 0:85b3fd62ea1a 1017 * @{
NYX 0:85b3fd62ea1a 1018 */
NYX 0:85b3fd62ea1a 1019 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
NYX 0:85b3fd62ea1a 1020 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
NYX 0:85b3fd62ea1a 1021 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
NYX 0:85b3fd62ea1a 1022 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
NYX 0:85b3fd62ea1a 1023 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
NYX 0:85b3fd62ea1a 1024 /**
NYX 0:85b3fd62ea1a 1025 * @}
NYX 0:85b3fd62ea1a 1026 */
NYX 0:85b3fd62ea1a 1027 /**
NYX 0:85b3fd62ea1a 1028 * @}
NYX 0:85b3fd62ea1a 1029 */
NYX 0:85b3fd62ea1a 1030 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 1031
NYX 0:85b3fd62ea1a 1032 /**
NYX 0:85b3fd62ea1a 1033 * @}
NYX 0:85b3fd62ea1a 1034 */
NYX 0:85b3fd62ea1a 1035 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 1036
NYX 0:85b3fd62ea1a 1037 /**
NYX 0:85b3fd62ea1a 1038 * @}
NYX 0:85b3fd62ea1a 1039 */
NYX 0:85b3fd62ea1a 1040
NYX 0:85b3fd62ea1a 1041 /**
NYX 0:85b3fd62ea1a 1042 * @}
NYX 0:85b3fd62ea1a 1043 */
NYX 0:85b3fd62ea1a 1044
NYX 0:85b3fd62ea1a 1045 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 1046 }
NYX 0:85b3fd62ea1a 1047 #endif
NYX 0:85b3fd62ea1a 1048
NYX 0:85b3fd62ea1a 1049 #endif /* __STM32F4xx_LL_FSMC_H */
NYX 0:85b3fd62ea1a 1050
NYX 0:85b3fd62ea1a 1051 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/