Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_fsmc.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief FSMC Low Layer HAL module driver.
NYX 0:85b3fd62ea1a 8 *
NYX 0:85b3fd62ea1a 9 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
NYX 0:85b3fd62ea1a 11 * + Initialization/de-initialization functions
NYX 0:85b3fd62ea1a 12 * + Peripheral Control functions
NYX 0:85b3fd62ea1a 13 * + Peripheral State functions
NYX 0:85b3fd62ea1a 14 *
NYX 0:85b3fd62ea1a 15 @verbatim
NYX 0:85b3fd62ea1a 16 ==============================================================================
NYX 0:85b3fd62ea1a 17 ##### FSMC peripheral features #####
NYX 0:85b3fd62ea1a 18 ==============================================================================
NYX 0:85b3fd62ea1a 19 [..] The Flexible static memory controller (FSMC) includes two memory controllers:
NYX 0:85b3fd62ea1a 20 (+) The NOR/PSRAM memory controller
NYX 0:85b3fd62ea1a 21 (+) The NAND/PC Card memory controller
NYX 0:85b3fd62ea1a 22
NYX 0:85b3fd62ea1a 23 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
NYX 0:85b3fd62ea1a 24 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
NYX 0:85b3fd62ea1a 25 (+) to translate AHB transactions into the appropriate external device protocol.
NYX 0:85b3fd62ea1a 26 (+) to meet the access time requirements of the external memory devices.
NYX 0:85b3fd62ea1a 27
NYX 0:85b3fd62ea1a 28 [..] All external memories share the addresses, data and control signals with the controller.
NYX 0:85b3fd62ea1a 29 Each external device is accessed by means of a unique Chip Select. The FSMC performs
NYX 0:85b3fd62ea1a 30 only one access at a time to an external device.
NYX 0:85b3fd62ea1a 31 The main features of the FSMC controller are the following:
NYX 0:85b3fd62ea1a 32 (+) Interface with static-memory mapped devices including:
NYX 0:85b3fd62ea1a 33 (++) Static random access memory (SRAM).
NYX 0:85b3fd62ea1a 34 (++) Read-only memory (ROM).
NYX 0:85b3fd62ea1a 35 (++) NOR Flash memory/OneNAND Flash memory.
NYX 0:85b3fd62ea1a 36 (++) PSRAM (4 memory banks).
NYX 0:85b3fd62ea1a 37 (++) 16-bit PC Card compatible devices.
NYX 0:85b3fd62ea1a 38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
NYX 0:85b3fd62ea1a 39 data.
NYX 0:85b3fd62ea1a 40 (+) Independent Chip Select control for each memory bank.
NYX 0:85b3fd62ea1a 41 (+) Independent configuration for each memory bank.
NYX 0:85b3fd62ea1a 42
NYX 0:85b3fd62ea1a 43 @endverbatim
NYX 0:85b3fd62ea1a 44 ******************************************************************************
NYX 0:85b3fd62ea1a 45 * @attention
NYX 0:85b3fd62ea1a 46 *
NYX 0:85b3fd62ea1a 47 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 48 *
NYX 0:85b3fd62ea1a 49 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 50 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 51 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 52 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 54 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 55 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 57 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 58 * without specific prior written permission.
NYX 0:85b3fd62ea1a 59 *
NYX 0:85b3fd62ea1a 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 70 *
NYX 0:85b3fd62ea1a 71 ******************************************************************************
NYX 0:85b3fd62ea1a 72 */
NYX 0:85b3fd62ea1a 73
NYX 0:85b3fd62ea1a 74 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 75 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 76
NYX 0:85b3fd62ea1a 77 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 78 * @{
NYX 0:85b3fd62ea1a 79 */
NYX 0:85b3fd62ea1a 80
NYX 0:85b3fd62ea1a 81 /** @defgroup FSMC_LL FSMC Low Layer
NYX 0:85b3fd62ea1a 82 * @brief FSMC driver modules
NYX 0:85b3fd62ea1a 83 * @{
NYX 0:85b3fd62ea1a 84 */
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
NYX 0:85b3fd62ea1a 87 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
NYX 0:85b3fd62ea1a 88 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 89 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 90 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 91 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 92 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 93 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 94 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 95 /** @addtogroup FSMC_LL_Private_Functions
NYX 0:85b3fd62ea1a 96 * @{
NYX 0:85b3fd62ea1a 97 */
NYX 0:85b3fd62ea1a 98
NYX 0:85b3fd62ea1a 99 /** @addtogroup FSMC_LL_NORSRAM
NYX 0:85b3fd62ea1a 100 * @brief NORSRAM Controller functions
NYX 0:85b3fd62ea1a 101 *
NYX 0:85b3fd62ea1a 102 @verbatim
NYX 0:85b3fd62ea1a 103 ==============================================================================
NYX 0:85b3fd62ea1a 104 ##### How to use NORSRAM device driver #####
NYX 0:85b3fd62ea1a 105 ==============================================================================
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 [..]
NYX 0:85b3fd62ea1a 108 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
NYX 0:85b3fd62ea1a 109 to run the NORSRAM external devices.
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
NYX 0:85b3fd62ea1a 112 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
NYX 0:85b3fd62ea1a 113 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
NYX 0:85b3fd62ea1a 114 (+) FSMC NORSRAM bank extended timing configuration using the function
NYX 0:85b3fd62ea1a 115 FSMC_NORSRAM_Extended_Timing_Init()
NYX 0:85b3fd62ea1a 116 (+) FSMC NORSRAM bank enable/disable write operation using the functions
NYX 0:85b3fd62ea1a 117 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
NYX 0:85b3fd62ea1a 118
NYX 0:85b3fd62ea1a 119 @endverbatim
NYX 0:85b3fd62ea1a 120 * @{
NYX 0:85b3fd62ea1a 121 */
NYX 0:85b3fd62ea1a 122
NYX 0:85b3fd62ea1a 123 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
NYX 0:85b3fd62ea1a 124 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 125 *
NYX 0:85b3fd62ea1a 126 @verbatim
NYX 0:85b3fd62ea1a 127 ==============================================================================
NYX 0:85b3fd62ea1a 128 ##### Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 129 ==============================================================================
NYX 0:85b3fd62ea1a 130 [..]
NYX 0:85b3fd62ea1a 131 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 132 (+) Initialize and configure the FSMC NORSRAM interface
NYX 0:85b3fd62ea1a 133 (+) De-initialize the FSMC NORSRAM interface
NYX 0:85b3fd62ea1a 134 (+) Configure the FSMC clock and associated GPIOs
NYX 0:85b3fd62ea1a 135
NYX 0:85b3fd62ea1a 136 @endverbatim
NYX 0:85b3fd62ea1a 137 * @{
NYX 0:85b3fd62ea1a 138 */
NYX 0:85b3fd62ea1a 139
NYX 0:85b3fd62ea1a 140 /**
NYX 0:85b3fd62ea1a 141 * @brief Initialize the FSMC_NORSRAM device according to the specified
NYX 0:85b3fd62ea1a 142 * control parameters in the FSMC_NORSRAM_InitTypeDef
NYX 0:85b3fd62ea1a 143 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 144 * @param Init: Pointer to NORSRAM Initialization structure
NYX 0:85b3fd62ea1a 145 * @retval HAL status
NYX 0:85b3fd62ea1a 146 */
NYX 0:85b3fd62ea1a 147 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
NYX 0:85b3fd62ea1a 148 {
NYX 0:85b3fd62ea1a 149 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 150
NYX 0:85b3fd62ea1a 151 /* Check the parameters */
NYX 0:85b3fd62ea1a 152 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 153 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
NYX 0:85b3fd62ea1a 154 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
NYX 0:85b3fd62ea1a 155 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
NYX 0:85b3fd62ea1a 156 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
NYX 0:85b3fd62ea1a 157 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
NYX 0:85b3fd62ea1a 158 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
NYX 0:85b3fd62ea1a 159 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 160 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
NYX 0:85b3fd62ea1a 161 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 162 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
NYX 0:85b3fd62ea1a 163 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
NYX 0:85b3fd62ea1a 164 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
NYX 0:85b3fd62ea1a 165 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
NYX 0:85b3fd62ea1a 166 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
NYX 0:85b3fd62ea1a 167 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
NYX 0:85b3fd62ea1a 168 assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
NYX 0:85b3fd62ea1a 169 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 170 assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
NYX 0:85b3fd62ea1a 171 assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
NYX 0:85b3fd62ea1a 172 #endif /* STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 173
NYX 0:85b3fd62ea1a 174 /* Get the BTCR register value */
NYX 0:85b3fd62ea1a 175 tmpr = Device->BTCR[Init->NSBank];
NYX 0:85b3fd62ea1a 176
NYX 0:85b3fd62ea1a 177 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 178 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
NYX 0:85b3fd62ea1a 179 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */
NYX 0:85b3fd62ea1a 180 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
NYX 0:85b3fd62ea1a 181 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
NYX 0:85b3fd62ea1a 182 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
NYX 0:85b3fd62ea1a 183 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
NYX 0:85b3fd62ea1a 184 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW));
NYX 0:85b3fd62ea1a 185 /* Set NORSRAM device control parameters */
NYX 0:85b3fd62ea1a 186 tmpr |= (uint32_t)(Init->DataAddressMux |\
NYX 0:85b3fd62ea1a 187 Init->MemoryType |\
NYX 0:85b3fd62ea1a 188 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 189 Init->BurstAccessMode |\
NYX 0:85b3fd62ea1a 190 Init->WaitSignalPolarity |\
NYX 0:85b3fd62ea1a 191 Init->WrapMode |\
NYX 0:85b3fd62ea1a 192 Init->WaitSignalActive |\
NYX 0:85b3fd62ea1a 193 Init->WriteOperation |\
NYX 0:85b3fd62ea1a 194 Init->WaitSignal |\
NYX 0:85b3fd62ea1a 195 Init->ExtendedMode |\
NYX 0:85b3fd62ea1a 196 Init->AsynchronousWait |\
NYX 0:85b3fd62ea1a 197 Init->PageSize |\
NYX 0:85b3fd62ea1a 198 Init->WriteBurst
NYX 0:85b3fd62ea1a 199 );
NYX 0:85b3fd62ea1a 200 #else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 201 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
NYX 0:85b3fd62ea1a 202 WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */
NYX 0:85b3fd62ea1a 203 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
NYX 0:85b3fd62ea1a 204 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
NYX 0:85b3fd62ea1a 205 FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \
NYX 0:85b3fd62ea1a 206 FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \
NYX 0:85b3fd62ea1a 207 FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \
NYX 0:85b3fd62ea1a 208 FSMC_BCR1_WFDIS));
NYX 0:85b3fd62ea1a 209 /* Set NORSRAM device control parameters */
NYX 0:85b3fd62ea1a 210 tmpr |= (uint32_t)(Init->DataAddressMux |\
NYX 0:85b3fd62ea1a 211 Init->MemoryType |\
NYX 0:85b3fd62ea1a 212 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 213 Init->BurstAccessMode |\
NYX 0:85b3fd62ea1a 214 Init->WaitSignalPolarity |\
NYX 0:85b3fd62ea1a 215 Init->WaitSignalActive |\
NYX 0:85b3fd62ea1a 216 Init->WriteOperation |\
NYX 0:85b3fd62ea1a 217 Init->WaitSignal |\
NYX 0:85b3fd62ea1a 218 Init->ExtendedMode |\
NYX 0:85b3fd62ea1a 219 Init->AsynchronousWait |\
NYX 0:85b3fd62ea1a 220 Init->WriteBurst |\
NYX 0:85b3fd62ea1a 221 Init->ContinuousClock |\
NYX 0:85b3fd62ea1a 222 Init->PageSize |\
NYX 0:85b3fd62ea1a 223 Init->WriteFifo);
NYX 0:85b3fd62ea1a 224 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 225
NYX 0:85b3fd62ea1a 226 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
NYX 0:85b3fd62ea1a 227 {
NYX 0:85b3fd62ea1a 228 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
NYX 0:85b3fd62ea1a 229 }
NYX 0:85b3fd62ea1a 230
NYX 0:85b3fd62ea1a 231 Device->BTCR[Init->NSBank] = tmpr;
NYX 0:85b3fd62ea1a 232
NYX 0:85b3fd62ea1a 233 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 234 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
NYX 0:85b3fd62ea1a 235 if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
NYX 0:85b3fd62ea1a 236 {
NYX 0:85b3fd62ea1a 237 Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
NYX 0:85b3fd62ea1a 238 }
NYX 0:85b3fd62ea1a 239
NYX 0:85b3fd62ea1a 240 if(Init->NSBank != FSMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 241 {
NYX 0:85b3fd62ea1a 242 Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
NYX 0:85b3fd62ea1a 243 }
NYX 0:85b3fd62ea1a 244 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 245
NYX 0:85b3fd62ea1a 246 return HAL_OK;
NYX 0:85b3fd62ea1a 247 }
NYX 0:85b3fd62ea1a 248
NYX 0:85b3fd62ea1a 249 /**
NYX 0:85b3fd62ea1a 250 * @brief DeInitialize the FSMC_NORSRAM peripheral
NYX 0:85b3fd62ea1a 251 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 252 * @param ExDevice: Pointer to NORSRAM extended mode device instance
NYX 0:85b3fd62ea1a 253 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 254 * @retval HAL status
NYX 0:85b3fd62ea1a 255 */
NYX 0:85b3fd62ea1a 256 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
NYX 0:85b3fd62ea1a 257 {
NYX 0:85b3fd62ea1a 258 /* Check the parameters */
NYX 0:85b3fd62ea1a 259 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 260 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
NYX 0:85b3fd62ea1a 261 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 262
NYX 0:85b3fd62ea1a 263 /* Disable the FSMC_NORSRAM device */
NYX 0:85b3fd62ea1a 264 __FSMC_NORSRAM_DISABLE(Device, Bank);
NYX 0:85b3fd62ea1a 265
NYX 0:85b3fd62ea1a 266 /* De-initialize the FSMC_NORSRAM device */
NYX 0:85b3fd62ea1a 267 /* FSMC_NORSRAM_BANK1 */
NYX 0:85b3fd62ea1a 268 if(Bank == FSMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 269 {
NYX 0:85b3fd62ea1a 270 Device->BTCR[Bank] = 0x000030DBU;
NYX 0:85b3fd62ea1a 271 }
NYX 0:85b3fd62ea1a 272 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 273 else
NYX 0:85b3fd62ea1a 274 {
NYX 0:85b3fd62ea1a 275 Device->BTCR[Bank] = 0x000030D2U;
NYX 0:85b3fd62ea1a 276 }
NYX 0:85b3fd62ea1a 277
NYX 0:85b3fd62ea1a 278 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
NYX 0:85b3fd62ea1a 279 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
NYX 0:85b3fd62ea1a 280
NYX 0:85b3fd62ea1a 281 return HAL_OK;
NYX 0:85b3fd62ea1a 282 }
NYX 0:85b3fd62ea1a 283
NYX 0:85b3fd62ea1a 284
NYX 0:85b3fd62ea1a 285 /**
NYX 0:85b3fd62ea1a 286 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
NYX 0:85b3fd62ea1a 287 * parameters in the FSMC_NORSRAM_TimingTypeDef
NYX 0:85b3fd62ea1a 288 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 289 * @param Timing: Pointer to NORSRAM Timing structure
NYX 0:85b3fd62ea1a 290 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 291 * @retval HAL status
NYX 0:85b3fd62ea1a 292 */
NYX 0:85b3fd62ea1a 293 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 294 {
NYX 0:85b3fd62ea1a 295 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 296
NYX 0:85b3fd62ea1a 297 /* Check the parameters */
NYX 0:85b3fd62ea1a 298 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 299 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
NYX 0:85b3fd62ea1a 300 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
NYX 0:85b3fd62ea1a 301 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
NYX 0:85b3fd62ea1a 302 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
NYX 0:85b3fd62ea1a 303 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
NYX 0:85b3fd62ea1a 304 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
NYX 0:85b3fd62ea1a 305 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
NYX 0:85b3fd62ea1a 306 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 307
NYX 0:85b3fd62ea1a 308 /* Get the BTCR register value */
NYX 0:85b3fd62ea1a 309 tmpr = Device->BTCR[Bank + 1U];
NYX 0:85b3fd62ea1a 310
NYX 0:85b3fd62ea1a 311 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
NYX 0:85b3fd62ea1a 312 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
NYX 0:85b3fd62ea1a 313 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
NYX 0:85b3fd62ea1a 314 FSMC_BTR1_ACCMOD));
NYX 0:85b3fd62ea1a 315
NYX 0:85b3fd62ea1a 316 /* Set FSMC_NORSRAM device timing parameters */
NYX 0:85b3fd62ea1a 317 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
NYX 0:85b3fd62ea1a 318 ((Timing->AddressHoldTime) << 4U) |\
NYX 0:85b3fd62ea1a 319 ((Timing->DataSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 320 ((Timing->BusTurnAroundDuration) << 16U) |\
NYX 0:85b3fd62ea1a 321 (((Timing->CLKDivision)-1U) << 20U) |\
NYX 0:85b3fd62ea1a 322 (((Timing->DataLatency)-2U) << 24U) |\
NYX 0:85b3fd62ea1a 323 (Timing->AccessMode));
NYX 0:85b3fd62ea1a 324
NYX 0:85b3fd62ea1a 325 Device->BTCR[Bank + 1] = tmpr;
NYX 0:85b3fd62ea1a 326
NYX 0:85b3fd62ea1a 327 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 328 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
NYX 0:85b3fd62ea1a 329 if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
NYX 0:85b3fd62ea1a 330 {
NYX 0:85b3fd62ea1a 331 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
NYX 0:85b3fd62ea1a 332 tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U);
NYX 0:85b3fd62ea1a 333 Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr;
NYX 0:85b3fd62ea1a 334 }
NYX 0:85b3fd62ea1a 335 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 336
NYX 0:85b3fd62ea1a 337 return HAL_OK;
NYX 0:85b3fd62ea1a 338 }
NYX 0:85b3fd62ea1a 339
NYX 0:85b3fd62ea1a 340 /**
NYX 0:85b3fd62ea1a 341 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
NYX 0:85b3fd62ea1a 342 * parameters in the FSMC_NORSRAM_TimingTypeDef
NYX 0:85b3fd62ea1a 343 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 344 * @param Timing: Pointer to NORSRAM Timing structure
NYX 0:85b3fd62ea1a 345 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 346 * @retval HAL status
NYX 0:85b3fd62ea1a 347 */
NYX 0:85b3fd62ea1a 348 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
NYX 0:85b3fd62ea1a 349 {
NYX 0:85b3fd62ea1a 350 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 351
NYX 0:85b3fd62ea1a 352 /* Check the parameters */
NYX 0:85b3fd62ea1a 353 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
NYX 0:85b3fd62ea1a 354
NYX 0:85b3fd62ea1a 355 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
NYX 0:85b3fd62ea1a 356 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
NYX 0:85b3fd62ea1a 357 {
NYX 0:85b3fd62ea1a 358 /* Check the parameters */
NYX 0:85b3fd62ea1a 359 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
NYX 0:85b3fd62ea1a 360 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
NYX 0:85b3fd62ea1a 361 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
NYX 0:85b3fd62ea1a 362 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
NYX 0:85b3fd62ea1a 363 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
NYX 0:85b3fd62ea1a 364 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
NYX 0:85b3fd62ea1a 365 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 366
NYX 0:85b3fd62ea1a 367 /* Get the BWTR register value */
NYX 0:85b3fd62ea1a 368 tmpr = Device->BWTR[Bank];
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
NYX 0:85b3fd62ea1a 371 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
NYX 0:85b3fd62ea1a 372 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
NYX 0:85b3fd62ea1a 373
NYX 0:85b3fd62ea1a 374 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
NYX 0:85b3fd62ea1a 375 ((Timing->AddressHoldTime) << 4U) |\
NYX 0:85b3fd62ea1a 376 ((Timing->DataSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 377 ((Timing->BusTurnAroundDuration) << 16U) |\
NYX 0:85b3fd62ea1a 378 (Timing->AccessMode));
NYX 0:85b3fd62ea1a 379
NYX 0:85b3fd62ea1a 380 Device->BWTR[Bank] = tmpr;
NYX 0:85b3fd62ea1a 381 }
NYX 0:85b3fd62ea1a 382 else
NYX 0:85b3fd62ea1a 383 {
NYX 0:85b3fd62ea1a 384 Device->BWTR[Bank] = 0x0FFFFFFFU;
NYX 0:85b3fd62ea1a 385 }
NYX 0:85b3fd62ea1a 386
NYX 0:85b3fd62ea1a 387 return HAL_OK;
NYX 0:85b3fd62ea1a 388 }
NYX 0:85b3fd62ea1a 389 /**
NYX 0:85b3fd62ea1a 390 * @}
NYX 0:85b3fd62ea1a 391 */
NYX 0:85b3fd62ea1a 392
NYX 0:85b3fd62ea1a 393 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
NYX 0:85b3fd62ea1a 394 * @brief management functions
NYX 0:85b3fd62ea1a 395 *
NYX 0:85b3fd62ea1a 396 @verbatim
NYX 0:85b3fd62ea1a 397 ==============================================================================
NYX 0:85b3fd62ea1a 398 ##### FSMC_NORSRAM Control functions #####
NYX 0:85b3fd62ea1a 399 ==============================================================================
NYX 0:85b3fd62ea1a 400 [..]
NYX 0:85b3fd62ea1a 401 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 402 the FSMC NORSRAM interface.
NYX 0:85b3fd62ea1a 403
NYX 0:85b3fd62ea1a 404 @endverbatim
NYX 0:85b3fd62ea1a 405 * @{
NYX 0:85b3fd62ea1a 406 */
NYX 0:85b3fd62ea1a 407
NYX 0:85b3fd62ea1a 408 /**
NYX 0:85b3fd62ea1a 409 * @brief Enables dynamically FSMC_NORSRAM write operation.
NYX 0:85b3fd62ea1a 410 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 411 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 412 * @retval HAL status
NYX 0:85b3fd62ea1a 413 */
NYX 0:85b3fd62ea1a 414 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 415 {
NYX 0:85b3fd62ea1a 416 /* Check the parameters */
NYX 0:85b3fd62ea1a 417 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 418 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 419
NYX 0:85b3fd62ea1a 420 /* Enable write operation */
NYX 0:85b3fd62ea1a 421 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
NYX 0:85b3fd62ea1a 422
NYX 0:85b3fd62ea1a 423 return HAL_OK;
NYX 0:85b3fd62ea1a 424 }
NYX 0:85b3fd62ea1a 425
NYX 0:85b3fd62ea1a 426 /**
NYX 0:85b3fd62ea1a 427 * @brief Disables dynamically FSMC_NORSRAM write operation.
NYX 0:85b3fd62ea1a 428 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 429 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 430 * @retval HAL status
NYX 0:85b3fd62ea1a 431 */
NYX 0:85b3fd62ea1a 432 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 433 {
NYX 0:85b3fd62ea1a 434 /* Check the parameters */
NYX 0:85b3fd62ea1a 435 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 436 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 437
NYX 0:85b3fd62ea1a 438 /* Disable write operation */
NYX 0:85b3fd62ea1a 439 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
NYX 0:85b3fd62ea1a 440
NYX 0:85b3fd62ea1a 441 return HAL_OK;
NYX 0:85b3fd62ea1a 442 }
NYX 0:85b3fd62ea1a 443 /**
NYX 0:85b3fd62ea1a 444 * @}
NYX 0:85b3fd62ea1a 445 */
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 /**
NYX 0:85b3fd62ea1a 448 * @}
NYX 0:85b3fd62ea1a 449 */
NYX 0:85b3fd62ea1a 450
NYX 0:85b3fd62ea1a 451 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
NYX 0:85b3fd62ea1a 452 /** @addtogroup FSMC_LL_NAND
NYX 0:85b3fd62ea1a 453 * @brief NAND Controller functions
NYX 0:85b3fd62ea1a 454 *
NYX 0:85b3fd62ea1a 455 @verbatim
NYX 0:85b3fd62ea1a 456 ==============================================================================
NYX 0:85b3fd62ea1a 457 ##### How to use NAND device driver #####
NYX 0:85b3fd62ea1a 458 ==============================================================================
NYX 0:85b3fd62ea1a 459 [..]
NYX 0:85b3fd62ea1a 460 This driver contains a set of APIs to interface with the FSMC NAND banks in order
NYX 0:85b3fd62ea1a 461 to run the NAND external devices.
NYX 0:85b3fd62ea1a 462
NYX 0:85b3fd62ea1a 463 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
NYX 0:85b3fd62ea1a 464 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
NYX 0:85b3fd62ea1a 465 (+) FSMC NAND bank common space timing configuration using the function
NYX 0:85b3fd62ea1a 466 FSMC_NAND_CommonSpace_Timing_Init()
NYX 0:85b3fd62ea1a 467 (+) FSMC NAND bank attribute space timing configuration using the function
NYX 0:85b3fd62ea1a 468 FSMC_NAND_AttributeSpace_Timing_Init()
NYX 0:85b3fd62ea1a 469 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
NYX 0:85b3fd62ea1a 470 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
NYX 0:85b3fd62ea1a 471 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
NYX 0:85b3fd62ea1a 472
NYX 0:85b3fd62ea1a 473 @endverbatim
NYX 0:85b3fd62ea1a 474 * @{
NYX 0:85b3fd62ea1a 475 */
NYX 0:85b3fd62ea1a 476
NYX 0:85b3fd62ea1a 477 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
NYX 0:85b3fd62ea1a 478 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 479 *
NYX 0:85b3fd62ea1a 480 @verbatim
NYX 0:85b3fd62ea1a 481 ==============================================================================
NYX 0:85b3fd62ea1a 482 ##### Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 483 ==============================================================================
NYX 0:85b3fd62ea1a 484 [..]
NYX 0:85b3fd62ea1a 485 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 486 (+) Initialize and configure the FSMC NAND interface
NYX 0:85b3fd62ea1a 487 (+) De-initialize the FSMC NAND interface
NYX 0:85b3fd62ea1a 488 (+) Configure the FSMC clock and associated GPIOs
NYX 0:85b3fd62ea1a 489
NYX 0:85b3fd62ea1a 490 @endverbatim
NYX 0:85b3fd62ea1a 491 * @{
NYX 0:85b3fd62ea1a 492 */
NYX 0:85b3fd62ea1a 493
NYX 0:85b3fd62ea1a 494 /**
NYX 0:85b3fd62ea1a 495 * @brief Initializes the FSMC_NAND device according to the specified
NYX 0:85b3fd62ea1a 496 * control parameters in the FSMC_NAND_HandleTypeDef
NYX 0:85b3fd62ea1a 497 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 498 * @param Init: Pointer to NAND Initialization structure
NYX 0:85b3fd62ea1a 499 * @retval HAL status
NYX 0:85b3fd62ea1a 500 */
NYX 0:85b3fd62ea1a 501 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
NYX 0:85b3fd62ea1a 502 {
NYX 0:85b3fd62ea1a 503 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 504
NYX 0:85b3fd62ea1a 505 /* Check the parameters */
NYX 0:85b3fd62ea1a 506 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
NYX 0:85b3fd62ea1a 507 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
NYX 0:85b3fd62ea1a 508 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
NYX 0:85b3fd62ea1a 509 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
NYX 0:85b3fd62ea1a 510 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
NYX 0:85b3fd62ea1a 511 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
NYX 0:85b3fd62ea1a 512 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
NYX 0:85b3fd62ea1a 513
NYX 0:85b3fd62ea1a 514 if(Init->NandBank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 515 {
NYX 0:85b3fd62ea1a 516 /* Get the NAND bank 2 register value */
NYX 0:85b3fd62ea1a 517 tmpr = Device->PCR2;
NYX 0:85b3fd62ea1a 518 }
NYX 0:85b3fd62ea1a 519 else
NYX 0:85b3fd62ea1a 520 {
NYX 0:85b3fd62ea1a 521 /* Get the NAND bank 3 register value */
NYX 0:85b3fd62ea1a 522 tmpr = Device->PCR3;
NYX 0:85b3fd62ea1a 523 }
NYX 0:85b3fd62ea1a 524
NYX 0:85b3fd62ea1a 525 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
NYX 0:85b3fd62ea1a 526 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
NYX 0:85b3fd62ea1a 527 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
NYX 0:85b3fd62ea1a 528 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
NYX 0:85b3fd62ea1a 529
NYX 0:85b3fd62ea1a 530 /* Set NAND device control parameters */
NYX 0:85b3fd62ea1a 531 tmpr |= (uint32_t)(Init->Waitfeature |\
NYX 0:85b3fd62ea1a 532 FSMC_PCR_MEMORY_TYPE_NAND |\
NYX 0:85b3fd62ea1a 533 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 534 Init->EccComputation |\
NYX 0:85b3fd62ea1a 535 Init->ECCPageSize |\
NYX 0:85b3fd62ea1a 536 ((Init->TCLRSetupTime) << 9U) |\
NYX 0:85b3fd62ea1a 537 ((Init->TARSetupTime) << 13U));
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 if(Init->NandBank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 540 {
NYX 0:85b3fd62ea1a 541 /* NAND bank 2 registers configuration */
NYX 0:85b3fd62ea1a 542 Device->PCR2 = tmpr;
NYX 0:85b3fd62ea1a 543 }
NYX 0:85b3fd62ea1a 544 else
NYX 0:85b3fd62ea1a 545 {
NYX 0:85b3fd62ea1a 546 /* NAND bank 3 registers configuration */
NYX 0:85b3fd62ea1a 547 Device->PCR3 = tmpr;
NYX 0:85b3fd62ea1a 548 }
NYX 0:85b3fd62ea1a 549
NYX 0:85b3fd62ea1a 550 return HAL_OK;
NYX 0:85b3fd62ea1a 551 }
NYX 0:85b3fd62ea1a 552
NYX 0:85b3fd62ea1a 553 /**
NYX 0:85b3fd62ea1a 554 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
NYX 0:85b3fd62ea1a 555 * parameters in the FSMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 556 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 557 * @param Timing: Pointer to NAND timing structure
NYX 0:85b3fd62ea1a 558 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 559 * @retval HAL status
NYX 0:85b3fd62ea1a 560 */
NYX 0:85b3fd62ea1a 561 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 562 {
NYX 0:85b3fd62ea1a 563 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 564
NYX 0:85b3fd62ea1a 565 /* Check the parameters */
NYX 0:85b3fd62ea1a 566 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 567 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 568 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 569 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 570
NYX 0:85b3fd62ea1a 571 if(Bank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 572 {
NYX 0:85b3fd62ea1a 573 /* Get the NAND bank 2 register value */
NYX 0:85b3fd62ea1a 574 tmpr = Device->PMEM2;
NYX 0:85b3fd62ea1a 575 }
NYX 0:85b3fd62ea1a 576 else
NYX 0:85b3fd62ea1a 577 {
NYX 0:85b3fd62ea1a 578 /* Get the NAND bank 3 register value */
NYX 0:85b3fd62ea1a 579 tmpr = Device->PMEM3;
NYX 0:85b3fd62ea1a 580 }
NYX 0:85b3fd62ea1a 581
NYX 0:85b3fd62ea1a 582 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
NYX 0:85b3fd62ea1a 583 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
NYX 0:85b3fd62ea1a 584 FSMC_PMEM2_MEMHIZ2));
NYX 0:85b3fd62ea1a 585
NYX 0:85b3fd62ea1a 586 /* Set FSMC_NAND device timing parameters */
NYX 0:85b3fd62ea1a 587 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 588 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 589 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 590 ((Timing->HiZSetupTime) << 24U)
NYX 0:85b3fd62ea1a 591 );
NYX 0:85b3fd62ea1a 592
NYX 0:85b3fd62ea1a 593 if(Bank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 594 {
NYX 0:85b3fd62ea1a 595 /* NAND bank 2 registers configuration */
NYX 0:85b3fd62ea1a 596 Device->PMEM2 = tmpr;
NYX 0:85b3fd62ea1a 597 }
NYX 0:85b3fd62ea1a 598 else
NYX 0:85b3fd62ea1a 599 {
NYX 0:85b3fd62ea1a 600 /* NAND bank 3 registers configuration */
NYX 0:85b3fd62ea1a 601 Device->PMEM3 = tmpr;
NYX 0:85b3fd62ea1a 602 }
NYX 0:85b3fd62ea1a 603
NYX 0:85b3fd62ea1a 604 return HAL_OK;
NYX 0:85b3fd62ea1a 605 }
NYX 0:85b3fd62ea1a 606
NYX 0:85b3fd62ea1a 607 /**
NYX 0:85b3fd62ea1a 608 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
NYX 0:85b3fd62ea1a 609 * parameters in the FSMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 610 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 611 * @param Timing: Pointer to NAND timing structure
NYX 0:85b3fd62ea1a 612 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 613 * @retval HAL status
NYX 0:85b3fd62ea1a 614 */
NYX 0:85b3fd62ea1a 615 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 616 {
NYX 0:85b3fd62ea1a 617 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 618
NYX 0:85b3fd62ea1a 619 /* Check the parameters */
NYX 0:85b3fd62ea1a 620 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 621 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 622 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 623 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 624
NYX 0:85b3fd62ea1a 625 if(Bank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 626 {
NYX 0:85b3fd62ea1a 627 /* Get the NAND bank 2 register value */
NYX 0:85b3fd62ea1a 628 tmpr = Device->PATT2;
NYX 0:85b3fd62ea1a 629 }
NYX 0:85b3fd62ea1a 630 else
NYX 0:85b3fd62ea1a 631 {
NYX 0:85b3fd62ea1a 632 /* Get the NAND bank 3 register value */
NYX 0:85b3fd62ea1a 633 tmpr = Device->PATT3;
NYX 0:85b3fd62ea1a 634 }
NYX 0:85b3fd62ea1a 635
NYX 0:85b3fd62ea1a 636 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
NYX 0:85b3fd62ea1a 637 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
NYX 0:85b3fd62ea1a 638 FSMC_PATT2_ATTHIZ2));
NYX 0:85b3fd62ea1a 639
NYX 0:85b3fd62ea1a 640 /* Set FSMC_NAND device timing parameters */
NYX 0:85b3fd62ea1a 641 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 642 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 643 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 644 ((Timing->HiZSetupTime) << 24U)
NYX 0:85b3fd62ea1a 645 );
NYX 0:85b3fd62ea1a 646
NYX 0:85b3fd62ea1a 647 if(Bank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 648 {
NYX 0:85b3fd62ea1a 649 /* NAND bank 2 registers configuration */
NYX 0:85b3fd62ea1a 650 Device->PATT2 = tmpr;
NYX 0:85b3fd62ea1a 651 }
NYX 0:85b3fd62ea1a 652 else
NYX 0:85b3fd62ea1a 653 {
NYX 0:85b3fd62ea1a 654 /* NAND bank 3 registers configuration */
NYX 0:85b3fd62ea1a 655 Device->PATT3 = tmpr;
NYX 0:85b3fd62ea1a 656 }
NYX 0:85b3fd62ea1a 657
NYX 0:85b3fd62ea1a 658 return HAL_OK;
NYX 0:85b3fd62ea1a 659 }
NYX 0:85b3fd62ea1a 660
NYX 0:85b3fd62ea1a 661 /**
NYX 0:85b3fd62ea1a 662 * @brief DeInitializes the FSMC_NAND device
NYX 0:85b3fd62ea1a 663 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 664 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 665 * @retval HAL status
NYX 0:85b3fd62ea1a 666 */
NYX 0:85b3fd62ea1a 667 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 668 {
NYX 0:85b3fd62ea1a 669 /* Disable the NAND Bank */
NYX 0:85b3fd62ea1a 670 __FSMC_NAND_DISABLE(Device, Bank);
NYX 0:85b3fd62ea1a 671
NYX 0:85b3fd62ea1a 672 /* De-initialize the NAND Bank */
NYX 0:85b3fd62ea1a 673 if(Bank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 674 {
NYX 0:85b3fd62ea1a 675 /* Set the FSMC_NAND_BANK2 registers to their reset values */
NYX 0:85b3fd62ea1a 676 Device->PCR2 = 0x00000018U;
NYX 0:85b3fd62ea1a 677 Device->SR2 = 0x00000040U;
NYX 0:85b3fd62ea1a 678 Device->PMEM2 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 679 Device->PATT2 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 680 }
NYX 0:85b3fd62ea1a 681 /* FSMC_Bank3_NAND */
NYX 0:85b3fd62ea1a 682 else
NYX 0:85b3fd62ea1a 683 {
NYX 0:85b3fd62ea1a 684 /* Set the FSMC_NAND_BANK3 registers to their reset values */
NYX 0:85b3fd62ea1a 685 Device->PCR3 = 0x00000018U;
NYX 0:85b3fd62ea1a 686 Device->SR3 = 0x00000040U;
NYX 0:85b3fd62ea1a 687 Device->PMEM3 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 688 Device->PATT3 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 689 }
NYX 0:85b3fd62ea1a 690
NYX 0:85b3fd62ea1a 691 return HAL_OK;
NYX 0:85b3fd62ea1a 692 }
NYX 0:85b3fd62ea1a 693 /**
NYX 0:85b3fd62ea1a 694 * @}
NYX 0:85b3fd62ea1a 695 */
NYX 0:85b3fd62ea1a 696
NYX 0:85b3fd62ea1a 697 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
NYX 0:85b3fd62ea1a 698 * @brief management functions
NYX 0:85b3fd62ea1a 699 *
NYX 0:85b3fd62ea1a 700 @verbatim
NYX 0:85b3fd62ea1a 701 ==============================================================================
NYX 0:85b3fd62ea1a 702 ##### FSMC_NAND Control functions #####
NYX 0:85b3fd62ea1a 703 ==============================================================================
NYX 0:85b3fd62ea1a 704 [..]
NYX 0:85b3fd62ea1a 705 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 706 the FSMC NAND interface.
NYX 0:85b3fd62ea1a 707
NYX 0:85b3fd62ea1a 708 @endverbatim
NYX 0:85b3fd62ea1a 709 * @{
NYX 0:85b3fd62ea1a 710 */
NYX 0:85b3fd62ea1a 711
NYX 0:85b3fd62ea1a 712 /**
NYX 0:85b3fd62ea1a 713 * @brief Enables dynamically FSMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 714 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 715 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 716 * @retval HAL status
NYX 0:85b3fd62ea1a 717 */
NYX 0:85b3fd62ea1a 718 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 719 {
NYX 0:85b3fd62ea1a 720 /* Enable ECC feature */
NYX 0:85b3fd62ea1a 721 if(Bank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 722 {
NYX 0:85b3fd62ea1a 723 Device->PCR2 |= FSMC_PCR2_ECCEN;
NYX 0:85b3fd62ea1a 724 }
NYX 0:85b3fd62ea1a 725 else
NYX 0:85b3fd62ea1a 726 {
NYX 0:85b3fd62ea1a 727 Device->PCR3 |= FSMC_PCR3_ECCEN;
NYX 0:85b3fd62ea1a 728 }
NYX 0:85b3fd62ea1a 729
NYX 0:85b3fd62ea1a 730 return HAL_OK;
NYX 0:85b3fd62ea1a 731 }
NYX 0:85b3fd62ea1a 732
NYX 0:85b3fd62ea1a 733 /**
NYX 0:85b3fd62ea1a 734 * @brief Disables dynamically FSMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 735 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 736 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 737 * @retval HAL status
NYX 0:85b3fd62ea1a 738 */
NYX 0:85b3fd62ea1a 739 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 740 {
NYX 0:85b3fd62ea1a 741 /* Disable ECC feature */
NYX 0:85b3fd62ea1a 742 if(Bank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 743 {
NYX 0:85b3fd62ea1a 744 Device->PCR2 &= ~FSMC_PCR2_ECCEN;
NYX 0:85b3fd62ea1a 745 }
NYX 0:85b3fd62ea1a 746 else
NYX 0:85b3fd62ea1a 747 {
NYX 0:85b3fd62ea1a 748 Device->PCR3 &= ~FSMC_PCR3_ECCEN;
NYX 0:85b3fd62ea1a 749 }
NYX 0:85b3fd62ea1a 750
NYX 0:85b3fd62ea1a 751 return HAL_OK;
NYX 0:85b3fd62ea1a 752 }
NYX 0:85b3fd62ea1a 753
NYX 0:85b3fd62ea1a 754 /**
NYX 0:85b3fd62ea1a 755 * @brief Disables dynamically FSMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 756 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 757 * @param ECCval: Pointer to ECC value
NYX 0:85b3fd62ea1a 758 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 759 * @param Timeout: Timeout wait value
NYX 0:85b3fd62ea1a 760 * @retval HAL status
NYX 0:85b3fd62ea1a 761 */
NYX 0:85b3fd62ea1a 762 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
NYX 0:85b3fd62ea1a 763 {
NYX 0:85b3fd62ea1a 764 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 765
NYX 0:85b3fd62ea1a 766 /* Check the parameters */
NYX 0:85b3fd62ea1a 767 assert_param(IS_FSMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 768 assert_param(IS_FSMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 769
NYX 0:85b3fd62ea1a 770 /* Get tick */
NYX 0:85b3fd62ea1a 771 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 772
NYX 0:85b3fd62ea1a 773 /* Wait until FIFO is empty */
NYX 0:85b3fd62ea1a 774 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
NYX 0:85b3fd62ea1a 775 {
NYX 0:85b3fd62ea1a 776 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 777 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 778 {
NYX 0:85b3fd62ea1a 779 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 780 {
NYX 0:85b3fd62ea1a 781 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 782 }
NYX 0:85b3fd62ea1a 783 }
NYX 0:85b3fd62ea1a 784 }
NYX 0:85b3fd62ea1a 785
NYX 0:85b3fd62ea1a 786 if(Bank == FSMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 787 {
NYX 0:85b3fd62ea1a 788 /* Get the ECCR2 register value */
NYX 0:85b3fd62ea1a 789 *ECCval = (uint32_t)Device->ECCR2;
NYX 0:85b3fd62ea1a 790 }
NYX 0:85b3fd62ea1a 791 else
NYX 0:85b3fd62ea1a 792 {
NYX 0:85b3fd62ea1a 793 /* Get the ECCR3 register value */
NYX 0:85b3fd62ea1a 794 *ECCval = (uint32_t)Device->ECCR3;
NYX 0:85b3fd62ea1a 795 }
NYX 0:85b3fd62ea1a 796
NYX 0:85b3fd62ea1a 797 return HAL_OK;
NYX 0:85b3fd62ea1a 798 }
NYX 0:85b3fd62ea1a 799
NYX 0:85b3fd62ea1a 800 /**
NYX 0:85b3fd62ea1a 801 * @}
NYX 0:85b3fd62ea1a 802 */
NYX 0:85b3fd62ea1a 803
NYX 0:85b3fd62ea1a 804 /**
NYX 0:85b3fd62ea1a 805 * @}
NYX 0:85b3fd62ea1a 806 */
NYX 0:85b3fd62ea1a 807
NYX 0:85b3fd62ea1a 808 /** @addtogroup FSMC_LL_PCCARD
NYX 0:85b3fd62ea1a 809 * @brief PCCARD Controller functions
NYX 0:85b3fd62ea1a 810 *
NYX 0:85b3fd62ea1a 811 @verbatim
NYX 0:85b3fd62ea1a 812 ==============================================================================
NYX 0:85b3fd62ea1a 813 ##### How to use PCCARD device driver #####
NYX 0:85b3fd62ea1a 814 ==============================================================================
NYX 0:85b3fd62ea1a 815 [..]
NYX 0:85b3fd62ea1a 816 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
NYX 0:85b3fd62ea1a 817 to run the PCCARD/compact flash external devices.
NYX 0:85b3fd62ea1a 818
NYX 0:85b3fd62ea1a 819 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
NYX 0:85b3fd62ea1a 820 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
NYX 0:85b3fd62ea1a 821 (+) FSMC PCCARD bank common space timing configuration using the function
NYX 0:85b3fd62ea1a 822 FSMC_PCCARD_CommonSpace_Timing_Init()
NYX 0:85b3fd62ea1a 823 (+) FSMC PCCARD bank attribute space timing configuration using the function
NYX 0:85b3fd62ea1a 824 FSMC_PCCARD_AttributeSpace_Timing_Init()
NYX 0:85b3fd62ea1a 825 (+) FSMC PCCARD bank IO space timing configuration using the function
NYX 0:85b3fd62ea1a 826 FSMC_PCCARD_IOSpace_Timing_Init()
NYX 0:85b3fd62ea1a 827
NYX 0:85b3fd62ea1a 828 @endverbatim
NYX 0:85b3fd62ea1a 829 * @{
NYX 0:85b3fd62ea1a 830 */
NYX 0:85b3fd62ea1a 831
NYX 0:85b3fd62ea1a 832 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
NYX 0:85b3fd62ea1a 833 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 834 *
NYX 0:85b3fd62ea1a 835 @verbatim
NYX 0:85b3fd62ea1a 836 ==============================================================================
NYX 0:85b3fd62ea1a 837 ##### Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 838 ==============================================================================
NYX 0:85b3fd62ea1a 839 [..]
NYX 0:85b3fd62ea1a 840 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 841 (+) Initialize and configure the FSMC PCCARD interface
NYX 0:85b3fd62ea1a 842 (+) De-initialize the FSMC PCCARD interface
NYX 0:85b3fd62ea1a 843 (+) Configure the FSMC clock and associated GPIOs
NYX 0:85b3fd62ea1a 844
NYX 0:85b3fd62ea1a 845 @endverbatim
NYX 0:85b3fd62ea1a 846 * @{
NYX 0:85b3fd62ea1a 847 */
NYX 0:85b3fd62ea1a 848
NYX 0:85b3fd62ea1a 849 /**
NYX 0:85b3fd62ea1a 850 * @brief Initializes the FSMC_PCCARD device according to the specified
NYX 0:85b3fd62ea1a 851 * control parameters in the FSMC_PCCARD_HandleTypeDef
NYX 0:85b3fd62ea1a 852 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 853 * @param Init: Pointer to PCCARD Initialization structure
NYX 0:85b3fd62ea1a 854 * @retval HAL status
NYX 0:85b3fd62ea1a 855 */
NYX 0:85b3fd62ea1a 856 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
NYX 0:85b3fd62ea1a 857 {
NYX 0:85b3fd62ea1a 858 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 859
NYX 0:85b3fd62ea1a 860 /* Check the parameters */
NYX 0:85b3fd62ea1a 861 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
NYX 0:85b3fd62ea1a 862 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
NYX 0:85b3fd62ea1a 863 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
NYX 0:85b3fd62ea1a 864
NYX 0:85b3fd62ea1a 865 /* Get PCCARD control register value */
NYX 0:85b3fd62ea1a 866 tmpr = Device->PCR4;
NYX 0:85b3fd62ea1a 867
NYX 0:85b3fd62ea1a 868 /* Clear TAR, TCLR, PWAITEN and PWID bits */
NYX 0:85b3fd62ea1a 869 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
NYX 0:85b3fd62ea1a 870 FSMC_PCR4_PWID));
NYX 0:85b3fd62ea1a 871
NYX 0:85b3fd62ea1a 872 /* Set FSMC_PCCARD device control parameters */
NYX 0:85b3fd62ea1a 873 tmpr |= (uint32_t)(Init->Waitfeature |\
NYX 0:85b3fd62ea1a 874 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
NYX 0:85b3fd62ea1a 875 (Init->TCLRSetupTime << 9U) |\
NYX 0:85b3fd62ea1a 876 (Init->TARSetupTime << 13U));
NYX 0:85b3fd62ea1a 877
NYX 0:85b3fd62ea1a 878 Device->PCR4 = tmpr;
NYX 0:85b3fd62ea1a 879
NYX 0:85b3fd62ea1a 880 return HAL_OK;
NYX 0:85b3fd62ea1a 881 }
NYX 0:85b3fd62ea1a 882
NYX 0:85b3fd62ea1a 883 /**
NYX 0:85b3fd62ea1a 884 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
NYX 0:85b3fd62ea1a 885 * parameters in the FSMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 886 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 887 * @param Timing: Pointer to PCCARD timing structure
NYX 0:85b3fd62ea1a 888 * @retval HAL status
NYX 0:85b3fd62ea1a 889 */
NYX 0:85b3fd62ea1a 890 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
NYX 0:85b3fd62ea1a 891 {
NYX 0:85b3fd62ea1a 892 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 893
NYX 0:85b3fd62ea1a 894 /* Check the parameters */
NYX 0:85b3fd62ea1a 895 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 896 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 897 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 898 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 899
NYX 0:85b3fd62ea1a 900 /* Get PCCARD common space timing register value */
NYX 0:85b3fd62ea1a 901 tmpr = Device->PMEM4;
NYX 0:85b3fd62ea1a 902
NYX 0:85b3fd62ea1a 903 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
NYX 0:85b3fd62ea1a 904 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
NYX 0:85b3fd62ea1a 905 FSMC_PMEM4_MEMHIZ4));
NYX 0:85b3fd62ea1a 906 /* Set PCCARD timing parameters */
NYX 0:85b3fd62ea1a 907 tmpr |= (uint32_t)((Timing->SetupTime |\
NYX 0:85b3fd62ea1a 908 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 909 (Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 910 ((Timing->HiZSetupTime) << 24U));
NYX 0:85b3fd62ea1a 911
NYX 0:85b3fd62ea1a 912 Device->PMEM4 = tmpr;
NYX 0:85b3fd62ea1a 913
NYX 0:85b3fd62ea1a 914 return HAL_OK;
NYX 0:85b3fd62ea1a 915 }
NYX 0:85b3fd62ea1a 916
NYX 0:85b3fd62ea1a 917 /**
NYX 0:85b3fd62ea1a 918 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
NYX 0:85b3fd62ea1a 919 * parameters in the FSMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 920 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 921 * @param Timing: Pointer to PCCARD timing structure
NYX 0:85b3fd62ea1a 922 * @retval HAL status
NYX 0:85b3fd62ea1a 923 */
NYX 0:85b3fd62ea1a 924 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
NYX 0:85b3fd62ea1a 925 {
NYX 0:85b3fd62ea1a 926 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 927
NYX 0:85b3fd62ea1a 928 /* Check the parameters */
NYX 0:85b3fd62ea1a 929 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 930 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 931 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 932 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 933
NYX 0:85b3fd62ea1a 934 /* Get PCCARD timing parameters */
NYX 0:85b3fd62ea1a 935 tmpr = Device->PATT4;
NYX 0:85b3fd62ea1a 936
NYX 0:85b3fd62ea1a 937 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
NYX 0:85b3fd62ea1a 938 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
NYX 0:85b3fd62ea1a 939 FSMC_PATT4_ATTHIZ4));
NYX 0:85b3fd62ea1a 940
NYX 0:85b3fd62ea1a 941 /* Set PCCARD timing parameters */
NYX 0:85b3fd62ea1a 942 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 943 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 944 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 945 ((Timing->HiZSetupTime) << 24U));
NYX 0:85b3fd62ea1a 946 Device->PATT4 = tmpr;
NYX 0:85b3fd62ea1a 947
NYX 0:85b3fd62ea1a 948 return HAL_OK;
NYX 0:85b3fd62ea1a 949 }
NYX 0:85b3fd62ea1a 950
NYX 0:85b3fd62ea1a 951 /**
NYX 0:85b3fd62ea1a 952 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
NYX 0:85b3fd62ea1a 953 * parameters in the FSMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 954 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 955 * @param Timing: Pointer to PCCARD timing structure
NYX 0:85b3fd62ea1a 956 * @retval HAL status
NYX 0:85b3fd62ea1a 957 */
NYX 0:85b3fd62ea1a 958 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
NYX 0:85b3fd62ea1a 959 {
NYX 0:85b3fd62ea1a 960 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 961
NYX 0:85b3fd62ea1a 962 /* Check the parameters */
NYX 0:85b3fd62ea1a 963 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 964 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 965 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 966 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 967
NYX 0:85b3fd62ea1a 968 /* Get FSMC_PCCARD device timing parameters */
NYX 0:85b3fd62ea1a 969 tmpr = Device->PIO4;
NYX 0:85b3fd62ea1a 970
NYX 0:85b3fd62ea1a 971 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
NYX 0:85b3fd62ea1a 972 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
NYX 0:85b3fd62ea1a 973 FSMC_PIO4_IOHIZ4));
NYX 0:85b3fd62ea1a 974
NYX 0:85b3fd62ea1a 975 /* Set FSMC_PCCARD device timing parameters */
NYX 0:85b3fd62ea1a 976 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 977 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 978 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 979 ((Timing->HiZSetupTime) << 24U));
NYX 0:85b3fd62ea1a 980
NYX 0:85b3fd62ea1a 981 Device->PIO4 = tmpr;
NYX 0:85b3fd62ea1a 982
NYX 0:85b3fd62ea1a 983 return HAL_OK;
NYX 0:85b3fd62ea1a 984 }
NYX 0:85b3fd62ea1a 985
NYX 0:85b3fd62ea1a 986 /**
NYX 0:85b3fd62ea1a 987 * @brief DeInitializes the FSMC_PCCARD device
NYX 0:85b3fd62ea1a 988 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 989 * @retval HAL status
NYX 0:85b3fd62ea1a 990 */
NYX 0:85b3fd62ea1a 991 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
NYX 0:85b3fd62ea1a 992 {
NYX 0:85b3fd62ea1a 993 /* Disable the FSMC_PCCARD device */
NYX 0:85b3fd62ea1a 994 __FSMC_PCCARD_DISABLE(Device);
NYX 0:85b3fd62ea1a 995
NYX 0:85b3fd62ea1a 996 /* De-initialize the FSMC_PCCARD device */
NYX 0:85b3fd62ea1a 997 Device->PCR4 = 0x00000018U;
NYX 0:85b3fd62ea1a 998 Device->SR4 = 0x00000000U;
NYX 0:85b3fd62ea1a 999 Device->PMEM4 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 1000 Device->PATT4 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 1001 Device->PIO4 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 1002
NYX 0:85b3fd62ea1a 1003 return HAL_OK;
NYX 0:85b3fd62ea1a 1004 }
NYX 0:85b3fd62ea1a 1005 /**
NYX 0:85b3fd62ea1a 1006 * @}
NYX 0:85b3fd62ea1a 1007 */
NYX 0:85b3fd62ea1a 1008
NYX 0:85b3fd62ea1a 1009 /**
NYX 0:85b3fd62ea1a 1010 * @}
NYX 0:85b3fd62ea1a 1011 */
NYX 0:85b3fd62ea1a 1012 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
NYX 0:85b3fd62ea1a 1013
NYX 0:85b3fd62ea1a 1014 /**
NYX 0:85b3fd62ea1a 1015 * @}
NYX 0:85b3fd62ea1a 1016 */
NYX 0:85b3fd62ea1a 1017 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 1018 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 1019
NYX 0:85b3fd62ea1a 1020 /**
NYX 0:85b3fd62ea1a 1021 * @}
NYX 0:85b3fd62ea1a 1022 */
NYX 0:85b3fd62ea1a 1023
NYX 0:85b3fd62ea1a 1024 /**
NYX 0:85b3fd62ea1a 1025 * @}
NYX 0:85b3fd62ea1a 1026 */
NYX 0:85b3fd62ea1a 1027 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/