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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

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User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_ll_fmc.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of FMC HAL module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_LL_FMC_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_LL_FMC_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	47	#include "stm32f4xx_hal_def.h"
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	/** @addtogroup FMC_LL
NYX	0:85b3fd62ea1a	54	* @{
NYX	0:85b3fd62ea1a	55	*/
NYX	0:85b3fd62ea1a	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
NYX	0:85b3fd62ea1a	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	58	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
NYX	0:85b3fd62ea1a	60	* @{
NYX	0:85b3fd62ea1a	61	*/
NYX	0:85b3fd62ea1a	62
NYX	0:85b3fd62ea1a	63	/**
NYX	0:85b3fd62ea1a	64	* @brief FMC NORSRAM Configuration Structure definition
NYX	0:85b3fd62ea1a	65	*/
NYX	0:85b3fd62ea1a	66	typedef struct
NYX	0:85b3fd62ea1a	67	{
NYX	0:85b3fd62ea1a	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
NYX	0:85b3fd62ea1a	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
NYX	0:85b3fd62ea1a	70
NYX	0:85b3fd62ea1a	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
NYX	0:85b3fd62ea1a	72	multiplexed on the data bus or not.
NYX	0:85b3fd62ea1a	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
NYX	0:85b3fd62ea1a	74
NYX	0:85b3fd62ea1a	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
NYX	0:85b3fd62ea1a	76	the corresponding memory device.
NYX	0:85b3fd62ea1a	77	This parameter can be a value of @ref FMC_Memory_Type */
NYX	0:85b3fd62ea1a	78
NYX	0:85b3fd62ea1a	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
NYX	0:85b3fd62ea1a	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
NYX	0:85b3fd62ea1a	81
NYX	0:85b3fd62ea1a	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
NYX	0:85b3fd62ea1a	83	valid only with synchronous burst Flash memories.
NYX	0:85b3fd62ea1a	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
NYX	0:85b3fd62ea1a	85
NYX	0:85b3fd62ea1a	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
NYX	0:85b3fd62ea1a	87	the Flash memory in burst mode.
NYX	0:85b3fd62ea1a	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
NYX	0:85b3fd62ea1a	89
NYX	0:85b3fd62ea1a	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
NYX	0:85b3fd62ea1a	91	memory, valid only when accessing Flash memories in burst mode.
NYX	0:85b3fd62ea1a	92	This parameter can be a value of @ref FMC_Wrap_Mode
NYX	0:85b3fd62ea1a	93	This mode is not available for the STM32F446/467/479xx devices */
NYX	0:85b3fd62ea1a	94
NYX	0:85b3fd62ea1a	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
NYX	0:85b3fd62ea1a	96	clock cycle before the wait state or during the wait state,
NYX	0:85b3fd62ea1a	97	valid only when accessing memories in burst mode.
NYX	0:85b3fd62ea1a	98	This parameter can be a value of @ref FMC_Wait_Timing */
NYX	0:85b3fd62ea1a	99
NYX	0:85b3fd62ea1a	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
NYX	0:85b3fd62ea1a	101	This parameter can be a value of @ref FMC_Write_Operation */
NYX	0:85b3fd62ea1a	102
NYX	0:85b3fd62ea1a	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
NYX	0:85b3fd62ea1a	104	signal, valid for Flash memory access in burst mode.
NYX	0:85b3fd62ea1a	105	This parameter can be a value of @ref FMC_Wait_Signal */
NYX	0:85b3fd62ea1a	106
NYX	0:85b3fd62ea1a	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
NYX	0:85b3fd62ea1a	108	This parameter can be a value of @ref FMC_Extended_Mode */
NYX	0:85b3fd62ea1a	109
NYX	0:85b3fd62ea1a	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
NYX	0:85b3fd62ea1a	111	valid only with asynchronous Flash memories.
NYX	0:85b3fd62ea1a	112	This parameter can be a value of @ref FMC_AsynchronousWait */
NYX	0:85b3fd62ea1a	113
NYX	0:85b3fd62ea1a	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
NYX	0:85b3fd62ea1a	115	This parameter can be a value of @ref FMC_Write_Burst */
NYX	0:85b3fd62ea1a	116
NYX	0:85b3fd62ea1a	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
NYX	0:85b3fd62ea1a	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
NYX	0:85b3fd62ea1a	119	through FMC_BCR2..4 registers.
NYX	0:85b3fd62ea1a	120	This parameter can be a value of @ref FMC_Continous_Clock */
NYX	0:85b3fd62ea1a	121
NYX	0:85b3fd62ea1a	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
NYX	0:85b3fd62ea1a	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
NYX	0:85b3fd62ea1a	124	through FMC_BCR2..4 registers.
NYX	0:85b3fd62ea1a	125	This parameter can be a value of @ref FMC_Write_FIFO
NYX	0:85b3fd62ea1a	126	This mode is available only for the STM32F446/469/479xx devices */
NYX	0:85b3fd62ea1a	127
NYX	0:85b3fd62ea1a	128	uint32_t PageSize; /*!< Specifies the memory page size.
NYX	0:85b3fd62ea1a	129	This parameter can be a value of @ref FMC_Page_Size */
NYX	0:85b3fd62ea1a	130	}FMC_NORSRAM_InitTypeDef;
NYX	0:85b3fd62ea1a	131
NYX	0:85b3fd62ea1a	132	/**
NYX	0:85b3fd62ea1a	133	* @brief FMC NORSRAM Timing parameters structure definition
NYX	0:85b3fd62ea1a	134	*/
NYX	0:85b3fd62ea1a	135	typedef struct
NYX	0:85b3fd62ea1a	136	{
NYX	0:85b3fd62ea1a	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
NYX	0:85b3fd62ea1a	138	the duration of the address setup time.
NYX	0:85b3fd62ea1a	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
NYX	0:85b3fd62ea1a	140	@note This parameter is not used with synchronous NOR Flash memories. */
NYX	0:85b3fd62ea1a	141
NYX	0:85b3fd62ea1a	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
NYX	0:85b3fd62ea1a	143	the duration of the address hold time.
NYX	0:85b3fd62ea1a	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
NYX	0:85b3fd62ea1a	145	@note This parameter is not used with synchronous NOR Flash memories. */
NYX	0:85b3fd62ea1a	146
NYX	0:85b3fd62ea1a	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
NYX	0:85b3fd62ea1a	148	the duration of the data setup time.
NYX	0:85b3fd62ea1a	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
NYX	0:85b3fd62ea1a	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NYX	0:85b3fd62ea1a	151	NOR Flash memories. */
NYX	0:85b3fd62ea1a	152
NYX	0:85b3fd62ea1a	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
NYX	0:85b3fd62ea1a	154	the duration of the bus turnaround.
NYX	0:85b3fd62ea1a	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
NYX	0:85b3fd62ea1a	156	@note This parameter is only used for multiplexed NOR Flash memories. */
NYX	0:85b3fd62ea1a	157
NYX	0:85b3fd62ea1a	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
NYX	0:85b3fd62ea1a	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
NYX	0:85b3fd62ea1a	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
NYX	0:85b3fd62ea1a	161	accesses. */
NYX	0:85b3fd62ea1a	162
NYX	0:85b3fd62ea1a	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
NYX	0:85b3fd62ea1a	164	to the memory before getting the first data.
NYX	0:85b3fd62ea1a	165	The parameter value depends on the memory type as shown below:
NYX	0:85b3fd62ea1a	166	- It must be set to 0 in case of a CRAM
NYX	0:85b3fd62ea1a	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
NYX	0:85b3fd62ea1a	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
NYX	0:85b3fd62ea1a	169	with synchronous burst mode enable */
NYX	0:85b3fd62ea1a	170
NYX	0:85b3fd62ea1a	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
NYX	0:85b3fd62ea1a	172	This parameter can be a value of @ref FMC_Access_Mode */
NYX	0:85b3fd62ea1a	173	}FMC_NORSRAM_TimingTypeDef;
NYX	0:85b3fd62ea1a	174
NYX	0:85b3fd62ea1a	175	/**
NYX	0:85b3fd62ea1a	176	* @brief FMC NAND Configuration Structure definition
NYX	0:85b3fd62ea1a	177	*/
NYX	0:85b3fd62ea1a	178	typedef struct
NYX	0:85b3fd62ea1a	179	{
NYX	0:85b3fd62ea1a	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
NYX	0:85b3fd62ea1a	181	This parameter can be a value of @ref FMC_NAND_Bank */
NYX	0:85b3fd62ea1a	182
NYX	0:85b3fd62ea1a	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
NYX	0:85b3fd62ea1a	184	This parameter can be any value of @ref FMC_Wait_feature */
NYX	0:85b3fd62ea1a	185
NYX	0:85b3fd62ea1a	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
NYX	0:85b3fd62ea1a	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
NYX	0:85b3fd62ea1a	188
NYX	0:85b3fd62ea1a	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
NYX	0:85b3fd62ea1a	190	This parameter can be any value of @ref FMC_ECC */
NYX	0:85b3fd62ea1a	191
NYX	0:85b3fd62ea1a	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
NYX	0:85b3fd62ea1a	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
NYX	0:85b3fd62ea1a	194
NYX	0:85b3fd62ea1a	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
NYX	0:85b3fd62ea1a	196	delay between CLE low and RE low.
NYX	0:85b3fd62ea1a	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
NYX	0:85b3fd62ea1a	198
NYX	0:85b3fd62ea1a	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
NYX	0:85b3fd62ea1a	200	delay between ALE low and RE low.
NYX	0:85b3fd62ea1a	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX	0:85b3fd62ea1a	202	}FMC_NAND_InitTypeDef;
NYX	0:85b3fd62ea1a	203
NYX	0:85b3fd62ea1a	204	/**
NYX	0:85b3fd62ea1a	205	* @brief FMC NAND/PCCARD Timing parameters structure definition
NYX	0:85b3fd62ea1a	206	*/
NYX	0:85b3fd62ea1a	207	typedef struct
NYX	0:85b3fd62ea1a	208	{
NYX	0:85b3fd62ea1a	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
NYX	0:85b3fd62ea1a	210	the command assertion for NAND-Flash read or write access
NYX	0:85b3fd62ea1a	211	to common/Attribute or I/O memory space (depending on
NYX	0:85b3fd62ea1a	212	the memory space timing to be configured).
NYX	0:85b3fd62ea1a	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
NYX	0:85b3fd62ea1a	214
NYX	0:85b3fd62ea1a	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
NYX	0:85b3fd62ea1a	216	command for NAND-Flash read or write access to
NYX	0:85b3fd62ea1a	217	common/Attribute or I/O memory space (depending on the
NYX	0:85b3fd62ea1a	218	memory space timing to be configured).
NYX	0:85b3fd62ea1a	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX	0:85b3fd62ea1a	220
NYX	0:85b3fd62ea1a	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
NYX	0:85b3fd62ea1a	222	(and data for write access) after the command de-assertion
NYX	0:85b3fd62ea1a	223	for NAND-Flash read or write access to common/Attribute
NYX	0:85b3fd62ea1a	224	or I/O memory space (depending on the memory space timing
NYX	0:85b3fd62ea1a	225	to be configured).
NYX	0:85b3fd62ea1a	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX	0:85b3fd62ea1a	227
NYX	0:85b3fd62ea1a	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
NYX	0:85b3fd62ea1a	229	data bus is kept in HiZ after the start of a NAND-Flash
NYX	0:85b3fd62ea1a	230	write access to common/Attribute or I/O memory space (depending
NYX	0:85b3fd62ea1a	231	on the memory space timing to be configured).
NYX	0:85b3fd62ea1a	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX	0:85b3fd62ea1a	233	}FMC_NAND_PCC_TimingTypeDef;
NYX	0:85b3fd62ea1a	234
NYX	0:85b3fd62ea1a	235	/**
NYX	0:85b3fd62ea1a	236	* @brief FMC NAND Configuration Structure definition
NYX	0:85b3fd62ea1a	237	*/
NYX	0:85b3fd62ea1a	238	typedef struct
NYX	0:85b3fd62ea1a	239	{
NYX	0:85b3fd62ea1a	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
NYX	0:85b3fd62ea1a	241	This parameter can be any value of @ref FMC_Wait_feature */
NYX	0:85b3fd62ea1a	242
NYX	0:85b3fd62ea1a	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
NYX	0:85b3fd62ea1a	244	delay between CLE low and RE low.
NYX	0:85b3fd62ea1a	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
NYX	0:85b3fd62ea1a	246
NYX	0:85b3fd62ea1a	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
NYX	0:85b3fd62ea1a	248	delay between ALE low and RE low.
NYX	0:85b3fd62ea1a	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
NYX	0:85b3fd62ea1a	250	}FMC_PCCARD_InitTypeDef;
NYX	0:85b3fd62ea1a	251
NYX	0:85b3fd62ea1a	252	/**
NYX	0:85b3fd62ea1a	253	* @brief FMC SDRAM Configuration Structure definition
NYX	0:85b3fd62ea1a	254	*/
NYX	0:85b3fd62ea1a	255	typedef struct
NYX	0:85b3fd62ea1a	256	{
NYX	0:85b3fd62ea1a	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
NYX	0:85b3fd62ea1a	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
NYX	0:85b3fd62ea1a	259
NYX	0:85b3fd62ea1a	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
NYX	0:85b3fd62ea1a	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
NYX	0:85b3fd62ea1a	262
NYX	0:85b3fd62ea1a	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
NYX	0:85b3fd62ea1a	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
NYX	0:85b3fd62ea1a	265
NYX	0:85b3fd62ea1a	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
NYX	0:85b3fd62ea1a	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
NYX	0:85b3fd62ea1a	268
NYX	0:85b3fd62ea1a	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
NYX	0:85b3fd62ea1a	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
NYX	0:85b3fd62ea1a	271
NYX	0:85b3fd62ea1a	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
NYX	0:85b3fd62ea1a	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
NYX	0:85b3fd62ea1a	274
NYX	0:85b3fd62ea1a	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
NYX	0:85b3fd62ea1a	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
NYX	0:85b3fd62ea1a	277
NYX	0:85b3fd62ea1a	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
NYX	0:85b3fd62ea1a	279	to disable the clock before changing frequency.
NYX	0:85b3fd62ea1a	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
NYX	0:85b3fd62ea1a	281
NYX	0:85b3fd62ea1a	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
NYX	0:85b3fd62ea1a	283	commands during the CAS latency and stores data in the Read FIFO.
NYX	0:85b3fd62ea1a	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
NYX	0:85b3fd62ea1a	285
NYX	0:85b3fd62ea1a	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
NYX	0:85b3fd62ea1a	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
NYX	0:85b3fd62ea1a	288	}FMC_SDRAM_InitTypeDef;
NYX	0:85b3fd62ea1a	289
NYX	0:85b3fd62ea1a	290	/**
NYX	0:85b3fd62ea1a	291	* @brief FMC SDRAM Timing parameters structure definition
NYX	0:85b3fd62ea1a	292	*/
NYX	0:85b3fd62ea1a	293	typedef struct
NYX	0:85b3fd62ea1a	294	{
NYX	0:85b3fd62ea1a	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
NYX	0:85b3fd62ea1a	296	an active or Refresh command in number of memory clock cycles.
NYX	0:85b3fd62ea1a	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
NYX	0:85b3fd62ea1a	298
NYX	0:85b3fd62ea1a	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
NYX	0:85b3fd62ea1a	300	issuing the Activate command in number of memory clock cycles.
NYX	0:85b3fd62ea1a	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
NYX	0:85b3fd62ea1a	302
NYX	0:85b3fd62ea1a	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
NYX	0:85b3fd62ea1a	304	cycles.
NYX	0:85b3fd62ea1a	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
NYX	0:85b3fd62ea1a	306
NYX	0:85b3fd62ea1a	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
NYX	0:85b3fd62ea1a	308	and the delay between two consecutive Refresh commands in number of
NYX	0:85b3fd62ea1a	309	memory clock cycles.
NYX	0:85b3fd62ea1a	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
NYX	0:85b3fd62ea1a	311
NYX	0:85b3fd62ea1a	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
NYX	0:85b3fd62ea1a	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
NYX	0:85b3fd62ea1a	314
NYX	0:85b3fd62ea1a	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
NYX	0:85b3fd62ea1a	316	in number of memory clock cycles.
NYX	0:85b3fd62ea1a	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
NYX	0:85b3fd62ea1a	318
NYX	0:85b3fd62ea1a	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
NYX	0:85b3fd62ea1a	320	command in number of memory clock cycles.
NYX	0:85b3fd62ea1a	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
NYX	0:85b3fd62ea1a	322	}FMC_SDRAM_TimingTypeDef;
NYX	0:85b3fd62ea1a	323
NYX	0:85b3fd62ea1a	324	/**
NYX	0:85b3fd62ea1a	325	* @brief SDRAM command parameters structure definition
NYX	0:85b3fd62ea1a	326	*/
NYX	0:85b3fd62ea1a	327	typedef struct
NYX	0:85b3fd62ea1a	328	{
NYX	0:85b3fd62ea1a	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
NYX	0:85b3fd62ea1a	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
NYX	0:85b3fd62ea1a	331
NYX	0:85b3fd62ea1a	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
NYX	0:85b3fd62ea1a	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
NYX	0:85b3fd62ea1a	334
NYX	0:85b3fd62ea1a	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
NYX	0:85b3fd62ea1a	336	in auto refresh mode.
NYX	0:85b3fd62ea1a	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
NYX	0:85b3fd62ea1a	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
NYX	0:85b3fd62ea1a	339	}FMC_SDRAM_CommandTypeDef;
NYX	0:85b3fd62ea1a	340	/**
NYX	0:85b3fd62ea1a	341	* @}
NYX	0:85b3fd62ea1a	342	*/
NYX	0:85b3fd62ea1a	343
NYX	0:85b3fd62ea1a	344	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	345	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
NYX	0:85b3fd62ea1a	346	* @{
NYX	0:85b3fd62ea1a	347	*/
NYX	0:85b3fd62ea1a	348
NYX	0:85b3fd62ea1a	349	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
NYX	0:85b3fd62ea1a	350	* @{
NYX	0:85b3fd62ea1a	351	*/
NYX	0:85b3fd62ea1a	352	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
NYX	0:85b3fd62ea1a	353	* @{
NYX	0:85b3fd62ea1a	354	*/
NYX	0:85b3fd62ea1a	355	#define FMC_NORSRAM_BANK1 0x00000000U
NYX	0:85b3fd62ea1a	356	#define FMC_NORSRAM_BANK2 0x00000002U
NYX	0:85b3fd62ea1a	357	#define FMC_NORSRAM_BANK3 0x00000004U
NYX	0:85b3fd62ea1a	358	#define FMC_NORSRAM_BANK4 0x00000006U
NYX	0:85b3fd62ea1a	359	/**
NYX	0:85b3fd62ea1a	360	* @}
NYX	0:85b3fd62ea1a	361	*/
NYX	0:85b3fd62ea1a	362
NYX	0:85b3fd62ea1a	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
NYX	0:85b3fd62ea1a	364	* @{
NYX	0:85b3fd62ea1a	365	*/
NYX	0:85b3fd62ea1a	366	#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	367	#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
NYX	0:85b3fd62ea1a	368	/**
NYX	0:85b3fd62ea1a	369	* @}
NYX	0:85b3fd62ea1a	370	*/
NYX	0:85b3fd62ea1a	371
NYX	0:85b3fd62ea1a	372	/** @defgroup FMC_Memory_Type FMC Memory Type
NYX	0:85b3fd62ea1a	373	* @{
NYX	0:85b3fd62ea1a	374	*/
NYX	0:85b3fd62ea1a	375	#define FMC_MEMORY_TYPE_SRAM 0x00000000U
NYX	0:85b3fd62ea1a	376	#define FMC_MEMORY_TYPE_PSRAM 0x00000004U
NYX	0:85b3fd62ea1a	377	#define FMC_MEMORY_TYPE_NOR 0x00000008U
NYX	0:85b3fd62ea1a	378	/**
NYX	0:85b3fd62ea1a	379	* @}
NYX	0:85b3fd62ea1a	380	*/
NYX	0:85b3fd62ea1a	381
NYX	0:85b3fd62ea1a	382	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
NYX	0:85b3fd62ea1a	383	* @{
NYX	0:85b3fd62ea1a	384	*/
NYX	0:85b3fd62ea1a	385	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
NYX	0:85b3fd62ea1a	386	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
NYX	0:85b3fd62ea1a	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
NYX	0:85b3fd62ea1a	388	/**
NYX	0:85b3fd62ea1a	389	* @}
NYX	0:85b3fd62ea1a	390	*/
NYX	0:85b3fd62ea1a	391
NYX	0:85b3fd62ea1a	392	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
NYX	0:85b3fd62ea1a	393	* @{
NYX	0:85b3fd62ea1a	394	*/
NYX	0:85b3fd62ea1a	395	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
NYX	0:85b3fd62ea1a	396	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	397	/**
NYX	0:85b3fd62ea1a	398	* @}
NYX	0:85b3fd62ea1a	399	*/
NYX	0:85b3fd62ea1a	400
NYX	0:85b3fd62ea1a	401	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
NYX	0:85b3fd62ea1a	402	* @{
NYX	0:85b3fd62ea1a	403	*/
NYX	0:85b3fd62ea1a	404	#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	405	#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
NYX	0:85b3fd62ea1a	406	/**
NYX	0:85b3fd62ea1a	407	* @}
NYX	0:85b3fd62ea1a	408	*/
NYX	0:85b3fd62ea1a	409
NYX	0:85b3fd62ea1a	410	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
NYX	0:85b3fd62ea1a	411	* @{
NYX	0:85b3fd62ea1a	412	*/
NYX	0:85b3fd62ea1a	413	#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
NYX	0:85b3fd62ea1a	414	#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
NYX	0:85b3fd62ea1a	415	/**
NYX	0:85b3fd62ea1a	416	* @}
NYX	0:85b3fd62ea1a	417	*/
NYX	0:85b3fd62ea1a	418
NYX	0:85b3fd62ea1a	419	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
NYX	0:85b3fd62ea1a	420	* @{
NYX	0:85b3fd62ea1a	421	*/
NYX	0:85b3fd62ea1a	422	/** @note This mode is not available for the STM32F446/469/479xx devices
NYX	0:85b3fd62ea1a	423	*/
NYX	0:85b3fd62ea1a	424	#define FMC_WRAP_MODE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	425	#define FMC_WRAP_MODE_ENABLE 0x00000400U
NYX	0:85b3fd62ea1a	426	/**
NYX	0:85b3fd62ea1a	427	* @}
NYX	0:85b3fd62ea1a	428	*/
NYX	0:85b3fd62ea1a	429
NYX	0:85b3fd62ea1a	430	/** @defgroup FMC_Wait_Timing FMC Wait Timing
NYX	0:85b3fd62ea1a	431	* @{
NYX	0:85b3fd62ea1a	432	*/
NYX	0:85b3fd62ea1a	433	#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U
NYX	0:85b3fd62ea1a	434	#define FMC_WAIT_TIMING_DURING_WS 0x00000800U
NYX	0:85b3fd62ea1a	435	/**
NYX	0:85b3fd62ea1a	436	* @}
NYX	0:85b3fd62ea1a	437	*/
NYX	0:85b3fd62ea1a	438
NYX	0:85b3fd62ea1a	439	/** @defgroup FMC_Write_Operation FMC Write Operation
NYX	0:85b3fd62ea1a	440	* @{
NYX	0:85b3fd62ea1a	441	*/
NYX	0:85b3fd62ea1a	442	#define FMC_WRITE_OPERATION_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	443	#define FMC_WRITE_OPERATION_ENABLE 0x00001000U
NYX	0:85b3fd62ea1a	444	/**
NYX	0:85b3fd62ea1a	445	* @}
NYX	0:85b3fd62ea1a	446	*/
NYX	0:85b3fd62ea1a	447
NYX	0:85b3fd62ea1a	448	/** @defgroup FMC_Wait_Signal FMC Wait Signal
NYX	0:85b3fd62ea1a	449	* @{
NYX	0:85b3fd62ea1a	450	*/
NYX	0:85b3fd62ea1a	451	#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	452	#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U
NYX	0:85b3fd62ea1a	453	/**
NYX	0:85b3fd62ea1a	454	* @}
NYX	0:85b3fd62ea1a	455	*/
NYX	0:85b3fd62ea1a	456
NYX	0:85b3fd62ea1a	457	/** @defgroup FMC_Extended_Mode FMC Extended Mode
NYX	0:85b3fd62ea1a	458	* @{
NYX	0:85b3fd62ea1a	459	*/
NYX	0:85b3fd62ea1a	460	#define FMC_EXTENDED_MODE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	461	#define FMC_EXTENDED_MODE_ENABLE 0x00004000U
NYX	0:85b3fd62ea1a	462	/**
NYX	0:85b3fd62ea1a	463	* @}
NYX	0:85b3fd62ea1a	464	*/
NYX	0:85b3fd62ea1a	465
NYX	0:85b3fd62ea1a	466	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
NYX	0:85b3fd62ea1a	467	* @{
NYX	0:85b3fd62ea1a	468	*/
NYX	0:85b3fd62ea1a	469	#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	470	#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
NYX	0:85b3fd62ea1a	471	/**
NYX	0:85b3fd62ea1a	472	* @}
NYX	0:85b3fd62ea1a	473	*/
NYX	0:85b3fd62ea1a	474
NYX	0:85b3fd62ea1a	475	/** @defgroup FMC_Page_Size FMC Page Size
NYX	0:85b3fd62ea1a	476	* @{
NYX	0:85b3fd62ea1a	477	*/
NYX	0:85b3fd62ea1a	478	#define FMC_PAGE_SIZE_NONE 0x00000000U
NYX	0:85b3fd62ea1a	479	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
NYX	0:85b3fd62ea1a	480	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
NYX	0:85b3fd62ea1a	481	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
NYX	0:85b3fd62ea1a	482	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
NYX	0:85b3fd62ea1a	483	/**
NYX	0:85b3fd62ea1a	484	* @}
NYX	0:85b3fd62ea1a	485	*/
NYX	0:85b3fd62ea1a	486
NYX	0:85b3fd62ea1a	487	/** @defgroup FMC_Write_FIFO FMC Write FIFO
NYX	0:85b3fd62ea1a	488	* @note These values are available only for the STM32F446/469/479xx devices.
NYX	0:85b3fd62ea1a	489	* @{
NYX	0:85b3fd62ea1a	490	*/
NYX	0:85b3fd62ea1a	491	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
NYX	0:85b3fd62ea1a	492	#define FMC_WRITE_FIFO_ENABLE 0x00000000U
NYX	0:85b3fd62ea1a	493	/**
NYX	0:85b3fd62ea1a	494	* @}
NYX	0:85b3fd62ea1a	495	*/
NYX	0:85b3fd62ea1a	496
NYX	0:85b3fd62ea1a	497	/** @defgroup FMC_Write_Burst FMC Write Burst
NYX	0:85b3fd62ea1a	498	* @{
NYX	0:85b3fd62ea1a	499	*/
NYX	0:85b3fd62ea1a	500	#define FMC_WRITE_BURST_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	501	#define FMC_WRITE_BURST_ENABLE 0x00080000U
NYX	0:85b3fd62ea1a	502	/**
NYX	0:85b3fd62ea1a	503	* @}
NYX	0:85b3fd62ea1a	504	*/
NYX	0:85b3fd62ea1a	505
NYX	0:85b3fd62ea1a	506	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
NYX	0:85b3fd62ea1a	507	* @{
NYX	0:85b3fd62ea1a	508	*/
NYX	0:85b3fd62ea1a	509	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
NYX	0:85b3fd62ea1a	510	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
NYX	0:85b3fd62ea1a	511	/**
NYX	0:85b3fd62ea1a	512	* @}
NYX	0:85b3fd62ea1a	513	*/
NYX	0:85b3fd62ea1a	514
NYX	0:85b3fd62ea1a	515	/** @defgroup FMC_Access_Mode FMC Access Mode
NYX	0:85b3fd62ea1a	516	* @{
NYX	0:85b3fd62ea1a	517	*/
NYX	0:85b3fd62ea1a	518	#define FMC_ACCESS_MODE_A 0x00000000U
NYX	0:85b3fd62ea1a	519	#define FMC_ACCESS_MODE_B 0x10000000U
NYX	0:85b3fd62ea1a	520	#define FMC_ACCESS_MODE_C 0x20000000U
NYX	0:85b3fd62ea1a	521	#define FMC_ACCESS_MODE_D 0x30000000U
NYX	0:85b3fd62ea1a	522	/**
NYX	0:85b3fd62ea1a	523	* @}
NYX	0:85b3fd62ea1a	524	*/
NYX	0:85b3fd62ea1a	525
NYX	0:85b3fd62ea1a	526	/**
NYX	0:85b3fd62ea1a	527	* @}
NYX	0:85b3fd62ea1a	528	*/
NYX	0:85b3fd62ea1a	529
NYX	0:85b3fd62ea1a	530	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
NYX	0:85b3fd62ea1a	531	* @{
NYX	0:85b3fd62ea1a	532	*/
NYX	0:85b3fd62ea1a	533	/** @defgroup FMC_NAND_Bank FMC NAND Bank
NYX	0:85b3fd62ea1a	534	* @{
NYX	0:85b3fd62ea1a	535	*/
NYX	0:85b3fd62ea1a	536	#define FMC_NAND_BANK2 0x00000010U
NYX	0:85b3fd62ea1a	537	#define FMC_NAND_BANK3 0x00000100U
NYX	0:85b3fd62ea1a	538	/**
NYX	0:85b3fd62ea1a	539	* @}
NYX	0:85b3fd62ea1a	540	*/
NYX	0:85b3fd62ea1a	541
NYX	0:85b3fd62ea1a	542	/** @defgroup FMC_Wait_feature FMC Wait feature
NYX	0:85b3fd62ea1a	543	* @{
NYX	0:85b3fd62ea1a	544	*/
NYX	0:85b3fd62ea1a	545	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	546	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
NYX	0:85b3fd62ea1a	547	/**
NYX	0:85b3fd62ea1a	548	* @}
NYX	0:85b3fd62ea1a	549	*/
NYX	0:85b3fd62ea1a	550
NYX	0:85b3fd62ea1a	551	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
NYX	0:85b3fd62ea1a	552	* @{
NYX	0:85b3fd62ea1a	553	*/
NYX	0:85b3fd62ea1a	554	#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
NYX	0:85b3fd62ea1a	555	#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U
NYX	0:85b3fd62ea1a	556	/**
NYX	0:85b3fd62ea1a	557	* @}
NYX	0:85b3fd62ea1a	558	*/
NYX	0:85b3fd62ea1a	559
NYX	0:85b3fd62ea1a	560	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
NYX	0:85b3fd62ea1a	561	* @{
NYX	0:85b3fd62ea1a	562	*/
NYX	0:85b3fd62ea1a	563	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
NYX	0:85b3fd62ea1a	564	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
NYX	0:85b3fd62ea1a	565	/**
NYX	0:85b3fd62ea1a	566	* @}
NYX	0:85b3fd62ea1a	567	*/
NYX	0:85b3fd62ea1a	568
NYX	0:85b3fd62ea1a	569	/** @defgroup FMC_ECC FMC ECC
NYX	0:85b3fd62ea1a	570	* @{
NYX	0:85b3fd62ea1a	571	*/
NYX	0:85b3fd62ea1a	572	#define FMC_NAND_ECC_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	573	#define FMC_NAND_ECC_ENABLE 0x00000040U
NYX	0:85b3fd62ea1a	574	/**
NYX	0:85b3fd62ea1a	575	* @}
NYX	0:85b3fd62ea1a	576	*/
NYX	0:85b3fd62ea1a	577
NYX	0:85b3fd62ea1a	578	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
NYX	0:85b3fd62ea1a	579	* @{
NYX	0:85b3fd62ea1a	580	*/
NYX	0:85b3fd62ea1a	581	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
NYX	0:85b3fd62ea1a	582	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
NYX	0:85b3fd62ea1a	583	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
NYX	0:85b3fd62ea1a	584	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
NYX	0:85b3fd62ea1a	585	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
NYX	0:85b3fd62ea1a	586	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
NYX	0:85b3fd62ea1a	587	/**
NYX	0:85b3fd62ea1a	588	* @}
NYX	0:85b3fd62ea1a	589	*/
NYX	0:85b3fd62ea1a	590
NYX	0:85b3fd62ea1a	591	/**
NYX	0:85b3fd62ea1a	592	* @}
NYX	0:85b3fd62ea1a	593	*/
NYX	0:85b3fd62ea1a	594
NYX	0:85b3fd62ea1a	595	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
NYX	0:85b3fd62ea1a	596	* @{
NYX	0:85b3fd62ea1a	597	*/
NYX	0:85b3fd62ea1a	598	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
NYX	0:85b3fd62ea1a	599	* @{
NYX	0:85b3fd62ea1a	600	*/
NYX	0:85b3fd62ea1a	601	#define FMC_SDRAM_BANK1 0x00000000U
NYX	0:85b3fd62ea1a	602	#define FMC_SDRAM_BANK2 0x00000001U
NYX	0:85b3fd62ea1a	603	/**
NYX	0:85b3fd62ea1a	604	* @}
NYX	0:85b3fd62ea1a	605	*/
NYX	0:85b3fd62ea1a	606
NYX	0:85b3fd62ea1a	607	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
NYX	0:85b3fd62ea1a	608	* @{
NYX	0:85b3fd62ea1a	609	*/
NYX	0:85b3fd62ea1a	610	#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U
NYX	0:85b3fd62ea1a	611	#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U
NYX	0:85b3fd62ea1a	612	#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U
NYX	0:85b3fd62ea1a	613	#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U
NYX	0:85b3fd62ea1a	614	/**
NYX	0:85b3fd62ea1a	615	* @}
NYX	0:85b3fd62ea1a	616	*/
NYX	0:85b3fd62ea1a	617
NYX	0:85b3fd62ea1a	618	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
NYX	0:85b3fd62ea1a	619	* @{
NYX	0:85b3fd62ea1a	620	*/
NYX	0:85b3fd62ea1a	621	#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U
NYX	0:85b3fd62ea1a	622	#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U
NYX	0:85b3fd62ea1a	623	#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U
NYX	0:85b3fd62ea1a	624	/**
NYX	0:85b3fd62ea1a	625	* @}
NYX	0:85b3fd62ea1a	626	*/
NYX	0:85b3fd62ea1a	627
NYX	0:85b3fd62ea1a	628	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
NYX	0:85b3fd62ea1a	629	* @{
NYX	0:85b3fd62ea1a	630	*/
NYX	0:85b3fd62ea1a	631	#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U
NYX	0:85b3fd62ea1a	632	#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U
NYX	0:85b3fd62ea1a	633	#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U
NYX	0:85b3fd62ea1a	634	/**
NYX	0:85b3fd62ea1a	635	* @}
NYX	0:85b3fd62ea1a	636	*/
NYX	0:85b3fd62ea1a	637
NYX	0:85b3fd62ea1a	638	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
NYX	0:85b3fd62ea1a	639	* @{
NYX	0:85b3fd62ea1a	640	*/
NYX	0:85b3fd62ea1a	641	#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U
NYX	0:85b3fd62ea1a	642	#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U
NYX	0:85b3fd62ea1a	643	/**
NYX	0:85b3fd62ea1a	644	* @}
NYX	0:85b3fd62ea1a	645	*/
NYX	0:85b3fd62ea1a	646
NYX	0:85b3fd62ea1a	647	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
NYX	0:85b3fd62ea1a	648	* @{
NYX	0:85b3fd62ea1a	649	*/
NYX	0:85b3fd62ea1a	650	#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U
NYX	0:85b3fd62ea1a	651	#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U
NYX	0:85b3fd62ea1a	652	#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U
NYX	0:85b3fd62ea1a	653	/**
NYX	0:85b3fd62ea1a	654	* @}
NYX	0:85b3fd62ea1a	655	*/
NYX	0:85b3fd62ea1a	656
NYX	0:85b3fd62ea1a	657	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
NYX	0:85b3fd62ea1a	658	* @{
NYX	0:85b3fd62ea1a	659	*/
NYX	0:85b3fd62ea1a	660	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	661	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U
NYX	0:85b3fd62ea1a	662
NYX	0:85b3fd62ea1a	663	/**
NYX	0:85b3fd62ea1a	664	* @}
NYX	0:85b3fd62ea1a	665	*/
NYX	0:85b3fd62ea1a	666
NYX	0:85b3fd62ea1a	667	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
NYX	0:85b3fd62ea1a	668	* @{
NYX	0:85b3fd62ea1a	669	*/
NYX	0:85b3fd62ea1a	670	#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	671	#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U
NYX	0:85b3fd62ea1a	672	#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U
NYX	0:85b3fd62ea1a	673	/**
NYX	0:85b3fd62ea1a	674	* @}
NYX	0:85b3fd62ea1a	675	*/
NYX	0:85b3fd62ea1a	676
NYX	0:85b3fd62ea1a	677	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
NYX	0:85b3fd62ea1a	678	* @{
NYX	0:85b3fd62ea1a	679	*/
NYX	0:85b3fd62ea1a	680	#define FMC_SDRAM_RBURST_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	681	#define FMC_SDRAM_RBURST_ENABLE 0x00001000U
NYX	0:85b3fd62ea1a	682	/**
NYX	0:85b3fd62ea1a	683	* @}
NYX	0:85b3fd62ea1a	684	*/
NYX	0:85b3fd62ea1a	685
NYX	0:85b3fd62ea1a	686	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
NYX	0:85b3fd62ea1a	687	* @{
NYX	0:85b3fd62ea1a	688	*/
NYX	0:85b3fd62ea1a	689	#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U
NYX	0:85b3fd62ea1a	690	#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U
NYX	0:85b3fd62ea1a	691	#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U
NYX	0:85b3fd62ea1a	692	/**
NYX	0:85b3fd62ea1a	693	* @}
NYX	0:85b3fd62ea1a	694	*/
NYX	0:85b3fd62ea1a	695
NYX	0:85b3fd62ea1a	696	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
NYX	0:85b3fd62ea1a	697	* @{
NYX	0:85b3fd62ea1a	698	*/
NYX	0:85b3fd62ea1a	699	#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U
NYX	0:85b3fd62ea1a	700	#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U
NYX	0:85b3fd62ea1a	701	#define FMC_SDRAM_CMD_PALL 0x00000002U
NYX	0:85b3fd62ea1a	702	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U
NYX	0:85b3fd62ea1a	703	#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U
NYX	0:85b3fd62ea1a	704	#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U
NYX	0:85b3fd62ea1a	705	#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U
NYX	0:85b3fd62ea1a	706	/**
NYX	0:85b3fd62ea1a	707	* @}
NYX	0:85b3fd62ea1a	708	*/
NYX	0:85b3fd62ea1a	709
NYX	0:85b3fd62ea1a	710	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
NYX	0:85b3fd62ea1a	711	* @{
NYX	0:85b3fd62ea1a	712	*/
NYX	0:85b3fd62ea1a	713	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
NYX	0:85b3fd62ea1a	714	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
NYX	0:85b3fd62ea1a	715	#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U
NYX	0:85b3fd62ea1a	716	/**
NYX	0:85b3fd62ea1a	717	* @}
NYX	0:85b3fd62ea1a	718	*/
NYX	0:85b3fd62ea1a	719
NYX	0:85b3fd62ea1a	720	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
NYX	0:85b3fd62ea1a	721	* @{
NYX	0:85b3fd62ea1a	722	*/
NYX	0:85b3fd62ea1a	723	#define FMC_SDRAM_NORMAL_MODE 0x00000000U
NYX	0:85b3fd62ea1a	724	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
NYX	0:85b3fd62ea1a	725	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
NYX	0:85b3fd62ea1a	726	/**
NYX	0:85b3fd62ea1a	727	* @}
NYX	0:85b3fd62ea1a	728	*/
NYX	0:85b3fd62ea1a	729
NYX	0:85b3fd62ea1a	730	/**
NYX	0:85b3fd62ea1a	731	* @}
NYX	0:85b3fd62ea1a	732	*/
NYX	0:85b3fd62ea1a	733
NYX	0:85b3fd62ea1a	734	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
NYX	0:85b3fd62ea1a	735	* @{
NYX	0:85b3fd62ea1a	736	*/
NYX	0:85b3fd62ea1a	737	#define FMC_IT_RISING_EDGE 0x00000008U
NYX	0:85b3fd62ea1a	738	#define FMC_IT_LEVEL 0x00000010U
NYX	0:85b3fd62ea1a	739	#define FMC_IT_FALLING_EDGE 0x00000020U
NYX	0:85b3fd62ea1a	740	#define FMC_IT_REFRESH_ERROR 0x00004000U
NYX	0:85b3fd62ea1a	741	/**
NYX	0:85b3fd62ea1a	742	* @}
NYX	0:85b3fd62ea1a	743	*/
NYX	0:85b3fd62ea1a	744
NYX	0:85b3fd62ea1a	745	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
NYX	0:85b3fd62ea1a	746	* @{
NYX	0:85b3fd62ea1a	747	*/
NYX	0:85b3fd62ea1a	748	#define FMC_FLAG_RISING_EDGE 0x00000001U
NYX	0:85b3fd62ea1a	749	#define FMC_FLAG_LEVEL 0x00000002U
NYX	0:85b3fd62ea1a	750	#define FMC_FLAG_FALLING_EDGE 0x00000004U
NYX	0:85b3fd62ea1a	751	#define FMC_FLAG_FEMPT 0x00000040U
NYX	0:85b3fd62ea1a	752	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
NYX	0:85b3fd62ea1a	753	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
NYX	0:85b3fd62ea1a	754	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
NYX	0:85b3fd62ea1a	755	/**
NYX	0:85b3fd62ea1a	756	* @}
NYX	0:85b3fd62ea1a	757	*/
NYX	0:85b3fd62ea1a	758
NYX	0:85b3fd62ea1a	759	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
NYX	0:85b3fd62ea1a	760	* @{
NYX	0:85b3fd62ea1a	761	*/
NYX	0:85b3fd62ea1a	762	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	763	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
NYX	0:85b3fd62ea1a	764	#else
NYX	0:85b3fd62ea1a	765	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
NYX	0:85b3fd62ea1a	766	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
NYX	0:85b3fd62ea1a	767	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	768	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
NYX	0:85b3fd62ea1a	769	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
NYX	0:85b3fd62ea1a	770	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
NYX	0:85b3fd62ea1a	771
NYX	0:85b3fd62ea1a	772
NYX	0:85b3fd62ea1a	773	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	774	#define FMC_NAND_DEVICE FMC_Bank3
NYX	0:85b3fd62ea1a	775	#else
NYX	0:85b3fd62ea1a	776	#define FMC_NAND_DEVICE FMC_Bank2_3
NYX	0:85b3fd62ea1a	777	#define FMC_PCCARD_DEVICE FMC_Bank4
NYX	0:85b3fd62ea1a	778	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	779	#define FMC_NORSRAM_DEVICE FMC_Bank1
NYX	0:85b3fd62ea1a	780	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
NYX	0:85b3fd62ea1a	781	#define FMC_SDRAM_DEVICE FMC_Bank5_6
NYX	0:85b3fd62ea1a	782	/**
NYX	0:85b3fd62ea1a	783	* @}
NYX	0:85b3fd62ea1a	784	*/
NYX	0:85b3fd62ea1a	785
NYX	0:85b3fd62ea1a	786	/**
NYX	0:85b3fd62ea1a	787	* @}
NYX	0:85b3fd62ea1a	788	*/
NYX	0:85b3fd62ea1a	789
NYX	0:85b3fd62ea1a	790	/* Private macro -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	791	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
NYX	0:85b3fd62ea1a	792	* @{
NYX	0:85b3fd62ea1a	793	*/
NYX	0:85b3fd62ea1a	794
NYX	0:85b3fd62ea1a	795	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
NYX	0:85b3fd62ea1a	796	* @brief macros to handle NOR device enable/disable and read/write operations
NYX	0:85b3fd62ea1a	797	* @{
NYX	0:85b3fd62ea1a	798	*/
NYX	0:85b3fd62ea1a	799	/**
NYX	0:85b3fd62ea1a	800	* @brief Enable the NORSRAM device access.
NYX	0:85b3fd62ea1a	801	* @param __INSTANCE__: FMC_NORSRAM Instance
NYX	0:85b3fd62ea1a	802	* @param __BANK__: FMC_NORSRAM Bank
NYX	0:85b3fd62ea1a	803	* @retval None
NYX	0:85b3fd62ea1a	804	*/
NYX	0:85b3fd62ea1a	805	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
NYX	0:85b3fd62ea1a	806
NYX	0:85b3fd62ea1a	807	/**
NYX	0:85b3fd62ea1a	808	* @brief Disable the NORSRAM device access.
NYX	0:85b3fd62ea1a	809	* @param __INSTANCE__: FMC_NORSRAM Instance
NYX	0:85b3fd62ea1a	810	* @param __BANK__: FMC_NORSRAM Bank
NYX	0:85b3fd62ea1a	811	* @retval None
NYX	0:85b3fd62ea1a	812	*/
NYX	0:85b3fd62ea1a	813	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
NYX	0:85b3fd62ea1a	814	/**
NYX	0:85b3fd62ea1a	815	* @}
NYX	0:85b3fd62ea1a	816	*/
NYX	0:85b3fd62ea1a	817
NYX	0:85b3fd62ea1a	818	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
NYX	0:85b3fd62ea1a	819	* @brief macros to handle NAND device enable/disable
NYX	0:85b3fd62ea1a	820	* @{
NYX	0:85b3fd62ea1a	821	*/
NYX	0:85b3fd62ea1a	822	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	823	/**
NYX	0:85b3fd62ea1a	824	* @brief Enable the NAND device access.
NYX	0:85b3fd62ea1a	825	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	826	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	827	* @retval None
NYX	0:85b3fd62ea1a	828	*/
NYX	0:85b3fd62ea1a	829	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
NYX	0:85b3fd62ea1a	830
NYX	0:85b3fd62ea1a	831	/**
NYX	0:85b3fd62ea1a	832	* @brief Disable the NAND device access.
NYX	0:85b3fd62ea1a	833	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	834	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	835	* @retval None
NYX	0:85b3fd62ea1a	836	*/
NYX	0:85b3fd62ea1a	837	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
NYX	0:85b3fd62ea1a	838	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
NYX	0:85b3fd62ea1a	839	/**
NYX	0:85b3fd62ea1a	840	* @brief Enable the NAND device access.
NYX	0:85b3fd62ea1a	841	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	842	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	843	* @retval None
NYX	0:85b3fd62ea1a	844	*/
NYX	0:85b3fd62ea1a	845	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
NYX	0:85b3fd62ea1a	846	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
NYX	0:85b3fd62ea1a	847
NYX	0:85b3fd62ea1a	848	/**
NYX	0:85b3fd62ea1a	849	* @brief Disable the NAND device access.
NYX	0:85b3fd62ea1a	850	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	851	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	852	* @retval None
NYX	0:85b3fd62ea1a	853	*/
NYX	0:85b3fd62ea1a	854	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
NYX	0:85b3fd62ea1a	855	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
NYX	0:85b3fd62ea1a	856
NYX	0:85b3fd62ea1a	857	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
NYX	0:85b3fd62ea1a	858	/**
NYX	0:85b3fd62ea1a	859	* @}
NYX	0:85b3fd62ea1a	860	*/
NYX	0:85b3fd62ea1a	861	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
NYX	0:85b3fd62ea1a	862	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
NYX	0:85b3fd62ea1a	863	* @brief macros to handle SRAM read/write operations
NYX	0:85b3fd62ea1a	864	* @{
NYX	0:85b3fd62ea1a	865	*/
NYX	0:85b3fd62ea1a	866	/**
NYX	0:85b3fd62ea1a	867	* @brief Enable the PCCARD device access.
NYX	0:85b3fd62ea1a	868	* @param __INSTANCE__: FMC_PCCARD Instance
NYX	0:85b3fd62ea1a	869	* @retval None
NYX	0:85b3fd62ea1a	870	*/
NYX	0:85b3fd62ea1a	871	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
NYX	0:85b3fd62ea1a	872
NYX	0:85b3fd62ea1a	873	/**
NYX	0:85b3fd62ea1a	874	* @brief Disable the PCCARD device access.
NYX	0:85b3fd62ea1a	875	* @param __INSTANCE__: FMC_PCCARD Instance
NYX	0:85b3fd62ea1a	876	* @retval None
NYX	0:85b3fd62ea1a	877	*/
NYX	0:85b3fd62ea1a	878	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
NYX	0:85b3fd62ea1a	879	/**
NYX	0:85b3fd62ea1a	880	* @}
NYX	0:85b3fd62ea1a	881	*/
NYX	0:85b3fd62ea1a	882	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
NYX	0:85b3fd62ea1a	883
NYX	0:85b3fd62ea1a	884	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
NYX	0:85b3fd62ea1a	885	* @brief macros to handle FMC flags and interrupts
NYX	0:85b3fd62ea1a	886	* @{
NYX	0:85b3fd62ea1a	887	*/
NYX	0:85b3fd62ea1a	888	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	889	/**
NYX	0:85b3fd62ea1a	890	* @brief Enable the NAND device interrupt.
NYX	0:85b3fd62ea1a	891	* @param __INSTANCE__: FMC_NAND instance
NYX	0:85b3fd62ea1a	892	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	893	* @param __INTERRUPT__: FMC_NAND interrupt
NYX	0:85b3fd62ea1a	894	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	895	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
NYX	0:85b3fd62ea1a	896	* @arg FMC_IT_LEVEL: Interrupt level.
NYX	0:85b3fd62ea1a	897	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX	0:85b3fd62ea1a	898	* @retval None
NYX	0:85b3fd62ea1a	899	*/
NYX	0:85b3fd62ea1a	900	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
NYX	0:85b3fd62ea1a	901
NYX	0:85b3fd62ea1a	902	/**
NYX	0:85b3fd62ea1a	903	* @brief Disable the NAND device interrupt.
NYX	0:85b3fd62ea1a	904	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	905	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	906	* @param __INTERRUPT__: FMC_NAND interrupt
NYX	0:85b3fd62ea1a	907	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	908	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
NYX	0:85b3fd62ea1a	909	* @arg FMC_IT_LEVEL: Interrupt level.
NYX	0:85b3fd62ea1a	910	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX	0:85b3fd62ea1a	911	* @retval None
NYX	0:85b3fd62ea1a	912	*/
NYX	0:85b3fd62ea1a	913	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
NYX	0:85b3fd62ea1a	914
NYX	0:85b3fd62ea1a	915	/**
NYX	0:85b3fd62ea1a	916	* @brief Get flag status of the NAND device.
NYX	0:85b3fd62ea1a	917	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	918	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	919	* @param __FLAG__: FMC_NAND flag
NYX	0:85b3fd62ea1a	920	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	921	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX	0:85b3fd62ea1a	922	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
NYX	0:85b3fd62ea1a	923	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX	0:85b3fd62ea1a	924	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
NYX	0:85b3fd62ea1a	925	* @retval The state of FLAG (SET or RESET).
NYX	0:85b3fd62ea1a	926	*/
NYX	0:85b3fd62ea1a	927	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
NYX	0:85b3fd62ea1a	928	/**
NYX	0:85b3fd62ea1a	929	* @brief Clear flag status of the NAND device.
NYX	0:85b3fd62ea1a	930	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	931	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	932	* @param __FLAG__: FMC_NAND flag
NYX	0:85b3fd62ea1a	933	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	934	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX	0:85b3fd62ea1a	935	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
NYX	0:85b3fd62ea1a	936	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX	0:85b3fd62ea1a	937	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
NYX	0:85b3fd62ea1a	938	* @retval None
NYX	0:85b3fd62ea1a	939	*/
NYX	0:85b3fd62ea1a	940	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
NYX	0:85b3fd62ea1a	941	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
NYX	0:85b3fd62ea1a	942	/**
NYX	0:85b3fd62ea1a	943	* @brief Enable the NAND device interrupt.
NYX	0:85b3fd62ea1a	944	* @param __INSTANCE__: FMC_NAND instance
NYX	0:85b3fd62ea1a	945	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	946	* @param __INTERRUPT__: FMC_NAND interrupt
NYX	0:85b3fd62ea1a	947	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	948	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
NYX	0:85b3fd62ea1a	949	* @arg FMC_IT_LEVEL: Interrupt level.
NYX	0:85b3fd62ea1a	950	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX	0:85b3fd62ea1a	951	* @retval None
NYX	0:85b3fd62ea1a	952	*/
NYX	0:85b3fd62ea1a	953	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
NYX	0:85b3fd62ea1a	954	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
NYX	0:85b3fd62ea1a	955
NYX	0:85b3fd62ea1a	956	/**
NYX	0:85b3fd62ea1a	957	* @brief Disable the NAND device interrupt.
NYX	0:85b3fd62ea1a	958	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	959	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	960	* @param __INTERRUPT__: FMC_NAND interrupt
NYX	0:85b3fd62ea1a	961	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	962	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
NYX	0:85b3fd62ea1a	963	* @arg FMC_IT_LEVEL: Interrupt level.
NYX	0:85b3fd62ea1a	964	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX	0:85b3fd62ea1a	965	* @retval None
NYX	0:85b3fd62ea1a	966	*/
NYX	0:85b3fd62ea1a	967	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
NYX	0:85b3fd62ea1a	968	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
NYX	0:85b3fd62ea1a	969
NYX	0:85b3fd62ea1a	970	/**
NYX	0:85b3fd62ea1a	971	* @brief Get flag status of the NAND device.
NYX	0:85b3fd62ea1a	972	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	973	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	974	* @param __FLAG__: FMC_NAND flag
NYX	0:85b3fd62ea1a	975	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	976	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX	0:85b3fd62ea1a	977	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
NYX	0:85b3fd62ea1a	978	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX	0:85b3fd62ea1a	979	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
NYX	0:85b3fd62ea1a	980	* @retval The state of FLAG (SET or RESET).
NYX	0:85b3fd62ea1a	981	*/
NYX	0:85b3fd62ea1a	982	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
NYX	0:85b3fd62ea1a	983	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
NYX	0:85b3fd62ea1a	984	/**
NYX	0:85b3fd62ea1a	985	* @brief Clear flag status of the NAND device.
NYX	0:85b3fd62ea1a	986	* @param __INSTANCE__: FMC_NAND Instance
NYX	0:85b3fd62ea1a	987	* @param __BANK__: FMC_NAND Bank
NYX	0:85b3fd62ea1a	988	* @param __FLAG__: FMC_NAND flag
NYX	0:85b3fd62ea1a	989	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	990	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX	0:85b3fd62ea1a	991	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
NYX	0:85b3fd62ea1a	992	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX	0:85b3fd62ea1a	993	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
NYX	0:85b3fd62ea1a	994	* @retval None
NYX	0:85b3fd62ea1a	995	*/
NYX	0:85b3fd62ea1a	996	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
NYX	0:85b3fd62ea1a	997	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
NYX	0:85b3fd62ea1a	998	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
NYX	0:85b3fd62ea1a	999
NYX	0:85b3fd62ea1a	1000	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
NYX	0:85b3fd62ea1a	1001	/**
NYX	0:85b3fd62ea1a	1002	* @brief Enable the PCCARD device interrupt.
NYX	0:85b3fd62ea1a	1003	* @param __INSTANCE__: FMC_PCCARD instance
NYX	0:85b3fd62ea1a	1004	* @param __INTERRUPT__: FMC_PCCARD interrupt
NYX	0:85b3fd62ea1a	1005	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1006	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
NYX	0:85b3fd62ea1a	1007	* @arg FMC_IT_LEVEL: Interrupt level.
NYX	0:85b3fd62ea1a	1008	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX	0:85b3fd62ea1a	1009	* @retval None
NYX	0:85b3fd62ea1a	1010	*/
NYX	0:85b3fd62ea1a	1011	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
NYX	0:85b3fd62ea1a	1012
NYX	0:85b3fd62ea1a	1013	/**
NYX	0:85b3fd62ea1a	1014	* @brief Disable the PCCARD device interrupt.
NYX	0:85b3fd62ea1a	1015	* @param __INSTANCE__: FMC_PCCARD instance
NYX	0:85b3fd62ea1a	1016	* @param __INTERRUPT__: FMC_PCCARD interrupt
NYX	0:85b3fd62ea1a	1017	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1018	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
NYX	0:85b3fd62ea1a	1019	* @arg FMC_IT_LEVEL: Interrupt level.
NYX	0:85b3fd62ea1a	1020	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
NYX	0:85b3fd62ea1a	1021	* @retval None
NYX	0:85b3fd62ea1a	1022	*/
NYX	0:85b3fd62ea1a	1023	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
NYX	0:85b3fd62ea1a	1024
NYX	0:85b3fd62ea1a	1025	/**
NYX	0:85b3fd62ea1a	1026	* @brief Get flag status of the PCCARD device.
NYX	0:85b3fd62ea1a	1027	* @param __INSTANCE__: FMC_PCCARD instance
NYX	0:85b3fd62ea1a	1028	* @param __FLAG__: FMC_PCCARD flag
NYX	0:85b3fd62ea1a	1029	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1030	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX	0:85b3fd62ea1a	1031	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
NYX	0:85b3fd62ea1a	1032	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX	0:85b3fd62ea1a	1033	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
NYX	0:85b3fd62ea1a	1034	* @retval The state of FLAG (SET or RESET).
NYX	0:85b3fd62ea1a	1035	*/
NYX	0:85b3fd62ea1a	1036	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
NYX	0:85b3fd62ea1a	1037
NYX	0:85b3fd62ea1a	1038	/**
NYX	0:85b3fd62ea1a	1039	* @brief Clear flag status of the PCCARD device.
NYX	0:85b3fd62ea1a	1040	* @param __INSTANCE__: FMC_PCCARD instance
NYX	0:85b3fd62ea1a	1041	* @param __FLAG__: FMC_PCCARD flag
NYX	0:85b3fd62ea1a	1042	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1043	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
NYX	0:85b3fd62ea1a	1044	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
NYX	0:85b3fd62ea1a	1045	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
NYX	0:85b3fd62ea1a	1046	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
NYX	0:85b3fd62ea1a	1047	* @retval None
NYX	0:85b3fd62ea1a	1048	*/
NYX	0:85b3fd62ea1a	1049	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
NYX	0:85b3fd62ea1a	1050	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
NYX	0:85b3fd62ea1a	1051
NYX	0:85b3fd62ea1a	1052	/**
NYX	0:85b3fd62ea1a	1053	* @brief Enable the SDRAM device interrupt.
NYX	0:85b3fd62ea1a	1054	* @param __INSTANCE__: FMC_SDRAM instance
NYX	0:85b3fd62ea1a	1055	* @param __INTERRUPT__: FMC_SDRAM interrupt
NYX	0:85b3fd62ea1a	1056	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1057	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
NYX	0:85b3fd62ea1a	1058	* @retval None
NYX	0:85b3fd62ea1a	1059	*/
NYX	0:85b3fd62ea1a	1060	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
NYX	0:85b3fd62ea1a	1061
NYX	0:85b3fd62ea1a	1062	/**
NYX	0:85b3fd62ea1a	1063	* @brief Disable the SDRAM device interrupt.
NYX	0:85b3fd62ea1a	1064	* @param __INSTANCE__: FMC_SDRAM instance
NYX	0:85b3fd62ea1a	1065	* @param __INTERRUPT__: FMC_SDRAM interrupt
NYX	0:85b3fd62ea1a	1066	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1067	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
NYX	0:85b3fd62ea1a	1068	* @retval None
NYX	0:85b3fd62ea1a	1069	*/
NYX	0:85b3fd62ea1a	1070	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
NYX	0:85b3fd62ea1a	1071
NYX	0:85b3fd62ea1a	1072	/**
NYX	0:85b3fd62ea1a	1073	* @brief Get flag status of the SDRAM device.
NYX	0:85b3fd62ea1a	1074	* @param __INSTANCE__: FMC_SDRAM instance
NYX	0:85b3fd62ea1a	1075	* @param __FLAG__: FMC_SDRAM flag
NYX	0:85b3fd62ea1a	1076	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1077	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
NYX	0:85b3fd62ea1a	1078	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
NYX	0:85b3fd62ea1a	1079	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
NYX	0:85b3fd62ea1a	1080	* @retval The state of FLAG (SET or RESET).
NYX	0:85b3fd62ea1a	1081	*/
NYX	0:85b3fd62ea1a	1082	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
NYX	0:85b3fd62ea1a	1083
NYX	0:85b3fd62ea1a	1084	/**
NYX	0:85b3fd62ea1a	1085	* @brief Clear flag status of the SDRAM device.
NYX	0:85b3fd62ea1a	1086	* @param __INSTANCE__: FMC_SDRAM instance
NYX	0:85b3fd62ea1a	1087	* @param __FLAG__: FMC_SDRAM flag
NYX	0:85b3fd62ea1a	1088	* This parameter can be any combination of the following values:
NYX	0:85b3fd62ea1a	1089	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
NYX	0:85b3fd62ea1a	1090	* @retval None
NYX	0:85b3fd62ea1a	1091	*/
NYX	0:85b3fd62ea1a	1092	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
NYX	0:85b3fd62ea1a	1093	/**
NYX	0:85b3fd62ea1a	1094	* @}
NYX	0:85b3fd62ea1a	1095	*/
NYX	0:85b3fd62ea1a	1096
NYX	0:85b3fd62ea1a	1097	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
NYX	0:85b3fd62ea1a	1098	* @{
NYX	0:85b3fd62ea1a	1099	*/
NYX	0:85b3fd62ea1a	1100	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
NYX	0:85b3fd62ea1a	1101	((BANK) == FMC_NORSRAM_BANK2) \|\| \
NYX	0:85b3fd62ea1a	1102	((BANK) == FMC_NORSRAM_BANK3) \|\| \
NYX	0:85b3fd62ea1a	1103	((BANK) == FMC_NORSRAM_BANK4))
NYX	0:85b3fd62ea1a	1104
NYX	0:85b3fd62ea1a	1105	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1106	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
NYX	0:85b3fd62ea1a	1107
NYX	0:85b3fd62ea1a	1108	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
NYX	0:85b3fd62ea1a	1109	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
NYX	0:85b3fd62ea1a	1110	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
NYX	0:85b3fd62ea1a	1111
NYX	0:85b3fd62ea1a	1112	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
NYX	0:85b3fd62ea1a	1113	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
NYX	0:85b3fd62ea1a	1114	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
NYX	0:85b3fd62ea1a	1115
NYX	0:85b3fd62ea1a	1116	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
NYX	0:85b3fd62ea1a	1117	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
NYX	0:85b3fd62ea1a	1118	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
NYX	0:85b3fd62ea1a	1119	((__MODE__) == FMC_ACCESS_MODE_D))
NYX	0:85b3fd62ea1a	1120
NYX	0:85b3fd62ea1a	1121	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
NYX	0:85b3fd62ea1a	1122	((BANK) == FMC_NAND_BANK3))
NYX	0:85b3fd62ea1a	1123
NYX	0:85b3fd62ea1a	1124	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1125	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
NYX	0:85b3fd62ea1a	1126
NYX	0:85b3fd62ea1a	1127	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
NYX	0:85b3fd62ea1a	1128	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
NYX	0:85b3fd62ea1a	1129
NYX	0:85b3fd62ea1a	1130	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1131	((STATE) == FMC_NAND_ECC_ENABLE))
NYX	0:85b3fd62ea1a	1132
NYX	0:85b3fd62ea1a	1133	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
NYX	0:85b3fd62ea1a	1134	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
NYX	0:85b3fd62ea1a	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
NYX	0:85b3fd62ea1a	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
NYX	0:85b3fd62ea1a	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
NYX	0:85b3fd62ea1a	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
NYX	0:85b3fd62ea1a	1139
NYX	0:85b3fd62ea1a	1140	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
NYX	0:85b3fd62ea1a	1141
NYX	0:85b3fd62ea1a	1142	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
NYX	0:85b3fd62ea1a	1143
NYX	0:85b3fd62ea1a	1144	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
NYX	0:85b3fd62ea1a	1145
NYX	0:85b3fd62ea1a	1146	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
NYX	0:85b3fd62ea1a	1147
NYX	0:85b3fd62ea1a	1148	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
NYX	0:85b3fd62ea1a	1149
NYX	0:85b3fd62ea1a	1150	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
NYX	0:85b3fd62ea1a	1151
NYX	0:85b3fd62ea1a	1152	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
NYX	0:85b3fd62ea1a	1153
NYX	0:85b3fd62ea1a	1154	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
NYX	0:85b3fd62ea1a	1155
NYX	0:85b3fd62ea1a	1156	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
NYX	0:85b3fd62ea1a	1157
NYX	0:85b3fd62ea1a	1158	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
NYX	0:85b3fd62ea1a	1159
NYX	0:85b3fd62ea1a	1160	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1161	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
NYX	0:85b3fd62ea1a	1162
NYX	0:85b3fd62ea1a	1163	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
NYX	0:85b3fd62ea1a	1164	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
NYX	0:85b3fd62ea1a	1165
NYX	0:85b3fd62ea1a	1166	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
NYX	0:85b3fd62ea1a	1167	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1168	((__MODE__) == FMC_WRAP_MODE_ENABLE))
NYX	0:85b3fd62ea1a	1169	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
NYX	0:85b3fd62ea1a	1170
NYX	0:85b3fd62ea1a	1171	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
NYX	0:85b3fd62ea1a	1172	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
NYX	0:85b3fd62ea1a	1173
NYX	0:85b3fd62ea1a	1174	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1175	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
NYX	0:85b3fd62ea1a	1176
NYX	0:85b3fd62ea1a	1177	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1178	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
NYX	0:85b3fd62ea1a	1179
NYX	0:85b3fd62ea1a	1180	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1181	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
NYX	0:85b3fd62ea1a	1182
NYX	0:85b3fd62ea1a	1183	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1184	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
NYX	0:85b3fd62ea1a	1185
NYX	0:85b3fd62ea1a	1186	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1187	((__BURST__) == FMC_WRITE_BURST_ENABLE))
NYX	0:85b3fd62ea1a	1188
NYX	0:85b3fd62ea1a	1189	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
NYX	0:85b3fd62ea1a	1190	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
NYX	0:85b3fd62ea1a	1191
NYX	0:85b3fd62ea1a	1192	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
NYX	0:85b3fd62ea1a	1193
NYX	0:85b3fd62ea1a	1194	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
NYX	0:85b3fd62ea1a	1195
NYX	0:85b3fd62ea1a	1196	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
NYX	0:85b3fd62ea1a	1197
NYX	0:85b3fd62ea1a	1198	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
NYX	0:85b3fd62ea1a	1199
NYX	0:85b3fd62ea1a	1200	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
NYX	0:85b3fd62ea1a	1201
NYX	0:85b3fd62ea1a	1202	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
NYX	0:85b3fd62ea1a	1203
NYX	0:85b3fd62ea1a	1204	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
NYX	0:85b3fd62ea1a	1205	((BANK) == FMC_SDRAM_BANK2))
NYX	0:85b3fd62ea1a	1206
NYX	0:85b3fd62ea1a	1207	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
NYX	0:85b3fd62ea1a	1208	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
NYX	0:85b3fd62ea1a	1209	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
NYX	0:85b3fd62ea1a	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
NYX	0:85b3fd62ea1a	1211
NYX	0:85b3fd62ea1a	1212	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
NYX	0:85b3fd62ea1a	1213	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
NYX	0:85b3fd62ea1a	1214	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
NYX	0:85b3fd62ea1a	1215
NYX	0:85b3fd62ea1a	1216	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
NYX	0:85b3fd62ea1a	1217	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
NYX	0:85b3fd62ea1a	1218	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
NYX	0:85b3fd62ea1a	1219
NYX	0:85b3fd62ea1a	1220	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
NYX	0:85b3fd62ea1a	1221	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
NYX	0:85b3fd62ea1a	1222
NYX	0:85b3fd62ea1a	1223
NYX	0:85b3fd62ea1a	1224	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
NYX	0:85b3fd62ea1a	1225	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
NYX	0:85b3fd62ea1a	1226	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
NYX	0:85b3fd62ea1a	1227
NYX	0:85b3fd62ea1a	1228	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1229	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
NYX	0:85b3fd62ea1a	1230	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
NYX	0:85b3fd62ea1a	1231
NYX	0:85b3fd62ea1a	1232	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1233	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
NYX	0:85b3fd62ea1a	1234
NYX	0:85b3fd62ea1a	1235
NYX	0:85b3fd62ea1a	1236	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
NYX	0:85b3fd62ea1a	1237	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
NYX	0:85b3fd62ea1a	1238	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
NYX	0:85b3fd62ea1a	1239
NYX	0:85b3fd62ea1a	1240	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
NYX	0:85b3fd62ea1a	1241
NYX	0:85b3fd62ea1a	1242	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
NYX	0:85b3fd62ea1a	1243
NYX	0:85b3fd62ea1a	1244	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
NYX	0:85b3fd62ea1a	1245
NYX	0:85b3fd62ea1a	1246	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
NYX	0:85b3fd62ea1a	1247
NYX	0:85b3fd62ea1a	1248	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
NYX	0:85b3fd62ea1a	1249
NYX	0:85b3fd62ea1a	1250	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
NYX	0:85b3fd62ea1a	1251
NYX	0:85b3fd62ea1a	1252	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
NYX	0:85b3fd62ea1a	1253
NYX	0:85b3fd62ea1a	1254	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
NYX	0:85b3fd62ea1a	1255	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	1256	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
NYX	0:85b3fd62ea1a	1257	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
NYX	0:85b3fd62ea1a	1258	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
NYX	0:85b3fd62ea1a	1259	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
NYX	0:85b3fd62ea1a	1260	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
NYX	0:85b3fd62ea1a	1261
NYX	0:85b3fd62ea1a	1262	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
NYX	0:85b3fd62ea1a	1263	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
NYX	0:85b3fd62ea1a	1264	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
NYX	0:85b3fd62ea1a	1265
NYX	0:85b3fd62ea1a	1266	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
NYX	0:85b3fd62ea1a	1267
NYX	0:85b3fd62ea1a	1268	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
NYX	0:85b3fd62ea1a	1269
NYX	0:85b3fd62ea1a	1270	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
NYX	0:85b3fd62ea1a	1271
NYX	0:85b3fd62ea1a	1272	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
NYX	0:85b3fd62ea1a	1273
NYX	0:85b3fd62ea1a	1274	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1275	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
NYX	0:85b3fd62ea1a	1276
NYX	0:85b3fd62ea1a	1277	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
NYX	0:85b3fd62ea1a	1278	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
NYX	0:85b3fd62ea1a	1279	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
NYX	0:85b3fd62ea1a	1280	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
NYX	0:85b3fd62ea1a	1281	((SIZE) == FMC_PAGE_SIZE_1024))
NYX	0:85b3fd62ea1a	1282
NYX	0:85b3fd62ea1a	1283	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
NYX	0:85b3fd62ea1a	1284	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1285	((FIFO) == FMC_WRITE_FIFO_ENABLE))
NYX	0:85b3fd62ea1a	1286	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1287
NYX	0:85b3fd62ea1a	1288	/**
NYX	0:85b3fd62ea1a	1289	* @}
NYX	0:85b3fd62ea1a	1290	*/
NYX	0:85b3fd62ea1a	1291
NYX	0:85b3fd62ea1a	1292	/**
NYX	0:85b3fd62ea1a	1293	* @}
NYX	0:85b3fd62ea1a	1294	*/
NYX	0:85b3fd62ea1a	1295
NYX	0:85b3fd62ea1a	1296	/* Private functions ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1297	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
NYX	0:85b3fd62ea1a	1298	* @{
NYX	0:85b3fd62ea1a	1299	*/
NYX	0:85b3fd62ea1a	1300
NYX	0:85b3fd62ea1a	1301	/** @defgroup FMC_LL_NORSRAM NOR SRAM
NYX	0:85b3fd62ea1a	1302	* @{
NYX	0:85b3fd62ea1a	1303	*/
NYX	0:85b3fd62ea1a	1304	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
NYX	0:85b3fd62ea1a	1305	* @{
NYX	0:85b3fd62ea1a	1306	*/
NYX	0:85b3fd62ea1a	1307	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
NYX	0:85b3fd62ea1a	1308	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
NYX	0:85b3fd62ea1a	1309	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
NYX	0:85b3fd62ea1a	1310	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
NYX	0:85b3fd62ea1a	1311	/**
NYX	0:85b3fd62ea1a	1312	* @}
NYX	0:85b3fd62ea1a	1313	*/
NYX	0:85b3fd62ea1a	1314
NYX	0:85b3fd62ea1a	1315	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
NYX	0:85b3fd62ea1a	1316	* @{
NYX	0:85b3fd62ea1a	1317	*/
NYX	0:85b3fd62ea1a	1318	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1320	/**
NYX	0:85b3fd62ea1a	1321	* @}
NYX	0:85b3fd62ea1a	1322	*/
NYX	0:85b3fd62ea1a	1323	/**
NYX	0:85b3fd62ea1a	1324	* @}
NYX	0:85b3fd62ea1a	1325	*/
NYX	0:85b3fd62ea1a	1326
NYX	0:85b3fd62ea1a	1327	/** @defgroup FMC_LL_NAND NAND
NYX	0:85b3fd62ea1a	1328	* @{
NYX	0:85b3fd62ea1a	1329	*/
NYX	0:85b3fd62ea1a	1330	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
NYX	0:85b3fd62ea1a	1331	* @{
NYX	0:85b3fd62ea1a	1332	*/
NYX	0:85b3fd62ea1a	1333	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
NYX	0:85b3fd62ea1a	1334	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
NYX	0:85b3fd62ea1a	1335	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
NYX	0:85b3fd62ea1a	1336	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1337	/**
NYX	0:85b3fd62ea1a	1338	* @}
NYX	0:85b3fd62ea1a	1339	*/
NYX	0:85b3fd62ea1a	1340
NYX	0:85b3fd62ea1a	1341	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
NYX	0:85b3fd62ea1a	1342	* @{
NYX	0:85b3fd62ea1a	1343	*/
NYX	0:85b3fd62ea1a	1344	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1345	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1346	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
NYX	0:85b3fd62ea1a	1347
NYX	0:85b3fd62ea1a	1348	/**
NYX	0:85b3fd62ea1a	1349	* @}
NYX	0:85b3fd62ea1a	1350	*/
NYX	0:85b3fd62ea1a	1351	/**
NYX	0:85b3fd62ea1a	1352	* @}
NYX	0:85b3fd62ea1a	1353	*/
NYX	0:85b3fd62ea1a	1354	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
NYX	0:85b3fd62ea1a	1355	/** @defgroup FMC_LL_PCCARD PCCARD
NYX	0:85b3fd62ea1a	1356	* @{
NYX	0:85b3fd62ea1a	1357	*/
NYX	0:85b3fd62ea1a	1358	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
NYX	0:85b3fd62ea1a	1359	* @{
NYX	0:85b3fd62ea1a	1360	*/
NYX	0:85b3fd62ea1a	1361	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
NYX	0:85b3fd62ea1a	1362	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
NYX	0:85b3fd62ea1a	1363	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
NYX	0:85b3fd62ea1a	1364	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
NYX	0:85b3fd62ea1a	1365	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
NYX	0:85b3fd62ea1a	1366	/**
NYX	0:85b3fd62ea1a	1367	* @}
NYX	0:85b3fd62ea1a	1368	*/
NYX	0:85b3fd62ea1a	1369	/**
NYX	0:85b3fd62ea1a	1370	* @}
NYX	0:85b3fd62ea1a	1371	*/
NYX	0:85b3fd62ea1a	1372	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
NYX	0:85b3fd62ea1a	1373
NYX	0:85b3fd62ea1a	1374	/** @defgroup FMC_LL_SDRAM SDRAM
NYX	0:85b3fd62ea1a	1375	* @{
NYX	0:85b3fd62ea1a	1376	*/
NYX	0:85b3fd62ea1a	1377	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
NYX	0:85b3fd62ea1a	1378	* @{
NYX	0:85b3fd62ea1a	1379	*/
NYX	0:85b3fd62ea1a	1380	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
NYX	0:85b3fd62ea1a	1381	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
NYX	0:85b3fd62ea1a	1382	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1383	/**
NYX	0:85b3fd62ea1a	1384	* @}
NYX	0:85b3fd62ea1a	1385	*/
NYX	0:85b3fd62ea1a	1386
NYX	0:85b3fd62ea1a	1387	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
NYX	0:85b3fd62ea1a	1388	* @{
NYX	0:85b3fd62ea1a	1389	*/
NYX	0:85b3fd62ea1a	1390	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1392	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
NYX	0:85b3fd62ea1a	1393	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
NYX	0:85b3fd62ea1a	1394	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
NYX	0:85b3fd62ea1a	1395	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
NYX	0:85b3fd62ea1a	1396	/**
NYX	0:85b3fd62ea1a	1397	* @}
NYX	0:85b3fd62ea1a	1398	*/
NYX	0:85b3fd62ea1a	1399	/**
NYX	0:85b3fd62ea1a	1400	* @}
NYX	0:85b3fd62ea1a	1401	*/
NYX	0:85b3fd62ea1a	1402
NYX	0:85b3fd62ea1a	1403	/**
NYX	0:85b3fd62ea1a	1404	* @}
NYX	0:85b3fd62ea1a	1405	*/
NYX	0:85b3fd62ea1a	1406
NYX	0:85b3fd62ea1a	1407	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
NYX	0:85b3fd62ea1a	1408	/**
NYX	0:85b3fd62ea1a	1409	* @}
NYX	0:85b3fd62ea1a	1410	*/
NYX	0:85b3fd62ea1a	1411
NYX	0:85b3fd62ea1a	1412	/**
NYX	0:85b3fd62ea1a	1413	* @}
NYX	0:85b3fd62ea1a	1414	*/
NYX	0:85b3fd62ea1a	1415	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	1416	}
NYX	0:85b3fd62ea1a	1417	#endif
NYX	0:85b3fd62ea1a	1418
NYX	0:85b3fd62ea1a	1419	#endif /* __STM32F4xx_LL_FMC_H */
NYX	0:85b3fd62ea1a	1420
NYX	0:85b3fd62ea1a	1421	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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