Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_fmc.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief FMC Low Layer HAL module driver.
NYX 0:85b3fd62ea1a 8 *
NYX 0:85b3fd62ea1a 9 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
NYX 0:85b3fd62ea1a 11 * + Initialization/de-initialization functions
NYX 0:85b3fd62ea1a 12 * + Peripheral Control functions
NYX 0:85b3fd62ea1a 13 * + Peripheral State functions
NYX 0:85b3fd62ea1a 14 *
NYX 0:85b3fd62ea1a 15 @verbatim
NYX 0:85b3fd62ea1a 16 ==============================================================================
NYX 0:85b3fd62ea1a 17 ##### FMC peripheral features #####
NYX 0:85b3fd62ea1a 18 ==============================================================================
NYX 0:85b3fd62ea1a 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
NYX 0:85b3fd62ea1a 20 (+) The NOR/PSRAM memory controller
NYX 0:85b3fd62ea1a 21 (+) The NAND/PC Card memory controller
NYX 0:85b3fd62ea1a 22 (+) The Synchronous DRAM (SDRAM) controller
NYX 0:85b3fd62ea1a 23
NYX 0:85b3fd62ea1a 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
NYX 0:85b3fd62ea1a 25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
NYX 0:85b3fd62ea1a 26 (+) to translate AHB transactions into the appropriate external device protocol
NYX 0:85b3fd62ea1a 27 (+) to meet the access time requirements of the external memory devices
NYX 0:85b3fd62ea1a 28
NYX 0:85b3fd62ea1a 29 [..] All external memories share the addresses, data and control signals with the controller.
NYX 0:85b3fd62ea1a 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
NYX 0:85b3fd62ea1a 31 only one access at a time to an external device.
NYX 0:85b3fd62ea1a 32 The main features of the FMC controller are the following:
NYX 0:85b3fd62ea1a 33 (+) Interface with static-memory mapped devices including:
NYX 0:85b3fd62ea1a 34 (++) Static random access memory (SRAM)
NYX 0:85b3fd62ea1a 35 (++) Read-only memory (ROM)
NYX 0:85b3fd62ea1a 36 (++) NOR Flash memory/OneNAND Flash memory
NYX 0:85b3fd62ea1a 37 (++) PSRAM (4 memory banks)
NYX 0:85b3fd62ea1a 38 (++) 16-bit PC Card compatible devices
NYX 0:85b3fd62ea1a 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
NYX 0:85b3fd62ea1a 40 data
NYX 0:85b3fd62ea1a 41 (+) Interface with synchronous DRAM (SDRAM) memories
NYX 0:85b3fd62ea1a 42 (+) Independent Chip Select control for each memory bank
NYX 0:85b3fd62ea1a 43 (+) Independent configuration for each memory bank
NYX 0:85b3fd62ea1a 44
NYX 0:85b3fd62ea1a 45 @endverbatim
NYX 0:85b3fd62ea1a 46 ******************************************************************************
NYX 0:85b3fd62ea1a 47 * @attention
NYX 0:85b3fd62ea1a 48 *
NYX 0:85b3fd62ea1a 49 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 50 *
NYX 0:85b3fd62ea1a 51 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 52 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 53 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 54 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 55 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 56 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 57 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 59 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 60 * without specific prior written permission.
NYX 0:85b3fd62ea1a 61 *
NYX 0:85b3fd62ea1a 62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 72 *
NYX 0:85b3fd62ea1a 73 ******************************************************************************
NYX 0:85b3fd62ea1a 74 */
NYX 0:85b3fd62ea1a 75
NYX 0:85b3fd62ea1a 76 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 77 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 78
NYX 0:85b3fd62ea1a 79 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 80 * @{
NYX 0:85b3fd62ea1a 81 */
NYX 0:85b3fd62ea1a 82
NYX 0:85b3fd62ea1a 83 /** @defgroup FMC_LL FMC Low Layer
NYX 0:85b3fd62ea1a 84 * @brief FMC driver modules
NYX 0:85b3fd62ea1a 85 * @{
NYX 0:85b3fd62ea1a 86 */
NYX 0:85b3fd62ea1a 87
NYX 0:85b3fd62ea1a 88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
NYX 0:85b3fd62ea1a 89
NYX 0:85b3fd62ea1a 90 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 91
NYX 0:85b3fd62ea1a 92 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 93 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 94 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 95 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 96 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 97 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 98 /** @addtogroup FMC_LL_Private_Functions
NYX 0:85b3fd62ea1a 99 * @{
NYX 0:85b3fd62ea1a 100 */
NYX 0:85b3fd62ea1a 101
NYX 0:85b3fd62ea1a 102 /** @addtogroup FMC_LL_NORSRAM
NYX 0:85b3fd62ea1a 103 * @brief NORSRAM Controller functions
NYX 0:85b3fd62ea1a 104 *
NYX 0:85b3fd62ea1a 105 @verbatim
NYX 0:85b3fd62ea1a 106 ==============================================================================
NYX 0:85b3fd62ea1a 107 ##### How to use NORSRAM device driver #####
NYX 0:85b3fd62ea1a 108 ==============================================================================
NYX 0:85b3fd62ea1a 109
NYX 0:85b3fd62ea1a 110 [..]
NYX 0:85b3fd62ea1a 111 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
NYX 0:85b3fd62ea1a 112 to run the NORSRAM external devices.
NYX 0:85b3fd62ea1a 113
NYX 0:85b3fd62ea1a 114 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
NYX 0:85b3fd62ea1a 115 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
NYX 0:85b3fd62ea1a 116 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
NYX 0:85b3fd62ea1a 117 (+) FMC NORSRAM bank extended timing configuration using the function
NYX 0:85b3fd62ea1a 118 FMC_NORSRAM_Extended_Timing_Init()
NYX 0:85b3fd62ea1a 119 (+) FMC NORSRAM bank enable/disable write operation using the functions
NYX 0:85b3fd62ea1a 120 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
NYX 0:85b3fd62ea1a 121
NYX 0:85b3fd62ea1a 122
NYX 0:85b3fd62ea1a 123 @endverbatim
NYX 0:85b3fd62ea1a 124 * @{
NYX 0:85b3fd62ea1a 125 */
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
NYX 0:85b3fd62ea1a 128 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 129 *
NYX 0:85b3fd62ea1a 130 @verbatim
NYX 0:85b3fd62ea1a 131 ==============================================================================
NYX 0:85b3fd62ea1a 132 ##### Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 133 ==============================================================================
NYX 0:85b3fd62ea1a 134 [..]
NYX 0:85b3fd62ea1a 135 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 136 (+) Initialize and configure the FMC NORSRAM interface
NYX 0:85b3fd62ea1a 137 (+) De-initialize the FMC NORSRAM interface
NYX 0:85b3fd62ea1a 138 (+) Configure the FMC clock and associated GPIOs
NYX 0:85b3fd62ea1a 139
NYX 0:85b3fd62ea1a 140 @endverbatim
NYX 0:85b3fd62ea1a 141 * @{
NYX 0:85b3fd62ea1a 142 */
NYX 0:85b3fd62ea1a 143
NYX 0:85b3fd62ea1a 144 /**
NYX 0:85b3fd62ea1a 145 * @brief Initialize the FMC_NORSRAM device according to the specified
NYX 0:85b3fd62ea1a 146 * control parameters in the FMC_NORSRAM_InitTypeDef
NYX 0:85b3fd62ea1a 147 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 148 * @param Init: Pointer to NORSRAM Initialization structure
NYX 0:85b3fd62ea1a 149 * @retval HAL status
NYX 0:85b3fd62ea1a 150 */
NYX 0:85b3fd62ea1a 151 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
NYX 0:85b3fd62ea1a 152 {
NYX 0:85b3fd62ea1a 153 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 154
NYX 0:85b3fd62ea1a 155 /* Check the parameters */
NYX 0:85b3fd62ea1a 156 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 157 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
NYX 0:85b3fd62ea1a 158 assert_param(IS_FMC_MUX(Init->DataAddressMux));
NYX 0:85b3fd62ea1a 159 assert_param(IS_FMC_MEMORY(Init->MemoryType));
NYX 0:85b3fd62ea1a 160 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
NYX 0:85b3fd62ea1a 161 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
NYX 0:85b3fd62ea1a 162 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
NYX 0:85b3fd62ea1a 163 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
NYX 0:85b3fd62ea1a 164 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
NYX 0:85b3fd62ea1a 165 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
NYX 0:85b3fd62ea1a 166 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
NYX 0:85b3fd62ea1a 167 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
NYX 0:85b3fd62ea1a 168 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
NYX 0:85b3fd62ea1a 169 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
NYX 0:85b3fd62ea1a 170 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
NYX 0:85b3fd62ea1a 171 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
NYX 0:85b3fd62ea1a 172 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
NYX 0:85b3fd62ea1a 173 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
NYX 0:85b3fd62ea1a 174 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 175 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
NYX 0:85b3fd62ea1a 176 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 177
NYX 0:85b3fd62ea1a 178 /* Get the BTCR register value */
NYX 0:85b3fd62ea1a 179 tmpr = Device->BTCR[Init->NSBank];
NYX 0:85b3fd62ea1a 180
NYX 0:85b3fd62ea1a 181 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
NYX 0:85b3fd62ea1a 182 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
NYX 0:85b3fd62ea1a 183 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */
NYX 0:85b3fd62ea1a 184 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
NYX 0:85b3fd62ea1a 185 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
NYX 0:85b3fd62ea1a 186 FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \
NYX 0:85b3fd62ea1a 187 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
NYX 0:85b3fd62ea1a 188 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \
NYX 0:85b3fd62ea1a 189 FMC_BCR1_CCLKEN));
NYX 0:85b3fd62ea1a 190
NYX 0:85b3fd62ea1a 191 /* Set NORSRAM device control parameters */
NYX 0:85b3fd62ea1a 192 tmpr |= (uint32_t)(Init->DataAddressMux |\
NYX 0:85b3fd62ea1a 193 Init->MemoryType |\
NYX 0:85b3fd62ea1a 194 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 195 Init->BurstAccessMode |\
NYX 0:85b3fd62ea1a 196 Init->WaitSignalPolarity |\
NYX 0:85b3fd62ea1a 197 Init->WrapMode |\
NYX 0:85b3fd62ea1a 198 Init->WaitSignalActive |\
NYX 0:85b3fd62ea1a 199 Init->WriteOperation |\
NYX 0:85b3fd62ea1a 200 Init->WaitSignal |\
NYX 0:85b3fd62ea1a 201 Init->ExtendedMode |\
NYX 0:85b3fd62ea1a 202 Init->AsynchronousWait |\
NYX 0:85b3fd62ea1a 203 Init->PageSize |\
NYX 0:85b3fd62ea1a 204 Init->WriteBurst |\
NYX 0:85b3fd62ea1a 205 Init->ContinuousClock);
NYX 0:85b3fd62ea1a 206 #else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
NYX 0:85b3fd62ea1a 207 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
NYX 0:85b3fd62ea1a 208 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
NYX 0:85b3fd62ea1a 209 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
NYX 0:85b3fd62ea1a 210 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
NYX 0:85b3fd62ea1a 211 FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \
NYX 0:85b3fd62ea1a 212 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
NYX 0:85b3fd62ea1a 213 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \
NYX 0:85b3fd62ea1a 214 FMC_BCR1_WFDIS));
NYX 0:85b3fd62ea1a 215
NYX 0:85b3fd62ea1a 216 /* Set NORSRAM device control parameters */
NYX 0:85b3fd62ea1a 217 tmpr |= (uint32_t)(Init->DataAddressMux |\
NYX 0:85b3fd62ea1a 218 Init->MemoryType |\
NYX 0:85b3fd62ea1a 219 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 220 Init->BurstAccessMode |\
NYX 0:85b3fd62ea1a 221 Init->WaitSignalPolarity |\
NYX 0:85b3fd62ea1a 222 Init->WaitSignalActive |\
NYX 0:85b3fd62ea1a 223 Init->WriteOperation |\
NYX 0:85b3fd62ea1a 224 Init->WaitSignal |\
NYX 0:85b3fd62ea1a 225 Init->ExtendedMode |\
NYX 0:85b3fd62ea1a 226 Init->AsynchronousWait |\
NYX 0:85b3fd62ea1a 227 Init->WriteBurst |\
NYX 0:85b3fd62ea1a 228 Init->ContinuousClock |\
NYX 0:85b3fd62ea1a 229 Init->PageSize |\
NYX 0:85b3fd62ea1a 230 Init->WriteFifo);
NYX 0:85b3fd62ea1a 231 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
NYX 0:85b3fd62ea1a 232
NYX 0:85b3fd62ea1a 233 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
NYX 0:85b3fd62ea1a 234 {
NYX 0:85b3fd62ea1a 235 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
NYX 0:85b3fd62ea1a 236 }
NYX 0:85b3fd62ea1a 237
NYX 0:85b3fd62ea1a 238 Device->BTCR[Init->NSBank] = tmpr;
NYX 0:85b3fd62ea1a 239
NYX 0:85b3fd62ea1a 240 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
NYX 0:85b3fd62ea1a 241 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
NYX 0:85b3fd62ea1a 242 {
NYX 0:85b3fd62ea1a 243 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
NYX 0:85b3fd62ea1a 244 }
NYX 0:85b3fd62ea1a 245
NYX 0:85b3fd62ea1a 246 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 247 if(Init->NSBank != FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 248 {
NYX 0:85b3fd62ea1a 249 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
NYX 0:85b3fd62ea1a 250 }
NYX 0:85b3fd62ea1a 251 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 252
NYX 0:85b3fd62ea1a 253 return HAL_OK;
NYX 0:85b3fd62ea1a 254 }
NYX 0:85b3fd62ea1a 255
NYX 0:85b3fd62ea1a 256 /**
NYX 0:85b3fd62ea1a 257 * @brief DeInitialize the FMC_NORSRAM peripheral
NYX 0:85b3fd62ea1a 258 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 259 * @param ExDevice: Pointer to NORSRAM extended mode device instance
NYX 0:85b3fd62ea1a 260 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 261 * @retval HAL status
NYX 0:85b3fd62ea1a 262 */
NYX 0:85b3fd62ea1a 263 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
NYX 0:85b3fd62ea1a 264 {
NYX 0:85b3fd62ea1a 265 /* Check the parameters */
NYX 0:85b3fd62ea1a 266 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 267 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
NYX 0:85b3fd62ea1a 268 assert_param(IS_FMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 269
NYX 0:85b3fd62ea1a 270 /* Disable the FMC_NORSRAM device */
NYX 0:85b3fd62ea1a 271 __FMC_NORSRAM_DISABLE(Device, Bank);
NYX 0:85b3fd62ea1a 272
NYX 0:85b3fd62ea1a 273 /* De-initialize the FMC_NORSRAM device */
NYX 0:85b3fd62ea1a 274 /* FMC_NORSRAM_BANK1 */
NYX 0:85b3fd62ea1a 275 if(Bank == FMC_NORSRAM_BANK1)
NYX 0:85b3fd62ea1a 276 {
NYX 0:85b3fd62ea1a 277 Device->BTCR[Bank] = 0x000030DBU;
NYX 0:85b3fd62ea1a 278 }
NYX 0:85b3fd62ea1a 279 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
NYX 0:85b3fd62ea1a 280 else
NYX 0:85b3fd62ea1a 281 {
NYX 0:85b3fd62ea1a 282 Device->BTCR[Bank] = 0x000030D2U;
NYX 0:85b3fd62ea1a 283 }
NYX 0:85b3fd62ea1a 284
NYX 0:85b3fd62ea1a 285 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
NYX 0:85b3fd62ea1a 286 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
NYX 0:85b3fd62ea1a 287
NYX 0:85b3fd62ea1a 288 return HAL_OK;
NYX 0:85b3fd62ea1a 289 }
NYX 0:85b3fd62ea1a 290
NYX 0:85b3fd62ea1a 291 /**
NYX 0:85b3fd62ea1a 292 * @brief Initialize the FMC_NORSRAM Timing according to the specified
NYX 0:85b3fd62ea1a 293 * parameters in the FMC_NORSRAM_TimingTypeDef
NYX 0:85b3fd62ea1a 294 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 295 * @param Timing: Pointer to NORSRAM Timing structure
NYX 0:85b3fd62ea1a 296 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 297 * @retval HAL status
NYX 0:85b3fd62ea1a 298 */
NYX 0:85b3fd62ea1a 299 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 300 {
NYX 0:85b3fd62ea1a 301 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 302
NYX 0:85b3fd62ea1a 303 /* Check the parameters */
NYX 0:85b3fd62ea1a 304 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 305 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
NYX 0:85b3fd62ea1a 306 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
NYX 0:85b3fd62ea1a 307 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
NYX 0:85b3fd62ea1a 308 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
NYX 0:85b3fd62ea1a 309 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
NYX 0:85b3fd62ea1a 310 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
NYX 0:85b3fd62ea1a 311 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
NYX 0:85b3fd62ea1a 312 assert_param(IS_FMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 313
NYX 0:85b3fd62ea1a 314 /* Get the BTCR register value */
NYX 0:85b3fd62ea1a 315 tmpr = Device->BTCR[Bank + 1U];
NYX 0:85b3fd62ea1a 316
NYX 0:85b3fd62ea1a 317 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
NYX 0:85b3fd62ea1a 318 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
NYX 0:85b3fd62ea1a 319 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
NYX 0:85b3fd62ea1a 320 FMC_BTR1_ACCMOD));
NYX 0:85b3fd62ea1a 321
NYX 0:85b3fd62ea1a 322 /* Set FMC_NORSRAM device timing parameters */
NYX 0:85b3fd62ea1a 323 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
NYX 0:85b3fd62ea1a 324 ((Timing->AddressHoldTime) << 4U) |\
NYX 0:85b3fd62ea1a 325 ((Timing->DataSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 326 ((Timing->BusTurnAroundDuration) << 16U) |\
NYX 0:85b3fd62ea1a 327 (((Timing->CLKDivision) - 1U) << 20U) |\
NYX 0:85b3fd62ea1a 328 (((Timing->DataLatency) - 2U) << 24U) |\
NYX 0:85b3fd62ea1a 329 (Timing->AccessMode));
NYX 0:85b3fd62ea1a 330
NYX 0:85b3fd62ea1a 331 Device->BTCR[Bank + 1U] = tmpr;
NYX 0:85b3fd62ea1a 332
NYX 0:85b3fd62ea1a 333 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
NYX 0:85b3fd62ea1a 334 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
NYX 0:85b3fd62ea1a 335 {
NYX 0:85b3fd62ea1a 336 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
NYX 0:85b3fd62ea1a 337 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U);
NYX 0:85b3fd62ea1a 338 Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr;
NYX 0:85b3fd62ea1a 339 }
NYX 0:85b3fd62ea1a 340
NYX 0:85b3fd62ea1a 341 return HAL_OK;
NYX 0:85b3fd62ea1a 342 }
NYX 0:85b3fd62ea1a 343
NYX 0:85b3fd62ea1a 344 /**
NYX 0:85b3fd62ea1a 345 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
NYX 0:85b3fd62ea1a 346 * parameters in the FMC_NORSRAM_TimingTypeDef
NYX 0:85b3fd62ea1a 347 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 348 * @param Timing: Pointer to NORSRAM Timing structure
NYX 0:85b3fd62ea1a 349 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 350 * @retval HAL status
NYX 0:85b3fd62ea1a 351 */
NYX 0:85b3fd62ea1a 352 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
NYX 0:85b3fd62ea1a 353 {
NYX 0:85b3fd62ea1a 354 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 355
NYX 0:85b3fd62ea1a 356 /* Check the parameters */
NYX 0:85b3fd62ea1a 357 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
NYX 0:85b3fd62ea1a 358
NYX 0:85b3fd62ea1a 359 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
NYX 0:85b3fd62ea1a 360 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
NYX 0:85b3fd62ea1a 361 {
NYX 0:85b3fd62ea1a 362 /* Check the parameters */
NYX 0:85b3fd62ea1a 363 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
NYX 0:85b3fd62ea1a 364 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
NYX 0:85b3fd62ea1a 365 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
NYX 0:85b3fd62ea1a 366 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
NYX 0:85b3fd62ea1a 367 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
NYX 0:85b3fd62ea1a 368 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
NYX 0:85b3fd62ea1a 369 assert_param(IS_FMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 370
NYX 0:85b3fd62ea1a 371 /* Get the BWTR register value */
NYX 0:85b3fd62ea1a 372 tmpr = Device->BWTR[Bank];
NYX 0:85b3fd62ea1a 373
NYX 0:85b3fd62ea1a 374 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
NYX 0:85b3fd62ea1a 375 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
NYX 0:85b3fd62ea1a 376 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
NYX 0:85b3fd62ea1a 377
NYX 0:85b3fd62ea1a 378 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
NYX 0:85b3fd62ea1a 379 ((Timing->AddressHoldTime) << 4U) |\
NYX 0:85b3fd62ea1a 380 ((Timing->DataSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 381 ((Timing->BusTurnAroundDuration) << 16U) |\
NYX 0:85b3fd62ea1a 382 (Timing->AccessMode));
NYX 0:85b3fd62ea1a 383
NYX 0:85b3fd62ea1a 384 Device->BWTR[Bank] = tmpr;
NYX 0:85b3fd62ea1a 385 }
NYX 0:85b3fd62ea1a 386 else
NYX 0:85b3fd62ea1a 387 {
NYX 0:85b3fd62ea1a 388 Device->BWTR[Bank] = 0x0FFFFFFFU;
NYX 0:85b3fd62ea1a 389 }
NYX 0:85b3fd62ea1a 390
NYX 0:85b3fd62ea1a 391 return HAL_OK;
NYX 0:85b3fd62ea1a 392 }
NYX 0:85b3fd62ea1a 393 /**
NYX 0:85b3fd62ea1a 394 * @}
NYX 0:85b3fd62ea1a 395 */
NYX 0:85b3fd62ea1a 396
NYX 0:85b3fd62ea1a 397 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
NYX 0:85b3fd62ea1a 398 * @brief management functions
NYX 0:85b3fd62ea1a 399 *
NYX 0:85b3fd62ea1a 400 @verbatim
NYX 0:85b3fd62ea1a 401 ==============================================================================
NYX 0:85b3fd62ea1a 402 ##### FMC_NORSRAM Control functions #####
NYX 0:85b3fd62ea1a 403 ==============================================================================
NYX 0:85b3fd62ea1a 404 [..]
NYX 0:85b3fd62ea1a 405 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 406 the FMC NORSRAM interface.
NYX 0:85b3fd62ea1a 407
NYX 0:85b3fd62ea1a 408 @endverbatim
NYX 0:85b3fd62ea1a 409 * @{
NYX 0:85b3fd62ea1a 410 */
NYX 0:85b3fd62ea1a 411 /**
NYX 0:85b3fd62ea1a 412 * @brief Enables dynamically FMC_NORSRAM write operation.
NYX 0:85b3fd62ea1a 413 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 414 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 415 * @retval HAL status
NYX 0:85b3fd62ea1a 416 */
NYX 0:85b3fd62ea1a 417 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 418 {
NYX 0:85b3fd62ea1a 419 /* Check the parameters */
NYX 0:85b3fd62ea1a 420 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 421 assert_param(IS_FMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 422
NYX 0:85b3fd62ea1a 423 /* Enable write operation */
NYX 0:85b3fd62ea1a 424 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
NYX 0:85b3fd62ea1a 425
NYX 0:85b3fd62ea1a 426 return HAL_OK;
NYX 0:85b3fd62ea1a 427 }
NYX 0:85b3fd62ea1a 428
NYX 0:85b3fd62ea1a 429 /**
NYX 0:85b3fd62ea1a 430 * @brief Disables dynamically FMC_NORSRAM write operation.
NYX 0:85b3fd62ea1a 431 * @param Device: Pointer to NORSRAM device instance
NYX 0:85b3fd62ea1a 432 * @param Bank: NORSRAM bank number
NYX 0:85b3fd62ea1a 433 * @retval HAL status
NYX 0:85b3fd62ea1a 434 */
NYX 0:85b3fd62ea1a 435 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 436 {
NYX 0:85b3fd62ea1a 437 /* Check the parameters */
NYX 0:85b3fd62ea1a 438 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 439 assert_param(IS_FMC_NORSRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 440
NYX 0:85b3fd62ea1a 441 /* Disable write operation */
NYX 0:85b3fd62ea1a 442 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
NYX 0:85b3fd62ea1a 443
NYX 0:85b3fd62ea1a 444 return HAL_OK;
NYX 0:85b3fd62ea1a 445 }
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 /**
NYX 0:85b3fd62ea1a 448 * @}
NYX 0:85b3fd62ea1a 449 */
NYX 0:85b3fd62ea1a 450
NYX 0:85b3fd62ea1a 451 /**
NYX 0:85b3fd62ea1a 452 * @}
NYX 0:85b3fd62ea1a 453 */
NYX 0:85b3fd62ea1a 454
NYX 0:85b3fd62ea1a 455 /** @addtogroup FMC_LL_NAND
NYX 0:85b3fd62ea1a 456 * @brief NAND Controller functions
NYX 0:85b3fd62ea1a 457 *
NYX 0:85b3fd62ea1a 458 @verbatim
NYX 0:85b3fd62ea1a 459 ==============================================================================
NYX 0:85b3fd62ea1a 460 ##### How to use NAND device driver #####
NYX 0:85b3fd62ea1a 461 ==============================================================================
NYX 0:85b3fd62ea1a 462 [..]
NYX 0:85b3fd62ea1a 463 This driver contains a set of APIs to interface with the FMC NAND banks in order
NYX 0:85b3fd62ea1a 464 to run the NAND external devices.
NYX 0:85b3fd62ea1a 465
NYX 0:85b3fd62ea1a 466 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
NYX 0:85b3fd62ea1a 467 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
NYX 0:85b3fd62ea1a 468 (+) FMC NAND bank common space timing configuration using the function
NYX 0:85b3fd62ea1a 469 FMC_NAND_CommonSpace_Timing_Init()
NYX 0:85b3fd62ea1a 470 (+) FMC NAND bank attribute space timing configuration using the function
NYX 0:85b3fd62ea1a 471 FMC_NAND_AttributeSpace_Timing_Init()
NYX 0:85b3fd62ea1a 472 (+) FMC NAND bank enable/disable ECC correction feature using the functions
NYX 0:85b3fd62ea1a 473 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
NYX 0:85b3fd62ea1a 474 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
NYX 0:85b3fd62ea1a 475
NYX 0:85b3fd62ea1a 476 @endverbatim
NYX 0:85b3fd62ea1a 477 * @{
NYX 0:85b3fd62ea1a 478 */
NYX 0:85b3fd62ea1a 479
NYX 0:85b3fd62ea1a 480 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 481 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
NYX 0:85b3fd62ea1a 482 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 483 *
NYX 0:85b3fd62ea1a 484 @verbatim
NYX 0:85b3fd62ea1a 485 ==============================================================================
NYX 0:85b3fd62ea1a 486 ##### Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 487 ==============================================================================
NYX 0:85b3fd62ea1a 488 [..]
NYX 0:85b3fd62ea1a 489 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 490 (+) Initialize and configure the FMC NAND interface
NYX 0:85b3fd62ea1a 491 (+) De-initialize the FMC NAND interface
NYX 0:85b3fd62ea1a 492 (+) Configure the FMC clock and associated GPIOs
NYX 0:85b3fd62ea1a 493
NYX 0:85b3fd62ea1a 494 @endverbatim
NYX 0:85b3fd62ea1a 495 * @{
NYX 0:85b3fd62ea1a 496 */
NYX 0:85b3fd62ea1a 497
NYX 0:85b3fd62ea1a 498 /**
NYX 0:85b3fd62ea1a 499 * @brief Initializes the FMC_NAND device according to the specified
NYX 0:85b3fd62ea1a 500 * control parameters in the FMC_NAND_HandleTypeDef
NYX 0:85b3fd62ea1a 501 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 502 * @param Init: Pointer to NAND Initialization structure
NYX 0:85b3fd62ea1a 503 * @retval HAL status
NYX 0:85b3fd62ea1a 504 */
NYX 0:85b3fd62ea1a 505 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
NYX 0:85b3fd62ea1a 506 {
NYX 0:85b3fd62ea1a 507 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 508
NYX 0:85b3fd62ea1a 509 /* Check the parameters */
NYX 0:85b3fd62ea1a 510 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 511 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
NYX 0:85b3fd62ea1a 512 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
NYX 0:85b3fd62ea1a 513 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
NYX 0:85b3fd62ea1a 514 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
NYX 0:85b3fd62ea1a 515 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
NYX 0:85b3fd62ea1a 516 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
NYX 0:85b3fd62ea1a 517 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
NYX 0:85b3fd62ea1a 518
NYX 0:85b3fd62ea1a 519 /* Get the NAND bank register value */
NYX 0:85b3fd62ea1a 520 tmpr = Device->PCR;
NYX 0:85b3fd62ea1a 521
NYX 0:85b3fd62ea1a 522 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
NYX 0:85b3fd62ea1a 523 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
NYX 0:85b3fd62ea1a 524 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
NYX 0:85b3fd62ea1a 525 FMC_PCR_TAR | FMC_PCR_ECCPS));
NYX 0:85b3fd62ea1a 526
NYX 0:85b3fd62ea1a 527 /* Set NAND device control parameters */
NYX 0:85b3fd62ea1a 528 tmpr |= (uint32_t)(Init->Waitfeature |\
NYX 0:85b3fd62ea1a 529 FMC_PCR_MEMORY_TYPE_NAND |\
NYX 0:85b3fd62ea1a 530 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 531 Init->EccComputation |\
NYX 0:85b3fd62ea1a 532 Init->ECCPageSize |\
NYX 0:85b3fd62ea1a 533 ((Init->TCLRSetupTime) << 9U) |\
NYX 0:85b3fd62ea1a 534 ((Init->TARSetupTime) << 13U));
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 /* NAND bank registers configuration */
NYX 0:85b3fd62ea1a 537 Device->PCR = tmpr;
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 return HAL_OK;
NYX 0:85b3fd62ea1a 540 }
NYX 0:85b3fd62ea1a 541
NYX 0:85b3fd62ea1a 542 /**
NYX 0:85b3fd62ea1a 543 * @brief Initializes the FMC_NAND Common space Timing according to the specified
NYX 0:85b3fd62ea1a 544 * parameters in the FMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 545 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 546 * @param Timing: Pointer to NAND timing structure
NYX 0:85b3fd62ea1a 547 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 548 * @retval HAL status
NYX 0:85b3fd62ea1a 549 */
NYX 0:85b3fd62ea1a 550 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 551 {
NYX 0:85b3fd62ea1a 552 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 553
NYX 0:85b3fd62ea1a 554 /* Check the parameters */
NYX 0:85b3fd62ea1a 555 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 556 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 557 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 558 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 559 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 560 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 561
NYX 0:85b3fd62ea1a 562 /* Get the NAND bank 2 register value */
NYX 0:85b3fd62ea1a 563 tmpr = Device->PMEM;
NYX 0:85b3fd62ea1a 564
NYX 0:85b3fd62ea1a 565
NYX 0:85b3fd62ea1a 566 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
NYX 0:85b3fd62ea1a 567 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \
NYX 0:85b3fd62ea1a 568 FMC_PMEM_MEMHIZ2));
NYX 0:85b3fd62ea1a 569
NYX 0:85b3fd62ea1a 570 /* Set FMC_NAND device timing parameters */
NYX 0:85b3fd62ea1a 571 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 572 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 573 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 574 ((Timing->HiZSetupTime) << 24U)
NYX 0:85b3fd62ea1a 575 );
NYX 0:85b3fd62ea1a 576
NYX 0:85b3fd62ea1a 577 /* NAND bank registers configuration */
NYX 0:85b3fd62ea1a 578 Device->PMEM = tmpr;
NYX 0:85b3fd62ea1a 579
NYX 0:85b3fd62ea1a 580 return HAL_OK;
NYX 0:85b3fd62ea1a 581 }
NYX 0:85b3fd62ea1a 582
NYX 0:85b3fd62ea1a 583 /**
NYX 0:85b3fd62ea1a 584 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
NYX 0:85b3fd62ea1a 585 * parameters in the FMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 586 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 587 * @param Timing: Pointer to NAND timing structure
NYX 0:85b3fd62ea1a 588 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 589 * @retval HAL status
NYX 0:85b3fd62ea1a 590 */
NYX 0:85b3fd62ea1a 591 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 592 {
NYX 0:85b3fd62ea1a 593 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 594
NYX 0:85b3fd62ea1a 595 /* Check the parameters */
NYX 0:85b3fd62ea1a 596 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 597 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 598 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 599 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 600 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 601 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 602
NYX 0:85b3fd62ea1a 603 /* Get the NAND bank register value */
NYX 0:85b3fd62ea1a 604 tmpr = Device->PATT;
NYX 0:85b3fd62ea1a 605
NYX 0:85b3fd62ea1a 606 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
NYX 0:85b3fd62ea1a 607 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \
NYX 0:85b3fd62ea1a 608 FMC_PATT_ATTHIZ2));
NYX 0:85b3fd62ea1a 609
NYX 0:85b3fd62ea1a 610 /* Set FMC_NAND device timing parameters */
NYX 0:85b3fd62ea1a 611 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 612 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 613 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 614 ((Timing->HiZSetupTime) << 24U));
NYX 0:85b3fd62ea1a 615
NYX 0:85b3fd62ea1a 616 /* NAND bank registers configuration */
NYX 0:85b3fd62ea1a 617 Device->PATT = tmpr;
NYX 0:85b3fd62ea1a 618
NYX 0:85b3fd62ea1a 619 return HAL_OK;
NYX 0:85b3fd62ea1a 620 }
NYX 0:85b3fd62ea1a 621
NYX 0:85b3fd62ea1a 622
NYX 0:85b3fd62ea1a 623 /**
NYX 0:85b3fd62ea1a 624 * @brief DeInitializes the FMC_NAND device
NYX 0:85b3fd62ea1a 625 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 626 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 627 * @retval HAL status
NYX 0:85b3fd62ea1a 628 */
NYX 0:85b3fd62ea1a 629 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 630 {
NYX 0:85b3fd62ea1a 631 /* Check the parameters */
NYX 0:85b3fd62ea1a 632 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 633 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 634
NYX 0:85b3fd62ea1a 635 /* Disable the NAND Bank */
NYX 0:85b3fd62ea1a 636 __FMC_NAND_DISABLE(Device, Bank);
NYX 0:85b3fd62ea1a 637
NYX 0:85b3fd62ea1a 638 /* De-initialize the NAND Bank */
NYX 0:85b3fd62ea1a 639 /* Set the FMC_NAND_BANK registers to their reset values */
NYX 0:85b3fd62ea1a 640 Device->PCR = 0x00000018U;
NYX 0:85b3fd62ea1a 641 Device->SR = 0x00000040U;
NYX 0:85b3fd62ea1a 642 Device->PMEM = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 643 Device->PATT = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 644
NYX 0:85b3fd62ea1a 645 return HAL_OK;
NYX 0:85b3fd62ea1a 646 }
NYX 0:85b3fd62ea1a 647
NYX 0:85b3fd62ea1a 648 /**
NYX 0:85b3fd62ea1a 649 * @}
NYX 0:85b3fd62ea1a 650 */
NYX 0:85b3fd62ea1a 651
NYX 0:85b3fd62ea1a 652
NYX 0:85b3fd62ea1a 653 /** @defgroup HAL_FMC_NAND_Group2 Control functions
NYX 0:85b3fd62ea1a 654 * @brief management functions
NYX 0:85b3fd62ea1a 655 *
NYX 0:85b3fd62ea1a 656 @verbatim
NYX 0:85b3fd62ea1a 657 ==============================================================================
NYX 0:85b3fd62ea1a 658 ##### FMC_NAND Control functions #####
NYX 0:85b3fd62ea1a 659 ==============================================================================
NYX 0:85b3fd62ea1a 660 [..]
NYX 0:85b3fd62ea1a 661 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 662 the FMC NAND interface.
NYX 0:85b3fd62ea1a 663
NYX 0:85b3fd62ea1a 664 @endverbatim
NYX 0:85b3fd62ea1a 665 * @{
NYX 0:85b3fd62ea1a 666 */
NYX 0:85b3fd62ea1a 667
NYX 0:85b3fd62ea1a 668
NYX 0:85b3fd62ea1a 669 /**
NYX 0:85b3fd62ea1a 670 * @brief Enables dynamically FMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 671 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 672 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 673 * @retval HAL status
NYX 0:85b3fd62ea1a 674 */
NYX 0:85b3fd62ea1a 675 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 676 {
NYX 0:85b3fd62ea1a 677 /* Check the parameters */
NYX 0:85b3fd62ea1a 678 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 679 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 680
NYX 0:85b3fd62ea1a 681 /* Enable ECC feature */
NYX 0:85b3fd62ea1a 682 Device->PCR |= FMC_PCR_ECCEN;
NYX 0:85b3fd62ea1a 683
NYX 0:85b3fd62ea1a 684 return HAL_OK;
NYX 0:85b3fd62ea1a 685 }
NYX 0:85b3fd62ea1a 686
NYX 0:85b3fd62ea1a 687
NYX 0:85b3fd62ea1a 688 /**
NYX 0:85b3fd62ea1a 689 * @brief Disables dynamically FMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 690 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 691 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 692 * @retval HAL status
NYX 0:85b3fd62ea1a 693 */
NYX 0:85b3fd62ea1a 694 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 695 {
NYX 0:85b3fd62ea1a 696 /* Check the parameters */
NYX 0:85b3fd62ea1a 697 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 698 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 699
NYX 0:85b3fd62ea1a 700 /* Disable ECC feature */
NYX 0:85b3fd62ea1a 701 Device->PCR &= ~FMC_PCR_ECCEN;
NYX 0:85b3fd62ea1a 702
NYX 0:85b3fd62ea1a 703 return HAL_OK;
NYX 0:85b3fd62ea1a 704 }
NYX 0:85b3fd62ea1a 705
NYX 0:85b3fd62ea1a 706 /**
NYX 0:85b3fd62ea1a 707 * @brief Disables dynamically FMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 708 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 709 * @param ECCval: Pointer to ECC value
NYX 0:85b3fd62ea1a 710 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 711 * @param Timeout: Timeout wait value
NYX 0:85b3fd62ea1a 712 * @retval HAL status
NYX 0:85b3fd62ea1a 713 */
NYX 0:85b3fd62ea1a 714 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
NYX 0:85b3fd62ea1a 715 {
NYX 0:85b3fd62ea1a 716 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 717
NYX 0:85b3fd62ea1a 718 /* Check the parameters */
NYX 0:85b3fd62ea1a 719 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 720 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 721
NYX 0:85b3fd62ea1a 722 /* Get tick */
NYX 0:85b3fd62ea1a 723 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 724
NYX 0:85b3fd62ea1a 725 /* Wait until FIFO is empty */
NYX 0:85b3fd62ea1a 726 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
NYX 0:85b3fd62ea1a 727 {
NYX 0:85b3fd62ea1a 728 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 729 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 730 {
NYX 0:85b3fd62ea1a 731 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 732 {
NYX 0:85b3fd62ea1a 733 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 734 }
NYX 0:85b3fd62ea1a 735 }
NYX 0:85b3fd62ea1a 736 }
NYX 0:85b3fd62ea1a 737
NYX 0:85b3fd62ea1a 738 /* Get the ECCR register value */
NYX 0:85b3fd62ea1a 739 *ECCval = (uint32_t)Device->ECCR;
NYX 0:85b3fd62ea1a 740
NYX 0:85b3fd62ea1a 741 return HAL_OK;
NYX 0:85b3fd62ea1a 742 }
NYX 0:85b3fd62ea1a 743
NYX 0:85b3fd62ea1a 744 /**
NYX 0:85b3fd62ea1a 745 * @}
NYX 0:85b3fd62ea1a 746 */
NYX 0:85b3fd62ea1a 747
NYX 0:85b3fd62ea1a 748 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
NYX 0:85b3fd62ea1a 749 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
NYX 0:85b3fd62ea1a 750 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 751 *
NYX 0:85b3fd62ea1a 752 @verbatim
NYX 0:85b3fd62ea1a 753 ==============================================================================
NYX 0:85b3fd62ea1a 754 ##### Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 755 ==============================================================================
NYX 0:85b3fd62ea1a 756 [..]
NYX 0:85b3fd62ea1a 757 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 758 (+) Initialize and configure the FMC NAND interface
NYX 0:85b3fd62ea1a 759 (+) De-initialize the FMC NAND interface
NYX 0:85b3fd62ea1a 760 (+) Configure the FMC clock and associated GPIOs
NYX 0:85b3fd62ea1a 761
NYX 0:85b3fd62ea1a 762 @endverbatim
NYX 0:85b3fd62ea1a 763 * @{
NYX 0:85b3fd62ea1a 764 */
NYX 0:85b3fd62ea1a 765 /**
NYX 0:85b3fd62ea1a 766 * @brief Initializes the FMC_NAND device according to the specified
NYX 0:85b3fd62ea1a 767 * control parameters in the FMC_NAND_HandleTypeDef
NYX 0:85b3fd62ea1a 768 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 769 * @param Init: Pointer to NAND Initialization structure
NYX 0:85b3fd62ea1a 770 * @retval HAL status
NYX 0:85b3fd62ea1a 771 */
NYX 0:85b3fd62ea1a 772 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
NYX 0:85b3fd62ea1a 773 {
NYX 0:85b3fd62ea1a 774 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 775
NYX 0:85b3fd62ea1a 776 /* Check the parameters */
NYX 0:85b3fd62ea1a 777 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 778 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
NYX 0:85b3fd62ea1a 779 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
NYX 0:85b3fd62ea1a 780 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
NYX 0:85b3fd62ea1a 781 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
NYX 0:85b3fd62ea1a 782 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
NYX 0:85b3fd62ea1a 783 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
NYX 0:85b3fd62ea1a 784 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
NYX 0:85b3fd62ea1a 785
NYX 0:85b3fd62ea1a 786 if(Init->NandBank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 787 {
NYX 0:85b3fd62ea1a 788 /* Get the NAND bank 2 register value */
NYX 0:85b3fd62ea1a 789 tmpr = Device->PCR2;
NYX 0:85b3fd62ea1a 790 }
NYX 0:85b3fd62ea1a 791 else
NYX 0:85b3fd62ea1a 792 {
NYX 0:85b3fd62ea1a 793 /* Get the NAND bank 3 register value */
NYX 0:85b3fd62ea1a 794 tmpr = Device->PCR3;
NYX 0:85b3fd62ea1a 795 }
NYX 0:85b3fd62ea1a 796
NYX 0:85b3fd62ea1a 797 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
NYX 0:85b3fd62ea1a 798 tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \
NYX 0:85b3fd62ea1a 799 FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
NYX 0:85b3fd62ea1a 800 FMC_PCR2_TAR | FMC_PCR2_ECCPS));
NYX 0:85b3fd62ea1a 801
NYX 0:85b3fd62ea1a 802 /* Set NAND device control parameters */
NYX 0:85b3fd62ea1a 803 tmpr |= (uint32_t)(Init->Waitfeature |\
NYX 0:85b3fd62ea1a 804 FMC_PCR_MEMORY_TYPE_NAND |\
NYX 0:85b3fd62ea1a 805 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 806 Init->EccComputation |\
NYX 0:85b3fd62ea1a 807 Init->ECCPageSize |\
NYX 0:85b3fd62ea1a 808 ((Init->TCLRSetupTime) << 9U) |\
NYX 0:85b3fd62ea1a 809 ((Init->TARSetupTime) << 13U));
NYX 0:85b3fd62ea1a 810
NYX 0:85b3fd62ea1a 811 if(Init->NandBank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 812 {
NYX 0:85b3fd62ea1a 813 /* NAND bank 2 registers configuration */
NYX 0:85b3fd62ea1a 814 Device->PCR2 = tmpr;
NYX 0:85b3fd62ea1a 815 }
NYX 0:85b3fd62ea1a 816 else
NYX 0:85b3fd62ea1a 817 {
NYX 0:85b3fd62ea1a 818 /* NAND bank 3 registers configuration */
NYX 0:85b3fd62ea1a 819 Device->PCR3 = tmpr;
NYX 0:85b3fd62ea1a 820 }
NYX 0:85b3fd62ea1a 821
NYX 0:85b3fd62ea1a 822 return HAL_OK;
NYX 0:85b3fd62ea1a 823
NYX 0:85b3fd62ea1a 824 }
NYX 0:85b3fd62ea1a 825
NYX 0:85b3fd62ea1a 826 /**
NYX 0:85b3fd62ea1a 827 * @brief Initializes the FMC_NAND Common space Timing according to the specified
NYX 0:85b3fd62ea1a 828 * parameters in the FMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 829 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 830 * @param Timing: Pointer to NAND timing structure
NYX 0:85b3fd62ea1a 831 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 832 * @retval HAL status
NYX 0:85b3fd62ea1a 833 */
NYX 0:85b3fd62ea1a 834 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 835 {
NYX 0:85b3fd62ea1a 836 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 837
NYX 0:85b3fd62ea1a 838 /* Check the parameters */
NYX 0:85b3fd62ea1a 839 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 840 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 841 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 842 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 843 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 844 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 845
NYX 0:85b3fd62ea1a 846 if(Bank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 847 {
NYX 0:85b3fd62ea1a 848 /* Get the NAND bank 2 register value */
NYX 0:85b3fd62ea1a 849 tmpr = Device->PMEM2;
NYX 0:85b3fd62ea1a 850 }
NYX 0:85b3fd62ea1a 851 else
NYX 0:85b3fd62ea1a 852 {
NYX 0:85b3fd62ea1a 853 /* Get the NAND bank 3 register value */
NYX 0:85b3fd62ea1a 854 tmpr = Device->PMEM3;
NYX 0:85b3fd62ea1a 855 }
NYX 0:85b3fd62ea1a 856
NYX 0:85b3fd62ea1a 857 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
NYX 0:85b3fd62ea1a 858 tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \
NYX 0:85b3fd62ea1a 859 FMC_PMEM2_MEMHIZ2));
NYX 0:85b3fd62ea1a 860
NYX 0:85b3fd62ea1a 861 /* Set FMC_NAND device timing parameters */
NYX 0:85b3fd62ea1a 862 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 863 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 864 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 865 ((Timing->HiZSetupTime) << 24U)
NYX 0:85b3fd62ea1a 866 );
NYX 0:85b3fd62ea1a 867
NYX 0:85b3fd62ea1a 868 if(Bank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 869 {
NYX 0:85b3fd62ea1a 870 /* NAND bank 2 registers configuration */
NYX 0:85b3fd62ea1a 871 Device->PMEM2 = tmpr;
NYX 0:85b3fd62ea1a 872 }
NYX 0:85b3fd62ea1a 873 else
NYX 0:85b3fd62ea1a 874 {
NYX 0:85b3fd62ea1a 875 /* NAND bank 3 registers configuration */
NYX 0:85b3fd62ea1a 876 Device->PMEM3 = tmpr;
NYX 0:85b3fd62ea1a 877 }
NYX 0:85b3fd62ea1a 878
NYX 0:85b3fd62ea1a 879 return HAL_OK;
NYX 0:85b3fd62ea1a 880 }
NYX 0:85b3fd62ea1a 881
NYX 0:85b3fd62ea1a 882 /**
NYX 0:85b3fd62ea1a 883 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
NYX 0:85b3fd62ea1a 884 * parameters in the FMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 885 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 886 * @param Timing: Pointer to NAND timing structure
NYX 0:85b3fd62ea1a 887 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 888 * @retval HAL status
NYX 0:85b3fd62ea1a 889 */
NYX 0:85b3fd62ea1a 890 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 891 {
NYX 0:85b3fd62ea1a 892 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 893
NYX 0:85b3fd62ea1a 894 /* Check the parameters */
NYX 0:85b3fd62ea1a 895 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 896 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 897 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 898 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 899 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 900 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 901
NYX 0:85b3fd62ea1a 902 if(Bank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 903 {
NYX 0:85b3fd62ea1a 904 /* Get the NAND bank 2 register value */
NYX 0:85b3fd62ea1a 905 tmpr = Device->PATT2;
NYX 0:85b3fd62ea1a 906 }
NYX 0:85b3fd62ea1a 907 else
NYX 0:85b3fd62ea1a 908 {
NYX 0:85b3fd62ea1a 909 /* Get the NAND bank 3 register value */
NYX 0:85b3fd62ea1a 910 tmpr = Device->PATT3;
NYX 0:85b3fd62ea1a 911 }
NYX 0:85b3fd62ea1a 912
NYX 0:85b3fd62ea1a 913 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
NYX 0:85b3fd62ea1a 914 tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \
NYX 0:85b3fd62ea1a 915 FMC_PATT2_ATTHIZ2));
NYX 0:85b3fd62ea1a 916
NYX 0:85b3fd62ea1a 917 /* Set FMC_NAND device timing parameters */
NYX 0:85b3fd62ea1a 918 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 919 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 920 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 921 ((Timing->HiZSetupTime) << 24U));
NYX 0:85b3fd62ea1a 922
NYX 0:85b3fd62ea1a 923 if(Bank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 924 {
NYX 0:85b3fd62ea1a 925 /* NAND bank 2 registers configuration */
NYX 0:85b3fd62ea1a 926 Device->PATT2 = tmpr;
NYX 0:85b3fd62ea1a 927 }
NYX 0:85b3fd62ea1a 928 else
NYX 0:85b3fd62ea1a 929 {
NYX 0:85b3fd62ea1a 930 /* NAND bank 3 registers configuration */
NYX 0:85b3fd62ea1a 931 Device->PATT3 = tmpr;
NYX 0:85b3fd62ea1a 932 }
NYX 0:85b3fd62ea1a 933
NYX 0:85b3fd62ea1a 934 return HAL_OK;
NYX 0:85b3fd62ea1a 935 }
NYX 0:85b3fd62ea1a 936
NYX 0:85b3fd62ea1a 937 /**
NYX 0:85b3fd62ea1a 938 * @brief DeInitializes the FMC_NAND device
NYX 0:85b3fd62ea1a 939 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 940 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 941 * @retval HAL status
NYX 0:85b3fd62ea1a 942 */
NYX 0:85b3fd62ea1a 943 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 944 {
NYX 0:85b3fd62ea1a 945 /* Check the parameters */
NYX 0:85b3fd62ea1a 946 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 947 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 948
NYX 0:85b3fd62ea1a 949 /* Disable the NAND Bank */
NYX 0:85b3fd62ea1a 950 __FMC_NAND_DISABLE(Device, Bank);
NYX 0:85b3fd62ea1a 951
NYX 0:85b3fd62ea1a 952 /* De-initialize the NAND Bank */
NYX 0:85b3fd62ea1a 953 if(Bank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 954 {
NYX 0:85b3fd62ea1a 955 /* Set the FMC_NAND_BANK2 registers to their reset values */
NYX 0:85b3fd62ea1a 956 Device->PCR2 = 0x00000018U;
NYX 0:85b3fd62ea1a 957 Device->SR2 = 0x00000040U;
NYX 0:85b3fd62ea1a 958 Device->PMEM2 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 959 Device->PATT2 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 960 }
NYX 0:85b3fd62ea1a 961 /* FMC_Bank3_NAND */
NYX 0:85b3fd62ea1a 962 else
NYX 0:85b3fd62ea1a 963 {
NYX 0:85b3fd62ea1a 964 /* Set the FMC_NAND_BANK3 registers to their reset values */
NYX 0:85b3fd62ea1a 965 Device->PCR3 = 0x00000018U;
NYX 0:85b3fd62ea1a 966 Device->SR3 = 0x00000040U;
NYX 0:85b3fd62ea1a 967 Device->PMEM3 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 968 Device->PATT3 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 969 }
NYX 0:85b3fd62ea1a 970
NYX 0:85b3fd62ea1a 971 return HAL_OK;
NYX 0:85b3fd62ea1a 972 }
NYX 0:85b3fd62ea1a 973
NYX 0:85b3fd62ea1a 974 /**
NYX 0:85b3fd62ea1a 975 * @}
NYX 0:85b3fd62ea1a 976 */
NYX 0:85b3fd62ea1a 977
NYX 0:85b3fd62ea1a 978 /** @addtogroup FMC_LL_NAND_Private_Functions_Group2
NYX 0:85b3fd62ea1a 979 * @brief management functions
NYX 0:85b3fd62ea1a 980 *
NYX 0:85b3fd62ea1a 981 @verbatim
NYX 0:85b3fd62ea1a 982 ==============================================================================
NYX 0:85b3fd62ea1a 983 ##### FMC_NAND Control functions #####
NYX 0:85b3fd62ea1a 984 ==============================================================================
NYX 0:85b3fd62ea1a 985 [..]
NYX 0:85b3fd62ea1a 986 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 987 the FMC NAND interface.
NYX 0:85b3fd62ea1a 988
NYX 0:85b3fd62ea1a 989 @endverbatim
NYX 0:85b3fd62ea1a 990 * @{
NYX 0:85b3fd62ea1a 991 */
NYX 0:85b3fd62ea1a 992 /**
NYX 0:85b3fd62ea1a 993 * @brief Enables dynamically FMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 994 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 995 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 996 * @retval HAL status
NYX 0:85b3fd62ea1a 997 */
NYX 0:85b3fd62ea1a 998 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 999 {
NYX 0:85b3fd62ea1a 1000 /* Check the parameters */
NYX 0:85b3fd62ea1a 1001 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 1002 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 1003
NYX 0:85b3fd62ea1a 1004 /* Enable ECC feature */
NYX 0:85b3fd62ea1a 1005 if(Bank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 1006 {
NYX 0:85b3fd62ea1a 1007 Device->PCR2 |= FMC_PCR2_ECCEN;
NYX 0:85b3fd62ea1a 1008 }
NYX 0:85b3fd62ea1a 1009 else
NYX 0:85b3fd62ea1a 1010 {
NYX 0:85b3fd62ea1a 1011 Device->PCR3 |= FMC_PCR3_ECCEN;
NYX 0:85b3fd62ea1a 1012 }
NYX 0:85b3fd62ea1a 1013
NYX 0:85b3fd62ea1a 1014 return HAL_OK;
NYX 0:85b3fd62ea1a 1015 }
NYX 0:85b3fd62ea1a 1016
NYX 0:85b3fd62ea1a 1017 /**
NYX 0:85b3fd62ea1a 1018 * @brief Disables dynamically FMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 1019 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 1020 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 1021 * @retval HAL status
NYX 0:85b3fd62ea1a 1022 */
NYX 0:85b3fd62ea1a 1023 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 1024 {
NYX 0:85b3fd62ea1a 1025 /* Check the parameters */
NYX 0:85b3fd62ea1a 1026 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 1027 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 1028
NYX 0:85b3fd62ea1a 1029 /* Disable ECC feature */
NYX 0:85b3fd62ea1a 1030 if(Bank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 1031 {
NYX 0:85b3fd62ea1a 1032 Device->PCR2 &= ~FMC_PCR2_ECCEN;
NYX 0:85b3fd62ea1a 1033 }
NYX 0:85b3fd62ea1a 1034 else
NYX 0:85b3fd62ea1a 1035 {
NYX 0:85b3fd62ea1a 1036 Device->PCR3 &= ~FMC_PCR3_ECCEN;
NYX 0:85b3fd62ea1a 1037 }
NYX 0:85b3fd62ea1a 1038
NYX 0:85b3fd62ea1a 1039 return HAL_OK;
NYX 0:85b3fd62ea1a 1040 }
NYX 0:85b3fd62ea1a 1041
NYX 0:85b3fd62ea1a 1042 /**
NYX 0:85b3fd62ea1a 1043 * @brief Disables dynamically FMC_NAND ECC feature.
NYX 0:85b3fd62ea1a 1044 * @param Device: Pointer to NAND device instance
NYX 0:85b3fd62ea1a 1045 * @param ECCval: Pointer to ECC value
NYX 0:85b3fd62ea1a 1046 * @param Bank: NAND bank number
NYX 0:85b3fd62ea1a 1047 * @param Timeout: Timeout wait value
NYX 0:85b3fd62ea1a 1048 * @retval HAL status
NYX 0:85b3fd62ea1a 1049 */
NYX 0:85b3fd62ea1a 1050 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
NYX 0:85b3fd62ea1a 1051 {
NYX 0:85b3fd62ea1a 1052 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1053
NYX 0:85b3fd62ea1a 1054 /* Check the parameters */
NYX 0:85b3fd62ea1a 1055 assert_param(IS_FMC_NAND_DEVICE(Device));
NYX 0:85b3fd62ea1a 1056 assert_param(IS_FMC_NAND_BANK(Bank));
NYX 0:85b3fd62ea1a 1057
NYX 0:85b3fd62ea1a 1058 /* Get tick */
NYX 0:85b3fd62ea1a 1059 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1060
NYX 0:85b3fd62ea1a 1061 /* Wait until FIFO is empty */
NYX 0:85b3fd62ea1a 1062 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
NYX 0:85b3fd62ea1a 1063 {
NYX 0:85b3fd62ea1a 1064 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1065 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 1066 {
NYX 0:85b3fd62ea1a 1067 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 1068 {
NYX 0:85b3fd62ea1a 1069 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1070 }
NYX 0:85b3fd62ea1a 1071 }
NYX 0:85b3fd62ea1a 1072 }
NYX 0:85b3fd62ea1a 1073
NYX 0:85b3fd62ea1a 1074 if(Bank == FMC_NAND_BANK2)
NYX 0:85b3fd62ea1a 1075 {
NYX 0:85b3fd62ea1a 1076 /* Get the ECCR2 register value */
NYX 0:85b3fd62ea1a 1077 *ECCval = (uint32_t)Device->ECCR2;
NYX 0:85b3fd62ea1a 1078 }
NYX 0:85b3fd62ea1a 1079 else
NYX 0:85b3fd62ea1a 1080 {
NYX 0:85b3fd62ea1a 1081 /* Get the ECCR3 register value */
NYX 0:85b3fd62ea1a 1082 *ECCval = (uint32_t)Device->ECCR3;
NYX 0:85b3fd62ea1a 1083 }
NYX 0:85b3fd62ea1a 1084
NYX 0:85b3fd62ea1a 1085 return HAL_OK;
NYX 0:85b3fd62ea1a 1086 }
NYX 0:85b3fd62ea1a 1087
NYX 0:85b3fd62ea1a 1088 /**
NYX 0:85b3fd62ea1a 1089 * @}
NYX 0:85b3fd62ea1a 1090 */
NYX 0:85b3fd62ea1a 1091
NYX 0:85b3fd62ea1a 1092 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
NYX 0:85b3fd62ea1a 1093 /**
NYX 0:85b3fd62ea1a 1094 * @}
NYX 0:85b3fd62ea1a 1095 */
NYX 0:85b3fd62ea1a 1096
NYX 0:85b3fd62ea1a 1097 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
NYX 0:85b3fd62ea1a 1098 /** @addtogroup FMC_LL_PCCARD
NYX 0:85b3fd62ea1a 1099 * @brief PCCARD Controller functions
NYX 0:85b3fd62ea1a 1100 *
NYX 0:85b3fd62ea1a 1101 @verbatim
NYX 0:85b3fd62ea1a 1102 ==============================================================================
NYX 0:85b3fd62ea1a 1103 ##### How to use PCCARD device driver #####
NYX 0:85b3fd62ea1a 1104 ==============================================================================
NYX 0:85b3fd62ea1a 1105 [..]
NYX 0:85b3fd62ea1a 1106 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
NYX 0:85b3fd62ea1a 1107 to run the PCCARD/compact flash external devices.
NYX 0:85b3fd62ea1a 1108
NYX 0:85b3fd62ea1a 1109 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
NYX 0:85b3fd62ea1a 1110 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
NYX 0:85b3fd62ea1a 1111 (+) FMC PCCARD bank common space timing configuration using the function
NYX 0:85b3fd62ea1a 1112 FMC_PCCARD_CommonSpace_Timing_Init()
NYX 0:85b3fd62ea1a 1113 (+) FMC PCCARD bank attribute space timing configuration using the function
NYX 0:85b3fd62ea1a 1114 FMC_PCCARD_AttributeSpace_Timing_Init()
NYX 0:85b3fd62ea1a 1115 (+) FMC PCCARD bank IO space timing configuration using the function
NYX 0:85b3fd62ea1a 1116 FMC_PCCARD_IOSpace_Timing_Init()
NYX 0:85b3fd62ea1a 1117 @endverbatim
NYX 0:85b3fd62ea1a 1118 * @{
NYX 0:85b3fd62ea1a 1119 */
NYX 0:85b3fd62ea1a 1120
NYX 0:85b3fd62ea1a 1121 /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
NYX 0:85b3fd62ea1a 1122 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 1123 *
NYX 0:85b3fd62ea1a 1124 @verbatim
NYX 0:85b3fd62ea1a 1125 ==============================================================================
NYX 0:85b3fd62ea1a 1126 ##### Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 1127 ==============================================================================
NYX 0:85b3fd62ea1a 1128 [..]
NYX 0:85b3fd62ea1a 1129 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 1130 (+) Initialize and configure the FMC PCCARD interface
NYX 0:85b3fd62ea1a 1131 (+) De-initialize the FMC PCCARD interface
NYX 0:85b3fd62ea1a 1132 (+) Configure the FMC clock and associated GPIOs
NYX 0:85b3fd62ea1a 1133
NYX 0:85b3fd62ea1a 1134 @endverbatim
NYX 0:85b3fd62ea1a 1135 * @{
NYX 0:85b3fd62ea1a 1136 */
NYX 0:85b3fd62ea1a 1137
NYX 0:85b3fd62ea1a 1138 /**
NYX 0:85b3fd62ea1a 1139 * @brief Initializes the FMC_PCCARD device according to the specified
NYX 0:85b3fd62ea1a 1140 * control parameters in the FMC_PCCARD_HandleTypeDef
NYX 0:85b3fd62ea1a 1141 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 1142 * @param Init: Pointer to PCCARD Initialization structure
NYX 0:85b3fd62ea1a 1143 * @retval HAL status
NYX 0:85b3fd62ea1a 1144 */
NYX 0:85b3fd62ea1a 1145 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
NYX 0:85b3fd62ea1a 1146 {
NYX 0:85b3fd62ea1a 1147 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 1148
NYX 0:85b3fd62ea1a 1149 /* Check the parameters */
NYX 0:85b3fd62ea1a 1150 assert_param(IS_FMC_PCCARD_DEVICE(Device));
NYX 0:85b3fd62ea1a 1151 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
NYX 0:85b3fd62ea1a 1152 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
NYX 0:85b3fd62ea1a 1153 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
NYX 0:85b3fd62ea1a 1154
NYX 0:85b3fd62ea1a 1155 /* Get PCCARD control register value */
NYX 0:85b3fd62ea1a 1156 tmpr = Device->PCR4;
NYX 0:85b3fd62ea1a 1157
NYX 0:85b3fd62ea1a 1158 /* Clear TAR, TCLR, PWAITEN and PWID bits */
NYX 0:85b3fd62ea1a 1159 tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \
NYX 0:85b3fd62ea1a 1160 FMC_PCR4_PWID));
NYX 0:85b3fd62ea1a 1161
NYX 0:85b3fd62ea1a 1162 /* Set FMC_PCCARD device control parameters */
NYX 0:85b3fd62ea1a 1163 tmpr |= (uint32_t)(Init->Waitfeature |\
NYX 0:85b3fd62ea1a 1164 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
NYX 0:85b3fd62ea1a 1165 (Init->TCLRSetupTime << 9U) |\
NYX 0:85b3fd62ea1a 1166 (Init->TARSetupTime << 13U));
NYX 0:85b3fd62ea1a 1167
NYX 0:85b3fd62ea1a 1168 Device->PCR4 = tmpr;
NYX 0:85b3fd62ea1a 1169
NYX 0:85b3fd62ea1a 1170 return HAL_OK;
NYX 0:85b3fd62ea1a 1171 }
NYX 0:85b3fd62ea1a 1172
NYX 0:85b3fd62ea1a 1173 /**
NYX 0:85b3fd62ea1a 1174 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
NYX 0:85b3fd62ea1a 1175 * parameters in the FMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 1176 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 1177 * @param Timing: Pointer to PCCARD timing structure
NYX 0:85b3fd62ea1a 1178 * @retval HAL status
NYX 0:85b3fd62ea1a 1179 */
NYX 0:85b3fd62ea1a 1180 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
NYX 0:85b3fd62ea1a 1181 {
NYX 0:85b3fd62ea1a 1182 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 1183
NYX 0:85b3fd62ea1a 1184 /* Check the parameters */
NYX 0:85b3fd62ea1a 1185 assert_param(IS_FMC_PCCARD_DEVICE(Device));
NYX 0:85b3fd62ea1a 1186 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 1187 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 1188 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 1189 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 1190
NYX 0:85b3fd62ea1a 1191 /* Get PCCARD common space timing register value */
NYX 0:85b3fd62ea1a 1192 tmpr = Device->PMEM4;
NYX 0:85b3fd62ea1a 1193
NYX 0:85b3fd62ea1a 1194 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
NYX 0:85b3fd62ea1a 1195 tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \
NYX 0:85b3fd62ea1a 1196 FMC_PMEM4_MEMHIZ4));
NYX 0:85b3fd62ea1a 1197 /* Set PCCARD timing parameters */
NYX 0:85b3fd62ea1a 1198 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 1199 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 1200 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 1201 ((Timing->HiZSetupTime) << 24U));
NYX 0:85b3fd62ea1a 1202
NYX 0:85b3fd62ea1a 1203 Device->PMEM4 = tmpr;
NYX 0:85b3fd62ea1a 1204
NYX 0:85b3fd62ea1a 1205 return HAL_OK;
NYX 0:85b3fd62ea1a 1206 }
NYX 0:85b3fd62ea1a 1207
NYX 0:85b3fd62ea1a 1208 /**
NYX 0:85b3fd62ea1a 1209 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
NYX 0:85b3fd62ea1a 1210 * parameters in the FMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 1211 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 1212 * @param Timing: Pointer to PCCARD timing structure
NYX 0:85b3fd62ea1a 1213 * @retval HAL status
NYX 0:85b3fd62ea1a 1214 */
NYX 0:85b3fd62ea1a 1215 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
NYX 0:85b3fd62ea1a 1216 {
NYX 0:85b3fd62ea1a 1217 uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 1218
NYX 0:85b3fd62ea1a 1219 /* Check the parameters */
NYX 0:85b3fd62ea1a 1220 assert_param(IS_FMC_PCCARD_DEVICE(Device));
NYX 0:85b3fd62ea1a 1221 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 1222 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 1223 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 1224 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 1225
NYX 0:85b3fd62ea1a 1226 /* Get PCCARD timing parameters */
NYX 0:85b3fd62ea1a 1227 tmpr = Device->PATT4;
NYX 0:85b3fd62ea1a 1228
NYX 0:85b3fd62ea1a 1229 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
NYX 0:85b3fd62ea1a 1230 tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \
NYX 0:85b3fd62ea1a 1231 FMC_PATT4_ATTHIZ4));
NYX 0:85b3fd62ea1a 1232
NYX 0:85b3fd62ea1a 1233 /* Set PCCARD timing parameters */
NYX 0:85b3fd62ea1a 1234 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 1235 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 1236 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 1237 ((Timing->HiZSetupTime) << 24U));
NYX 0:85b3fd62ea1a 1238 Device->PATT4 = tmpr;
NYX 0:85b3fd62ea1a 1239
NYX 0:85b3fd62ea1a 1240 return HAL_OK;
NYX 0:85b3fd62ea1a 1241 }
NYX 0:85b3fd62ea1a 1242
NYX 0:85b3fd62ea1a 1243 /**
NYX 0:85b3fd62ea1a 1244 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
NYX 0:85b3fd62ea1a 1245 * parameters in the FMC_NAND_PCC_TimingTypeDef
NYX 0:85b3fd62ea1a 1246 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 1247 * @param Timing: Pointer to PCCARD timing structure
NYX 0:85b3fd62ea1a 1248 * @retval HAL status
NYX 0:85b3fd62ea1a 1249 */
NYX 0:85b3fd62ea1a 1250 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
NYX 0:85b3fd62ea1a 1251 {
NYX 0:85b3fd62ea1a 1252 uint32_t tmpr = 0;
NYX 0:85b3fd62ea1a 1253
NYX 0:85b3fd62ea1a 1254 /* Check the parameters */
NYX 0:85b3fd62ea1a 1255 assert_param(IS_FMC_PCCARD_DEVICE(Device));
NYX 0:85b3fd62ea1a 1256 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
NYX 0:85b3fd62ea1a 1257 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
NYX 0:85b3fd62ea1a 1258 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
NYX 0:85b3fd62ea1a 1259 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
NYX 0:85b3fd62ea1a 1260
NYX 0:85b3fd62ea1a 1261 /* Get FMC_PCCARD device timing parameters */
NYX 0:85b3fd62ea1a 1262 tmpr = Device->PIO4;
NYX 0:85b3fd62ea1a 1263
NYX 0:85b3fd62ea1a 1264 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
NYX 0:85b3fd62ea1a 1265 tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \
NYX 0:85b3fd62ea1a 1266 FMC_PIO4_IOHIZ4));
NYX 0:85b3fd62ea1a 1267
NYX 0:85b3fd62ea1a 1268 /* Set FMC_PCCARD device timing parameters */
NYX 0:85b3fd62ea1a 1269 tmpr |= (uint32_t)(Timing->SetupTime |\
NYX 0:85b3fd62ea1a 1270 ((Timing->WaitSetupTime) << 8U) |\
NYX 0:85b3fd62ea1a 1271 ((Timing->HoldSetupTime) << 16U) |\
NYX 0:85b3fd62ea1a 1272 ((Timing->HiZSetupTime) << 24U));
NYX 0:85b3fd62ea1a 1273
NYX 0:85b3fd62ea1a 1274 Device->PIO4 = tmpr;
NYX 0:85b3fd62ea1a 1275
NYX 0:85b3fd62ea1a 1276 return HAL_OK;
NYX 0:85b3fd62ea1a 1277 }
NYX 0:85b3fd62ea1a 1278
NYX 0:85b3fd62ea1a 1279 /**
NYX 0:85b3fd62ea1a 1280 * @brief DeInitializes the FMC_PCCARD device
NYX 0:85b3fd62ea1a 1281 * @param Device: Pointer to PCCARD device instance
NYX 0:85b3fd62ea1a 1282 * @retval HAL status
NYX 0:85b3fd62ea1a 1283 */
NYX 0:85b3fd62ea1a 1284 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
NYX 0:85b3fd62ea1a 1285 {
NYX 0:85b3fd62ea1a 1286 /* Check the parameters */
NYX 0:85b3fd62ea1a 1287 assert_param(IS_FMC_PCCARD_DEVICE(Device));
NYX 0:85b3fd62ea1a 1288
NYX 0:85b3fd62ea1a 1289 /* Disable the FMC_PCCARD device */
NYX 0:85b3fd62ea1a 1290 __FMC_PCCARD_DISABLE(Device);
NYX 0:85b3fd62ea1a 1291
NYX 0:85b3fd62ea1a 1292 /* De-initialize the FMC_PCCARD device */
NYX 0:85b3fd62ea1a 1293 Device->PCR4 = 0x00000018U;
NYX 0:85b3fd62ea1a 1294 Device->SR4 = 0x00000000U;
NYX 0:85b3fd62ea1a 1295 Device->PMEM4 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 1296 Device->PATT4 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 1297 Device->PIO4 = 0xFCFCFCFCU;
NYX 0:85b3fd62ea1a 1298
NYX 0:85b3fd62ea1a 1299 return HAL_OK;
NYX 0:85b3fd62ea1a 1300 }
NYX 0:85b3fd62ea1a 1301
NYX 0:85b3fd62ea1a 1302 /**
NYX 0:85b3fd62ea1a 1303 * @}
NYX 0:85b3fd62ea1a 1304 */
NYX 0:85b3fd62ea1a 1305 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
NYX 0:85b3fd62ea1a 1306
NYX 0:85b3fd62ea1a 1307
NYX 0:85b3fd62ea1a 1308 /** @addtogroup FMC_LL_SDRAM
NYX 0:85b3fd62ea1a 1309 * @brief SDRAM Controller functions
NYX 0:85b3fd62ea1a 1310 *
NYX 0:85b3fd62ea1a 1311 @verbatim
NYX 0:85b3fd62ea1a 1312 ==============================================================================
NYX 0:85b3fd62ea1a 1313 ##### How to use SDRAM device driver #####
NYX 0:85b3fd62ea1a 1314 ==============================================================================
NYX 0:85b3fd62ea1a 1315 [..]
NYX 0:85b3fd62ea1a 1316 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
NYX 0:85b3fd62ea1a 1317 to run the SDRAM external devices.
NYX 0:85b3fd62ea1a 1318
NYX 0:85b3fd62ea1a 1319 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
NYX 0:85b3fd62ea1a 1320 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
NYX 0:85b3fd62ea1a 1321 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
NYX 0:85b3fd62ea1a 1322 (+) FMC SDRAM bank enable/disable write operation using the functions
NYX 0:85b3fd62ea1a 1323 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
NYX 0:85b3fd62ea1a 1324 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
NYX 0:85b3fd62ea1a 1325
NYX 0:85b3fd62ea1a 1326 @endverbatim
NYX 0:85b3fd62ea1a 1327 * @{
NYX 0:85b3fd62ea1a 1328 */
NYX 0:85b3fd62ea1a 1329
NYX 0:85b3fd62ea1a 1330 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
NYX 0:85b3fd62ea1a 1331 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 1332 *
NYX 0:85b3fd62ea1a 1333 @verbatim
NYX 0:85b3fd62ea1a 1334 ==============================================================================
NYX 0:85b3fd62ea1a 1335 ##### Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 1336 ==============================================================================
NYX 0:85b3fd62ea1a 1337 [..]
NYX 0:85b3fd62ea1a 1338 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 1339 (+) Initialize and configure the FMC SDRAM interface
NYX 0:85b3fd62ea1a 1340 (+) De-initialize the FMC SDRAM interface
NYX 0:85b3fd62ea1a 1341 (+) Configure the FMC clock and associated GPIOs
NYX 0:85b3fd62ea1a 1342
NYX 0:85b3fd62ea1a 1343 @endverbatim
NYX 0:85b3fd62ea1a 1344 * @{
NYX 0:85b3fd62ea1a 1345 */
NYX 0:85b3fd62ea1a 1346
NYX 0:85b3fd62ea1a 1347 /**
NYX 0:85b3fd62ea1a 1348 * @brief Initializes the FMC_SDRAM device according to the specified
NYX 0:85b3fd62ea1a 1349 * control parameters in the FMC_SDRAM_InitTypeDef
NYX 0:85b3fd62ea1a 1350 * @param Device: Pointer to SDRAM device instance
NYX 0:85b3fd62ea1a 1351 * @param Init: Pointer to SDRAM Initialization structure
NYX 0:85b3fd62ea1a 1352 * @retval HAL status
NYX 0:85b3fd62ea1a 1353 */
NYX 0:85b3fd62ea1a 1354 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
NYX 0:85b3fd62ea1a 1355 {
NYX 0:85b3fd62ea1a 1356 uint32_t tmpr1 = 0U;
NYX 0:85b3fd62ea1a 1357 uint32_t tmpr2 = 0U;
NYX 0:85b3fd62ea1a 1358
NYX 0:85b3fd62ea1a 1359 /* Check the parameters */
NYX 0:85b3fd62ea1a 1360 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1361 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
NYX 0:85b3fd62ea1a 1362 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
NYX 0:85b3fd62ea1a 1363 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
NYX 0:85b3fd62ea1a 1364 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
NYX 0:85b3fd62ea1a 1365 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
NYX 0:85b3fd62ea1a 1366 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
NYX 0:85b3fd62ea1a 1367 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
NYX 0:85b3fd62ea1a 1368 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
NYX 0:85b3fd62ea1a 1369 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
NYX 0:85b3fd62ea1a 1370 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
NYX 0:85b3fd62ea1a 1371
NYX 0:85b3fd62ea1a 1372 /* Set SDRAM bank configuration parameters */
NYX 0:85b3fd62ea1a 1373 if (Init->SDBank != FMC_SDRAM_BANK2)
NYX 0:85b3fd62ea1a 1374 {
NYX 0:85b3fd62ea1a 1375 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
NYX 0:85b3fd62ea1a 1376
NYX 0:85b3fd62ea1a 1377 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
NYX 0:85b3fd62ea1a 1378 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
NYX 0:85b3fd62ea1a 1379 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
NYX 0:85b3fd62ea1a 1380 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
NYX 0:85b3fd62ea1a 1381
NYX 0:85b3fd62ea1a 1382
NYX 0:85b3fd62ea1a 1383 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
NYX 0:85b3fd62ea1a 1384 Init->RowBitsNumber |\
NYX 0:85b3fd62ea1a 1385 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 1386 Init->InternalBankNumber |\
NYX 0:85b3fd62ea1a 1387 Init->CASLatency |\
NYX 0:85b3fd62ea1a 1388 Init->WriteProtection |\
NYX 0:85b3fd62ea1a 1389 Init->SDClockPeriod |\
NYX 0:85b3fd62ea1a 1390 Init->ReadBurst |\
NYX 0:85b3fd62ea1a 1391 Init->ReadPipeDelay
NYX 0:85b3fd62ea1a 1392 );
NYX 0:85b3fd62ea1a 1393 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
NYX 0:85b3fd62ea1a 1394 }
NYX 0:85b3fd62ea1a 1395 else /* FMC_Bank2_SDRAM */
NYX 0:85b3fd62ea1a 1396 {
NYX 0:85b3fd62ea1a 1397 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
NYX 0:85b3fd62ea1a 1398
NYX 0:85b3fd62ea1a 1399 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
NYX 0:85b3fd62ea1a 1400 tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
NYX 0:85b3fd62ea1a 1401
NYX 0:85b3fd62ea1a 1402 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
NYX 0:85b3fd62ea1a 1403 Init->ReadBurst |\
NYX 0:85b3fd62ea1a 1404 Init->ReadPipeDelay);
NYX 0:85b3fd62ea1a 1405
NYX 0:85b3fd62ea1a 1406 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
NYX 0:85b3fd62ea1a 1407
NYX 0:85b3fd62ea1a 1408 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
NYX 0:85b3fd62ea1a 1409 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
NYX 0:85b3fd62ea1a 1410 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
NYX 0:85b3fd62ea1a 1411 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
NYX 0:85b3fd62ea1a 1412
NYX 0:85b3fd62ea1a 1413 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
NYX 0:85b3fd62ea1a 1414 Init->RowBitsNumber |\
NYX 0:85b3fd62ea1a 1415 Init->MemoryDataWidth |\
NYX 0:85b3fd62ea1a 1416 Init->InternalBankNumber |\
NYX 0:85b3fd62ea1a 1417 Init->CASLatency |\
NYX 0:85b3fd62ea1a 1418 Init->WriteProtection);
NYX 0:85b3fd62ea1a 1419
NYX 0:85b3fd62ea1a 1420 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
NYX 0:85b3fd62ea1a 1421 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
NYX 0:85b3fd62ea1a 1422 }
NYX 0:85b3fd62ea1a 1423
NYX 0:85b3fd62ea1a 1424 return HAL_OK;
NYX 0:85b3fd62ea1a 1425 }
NYX 0:85b3fd62ea1a 1426
NYX 0:85b3fd62ea1a 1427 /**
NYX 0:85b3fd62ea1a 1428 * @brief Initializes the FMC_SDRAM device timing according to the specified
NYX 0:85b3fd62ea1a 1429 * parameters in the FMC_SDRAM_TimingTypeDef
NYX 0:85b3fd62ea1a 1430 * @param Device: Pointer to SDRAM device instance
NYX 0:85b3fd62ea1a 1431 * @param Timing: Pointer to SDRAM Timing structure
NYX 0:85b3fd62ea1a 1432 * @param Bank: SDRAM bank number
NYX 0:85b3fd62ea1a 1433 * @retval HAL status
NYX 0:85b3fd62ea1a 1434 */
NYX 0:85b3fd62ea1a 1435 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
NYX 0:85b3fd62ea1a 1436 {
NYX 0:85b3fd62ea1a 1437 uint32_t tmpr1 = 0U;
NYX 0:85b3fd62ea1a 1438 uint32_t tmpr2 = 0U;
NYX 0:85b3fd62ea1a 1439
NYX 0:85b3fd62ea1a 1440 /* Check the parameters */
NYX 0:85b3fd62ea1a 1441 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1442 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
NYX 0:85b3fd62ea1a 1443 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
NYX 0:85b3fd62ea1a 1444 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
NYX 0:85b3fd62ea1a 1445 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
NYX 0:85b3fd62ea1a 1446 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
NYX 0:85b3fd62ea1a 1447 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
NYX 0:85b3fd62ea1a 1448 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
NYX 0:85b3fd62ea1a 1449 assert_param(IS_FMC_SDRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 1450
NYX 0:85b3fd62ea1a 1451 /* Set SDRAM device timing parameters */
NYX 0:85b3fd62ea1a 1452 if (Bank != FMC_SDRAM_BANK2)
NYX 0:85b3fd62ea1a 1453 {
NYX 0:85b3fd62ea1a 1454 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
NYX 0:85b3fd62ea1a 1455
NYX 0:85b3fd62ea1a 1456 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
NYX 0:85b3fd62ea1a 1457 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
NYX 0:85b3fd62ea1a 1458 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
NYX 0:85b3fd62ea1a 1459 FMC_SDTR1_TRCD));
NYX 0:85b3fd62ea1a 1460
NYX 0:85b3fd62ea1a 1461 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
NYX 0:85b3fd62ea1a 1462 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
NYX 0:85b3fd62ea1a 1463 (((Timing->SelfRefreshTime)-1U) << 8U) |\
NYX 0:85b3fd62ea1a 1464 (((Timing->RowCycleDelay)-1U) << 12U) |\
NYX 0:85b3fd62ea1a 1465 (((Timing->WriteRecoveryTime)-1U) <<16U) |\
NYX 0:85b3fd62ea1a 1466 (((Timing->RPDelay)-1U) << 20U) |\
NYX 0:85b3fd62ea1a 1467 (((Timing->RCDDelay)-1U) << 24U));
NYX 0:85b3fd62ea1a 1468 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
NYX 0:85b3fd62ea1a 1469 }
NYX 0:85b3fd62ea1a 1470 else /* FMC_Bank2_SDRAM */
NYX 0:85b3fd62ea1a 1471 {
NYX 0:85b3fd62ea1a 1472 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
NYX 0:85b3fd62ea1a 1473
NYX 0:85b3fd62ea1a 1474 /* Clear TRC and TRP bits */
NYX 0:85b3fd62ea1a 1475 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
NYX 0:85b3fd62ea1a 1476
NYX 0:85b3fd62ea1a 1477 tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\
NYX 0:85b3fd62ea1a 1478 (((Timing->RPDelay)-1U) << 20U));
NYX 0:85b3fd62ea1a 1479
NYX 0:85b3fd62ea1a 1480 tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
NYX 0:85b3fd62ea1a 1481
NYX 0:85b3fd62ea1a 1482 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
NYX 0:85b3fd62ea1a 1483 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
NYX 0:85b3fd62ea1a 1484 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
NYX 0:85b3fd62ea1a 1485 FMC_SDTR1_TRCD));
NYX 0:85b3fd62ea1a 1486
NYX 0:85b3fd62ea1a 1487 tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\
NYX 0:85b3fd62ea1a 1488 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
NYX 0:85b3fd62ea1a 1489 (((Timing->SelfRefreshTime)-1U) << 8U) |\
NYX 0:85b3fd62ea1a 1490 (((Timing->WriteRecoveryTime)-1U) <<16U) |\
NYX 0:85b3fd62ea1a 1491 (((Timing->RCDDelay)-1U) << 24U)));
NYX 0:85b3fd62ea1a 1492
NYX 0:85b3fd62ea1a 1493 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
NYX 0:85b3fd62ea1a 1494 Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
NYX 0:85b3fd62ea1a 1495 }
NYX 0:85b3fd62ea1a 1496 return HAL_OK;
NYX 0:85b3fd62ea1a 1497 }
NYX 0:85b3fd62ea1a 1498
NYX 0:85b3fd62ea1a 1499 /**
NYX 0:85b3fd62ea1a 1500 * @brief DeInitializes the FMC_SDRAM peripheral
NYX 0:85b3fd62ea1a 1501 * @param Device: Pointer to SDRAM device instance
NYX 0:85b3fd62ea1a 1502 * @retval HAL status
NYX 0:85b3fd62ea1a 1503 */
NYX 0:85b3fd62ea1a 1504 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 1505 {
NYX 0:85b3fd62ea1a 1506 /* Check the parameters */
NYX 0:85b3fd62ea1a 1507 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1508 assert_param(IS_FMC_SDRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 1509
NYX 0:85b3fd62ea1a 1510 /* De-initialize the SDRAM device */
NYX 0:85b3fd62ea1a 1511 Device->SDCR[Bank] = 0x000002D0U;
NYX 0:85b3fd62ea1a 1512 Device->SDTR[Bank] = 0x0FFFFFFFU;
NYX 0:85b3fd62ea1a 1513 Device->SDCMR = 0x00000000U;
NYX 0:85b3fd62ea1a 1514 Device->SDRTR = 0x00000000U;
NYX 0:85b3fd62ea1a 1515 Device->SDSR = 0x00000000U;
NYX 0:85b3fd62ea1a 1516
NYX 0:85b3fd62ea1a 1517 return HAL_OK;
NYX 0:85b3fd62ea1a 1518 }
NYX 0:85b3fd62ea1a 1519
NYX 0:85b3fd62ea1a 1520 /**
NYX 0:85b3fd62ea1a 1521 * @}
NYX 0:85b3fd62ea1a 1522 */
NYX 0:85b3fd62ea1a 1523
NYX 0:85b3fd62ea1a 1524 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
NYX 0:85b3fd62ea1a 1525 * @brief management functions
NYX 0:85b3fd62ea1a 1526 *
NYX 0:85b3fd62ea1a 1527 @verbatim
NYX 0:85b3fd62ea1a 1528 ==============================================================================
NYX 0:85b3fd62ea1a 1529 ##### FMC_SDRAM Control functions #####
NYX 0:85b3fd62ea1a 1530 ==============================================================================
NYX 0:85b3fd62ea1a 1531 [..]
NYX 0:85b3fd62ea1a 1532 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 1533 the FMC SDRAM interface.
NYX 0:85b3fd62ea1a 1534
NYX 0:85b3fd62ea1a 1535 @endverbatim
NYX 0:85b3fd62ea1a 1536 * @{
NYX 0:85b3fd62ea1a 1537 */
NYX 0:85b3fd62ea1a 1538 /**
NYX 0:85b3fd62ea1a 1539 * @brief Enables dynamically FMC_SDRAM write protection.
NYX 0:85b3fd62ea1a 1540 * @param Device: Pointer to SDRAM device instance
NYX 0:85b3fd62ea1a 1541 * @param Bank: SDRAM bank number
NYX 0:85b3fd62ea1a 1542 * @retval HAL status
NYX 0:85b3fd62ea1a 1543 */
NYX 0:85b3fd62ea1a 1544 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 1545 {
NYX 0:85b3fd62ea1a 1546 /* Check the parameters */
NYX 0:85b3fd62ea1a 1547 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1548 assert_param(IS_FMC_SDRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 1549
NYX 0:85b3fd62ea1a 1550 /* Enable write protection */
NYX 0:85b3fd62ea1a 1551 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
NYX 0:85b3fd62ea1a 1552
NYX 0:85b3fd62ea1a 1553 return HAL_OK;
NYX 0:85b3fd62ea1a 1554 }
NYX 0:85b3fd62ea1a 1555
NYX 0:85b3fd62ea1a 1556 /**
NYX 0:85b3fd62ea1a 1557 * @brief Disables dynamically FMC_SDRAM write protection.
NYX 0:85b3fd62ea1a 1558 * @param hsdram: FMC_SDRAM handle
NYX 0:85b3fd62ea1a 1559 * @retval HAL status
NYX 0:85b3fd62ea1a 1560 */
NYX 0:85b3fd62ea1a 1561 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 1562 {
NYX 0:85b3fd62ea1a 1563 /* Check the parameters */
NYX 0:85b3fd62ea1a 1564 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1565 assert_param(IS_FMC_SDRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 1566
NYX 0:85b3fd62ea1a 1567 /* Disable write protection */
NYX 0:85b3fd62ea1a 1568 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
NYX 0:85b3fd62ea1a 1569
NYX 0:85b3fd62ea1a 1570 return HAL_OK;
NYX 0:85b3fd62ea1a 1571 }
NYX 0:85b3fd62ea1a 1572
NYX 0:85b3fd62ea1a 1573 /**
NYX 0:85b3fd62ea1a 1574 * @brief Send Command to the FMC SDRAM bank
NYX 0:85b3fd62ea1a 1575 * @param Device: Pointer to SDRAM device instance
NYX 0:85b3fd62ea1a 1576 * @param Command: Pointer to SDRAM command structure
NYX 0:85b3fd62ea1a 1577 * @param Timing: Pointer to SDRAM Timing structure
NYX 0:85b3fd62ea1a 1578 * @param Timeout: Timeout wait value
NYX 0:85b3fd62ea1a 1579 * @retval HAL state
NYX 0:85b3fd62ea1a 1580 */
NYX 0:85b3fd62ea1a 1581 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
NYX 0:85b3fd62ea1a 1582 {
NYX 0:85b3fd62ea1a 1583 __IO uint32_t tmpr = 0U;
NYX 0:85b3fd62ea1a 1584 uint32_t tickstart = 0U;
NYX 0:85b3fd62ea1a 1585
NYX 0:85b3fd62ea1a 1586 /* Check the parameters */
NYX 0:85b3fd62ea1a 1587 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1588 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
NYX 0:85b3fd62ea1a 1589 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
NYX 0:85b3fd62ea1a 1590 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
NYX 0:85b3fd62ea1a 1591 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
NYX 0:85b3fd62ea1a 1592
NYX 0:85b3fd62ea1a 1593 /* Set command register */
NYX 0:85b3fd62ea1a 1594 tmpr = (uint32_t)((Command->CommandMode) |\
NYX 0:85b3fd62ea1a 1595 (Command->CommandTarget) |\
NYX 0:85b3fd62ea1a 1596 (((Command->AutoRefreshNumber)-1U) << 5U) |\
NYX 0:85b3fd62ea1a 1597 ((Command->ModeRegisterDefinition) << 9U)
NYX 0:85b3fd62ea1a 1598 );
NYX 0:85b3fd62ea1a 1599
NYX 0:85b3fd62ea1a 1600 Device->SDCMR = tmpr;
NYX 0:85b3fd62ea1a 1601
NYX 0:85b3fd62ea1a 1602 /* Get tick */
NYX 0:85b3fd62ea1a 1603 tickstart = HAL_GetTick();
NYX 0:85b3fd62ea1a 1604
NYX 0:85b3fd62ea1a 1605 /* Wait until command is send */
NYX 0:85b3fd62ea1a 1606 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
NYX 0:85b3fd62ea1a 1607 {
NYX 0:85b3fd62ea1a 1608 /* Check for the Timeout */
NYX 0:85b3fd62ea1a 1609 if(Timeout != HAL_MAX_DELAY)
NYX 0:85b3fd62ea1a 1610 {
NYX 0:85b3fd62ea1a 1611 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
NYX 0:85b3fd62ea1a 1612 {
NYX 0:85b3fd62ea1a 1613 return HAL_TIMEOUT;
NYX 0:85b3fd62ea1a 1614 }
NYX 0:85b3fd62ea1a 1615 }
NYX 0:85b3fd62ea1a 1616 }
NYX 0:85b3fd62ea1a 1617
NYX 0:85b3fd62ea1a 1618 return HAL_OK;
NYX 0:85b3fd62ea1a 1619 }
NYX 0:85b3fd62ea1a 1620
NYX 0:85b3fd62ea1a 1621 /**
NYX 0:85b3fd62ea1a 1622 * @brief Program the SDRAM Memory Refresh rate.
NYX 0:85b3fd62ea1a 1623 * @param Device: Pointer to SDRAM device instance
NYX 0:85b3fd62ea1a 1624 * @param RefreshRate: The SDRAM refresh rate value.
NYX 0:85b3fd62ea1a 1625 * @retval HAL state
NYX 0:85b3fd62ea1a 1626 */
NYX 0:85b3fd62ea1a 1627 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
NYX 0:85b3fd62ea1a 1628 {
NYX 0:85b3fd62ea1a 1629 /* Check the parameters */
NYX 0:85b3fd62ea1a 1630 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1631 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
NYX 0:85b3fd62ea1a 1632
NYX 0:85b3fd62ea1a 1633 /* Set the refresh rate in command register */
NYX 0:85b3fd62ea1a 1634 Device->SDRTR |= (RefreshRate<<1U);
NYX 0:85b3fd62ea1a 1635
NYX 0:85b3fd62ea1a 1636 return HAL_OK;
NYX 0:85b3fd62ea1a 1637 }
NYX 0:85b3fd62ea1a 1638
NYX 0:85b3fd62ea1a 1639 /**
NYX 0:85b3fd62ea1a 1640 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
NYX 0:85b3fd62ea1a 1641 * @param Device: Pointer to SDRAM device instance
NYX 0:85b3fd62ea1a 1642 * @param AutoRefreshNumber: Specifies the auto Refresh number.
NYX 0:85b3fd62ea1a 1643 * @retval None
NYX 0:85b3fd62ea1a 1644 */
NYX 0:85b3fd62ea1a 1645 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
NYX 0:85b3fd62ea1a 1646 {
NYX 0:85b3fd62ea1a 1647 /* Check the parameters */
NYX 0:85b3fd62ea1a 1648 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1649 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
NYX 0:85b3fd62ea1a 1650
NYX 0:85b3fd62ea1a 1651 /* Set the Auto-refresh number in command register */
NYX 0:85b3fd62ea1a 1652 Device->SDCMR |= (AutoRefreshNumber << 5U);
NYX 0:85b3fd62ea1a 1653
NYX 0:85b3fd62ea1a 1654 return HAL_OK;
NYX 0:85b3fd62ea1a 1655 }
NYX 0:85b3fd62ea1a 1656
NYX 0:85b3fd62ea1a 1657 /**
NYX 0:85b3fd62ea1a 1658 * @brief Returns the indicated FMC SDRAM bank mode status.
NYX 0:85b3fd62ea1a 1659 * @param Device: Pointer to SDRAM device instance
NYX 0:85b3fd62ea1a 1660 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
NYX 0:85b3fd62ea1a 1661 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
NYX 0:85b3fd62ea1a 1662 * @retval The FMC SDRAM bank mode status, could be on of the following values:
NYX 0:85b3fd62ea1a 1663 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
NYX 0:85b3fd62ea1a 1664 * FMC_SDRAM_POWER_DOWN_MODE.
NYX 0:85b3fd62ea1a 1665 */
NYX 0:85b3fd62ea1a 1666 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
NYX 0:85b3fd62ea1a 1667 {
NYX 0:85b3fd62ea1a 1668 uint32_t tmpreg = 0U;
NYX 0:85b3fd62ea1a 1669
NYX 0:85b3fd62ea1a 1670 /* Check the parameters */
NYX 0:85b3fd62ea1a 1671 assert_param(IS_FMC_SDRAM_DEVICE(Device));
NYX 0:85b3fd62ea1a 1672 assert_param(IS_FMC_SDRAM_BANK(Bank));
NYX 0:85b3fd62ea1a 1673
NYX 0:85b3fd62ea1a 1674 /* Get the corresponding bank mode */
NYX 0:85b3fd62ea1a 1675 if(Bank == FMC_SDRAM_BANK1)
NYX 0:85b3fd62ea1a 1676 {
NYX 0:85b3fd62ea1a 1677 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
NYX 0:85b3fd62ea1a 1678 }
NYX 0:85b3fd62ea1a 1679 else
NYX 0:85b3fd62ea1a 1680 {
NYX 0:85b3fd62ea1a 1681 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
NYX 0:85b3fd62ea1a 1682 }
NYX 0:85b3fd62ea1a 1683
NYX 0:85b3fd62ea1a 1684 /* Return the mode status */
NYX 0:85b3fd62ea1a 1685 return tmpreg;
NYX 0:85b3fd62ea1a 1686 }
NYX 0:85b3fd62ea1a 1687
NYX 0:85b3fd62ea1a 1688 /**
NYX 0:85b3fd62ea1a 1689 * @}
NYX 0:85b3fd62ea1a 1690 */
NYX 0:85b3fd62ea1a 1691
NYX 0:85b3fd62ea1a 1692 /**
NYX 0:85b3fd62ea1a 1693 * @}
NYX 0:85b3fd62ea1a 1694 */
NYX 0:85b3fd62ea1a 1695
NYX 0:85b3fd62ea1a 1696 /**
NYX 0:85b3fd62ea1a 1697 * @}
NYX 0:85b3fd62ea1a 1698 */
NYX 0:85b3fd62ea1a 1699 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 1700 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 1701
NYX 0:85b3fd62ea1a 1702 /**
NYX 0:85b3fd62ea1a 1703 * @}
NYX 0:85b3fd62ea1a 1704 */
NYX 0:85b3fd62ea1a 1705
NYX 0:85b3fd62ea1a 1706 /**
NYX 0:85b3fd62ea1a 1707 * @}
NYX 0:85b3fd62ea1a 1708 */
NYX 0:85b3fd62ea1a 1709
NYX 0:85b3fd62ea1a 1710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/