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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_ll_dma.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of DMA LL module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_LL_DMA_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_LL_DMA_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	47	#include "stm32f4xx.h"
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_LL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	#if defined (DMA1) \|\| defined (DMA2)
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/** @defgroup DMA_LL DMA
NYX	0:85b3fd62ea1a	56	* @{
NYX	0:85b3fd62ea1a	57	*/
NYX	0:85b3fd62ea1a	58
NYX	0:85b3fd62ea1a	59	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	60	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
NYX	0:85b3fd62ea1a	62	* @{
NYX	0:85b3fd62ea1a	63	*/
NYX	0:85b3fd62ea1a	64	/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
NYX	0:85b3fd62ea1a	65	static const uint8_t STREAM_OFFSET_TAB[] =
NYX	0:85b3fd62ea1a	66	{
NYX	0:85b3fd62ea1a	67	(uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
NYX	0:85b3fd62ea1a	68	(uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
NYX	0:85b3fd62ea1a	69	(uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
NYX	0:85b3fd62ea1a	70	(uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
NYX	0:85b3fd62ea1a	71	(uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
NYX	0:85b3fd62ea1a	72	(uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
NYX	0:85b3fd62ea1a	73	(uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
NYX	0:85b3fd62ea1a	74	(uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
NYX	0:85b3fd62ea1a	75	};
NYX	0:85b3fd62ea1a	76
NYX	0:85b3fd62ea1a	77	/**
NYX	0:85b3fd62ea1a	78	* @}
NYX	0:85b3fd62ea1a	79	*/
NYX	0:85b3fd62ea1a	80
NYX	0:85b3fd62ea1a	81	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	82	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
NYX	0:85b3fd62ea1a	83	* @{
NYX	0:85b3fd62ea1a	84	*/
NYX	0:85b3fd62ea1a	85	/**
NYX	0:85b3fd62ea1a	86	* @}
NYX	0:85b3fd62ea1a	87	*/
NYX	0:85b3fd62ea1a	88
NYX	0:85b3fd62ea1a	89
NYX	0:85b3fd62ea1a	90	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	91	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	92	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	93	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
NYX	0:85b3fd62ea1a	94	* @{
NYX	0:85b3fd62ea1a	95	*/
NYX	0:85b3fd62ea1a	96	typedef struct
NYX	0:85b3fd62ea1a	97	{
NYX	0:85b3fd62ea1a	98	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
NYX	0:85b3fd62ea1a	99	or as Source base address in case of memory to memory transfer direction.
NYX	0:85b3fd62ea1a	100
NYX	0:85b3fd62ea1a	101	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
NYX	0:85b3fd62ea1a	102
NYX	0:85b3fd62ea1a	103	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
NYX	0:85b3fd62ea1a	104	or as Destination base address in case of memory to memory transfer direction.
NYX	0:85b3fd62ea1a	105
NYX	0:85b3fd62ea1a	106	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
NYX	0:85b3fd62ea1a	107
NYX	0:85b3fd62ea1a	108	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
NYX	0:85b3fd62ea1a	109	from memory to memory or from peripheral to memory.
NYX	0:85b3fd62ea1a	110	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
NYX	0:85b3fd62ea1a	111
NYX	0:85b3fd62ea1a	112	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
NYX	0:85b3fd62ea1a	113
NYX	0:85b3fd62ea1a	114	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
NYX	0:85b3fd62ea1a	115	This parameter can be a value of @ref DMA_LL_EC_MODE
NYX	0:85b3fd62ea1a	116	@note The circular buffer mode cannot be used if the memory to memory
NYX	0:85b3fd62ea1a	117	data transfer direction is configured on the selected Stream
NYX	0:85b3fd62ea1a	118
NYX	0:85b3fd62ea1a	119	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
NYX	0:85b3fd62ea1a	120
NYX	0:85b3fd62ea1a	121	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
NYX	0:85b3fd62ea1a	122	is incremented or not.
NYX	0:85b3fd62ea1a	123	This parameter can be a value of @ref DMA_LL_EC_PERIPH
NYX	0:85b3fd62ea1a	124
NYX	0:85b3fd62ea1a	125	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
NYX	0:85b3fd62ea1a	126
NYX	0:85b3fd62ea1a	127	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
NYX	0:85b3fd62ea1a	128	is incremented or not.
NYX	0:85b3fd62ea1a	129	This parameter can be a value of @ref DMA_LL_EC_MEMORY
NYX	0:85b3fd62ea1a	130
NYX	0:85b3fd62ea1a	131	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
NYX	0:85b3fd62ea1a	132
NYX	0:85b3fd62ea1a	133	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
NYX	0:85b3fd62ea1a	134	in case of memory to memory transfer direction.
NYX	0:85b3fd62ea1a	135	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
NYX	0:85b3fd62ea1a	136
NYX	0:85b3fd62ea1a	137	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
NYX	0:85b3fd62ea1a	138
NYX	0:85b3fd62ea1a	139	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
NYX	0:85b3fd62ea1a	140	in case of memory to memory transfer direction.
NYX	0:85b3fd62ea1a	141	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
NYX	0:85b3fd62ea1a	142
NYX	0:85b3fd62ea1a	143	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
NYX	0:85b3fd62ea1a	144
NYX	0:85b3fd62ea1a	145	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
NYX	0:85b3fd62ea1a	146	The data unit is equal to the source buffer configuration set in PeripheralSize
NYX	0:85b3fd62ea1a	147	or MemorySize parameters depending in the transfer direction.
NYX	0:85b3fd62ea1a	148	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
NYX	0:85b3fd62ea1a	149
NYX	0:85b3fd62ea1a	150	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
NYX	0:85b3fd62ea1a	151
NYX	0:85b3fd62ea1a	152	uint32_t Channel; /*!< Specifies the peripheral channel.
NYX	0:85b3fd62ea1a	153	This parameter can be a value of @ref DMA_LL_EC_CHANNEL
NYX	0:85b3fd62ea1a	154
NYX	0:85b3fd62ea1a	155	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
NYX	0:85b3fd62ea1a	156
NYX	0:85b3fd62ea1a	157	uint32_t Priority; /*!< Specifies the channel priority level.
NYX	0:85b3fd62ea1a	158	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
NYX	0:85b3fd62ea1a	159
NYX	0:85b3fd62ea1a	160	This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
NYX	0:85b3fd62ea1a	161
NYX	0:85b3fd62ea1a	162	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
NYX	0:85b3fd62ea1a	163	This parameter can be a value of @ref DMA_LL_FIFOMODE
NYX	0:85b3fd62ea1a	164	@note The Direct mode (FIFO mode disabled) cannot be used if the
NYX	0:85b3fd62ea1a	165	memory-to-memory data transfer is configured on the selected stream
NYX	0:85b3fd62ea1a	166
NYX	0:85b3fd62ea1a	167	This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
NYX	0:85b3fd62ea1a	168
NYX	0:85b3fd62ea1a	169	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
NYX	0:85b3fd62ea1a	170	This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
NYX	0:85b3fd62ea1a	171
NYX	0:85b3fd62ea1a	172	This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
NYX	0:85b3fd62ea1a	173
NYX	0:85b3fd62ea1a	174	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
NYX	0:85b3fd62ea1a	175	It specifies the amount of data to be transferred in a single non interruptible
NYX	0:85b3fd62ea1a	176	transaction.
NYX	0:85b3fd62ea1a	177	This parameter can be a value of @ref DMA_LL_EC_MBURST
NYX	0:85b3fd62ea1a	178	@note The burst mode is possible only if the address Increment mode is enabled.
NYX	0:85b3fd62ea1a	179
NYX	0:85b3fd62ea1a	180	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
NYX	0:85b3fd62ea1a	181
NYX	0:85b3fd62ea1a	182	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
NYX	0:85b3fd62ea1a	183	It specifies the amount of data to be transferred in a single non interruptible
NYX	0:85b3fd62ea1a	184	transaction.
NYX	0:85b3fd62ea1a	185	This parameter can be a value of @ref DMA_LL_EC_PBURST
NYX	0:85b3fd62ea1a	186	@note The burst mode is possible only if the address Increment mode is enabled.
NYX	0:85b3fd62ea1a	187
NYX	0:85b3fd62ea1a	188	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
NYX	0:85b3fd62ea1a	189
NYX	0:85b3fd62ea1a	190	} LL_DMA_InitTypeDef;
NYX	0:85b3fd62ea1a	191	/**
NYX	0:85b3fd62ea1a	192	* @}
NYX	0:85b3fd62ea1a	193	*/
NYX	0:85b3fd62ea1a	194	#endif /USE_FULL_LL_DRIVER/
NYX	0:85b3fd62ea1a	195	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	196	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
NYX	0:85b3fd62ea1a	197	* @{
NYX	0:85b3fd62ea1a	198	*/
NYX	0:85b3fd62ea1a	199
NYX	0:85b3fd62ea1a	200	/** @defgroup DMA_LL_EC_STREAM STREAM
NYX	0:85b3fd62ea1a	201	* @{
NYX	0:85b3fd62ea1a	202	*/
NYX	0:85b3fd62ea1a	203	#define LL_DMA_STREAM_0 0x00000000U
NYX	0:85b3fd62ea1a	204	#define LL_DMA_STREAM_1 0x00000001U
NYX	0:85b3fd62ea1a	205	#define LL_DMA_STREAM_2 0x00000002U
NYX	0:85b3fd62ea1a	206	#define LL_DMA_STREAM_3 0x00000003U
NYX	0:85b3fd62ea1a	207	#define LL_DMA_STREAM_4 0x00000004U
NYX	0:85b3fd62ea1a	208	#define LL_DMA_STREAM_5 0x00000005U
NYX	0:85b3fd62ea1a	209	#define LL_DMA_STREAM_6 0x00000006U
NYX	0:85b3fd62ea1a	210	#define LL_DMA_STREAM_7 0x00000007U
NYX	0:85b3fd62ea1a	211	#define LL_DMA_STREAM_ALL 0xFFFF0000U
NYX	0:85b3fd62ea1a	212	/**
NYX	0:85b3fd62ea1a	213	* @}
NYX	0:85b3fd62ea1a	214	*/
NYX	0:85b3fd62ea1a	215
NYX	0:85b3fd62ea1a	216	/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
NYX	0:85b3fd62ea1a	217	* @{
NYX	0:85b3fd62ea1a	218	*/
NYX	0:85b3fd62ea1a	219	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
NYX	0:85b3fd62ea1a	220	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /!< Memory to peripheral direction /
NYX	0:85b3fd62ea1a	221	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /!< Memory to memory direction /
NYX	0:85b3fd62ea1a	222	/**
NYX	0:85b3fd62ea1a	223	* @}
NYX	0:85b3fd62ea1a	224	*/
NYX	0:85b3fd62ea1a	225
NYX	0:85b3fd62ea1a	226	/** @defgroup DMA_LL_EC_MODE MODE
NYX	0:85b3fd62ea1a	227	* @{
NYX	0:85b3fd62ea1a	228	*/
NYX	0:85b3fd62ea1a	229	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
NYX	0:85b3fd62ea1a	230	#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /!< Circular Mode /
NYX	0:85b3fd62ea1a	231	#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /!< Peripheral flow control mode /
NYX	0:85b3fd62ea1a	232	/**
NYX	0:85b3fd62ea1a	233	* @}
NYX	0:85b3fd62ea1a	234	*/
NYX	0:85b3fd62ea1a	235
NYX	0:85b3fd62ea1a	236	/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
NYX	0:85b3fd62ea1a	237	* @{
NYX	0:85b3fd62ea1a	238	*/
NYX	0:85b3fd62ea1a	239	#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /!< Disable double buffering mode /
NYX	0:85b3fd62ea1a	240	#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /!< Enable double buffering mode /
NYX	0:85b3fd62ea1a	241	/**
NYX	0:85b3fd62ea1a	242	* @}
NYX	0:85b3fd62ea1a	243	*/
NYX	0:85b3fd62ea1a	244
NYX	0:85b3fd62ea1a	245	/** @defgroup DMA_LL_EC_PERIPH PERIPH
NYX	0:85b3fd62ea1a	246	* @{
NYX	0:85b3fd62ea1a	247	*/
NYX	0:85b3fd62ea1a	248	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
NYX	0:85b3fd62ea1a	249	#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /!< Peripheral increment mode Enable /
NYX	0:85b3fd62ea1a	250	/**
NYX	0:85b3fd62ea1a	251	* @}
NYX	0:85b3fd62ea1a	252	*/
NYX	0:85b3fd62ea1a	253
NYX	0:85b3fd62ea1a	254	/** @defgroup DMA_LL_EC_MEMORY MEMORY
NYX	0:85b3fd62ea1a	255	* @{
NYX	0:85b3fd62ea1a	256	*/
NYX	0:85b3fd62ea1a	257	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
NYX	0:85b3fd62ea1a	258	#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /!< Memory increment mode Enable /
NYX	0:85b3fd62ea1a	259	/**
NYX	0:85b3fd62ea1a	260	* @}
NYX	0:85b3fd62ea1a	261	*/
NYX	0:85b3fd62ea1a	262
NYX	0:85b3fd62ea1a	263	/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
NYX	0:85b3fd62ea1a	264	* @{
NYX	0:85b3fd62ea1a	265	*/
NYX	0:85b3fd62ea1a	266	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
NYX	0:85b3fd62ea1a	267	#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
NYX	0:85b3fd62ea1a	268	#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /!< Peripheral data alignment : Word /
NYX	0:85b3fd62ea1a	269	/**
NYX	0:85b3fd62ea1a	270	* @}
NYX	0:85b3fd62ea1a	271	*/
NYX	0:85b3fd62ea1a	272
NYX	0:85b3fd62ea1a	273	/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
NYX	0:85b3fd62ea1a	274	* @{
NYX	0:85b3fd62ea1a	275	*/
NYX	0:85b3fd62ea1a	276	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
NYX	0:85b3fd62ea1a	277	#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /!< Memory data alignment : HalfWord /
NYX	0:85b3fd62ea1a	278	#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /!< Memory data alignment : Word /
NYX	0:85b3fd62ea1a	279	/**
NYX	0:85b3fd62ea1a	280	* @}
NYX	0:85b3fd62ea1a	281	*/
NYX	0:85b3fd62ea1a	282
NYX	0:85b3fd62ea1a	283	/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
NYX	0:85b3fd62ea1a	284	* @{
NYX	0:85b3fd62ea1a	285	*/
NYX	0:85b3fd62ea1a	286	#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /!< Peripheral increment offset size is linked to the PSIZE /
NYX	0:85b3fd62ea1a	287	#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /!< Peripheral increment offset size is fixed to 4 (32-bit alignment) /
NYX	0:85b3fd62ea1a	288	/**
NYX	0:85b3fd62ea1a	289	* @}
NYX	0:85b3fd62ea1a	290	*/
NYX	0:85b3fd62ea1a	291
NYX	0:85b3fd62ea1a	292	/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
NYX	0:85b3fd62ea1a	293	* @{
NYX	0:85b3fd62ea1a	294	*/
NYX	0:85b3fd62ea1a	295	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
NYX	0:85b3fd62ea1a	296	#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /!< Priority level : Medium /
NYX	0:85b3fd62ea1a	297	#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /!< Priority level : High /
NYX	0:85b3fd62ea1a	298	#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /!< Priority level : Very_High /
NYX	0:85b3fd62ea1a	299	/**
NYX	0:85b3fd62ea1a	300	* @}
NYX	0:85b3fd62ea1a	301	*/
NYX	0:85b3fd62ea1a	302
NYX	0:85b3fd62ea1a	303	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
NYX	0:85b3fd62ea1a	304	* @{
NYX	0:85b3fd62ea1a	305	*/
NYX	0:85b3fd62ea1a	306	#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
NYX	0:85b3fd62ea1a	307	#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
NYX	0:85b3fd62ea1a	308	#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
NYX	0:85b3fd62ea1a	309	#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 \| DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
NYX	0:85b3fd62ea1a	310	#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
NYX	0:85b3fd62ea1a	311	#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
NYX	0:85b3fd62ea1a	312	#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
NYX	0:85b3fd62ea1a	313	#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1 \| DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
NYX	0:85b3fd62ea1a	314	/**
NYX	0:85b3fd62ea1a	315	* @}
NYX	0:85b3fd62ea1a	316	*/
NYX	0:85b3fd62ea1a	317
NYX	0:85b3fd62ea1a	318	/** @defgroup DMA_LL_EC_MBURST MBURST
NYX	0:85b3fd62ea1a	319	* @{
NYX	0:85b3fd62ea1a	320	*/
NYX	0:85b3fd62ea1a	321	#define LL_DMA_MBURST_SINGLE 0x00000000U /!< Memory burst single transfer configuration /
NYX	0:85b3fd62ea1a	322	#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /!< Memory burst of 4 beats transfer configuration /
NYX	0:85b3fd62ea1a	323	#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /!< Memory burst of 8 beats transfer configuration /
NYX	0:85b3fd62ea1a	324	#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 \| DMA_SxCR_MBURST_1) /!< Memory burst of 16 beats transfer configuration /
NYX	0:85b3fd62ea1a	325	/**
NYX	0:85b3fd62ea1a	326	* @}
NYX	0:85b3fd62ea1a	327	*/
NYX	0:85b3fd62ea1a	328
NYX	0:85b3fd62ea1a	329	/** @defgroup DMA_LL_EC_PBURST PBURST
NYX	0:85b3fd62ea1a	330	* @{
NYX	0:85b3fd62ea1a	331	*/
NYX	0:85b3fd62ea1a	332	#define LL_DMA_PBURST_SINGLE 0x00000000U /!< Peripheral burst single transfer configuration /
NYX	0:85b3fd62ea1a	333	#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /!< Peripheral burst of 4 beats transfer configuration /
NYX	0:85b3fd62ea1a	334	#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /!< Peripheral burst of 8 beats transfer configuration /
NYX	0:85b3fd62ea1a	335	#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 \| DMA_SxCR_PBURST_1) /!< Peripheral burst of 16 beats transfer configuration /
NYX	0:85b3fd62ea1a	336	/**
NYX	0:85b3fd62ea1a	337	* @}
NYX	0:85b3fd62ea1a	338	*/
NYX	0:85b3fd62ea1a	339
NYX	0:85b3fd62ea1a	340	/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
NYX	0:85b3fd62ea1a	341	* @{
NYX	0:85b3fd62ea1a	342	*/
NYX	0:85b3fd62ea1a	343	#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /!< FIFO mode disable (direct mode is enabled) /
NYX	0:85b3fd62ea1a	344	#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /!< FIFO mode enable /
NYX	0:85b3fd62ea1a	345	/**
NYX	0:85b3fd62ea1a	346	* @}
NYX	0:85b3fd62ea1a	347	*/
NYX	0:85b3fd62ea1a	348
NYX	0:85b3fd62ea1a	349	/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
NYX	0:85b3fd62ea1a	350	* @{
NYX	0:85b3fd62ea1a	351	*/
NYX	0:85b3fd62ea1a	352	#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /!< 0 < fifo_level < 1/4 /
NYX	0:85b3fd62ea1a	353	#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /!< 1/4 < fifo_level < 1/2 /
NYX	0:85b3fd62ea1a	354	#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /!< 1/2 < fifo_level < 3/4 /
NYX	0:85b3fd62ea1a	355	#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 \| DMA_SxFCR_FS_0) /!< 3/4 < fifo_level < full /
NYX	0:85b3fd62ea1a	356	#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /!< FIFO is empty /
NYX	0:85b3fd62ea1a	357	#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 \| DMA_SxFCR_FS_0) /!< FIFO is full /
NYX	0:85b3fd62ea1a	358	/**
NYX	0:85b3fd62ea1a	359	* @}
NYX	0:85b3fd62ea1a	360	*/
NYX	0:85b3fd62ea1a	361
NYX	0:85b3fd62ea1a	362	/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
NYX	0:85b3fd62ea1a	363	* @{
NYX	0:85b3fd62ea1a	364	*/
NYX	0:85b3fd62ea1a	365	#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /!< FIFO threshold 1 quart full configuration /
NYX	0:85b3fd62ea1a	366	#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /!< FIFO threshold half full configuration /
NYX	0:85b3fd62ea1a	367	#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /!< FIFO threshold 3 quarts full configuration /
NYX	0:85b3fd62ea1a	368	#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /!< FIFO threshold full configuration /
NYX	0:85b3fd62ea1a	369	/**
NYX	0:85b3fd62ea1a	370	* @}
NYX	0:85b3fd62ea1a	371	*/
NYX	0:85b3fd62ea1a	372
NYX	0:85b3fd62ea1a	373	/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
NYX	0:85b3fd62ea1a	374	* @{
NYX	0:85b3fd62ea1a	375	*/
NYX	0:85b3fd62ea1a	376	#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /!< Set CurrentTarget Memory to Memory 0 /
NYX	0:85b3fd62ea1a	377	#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /!< Set CurrentTarget Memory to Memory 1 /
NYX	0:85b3fd62ea1a	378	/**
NYX	0:85b3fd62ea1a	379	* @}
NYX	0:85b3fd62ea1a	380	*/
NYX	0:85b3fd62ea1a	381
NYX	0:85b3fd62ea1a	382	/**
NYX	0:85b3fd62ea1a	383	* @}
NYX	0:85b3fd62ea1a	384	*/
NYX	0:85b3fd62ea1a	385
NYX	0:85b3fd62ea1a	386	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	387	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
NYX	0:85b3fd62ea1a	388	* @{
NYX	0:85b3fd62ea1a	389	*/
NYX	0:85b3fd62ea1a	390
NYX	0:85b3fd62ea1a	391	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
NYX	0:85b3fd62ea1a	392	* @{
NYX	0:85b3fd62ea1a	393	*/
NYX	0:85b3fd62ea1a	394	/**
NYX	0:85b3fd62ea1a	395	* @brief Write a value in DMA register
NYX	0:85b3fd62ea1a	396	* @param __INSTANCE__ DMA Instance
NYX	0:85b3fd62ea1a	397	* @param __REG__ Register to be written
NYX	0:85b3fd62ea1a	398	* @param __VALUE__ Value to be written in the register
NYX	0:85b3fd62ea1a	399	* @retval None
NYX	0:85b3fd62ea1a	400	*/
NYX	0:85b3fd62ea1a	401	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
NYX	0:85b3fd62ea1a	402
NYX	0:85b3fd62ea1a	403	/**
NYX	0:85b3fd62ea1a	404	* @brief Read a value in DMA register
NYX	0:85b3fd62ea1a	405	* @param __INSTANCE__ DMA Instance
NYX	0:85b3fd62ea1a	406	* @param __REG__ Register to be read
NYX	0:85b3fd62ea1a	407	* @retval Register value
NYX	0:85b3fd62ea1a	408	*/
NYX	0:85b3fd62ea1a	409	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
NYX	0:85b3fd62ea1a	410	/**
NYX	0:85b3fd62ea1a	411	* @}
NYX	0:85b3fd62ea1a	412	*/
NYX	0:85b3fd62ea1a	413
NYX	0:85b3fd62ea1a	414	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
NYX	0:85b3fd62ea1a	415	* @{
NYX	0:85b3fd62ea1a	416	*/
NYX	0:85b3fd62ea1a	417	/**
NYX	0:85b3fd62ea1a	418	* @brief Convert DMAx_Streamy into DMAx
NYX	0:85b3fd62ea1a	419	* @param __STREAM_INSTANCE__ DMAx_Streamy
NYX	0:85b3fd62ea1a	420	* @retval DMAx
NYX	0:85b3fd62ea1a	421	*/
NYX	0:85b3fd62ea1a	422	#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
NYX	0:85b3fd62ea1a	423	(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
NYX	0:85b3fd62ea1a	424
NYX	0:85b3fd62ea1a	425	/**
NYX	0:85b3fd62ea1a	426	* @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
NYX	0:85b3fd62ea1a	427	* @param __STREAM_INSTANCE__ DMAx_Streamy
NYX	0:85b3fd62ea1a	428	* @retval LL_DMA_CHANNEL_y
NYX	0:85b3fd62ea1a	429	*/
NYX	0:85b3fd62ea1a	430	#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
NYX	0:85b3fd62ea1a	431	(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
NYX	0:85b3fd62ea1a	432	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
NYX	0:85b3fd62ea1a	433	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
NYX	0:85b3fd62ea1a	434	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
NYX	0:85b3fd62ea1a	435	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
NYX	0:85b3fd62ea1a	436	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
NYX	0:85b3fd62ea1a	437	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
NYX	0:85b3fd62ea1a	438	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
NYX	0:85b3fd62ea1a	439	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
NYX	0:85b3fd62ea1a	440	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
NYX	0:85b3fd62ea1a	441	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
NYX	0:85b3fd62ea1a	442	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
NYX	0:85b3fd62ea1a	443	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
NYX	0:85b3fd62ea1a	444	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
NYX	0:85b3fd62ea1a	445	LL_DMA_STREAM_7)
NYX	0:85b3fd62ea1a	446
NYX	0:85b3fd62ea1a	447	/**
NYX	0:85b3fd62ea1a	448	* @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
NYX	0:85b3fd62ea1a	449	* @param __DMA_INSTANCE__ DMAx
NYX	0:85b3fd62ea1a	450	* @param __STREAM__ LL_DMA_STREAM_y
NYX	0:85b3fd62ea1a	451	* @retval DMAx_Streamy
NYX	0:85b3fd62ea1a	452	*/
NYX	0:85b3fd62ea1a	453	#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
NYX	0:85b3fd62ea1a	454	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
NYX	0:85b3fd62ea1a	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
NYX	0:85b3fd62ea1a	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
NYX	0:85b3fd62ea1a	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
NYX	0:85b3fd62ea1a	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
NYX	0:85b3fd62ea1a	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
NYX	0:85b3fd62ea1a	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
NYX	0:85b3fd62ea1a	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
NYX	0:85b3fd62ea1a	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
NYX	0:85b3fd62ea1a	463	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
NYX	0:85b3fd62ea1a	464	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
NYX	0:85b3fd62ea1a	465	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
NYX	0:85b3fd62ea1a	466	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
NYX	0:85b3fd62ea1a	467	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
NYX	0:85b3fd62ea1a	468	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
NYX	0:85b3fd62ea1a	469	DMA2_Stream7)
NYX	0:85b3fd62ea1a	470
NYX	0:85b3fd62ea1a	471	/**
NYX	0:85b3fd62ea1a	472	* @}
NYX	0:85b3fd62ea1a	473	*/
NYX	0:85b3fd62ea1a	474
NYX	0:85b3fd62ea1a	475	/**
NYX	0:85b3fd62ea1a	476	* @}
NYX	0:85b3fd62ea1a	477	*/
NYX	0:85b3fd62ea1a	478
NYX	0:85b3fd62ea1a	479
NYX	0:85b3fd62ea1a	480	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	481	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
NYX	0:85b3fd62ea1a	482	* @{
NYX	0:85b3fd62ea1a	483	*/
NYX	0:85b3fd62ea1a	484
NYX	0:85b3fd62ea1a	485	/** @defgroup DMA_LL_EF_Configuration Configuration
NYX	0:85b3fd62ea1a	486	* @{
NYX	0:85b3fd62ea1a	487	*/
NYX	0:85b3fd62ea1a	488	/**
NYX	0:85b3fd62ea1a	489	* @brief Enable DMA stream.
NYX	0:85b3fd62ea1a	490	* @rmtoll CR EN LL_DMA_EnableStream
NYX	0:85b3fd62ea1a	491	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	492	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	493	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	494	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	495	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	496	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	497	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	498	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	499	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	500	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	501	* @retval None
NYX	0:85b3fd62ea1a	502	*/
NYX	0:85b3fd62ea1a	503	__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	504	{
NYX	0:85b3fd62ea1a	505	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
NYX	0:85b3fd62ea1a	506	}
NYX	0:85b3fd62ea1a	507
NYX	0:85b3fd62ea1a	508	/**
NYX	0:85b3fd62ea1a	509	* @brief Disable DMA stream.
NYX	0:85b3fd62ea1a	510	* @rmtoll CR EN LL_DMA_DisableStream
NYX	0:85b3fd62ea1a	511	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	512	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	513	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	514	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	515	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	516	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	517	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	518	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	519	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	520	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	521	* @retval None
NYX	0:85b3fd62ea1a	522	*/
NYX	0:85b3fd62ea1a	523	__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	524	{
NYX	0:85b3fd62ea1a	525	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
NYX	0:85b3fd62ea1a	526	}
NYX	0:85b3fd62ea1a	527
NYX	0:85b3fd62ea1a	528	/**
NYX	0:85b3fd62ea1a	529	* @brief Check if DMA stream is enabled or disabled.
NYX	0:85b3fd62ea1a	530	* @rmtoll CR EN LL_DMA_IsEnabledStream
NYX	0:85b3fd62ea1a	531	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	532	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	533	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	534	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	535	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	536	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	537	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	538	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	539	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	540	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	541	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	542	*/
NYX	0:85b3fd62ea1a	543	__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	544	{
NYX	0:85b3fd62ea1a	545	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
NYX	0:85b3fd62ea1a	546	}
NYX	0:85b3fd62ea1a	547
NYX	0:85b3fd62ea1a	548	/**
NYX	0:85b3fd62ea1a	549	* @brief Configure all parameters linked to DMA transfer.
NYX	0:85b3fd62ea1a	550	* @rmtoll CR DIR LL_DMA_ConfigTransfer\n
NYX	0:85b3fd62ea1a	551	* CR CIRC LL_DMA_ConfigTransfer\n
NYX	0:85b3fd62ea1a	552	* CR PINC LL_DMA_ConfigTransfer\n
NYX	0:85b3fd62ea1a	553	* CR MINC LL_DMA_ConfigTransfer\n
NYX	0:85b3fd62ea1a	554	* CR PSIZE LL_DMA_ConfigTransfer\n
NYX	0:85b3fd62ea1a	555	* CR MSIZE LL_DMA_ConfigTransfer\n
NYX	0:85b3fd62ea1a	556	* CR PL LL_DMA_ConfigTransfer\n
NYX	0:85b3fd62ea1a	557	* CR PFCTRL LL_DMA_ConfigTransfer
NYX	0:85b3fd62ea1a	558	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	559	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	560	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	561	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	562	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	563	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	564	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	565	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	566	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	567	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	568	* @param Configuration This parameter must be a combination of all the following values:
NYX	0:85b3fd62ea1a	569	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
NYX	0:85b3fd62ea1a	570	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
NYX	0:85b3fd62ea1a	571	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
NYX	0:85b3fd62ea1a	572	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
NYX	0:85b3fd62ea1a	573	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
NYX	0:85b3fd62ea1a	574	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
NYX	0:85b3fd62ea1a	575	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
NYX	0:85b3fd62ea1a	576	*@retval None
NYX	0:85b3fd62ea1a	577	*/
NYX	0:85b3fd62ea1a	578	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
NYX	0:85b3fd62ea1a	579	{
NYX	0:85b3fd62ea1a	580	MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
NYX	0:85b3fd62ea1a	581	DMA_SxCR_DIR \| DMA_SxCR_CIRC \| DMA_SxCR_PINC \| DMA_SxCR_MINC \| DMA_SxCR_PSIZE \| DMA_SxCR_MSIZE \| DMA_SxCR_PL \| DMA_SxCR_PFCTRL,
NYX	0:85b3fd62ea1a	582	Configuration);
NYX	0:85b3fd62ea1a	583	}
NYX	0:85b3fd62ea1a	584
NYX	0:85b3fd62ea1a	585	/**
NYX	0:85b3fd62ea1a	586	* @brief Set Data transfer direction (read from peripheral or from memory).
NYX	0:85b3fd62ea1a	587	* @rmtoll CR DIR LL_DMA_SetDataTransferDirection
NYX	0:85b3fd62ea1a	588	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	589	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	590	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	591	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	592	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	593	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	594	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	595	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	596	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	597	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	598	* @param Direction This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	599	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
NYX	0:85b3fd62ea1a	600	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
NYX	0:85b3fd62ea1a	601	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
NYX	0:85b3fd62ea1a	602	* @retval None
NYX	0:85b3fd62ea1a	603	*/
NYX	0:85b3fd62ea1a	604	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
NYX	0:85b3fd62ea1a	605	{
NYX	0:85b3fd62ea1a	606	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
NYX	0:85b3fd62ea1a	607	}
NYX	0:85b3fd62ea1a	608
NYX	0:85b3fd62ea1a	609	/**
NYX	0:85b3fd62ea1a	610	* @brief Get Data transfer direction (read from peripheral or from memory).
NYX	0:85b3fd62ea1a	611	* @rmtoll CR DIR LL_DMA_GetDataTransferDirection
NYX	0:85b3fd62ea1a	612	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	613	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	614	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	615	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	616	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	617	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	618	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	619	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	620	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	621	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	622	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	623	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
NYX	0:85b3fd62ea1a	624	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
NYX	0:85b3fd62ea1a	625	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
NYX	0:85b3fd62ea1a	626	*/
NYX	0:85b3fd62ea1a	627	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	628	{
NYX	0:85b3fd62ea1a	629	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
NYX	0:85b3fd62ea1a	630	}
NYX	0:85b3fd62ea1a	631
NYX	0:85b3fd62ea1a	632	/**
NYX	0:85b3fd62ea1a	633	* @brief Set DMA mode normal, circular or peripheral flow control.
NYX	0:85b3fd62ea1a	634	* @rmtoll CR CIRC LL_DMA_SetMode\n
NYX	0:85b3fd62ea1a	635	* CR PFCTRL LL_DMA_SetMode
NYX	0:85b3fd62ea1a	636	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	637	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	638	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	639	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	640	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	641	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	642	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	643	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	644	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	645	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	646	* @param Mode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	647	* @arg @ref LL_DMA_MODE_NORMAL
NYX	0:85b3fd62ea1a	648	* @arg @ref LL_DMA_MODE_CIRCULAR
NYX	0:85b3fd62ea1a	649	* @arg @ref LL_DMA_MODE_PFCTRL
NYX	0:85b3fd62ea1a	650	* @retval None
NYX	0:85b3fd62ea1a	651	*/
NYX	0:85b3fd62ea1a	652	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
NYX	0:85b3fd62ea1a	653	{
NYX	0:85b3fd62ea1a	654	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL, Mode);
NYX	0:85b3fd62ea1a	655	}
NYX	0:85b3fd62ea1a	656
NYX	0:85b3fd62ea1a	657	/**
NYX	0:85b3fd62ea1a	658	* @brief Get DMA mode normal, circular or peripheral flow control.
NYX	0:85b3fd62ea1a	659	* @rmtoll CR CIRC LL_DMA_GetMode\n
NYX	0:85b3fd62ea1a	660	* CR PFCTRL LL_DMA_GetMode
NYX	0:85b3fd62ea1a	661	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	662	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	663	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	664	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	665	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	666	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	667	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	668	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	669	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	670	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	671	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	672	* @arg @ref LL_DMA_MODE_NORMAL
NYX	0:85b3fd62ea1a	673	* @arg @ref LL_DMA_MODE_CIRCULAR
NYX	0:85b3fd62ea1a	674	* @arg @ref LL_DMA_MODE_PFCTRL
NYX	0:85b3fd62ea1a	675	*/
NYX	0:85b3fd62ea1a	676	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	677	{
NYX	0:85b3fd62ea1a	678	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL));
NYX	0:85b3fd62ea1a	679	}
NYX	0:85b3fd62ea1a	680
NYX	0:85b3fd62ea1a	681	/**
NYX	0:85b3fd62ea1a	682	* @brief Set Peripheral increment mode.
NYX	0:85b3fd62ea1a	683	* @rmtoll CR PINC LL_DMA_SetPeriphIncMode
NYX	0:85b3fd62ea1a	684	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	685	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	686	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	687	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	688	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	689	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	690	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	691	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	692	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	693	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	694	* @param IncrementMode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	695	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
NYX	0:85b3fd62ea1a	696	* @arg @ref LL_DMA_PERIPH_INCREMENT
NYX	0:85b3fd62ea1a	697	* @retval None
NYX	0:85b3fd62ea1a	698	*/
NYX	0:85b3fd62ea1a	699	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
NYX	0:85b3fd62ea1a	700	{
NYX	0:85b3fd62ea1a	701	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
NYX	0:85b3fd62ea1a	702	}
NYX	0:85b3fd62ea1a	703
NYX	0:85b3fd62ea1a	704	/**
NYX	0:85b3fd62ea1a	705	* @brief Get Peripheral increment mode.
NYX	0:85b3fd62ea1a	706	* @rmtoll CR PINC LL_DMA_GetPeriphIncMode
NYX	0:85b3fd62ea1a	707	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	708	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	709	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	710	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	711	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	712	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	713	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	714	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	715	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	716	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	717	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	718	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
NYX	0:85b3fd62ea1a	719	* @arg @ref LL_DMA_PERIPH_INCREMENT
NYX	0:85b3fd62ea1a	720	*/
NYX	0:85b3fd62ea1a	721	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	722	{
NYX	0:85b3fd62ea1a	723	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
NYX	0:85b3fd62ea1a	724	}
NYX	0:85b3fd62ea1a	725
NYX	0:85b3fd62ea1a	726	/**
NYX	0:85b3fd62ea1a	727	* @brief Set Memory increment mode.
NYX	0:85b3fd62ea1a	728	* @rmtoll CR MINC LL_DMA_SetMemoryIncMode
NYX	0:85b3fd62ea1a	729	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	730	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	731	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	732	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	733	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	734	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	735	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	736	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	737	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	738	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	739	* @param IncrementMode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	740	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
NYX	0:85b3fd62ea1a	741	* @arg @ref LL_DMA_MEMORY_INCREMENT
NYX	0:85b3fd62ea1a	742	* @retval None
NYX	0:85b3fd62ea1a	743	*/
NYX	0:85b3fd62ea1a	744	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
NYX	0:85b3fd62ea1a	745	{
NYX	0:85b3fd62ea1a	746	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
NYX	0:85b3fd62ea1a	747	}
NYX	0:85b3fd62ea1a	748
NYX	0:85b3fd62ea1a	749	/**
NYX	0:85b3fd62ea1a	750	* @brief Get Memory increment mode.
NYX	0:85b3fd62ea1a	751	* @rmtoll CR MINC LL_DMA_GetMemoryIncMode
NYX	0:85b3fd62ea1a	752	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	753	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	754	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	755	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	756	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	757	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	758	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	759	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	760	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	761	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	762	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	763	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
NYX	0:85b3fd62ea1a	764	* @arg @ref LL_DMA_MEMORY_INCREMENT
NYX	0:85b3fd62ea1a	765	*/
NYX	0:85b3fd62ea1a	766	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	767	{
NYX	0:85b3fd62ea1a	768	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
NYX	0:85b3fd62ea1a	769	}
NYX	0:85b3fd62ea1a	770
NYX	0:85b3fd62ea1a	771	/**
NYX	0:85b3fd62ea1a	772	* @brief Set Peripheral size.
NYX	0:85b3fd62ea1a	773	* @rmtoll CR PSIZE LL_DMA_SetPeriphSize
NYX	0:85b3fd62ea1a	774	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	775	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	776	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	777	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	778	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	779	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	780	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	781	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	782	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	783	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	784	* @param Size This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	785	* @arg @ref LL_DMA_PDATAALIGN_BYTE
NYX	0:85b3fd62ea1a	786	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
NYX	0:85b3fd62ea1a	787	* @arg @ref LL_DMA_PDATAALIGN_WORD
NYX	0:85b3fd62ea1a	788	* @retval None
NYX	0:85b3fd62ea1a	789	*/
NYX	0:85b3fd62ea1a	790	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
NYX	0:85b3fd62ea1a	791	{
NYX	0:85b3fd62ea1a	792	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
NYX	0:85b3fd62ea1a	793	}
NYX	0:85b3fd62ea1a	794
NYX	0:85b3fd62ea1a	795	/**
NYX	0:85b3fd62ea1a	796	* @brief Get Peripheral size.
NYX	0:85b3fd62ea1a	797	* @rmtoll CR PSIZE LL_DMA_GetPeriphSize
NYX	0:85b3fd62ea1a	798	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	799	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	800	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	801	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	802	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	803	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	804	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	805	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	806	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	807	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	808	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	809	* @arg @ref LL_DMA_PDATAALIGN_BYTE
NYX	0:85b3fd62ea1a	810	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
NYX	0:85b3fd62ea1a	811	* @arg @ref LL_DMA_PDATAALIGN_WORD
NYX	0:85b3fd62ea1a	812	*/
NYX	0:85b3fd62ea1a	813	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	814	{
NYX	0:85b3fd62ea1a	815	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
NYX	0:85b3fd62ea1a	816	}
NYX	0:85b3fd62ea1a	817
NYX	0:85b3fd62ea1a	818	/**
NYX	0:85b3fd62ea1a	819	* @brief Set Memory size.
NYX	0:85b3fd62ea1a	820	* @rmtoll CR MSIZE LL_DMA_SetMemorySize
NYX	0:85b3fd62ea1a	821	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	822	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	823	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	824	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	825	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	826	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	827	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	828	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	829	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	830	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	831	* @param Size This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	832	* @arg @ref LL_DMA_MDATAALIGN_BYTE
NYX	0:85b3fd62ea1a	833	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
NYX	0:85b3fd62ea1a	834	* @arg @ref LL_DMA_MDATAALIGN_WORD
NYX	0:85b3fd62ea1a	835	* @retval None
NYX	0:85b3fd62ea1a	836	*/
NYX	0:85b3fd62ea1a	837	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
NYX	0:85b3fd62ea1a	838	{
NYX	0:85b3fd62ea1a	839	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
NYX	0:85b3fd62ea1a	840	}
NYX	0:85b3fd62ea1a	841
NYX	0:85b3fd62ea1a	842	/**
NYX	0:85b3fd62ea1a	843	* @brief Get Memory size.
NYX	0:85b3fd62ea1a	844	* @rmtoll CR MSIZE LL_DMA_GetMemorySize
NYX	0:85b3fd62ea1a	845	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	846	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	847	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	848	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	849	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	850	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	851	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	852	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	853	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	854	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	855	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	856	* @arg @ref LL_DMA_MDATAALIGN_BYTE
NYX	0:85b3fd62ea1a	857	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
NYX	0:85b3fd62ea1a	858	* @arg @ref LL_DMA_MDATAALIGN_WORD
NYX	0:85b3fd62ea1a	859	*/
NYX	0:85b3fd62ea1a	860	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	861	{
NYX	0:85b3fd62ea1a	862	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
NYX	0:85b3fd62ea1a	863	}
NYX	0:85b3fd62ea1a	864
NYX	0:85b3fd62ea1a	865	/**
NYX	0:85b3fd62ea1a	866	* @brief Set Peripheral increment offset size.
NYX	0:85b3fd62ea1a	867	* @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
NYX	0:85b3fd62ea1a	868	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	869	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	870	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	871	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	872	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	873	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	874	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	875	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	876	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	877	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	878	* @param OffsetSize This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	879	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
NYX	0:85b3fd62ea1a	880	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
NYX	0:85b3fd62ea1a	881	* @retval None
NYX	0:85b3fd62ea1a	882	*/
NYX	0:85b3fd62ea1a	883	__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
NYX	0:85b3fd62ea1a	884	{
NYX	0:85b3fd62ea1a	885	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
NYX	0:85b3fd62ea1a	886	}
NYX	0:85b3fd62ea1a	887
NYX	0:85b3fd62ea1a	888	/**
NYX	0:85b3fd62ea1a	889	* @brief Get Peripheral increment offset size.
NYX	0:85b3fd62ea1a	890	* @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
NYX	0:85b3fd62ea1a	891	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	892	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	893	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	894	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	895	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	896	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	897	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	898	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	899	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	900	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	901	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	902	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
NYX	0:85b3fd62ea1a	903	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
NYX	0:85b3fd62ea1a	904	*/
NYX	0:85b3fd62ea1a	905	__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	906	{
NYX	0:85b3fd62ea1a	907	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
NYX	0:85b3fd62ea1a	908	}
NYX	0:85b3fd62ea1a	909
NYX	0:85b3fd62ea1a	910	/**
NYX	0:85b3fd62ea1a	911	* @brief Set Stream priority level.
NYX	0:85b3fd62ea1a	912	* @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
NYX	0:85b3fd62ea1a	913	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	914	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	915	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	916	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	917	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	918	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	919	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	920	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	921	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	922	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	923	* @param Priority This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	924	* @arg @ref LL_DMA_PRIORITY_LOW
NYX	0:85b3fd62ea1a	925	* @arg @ref LL_DMA_PRIORITY_MEDIUM
NYX	0:85b3fd62ea1a	926	* @arg @ref LL_DMA_PRIORITY_HIGH
NYX	0:85b3fd62ea1a	927	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
NYX	0:85b3fd62ea1a	928	* @retval None
NYX	0:85b3fd62ea1a	929	*/
NYX	0:85b3fd62ea1a	930	__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
NYX	0:85b3fd62ea1a	931	{
NYX	0:85b3fd62ea1a	932	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
NYX	0:85b3fd62ea1a	933	}
NYX	0:85b3fd62ea1a	934
NYX	0:85b3fd62ea1a	935	/**
NYX	0:85b3fd62ea1a	936	* @brief Get Stream priority level.
NYX	0:85b3fd62ea1a	937	* @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
NYX	0:85b3fd62ea1a	938	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	939	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	940	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	941	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	942	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	943	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	944	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	945	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	946	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	947	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	948	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	949	* @arg @ref LL_DMA_PRIORITY_LOW
NYX	0:85b3fd62ea1a	950	* @arg @ref LL_DMA_PRIORITY_MEDIUM
NYX	0:85b3fd62ea1a	951	* @arg @ref LL_DMA_PRIORITY_HIGH
NYX	0:85b3fd62ea1a	952	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
NYX	0:85b3fd62ea1a	953	*/
NYX	0:85b3fd62ea1a	954	__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	955	{
NYX	0:85b3fd62ea1a	956	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
NYX	0:85b3fd62ea1a	957	}
NYX	0:85b3fd62ea1a	958
NYX	0:85b3fd62ea1a	959	/**
NYX	0:85b3fd62ea1a	960	* @brief Set Number of data to transfer.
NYX	0:85b3fd62ea1a	961	* @rmtoll NDTR NDT LL_DMA_SetDataLength
NYX	0:85b3fd62ea1a	962	* @note This action has no effect if
NYX	0:85b3fd62ea1a	963	* stream is enabled.
NYX	0:85b3fd62ea1a	964	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	965	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	966	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	967	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	968	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	969	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	970	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	971	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	972	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	973	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	974	* @param NbData Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	975	* @retval None
NYX	0:85b3fd62ea1a	976	*/
NYX	0:85b3fd62ea1a	977	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
NYX	0:85b3fd62ea1a	978	{
NYX	0:85b3fd62ea1a	979	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
NYX	0:85b3fd62ea1a	980	}
NYX	0:85b3fd62ea1a	981
NYX	0:85b3fd62ea1a	982	/**
NYX	0:85b3fd62ea1a	983	* @brief Get Number of data to transfer.
NYX	0:85b3fd62ea1a	984	* @rmtoll NDTR NDT LL_DMA_GetDataLength
NYX	0:85b3fd62ea1a	985	* @note Once the stream is enabled, the return value indicate the
NYX	0:85b3fd62ea1a	986	* remaining bytes to be transmitted.
NYX	0:85b3fd62ea1a	987	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	988	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	989	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	990	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	991	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	992	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	993	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	994	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	995	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	996	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	997	* @retval Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	998	*/
NYX	0:85b3fd62ea1a	999	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1000	{
NYX	0:85b3fd62ea1a	1001	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
NYX	0:85b3fd62ea1a	1002	}
NYX	0:85b3fd62ea1a	1003
NYX	0:85b3fd62ea1a	1004	/**
NYX	0:85b3fd62ea1a	1005	* @brief Select Channel number associated to the Stream.
NYX	0:85b3fd62ea1a	1006	* @rmtoll CR CHSEL LL_DMA_SetChannelSelection
NYX	0:85b3fd62ea1a	1007	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1008	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1009	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1010	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1011	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1012	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1013	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1014	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1015	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1016	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1017	* @param Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1018	* @arg @ref LL_DMA_CHANNEL_0
NYX	0:85b3fd62ea1a	1019	* @arg @ref LL_DMA_CHANNEL_1
NYX	0:85b3fd62ea1a	1020	* @arg @ref LL_DMA_CHANNEL_2
NYX	0:85b3fd62ea1a	1021	* @arg @ref LL_DMA_CHANNEL_3
NYX	0:85b3fd62ea1a	1022	* @arg @ref LL_DMA_CHANNEL_4
NYX	0:85b3fd62ea1a	1023	* @arg @ref LL_DMA_CHANNEL_5
NYX	0:85b3fd62ea1a	1024	* @arg @ref LL_DMA_CHANNEL_6
NYX	0:85b3fd62ea1a	1025	* @arg @ref LL_DMA_CHANNEL_7
NYX	0:85b3fd62ea1a	1026	* @retval None
NYX	0:85b3fd62ea1a	1027	*/
NYX	0:85b3fd62ea1a	1028	__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
NYX	0:85b3fd62ea1a	1029	{
NYX	0:85b3fd62ea1a	1030	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
NYX	0:85b3fd62ea1a	1031	}
NYX	0:85b3fd62ea1a	1032
NYX	0:85b3fd62ea1a	1033	/**
NYX	0:85b3fd62ea1a	1034	* @brief Get the Channel number associated to the Stream.
NYX	0:85b3fd62ea1a	1035	* @rmtoll CR CHSEL LL_DMA_GetChannelSelection
NYX	0:85b3fd62ea1a	1036	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1037	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1038	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1039	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1040	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1041	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1042	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1043	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1044	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1045	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1046	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1047	* @arg @ref LL_DMA_CHANNEL_0
NYX	0:85b3fd62ea1a	1048	* @arg @ref LL_DMA_CHANNEL_1
NYX	0:85b3fd62ea1a	1049	* @arg @ref LL_DMA_CHANNEL_2
NYX	0:85b3fd62ea1a	1050	* @arg @ref LL_DMA_CHANNEL_3
NYX	0:85b3fd62ea1a	1051	* @arg @ref LL_DMA_CHANNEL_4
NYX	0:85b3fd62ea1a	1052	* @arg @ref LL_DMA_CHANNEL_5
NYX	0:85b3fd62ea1a	1053	* @arg @ref LL_DMA_CHANNEL_6
NYX	0:85b3fd62ea1a	1054	* @arg @ref LL_DMA_CHANNEL_7
NYX	0:85b3fd62ea1a	1055	*/
NYX	0:85b3fd62ea1a	1056	__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1057	{
NYX	0:85b3fd62ea1a	1058	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
NYX	0:85b3fd62ea1a	1059	}
NYX	0:85b3fd62ea1a	1060
NYX	0:85b3fd62ea1a	1061	/**
NYX	0:85b3fd62ea1a	1062	* @brief Set Memory burst transfer configuration.
NYX	0:85b3fd62ea1a	1063	* @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
NYX	0:85b3fd62ea1a	1064	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1065	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1066	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1067	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1068	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1069	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1070	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1071	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1072	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1073	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1074	* @param Mburst This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1075	* @arg @ref LL_DMA_MBURST_SINGLE
NYX	0:85b3fd62ea1a	1076	* @arg @ref LL_DMA_MBURST_INC4
NYX	0:85b3fd62ea1a	1077	* @arg @ref LL_DMA_MBURST_INC8
NYX	0:85b3fd62ea1a	1078	* @arg @ref LL_DMA_MBURST_INC16
NYX	0:85b3fd62ea1a	1079	* @retval None
NYX	0:85b3fd62ea1a	1080	*/
NYX	0:85b3fd62ea1a	1081	__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
NYX	0:85b3fd62ea1a	1082	{
NYX	0:85b3fd62ea1a	1083	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
NYX	0:85b3fd62ea1a	1084	}
NYX	0:85b3fd62ea1a	1085
NYX	0:85b3fd62ea1a	1086	/**
NYX	0:85b3fd62ea1a	1087	* @brief Get Memory burst transfer configuration.
NYX	0:85b3fd62ea1a	1088	* @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
NYX	0:85b3fd62ea1a	1089	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1090	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1091	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1092	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1093	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1094	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1095	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1096	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1097	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1098	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1099	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1100	* @arg @ref LL_DMA_MBURST_SINGLE
NYX	0:85b3fd62ea1a	1101	* @arg @ref LL_DMA_MBURST_INC4
NYX	0:85b3fd62ea1a	1102	* @arg @ref LL_DMA_MBURST_INC8
NYX	0:85b3fd62ea1a	1103	* @arg @ref LL_DMA_MBURST_INC16
NYX	0:85b3fd62ea1a	1104	*/
NYX	0:85b3fd62ea1a	1105	__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1106	{
NYX	0:85b3fd62ea1a	1107	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
NYX	0:85b3fd62ea1a	1108	}
NYX	0:85b3fd62ea1a	1109
NYX	0:85b3fd62ea1a	1110	/**
NYX	0:85b3fd62ea1a	1111	* @brief Set Peripheral burst transfer configuration.
NYX	0:85b3fd62ea1a	1112	* @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
NYX	0:85b3fd62ea1a	1113	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1114	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1115	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1116	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1117	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1118	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1119	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1120	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1121	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1122	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1123	* @param Pburst This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1124	* @arg @ref LL_DMA_PBURST_SINGLE
NYX	0:85b3fd62ea1a	1125	* @arg @ref LL_DMA_PBURST_INC4
NYX	0:85b3fd62ea1a	1126	* @arg @ref LL_DMA_PBURST_INC8
NYX	0:85b3fd62ea1a	1127	* @arg @ref LL_DMA_PBURST_INC16
NYX	0:85b3fd62ea1a	1128	* @retval None
NYX	0:85b3fd62ea1a	1129	*/
NYX	0:85b3fd62ea1a	1130	__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
NYX	0:85b3fd62ea1a	1131	{
NYX	0:85b3fd62ea1a	1132	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
NYX	0:85b3fd62ea1a	1133	}
NYX	0:85b3fd62ea1a	1134
NYX	0:85b3fd62ea1a	1135	/**
NYX	0:85b3fd62ea1a	1136	* @brief Get Peripheral burst transfer configuration.
NYX	0:85b3fd62ea1a	1137	* @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
NYX	0:85b3fd62ea1a	1138	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1139	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1140	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1141	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1142	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1143	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1144	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1145	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1146	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1147	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1148	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1149	* @arg @ref LL_DMA_PBURST_SINGLE
NYX	0:85b3fd62ea1a	1150	* @arg @ref LL_DMA_PBURST_INC4
NYX	0:85b3fd62ea1a	1151	* @arg @ref LL_DMA_PBURST_INC8
NYX	0:85b3fd62ea1a	1152	* @arg @ref LL_DMA_PBURST_INC16
NYX	0:85b3fd62ea1a	1153	*/
NYX	0:85b3fd62ea1a	1154	__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1155	{
NYX	0:85b3fd62ea1a	1156	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
NYX	0:85b3fd62ea1a	1157	}
NYX	0:85b3fd62ea1a	1158
NYX	0:85b3fd62ea1a	1159	/**
NYX	0:85b3fd62ea1a	1160	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
NYX	0:85b3fd62ea1a	1161	* @rmtoll CR CT LL_DMA_SetCurrentTargetMem
NYX	0:85b3fd62ea1a	1162	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1163	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1164	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1165	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1166	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1167	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1168	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1169	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1170	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1171	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1172	* @param CurrentMemory This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1173	* @arg @ref LL_DMA_CURRENTTARGETMEM0
NYX	0:85b3fd62ea1a	1174	* @arg @ref LL_DMA_CURRENTTARGETMEM1
NYX	0:85b3fd62ea1a	1175	* @retval None
NYX	0:85b3fd62ea1a	1176	*/
NYX	0:85b3fd62ea1a	1177	__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
NYX	0:85b3fd62ea1a	1178	{
NYX	0:85b3fd62ea1a	1179	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
NYX	0:85b3fd62ea1a	1180	}
NYX	0:85b3fd62ea1a	1181
NYX	0:85b3fd62ea1a	1182	/**
NYX	0:85b3fd62ea1a	1183	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
NYX	0:85b3fd62ea1a	1184	* @rmtoll CR CT LL_DMA_GetCurrentTargetMem
NYX	0:85b3fd62ea1a	1185	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1186	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1187	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1188	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1189	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1190	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1191	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1192	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1193	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1194	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1195	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1196	* @arg @ref LL_DMA_CURRENTTARGETMEM0
NYX	0:85b3fd62ea1a	1197	* @arg @ref LL_DMA_CURRENTTARGETMEM1
NYX	0:85b3fd62ea1a	1198	*/
NYX	0:85b3fd62ea1a	1199	__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1200	{
NYX	0:85b3fd62ea1a	1201	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
NYX	0:85b3fd62ea1a	1202	}
NYX	0:85b3fd62ea1a	1203
NYX	0:85b3fd62ea1a	1204	/**
NYX	0:85b3fd62ea1a	1205	* @brief Enable the double buffer mode.
NYX	0:85b3fd62ea1a	1206	* @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
NYX	0:85b3fd62ea1a	1207	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1208	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1209	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1210	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1211	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1212	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1213	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1214	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1215	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1216	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1217	* @retval None
NYX	0:85b3fd62ea1a	1218	*/
NYX	0:85b3fd62ea1a	1219	__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1220	{
NYX	0:85b3fd62ea1a	1221	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
NYX	0:85b3fd62ea1a	1222	}
NYX	0:85b3fd62ea1a	1223
NYX	0:85b3fd62ea1a	1224	/**
NYX	0:85b3fd62ea1a	1225	* @brief Disable the double buffer mode.
NYX	0:85b3fd62ea1a	1226	* @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
NYX	0:85b3fd62ea1a	1227	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1228	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1229	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1230	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1231	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1232	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1233	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1234	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1235	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1236	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1237	* @retval None
NYX	0:85b3fd62ea1a	1238	*/
NYX	0:85b3fd62ea1a	1239	__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1240	{
NYX	0:85b3fd62ea1a	1241	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
NYX	0:85b3fd62ea1a	1242	}
NYX	0:85b3fd62ea1a	1243
NYX	0:85b3fd62ea1a	1244	/**
NYX	0:85b3fd62ea1a	1245	* @brief Get FIFO status.
NYX	0:85b3fd62ea1a	1246	* @rmtoll FCR FS LL_DMA_GetFIFOStatus
NYX	0:85b3fd62ea1a	1247	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1248	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1249	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1250	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1251	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1252	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1253	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1254	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1255	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1256	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1257	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1258	* @arg @ref LL_DMA_FIFOSTATUS_0_25
NYX	0:85b3fd62ea1a	1259	* @arg @ref LL_DMA_FIFOSTATUS_25_50
NYX	0:85b3fd62ea1a	1260	* @arg @ref LL_DMA_FIFOSTATUS_50_75
NYX	0:85b3fd62ea1a	1261	* @arg @ref LL_DMA_FIFOSTATUS_75_100
NYX	0:85b3fd62ea1a	1262	* @arg @ref LL_DMA_FIFOSTATUS_EMPTY
NYX	0:85b3fd62ea1a	1263	* @arg @ref LL_DMA_FIFOSTATUS_FULL
NYX	0:85b3fd62ea1a	1264	*/
NYX	0:85b3fd62ea1a	1265	__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1266	{
NYX	0:85b3fd62ea1a	1267	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
NYX	0:85b3fd62ea1a	1268	}
NYX	0:85b3fd62ea1a	1269
NYX	0:85b3fd62ea1a	1270	/**
NYX	0:85b3fd62ea1a	1271	* @brief Disable Fifo mode.
NYX	0:85b3fd62ea1a	1272	* @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
NYX	0:85b3fd62ea1a	1273	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1274	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1275	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1276	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1277	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1278	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1279	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1280	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1281	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1282	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1283	* @retval None
NYX	0:85b3fd62ea1a	1284	*/
NYX	0:85b3fd62ea1a	1285	__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1286	{
NYX	0:85b3fd62ea1a	1287	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
NYX	0:85b3fd62ea1a	1288	}
NYX	0:85b3fd62ea1a	1289
NYX	0:85b3fd62ea1a	1290	/**
NYX	0:85b3fd62ea1a	1291	* @brief Enable Fifo mode.
NYX	0:85b3fd62ea1a	1292	* @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
NYX	0:85b3fd62ea1a	1293	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1294	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1295	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1296	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1297	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1298	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1299	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1300	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1301	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1302	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1303	* @retval None
NYX	0:85b3fd62ea1a	1304	*/
NYX	0:85b3fd62ea1a	1305	__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1306	{
NYX	0:85b3fd62ea1a	1307	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
NYX	0:85b3fd62ea1a	1308	}
NYX	0:85b3fd62ea1a	1309
NYX	0:85b3fd62ea1a	1310	/**
NYX	0:85b3fd62ea1a	1311	* @brief Select FIFO threshold.
NYX	0:85b3fd62ea1a	1312	* @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
NYX	0:85b3fd62ea1a	1313	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1314	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1315	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1316	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1317	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1318	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1319	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1320	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1321	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1322	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1323	* @param Threshold This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1324	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
NYX	0:85b3fd62ea1a	1325	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
NYX	0:85b3fd62ea1a	1326	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
NYX	0:85b3fd62ea1a	1327	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
NYX	0:85b3fd62ea1a	1328	* @retval None
NYX	0:85b3fd62ea1a	1329	*/
NYX	0:85b3fd62ea1a	1330	__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
NYX	0:85b3fd62ea1a	1331	{
NYX	0:85b3fd62ea1a	1332	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
NYX	0:85b3fd62ea1a	1333	}
NYX	0:85b3fd62ea1a	1334
NYX	0:85b3fd62ea1a	1335	/**
NYX	0:85b3fd62ea1a	1336	* @brief Get FIFO threshold.
NYX	0:85b3fd62ea1a	1337	* @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
NYX	0:85b3fd62ea1a	1338	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1339	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1340	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1341	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1342	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1343	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1344	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1345	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1346	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1347	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1348	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	1349	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
NYX	0:85b3fd62ea1a	1350	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
NYX	0:85b3fd62ea1a	1351	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
NYX	0:85b3fd62ea1a	1352	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
NYX	0:85b3fd62ea1a	1353	*/
NYX	0:85b3fd62ea1a	1354	__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1355	{
NYX	0:85b3fd62ea1a	1356	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
NYX	0:85b3fd62ea1a	1357	}
NYX	0:85b3fd62ea1a	1358
NYX	0:85b3fd62ea1a	1359	/**
NYX	0:85b3fd62ea1a	1360	* @brief Configure the FIFO .
NYX	0:85b3fd62ea1a	1361	* @rmtoll FCR FTH LL_DMA_ConfigFifo\n
NYX	0:85b3fd62ea1a	1362	* FCR DMDIS LL_DMA_ConfigFifo
NYX	0:85b3fd62ea1a	1363	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1364	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1365	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1366	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1367	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1368	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1369	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1370	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1371	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1372	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1373	* @param FifoMode This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1374	* @arg @ref LL_DMA_FIFOMODE_ENABLE
NYX	0:85b3fd62ea1a	1375	* @arg @ref LL_DMA_FIFOMODE_DISABLE
NYX	0:85b3fd62ea1a	1376	* @param FifoThreshold This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1377	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
NYX	0:85b3fd62ea1a	1378	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
NYX	0:85b3fd62ea1a	1379	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
NYX	0:85b3fd62ea1a	1380	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
NYX	0:85b3fd62ea1a	1381	* @retval None
NYX	0:85b3fd62ea1a	1382	*/
NYX	0:85b3fd62ea1a	1383	__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
NYX	0:85b3fd62ea1a	1384	{
NYX	0:85b3fd62ea1a	1385	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH\|DMA_SxFCR_DMDIS, FifoMode\|FifoThreshold);
NYX	0:85b3fd62ea1a	1386	}
NYX	0:85b3fd62ea1a	1387
NYX	0:85b3fd62ea1a	1388	/**
NYX	0:85b3fd62ea1a	1389	* @brief Configure the Source and Destination addresses.
NYX	0:85b3fd62ea1a	1390	* @note This API must not be called when the DMA stream is enabled.
NYX	0:85b3fd62ea1a	1391	* @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
NYX	0:85b3fd62ea1a	1392	* PAR PA LL_DMA_ConfigAddresses
NYX	0:85b3fd62ea1a	1393	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1394	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1395	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1396	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1397	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1398	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1399	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1400	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1401	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1402	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1403	* @param SrcAddress Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1404	* @param DstAddress Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1405	* @param Direction This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1406	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
NYX	0:85b3fd62ea1a	1407	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
NYX	0:85b3fd62ea1a	1408	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
NYX	0:85b3fd62ea1a	1409	* @retval None
NYX	0:85b3fd62ea1a	1410	*/
NYX	0:85b3fd62ea1a	1411	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
NYX	0:85b3fd62ea1a	1412	{
NYX	0:85b3fd62ea1a	1413	/* Direction Memory to Periph */
NYX	0:85b3fd62ea1a	1414	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
NYX	0:85b3fd62ea1a	1415	{
NYX	0:85b3fd62ea1a	1416	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
NYX	0:85b3fd62ea1a	1417	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
NYX	0:85b3fd62ea1a	1418	}
NYX	0:85b3fd62ea1a	1419	/* Direction Periph to Memory and Memory to Memory */
NYX	0:85b3fd62ea1a	1420	else
NYX	0:85b3fd62ea1a	1421	{
NYX	0:85b3fd62ea1a	1422	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
NYX	0:85b3fd62ea1a	1423	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
NYX	0:85b3fd62ea1a	1424	}
NYX	0:85b3fd62ea1a	1425	}
NYX	0:85b3fd62ea1a	1426
NYX	0:85b3fd62ea1a	1427	/**
NYX	0:85b3fd62ea1a	1428	* @brief Set the Memory address.
NYX	0:85b3fd62ea1a	1429	* @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
NYX	0:85b3fd62ea1a	1430	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
NYX	0:85b3fd62ea1a	1431	* @note This API must not be called when the DMA channel is enabled.
NYX	0:85b3fd62ea1a	1432	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1433	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1434	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1435	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1436	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1437	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1438	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1439	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1440	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1441	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1442	* @param MemoryAddress Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1443	* @retval None
NYX	0:85b3fd62ea1a	1444	*/
NYX	0:85b3fd62ea1a	1445	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
NYX	0:85b3fd62ea1a	1446	{
NYX	0:85b3fd62ea1a	1447	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
NYX	0:85b3fd62ea1a	1448	}
NYX	0:85b3fd62ea1a	1449
NYX	0:85b3fd62ea1a	1450	/**
NYX	0:85b3fd62ea1a	1451	* @brief Set the Peripheral address.
NYX	0:85b3fd62ea1a	1452	* @rmtoll PAR PA LL_DMA_SetPeriphAddress
NYX	0:85b3fd62ea1a	1453	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
NYX	0:85b3fd62ea1a	1454	* @note This API must not be called when the DMA channel is enabled.
NYX	0:85b3fd62ea1a	1455	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1456	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1457	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1458	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1459	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1460	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1461	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1462	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1463	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1464	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1465	* @param PeriphAddress Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1466	* @retval None
NYX	0:85b3fd62ea1a	1467	*/
NYX	0:85b3fd62ea1a	1468	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
NYX	0:85b3fd62ea1a	1469	{
NYX	0:85b3fd62ea1a	1470	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
NYX	0:85b3fd62ea1a	1471	}
NYX	0:85b3fd62ea1a	1472
NYX	0:85b3fd62ea1a	1473	/**
NYX	0:85b3fd62ea1a	1474	* @brief Get the Memory address.
NYX	0:85b3fd62ea1a	1475	* @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
NYX	0:85b3fd62ea1a	1476	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
NYX	0:85b3fd62ea1a	1477	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1478	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1479	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1480	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1481	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1482	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1483	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1484	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1485	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1486	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1487	* @retval Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1488	*/
NYX	0:85b3fd62ea1a	1489	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1490	{
NYX	0:85b3fd62ea1a	1491	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
NYX	0:85b3fd62ea1a	1492	}
NYX	0:85b3fd62ea1a	1493
NYX	0:85b3fd62ea1a	1494	/**
NYX	0:85b3fd62ea1a	1495	* @brief Get the Peripheral address.
NYX	0:85b3fd62ea1a	1496	* @rmtoll PAR PA LL_DMA_GetPeriphAddress
NYX	0:85b3fd62ea1a	1497	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
NYX	0:85b3fd62ea1a	1498	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1499	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1500	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1501	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1502	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1503	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1504	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1505	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1506	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1507	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1508	* @retval Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1509	*/
NYX	0:85b3fd62ea1a	1510	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1511	{
NYX	0:85b3fd62ea1a	1512	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
NYX	0:85b3fd62ea1a	1513	}
NYX	0:85b3fd62ea1a	1514
NYX	0:85b3fd62ea1a	1515	/**
NYX	0:85b3fd62ea1a	1516	* @brief Set the Memory to Memory Source address.
NYX	0:85b3fd62ea1a	1517	* @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
NYX	0:85b3fd62ea1a	1518	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
NYX	0:85b3fd62ea1a	1519	* @note This API must not be called when the DMA channel is enabled.
NYX	0:85b3fd62ea1a	1520	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1521	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1522	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1523	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1524	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1525	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1526	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1527	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1528	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1529	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1530	* @param MemoryAddress Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1531	* @retval None
NYX	0:85b3fd62ea1a	1532	*/
NYX	0:85b3fd62ea1a	1533	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
NYX	0:85b3fd62ea1a	1534	{
NYX	0:85b3fd62ea1a	1535	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
NYX	0:85b3fd62ea1a	1536	}
NYX	0:85b3fd62ea1a	1537
NYX	0:85b3fd62ea1a	1538	/**
NYX	0:85b3fd62ea1a	1539	* @brief Set the Memory to Memory Destination address.
NYX	0:85b3fd62ea1a	1540	* @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
NYX	0:85b3fd62ea1a	1541	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
NYX	0:85b3fd62ea1a	1542	* @note This API must not be called when the DMA channel is enabled.
NYX	0:85b3fd62ea1a	1543	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1544	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1545	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1546	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1547	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1548	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1549	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1550	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1551	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1552	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1553	* @param MemoryAddress Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1554	* @retval None
NYX	0:85b3fd62ea1a	1555	*/
NYX	0:85b3fd62ea1a	1556	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
NYX	0:85b3fd62ea1a	1557	{
NYX	0:85b3fd62ea1a	1558	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
NYX	0:85b3fd62ea1a	1559	}
NYX	0:85b3fd62ea1a	1560
NYX	0:85b3fd62ea1a	1561	/**
NYX	0:85b3fd62ea1a	1562	* @brief Get the Memory to Memory Source address.
NYX	0:85b3fd62ea1a	1563	* @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
NYX	0:85b3fd62ea1a	1564	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
NYX	0:85b3fd62ea1a	1565	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1566	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1567	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1568	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1569	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1570	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1571	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1572	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1573	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1574	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1575	* @retval Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1576	*/
NYX	0:85b3fd62ea1a	1577	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1578	{
NYX	0:85b3fd62ea1a	1579	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
NYX	0:85b3fd62ea1a	1580	}
NYX	0:85b3fd62ea1a	1581
NYX	0:85b3fd62ea1a	1582	/**
NYX	0:85b3fd62ea1a	1583	* @brief Get the Memory to Memory Destination address.
NYX	0:85b3fd62ea1a	1584	* @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
NYX	0:85b3fd62ea1a	1585	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
NYX	0:85b3fd62ea1a	1586	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1587	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1588	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1589	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1590	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1591	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1592	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1593	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1594	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1595	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1596	* @retval Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1597	*/
NYX	0:85b3fd62ea1a	1598	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1599	{
NYX	0:85b3fd62ea1a	1600	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
NYX	0:85b3fd62ea1a	1601	}
NYX	0:85b3fd62ea1a	1602
NYX	0:85b3fd62ea1a	1603	/**
NYX	0:85b3fd62ea1a	1604	* @brief Set Memory 1 address (used in case of Double buffer mode).
NYX	0:85b3fd62ea1a	1605	* @rmtoll M1AR M1A LL_DMA_SetMemory1Address
NYX	0:85b3fd62ea1a	1606	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1607	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1608	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1609	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1610	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1611	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1612	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1613	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1614	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1615	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1616	* @param Address Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1617	* @retval None
NYX	0:85b3fd62ea1a	1618	*/
NYX	0:85b3fd62ea1a	1619	__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
NYX	0:85b3fd62ea1a	1620	{
NYX	0:85b3fd62ea1a	1621	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
NYX	0:85b3fd62ea1a	1622	}
NYX	0:85b3fd62ea1a	1623
NYX	0:85b3fd62ea1a	1624	/**
NYX	0:85b3fd62ea1a	1625	* @brief Get Memory 1 address (used in case of Double buffer mode).
NYX	0:85b3fd62ea1a	1626	* @rmtoll M1AR M1A LL_DMA_GetMemory1Address
NYX	0:85b3fd62ea1a	1627	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1628	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1629	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	1630	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	1631	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	1632	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	1633	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	1634	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	1635	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	1636	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	1637	* @retval Between 0 to 0xFFFFFFFF
NYX	0:85b3fd62ea1a	1638	*/
NYX	0:85b3fd62ea1a	1639	__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	1640	{
NYX	0:85b3fd62ea1a	1641	return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
NYX	0:85b3fd62ea1a	1642	}
NYX	0:85b3fd62ea1a	1643
NYX	0:85b3fd62ea1a	1644	/**
NYX	0:85b3fd62ea1a	1645	* @}
NYX	0:85b3fd62ea1a	1646	*/
NYX	0:85b3fd62ea1a	1647
NYX	0:85b3fd62ea1a	1648	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
NYX	0:85b3fd62ea1a	1649	* @{
NYX	0:85b3fd62ea1a	1650	*/
NYX	0:85b3fd62ea1a	1651
NYX	0:85b3fd62ea1a	1652	/**
NYX	0:85b3fd62ea1a	1653	* @brief Get Stream 0 half transfer flag.
NYX	0:85b3fd62ea1a	1654	* @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
NYX	0:85b3fd62ea1a	1655	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1656	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1657	*/
NYX	0:85b3fd62ea1a	1658	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1659	{
NYX	0:85b3fd62ea1a	1660	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
NYX	0:85b3fd62ea1a	1661	}
NYX	0:85b3fd62ea1a	1662
NYX	0:85b3fd62ea1a	1663	/**
NYX	0:85b3fd62ea1a	1664	* @brief Get Stream 1 half transfer flag.
NYX	0:85b3fd62ea1a	1665	* @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
NYX	0:85b3fd62ea1a	1666	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1667	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1668	*/
NYX	0:85b3fd62ea1a	1669	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1670	{
NYX	0:85b3fd62ea1a	1671	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
NYX	0:85b3fd62ea1a	1672	}
NYX	0:85b3fd62ea1a	1673
NYX	0:85b3fd62ea1a	1674	/**
NYX	0:85b3fd62ea1a	1675	* @brief Get Stream 2 half transfer flag.
NYX	0:85b3fd62ea1a	1676	* @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
NYX	0:85b3fd62ea1a	1677	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1678	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1679	*/
NYX	0:85b3fd62ea1a	1680	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1681	{
NYX	0:85b3fd62ea1a	1682	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
NYX	0:85b3fd62ea1a	1683	}
NYX	0:85b3fd62ea1a	1684
NYX	0:85b3fd62ea1a	1685	/**
NYX	0:85b3fd62ea1a	1686	* @brief Get Stream 3 half transfer flag.
NYX	0:85b3fd62ea1a	1687	* @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
NYX	0:85b3fd62ea1a	1688	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1689	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1690	*/
NYX	0:85b3fd62ea1a	1691	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1692	{
NYX	0:85b3fd62ea1a	1693	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
NYX	0:85b3fd62ea1a	1694	}
NYX	0:85b3fd62ea1a	1695
NYX	0:85b3fd62ea1a	1696	/**
NYX	0:85b3fd62ea1a	1697	* @brief Get Stream 4 half transfer flag.
NYX	0:85b3fd62ea1a	1698	* @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
NYX	0:85b3fd62ea1a	1699	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1700	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1701	*/
NYX	0:85b3fd62ea1a	1702	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1703	{
NYX	0:85b3fd62ea1a	1704	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
NYX	0:85b3fd62ea1a	1705	}
NYX	0:85b3fd62ea1a	1706
NYX	0:85b3fd62ea1a	1707	/**
NYX	0:85b3fd62ea1a	1708	* @brief Get Stream 5 half transfer flag.
NYX	0:85b3fd62ea1a	1709	* @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
NYX	0:85b3fd62ea1a	1710	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1711	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1712	*/
NYX	0:85b3fd62ea1a	1713	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1714	{
NYX	0:85b3fd62ea1a	1715	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
NYX	0:85b3fd62ea1a	1716	}
NYX	0:85b3fd62ea1a	1717
NYX	0:85b3fd62ea1a	1718	/**
NYX	0:85b3fd62ea1a	1719	* @brief Get Stream 6 half transfer flag.
NYX	0:85b3fd62ea1a	1720	* @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
NYX	0:85b3fd62ea1a	1721	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1722	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1723	*/
NYX	0:85b3fd62ea1a	1724	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1725	{
NYX	0:85b3fd62ea1a	1726	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
NYX	0:85b3fd62ea1a	1727	}
NYX	0:85b3fd62ea1a	1728
NYX	0:85b3fd62ea1a	1729	/**
NYX	0:85b3fd62ea1a	1730	* @brief Get Stream 7 half transfer flag.
NYX	0:85b3fd62ea1a	1731	* @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
NYX	0:85b3fd62ea1a	1732	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1733	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1734	*/
NYX	0:85b3fd62ea1a	1735	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1736	{
NYX	0:85b3fd62ea1a	1737	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
NYX	0:85b3fd62ea1a	1738	}
NYX	0:85b3fd62ea1a	1739
NYX	0:85b3fd62ea1a	1740	/**
NYX	0:85b3fd62ea1a	1741	* @brief Get Stream 0 transfer complete flag.
NYX	0:85b3fd62ea1a	1742	* @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
NYX	0:85b3fd62ea1a	1743	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1744	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1745	*/
NYX	0:85b3fd62ea1a	1746	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1747	{
NYX	0:85b3fd62ea1a	1748	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
NYX	0:85b3fd62ea1a	1749	}
NYX	0:85b3fd62ea1a	1750
NYX	0:85b3fd62ea1a	1751	/**
NYX	0:85b3fd62ea1a	1752	* @brief Get Stream 1 transfer complete flag.
NYX	0:85b3fd62ea1a	1753	* @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
NYX	0:85b3fd62ea1a	1754	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1755	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1756	*/
NYX	0:85b3fd62ea1a	1757	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1758	{
NYX	0:85b3fd62ea1a	1759	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
NYX	0:85b3fd62ea1a	1760	}
NYX	0:85b3fd62ea1a	1761
NYX	0:85b3fd62ea1a	1762	/**
NYX	0:85b3fd62ea1a	1763	* @brief Get Stream 2 transfer complete flag.
NYX	0:85b3fd62ea1a	1764	* @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
NYX	0:85b3fd62ea1a	1765	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1766	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1767	*/
NYX	0:85b3fd62ea1a	1768	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1769	{
NYX	0:85b3fd62ea1a	1770	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
NYX	0:85b3fd62ea1a	1771	}
NYX	0:85b3fd62ea1a	1772
NYX	0:85b3fd62ea1a	1773	/**
NYX	0:85b3fd62ea1a	1774	* @brief Get Stream 3 transfer complete flag.
NYX	0:85b3fd62ea1a	1775	* @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
NYX	0:85b3fd62ea1a	1776	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1777	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1778	*/
NYX	0:85b3fd62ea1a	1779	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1780	{
NYX	0:85b3fd62ea1a	1781	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
NYX	0:85b3fd62ea1a	1782	}
NYX	0:85b3fd62ea1a	1783
NYX	0:85b3fd62ea1a	1784	/**
NYX	0:85b3fd62ea1a	1785	* @brief Get Stream 4 transfer complete flag.
NYX	0:85b3fd62ea1a	1786	* @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
NYX	0:85b3fd62ea1a	1787	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1788	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1789	*/
NYX	0:85b3fd62ea1a	1790	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1791	{
NYX	0:85b3fd62ea1a	1792	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
NYX	0:85b3fd62ea1a	1793	}
NYX	0:85b3fd62ea1a	1794
NYX	0:85b3fd62ea1a	1795	/**
NYX	0:85b3fd62ea1a	1796	* @brief Get Stream 5 transfer complete flag.
NYX	0:85b3fd62ea1a	1797	* @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
NYX	0:85b3fd62ea1a	1798	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1799	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1800	*/
NYX	0:85b3fd62ea1a	1801	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1802	{
NYX	0:85b3fd62ea1a	1803	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
NYX	0:85b3fd62ea1a	1804	}
NYX	0:85b3fd62ea1a	1805
NYX	0:85b3fd62ea1a	1806	/**
NYX	0:85b3fd62ea1a	1807	* @brief Get Stream 6 transfer complete flag.
NYX	0:85b3fd62ea1a	1808	* @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
NYX	0:85b3fd62ea1a	1809	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1810	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1811	*/
NYX	0:85b3fd62ea1a	1812	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1813	{
NYX	0:85b3fd62ea1a	1814	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
NYX	0:85b3fd62ea1a	1815	}
NYX	0:85b3fd62ea1a	1816
NYX	0:85b3fd62ea1a	1817	/**
NYX	0:85b3fd62ea1a	1818	* @brief Get Stream 7 transfer complete flag.
NYX	0:85b3fd62ea1a	1819	* @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
NYX	0:85b3fd62ea1a	1820	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1821	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1822	*/
NYX	0:85b3fd62ea1a	1823	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1824	{
NYX	0:85b3fd62ea1a	1825	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
NYX	0:85b3fd62ea1a	1826	}
NYX	0:85b3fd62ea1a	1827
NYX	0:85b3fd62ea1a	1828	/**
NYX	0:85b3fd62ea1a	1829	* @brief Get Stream 0 transfer error flag.
NYX	0:85b3fd62ea1a	1830	* @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
NYX	0:85b3fd62ea1a	1831	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1832	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1833	*/
NYX	0:85b3fd62ea1a	1834	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1835	{
NYX	0:85b3fd62ea1a	1836	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
NYX	0:85b3fd62ea1a	1837	}
NYX	0:85b3fd62ea1a	1838
NYX	0:85b3fd62ea1a	1839	/**
NYX	0:85b3fd62ea1a	1840	* @brief Get Stream 1 transfer error flag.
NYX	0:85b3fd62ea1a	1841	* @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
NYX	0:85b3fd62ea1a	1842	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1843	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1844	*/
NYX	0:85b3fd62ea1a	1845	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1846	{
NYX	0:85b3fd62ea1a	1847	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
NYX	0:85b3fd62ea1a	1848	}
NYX	0:85b3fd62ea1a	1849
NYX	0:85b3fd62ea1a	1850	/**
NYX	0:85b3fd62ea1a	1851	* @brief Get Stream 2 transfer error flag.
NYX	0:85b3fd62ea1a	1852	* @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
NYX	0:85b3fd62ea1a	1853	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1854	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1855	*/
NYX	0:85b3fd62ea1a	1856	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1857	{
NYX	0:85b3fd62ea1a	1858	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
NYX	0:85b3fd62ea1a	1859	}
NYX	0:85b3fd62ea1a	1860
NYX	0:85b3fd62ea1a	1861	/**
NYX	0:85b3fd62ea1a	1862	* @brief Get Stream 3 transfer error flag.
NYX	0:85b3fd62ea1a	1863	* @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
NYX	0:85b3fd62ea1a	1864	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1865	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1866	*/
NYX	0:85b3fd62ea1a	1867	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1868	{
NYX	0:85b3fd62ea1a	1869	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
NYX	0:85b3fd62ea1a	1870	}
NYX	0:85b3fd62ea1a	1871
NYX	0:85b3fd62ea1a	1872	/**
NYX	0:85b3fd62ea1a	1873	* @brief Get Stream 4 transfer error flag.
NYX	0:85b3fd62ea1a	1874	* @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
NYX	0:85b3fd62ea1a	1875	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1876	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1877	*/
NYX	0:85b3fd62ea1a	1878	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1879	{
NYX	0:85b3fd62ea1a	1880	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
NYX	0:85b3fd62ea1a	1881	}
NYX	0:85b3fd62ea1a	1882
NYX	0:85b3fd62ea1a	1883	/**
NYX	0:85b3fd62ea1a	1884	* @brief Get Stream 5 transfer error flag.
NYX	0:85b3fd62ea1a	1885	* @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
NYX	0:85b3fd62ea1a	1886	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1887	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1888	*/
NYX	0:85b3fd62ea1a	1889	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1890	{
NYX	0:85b3fd62ea1a	1891	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
NYX	0:85b3fd62ea1a	1892	}
NYX	0:85b3fd62ea1a	1893
NYX	0:85b3fd62ea1a	1894	/**
NYX	0:85b3fd62ea1a	1895	* @brief Get Stream 6 transfer error flag.
NYX	0:85b3fd62ea1a	1896	* @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
NYX	0:85b3fd62ea1a	1897	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1898	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1899	*/
NYX	0:85b3fd62ea1a	1900	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1901	{
NYX	0:85b3fd62ea1a	1902	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
NYX	0:85b3fd62ea1a	1903	}
NYX	0:85b3fd62ea1a	1904
NYX	0:85b3fd62ea1a	1905	/**
NYX	0:85b3fd62ea1a	1906	* @brief Get Stream 7 transfer error flag.
NYX	0:85b3fd62ea1a	1907	* @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
NYX	0:85b3fd62ea1a	1908	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1909	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1910	*/
NYX	0:85b3fd62ea1a	1911	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1912	{
NYX	0:85b3fd62ea1a	1913	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
NYX	0:85b3fd62ea1a	1914	}
NYX	0:85b3fd62ea1a	1915
NYX	0:85b3fd62ea1a	1916	/**
NYX	0:85b3fd62ea1a	1917	* @brief Get Stream 0 direct mode error flag.
NYX	0:85b3fd62ea1a	1918	* @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
NYX	0:85b3fd62ea1a	1919	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1920	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1921	*/
NYX	0:85b3fd62ea1a	1922	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1923	{
NYX	0:85b3fd62ea1a	1924	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
NYX	0:85b3fd62ea1a	1925	}
NYX	0:85b3fd62ea1a	1926
NYX	0:85b3fd62ea1a	1927	/**
NYX	0:85b3fd62ea1a	1928	* @brief Get Stream 1 direct mode error flag.
NYX	0:85b3fd62ea1a	1929	* @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
NYX	0:85b3fd62ea1a	1930	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1931	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1932	*/
NYX	0:85b3fd62ea1a	1933	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1934	{
NYX	0:85b3fd62ea1a	1935	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
NYX	0:85b3fd62ea1a	1936	}
NYX	0:85b3fd62ea1a	1937
NYX	0:85b3fd62ea1a	1938	/**
NYX	0:85b3fd62ea1a	1939	* @brief Get Stream 2 direct mode error flag.
NYX	0:85b3fd62ea1a	1940	* @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
NYX	0:85b3fd62ea1a	1941	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1942	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1943	*/
NYX	0:85b3fd62ea1a	1944	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1945	{
NYX	0:85b3fd62ea1a	1946	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
NYX	0:85b3fd62ea1a	1947	}
NYX	0:85b3fd62ea1a	1948
NYX	0:85b3fd62ea1a	1949	/**
NYX	0:85b3fd62ea1a	1950	* @brief Get Stream 3 direct mode error flag.
NYX	0:85b3fd62ea1a	1951	* @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
NYX	0:85b3fd62ea1a	1952	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1953	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1954	*/
NYX	0:85b3fd62ea1a	1955	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1956	{
NYX	0:85b3fd62ea1a	1957	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
NYX	0:85b3fd62ea1a	1958	}
NYX	0:85b3fd62ea1a	1959
NYX	0:85b3fd62ea1a	1960	/**
NYX	0:85b3fd62ea1a	1961	* @brief Get Stream 4 direct mode error flag.
NYX	0:85b3fd62ea1a	1962	* @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
NYX	0:85b3fd62ea1a	1963	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1964	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1965	*/
NYX	0:85b3fd62ea1a	1966	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1967	{
NYX	0:85b3fd62ea1a	1968	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
NYX	0:85b3fd62ea1a	1969	}
NYX	0:85b3fd62ea1a	1970
NYX	0:85b3fd62ea1a	1971	/**
NYX	0:85b3fd62ea1a	1972	* @brief Get Stream 5 direct mode error flag.
NYX	0:85b3fd62ea1a	1973	* @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
NYX	0:85b3fd62ea1a	1974	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1975	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1976	*/
NYX	0:85b3fd62ea1a	1977	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1978	{
NYX	0:85b3fd62ea1a	1979	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
NYX	0:85b3fd62ea1a	1980	}
NYX	0:85b3fd62ea1a	1981
NYX	0:85b3fd62ea1a	1982	/**
NYX	0:85b3fd62ea1a	1983	* @brief Get Stream 6 direct mode error flag.
NYX	0:85b3fd62ea1a	1984	* @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
NYX	0:85b3fd62ea1a	1985	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1986	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1987	*/
NYX	0:85b3fd62ea1a	1988	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	1989	{
NYX	0:85b3fd62ea1a	1990	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
NYX	0:85b3fd62ea1a	1991	}
NYX	0:85b3fd62ea1a	1992
NYX	0:85b3fd62ea1a	1993	/**
NYX	0:85b3fd62ea1a	1994	* @brief Get Stream 7 direct mode error flag.
NYX	0:85b3fd62ea1a	1995	* @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
NYX	0:85b3fd62ea1a	1996	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	1997	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1998	*/
NYX	0:85b3fd62ea1a	1999	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2000	{
NYX	0:85b3fd62ea1a	2001	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
NYX	0:85b3fd62ea1a	2002	}
NYX	0:85b3fd62ea1a	2003
NYX	0:85b3fd62ea1a	2004	/**
NYX	0:85b3fd62ea1a	2005	* @brief Get Stream 0 FIFO error flag.
NYX	0:85b3fd62ea1a	2006	* @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
NYX	0:85b3fd62ea1a	2007	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2008	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2009	*/
NYX	0:85b3fd62ea1a	2010	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2011	{
NYX	0:85b3fd62ea1a	2012	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
NYX	0:85b3fd62ea1a	2013	}
NYX	0:85b3fd62ea1a	2014
NYX	0:85b3fd62ea1a	2015	/**
NYX	0:85b3fd62ea1a	2016	* @brief Get Stream 1 FIFO error flag.
NYX	0:85b3fd62ea1a	2017	* @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
NYX	0:85b3fd62ea1a	2018	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2019	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2020	*/
NYX	0:85b3fd62ea1a	2021	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2022	{
NYX	0:85b3fd62ea1a	2023	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
NYX	0:85b3fd62ea1a	2024	}
NYX	0:85b3fd62ea1a	2025
NYX	0:85b3fd62ea1a	2026	/**
NYX	0:85b3fd62ea1a	2027	* @brief Get Stream 2 FIFO error flag.
NYX	0:85b3fd62ea1a	2028	* @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
NYX	0:85b3fd62ea1a	2029	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2030	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2031	*/
NYX	0:85b3fd62ea1a	2032	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2033	{
NYX	0:85b3fd62ea1a	2034	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
NYX	0:85b3fd62ea1a	2035	}
NYX	0:85b3fd62ea1a	2036
NYX	0:85b3fd62ea1a	2037	/**
NYX	0:85b3fd62ea1a	2038	* @brief Get Stream 3 FIFO error flag.
NYX	0:85b3fd62ea1a	2039	* @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
NYX	0:85b3fd62ea1a	2040	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2041	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2042	*/
NYX	0:85b3fd62ea1a	2043	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2044	{
NYX	0:85b3fd62ea1a	2045	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
NYX	0:85b3fd62ea1a	2046	}
NYX	0:85b3fd62ea1a	2047
NYX	0:85b3fd62ea1a	2048	/**
NYX	0:85b3fd62ea1a	2049	* @brief Get Stream 4 FIFO error flag.
NYX	0:85b3fd62ea1a	2050	* @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
NYX	0:85b3fd62ea1a	2051	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2052	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2053	*/
NYX	0:85b3fd62ea1a	2054	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2055	{
NYX	0:85b3fd62ea1a	2056	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
NYX	0:85b3fd62ea1a	2057	}
NYX	0:85b3fd62ea1a	2058
NYX	0:85b3fd62ea1a	2059	/**
NYX	0:85b3fd62ea1a	2060	* @brief Get Stream 5 FIFO error flag.
NYX	0:85b3fd62ea1a	2061	* @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
NYX	0:85b3fd62ea1a	2062	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2063	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2064	*/
NYX	0:85b3fd62ea1a	2065	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2066	{
NYX	0:85b3fd62ea1a	2067	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
NYX	0:85b3fd62ea1a	2068	}
NYX	0:85b3fd62ea1a	2069
NYX	0:85b3fd62ea1a	2070	/**
NYX	0:85b3fd62ea1a	2071	* @brief Get Stream 6 FIFO error flag.
NYX	0:85b3fd62ea1a	2072	* @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
NYX	0:85b3fd62ea1a	2073	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2074	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2075	*/
NYX	0:85b3fd62ea1a	2076	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2077	{
NYX	0:85b3fd62ea1a	2078	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
NYX	0:85b3fd62ea1a	2079	}
NYX	0:85b3fd62ea1a	2080
NYX	0:85b3fd62ea1a	2081	/**
NYX	0:85b3fd62ea1a	2082	* @brief Get Stream 7 FIFO error flag.
NYX	0:85b3fd62ea1a	2083	* @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
NYX	0:85b3fd62ea1a	2084	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2085	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2086	*/
NYX	0:85b3fd62ea1a	2087	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2088	{
NYX	0:85b3fd62ea1a	2089	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
NYX	0:85b3fd62ea1a	2090	}
NYX	0:85b3fd62ea1a	2091
NYX	0:85b3fd62ea1a	2092	/**
NYX	0:85b3fd62ea1a	2093	* @brief Clear Stream 0 half transfer flag.
NYX	0:85b3fd62ea1a	2094	* @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
NYX	0:85b3fd62ea1a	2095	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2096	* @retval None
NYX	0:85b3fd62ea1a	2097	*/
NYX	0:85b3fd62ea1a	2098	__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2099	{
NYX	0:85b3fd62ea1a	2100	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
NYX	0:85b3fd62ea1a	2101	}
NYX	0:85b3fd62ea1a	2102
NYX	0:85b3fd62ea1a	2103	/**
NYX	0:85b3fd62ea1a	2104	* @brief Clear Stream 1 half transfer flag.
NYX	0:85b3fd62ea1a	2105	* @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
NYX	0:85b3fd62ea1a	2106	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2107	* @retval None
NYX	0:85b3fd62ea1a	2108	*/
NYX	0:85b3fd62ea1a	2109	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2110	{
NYX	0:85b3fd62ea1a	2111	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
NYX	0:85b3fd62ea1a	2112	}
NYX	0:85b3fd62ea1a	2113
NYX	0:85b3fd62ea1a	2114	/**
NYX	0:85b3fd62ea1a	2115	* @brief Clear Stream 2 half transfer flag.
NYX	0:85b3fd62ea1a	2116	* @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
NYX	0:85b3fd62ea1a	2117	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2118	* @retval None
NYX	0:85b3fd62ea1a	2119	*/
NYX	0:85b3fd62ea1a	2120	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2121	{
NYX	0:85b3fd62ea1a	2122	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
NYX	0:85b3fd62ea1a	2123	}
NYX	0:85b3fd62ea1a	2124
NYX	0:85b3fd62ea1a	2125	/**
NYX	0:85b3fd62ea1a	2126	* @brief Clear Stream 3 half transfer flag.
NYX	0:85b3fd62ea1a	2127	* @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
NYX	0:85b3fd62ea1a	2128	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2129	* @retval None
NYX	0:85b3fd62ea1a	2130	*/
NYX	0:85b3fd62ea1a	2131	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2132	{
NYX	0:85b3fd62ea1a	2133	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
NYX	0:85b3fd62ea1a	2134	}
NYX	0:85b3fd62ea1a	2135
NYX	0:85b3fd62ea1a	2136	/**
NYX	0:85b3fd62ea1a	2137	* @brief Clear Stream 4 half transfer flag.
NYX	0:85b3fd62ea1a	2138	* @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
NYX	0:85b3fd62ea1a	2139	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2140	* @retval None
NYX	0:85b3fd62ea1a	2141	*/
NYX	0:85b3fd62ea1a	2142	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2143	{
NYX	0:85b3fd62ea1a	2144	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
NYX	0:85b3fd62ea1a	2145	}
NYX	0:85b3fd62ea1a	2146
NYX	0:85b3fd62ea1a	2147	/**
NYX	0:85b3fd62ea1a	2148	* @brief Clear Stream 5 half transfer flag.
NYX	0:85b3fd62ea1a	2149	* @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
NYX	0:85b3fd62ea1a	2150	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2151	* @retval None
NYX	0:85b3fd62ea1a	2152	*/
NYX	0:85b3fd62ea1a	2153	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2154	{
NYX	0:85b3fd62ea1a	2155	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
NYX	0:85b3fd62ea1a	2156	}
NYX	0:85b3fd62ea1a	2157
NYX	0:85b3fd62ea1a	2158	/**
NYX	0:85b3fd62ea1a	2159	* @brief Clear Stream 6 half transfer flag.
NYX	0:85b3fd62ea1a	2160	* @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
NYX	0:85b3fd62ea1a	2161	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2162	* @retval None
NYX	0:85b3fd62ea1a	2163	*/
NYX	0:85b3fd62ea1a	2164	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2165	{
NYX	0:85b3fd62ea1a	2166	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
NYX	0:85b3fd62ea1a	2167	}
NYX	0:85b3fd62ea1a	2168
NYX	0:85b3fd62ea1a	2169	/**
NYX	0:85b3fd62ea1a	2170	* @brief Clear Stream 7 half transfer flag.
NYX	0:85b3fd62ea1a	2171	* @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
NYX	0:85b3fd62ea1a	2172	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2173	* @retval None
NYX	0:85b3fd62ea1a	2174	*/
NYX	0:85b3fd62ea1a	2175	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2176	{
NYX	0:85b3fd62ea1a	2177	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
NYX	0:85b3fd62ea1a	2178	}
NYX	0:85b3fd62ea1a	2179
NYX	0:85b3fd62ea1a	2180	/**
NYX	0:85b3fd62ea1a	2181	* @brief Clear Stream 0 transfer complete flag.
NYX	0:85b3fd62ea1a	2182	* @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
NYX	0:85b3fd62ea1a	2183	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2184	* @retval None
NYX	0:85b3fd62ea1a	2185	*/
NYX	0:85b3fd62ea1a	2186	__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2187	{
NYX	0:85b3fd62ea1a	2188	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
NYX	0:85b3fd62ea1a	2189	}
NYX	0:85b3fd62ea1a	2190
NYX	0:85b3fd62ea1a	2191	/**
NYX	0:85b3fd62ea1a	2192	* @brief Clear Stream 1 transfer complete flag.
NYX	0:85b3fd62ea1a	2193	* @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
NYX	0:85b3fd62ea1a	2194	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2195	* @retval None
NYX	0:85b3fd62ea1a	2196	*/
NYX	0:85b3fd62ea1a	2197	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2198	{
NYX	0:85b3fd62ea1a	2199	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
NYX	0:85b3fd62ea1a	2200	}
NYX	0:85b3fd62ea1a	2201
NYX	0:85b3fd62ea1a	2202	/**
NYX	0:85b3fd62ea1a	2203	* @brief Clear Stream 2 transfer complete flag.
NYX	0:85b3fd62ea1a	2204	* @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
NYX	0:85b3fd62ea1a	2205	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2206	* @retval None
NYX	0:85b3fd62ea1a	2207	*/
NYX	0:85b3fd62ea1a	2208	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2209	{
NYX	0:85b3fd62ea1a	2210	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
NYX	0:85b3fd62ea1a	2211	}
NYX	0:85b3fd62ea1a	2212
NYX	0:85b3fd62ea1a	2213	/**
NYX	0:85b3fd62ea1a	2214	* @brief Clear Stream 3 transfer complete flag.
NYX	0:85b3fd62ea1a	2215	* @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
NYX	0:85b3fd62ea1a	2216	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2217	* @retval None
NYX	0:85b3fd62ea1a	2218	*/
NYX	0:85b3fd62ea1a	2219	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2220	{
NYX	0:85b3fd62ea1a	2221	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
NYX	0:85b3fd62ea1a	2222	}
NYX	0:85b3fd62ea1a	2223
NYX	0:85b3fd62ea1a	2224	/**
NYX	0:85b3fd62ea1a	2225	* @brief Clear Stream 4 transfer complete flag.
NYX	0:85b3fd62ea1a	2226	* @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
NYX	0:85b3fd62ea1a	2227	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2228	* @retval None
NYX	0:85b3fd62ea1a	2229	*/
NYX	0:85b3fd62ea1a	2230	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2231	{
NYX	0:85b3fd62ea1a	2232	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
NYX	0:85b3fd62ea1a	2233	}
NYX	0:85b3fd62ea1a	2234
NYX	0:85b3fd62ea1a	2235	/**
NYX	0:85b3fd62ea1a	2236	* @brief Clear Stream 5 transfer complete flag.
NYX	0:85b3fd62ea1a	2237	* @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
NYX	0:85b3fd62ea1a	2238	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2239	* @retval None
NYX	0:85b3fd62ea1a	2240	*/
NYX	0:85b3fd62ea1a	2241	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2242	{
NYX	0:85b3fd62ea1a	2243	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
NYX	0:85b3fd62ea1a	2244	}
NYX	0:85b3fd62ea1a	2245
NYX	0:85b3fd62ea1a	2246	/**
NYX	0:85b3fd62ea1a	2247	* @brief Clear Stream 6 transfer complete flag.
NYX	0:85b3fd62ea1a	2248	* @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
NYX	0:85b3fd62ea1a	2249	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2250	* @retval None
NYX	0:85b3fd62ea1a	2251	*/
NYX	0:85b3fd62ea1a	2252	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2253	{
NYX	0:85b3fd62ea1a	2254	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
NYX	0:85b3fd62ea1a	2255	}
NYX	0:85b3fd62ea1a	2256
NYX	0:85b3fd62ea1a	2257	/**
NYX	0:85b3fd62ea1a	2258	* @brief Clear Stream 7 transfer complete flag.
NYX	0:85b3fd62ea1a	2259	* @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
NYX	0:85b3fd62ea1a	2260	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2261	* @retval None
NYX	0:85b3fd62ea1a	2262	*/
NYX	0:85b3fd62ea1a	2263	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2264	{
NYX	0:85b3fd62ea1a	2265	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
NYX	0:85b3fd62ea1a	2266	}
NYX	0:85b3fd62ea1a	2267
NYX	0:85b3fd62ea1a	2268	/**
NYX	0:85b3fd62ea1a	2269	* @brief Clear Stream 0 transfer error flag.
NYX	0:85b3fd62ea1a	2270	* @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
NYX	0:85b3fd62ea1a	2271	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2272	* @retval None
NYX	0:85b3fd62ea1a	2273	*/
NYX	0:85b3fd62ea1a	2274	__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2275	{
NYX	0:85b3fd62ea1a	2276	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
NYX	0:85b3fd62ea1a	2277	}
NYX	0:85b3fd62ea1a	2278
NYX	0:85b3fd62ea1a	2279	/**
NYX	0:85b3fd62ea1a	2280	* @brief Clear Stream 1 transfer error flag.
NYX	0:85b3fd62ea1a	2281	* @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
NYX	0:85b3fd62ea1a	2282	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2283	* @retval None
NYX	0:85b3fd62ea1a	2284	*/
NYX	0:85b3fd62ea1a	2285	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2286	{
NYX	0:85b3fd62ea1a	2287	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
NYX	0:85b3fd62ea1a	2288	}
NYX	0:85b3fd62ea1a	2289
NYX	0:85b3fd62ea1a	2290	/**
NYX	0:85b3fd62ea1a	2291	* @brief Clear Stream 2 transfer error flag.
NYX	0:85b3fd62ea1a	2292	* @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
NYX	0:85b3fd62ea1a	2293	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2294	* @retval None
NYX	0:85b3fd62ea1a	2295	*/
NYX	0:85b3fd62ea1a	2296	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2297	{
NYX	0:85b3fd62ea1a	2298	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
NYX	0:85b3fd62ea1a	2299	}
NYX	0:85b3fd62ea1a	2300
NYX	0:85b3fd62ea1a	2301	/**
NYX	0:85b3fd62ea1a	2302	* @brief Clear Stream 3 transfer error flag.
NYX	0:85b3fd62ea1a	2303	* @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
NYX	0:85b3fd62ea1a	2304	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2305	* @retval None
NYX	0:85b3fd62ea1a	2306	*/
NYX	0:85b3fd62ea1a	2307	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2308	{
NYX	0:85b3fd62ea1a	2309	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
NYX	0:85b3fd62ea1a	2310	}
NYX	0:85b3fd62ea1a	2311
NYX	0:85b3fd62ea1a	2312	/**
NYX	0:85b3fd62ea1a	2313	* @brief Clear Stream 4 transfer error flag.
NYX	0:85b3fd62ea1a	2314	* @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
NYX	0:85b3fd62ea1a	2315	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2316	* @retval None
NYX	0:85b3fd62ea1a	2317	*/
NYX	0:85b3fd62ea1a	2318	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2319	{
NYX	0:85b3fd62ea1a	2320	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
NYX	0:85b3fd62ea1a	2321	}
NYX	0:85b3fd62ea1a	2322
NYX	0:85b3fd62ea1a	2323	/**
NYX	0:85b3fd62ea1a	2324	* @brief Clear Stream 5 transfer error flag.
NYX	0:85b3fd62ea1a	2325	* @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
NYX	0:85b3fd62ea1a	2326	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2327	* @retval None
NYX	0:85b3fd62ea1a	2328	*/
NYX	0:85b3fd62ea1a	2329	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2330	{
NYX	0:85b3fd62ea1a	2331	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
NYX	0:85b3fd62ea1a	2332	}
NYX	0:85b3fd62ea1a	2333
NYX	0:85b3fd62ea1a	2334	/**
NYX	0:85b3fd62ea1a	2335	* @brief Clear Stream 6 transfer error flag.
NYX	0:85b3fd62ea1a	2336	* @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
NYX	0:85b3fd62ea1a	2337	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2338	* @retval None
NYX	0:85b3fd62ea1a	2339	*/
NYX	0:85b3fd62ea1a	2340	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2341	{
NYX	0:85b3fd62ea1a	2342	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
NYX	0:85b3fd62ea1a	2343	}
NYX	0:85b3fd62ea1a	2344
NYX	0:85b3fd62ea1a	2345	/**
NYX	0:85b3fd62ea1a	2346	* @brief Clear Stream 7 transfer error flag.
NYX	0:85b3fd62ea1a	2347	* @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
NYX	0:85b3fd62ea1a	2348	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2349	* @retval None
NYX	0:85b3fd62ea1a	2350	*/
NYX	0:85b3fd62ea1a	2351	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2352	{
NYX	0:85b3fd62ea1a	2353	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
NYX	0:85b3fd62ea1a	2354	}
NYX	0:85b3fd62ea1a	2355
NYX	0:85b3fd62ea1a	2356	/**
NYX	0:85b3fd62ea1a	2357	* @brief Clear Stream 0 direct mode error flag.
NYX	0:85b3fd62ea1a	2358	* @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
NYX	0:85b3fd62ea1a	2359	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2360	* @retval None
NYX	0:85b3fd62ea1a	2361	*/
NYX	0:85b3fd62ea1a	2362	__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2363	{
NYX	0:85b3fd62ea1a	2364	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
NYX	0:85b3fd62ea1a	2365	}
NYX	0:85b3fd62ea1a	2366
NYX	0:85b3fd62ea1a	2367	/**
NYX	0:85b3fd62ea1a	2368	* @brief Clear Stream 1 direct mode error flag.
NYX	0:85b3fd62ea1a	2369	* @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
NYX	0:85b3fd62ea1a	2370	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2371	* @retval None
NYX	0:85b3fd62ea1a	2372	*/
NYX	0:85b3fd62ea1a	2373	__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2374	{
NYX	0:85b3fd62ea1a	2375	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
NYX	0:85b3fd62ea1a	2376	}
NYX	0:85b3fd62ea1a	2377
NYX	0:85b3fd62ea1a	2378	/**
NYX	0:85b3fd62ea1a	2379	* @brief Clear Stream 2 direct mode error flag.
NYX	0:85b3fd62ea1a	2380	* @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
NYX	0:85b3fd62ea1a	2381	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2382	* @retval None
NYX	0:85b3fd62ea1a	2383	*/
NYX	0:85b3fd62ea1a	2384	__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2385	{
NYX	0:85b3fd62ea1a	2386	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
NYX	0:85b3fd62ea1a	2387	}
NYX	0:85b3fd62ea1a	2388
NYX	0:85b3fd62ea1a	2389	/**
NYX	0:85b3fd62ea1a	2390	* @brief Clear Stream 3 direct mode error flag.
NYX	0:85b3fd62ea1a	2391	* @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
NYX	0:85b3fd62ea1a	2392	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2393	* @retval None
NYX	0:85b3fd62ea1a	2394	*/
NYX	0:85b3fd62ea1a	2395	__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2396	{
NYX	0:85b3fd62ea1a	2397	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
NYX	0:85b3fd62ea1a	2398	}
NYX	0:85b3fd62ea1a	2399
NYX	0:85b3fd62ea1a	2400	/**
NYX	0:85b3fd62ea1a	2401	* @brief Clear Stream 4 direct mode error flag.
NYX	0:85b3fd62ea1a	2402	* @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
NYX	0:85b3fd62ea1a	2403	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2404	* @retval None
NYX	0:85b3fd62ea1a	2405	*/
NYX	0:85b3fd62ea1a	2406	__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2407	{
NYX	0:85b3fd62ea1a	2408	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
NYX	0:85b3fd62ea1a	2409	}
NYX	0:85b3fd62ea1a	2410
NYX	0:85b3fd62ea1a	2411	/**
NYX	0:85b3fd62ea1a	2412	* @brief Clear Stream 5 direct mode error flag.
NYX	0:85b3fd62ea1a	2413	* @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
NYX	0:85b3fd62ea1a	2414	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2415	* @retval None
NYX	0:85b3fd62ea1a	2416	*/
NYX	0:85b3fd62ea1a	2417	__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2418	{
NYX	0:85b3fd62ea1a	2419	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
NYX	0:85b3fd62ea1a	2420	}
NYX	0:85b3fd62ea1a	2421
NYX	0:85b3fd62ea1a	2422	/**
NYX	0:85b3fd62ea1a	2423	* @brief Clear Stream 6 direct mode error flag.
NYX	0:85b3fd62ea1a	2424	* @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
NYX	0:85b3fd62ea1a	2425	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2426	* @retval None
NYX	0:85b3fd62ea1a	2427	*/
NYX	0:85b3fd62ea1a	2428	__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2429	{
NYX	0:85b3fd62ea1a	2430	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
NYX	0:85b3fd62ea1a	2431	}
NYX	0:85b3fd62ea1a	2432
NYX	0:85b3fd62ea1a	2433	/**
NYX	0:85b3fd62ea1a	2434	* @brief Clear Stream 7 direct mode error flag.
NYX	0:85b3fd62ea1a	2435	* @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
NYX	0:85b3fd62ea1a	2436	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2437	* @retval None
NYX	0:85b3fd62ea1a	2438	*/
NYX	0:85b3fd62ea1a	2439	__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2440	{
NYX	0:85b3fd62ea1a	2441	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
NYX	0:85b3fd62ea1a	2442	}
NYX	0:85b3fd62ea1a	2443
NYX	0:85b3fd62ea1a	2444	/**
NYX	0:85b3fd62ea1a	2445	* @brief Clear Stream 0 FIFO error flag.
NYX	0:85b3fd62ea1a	2446	* @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
NYX	0:85b3fd62ea1a	2447	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2448	* @retval None
NYX	0:85b3fd62ea1a	2449	*/
NYX	0:85b3fd62ea1a	2450	__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2451	{
NYX	0:85b3fd62ea1a	2452	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
NYX	0:85b3fd62ea1a	2453	}
NYX	0:85b3fd62ea1a	2454
NYX	0:85b3fd62ea1a	2455	/**
NYX	0:85b3fd62ea1a	2456	* @brief Clear Stream 1 FIFO error flag.
NYX	0:85b3fd62ea1a	2457	* @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
NYX	0:85b3fd62ea1a	2458	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2459	* @retval None
NYX	0:85b3fd62ea1a	2460	*/
NYX	0:85b3fd62ea1a	2461	__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2462	{
NYX	0:85b3fd62ea1a	2463	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
NYX	0:85b3fd62ea1a	2464	}
NYX	0:85b3fd62ea1a	2465
NYX	0:85b3fd62ea1a	2466	/**
NYX	0:85b3fd62ea1a	2467	* @brief Clear Stream 2 FIFO error flag.
NYX	0:85b3fd62ea1a	2468	* @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
NYX	0:85b3fd62ea1a	2469	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2470	* @retval None
NYX	0:85b3fd62ea1a	2471	*/
NYX	0:85b3fd62ea1a	2472	__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2473	{
NYX	0:85b3fd62ea1a	2474	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
NYX	0:85b3fd62ea1a	2475	}
NYX	0:85b3fd62ea1a	2476
NYX	0:85b3fd62ea1a	2477	/**
NYX	0:85b3fd62ea1a	2478	* @brief Clear Stream 3 FIFO error flag.
NYX	0:85b3fd62ea1a	2479	* @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
NYX	0:85b3fd62ea1a	2480	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2481	* @retval None
NYX	0:85b3fd62ea1a	2482	*/
NYX	0:85b3fd62ea1a	2483	__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2484	{
NYX	0:85b3fd62ea1a	2485	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
NYX	0:85b3fd62ea1a	2486	}
NYX	0:85b3fd62ea1a	2487
NYX	0:85b3fd62ea1a	2488	/**
NYX	0:85b3fd62ea1a	2489	* @brief Clear Stream 4 FIFO error flag.
NYX	0:85b3fd62ea1a	2490	* @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
NYX	0:85b3fd62ea1a	2491	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2492	* @retval None
NYX	0:85b3fd62ea1a	2493	*/
NYX	0:85b3fd62ea1a	2494	__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2495	{
NYX	0:85b3fd62ea1a	2496	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
NYX	0:85b3fd62ea1a	2497	}
NYX	0:85b3fd62ea1a	2498
NYX	0:85b3fd62ea1a	2499	/**
NYX	0:85b3fd62ea1a	2500	* @brief Clear Stream 5 FIFO error flag.
NYX	0:85b3fd62ea1a	2501	* @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
NYX	0:85b3fd62ea1a	2502	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2503	* @retval None
NYX	0:85b3fd62ea1a	2504	*/
NYX	0:85b3fd62ea1a	2505	__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2506	{
NYX	0:85b3fd62ea1a	2507	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
NYX	0:85b3fd62ea1a	2508	}
NYX	0:85b3fd62ea1a	2509
NYX	0:85b3fd62ea1a	2510	/**
NYX	0:85b3fd62ea1a	2511	* @brief Clear Stream 6 FIFO error flag.
NYX	0:85b3fd62ea1a	2512	* @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
NYX	0:85b3fd62ea1a	2513	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2514	* @retval None
NYX	0:85b3fd62ea1a	2515	*/
NYX	0:85b3fd62ea1a	2516	__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2517	{
NYX	0:85b3fd62ea1a	2518	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
NYX	0:85b3fd62ea1a	2519	}
NYX	0:85b3fd62ea1a	2520
NYX	0:85b3fd62ea1a	2521	/**
NYX	0:85b3fd62ea1a	2522	* @brief Clear Stream 7 FIFO error flag.
NYX	0:85b3fd62ea1a	2523	* @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
NYX	0:85b3fd62ea1a	2524	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2525	* @retval None
NYX	0:85b3fd62ea1a	2526	*/
NYX	0:85b3fd62ea1a	2527	__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
NYX	0:85b3fd62ea1a	2528	{
NYX	0:85b3fd62ea1a	2529	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
NYX	0:85b3fd62ea1a	2530	}
NYX	0:85b3fd62ea1a	2531
NYX	0:85b3fd62ea1a	2532	/**
NYX	0:85b3fd62ea1a	2533	* @}
NYX	0:85b3fd62ea1a	2534	*/
NYX	0:85b3fd62ea1a	2535
NYX	0:85b3fd62ea1a	2536	/** @defgroup DMA_LL_EF_IT_Management IT_Management
NYX	0:85b3fd62ea1a	2537	* @{
NYX	0:85b3fd62ea1a	2538	*/
NYX	0:85b3fd62ea1a	2539
NYX	0:85b3fd62ea1a	2540	/**
NYX	0:85b3fd62ea1a	2541	* @brief Enable Half transfer interrupt.
NYX	0:85b3fd62ea1a	2542	* @rmtoll CR HTIE LL_DMA_EnableIT_HT
NYX	0:85b3fd62ea1a	2543	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2544	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2545	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2546	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2547	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2548	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2549	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2550	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2551	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2552	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2553	* @retval None
NYX	0:85b3fd62ea1a	2554	*/
NYX	0:85b3fd62ea1a	2555	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2556	{
NYX	0:85b3fd62ea1a	2557	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
NYX	0:85b3fd62ea1a	2558	}
NYX	0:85b3fd62ea1a	2559
NYX	0:85b3fd62ea1a	2560	/**
NYX	0:85b3fd62ea1a	2561	* @brief Enable Transfer error interrupt.
NYX	0:85b3fd62ea1a	2562	* @rmtoll CR TEIE LL_DMA_EnableIT_TE
NYX	0:85b3fd62ea1a	2563	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2564	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2565	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2566	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2567	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2568	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2569	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2570	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2571	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2572	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2573	* @retval None
NYX	0:85b3fd62ea1a	2574	*/
NYX	0:85b3fd62ea1a	2575	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2576	{
NYX	0:85b3fd62ea1a	2577	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
NYX	0:85b3fd62ea1a	2578	}
NYX	0:85b3fd62ea1a	2579
NYX	0:85b3fd62ea1a	2580	/**
NYX	0:85b3fd62ea1a	2581	* @brief Enable Transfer complete interrupt.
NYX	0:85b3fd62ea1a	2582	* @rmtoll CR TCIE LL_DMA_EnableIT_TC
NYX	0:85b3fd62ea1a	2583	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2584	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2585	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2586	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2587	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2588	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2589	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2590	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2591	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2592	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2593	* @retval None
NYX	0:85b3fd62ea1a	2594	*/
NYX	0:85b3fd62ea1a	2595	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2596	{
NYX	0:85b3fd62ea1a	2597	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
NYX	0:85b3fd62ea1a	2598	}
NYX	0:85b3fd62ea1a	2599
NYX	0:85b3fd62ea1a	2600	/**
NYX	0:85b3fd62ea1a	2601	* @brief Enable Direct mode error interrupt.
NYX	0:85b3fd62ea1a	2602	* @rmtoll CR DMEIE LL_DMA_EnableIT_DME
NYX	0:85b3fd62ea1a	2603	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2604	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2605	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2606	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2607	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2608	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2609	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2610	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2611	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2612	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2613	* @retval None
NYX	0:85b3fd62ea1a	2614	*/
NYX	0:85b3fd62ea1a	2615	__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2616	{
NYX	0:85b3fd62ea1a	2617	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
NYX	0:85b3fd62ea1a	2618	}
NYX	0:85b3fd62ea1a	2619
NYX	0:85b3fd62ea1a	2620	/**
NYX	0:85b3fd62ea1a	2621	* @brief Enable FIFO error interrupt.
NYX	0:85b3fd62ea1a	2622	* @rmtoll FCR FEIE LL_DMA_EnableIT_FE
NYX	0:85b3fd62ea1a	2623	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2624	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2625	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2626	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2627	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2628	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2629	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2630	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2631	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2632	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2633	* @retval None
NYX	0:85b3fd62ea1a	2634	*/
NYX	0:85b3fd62ea1a	2635	__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2636	{
NYX	0:85b3fd62ea1a	2637	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
NYX	0:85b3fd62ea1a	2638	}
NYX	0:85b3fd62ea1a	2639
NYX	0:85b3fd62ea1a	2640	/**
NYX	0:85b3fd62ea1a	2641	* @brief Disable Half transfer interrupt.
NYX	0:85b3fd62ea1a	2642	* @rmtoll CR HTIE LL_DMA_DisableIT_HT
NYX	0:85b3fd62ea1a	2643	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2644	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2645	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2646	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2647	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2648	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2649	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2650	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2651	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2652	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2653	* @retval None
NYX	0:85b3fd62ea1a	2654	*/
NYX	0:85b3fd62ea1a	2655	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2656	{
NYX	0:85b3fd62ea1a	2657	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
NYX	0:85b3fd62ea1a	2658	}
NYX	0:85b3fd62ea1a	2659
NYX	0:85b3fd62ea1a	2660	/**
NYX	0:85b3fd62ea1a	2661	* @brief Disable Transfer error interrupt.
NYX	0:85b3fd62ea1a	2662	* @rmtoll CR TEIE LL_DMA_DisableIT_TE
NYX	0:85b3fd62ea1a	2663	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2664	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2665	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2666	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2667	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2668	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2669	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2670	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2671	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2672	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2673	* @retval None
NYX	0:85b3fd62ea1a	2674	*/
NYX	0:85b3fd62ea1a	2675	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2676	{
NYX	0:85b3fd62ea1a	2677	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
NYX	0:85b3fd62ea1a	2678	}
NYX	0:85b3fd62ea1a	2679
NYX	0:85b3fd62ea1a	2680	/**
NYX	0:85b3fd62ea1a	2681	* @brief Disable Transfer complete interrupt.
NYX	0:85b3fd62ea1a	2682	* @rmtoll CR TCIE LL_DMA_DisableIT_TC
NYX	0:85b3fd62ea1a	2683	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2684	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2685	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2686	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2687	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2688	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2689	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2690	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2691	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2692	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2693	* @retval None
NYX	0:85b3fd62ea1a	2694	*/
NYX	0:85b3fd62ea1a	2695	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2696	{
NYX	0:85b3fd62ea1a	2697	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
NYX	0:85b3fd62ea1a	2698	}
NYX	0:85b3fd62ea1a	2699
NYX	0:85b3fd62ea1a	2700	/**
NYX	0:85b3fd62ea1a	2701	* @brief Disable Direct mode error interrupt.
NYX	0:85b3fd62ea1a	2702	* @rmtoll CR DMEIE LL_DMA_DisableIT_DME
NYX	0:85b3fd62ea1a	2703	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2704	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2705	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2706	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2707	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2708	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2709	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2710	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2711	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2712	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2713	* @retval None
NYX	0:85b3fd62ea1a	2714	*/
NYX	0:85b3fd62ea1a	2715	__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2716	{
NYX	0:85b3fd62ea1a	2717	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
NYX	0:85b3fd62ea1a	2718	}
NYX	0:85b3fd62ea1a	2719
NYX	0:85b3fd62ea1a	2720	/**
NYX	0:85b3fd62ea1a	2721	* @brief Disable FIFO error interrupt.
NYX	0:85b3fd62ea1a	2722	* @rmtoll FCR FEIE LL_DMA_DisableIT_FE
NYX	0:85b3fd62ea1a	2723	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2724	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2725	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2726	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2727	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2728	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2729	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2730	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2731	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2732	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2733	* @retval None
NYX	0:85b3fd62ea1a	2734	*/
NYX	0:85b3fd62ea1a	2735	__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2736	{
NYX	0:85b3fd62ea1a	2737	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
NYX	0:85b3fd62ea1a	2738	}
NYX	0:85b3fd62ea1a	2739
NYX	0:85b3fd62ea1a	2740	/**
NYX	0:85b3fd62ea1a	2741	* @brief Check if Half transfer interrup is enabled.
NYX	0:85b3fd62ea1a	2742	* @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
NYX	0:85b3fd62ea1a	2743	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2744	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2745	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2746	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2747	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2748	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2749	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2750	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2751	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2752	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2753	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2754	*/
NYX	0:85b3fd62ea1a	2755	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2756	{
NYX	0:85b3fd62ea1a	2757	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
NYX	0:85b3fd62ea1a	2758	}
NYX	0:85b3fd62ea1a	2759
NYX	0:85b3fd62ea1a	2760	/**
NYX	0:85b3fd62ea1a	2761	* @brief Check if Transfer error nterrup is enabled.
NYX	0:85b3fd62ea1a	2762	* @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
NYX	0:85b3fd62ea1a	2763	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2764	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2765	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2766	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2767	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2768	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2769	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2770	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2771	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2772	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2773	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2774	*/
NYX	0:85b3fd62ea1a	2775	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2776	{
NYX	0:85b3fd62ea1a	2777	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
NYX	0:85b3fd62ea1a	2778	}
NYX	0:85b3fd62ea1a	2779
NYX	0:85b3fd62ea1a	2780	/**
NYX	0:85b3fd62ea1a	2781	* @brief Check if Transfer complete interrup is enabled.
NYX	0:85b3fd62ea1a	2782	* @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
NYX	0:85b3fd62ea1a	2783	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2784	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2785	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2786	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2787	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2788	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2789	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2790	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2791	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2792	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2793	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2794	*/
NYX	0:85b3fd62ea1a	2795	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2796	{
NYX	0:85b3fd62ea1a	2797	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
NYX	0:85b3fd62ea1a	2798	}
NYX	0:85b3fd62ea1a	2799
NYX	0:85b3fd62ea1a	2800	/**
NYX	0:85b3fd62ea1a	2801	* @brief Check if Direct mode error interrupt is enabled.
NYX	0:85b3fd62ea1a	2802	* @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
NYX	0:85b3fd62ea1a	2803	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2804	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2805	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2806	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2807	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2808	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2809	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2810	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2811	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2812	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2813	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2814	*/
NYX	0:85b3fd62ea1a	2815	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2816	{
NYX	0:85b3fd62ea1a	2817	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
NYX	0:85b3fd62ea1a	2818	}
NYX	0:85b3fd62ea1a	2819
NYX	0:85b3fd62ea1a	2820	/**
NYX	0:85b3fd62ea1a	2821	* @brief Check if FIFO error interrup is enabled.
NYX	0:85b3fd62ea1a	2822	* @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
NYX	0:85b3fd62ea1a	2823	* @param DMAx DMAx Instance
NYX	0:85b3fd62ea1a	2824	* @param Stream This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	2825	* @arg @ref LL_DMA_STREAM_0
NYX	0:85b3fd62ea1a	2826	* @arg @ref LL_DMA_STREAM_1
NYX	0:85b3fd62ea1a	2827	* @arg @ref LL_DMA_STREAM_2
NYX	0:85b3fd62ea1a	2828	* @arg @ref LL_DMA_STREAM_3
NYX	0:85b3fd62ea1a	2829	* @arg @ref LL_DMA_STREAM_4
NYX	0:85b3fd62ea1a	2830	* @arg @ref LL_DMA_STREAM_5
NYX	0:85b3fd62ea1a	2831	* @arg @ref LL_DMA_STREAM_6
NYX	0:85b3fd62ea1a	2832	* @arg @ref LL_DMA_STREAM_7
NYX	0:85b3fd62ea1a	2833	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	2834	*/
NYX	0:85b3fd62ea1a	2835	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
NYX	0:85b3fd62ea1a	2836	{
NYX	0:85b3fd62ea1a	2837	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
NYX	0:85b3fd62ea1a	2838	}
NYX	0:85b3fd62ea1a	2839
NYX	0:85b3fd62ea1a	2840	/**
NYX	0:85b3fd62ea1a	2841	* @}
NYX	0:85b3fd62ea1a	2842	*/
NYX	0:85b3fd62ea1a	2843
NYX	0:85b3fd62ea1a	2844	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	2845	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
NYX	0:85b3fd62ea1a	2846	* @{
NYX	0:85b3fd62ea1a	2847	*/
NYX	0:85b3fd62ea1a	2848
NYX	0:85b3fd62ea1a	2849	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Stream, LL_DMA_InitTypeDef DMA_InitStruct);
NYX	0:85b3fd62ea1a	2850	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
NYX	0:85b3fd62ea1a	2851	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
NYX	0:85b3fd62ea1a	2852
NYX	0:85b3fd62ea1a	2853	/**
NYX	0:85b3fd62ea1a	2854	* @}
NYX	0:85b3fd62ea1a	2855	*/
NYX	0:85b3fd62ea1a	2856	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	2857
NYX	0:85b3fd62ea1a	2858	/**
NYX	0:85b3fd62ea1a	2859	* @}
NYX	0:85b3fd62ea1a	2860	*/
NYX	0:85b3fd62ea1a	2861
NYX	0:85b3fd62ea1a	2862	/**
NYX	0:85b3fd62ea1a	2863	* @}
NYX	0:85b3fd62ea1a	2864	*/
NYX	0:85b3fd62ea1a	2865
NYX	0:85b3fd62ea1a	2866	#endif /* DMA1 \|\| DMA2 */
NYX	0:85b3fd62ea1a	2867
NYX	0:85b3fd62ea1a	2868	/**
NYX	0:85b3fd62ea1a	2869	* @}
NYX	0:85b3fd62ea1a	2870	*/
NYX	0:85b3fd62ea1a	2871
NYX	0:85b3fd62ea1a	2872	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	2873	}
NYX	0:85b3fd62ea1a	2874	#endif
NYX	0:85b3fd62ea1a	2875
NYX	0:85b3fd62ea1a	2876	#endif /* __STM32F4xx_LL_DMA_H */
NYX	0:85b3fd62ea1a	2877
NYX	0:85b3fd62ea1a	2878	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
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Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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