Takaaki Numai / mbed-dev

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Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_dma.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief DMA LL module driver.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 38
NYX 0:85b3fd62ea1a 39 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 40 #include "stm32f4xx_ll_dma.h"
NYX 0:85b3fd62ea1a 41 #include "stm32f4xx_ll_bus.h"
NYX 0:85b3fd62ea1a 42 #ifdef USE_FULL_ASSERT
NYX 0:85b3fd62ea1a 43 #include "stm32_assert.h"
NYX 0:85b3fd62ea1a 44 #else
NYX 0:85b3fd62ea1a 45 #define assert_param(expr) ((void)0U)
NYX 0:85b3fd62ea1a 46 #endif
NYX 0:85b3fd62ea1a 47
NYX 0:85b3fd62ea1a 48 /** @addtogroup STM32F4xx_LL_Driver
NYX 0:85b3fd62ea1a 49 * @{
NYX 0:85b3fd62ea1a 50 */
NYX 0:85b3fd62ea1a 51
NYX 0:85b3fd62ea1a 52 #if defined (DMA1) || defined (DMA2)
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54 /** @defgroup DMA_LL DMA
NYX 0:85b3fd62ea1a 55 * @{
NYX 0:85b3fd62ea1a 56 */
NYX 0:85b3fd62ea1a 57
NYX 0:85b3fd62ea1a 58 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 59 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 61 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 62 /** @addtogroup DMA_LL_Private_Macros
NYX 0:85b3fd62ea1a 63 * @{
NYX 0:85b3fd62ea1a 64 */
NYX 0:85b3fd62ea1a 65 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
NYX 0:85b3fd62ea1a 66 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
NYX 0:85b3fd62ea1a 67 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
NYX 0:85b3fd62ea1a 70 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
NYX 0:85b3fd62ea1a 71 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
NYX 0:85b3fd62ea1a 72
NYX 0:85b3fd62ea1a 73 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
NYX 0:85b3fd62ea1a 74 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
NYX 0:85b3fd62ea1a 75
NYX 0:85b3fd62ea1a 76 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
NYX 0:85b3fd62ea1a 77 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
NYX 0:85b3fd62ea1a 78
NYX 0:85b3fd62ea1a 79 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
NYX 0:85b3fd62ea1a 80 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
NYX 0:85b3fd62ea1a 81 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
NYX 0:85b3fd62ea1a 82
NYX 0:85b3fd62ea1a 83 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
NYX 0:85b3fd62ea1a 84 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
NYX 0:85b3fd62ea1a 85 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
NYX 0:85b3fd62ea1a 86
NYX 0:85b3fd62ea1a 87 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
NYX 0:85b3fd62ea1a 88
NYX 0:85b3fd62ea1a 89 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
NYX 0:85b3fd62ea1a 90 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
NYX 0:85b3fd62ea1a 91 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
NYX 0:85b3fd62ea1a 92 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
NYX 0:85b3fd62ea1a 93 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
NYX 0:85b3fd62ea1a 94 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
NYX 0:85b3fd62ea1a 95 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
NYX 0:85b3fd62ea1a 96 ((__VALUE__) == LL_DMA_CHANNEL_7))
NYX 0:85b3fd62ea1a 97
NYX 0:85b3fd62ea1a 98 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
NYX 0:85b3fd62ea1a 99 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
NYX 0:85b3fd62ea1a 100 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
NYX 0:85b3fd62ea1a 101 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
NYX 0:85b3fd62ea1a 102
NYX 0:85b3fd62ea1a 103 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
NYX 0:85b3fd62ea1a 104 (((STREAM) == LL_DMA_STREAM_0) || \
NYX 0:85b3fd62ea1a 105 ((STREAM) == LL_DMA_STREAM_1) || \
NYX 0:85b3fd62ea1a 106 ((STREAM) == LL_DMA_STREAM_2) || \
NYX 0:85b3fd62ea1a 107 ((STREAM) == LL_DMA_STREAM_3) || \
NYX 0:85b3fd62ea1a 108 ((STREAM) == LL_DMA_STREAM_4) || \
NYX 0:85b3fd62ea1a 109 ((STREAM) == LL_DMA_STREAM_5) || \
NYX 0:85b3fd62ea1a 110 ((STREAM) == LL_DMA_STREAM_6) || \
NYX 0:85b3fd62ea1a 111 ((STREAM) == LL_DMA_STREAM_7) || \
NYX 0:85b3fd62ea1a 112 ((STREAM) == LL_DMA_STREAM_ALL))) ||\
NYX 0:85b3fd62ea1a 113 (((INSTANCE) == DMA2) && \
NYX 0:85b3fd62ea1a 114 (((STREAM) == LL_DMA_STREAM_0) || \
NYX 0:85b3fd62ea1a 115 ((STREAM) == LL_DMA_STREAM_1) || \
NYX 0:85b3fd62ea1a 116 ((STREAM) == LL_DMA_STREAM_2) || \
NYX 0:85b3fd62ea1a 117 ((STREAM) == LL_DMA_STREAM_3) || \
NYX 0:85b3fd62ea1a 118 ((STREAM) == LL_DMA_STREAM_4) || \
NYX 0:85b3fd62ea1a 119 ((STREAM) == LL_DMA_STREAM_5) || \
NYX 0:85b3fd62ea1a 120 ((STREAM) == LL_DMA_STREAM_6) || \
NYX 0:85b3fd62ea1a 121 ((STREAM) == LL_DMA_STREAM_7) || \
NYX 0:85b3fd62ea1a 122 ((STREAM) == LL_DMA_STREAM_ALL))))
NYX 0:85b3fd62ea1a 123
NYX 0:85b3fd62ea1a 124 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
NYX 0:85b3fd62ea1a 125 ((STATE) == LL_DMA_FIFOMODE_ENABLE))
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
NYX 0:85b3fd62ea1a 128 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
NYX 0:85b3fd62ea1a 129 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
NYX 0:85b3fd62ea1a 130 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
NYX 0:85b3fd62ea1a 131
NYX 0:85b3fd62ea1a 132 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
NYX 0:85b3fd62ea1a 133 ((BURST) == LL_DMA_MBURST_INC4) || \
NYX 0:85b3fd62ea1a 134 ((BURST) == LL_DMA_MBURST_INC8) || \
NYX 0:85b3fd62ea1a 135 ((BURST) == LL_DMA_MBURST_INC16))
NYX 0:85b3fd62ea1a 136
NYX 0:85b3fd62ea1a 137 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
NYX 0:85b3fd62ea1a 138 ((BURST) == LL_DMA_PBURST_INC4) || \
NYX 0:85b3fd62ea1a 139 ((BURST) == LL_DMA_PBURST_INC8) || \
NYX 0:85b3fd62ea1a 140 ((BURST) == LL_DMA_PBURST_INC16))
NYX 0:85b3fd62ea1a 141
NYX 0:85b3fd62ea1a 142 /**
NYX 0:85b3fd62ea1a 143 * @}
NYX 0:85b3fd62ea1a 144 */
NYX 0:85b3fd62ea1a 145
NYX 0:85b3fd62ea1a 146 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 147
NYX 0:85b3fd62ea1a 148 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 149 /** @addtogroup DMA_LL_Exported_Functions
NYX 0:85b3fd62ea1a 150 * @{
NYX 0:85b3fd62ea1a 151 */
NYX 0:85b3fd62ea1a 152
NYX 0:85b3fd62ea1a 153 /** @addtogroup DMA_LL_EF_Init
NYX 0:85b3fd62ea1a 154 * @{
NYX 0:85b3fd62ea1a 155 */
NYX 0:85b3fd62ea1a 156
NYX 0:85b3fd62ea1a 157 /**
NYX 0:85b3fd62ea1a 158 * @brief De-initialize the DMA registers to their default reset values.
NYX 0:85b3fd62ea1a 159 * @param DMAx DMAx Instance
NYX 0:85b3fd62ea1a 160 * @param Stream This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 161 * @arg @ref LL_DMA_STREAM_0
NYX 0:85b3fd62ea1a 162 * @arg @ref LL_DMA_STREAM_1
NYX 0:85b3fd62ea1a 163 * @arg @ref LL_DMA_STREAM_2
NYX 0:85b3fd62ea1a 164 * @arg @ref LL_DMA_STREAM_3
NYX 0:85b3fd62ea1a 165 * @arg @ref LL_DMA_STREAM_4
NYX 0:85b3fd62ea1a 166 * @arg @ref LL_DMA_STREAM_5
NYX 0:85b3fd62ea1a 167 * @arg @ref LL_DMA_STREAM_6
NYX 0:85b3fd62ea1a 168 * @arg @ref LL_DMA_STREAM_7
NYX 0:85b3fd62ea1a 169 * @arg @ref LL_DMA_STREAM_ALL
NYX 0:85b3fd62ea1a 170 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 171 * - SUCCESS: DMA registers are de-initialized
NYX 0:85b3fd62ea1a 172 * - ERROR: DMA registers are not de-initialized
NYX 0:85b3fd62ea1a 173 */
NYX 0:85b3fd62ea1a 174 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
NYX 0:85b3fd62ea1a 175 {
NYX 0:85b3fd62ea1a 176 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
NYX 0:85b3fd62ea1a 177 ErrorStatus status = SUCCESS;
NYX 0:85b3fd62ea1a 178
NYX 0:85b3fd62ea1a 179 /* Check the DMA Instance DMAx and Stream parameters*/
NYX 0:85b3fd62ea1a 180 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
NYX 0:85b3fd62ea1a 181
NYX 0:85b3fd62ea1a 182 if (Stream == LL_DMA_STREAM_ALL)
NYX 0:85b3fd62ea1a 183 {
NYX 0:85b3fd62ea1a 184 if (DMAx == DMA1)
NYX 0:85b3fd62ea1a 185 {
NYX 0:85b3fd62ea1a 186 /* Force reset of DMA clock */
NYX 0:85b3fd62ea1a 187 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
NYX 0:85b3fd62ea1a 188
NYX 0:85b3fd62ea1a 189 /* Release reset of DMA clock */
NYX 0:85b3fd62ea1a 190 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
NYX 0:85b3fd62ea1a 191 }
NYX 0:85b3fd62ea1a 192 else if (DMAx == DMA2)
NYX 0:85b3fd62ea1a 193 {
NYX 0:85b3fd62ea1a 194 /* Force reset of DMA clock */
NYX 0:85b3fd62ea1a 195 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
NYX 0:85b3fd62ea1a 196
NYX 0:85b3fd62ea1a 197 /* Release reset of DMA clock */
NYX 0:85b3fd62ea1a 198 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
NYX 0:85b3fd62ea1a 199 }
NYX 0:85b3fd62ea1a 200 else
NYX 0:85b3fd62ea1a 201 {
NYX 0:85b3fd62ea1a 202 status = ERROR;
NYX 0:85b3fd62ea1a 203 }
NYX 0:85b3fd62ea1a 204 }
NYX 0:85b3fd62ea1a 205 else
NYX 0:85b3fd62ea1a 206 {
NYX 0:85b3fd62ea1a 207 /* Disable the selected Stream */
NYX 0:85b3fd62ea1a 208 LL_DMA_DisableStream(DMAx,Stream);
NYX 0:85b3fd62ea1a 209
NYX 0:85b3fd62ea1a 210 /* Get the DMA Stream Instance */
NYX 0:85b3fd62ea1a 211 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
NYX 0:85b3fd62ea1a 212
NYX 0:85b3fd62ea1a 213 /* Reset DMAx_Streamy configuration register */
NYX 0:85b3fd62ea1a 214 LL_DMA_WriteReg(tmp, CR, 0U);
NYX 0:85b3fd62ea1a 215
NYX 0:85b3fd62ea1a 216 /* Reset DMAx_Streamy remaining bytes register */
NYX 0:85b3fd62ea1a 217 LL_DMA_WriteReg(tmp, NDTR, 0U);
NYX 0:85b3fd62ea1a 218
NYX 0:85b3fd62ea1a 219 /* Reset DMAx_Streamy peripheral address register */
NYX 0:85b3fd62ea1a 220 LL_DMA_WriteReg(tmp, PAR, 0U);
NYX 0:85b3fd62ea1a 221
NYX 0:85b3fd62ea1a 222 /* Reset DMAx_Streamy memory address register */
NYX 0:85b3fd62ea1a 223 LL_DMA_WriteReg(tmp, M0AR, 0U);
NYX 0:85b3fd62ea1a 224
NYX 0:85b3fd62ea1a 225 /* Reset DMAx_Streamy memory address register */
NYX 0:85b3fd62ea1a 226 LL_DMA_WriteReg(tmp, M1AR, 0U);
NYX 0:85b3fd62ea1a 227
NYX 0:85b3fd62ea1a 228 /* Reset DMAx_Streamy FIFO control register */
NYX 0:85b3fd62ea1a 229 LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
NYX 0:85b3fd62ea1a 230
NYX 0:85b3fd62ea1a 231 /* Reset Channel register field for DMAx Stream*/
NYX 0:85b3fd62ea1a 232 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
NYX 0:85b3fd62ea1a 233
NYX 0:85b3fd62ea1a 234 if(Stream == LL_DMA_STREAM_0)
NYX 0:85b3fd62ea1a 235 {
NYX 0:85b3fd62ea1a 236 /* Reset the Stream0 pending flags */
NYX 0:85b3fd62ea1a 237 DMAx->LIFCR = 0x0000003FU;
NYX 0:85b3fd62ea1a 238 }
NYX 0:85b3fd62ea1a 239 else if(Stream == LL_DMA_STREAM_1)
NYX 0:85b3fd62ea1a 240 {
NYX 0:85b3fd62ea1a 241 /* Reset the Stream1 pending flags */
NYX 0:85b3fd62ea1a 242 DMAx->LIFCR = 0x00000F40U;
NYX 0:85b3fd62ea1a 243 }
NYX 0:85b3fd62ea1a 244 else if(Stream == LL_DMA_STREAM_2)
NYX 0:85b3fd62ea1a 245 {
NYX 0:85b3fd62ea1a 246 /* Reset the Stream2 pending flags */
NYX 0:85b3fd62ea1a 247 DMAx->LIFCR = 0x003F0000U;
NYX 0:85b3fd62ea1a 248 }
NYX 0:85b3fd62ea1a 249 else if(Stream == LL_DMA_STREAM_3)
NYX 0:85b3fd62ea1a 250 {
NYX 0:85b3fd62ea1a 251 /* Reset the Stream3 pending flags */
NYX 0:85b3fd62ea1a 252 DMAx->LIFCR = 0x0F400000U;
NYX 0:85b3fd62ea1a 253 }
NYX 0:85b3fd62ea1a 254 else if(Stream == LL_DMA_STREAM_4)
NYX 0:85b3fd62ea1a 255 {
NYX 0:85b3fd62ea1a 256 /* Reset the Stream4 pending flags */
NYX 0:85b3fd62ea1a 257 DMAx->HIFCR = 0x0000003FU;
NYX 0:85b3fd62ea1a 258 }
NYX 0:85b3fd62ea1a 259 else if(Stream == LL_DMA_STREAM_5)
NYX 0:85b3fd62ea1a 260 {
NYX 0:85b3fd62ea1a 261 /* Reset the Stream5 pending flags */
NYX 0:85b3fd62ea1a 262 DMAx->HIFCR = 0x00000F40U;
NYX 0:85b3fd62ea1a 263 }
NYX 0:85b3fd62ea1a 264 else if(Stream == LL_DMA_STREAM_6)
NYX 0:85b3fd62ea1a 265 {
NYX 0:85b3fd62ea1a 266 /* Reset the Stream6 pending flags */
NYX 0:85b3fd62ea1a 267 DMAx->HIFCR = 0x003F0000U;
NYX 0:85b3fd62ea1a 268 }
NYX 0:85b3fd62ea1a 269 else if(Stream == LL_DMA_STREAM_7)
NYX 0:85b3fd62ea1a 270 {
NYX 0:85b3fd62ea1a 271 /* Reset the Stream7 pending flags */
NYX 0:85b3fd62ea1a 272 DMAx->HIFCR = 0x0F400000U;
NYX 0:85b3fd62ea1a 273 }
NYX 0:85b3fd62ea1a 274 else
NYX 0:85b3fd62ea1a 275 {
NYX 0:85b3fd62ea1a 276 status = ERROR;
NYX 0:85b3fd62ea1a 277 }
NYX 0:85b3fd62ea1a 278 }
NYX 0:85b3fd62ea1a 279
NYX 0:85b3fd62ea1a 280 return status;
NYX 0:85b3fd62ea1a 281 }
NYX 0:85b3fd62ea1a 282
NYX 0:85b3fd62ea1a 283 /**
NYX 0:85b3fd62ea1a 284 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
NYX 0:85b3fd62ea1a 285 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
NYX 0:85b3fd62ea1a 286 * @arg @ref __LL_DMA_GET_INSTANCE
NYX 0:85b3fd62ea1a 287 * @arg @ref __LL_DMA_GET_STREAM
NYX 0:85b3fd62ea1a 288 * @param DMAx DMAx Instance
NYX 0:85b3fd62ea1a 289 * @param Stream This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 290 * @arg @ref LL_DMA_STREAM_0
NYX 0:85b3fd62ea1a 291 * @arg @ref LL_DMA_STREAM_1
NYX 0:85b3fd62ea1a 292 * @arg @ref LL_DMA_STREAM_2
NYX 0:85b3fd62ea1a 293 * @arg @ref LL_DMA_STREAM_3
NYX 0:85b3fd62ea1a 294 * @arg @ref LL_DMA_STREAM_4
NYX 0:85b3fd62ea1a 295 * @arg @ref LL_DMA_STREAM_5
NYX 0:85b3fd62ea1a 296 * @arg @ref LL_DMA_STREAM_6
NYX 0:85b3fd62ea1a 297 * @arg @ref LL_DMA_STREAM_7
NYX 0:85b3fd62ea1a 298 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
NYX 0:85b3fd62ea1a 299 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 300 * - SUCCESS: DMA registers are initialized
NYX 0:85b3fd62ea1a 301 * - ERROR: Not applicable
NYX 0:85b3fd62ea1a 302 */
NYX 0:85b3fd62ea1a 303 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
NYX 0:85b3fd62ea1a 304 {
NYX 0:85b3fd62ea1a 305 /* Check the DMA Instance DMAx and Stream parameters*/
NYX 0:85b3fd62ea1a 306 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
NYX 0:85b3fd62ea1a 307
NYX 0:85b3fd62ea1a 308 /* Check the DMA parameters from DMA_InitStruct */
NYX 0:85b3fd62ea1a 309 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
NYX 0:85b3fd62ea1a 310 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
NYX 0:85b3fd62ea1a 311 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
NYX 0:85b3fd62ea1a 312 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
NYX 0:85b3fd62ea1a 313 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
NYX 0:85b3fd62ea1a 314 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
NYX 0:85b3fd62ea1a 315 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
NYX 0:85b3fd62ea1a 316 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
NYX 0:85b3fd62ea1a 317 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
NYX 0:85b3fd62ea1a 318 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
NYX 0:85b3fd62ea1a 319 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
NYX 0:85b3fd62ea1a 320 when FIFO mode is enabled */
NYX 0:85b3fd62ea1a 321 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
NYX 0:85b3fd62ea1a 322 {
NYX 0:85b3fd62ea1a 323 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
NYX 0:85b3fd62ea1a 324 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
NYX 0:85b3fd62ea1a 325 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
NYX 0:85b3fd62ea1a 326 }
NYX 0:85b3fd62ea1a 327
NYX 0:85b3fd62ea1a 328 /*---------------------------- DMAx SxCR Configuration ------------------------
NYX 0:85b3fd62ea1a 329 * Configure DMAx_Streamy: data transfer direction, data transfer mode,
NYX 0:85b3fd62ea1a 330 * peripheral and memory increment mode,
NYX 0:85b3fd62ea1a 331 * data size alignment and priority level with parameters :
NYX 0:85b3fd62ea1a 332 * - Direction: DMA_SxCR_DIR[1:0] bits
NYX 0:85b3fd62ea1a 333 * - Mode: DMA_SxCR_CIRC bit
NYX 0:85b3fd62ea1a 334 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
NYX 0:85b3fd62ea1a 335 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
NYX 0:85b3fd62ea1a 336 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
NYX 0:85b3fd62ea1a 337 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
NYX 0:85b3fd62ea1a 338 * - Priority: DMA_SxCR_PL[1:0] bits
NYX 0:85b3fd62ea1a 339 */
NYX 0:85b3fd62ea1a 340 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
NYX 0:85b3fd62ea1a 341 DMA_InitStruct->Mode | \
NYX 0:85b3fd62ea1a 342 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
NYX 0:85b3fd62ea1a 343 DMA_InitStruct->MemoryOrM2MDstIncMode | \
NYX 0:85b3fd62ea1a 344 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
NYX 0:85b3fd62ea1a 345 DMA_InitStruct->MemoryOrM2MDstDataSize | \
NYX 0:85b3fd62ea1a 346 DMA_InitStruct->Priority
NYX 0:85b3fd62ea1a 347 );
NYX 0:85b3fd62ea1a 348
NYX 0:85b3fd62ea1a 349 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
NYX 0:85b3fd62ea1a 350 {
NYX 0:85b3fd62ea1a 351 /*---------------------------- DMAx SxFCR Configuration ------------------------
NYX 0:85b3fd62ea1a 352 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
NYX 0:85b3fd62ea1a 353 * - FIFOMode: DMA_SxFCR_DMDIS bit
NYX 0:85b3fd62ea1a 354 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
NYX 0:85b3fd62ea1a 355 */
NYX 0:85b3fd62ea1a 356 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
NYX 0:85b3fd62ea1a 357
NYX 0:85b3fd62ea1a 358 /*---------------------------- DMAx SxCR Configuration --------------------------
NYX 0:85b3fd62ea1a 359 * Configure DMAx_Streamy: memory burst transfer with parameters :
NYX 0:85b3fd62ea1a 360 * - MemBurst: DMA_SxCR_MBURST[1:0] bits
NYX 0:85b3fd62ea1a 361 */
NYX 0:85b3fd62ea1a 362 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
NYX 0:85b3fd62ea1a 363
NYX 0:85b3fd62ea1a 364 /*---------------------------- DMAx SxCR Configuration --------------------------
NYX 0:85b3fd62ea1a 365 * Configure DMAx_Streamy: peripheral burst transfer with parameters :
NYX 0:85b3fd62ea1a 366 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
NYX 0:85b3fd62ea1a 367 */
NYX 0:85b3fd62ea1a 368 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
NYX 0:85b3fd62ea1a 369 }
NYX 0:85b3fd62ea1a 370
NYX 0:85b3fd62ea1a 371 /*-------------------------- DMAx SxM0AR Configuration --------------------------
NYX 0:85b3fd62ea1a 372 * Configure the memory or destination base address with parameter :
NYX 0:85b3fd62ea1a 373 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
NYX 0:85b3fd62ea1a 374 */
NYX 0:85b3fd62ea1a 375 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
NYX 0:85b3fd62ea1a 376
NYX 0:85b3fd62ea1a 377 /*-------------------------- DMAx SxPAR Configuration ---------------------------
NYX 0:85b3fd62ea1a 378 * Configure the peripheral or source base address with parameter :
NYX 0:85b3fd62ea1a 379 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
NYX 0:85b3fd62ea1a 380 */
NYX 0:85b3fd62ea1a 381 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
NYX 0:85b3fd62ea1a 382
NYX 0:85b3fd62ea1a 383 /*--------------------------- DMAx SxNDTR Configuration -------------------------
NYX 0:85b3fd62ea1a 384 * Configure the peripheral base address with parameter :
NYX 0:85b3fd62ea1a 385 * - NbData: DMA_SxNDT[15:0] bits
NYX 0:85b3fd62ea1a 386 */
NYX 0:85b3fd62ea1a 387 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
NYX 0:85b3fd62ea1a 388
NYX 0:85b3fd62ea1a 389 /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
NYX 0:85b3fd62ea1a 390 * Configure the peripheral base address with parameter :
NYX 0:85b3fd62ea1a 391 * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
NYX 0:85b3fd62ea1a 392 */
NYX 0:85b3fd62ea1a 393 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
NYX 0:85b3fd62ea1a 394
NYX 0:85b3fd62ea1a 395 return SUCCESS;
NYX 0:85b3fd62ea1a 396 }
NYX 0:85b3fd62ea1a 397
NYX 0:85b3fd62ea1a 398 /**
NYX 0:85b3fd62ea1a 399 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
NYX 0:85b3fd62ea1a 400 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
NYX 0:85b3fd62ea1a 401 * @retval None
NYX 0:85b3fd62ea1a 402 */
NYX 0:85b3fd62ea1a 403 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
NYX 0:85b3fd62ea1a 404 {
NYX 0:85b3fd62ea1a 405 /* Set DMA_InitStruct fields to default values */
NYX 0:85b3fd62ea1a 406 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
NYX 0:85b3fd62ea1a 407 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
NYX 0:85b3fd62ea1a 408 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
NYX 0:85b3fd62ea1a 409 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
NYX 0:85b3fd62ea1a 410 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
NYX 0:85b3fd62ea1a 411 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
NYX 0:85b3fd62ea1a 412 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
NYX 0:85b3fd62ea1a 413 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
NYX 0:85b3fd62ea1a 414 DMA_InitStruct->NbData = 0x00000000U;
NYX 0:85b3fd62ea1a 415 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
NYX 0:85b3fd62ea1a 416 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
NYX 0:85b3fd62ea1a 417 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
NYX 0:85b3fd62ea1a 418 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
NYX 0:85b3fd62ea1a 419 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
NYX 0:85b3fd62ea1a 420 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
NYX 0:85b3fd62ea1a 421 }
NYX 0:85b3fd62ea1a 422
NYX 0:85b3fd62ea1a 423 /**
NYX 0:85b3fd62ea1a 424 * @}
NYX 0:85b3fd62ea1a 425 */
NYX 0:85b3fd62ea1a 426
NYX 0:85b3fd62ea1a 427 /**
NYX 0:85b3fd62ea1a 428 * @}
NYX 0:85b3fd62ea1a 429 */
NYX 0:85b3fd62ea1a 430
NYX 0:85b3fd62ea1a 431 /**
NYX 0:85b3fd62ea1a 432 * @}
NYX 0:85b3fd62ea1a 433 */
NYX 0:85b3fd62ea1a 434
NYX 0:85b3fd62ea1a 435 #endif /* DMA1 || DMA2 */
NYX 0:85b3fd62ea1a 436
NYX 0:85b3fd62ea1a 437 /**
NYX 0:85b3fd62ea1a 438 * @}
NYX 0:85b3fd62ea1a 439 */
NYX 0:85b3fd62ea1a 440
NYX 0:85b3fd62ea1a 441 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 442
NYX 0:85b3fd62ea1a 443 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/