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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_ll_dac.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of DAC LL module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_LL_DAC_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_LL_DAC_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	47	#include "stm32f4xx.h"
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_LL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	#if defined(DAC)
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/** @defgroup DAC_LL DAC
NYX	0:85b3fd62ea1a	56	* @{
NYX	0:85b3fd62ea1a	57	*/
NYX	0:85b3fd62ea1a	58
NYX	0:85b3fd62ea1a	59	/* Private types -------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	60	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	61
NYX	0:85b3fd62ea1a	62	/* Private constants ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	63	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
NYX	0:85b3fd62ea1a	64	* @{
NYX	0:85b3fd62ea1a	65	*/
NYX	0:85b3fd62ea1a	66
NYX	0:85b3fd62ea1a	67	/* Internal masks for DAC channels definition */
NYX	0:85b3fd62ea1a	68	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
NYX	0:85b3fd62ea1a	69	/* - channel bits position into register CR */
NYX	0:85b3fd62ea1a	70	/* - channel bits position into register SWTRIG */
NYX	0:85b3fd62ea1a	71	/* - channel register offset of data holding register DHRx */
NYX	0:85b3fd62ea1a	72	/* - channel register offset of data output register DORx */
NYX	0:85b3fd62ea1a	73	#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
NYX	0:85b3fd62ea1a	74	#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
NYX	0:85b3fd62ea1a	75	#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
NYX	0:85b3fd62ea1a	76
NYX	0:85b3fd62ea1a	77	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
NYX	0:85b3fd62ea1a	78	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	79	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
NYX	0:85b3fd62ea1a	80	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
NYX	0:85b3fd62ea1a	81	#else
NYX	0:85b3fd62ea1a	82	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
NYX	0:85b3fd62ea1a	83	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	84
NYX	0:85b3fd62ea1a	85	#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
NYX	0:85b3fd62ea1a	86	#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
NYX	0:85b3fd62ea1a	87	#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
NYX	0:85b3fd62ea1a	88	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	89	#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
NYX	0:85b3fd62ea1a	90	#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
NYX	0:85b3fd62ea1a	91	#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
NYX	0:85b3fd62ea1a	92	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	93	#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
NYX	0:85b3fd62ea1a	94	#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
NYX	0:85b3fd62ea1a	95	#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
NYX	0:85b3fd62ea1a	96	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
NYX	0:85b3fd62ea1a	97
NYX	0:85b3fd62ea1a	98	#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
NYX	0:85b3fd62ea1a	99	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	100	#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
NYX	0:85b3fd62ea1a	101	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
NYX	0:85b3fd62ea1a	102	#else
NYX	0:85b3fd62ea1a	103	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
NYX	0:85b3fd62ea1a	104	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	105
NYX	0:85b3fd62ea1a	106	/* DAC registers bits positions */
NYX	0:85b3fd62ea1a	107	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	108	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
NYX	0:85b3fd62ea1a	109	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
NYX	0:85b3fd62ea1a	110	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
NYX	0:85b3fd62ea1a	111	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	112
NYX	0:85b3fd62ea1a	113	/* Miscellaneous data */
NYX	0:85b3fd62ea1a	114	#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
NYX	0:85b3fd62ea1a	115
NYX	0:85b3fd62ea1a	116	/**
NYX	0:85b3fd62ea1a	117	* @}
NYX	0:85b3fd62ea1a	118	*/
NYX	0:85b3fd62ea1a	119
NYX	0:85b3fd62ea1a	120
NYX	0:85b3fd62ea1a	121	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	122	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
NYX	0:85b3fd62ea1a	123	* @{
NYX	0:85b3fd62ea1a	124	*/
NYX	0:85b3fd62ea1a	125
NYX	0:85b3fd62ea1a	126	/**
NYX	0:85b3fd62ea1a	127	* @brief Driver macro reserved for internal use: isolate bits with the
NYX	0:85b3fd62ea1a	128	* selected mask and shift them to the register LSB
NYX	0:85b3fd62ea1a	129	* (shift mask on register position bit 0).
NYX	0:85b3fd62ea1a	130	* @param __BITS__ Bits in register 32 bits
NYX	0:85b3fd62ea1a	131	* @param __MASK__ Mask in register 32 bits
NYX	0:85b3fd62ea1a	132	* @retval Bits in register 32 bits
NYX	0:85b3fd62ea1a	133	*/
NYX	0:85b3fd62ea1a	134	#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
NYX	0:85b3fd62ea1a	135	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
NYX	0:85b3fd62ea1a	136
NYX	0:85b3fd62ea1a	137	/**
NYX	0:85b3fd62ea1a	138	* @brief Driver macro reserved for internal use: set a pointer to
NYX	0:85b3fd62ea1a	139	* a register from a register basis from which an offset
NYX	0:85b3fd62ea1a	140	* is applied.
NYX	0:85b3fd62ea1a	141	* @param __REG__ Register basis from which the offset is applied.
NYX	0:85b3fd62ea1a	142	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
NYX	0:85b3fd62ea1a	143	* @retval Pointer to register address
NYX	0:85b3fd62ea1a	144	*/
NYX	0:85b3fd62ea1a	145	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
NYX	0:85b3fd62ea1a	146	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
NYX	0:85b3fd62ea1a	147
NYX	0:85b3fd62ea1a	148	/**
NYX	0:85b3fd62ea1a	149	* @}
NYX	0:85b3fd62ea1a	150	*/
NYX	0:85b3fd62ea1a	151
NYX	0:85b3fd62ea1a	152
NYX	0:85b3fd62ea1a	153	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	154	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	155	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
NYX	0:85b3fd62ea1a	156	* @{
NYX	0:85b3fd62ea1a	157	*/
NYX	0:85b3fd62ea1a	158
NYX	0:85b3fd62ea1a	159	/**
NYX	0:85b3fd62ea1a	160	* @brief Structure definition of some features of DAC instance.
NYX	0:85b3fd62ea1a	161	*/
NYX	0:85b3fd62ea1a	162	typedef struct
NYX	0:85b3fd62ea1a	163	{
NYX	0:85b3fd62ea1a	164	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
NYX	0:85b3fd62ea1a	165	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
NYX	0:85b3fd62ea1a	166
NYX	0:85b3fd62ea1a	167	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
NYX	0:85b3fd62ea1a	168
NYX	0:85b3fd62ea1a	169	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
NYX	0:85b3fd62ea1a	170	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
NYX	0:85b3fd62ea1a	171
NYX	0:85b3fd62ea1a	172	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
NYX	0:85b3fd62ea1a	173
NYX	0:85b3fd62ea1a	174	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
NYX	0:85b3fd62ea1a	175	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
NYX	0:85b3fd62ea1a	176	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
NYX	0:85b3fd62ea1a	177	@note If waveform automatic generation mode is disabled, this parameter is discarded.
NYX	0:85b3fd62ea1a	178
NYX	0:85b3fd62ea1a	179	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
NYX	0:85b3fd62ea1a	180
NYX	0:85b3fd62ea1a	181	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
NYX	0:85b3fd62ea1a	182	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
NYX	0:85b3fd62ea1a	183
NYX	0:85b3fd62ea1a	184	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
NYX	0:85b3fd62ea1a	185
NYX	0:85b3fd62ea1a	186	} LL_DAC_InitTypeDef;
NYX	0:85b3fd62ea1a	187
NYX	0:85b3fd62ea1a	188	/**
NYX	0:85b3fd62ea1a	189	* @}
NYX	0:85b3fd62ea1a	190	*/
NYX	0:85b3fd62ea1a	191	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	192
NYX	0:85b3fd62ea1a	193	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	194	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
NYX	0:85b3fd62ea1a	195	* @{
NYX	0:85b3fd62ea1a	196	*/
NYX	0:85b3fd62ea1a	197
NYX	0:85b3fd62ea1a	198	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
NYX	0:85b3fd62ea1a	199	* @brief Flags defines which can be used with LL_DAC_ReadReg function
NYX	0:85b3fd62ea1a	200	* @{
NYX	0:85b3fd62ea1a	201	*/
NYX	0:85b3fd62ea1a	202	/* DAC channel 1 flags */
NYX	0:85b3fd62ea1a	203	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
NYX	0:85b3fd62ea1a	204
NYX	0:85b3fd62ea1a	205	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	206	/* DAC channel 2 flags */
NYX	0:85b3fd62ea1a	207	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
NYX	0:85b3fd62ea1a	208	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	209	/**
NYX	0:85b3fd62ea1a	210	* @}
NYX	0:85b3fd62ea1a	211	*/
NYX	0:85b3fd62ea1a	212
NYX	0:85b3fd62ea1a	213	/** @defgroup DAC_LL_EC_IT DAC interruptions
NYX	0:85b3fd62ea1a	214	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
NYX	0:85b3fd62ea1a	215	* @{
NYX	0:85b3fd62ea1a	216	*/
NYX	0:85b3fd62ea1a	217	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
NYX	0:85b3fd62ea1a	218	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	219	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
NYX	0:85b3fd62ea1a	220	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	221	/**
NYX	0:85b3fd62ea1a	222	* @}
NYX	0:85b3fd62ea1a	223	*/
NYX	0:85b3fd62ea1a	224
NYX	0:85b3fd62ea1a	225	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
NYX	0:85b3fd62ea1a	226	* @{
NYX	0:85b3fd62ea1a	227	*/
NYX	0:85b3fd62ea1a	228	#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
NYX	0:85b3fd62ea1a	229	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	230	#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
NYX	0:85b3fd62ea1a	231	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	232	/**
NYX	0:85b3fd62ea1a	233	* @}
NYX	0:85b3fd62ea1a	234	*/
NYX	0:85b3fd62ea1a	235
NYX	0:85b3fd62ea1a	236	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
NYX	0:85b3fd62ea1a	237	* @{
NYX	0:85b3fd62ea1a	238	*/
NYX	0:85b3fd62ea1a	239	#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger internal (SW start) /
NYX	0:85b3fd62ea1a	240	#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
NYX	0:85b3fd62ea1a	241	#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM8 TRGO. /
NYX	0:85b3fd62ea1a	242	#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
NYX	0:85b3fd62ea1a	243	#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
NYX	0:85b3fd62ea1a	244	#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
NYX	0:85b3fd62ea1a	245	#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM5 TRGO. /
NYX	0:85b3fd62ea1a	246	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
NYX	0:85b3fd62ea1a	247	/**
NYX	0:85b3fd62ea1a	248	* @}
NYX	0:85b3fd62ea1a	249	*/
NYX	0:85b3fd62ea1a	250
NYX	0:85b3fd62ea1a	251	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
NYX	0:85b3fd62ea1a	252	* @{
NYX	0:85b3fd62ea1a	253	*/
NYX	0:85b3fd62ea1a	254	#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /!< DAC channel wave auto generation mode disabled. /
NYX	0:85b3fd62ea1a	255	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
NYX	0:85b3fd62ea1a	256	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
NYX	0:85b3fd62ea1a	257	/**
NYX	0:85b3fd62ea1a	258	* @}
NYX	0:85b3fd62ea1a	259	*/
NYX	0:85b3fd62ea1a	260
NYX	0:85b3fd62ea1a	261	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
NYX	0:85b3fd62ea1a	262	* @{
NYX	0:85b3fd62ea1a	263	*/
NYX	0:85b3fd62ea1a	264	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
NYX	0:85b3fd62ea1a	265	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	266	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	267	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	268	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	269	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	270	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	271	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	272	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	273	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	274	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	275	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
NYX	0:85b3fd62ea1a	276	/**
NYX	0:85b3fd62ea1a	277	* @}
NYX	0:85b3fd62ea1a	278	*/
NYX	0:85b3fd62ea1a	279
NYX	0:85b3fd62ea1a	280	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
NYX	0:85b3fd62ea1a	281	* @{
NYX	0:85b3fd62ea1a	282	*/
NYX	0:85b3fd62ea1a	283	#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	284	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	285	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	286	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	287	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	288	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	289	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	290	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	291	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	292	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	293	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	294	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
NYX	0:85b3fd62ea1a	295	/**
NYX	0:85b3fd62ea1a	296	* @}
NYX	0:85b3fd62ea1a	297	*/
NYX	0:85b3fd62ea1a	298
NYX	0:85b3fd62ea1a	299	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
NYX	0:85b3fd62ea1a	300	* @{
NYX	0:85b3fd62ea1a	301	*/
NYX	0:85b3fd62ea1a	302	#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
NYX	0:85b3fd62ea1a	303	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
NYX	0:85b3fd62ea1a	304	/**
NYX	0:85b3fd62ea1a	305	* @}
NYX	0:85b3fd62ea1a	306	*/
NYX	0:85b3fd62ea1a	307
NYX	0:85b3fd62ea1a	308
NYX	0:85b3fd62ea1a	309	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
NYX	0:85b3fd62ea1a	310	* @{
NYX	0:85b3fd62ea1a	311	*/
NYX	0:85b3fd62ea1a	312	#define LL_DAC_RESOLUTION_12B 0x00000000U /!< DAC channel resolution 12 bits /
NYX	0:85b3fd62ea1a	313	#define LL_DAC_RESOLUTION_8B 0x00000002U /!< DAC channel resolution 8 bits /
NYX	0:85b3fd62ea1a	314	/**
NYX	0:85b3fd62ea1a	315	* @}
NYX	0:85b3fd62ea1a	316	*/
NYX	0:85b3fd62ea1a	317
NYX	0:85b3fd62ea1a	318	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
NYX	0:85b3fd62ea1a	319	* @{
NYX	0:85b3fd62ea1a	320	*/
NYX	0:85b3fd62ea1a	321	/* List of DAC registers intended to be used (most commonly) with */
NYX	0:85b3fd62ea1a	322	/* DMA transfer. */
NYX	0:85b3fd62ea1a	323	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
NYX	0:85b3fd62ea1a	324	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /!< DAC channel data holding register 12 bits right aligned /
NYX	0:85b3fd62ea1a	325	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /!< DAC channel data holding register 12 bits left aligned /
NYX	0:85b3fd62ea1a	326	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /!< DAC channel data holding register 8 bits right aligned /
NYX	0:85b3fd62ea1a	327	/**
NYX	0:85b3fd62ea1a	328	* @}
NYX	0:85b3fd62ea1a	329	*/
NYX	0:85b3fd62ea1a	330
NYX	0:85b3fd62ea1a	331	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
NYX	0:85b3fd62ea1a	332	* @note Only DAC IP HW delays are defined in DAC LL driver driver,
NYX	0:85b3fd62ea1a	333	* not timeout values.
NYX	0:85b3fd62ea1a	334	* For details on delays values, refer to descriptions in source code
NYX	0:85b3fd62ea1a	335	* above each literal definition.
NYX	0:85b3fd62ea1a	336	* @{
NYX	0:85b3fd62ea1a	337	*/
NYX	0:85b3fd62ea1a	338
NYX	0:85b3fd62ea1a	339	/* Delay for DAC channel voltage settling time from DAC channel startup */
NYX	0:85b3fd62ea1a	340	/* (transition from disable to enable). */
NYX	0:85b3fd62ea1a	341	/* Note: DAC channel startup time depends on board application environment: */
NYX	0:85b3fd62ea1a	342	/* impedance connected to DAC channel output. */
NYX	0:85b3fd62ea1a	343	/* The delay below is specified under conditions: */
NYX	0:85b3fd62ea1a	344	/* - voltage maximum transition (lowest to highest value) */
NYX	0:85b3fd62ea1a	345	/* - until voltage reaches final value +-1LSB */
NYX	0:85b3fd62ea1a	346	/* - DAC channel output buffer enabled */
NYX	0:85b3fd62ea1a	347	/* - load impedance of 5kOhm (min), 50pF (max) */
NYX	0:85b3fd62ea1a	348	/* Literal set to maximum value (refer to device datasheet, */
NYX	0:85b3fd62ea1a	349	/* parameter "tWAKEUP"). */
NYX	0:85b3fd62ea1a	350	/* Unit: us */
NYX	0:85b3fd62ea1a	351	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
NYX	0:85b3fd62ea1a	352
NYX	0:85b3fd62ea1a	353	/* Delay for DAC channel voltage settling time. */
NYX	0:85b3fd62ea1a	354	/* Note: DAC channel startup time depends on board application environment: */
NYX	0:85b3fd62ea1a	355	/* impedance connected to DAC channel output. */
NYX	0:85b3fd62ea1a	356	/* The delay below is specified under conditions: */
NYX	0:85b3fd62ea1a	357	/* - voltage maximum transition (lowest to highest value) */
NYX	0:85b3fd62ea1a	358	/* - until voltage reaches final value +-1LSB */
NYX	0:85b3fd62ea1a	359	/* - DAC channel output buffer enabled */
NYX	0:85b3fd62ea1a	360	/* - load impedance of 5kOhm min, 50pF max */
NYX	0:85b3fd62ea1a	361	/* Literal set to maximum value (refer to device datasheet, */
NYX	0:85b3fd62ea1a	362	/* parameter "tSETTLING"). */
NYX	0:85b3fd62ea1a	363	/* Unit: us */
NYX	0:85b3fd62ea1a	364	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /!< Delay for DAC channel voltage settling time /
NYX	0:85b3fd62ea1a	365	/**
NYX	0:85b3fd62ea1a	366	* @}
NYX	0:85b3fd62ea1a	367	*/
NYX	0:85b3fd62ea1a	368
NYX	0:85b3fd62ea1a	369	/**
NYX	0:85b3fd62ea1a	370	* @}
NYX	0:85b3fd62ea1a	371	*/
NYX	0:85b3fd62ea1a	372
NYX	0:85b3fd62ea1a	373	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	374	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
NYX	0:85b3fd62ea1a	375	* @{
NYX	0:85b3fd62ea1a	376	*/
NYX	0:85b3fd62ea1a	377
NYX	0:85b3fd62ea1a	378	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
NYX	0:85b3fd62ea1a	379	* @{
NYX	0:85b3fd62ea1a	380	*/
NYX	0:85b3fd62ea1a	381
NYX	0:85b3fd62ea1a	382	/**
NYX	0:85b3fd62ea1a	383	* @brief Write a value in DAC register
NYX	0:85b3fd62ea1a	384	* @param __INSTANCE__ DAC Instance
NYX	0:85b3fd62ea1a	385	* @param __REG__ Register to be written
NYX	0:85b3fd62ea1a	386	* @param __VALUE__ Value to be written in the register
NYX	0:85b3fd62ea1a	387	* @retval None
NYX	0:85b3fd62ea1a	388	*/
NYX	0:85b3fd62ea1a	389	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
NYX	0:85b3fd62ea1a	390
NYX	0:85b3fd62ea1a	391	/**
NYX	0:85b3fd62ea1a	392	* @brief Read a value in DAC register
NYX	0:85b3fd62ea1a	393	* @param __INSTANCE__ DAC Instance
NYX	0:85b3fd62ea1a	394	* @param __REG__ Register to be read
NYX	0:85b3fd62ea1a	395	* @retval Register value
NYX	0:85b3fd62ea1a	396	*/
NYX	0:85b3fd62ea1a	397	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
NYX	0:85b3fd62ea1a	398
NYX	0:85b3fd62ea1a	399	/**
NYX	0:85b3fd62ea1a	400	* @}
NYX	0:85b3fd62ea1a	401	*/
NYX	0:85b3fd62ea1a	402
NYX	0:85b3fd62ea1a	403	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
NYX	0:85b3fd62ea1a	404	* @{
NYX	0:85b3fd62ea1a	405	*/
NYX	0:85b3fd62ea1a	406
NYX	0:85b3fd62ea1a	407	/**
NYX	0:85b3fd62ea1a	408	* @brief Helper macro to get DAC channel number in decimal format
NYX	0:85b3fd62ea1a	409	* from literals LL_DAC_CHANNEL_x.
NYX	0:85b3fd62ea1a	410	* Example:
NYX	0:85b3fd62ea1a	411	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
NYX	0:85b3fd62ea1a	412	* will return decimal number "1".
NYX	0:85b3fd62ea1a	413	* @note The input can be a value from functions where a channel
NYX	0:85b3fd62ea1a	414	* number is returned.
NYX	0:85b3fd62ea1a	415	* @param __CHANNEL__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	416	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	417	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	418	*
NYX	0:85b3fd62ea1a	419	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	420	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	421	* @retval 1...2 (value "2" depending on DAC channel 2 availability)
NYX	0:85b3fd62ea1a	422	*/
NYX	0:85b3fd62ea1a	423	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
NYX	0:85b3fd62ea1a	424	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
NYX	0:85b3fd62ea1a	425
NYX	0:85b3fd62ea1a	426	/**
NYX	0:85b3fd62ea1a	427	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
NYX	0:85b3fd62ea1a	428	* from number in decimal format.
NYX	0:85b3fd62ea1a	429	* Example:
NYX	0:85b3fd62ea1a	430	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
NYX	0:85b3fd62ea1a	431	* will return a data equivalent to "LL_DAC_CHANNEL_1".
NYX	0:85b3fd62ea1a	432	* @note If the input parameter does not correspond to a DAC channel,
NYX	0:85b3fd62ea1a	433	* this macro returns value '0'.
NYX	0:85b3fd62ea1a	434	* @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
NYX	0:85b3fd62ea1a	435	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	436	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	437	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	438	*
NYX	0:85b3fd62ea1a	439	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	440	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	441	*/
NYX	0:85b3fd62ea1a	442	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	443	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
NYX	0:85b3fd62ea1a	444	(((__DECIMAL_NB__) == 1U) \
NYX	0:85b3fd62ea1a	445	? ( \
NYX	0:85b3fd62ea1a	446	LL_DAC_CHANNEL_1 \
NYX	0:85b3fd62ea1a	447	) \
NYX	0:85b3fd62ea1a	448	: \
NYX	0:85b3fd62ea1a	449	(((__DECIMAL_NB__) == 2U) \
NYX	0:85b3fd62ea1a	450	? ( \
NYX	0:85b3fd62ea1a	451	LL_DAC_CHANNEL_2 \
NYX	0:85b3fd62ea1a	452	) \
NYX	0:85b3fd62ea1a	453	: \
NYX	0:85b3fd62ea1a	454	( \
NYX	0:85b3fd62ea1a	455	0 \
NYX	0:85b3fd62ea1a	456	) \
NYX	0:85b3fd62ea1a	457	) \
NYX	0:85b3fd62ea1a	458	)
NYX	0:85b3fd62ea1a	459	#else
NYX	0:85b3fd62ea1a	460	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
NYX	0:85b3fd62ea1a	461	(((__DECIMAL_NB__) == 1U) \
NYX	0:85b3fd62ea1a	462	? ( \
NYX	0:85b3fd62ea1a	463	LL_DAC_CHANNEL_1 \
NYX	0:85b3fd62ea1a	464	) \
NYX	0:85b3fd62ea1a	465	: \
NYX	0:85b3fd62ea1a	466	( \
NYX	0:85b3fd62ea1a	467	0 \
NYX	0:85b3fd62ea1a	468	) \
NYX	0:85b3fd62ea1a	469	)
NYX	0:85b3fd62ea1a	470	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	471
NYX	0:85b3fd62ea1a	472	/**
NYX	0:85b3fd62ea1a	473	* @brief Helper macro to define the DAC conversion data full-scale digital
NYX	0:85b3fd62ea1a	474	* value corresponding to the selected DAC resolution.
NYX	0:85b3fd62ea1a	475	* @note DAC conversion data full-scale corresponds to voltage range
NYX	0:85b3fd62ea1a	476	* determined by analog voltage references Vref+ and Vref-
NYX	0:85b3fd62ea1a	477	* (refer to reference manual).
NYX	0:85b3fd62ea1a	478	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	479	* @arg @ref LL_DAC_RESOLUTION_12B
NYX	0:85b3fd62ea1a	480	* @arg @ref LL_DAC_RESOLUTION_8B
NYX	0:85b3fd62ea1a	481	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
NYX	0:85b3fd62ea1a	482	*/
NYX	0:85b3fd62ea1a	483	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
NYX	0:85b3fd62ea1a	484	((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
NYX	0:85b3fd62ea1a	485
NYX	0:85b3fd62ea1a	486	/**
NYX	0:85b3fd62ea1a	487	* @brief Helper macro to calculate the DAC conversion data (unit: digital
NYX	0:85b3fd62ea1a	488	* value) corresponding to a voltage (unit: mVolt).
NYX	0:85b3fd62ea1a	489	* @note This helper macro is intended to provide input data in voltage
NYX	0:85b3fd62ea1a	490	* rather than digital value,
NYX	0:85b3fd62ea1a	491	* to be used with LL DAC functions such as
NYX	0:85b3fd62ea1a	492	* @ref LL_DAC_ConvertData12RightAligned().
NYX	0:85b3fd62ea1a	493	* @note Analog reference voltage (Vref+) must be either known from
NYX	0:85b3fd62ea1a	494	* user board environment or can be calculated using ADC measurement
NYX	0:85b3fd62ea1a	495	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
NYX	0:85b3fd62ea1a	496	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
NYX	0:85b3fd62ea1a	497	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
NYX	0:85b3fd62ea1a	498	* (unit: mVolt).
NYX	0:85b3fd62ea1a	499	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	500	* @arg @ref LL_DAC_RESOLUTION_12B
NYX	0:85b3fd62ea1a	501	* @arg @ref LL_DAC_RESOLUTION_8B
NYX	0:85b3fd62ea1a	502	* @retval DAC conversion data (unit: digital value)
NYX	0:85b3fd62ea1a	503	*/
NYX	0:85b3fd62ea1a	504	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
NYX	0:85b3fd62ea1a	505	__DAC_VOLTAGE__,\
NYX	0:85b3fd62ea1a	506	__DAC_RESOLUTION__) \
NYX	0:85b3fd62ea1a	507	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
NYX	0:85b3fd62ea1a	508	/ (__VREFANALOG_VOLTAGE__) \
NYX	0:85b3fd62ea1a	509	)
NYX	0:85b3fd62ea1a	510
NYX	0:85b3fd62ea1a	511	/**
NYX	0:85b3fd62ea1a	512	* @}
NYX	0:85b3fd62ea1a	513	*/
NYX	0:85b3fd62ea1a	514
NYX	0:85b3fd62ea1a	515	/**
NYX	0:85b3fd62ea1a	516	* @}
NYX	0:85b3fd62ea1a	517	*/
NYX	0:85b3fd62ea1a	518
NYX	0:85b3fd62ea1a	519
NYX	0:85b3fd62ea1a	520	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	521	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
NYX	0:85b3fd62ea1a	522	* @{
NYX	0:85b3fd62ea1a	523	*/
NYX	0:85b3fd62ea1a	524	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
NYX	0:85b3fd62ea1a	525	* @{
NYX	0:85b3fd62ea1a	526	*/
NYX	0:85b3fd62ea1a	527
NYX	0:85b3fd62ea1a	528	/**
NYX	0:85b3fd62ea1a	529	* @brief Set the conversion trigger source for the selected DAC channel.
NYX	0:85b3fd62ea1a	530	* @note For conversion trigger source to be effective, DAC trigger
NYX	0:85b3fd62ea1a	531	* must be enabled using function @ref LL_DAC_EnableTrigger().
NYX	0:85b3fd62ea1a	532	* @note To set conversion trigger source, DAC channel must be disabled.
NYX	0:85b3fd62ea1a	533	* Otherwise, the setting is discarded.
NYX	0:85b3fd62ea1a	534	* @note Availability of parameters of trigger sources from timer
NYX	0:85b3fd62ea1a	535	* depends on timers availability on the selected device.
NYX	0:85b3fd62ea1a	536	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
NYX	0:85b3fd62ea1a	537	* CR TSEL2 LL_DAC_SetTriggerSource
NYX	0:85b3fd62ea1a	538	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	539	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	540	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	541	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	542	*
NYX	0:85b3fd62ea1a	543	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	544	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	545	* @param TriggerSource This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	546	* @arg @ref LL_DAC_TRIG_SOFTWARE
NYX	0:85b3fd62ea1a	547	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
NYX	0:85b3fd62ea1a	548	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
NYX	0:85b3fd62ea1a	549	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
NYX	0:85b3fd62ea1a	550	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
NYX	0:85b3fd62ea1a	551	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
NYX	0:85b3fd62ea1a	552	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
NYX	0:85b3fd62ea1a	553	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
NYX	0:85b3fd62ea1a	554	* @retval None
NYX	0:85b3fd62ea1a	555	*/
NYX	0:85b3fd62ea1a	556	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
NYX	0:85b3fd62ea1a	557	{
NYX	0:85b3fd62ea1a	558	MODIFY_REG(DACx->CR,
NYX	0:85b3fd62ea1a	559	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
NYX	0:85b3fd62ea1a	560	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	561	}
NYX	0:85b3fd62ea1a	562
NYX	0:85b3fd62ea1a	563	/**
NYX	0:85b3fd62ea1a	564	* @brief Get the conversion trigger source for the selected DAC channel.
NYX	0:85b3fd62ea1a	565	* @note For conversion trigger source to be effective, DAC trigger
NYX	0:85b3fd62ea1a	566	* must be enabled using function @ref LL_DAC_EnableTrigger().
NYX	0:85b3fd62ea1a	567	* @note Availability of parameters of trigger sources from timer
NYX	0:85b3fd62ea1a	568	* depends on timers availability on the selected device.
NYX	0:85b3fd62ea1a	569	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
NYX	0:85b3fd62ea1a	570	* CR TSEL2 LL_DAC_GetTriggerSource
NYX	0:85b3fd62ea1a	571	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	572	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	573	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	574	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	575	*
NYX	0:85b3fd62ea1a	576	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	577	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	578	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	579	* @arg @ref LL_DAC_TRIG_SOFTWARE
NYX	0:85b3fd62ea1a	580	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
NYX	0:85b3fd62ea1a	581	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
NYX	0:85b3fd62ea1a	582	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
NYX	0:85b3fd62ea1a	583	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
NYX	0:85b3fd62ea1a	584	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
NYX	0:85b3fd62ea1a	585	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
NYX	0:85b3fd62ea1a	586	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
NYX	0:85b3fd62ea1a	587	*/
NYX	0:85b3fd62ea1a	588	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	589	{
NYX	0:85b3fd62ea1a	590	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
NYX	0:85b3fd62ea1a	591	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
NYX	0:85b3fd62ea1a	592	);
NYX	0:85b3fd62ea1a	593	}
NYX	0:85b3fd62ea1a	594
NYX	0:85b3fd62ea1a	595	/**
NYX	0:85b3fd62ea1a	596	* @brief Set the waveform automatic generation mode
NYX	0:85b3fd62ea1a	597	* for the selected DAC channel.
NYX	0:85b3fd62ea1a	598	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
NYX	0:85b3fd62ea1a	599	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
NYX	0:85b3fd62ea1a	600	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	601	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	602	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	603	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	604	*
NYX	0:85b3fd62ea1a	605	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	606	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	607	* @param WaveAutoGeneration This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	608	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
NYX	0:85b3fd62ea1a	609	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
NYX	0:85b3fd62ea1a	610	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
NYX	0:85b3fd62ea1a	611	* @retval None
NYX	0:85b3fd62ea1a	612	*/
NYX	0:85b3fd62ea1a	613	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
NYX	0:85b3fd62ea1a	614	{
NYX	0:85b3fd62ea1a	615	MODIFY_REG(DACx->CR,
NYX	0:85b3fd62ea1a	616	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
NYX	0:85b3fd62ea1a	617	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	618	}
NYX	0:85b3fd62ea1a	619
NYX	0:85b3fd62ea1a	620	/**
NYX	0:85b3fd62ea1a	621	* @brief Get the waveform automatic generation mode
NYX	0:85b3fd62ea1a	622	* for the selected DAC channel.
NYX	0:85b3fd62ea1a	623	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
NYX	0:85b3fd62ea1a	624	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
NYX	0:85b3fd62ea1a	625	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	626	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	627	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	628	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	629	*
NYX	0:85b3fd62ea1a	630	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	631	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	632	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	633	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
NYX	0:85b3fd62ea1a	634	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
NYX	0:85b3fd62ea1a	635	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
NYX	0:85b3fd62ea1a	636	*/
NYX	0:85b3fd62ea1a	637	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	638	{
NYX	0:85b3fd62ea1a	639	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
NYX	0:85b3fd62ea1a	640	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
NYX	0:85b3fd62ea1a	641	);
NYX	0:85b3fd62ea1a	642	}
NYX	0:85b3fd62ea1a	643
NYX	0:85b3fd62ea1a	644	/**
NYX	0:85b3fd62ea1a	645	* @brief Set the noise waveform generation for the selected DAC channel:
NYX	0:85b3fd62ea1a	646	* Noise mode and parameters LFSR (linear feedback shift register).
NYX	0:85b3fd62ea1a	647	* @note For wave generation to be effective, DAC channel
NYX	0:85b3fd62ea1a	648	* wave generation mode must be enabled using
NYX	0:85b3fd62ea1a	649	* function @ref LL_DAC_SetWaveAutoGeneration().
NYX	0:85b3fd62ea1a	650	* @note This setting can be set when the selected DAC channel is disabled
NYX	0:85b3fd62ea1a	651	* (otherwise, the setting operation is ignored).
NYX	0:85b3fd62ea1a	652	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
NYX	0:85b3fd62ea1a	653	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
NYX	0:85b3fd62ea1a	654	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	655	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	656	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	657	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	658	*
NYX	0:85b3fd62ea1a	659	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	660	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	661	* @param NoiseLFSRMask This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	662	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
NYX	0:85b3fd62ea1a	663	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
NYX	0:85b3fd62ea1a	664	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
NYX	0:85b3fd62ea1a	665	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
NYX	0:85b3fd62ea1a	666	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
NYX	0:85b3fd62ea1a	667	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
NYX	0:85b3fd62ea1a	668	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
NYX	0:85b3fd62ea1a	669	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
NYX	0:85b3fd62ea1a	670	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
NYX	0:85b3fd62ea1a	671	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
NYX	0:85b3fd62ea1a	672	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
NYX	0:85b3fd62ea1a	673	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
NYX	0:85b3fd62ea1a	674	* @retval None
NYX	0:85b3fd62ea1a	675	*/
NYX	0:85b3fd62ea1a	676	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
NYX	0:85b3fd62ea1a	677	{
NYX	0:85b3fd62ea1a	678	MODIFY_REG(DACx->CR,
NYX	0:85b3fd62ea1a	679	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
NYX	0:85b3fd62ea1a	680	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	681	}
NYX	0:85b3fd62ea1a	682
NYX	0:85b3fd62ea1a	683	/**
NYX	0:85b3fd62ea1a	684	* @brief Set the noise waveform generation for the selected DAC channel:
NYX	0:85b3fd62ea1a	685	* Noise mode and parameters LFSR (linear feedback shift register).
NYX	0:85b3fd62ea1a	686	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
NYX	0:85b3fd62ea1a	687	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
NYX	0:85b3fd62ea1a	688	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	689	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	690	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	691	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	692	*
NYX	0:85b3fd62ea1a	693	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	694	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	695	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	696	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
NYX	0:85b3fd62ea1a	697	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
NYX	0:85b3fd62ea1a	698	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
NYX	0:85b3fd62ea1a	699	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
NYX	0:85b3fd62ea1a	700	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
NYX	0:85b3fd62ea1a	701	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
NYX	0:85b3fd62ea1a	702	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
NYX	0:85b3fd62ea1a	703	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
NYX	0:85b3fd62ea1a	704	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
NYX	0:85b3fd62ea1a	705	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
NYX	0:85b3fd62ea1a	706	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
NYX	0:85b3fd62ea1a	707	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
NYX	0:85b3fd62ea1a	708	*/
NYX	0:85b3fd62ea1a	709	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	710	{
NYX	0:85b3fd62ea1a	711	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
NYX	0:85b3fd62ea1a	712	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
NYX	0:85b3fd62ea1a	713	);
NYX	0:85b3fd62ea1a	714	}
NYX	0:85b3fd62ea1a	715
NYX	0:85b3fd62ea1a	716	/**
NYX	0:85b3fd62ea1a	717	* @brief Set the triangle waveform generation for the selected DAC channel:
NYX	0:85b3fd62ea1a	718	* triangle mode and amplitude.
NYX	0:85b3fd62ea1a	719	* @note For wave generation to be effective, DAC channel
NYX	0:85b3fd62ea1a	720	* wave generation mode must be enabled using
NYX	0:85b3fd62ea1a	721	* function @ref LL_DAC_SetWaveAutoGeneration().
NYX	0:85b3fd62ea1a	722	* @note This setting can be set when the selected DAC channel is disabled
NYX	0:85b3fd62ea1a	723	* (otherwise, the setting operation is ignored).
NYX	0:85b3fd62ea1a	724	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
NYX	0:85b3fd62ea1a	725	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
NYX	0:85b3fd62ea1a	726	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	727	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	728	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	729	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	730	*
NYX	0:85b3fd62ea1a	731	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	732	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	733	* @param TriangleAmplitude This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	734	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
NYX	0:85b3fd62ea1a	735	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
NYX	0:85b3fd62ea1a	736	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
NYX	0:85b3fd62ea1a	737	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
NYX	0:85b3fd62ea1a	738	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
NYX	0:85b3fd62ea1a	739	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
NYX	0:85b3fd62ea1a	740	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
NYX	0:85b3fd62ea1a	741	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
NYX	0:85b3fd62ea1a	742	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
NYX	0:85b3fd62ea1a	743	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
NYX	0:85b3fd62ea1a	744	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
NYX	0:85b3fd62ea1a	745	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
NYX	0:85b3fd62ea1a	746	* @retval None
NYX	0:85b3fd62ea1a	747	*/
NYX	0:85b3fd62ea1a	748	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
NYX	0:85b3fd62ea1a	749	{
NYX	0:85b3fd62ea1a	750	MODIFY_REG(DACx->CR,
NYX	0:85b3fd62ea1a	751	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
NYX	0:85b3fd62ea1a	752	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	753	}
NYX	0:85b3fd62ea1a	754
NYX	0:85b3fd62ea1a	755	/**
NYX	0:85b3fd62ea1a	756	* @brief Set the triangle waveform generation for the selected DAC channel:
NYX	0:85b3fd62ea1a	757	* triangle mode and amplitude.
NYX	0:85b3fd62ea1a	758	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
NYX	0:85b3fd62ea1a	759	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
NYX	0:85b3fd62ea1a	760	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	761	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	762	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	763	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	764	*
NYX	0:85b3fd62ea1a	765	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	766	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	767	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	768	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
NYX	0:85b3fd62ea1a	769	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
NYX	0:85b3fd62ea1a	770	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
NYX	0:85b3fd62ea1a	771	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
NYX	0:85b3fd62ea1a	772	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
NYX	0:85b3fd62ea1a	773	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
NYX	0:85b3fd62ea1a	774	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
NYX	0:85b3fd62ea1a	775	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
NYX	0:85b3fd62ea1a	776	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
NYX	0:85b3fd62ea1a	777	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
NYX	0:85b3fd62ea1a	778	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
NYX	0:85b3fd62ea1a	779	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
NYX	0:85b3fd62ea1a	780	*/
NYX	0:85b3fd62ea1a	781	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	782	{
NYX	0:85b3fd62ea1a	783	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
NYX	0:85b3fd62ea1a	784	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
NYX	0:85b3fd62ea1a	785	);
NYX	0:85b3fd62ea1a	786	}
NYX	0:85b3fd62ea1a	787
NYX	0:85b3fd62ea1a	788	/**
NYX	0:85b3fd62ea1a	789	* @brief Set the output buffer for the selected DAC channel.
NYX	0:85b3fd62ea1a	790	* @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
NYX	0:85b3fd62ea1a	791	* CR BOFF2 LL_DAC_SetOutputBuffer
NYX	0:85b3fd62ea1a	792	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	793	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	794	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	795	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	796	*
NYX	0:85b3fd62ea1a	797	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	798	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	799	* @param OutputBuffer This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	800	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
NYX	0:85b3fd62ea1a	801	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
NYX	0:85b3fd62ea1a	802	* @retval None
NYX	0:85b3fd62ea1a	803	*/
NYX	0:85b3fd62ea1a	804	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
NYX	0:85b3fd62ea1a	805	{
NYX	0:85b3fd62ea1a	806	MODIFY_REG(DACx->CR,
NYX	0:85b3fd62ea1a	807	DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
NYX	0:85b3fd62ea1a	808	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	809	}
NYX	0:85b3fd62ea1a	810
NYX	0:85b3fd62ea1a	811	/**
NYX	0:85b3fd62ea1a	812	* @brief Get the output buffer state for the selected DAC channel.
NYX	0:85b3fd62ea1a	813	* @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
NYX	0:85b3fd62ea1a	814	* CR BOFF2 LL_DAC_GetOutputBuffer
NYX	0:85b3fd62ea1a	815	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	816	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	817	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	818	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	819	*
NYX	0:85b3fd62ea1a	820	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	821	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	822	* @retval Returned value can be one of the following values:
NYX	0:85b3fd62ea1a	823	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
NYX	0:85b3fd62ea1a	824	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
NYX	0:85b3fd62ea1a	825	*/
NYX	0:85b3fd62ea1a	826	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	827	{
NYX	0:85b3fd62ea1a	828	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
NYX	0:85b3fd62ea1a	829	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
NYX	0:85b3fd62ea1a	830	);
NYX	0:85b3fd62ea1a	831	}
NYX	0:85b3fd62ea1a	832
NYX	0:85b3fd62ea1a	833	/**
NYX	0:85b3fd62ea1a	834	* @}
NYX	0:85b3fd62ea1a	835	*/
NYX	0:85b3fd62ea1a	836
NYX	0:85b3fd62ea1a	837	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
NYX	0:85b3fd62ea1a	838	* @{
NYX	0:85b3fd62ea1a	839	*/
NYX	0:85b3fd62ea1a	840
NYX	0:85b3fd62ea1a	841	/**
NYX	0:85b3fd62ea1a	842	* @brief Enable DAC DMA transfer request of the selected channel.
NYX	0:85b3fd62ea1a	843	* @note To configure DMA source address (peripheral address),
NYX	0:85b3fd62ea1a	844	* use function @ref LL_DAC_DMA_GetRegAddr().
NYX	0:85b3fd62ea1a	845	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
NYX	0:85b3fd62ea1a	846	* CR DMAEN2 LL_DAC_EnableDMAReq
NYX	0:85b3fd62ea1a	847	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	848	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	849	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	850	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	851	*
NYX	0:85b3fd62ea1a	852	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	853	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	854	* @retval None
NYX	0:85b3fd62ea1a	855	*/
NYX	0:85b3fd62ea1a	856	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	857	{
NYX	0:85b3fd62ea1a	858	SET_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	859	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	860	}
NYX	0:85b3fd62ea1a	861
NYX	0:85b3fd62ea1a	862	/**
NYX	0:85b3fd62ea1a	863	* @brief Disable DAC DMA transfer request of the selected channel.
NYX	0:85b3fd62ea1a	864	* @note To configure DMA source address (peripheral address),
NYX	0:85b3fd62ea1a	865	* use function @ref LL_DAC_DMA_GetRegAddr().
NYX	0:85b3fd62ea1a	866	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
NYX	0:85b3fd62ea1a	867	* CR DMAEN2 LL_DAC_DisableDMAReq
NYX	0:85b3fd62ea1a	868	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	869	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	870	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	871	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	872	*
NYX	0:85b3fd62ea1a	873	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	874	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	875	* @retval None
NYX	0:85b3fd62ea1a	876	*/
NYX	0:85b3fd62ea1a	877	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	878	{
NYX	0:85b3fd62ea1a	879	CLEAR_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	880	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	881	}
NYX	0:85b3fd62ea1a	882
NYX	0:85b3fd62ea1a	883	/**
NYX	0:85b3fd62ea1a	884	* @brief Get DAC DMA transfer request state of the selected channel.
NYX	0:85b3fd62ea1a	885	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
NYX	0:85b3fd62ea1a	886	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
NYX	0:85b3fd62ea1a	887	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
NYX	0:85b3fd62ea1a	888	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	889	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	890	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	891	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	892	*
NYX	0:85b3fd62ea1a	893	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	894	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	895	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	896	*/
NYX	0:85b3fd62ea1a	897	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	898	{
NYX	0:85b3fd62ea1a	899	return (READ_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	900	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
NYX	0:85b3fd62ea1a	901	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
NYX	0:85b3fd62ea1a	902	}
NYX	0:85b3fd62ea1a	903
NYX	0:85b3fd62ea1a	904	/**
NYX	0:85b3fd62ea1a	905	* @brief Function to help to configure DMA transfer to DAC: retrieve the
NYX	0:85b3fd62ea1a	906	* DAC register address from DAC instance and a list of DAC registers
NYX	0:85b3fd62ea1a	907	* intended to be used (most commonly) with DMA transfer.
NYX	0:85b3fd62ea1a	908	* @note These DAC registers are data holding registers:
NYX	0:85b3fd62ea1a	909	* when DAC conversion is requested, DAC generates a DMA transfer
NYX	0:85b3fd62ea1a	910	* request to have data available in DAC data holding registers.
NYX	0:85b3fd62ea1a	911	* @note This macro is intended to be used with LL DMA driver, refer to
NYX	0:85b3fd62ea1a	912	* function "LL_DMA_ConfigAddresses()".
NYX	0:85b3fd62ea1a	913	* Example:
NYX	0:85b3fd62ea1a	914	* LL_DMA_ConfigAddresses(DMA1,
NYX	0:85b3fd62ea1a	915	* LL_DMA_CHANNEL_1,
NYX	0:85b3fd62ea1a	916	* (uint32_t)&< array or variable >,
NYX	0:85b3fd62ea1a	917	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
NYX	0:85b3fd62ea1a	918	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
NYX	0:85b3fd62ea1a	919	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
NYX	0:85b3fd62ea1a	920	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
NYX	0:85b3fd62ea1a	921	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
NYX	0:85b3fd62ea1a	922	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
NYX	0:85b3fd62ea1a	923	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
NYX	0:85b3fd62ea1a	924	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
NYX	0:85b3fd62ea1a	925	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	926	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	927	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	928	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	929	*
NYX	0:85b3fd62ea1a	930	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	931	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	932	* @param Register This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	933	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
NYX	0:85b3fd62ea1a	934	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
NYX	0:85b3fd62ea1a	935	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
NYX	0:85b3fd62ea1a	936	* @retval DAC register address
NYX	0:85b3fd62ea1a	937	*/
NYX	0:85b3fd62ea1a	938	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
NYX	0:85b3fd62ea1a	939	{
NYX	0:85b3fd62ea1a	940	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
NYX	0:85b3fd62ea1a	941	/* DAC channel selected. */
NYX	0:85b3fd62ea1a	942	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
NYX	0:85b3fd62ea1a	943	}
NYX	0:85b3fd62ea1a	944	/**
NYX	0:85b3fd62ea1a	945	* @}
NYX	0:85b3fd62ea1a	946	*/
NYX	0:85b3fd62ea1a	947
NYX	0:85b3fd62ea1a	948	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
NYX	0:85b3fd62ea1a	949	* @{
NYX	0:85b3fd62ea1a	950	*/
NYX	0:85b3fd62ea1a	951
NYX	0:85b3fd62ea1a	952	/**
NYX	0:85b3fd62ea1a	953	* @brief Enable DAC selected channel.
NYX	0:85b3fd62ea1a	954	* @rmtoll CR EN1 LL_DAC_Enable\n
NYX	0:85b3fd62ea1a	955	* CR EN2 LL_DAC_Enable
NYX	0:85b3fd62ea1a	956	* @note After enable from off state, DAC channel requires a delay
NYX	0:85b3fd62ea1a	957	* for output voltage to reach accuracy +/- 1 LSB.
NYX	0:85b3fd62ea1a	958	* Refer to device datasheet, parameter "tWAKEUP".
NYX	0:85b3fd62ea1a	959	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	960	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	961	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	962	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	963	*
NYX	0:85b3fd62ea1a	964	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	965	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	966	* @retval None
NYX	0:85b3fd62ea1a	967	*/
NYX	0:85b3fd62ea1a	968	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	969	{
NYX	0:85b3fd62ea1a	970	SET_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	971	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	972	}
NYX	0:85b3fd62ea1a	973
NYX	0:85b3fd62ea1a	974	/**
NYX	0:85b3fd62ea1a	975	* @brief Disable DAC selected channel.
NYX	0:85b3fd62ea1a	976	* @rmtoll CR EN1 LL_DAC_Disable\n
NYX	0:85b3fd62ea1a	977	* CR EN2 LL_DAC_Disable
NYX	0:85b3fd62ea1a	978	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	979	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	980	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	981	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	982	*
NYX	0:85b3fd62ea1a	983	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	984	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	985	* @retval None
NYX	0:85b3fd62ea1a	986	*/
NYX	0:85b3fd62ea1a	987	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	988	{
NYX	0:85b3fd62ea1a	989	CLEAR_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	990	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	991	}
NYX	0:85b3fd62ea1a	992
NYX	0:85b3fd62ea1a	993	/**
NYX	0:85b3fd62ea1a	994	* @brief Get DAC enable state of the selected channel.
NYX	0:85b3fd62ea1a	995	* (0: DAC channel is disabled, 1: DAC channel is enabled)
NYX	0:85b3fd62ea1a	996	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
NYX	0:85b3fd62ea1a	997	* CR EN2 LL_DAC_IsEnabled
NYX	0:85b3fd62ea1a	998	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	999	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1000	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1001	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1002	*
NYX	0:85b3fd62ea1a	1003	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1004	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1005	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1006	*/
NYX	0:85b3fd62ea1a	1007	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	1008	{
NYX	0:85b3fd62ea1a	1009	return (READ_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	1010	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
NYX	0:85b3fd62ea1a	1011	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
NYX	0:85b3fd62ea1a	1012	}
NYX	0:85b3fd62ea1a	1013
NYX	0:85b3fd62ea1a	1014	/**
NYX	0:85b3fd62ea1a	1015	* @brief Enable DAC trigger of the selected channel.
NYX	0:85b3fd62ea1a	1016	* @note - If DAC trigger is disabled, DAC conversion is performed
NYX	0:85b3fd62ea1a	1017	* automatically once the data holding register is updated,
NYX	0:85b3fd62ea1a	1018	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
NYX	0:85b3fd62ea1a	1019	* @ref LL_DAC_ConvertData12RightAligned(), ...
NYX	0:85b3fd62ea1a	1020	* - If DAC trigger is enabled, DAC conversion is performed
NYX	0:85b3fd62ea1a	1021	* only when a hardware of software trigger event is occurring.
NYX	0:85b3fd62ea1a	1022	* Select trigger source using
NYX	0:85b3fd62ea1a	1023	* function @ref LL_DAC_SetTriggerSource().
NYX	0:85b3fd62ea1a	1024	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
NYX	0:85b3fd62ea1a	1025	* CR TEN2 LL_DAC_EnableTrigger
NYX	0:85b3fd62ea1a	1026	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1027	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1028	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1029	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1030	*
NYX	0:85b3fd62ea1a	1031	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1032	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1033	* @retval None
NYX	0:85b3fd62ea1a	1034	*/
NYX	0:85b3fd62ea1a	1035	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	1036	{
NYX	0:85b3fd62ea1a	1037	SET_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	1038	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	1039	}
NYX	0:85b3fd62ea1a	1040
NYX	0:85b3fd62ea1a	1041	/**
NYX	0:85b3fd62ea1a	1042	* @brief Disable DAC trigger of the selected channel.
NYX	0:85b3fd62ea1a	1043	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
NYX	0:85b3fd62ea1a	1044	* CR TEN2 LL_DAC_DisableTrigger
NYX	0:85b3fd62ea1a	1045	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1046	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1047	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1048	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1049	*
NYX	0:85b3fd62ea1a	1050	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1051	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1052	* @retval None
NYX	0:85b3fd62ea1a	1053	*/
NYX	0:85b3fd62ea1a	1054	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	1055	{
NYX	0:85b3fd62ea1a	1056	CLEAR_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	1057	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
NYX	0:85b3fd62ea1a	1058	}
NYX	0:85b3fd62ea1a	1059
NYX	0:85b3fd62ea1a	1060	/**
NYX	0:85b3fd62ea1a	1061	* @brief Get DAC trigger state of the selected channel.
NYX	0:85b3fd62ea1a	1062	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
NYX	0:85b3fd62ea1a	1063	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
NYX	0:85b3fd62ea1a	1064	* CR TEN2 LL_DAC_IsTriggerEnabled
NYX	0:85b3fd62ea1a	1065	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1066	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1067	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1068	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1069	*
NYX	0:85b3fd62ea1a	1070	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1071	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1072	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1073	*/
NYX	0:85b3fd62ea1a	1074	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	1075	{
NYX	0:85b3fd62ea1a	1076	return (READ_BIT(DACx->CR,
NYX	0:85b3fd62ea1a	1077	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
NYX	0:85b3fd62ea1a	1078	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
NYX	0:85b3fd62ea1a	1079	}
NYX	0:85b3fd62ea1a	1080
NYX	0:85b3fd62ea1a	1081	/**
NYX	0:85b3fd62ea1a	1082	* @brief Trig DAC conversion by software for the selected DAC channel.
NYX	0:85b3fd62ea1a	1083	* @note Preliminarily, DAC trigger must be set to software trigger
NYX	0:85b3fd62ea1a	1084	* using function @ref LL_DAC_SetTriggerSource()
NYX	0:85b3fd62ea1a	1085	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
NYX	0:85b3fd62ea1a	1086	* and DAC trigger must be enabled using
NYX	0:85b3fd62ea1a	1087	* function @ref LL_DAC_EnableTrigger().
NYX	0:85b3fd62ea1a	1088	* @note For devices featuring DAC with 2 channels: this function
NYX	0:85b3fd62ea1a	1089	* can perform a SW start of both DAC channels simultaneously.
NYX	0:85b3fd62ea1a	1090	* Two channels can be selected as parameter.
NYX	0:85b3fd62ea1a	1091	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
NYX	0:85b3fd62ea1a	1092	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
NYX	0:85b3fd62ea1a	1093	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
NYX	0:85b3fd62ea1a	1094	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1095	* @param DAC_Channel This parameter can a combination of the following values:
NYX	0:85b3fd62ea1a	1096	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1097	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1098	*
NYX	0:85b3fd62ea1a	1099	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1100	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1101	* @retval None
NYX	0:85b3fd62ea1a	1102	*/
NYX	0:85b3fd62ea1a	1103	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	1104	{
NYX	0:85b3fd62ea1a	1105	SET_BIT(DACx->SWTRIGR,
NYX	0:85b3fd62ea1a	1106	(DAC_Channel & DAC_SWTR_CHX_MASK));
NYX	0:85b3fd62ea1a	1107	}
NYX	0:85b3fd62ea1a	1108
NYX	0:85b3fd62ea1a	1109	/**
NYX	0:85b3fd62ea1a	1110	* @brief Set the data to be loaded in the data holding register
NYX	0:85b3fd62ea1a	1111	* in format 12 bits left alignment (LSB aligned on bit 0),
NYX	0:85b3fd62ea1a	1112	* for the selected DAC channel.
NYX	0:85b3fd62ea1a	1113	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
NYX	0:85b3fd62ea1a	1114	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
NYX	0:85b3fd62ea1a	1115	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1116	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1117	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1118	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1119	*
NYX	0:85b3fd62ea1a	1120	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1121	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1122	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
NYX	0:85b3fd62ea1a	1123	* @retval None
NYX	0:85b3fd62ea1a	1124	*/
NYX	0:85b3fd62ea1a	1125	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
NYX	0:85b3fd62ea1a	1126	{
NYX	0:85b3fd62ea1a	1127	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
NYX	0:85b3fd62ea1a	1128
NYX	0:85b3fd62ea1a	1129	MODIFY_REG(*preg,
NYX	0:85b3fd62ea1a	1130	DAC_DHR12R1_DACC1DHR,
NYX	0:85b3fd62ea1a	1131	Data);
NYX	0:85b3fd62ea1a	1132	}
NYX	0:85b3fd62ea1a	1133
NYX	0:85b3fd62ea1a	1134	/**
NYX	0:85b3fd62ea1a	1135	* @brief Set the data to be loaded in the data holding register
NYX	0:85b3fd62ea1a	1136	* in format 12 bits left alignment (MSB aligned on bit 15),
NYX	0:85b3fd62ea1a	1137	* for the selected DAC channel.
NYX	0:85b3fd62ea1a	1138	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
NYX	0:85b3fd62ea1a	1139	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
NYX	0:85b3fd62ea1a	1140	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1141	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1142	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1143	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1144	*
NYX	0:85b3fd62ea1a	1145	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1146	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1147	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
NYX	0:85b3fd62ea1a	1148	* @retval None
NYX	0:85b3fd62ea1a	1149	*/
NYX	0:85b3fd62ea1a	1150	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
NYX	0:85b3fd62ea1a	1151	{
NYX	0:85b3fd62ea1a	1152	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
NYX	0:85b3fd62ea1a	1153
NYX	0:85b3fd62ea1a	1154	MODIFY_REG(*preg,
NYX	0:85b3fd62ea1a	1155	DAC_DHR12L1_DACC1DHR,
NYX	0:85b3fd62ea1a	1156	Data);
NYX	0:85b3fd62ea1a	1157	}
NYX	0:85b3fd62ea1a	1158
NYX	0:85b3fd62ea1a	1159	/**
NYX	0:85b3fd62ea1a	1160	* @brief Set the data to be loaded in the data holding register
NYX	0:85b3fd62ea1a	1161	* in format 8 bits left alignment (LSB aligned on bit 0),
NYX	0:85b3fd62ea1a	1162	* for the selected DAC channel.
NYX	0:85b3fd62ea1a	1163	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
NYX	0:85b3fd62ea1a	1164	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
NYX	0:85b3fd62ea1a	1165	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1166	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1167	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1168	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1169	*
NYX	0:85b3fd62ea1a	1170	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1171	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1172	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
NYX	0:85b3fd62ea1a	1173	* @retval None
NYX	0:85b3fd62ea1a	1174	*/
NYX	0:85b3fd62ea1a	1175	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
NYX	0:85b3fd62ea1a	1176	{
NYX	0:85b3fd62ea1a	1177	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
NYX	0:85b3fd62ea1a	1178
NYX	0:85b3fd62ea1a	1179	MODIFY_REG(*preg,
NYX	0:85b3fd62ea1a	1180	DAC_DHR8R1_DACC1DHR,
NYX	0:85b3fd62ea1a	1181	Data);
NYX	0:85b3fd62ea1a	1182	}
NYX	0:85b3fd62ea1a	1183
NYX	0:85b3fd62ea1a	1184	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	1185	/**
NYX	0:85b3fd62ea1a	1186	* @brief Set the data to be loaded in the data holding register
NYX	0:85b3fd62ea1a	1187	* in format 12 bits left alignment (LSB aligned on bit 0),
NYX	0:85b3fd62ea1a	1188	* for both DAC channels.
NYX	0:85b3fd62ea1a	1189	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
NYX	0:85b3fd62ea1a	1190	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
NYX	0:85b3fd62ea1a	1191	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1192	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
NYX	0:85b3fd62ea1a	1193	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
NYX	0:85b3fd62ea1a	1194	* @retval None
NYX	0:85b3fd62ea1a	1195	*/
NYX	0:85b3fd62ea1a	1196	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
NYX	0:85b3fd62ea1a	1197	{
NYX	0:85b3fd62ea1a	1198	MODIFY_REG(DACx->DHR12RD,
NYX	0:85b3fd62ea1a	1199	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
NYX	0:85b3fd62ea1a	1200	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
NYX	0:85b3fd62ea1a	1201	}
NYX	0:85b3fd62ea1a	1202
NYX	0:85b3fd62ea1a	1203	/**
NYX	0:85b3fd62ea1a	1204	* @brief Set the data to be loaded in the data holding register
NYX	0:85b3fd62ea1a	1205	* in format 12 bits left alignment (MSB aligned on bit 15),
NYX	0:85b3fd62ea1a	1206	* for both DAC channels.
NYX	0:85b3fd62ea1a	1207	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
NYX	0:85b3fd62ea1a	1208	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
NYX	0:85b3fd62ea1a	1209	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1210	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
NYX	0:85b3fd62ea1a	1211	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
NYX	0:85b3fd62ea1a	1212	* @retval None
NYX	0:85b3fd62ea1a	1213	*/
NYX	0:85b3fd62ea1a	1214	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
NYX	0:85b3fd62ea1a	1215	{
NYX	0:85b3fd62ea1a	1216	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
NYX	0:85b3fd62ea1a	1217	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
NYX	0:85b3fd62ea1a	1218	/* the 4 LSB must be taken into account for the shift value. */
NYX	0:85b3fd62ea1a	1219	MODIFY_REG(DACx->DHR12LD,
NYX	0:85b3fd62ea1a	1220	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
NYX	0:85b3fd62ea1a	1221	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
NYX	0:85b3fd62ea1a	1222	}
NYX	0:85b3fd62ea1a	1223
NYX	0:85b3fd62ea1a	1224	/**
NYX	0:85b3fd62ea1a	1225	* @brief Set the data to be loaded in the data holding register
NYX	0:85b3fd62ea1a	1226	* in format 8 bits left alignment (LSB aligned on bit 0),
NYX	0:85b3fd62ea1a	1227	* for both DAC channels.
NYX	0:85b3fd62ea1a	1228	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
NYX	0:85b3fd62ea1a	1229	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
NYX	0:85b3fd62ea1a	1230	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1231	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
NYX	0:85b3fd62ea1a	1232	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
NYX	0:85b3fd62ea1a	1233	* @retval None
NYX	0:85b3fd62ea1a	1234	*/
NYX	0:85b3fd62ea1a	1235	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
NYX	0:85b3fd62ea1a	1236	{
NYX	0:85b3fd62ea1a	1237	MODIFY_REG(DACx->DHR8RD,
NYX	0:85b3fd62ea1a	1238	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
NYX	0:85b3fd62ea1a	1239	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
NYX	0:85b3fd62ea1a	1240	}
NYX	0:85b3fd62ea1a	1241
NYX	0:85b3fd62ea1a	1242	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	1243	/**
NYX	0:85b3fd62ea1a	1244	* @brief Retrieve output data currently generated for the selected DAC channel.
NYX	0:85b3fd62ea1a	1245	* @note Whatever alignment and resolution settings
NYX	0:85b3fd62ea1a	1246	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
NYX	0:85b3fd62ea1a	1247	* @ref LL_DAC_ConvertData12RightAligned(), ...),
NYX	0:85b3fd62ea1a	1248	* output data format is 12 bits right aligned (LSB aligned on bit 0).
NYX	0:85b3fd62ea1a	1249	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
NYX	0:85b3fd62ea1a	1250	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
NYX	0:85b3fd62ea1a	1251	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1252	* @param DAC_Channel This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1253	* @arg @ref LL_DAC_CHANNEL_1
NYX	0:85b3fd62ea1a	1254	* @arg @ref LL_DAC_CHANNEL_2 (1)
NYX	0:85b3fd62ea1a	1255	*
NYX	0:85b3fd62ea1a	1256	* (1) On this STM32 serie, parameter not available on all devices.
NYX	0:85b3fd62ea1a	1257	* Refer to device datasheet for channels availability.
NYX	0:85b3fd62ea1a	1258	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
NYX	0:85b3fd62ea1a	1259	*/
NYX	0:85b3fd62ea1a	1260	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
NYX	0:85b3fd62ea1a	1261	{
NYX	0:85b3fd62ea1a	1262	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
NYX	0:85b3fd62ea1a	1263
NYX	0:85b3fd62ea1a	1264	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
NYX	0:85b3fd62ea1a	1265	}
NYX	0:85b3fd62ea1a	1266
NYX	0:85b3fd62ea1a	1267	/**
NYX	0:85b3fd62ea1a	1268	* @}
NYX	0:85b3fd62ea1a	1269	*/
NYX	0:85b3fd62ea1a	1270
NYX	0:85b3fd62ea1a	1271	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
NYX	0:85b3fd62ea1a	1272	* @{
NYX	0:85b3fd62ea1a	1273	*/
NYX	0:85b3fd62ea1a	1274	/**
NYX	0:85b3fd62ea1a	1275	* @brief Get DAC underrun flag for DAC channel 1
NYX	0:85b3fd62ea1a	1276	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
NYX	0:85b3fd62ea1a	1277	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1278	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1279	*/
NYX	0:85b3fd62ea1a	1280	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1281	{
NYX	0:85b3fd62ea1a	1282	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
NYX	0:85b3fd62ea1a	1283	}
NYX	0:85b3fd62ea1a	1284
NYX	0:85b3fd62ea1a	1285	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	1286	/**
NYX	0:85b3fd62ea1a	1287	* @brief Get DAC underrun flag for DAC channel 2
NYX	0:85b3fd62ea1a	1288	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
NYX	0:85b3fd62ea1a	1289	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1290	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1291	*/
NYX	0:85b3fd62ea1a	1292	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1293	{
NYX	0:85b3fd62ea1a	1294	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
NYX	0:85b3fd62ea1a	1295	}
NYX	0:85b3fd62ea1a	1296	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	1297
NYX	0:85b3fd62ea1a	1298	/**
NYX	0:85b3fd62ea1a	1299	* @brief Clear DAC underrun flag for DAC channel 1
NYX	0:85b3fd62ea1a	1300	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
NYX	0:85b3fd62ea1a	1301	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1302	* @retval None
NYX	0:85b3fd62ea1a	1303	*/
NYX	0:85b3fd62ea1a	1304	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1305	{
NYX	0:85b3fd62ea1a	1306	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
NYX	0:85b3fd62ea1a	1307	}
NYX	0:85b3fd62ea1a	1308
NYX	0:85b3fd62ea1a	1309	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	1310	/**
NYX	0:85b3fd62ea1a	1311	* @brief Clear DAC underrun flag for DAC channel 2
NYX	0:85b3fd62ea1a	1312	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
NYX	0:85b3fd62ea1a	1313	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1314	* @retval None
NYX	0:85b3fd62ea1a	1315	*/
NYX	0:85b3fd62ea1a	1316	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1317	{
NYX	0:85b3fd62ea1a	1318	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
NYX	0:85b3fd62ea1a	1319	}
NYX	0:85b3fd62ea1a	1320	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	1321
NYX	0:85b3fd62ea1a	1322	/**
NYX	0:85b3fd62ea1a	1323	* @}
NYX	0:85b3fd62ea1a	1324	*/
NYX	0:85b3fd62ea1a	1325
NYX	0:85b3fd62ea1a	1326	/** @defgroup DAC_LL_EF_IT_Management IT management
NYX	0:85b3fd62ea1a	1327	* @{
NYX	0:85b3fd62ea1a	1328	*/
NYX	0:85b3fd62ea1a	1329
NYX	0:85b3fd62ea1a	1330	/**
NYX	0:85b3fd62ea1a	1331	* @brief Enable DMA underrun interrupt for DAC channel 1
NYX	0:85b3fd62ea1a	1332	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
NYX	0:85b3fd62ea1a	1333	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1334	* @retval None
NYX	0:85b3fd62ea1a	1335	*/
NYX	0:85b3fd62ea1a	1336	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1337	{
NYX	0:85b3fd62ea1a	1338	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
NYX	0:85b3fd62ea1a	1339	}
NYX	0:85b3fd62ea1a	1340
NYX	0:85b3fd62ea1a	1341	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	1342	/**
NYX	0:85b3fd62ea1a	1343	* @brief Enable DMA underrun interrupt for DAC channel 2
NYX	0:85b3fd62ea1a	1344	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
NYX	0:85b3fd62ea1a	1345	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1346	* @retval None
NYX	0:85b3fd62ea1a	1347	*/
NYX	0:85b3fd62ea1a	1348	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1349	{
NYX	0:85b3fd62ea1a	1350	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
NYX	0:85b3fd62ea1a	1351	}
NYX	0:85b3fd62ea1a	1352	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	1353
NYX	0:85b3fd62ea1a	1354	/**
NYX	0:85b3fd62ea1a	1355	* @brief Disable DMA underrun interrupt for DAC channel 1
NYX	0:85b3fd62ea1a	1356	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
NYX	0:85b3fd62ea1a	1357	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1358	* @retval None
NYX	0:85b3fd62ea1a	1359	*/
NYX	0:85b3fd62ea1a	1360	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1361	{
NYX	0:85b3fd62ea1a	1362	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
NYX	0:85b3fd62ea1a	1363	}
NYX	0:85b3fd62ea1a	1364
NYX	0:85b3fd62ea1a	1365	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	1366	/**
NYX	0:85b3fd62ea1a	1367	* @brief Disable DMA underrun interrupt for DAC channel 2
NYX	0:85b3fd62ea1a	1368	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
NYX	0:85b3fd62ea1a	1369	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1370	* @retval None
NYX	0:85b3fd62ea1a	1371	*/
NYX	0:85b3fd62ea1a	1372	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1373	{
NYX	0:85b3fd62ea1a	1374	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
NYX	0:85b3fd62ea1a	1375	}
NYX	0:85b3fd62ea1a	1376	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	1377
NYX	0:85b3fd62ea1a	1378	/**
NYX	0:85b3fd62ea1a	1379	* @brief Get DMA underrun interrupt for DAC channel 1
NYX	0:85b3fd62ea1a	1380	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
NYX	0:85b3fd62ea1a	1381	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1382	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1383	*/
NYX	0:85b3fd62ea1a	1384	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1385	{
NYX	0:85b3fd62ea1a	1386	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
NYX	0:85b3fd62ea1a	1387	}
NYX	0:85b3fd62ea1a	1388
NYX	0:85b3fd62ea1a	1389	#if defined(DAC_CHANNEL2_SUPPORT)
NYX	0:85b3fd62ea1a	1390	/**
NYX	0:85b3fd62ea1a	1391	* @brief Get DMA underrun interrupt for DAC channel 2
NYX	0:85b3fd62ea1a	1392	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
NYX	0:85b3fd62ea1a	1393	* @param DACx DAC instance
NYX	0:85b3fd62ea1a	1394	* @retval State of bit (1 or 0).
NYX	0:85b3fd62ea1a	1395	*/
NYX	0:85b3fd62ea1a	1396	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
NYX	0:85b3fd62ea1a	1397	{
NYX	0:85b3fd62ea1a	1398	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
NYX	0:85b3fd62ea1a	1399	}
NYX	0:85b3fd62ea1a	1400	#endif /* DAC_CHANNEL2_SUPPORT */
NYX	0:85b3fd62ea1a	1401
NYX	0:85b3fd62ea1a	1402	/**
NYX	0:85b3fd62ea1a	1403	* @}
NYX	0:85b3fd62ea1a	1404	*/
NYX	0:85b3fd62ea1a	1405
NYX	0:85b3fd62ea1a	1406	#if defined(USE_FULL_LL_DRIVER)
NYX	0:85b3fd62ea1a	1407	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
NYX	0:85b3fd62ea1a	1408	* @{
NYX	0:85b3fd62ea1a	1409	*/
NYX	0:85b3fd62ea1a	1410
NYX	0:85b3fd62ea1a	1411	ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
NYX	0:85b3fd62ea1a	1412	ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
NYX	0:85b3fd62ea1a	1413	void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
NYX	0:85b3fd62ea1a	1414
NYX	0:85b3fd62ea1a	1415	/**
NYX	0:85b3fd62ea1a	1416	* @}
NYX	0:85b3fd62ea1a	1417	*/
NYX	0:85b3fd62ea1a	1418	#endif /* USE_FULL_LL_DRIVER */
NYX	0:85b3fd62ea1a	1419
NYX	0:85b3fd62ea1a	1420	/**
NYX	0:85b3fd62ea1a	1421	* @}
NYX	0:85b3fd62ea1a	1422	*/
NYX	0:85b3fd62ea1a	1423
NYX	0:85b3fd62ea1a	1424	/**
NYX	0:85b3fd62ea1a	1425	* @}
NYX	0:85b3fd62ea1a	1426	*/
NYX	0:85b3fd62ea1a	1427
NYX	0:85b3fd62ea1a	1428	#endif /* DAC */
NYX	0:85b3fd62ea1a	1429
NYX	0:85b3fd62ea1a	1430	/**
NYX	0:85b3fd62ea1a	1431	* @}
NYX	0:85b3fd62ea1a	1432	*/
NYX	0:85b3fd62ea1a	1433
NYX	0:85b3fd62ea1a	1434	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	1435	}
NYX	0:85b3fd62ea1a	1436	#endif
NYX	0:85b3fd62ea1a	1437
NYX	0:85b3fd62ea1a	1438	#endif /* __STM32F4xx_LL_DAC_H */
NYX	0:85b3fd62ea1a	1439
NYX	0:85b3fd62ea1a	1440	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
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Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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