Takaaki Numai / mbed-dev

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Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_cortex.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of CORTEX LL module.
NYX 0:85b3fd62ea1a 8 @verbatim
NYX 0:85b3fd62ea1a 9 ==============================================================================
NYX 0:85b3fd62ea1a 10 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 11 ==============================================================================
NYX 0:85b3fd62ea1a 12 [..]
NYX 0:85b3fd62ea1a 13 The LL CORTEX driver contains a set of generic APIs that can be
NYX 0:85b3fd62ea1a 14 used by user:
NYX 0:85b3fd62ea1a 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
NYX 0:85b3fd62ea1a 16 functions
NYX 0:85b3fd62ea1a 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
NYX 0:85b3fd62ea1a 18 (+) MPU API to configure and enable regions
NYX 0:85b3fd62ea1a 19 (MPU services provided only on some devices)
NYX 0:85b3fd62ea1a 20 (+) API to access to MCU info (CPUID register)
NYX 0:85b3fd62ea1a 21 (+) API to enable fault handler (SHCSR accesses)
NYX 0:85b3fd62ea1a 22
NYX 0:85b3fd62ea1a 23 @endverbatim
NYX 0:85b3fd62ea1a 24 ******************************************************************************
NYX 0:85b3fd62ea1a 25 * @attention
NYX 0:85b3fd62ea1a 26 *
NYX 0:85b3fd62ea1a 27 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 28 *
NYX 0:85b3fd62ea1a 29 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 30 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 31 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 32 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 33 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 34 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 35 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 37 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 38 * without specific prior written permission.
NYX 0:85b3fd62ea1a 39 *
NYX 0:85b3fd62ea1a 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 50 *
NYX 0:85b3fd62ea1a 51 ******************************************************************************
NYX 0:85b3fd62ea1a 52 */
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 55 #ifndef __STM32F4xx_LL_CORTEX_H
NYX 0:85b3fd62ea1a 56 #define __STM32F4xx_LL_CORTEX_H
NYX 0:85b3fd62ea1a 57
NYX 0:85b3fd62ea1a 58 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 59 extern "C" {
NYX 0:85b3fd62ea1a 60 #endif
NYX 0:85b3fd62ea1a 61
NYX 0:85b3fd62ea1a 62 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 63 #include "stm32f4xx.h"
NYX 0:85b3fd62ea1a 64
NYX 0:85b3fd62ea1a 65 /** @addtogroup STM32F4xx_LL_Driver
NYX 0:85b3fd62ea1a 66 * @{
NYX 0:85b3fd62ea1a 67 */
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 /** @defgroup CORTEX_LL CORTEX
NYX 0:85b3fd62ea1a 70 * @{
NYX 0:85b3fd62ea1a 71 */
NYX 0:85b3fd62ea1a 72
NYX 0:85b3fd62ea1a 73 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 74 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 75
NYX 0:85b3fd62ea1a 76 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 77
NYX 0:85b3fd62ea1a 78 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 79
NYX 0:85b3fd62ea1a 80 /* Exported types ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 81 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 82 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
NYX 0:85b3fd62ea1a 83 * @{
NYX 0:85b3fd62ea1a 84 */
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
NYX 0:85b3fd62ea1a 87 * @{
NYX 0:85b3fd62ea1a 88 */
NYX 0:85b3fd62ea1a 89 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
NYX 0:85b3fd62ea1a 90 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
NYX 0:85b3fd62ea1a 91 /**
NYX 0:85b3fd62ea1a 92 * @}
NYX 0:85b3fd62ea1a 93 */
NYX 0:85b3fd62ea1a 94
NYX 0:85b3fd62ea1a 95 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
NYX 0:85b3fd62ea1a 96 * @{
NYX 0:85b3fd62ea1a 97 */
NYX 0:85b3fd62ea1a 98 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
NYX 0:85b3fd62ea1a 99 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
NYX 0:85b3fd62ea1a 100 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
NYX 0:85b3fd62ea1a 101 /**
NYX 0:85b3fd62ea1a 102 * @}
NYX 0:85b3fd62ea1a 103 */
NYX 0:85b3fd62ea1a 104
NYX 0:85b3fd62ea1a 105 #if __MPU_PRESENT
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
NYX 0:85b3fd62ea1a 108 * @{
NYX 0:85b3fd62ea1a 109 */
NYX 0:85b3fd62ea1a 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
NYX 0:85b3fd62ea1a 111 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
NYX 0:85b3fd62ea1a 112 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
NYX 0:85b3fd62ea1a 113 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
NYX 0:85b3fd62ea1a 114 /**
NYX 0:85b3fd62ea1a 115 * @}
NYX 0:85b3fd62ea1a 116 */
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
NYX 0:85b3fd62ea1a 119 * @{
NYX 0:85b3fd62ea1a 120 */
NYX 0:85b3fd62ea1a 121 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
NYX 0:85b3fd62ea1a 122 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
NYX 0:85b3fd62ea1a 123 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
NYX 0:85b3fd62ea1a 124 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
NYX 0:85b3fd62ea1a 125 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
NYX 0:85b3fd62ea1a 126 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
NYX 0:85b3fd62ea1a 127 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
NYX 0:85b3fd62ea1a 128 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
NYX 0:85b3fd62ea1a 129 /**
NYX 0:85b3fd62ea1a 130 * @}
NYX 0:85b3fd62ea1a 131 */
NYX 0:85b3fd62ea1a 132
NYX 0:85b3fd62ea1a 133 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
NYX 0:85b3fd62ea1a 134 * @{
NYX 0:85b3fd62ea1a 135 */
NYX 0:85b3fd62ea1a 136 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
NYX 0:85b3fd62ea1a 137 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
NYX 0:85b3fd62ea1a 138 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
NYX 0:85b3fd62ea1a 139 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
NYX 0:85b3fd62ea1a 140 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
NYX 0:85b3fd62ea1a 141 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 142 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 143 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 144 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 145 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 146 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 147 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 148 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 149 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 150 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 151 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 152 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 153 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 154 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 155 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 156 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 157 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 158 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 159 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 160 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 161 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 162 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 163 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
NYX 0:85b3fd62ea1a 164 /**
NYX 0:85b3fd62ea1a 165 * @}
NYX 0:85b3fd62ea1a 166 */
NYX 0:85b3fd62ea1a 167
NYX 0:85b3fd62ea1a 168 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
NYX 0:85b3fd62ea1a 169 * @{
NYX 0:85b3fd62ea1a 170 */
NYX 0:85b3fd62ea1a 171 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
NYX 0:85b3fd62ea1a 172 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
NYX 0:85b3fd62ea1a 173 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
NYX 0:85b3fd62ea1a 174 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
NYX 0:85b3fd62ea1a 175 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
NYX 0:85b3fd62ea1a 176 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
NYX 0:85b3fd62ea1a 177 /**
NYX 0:85b3fd62ea1a 178 * @}
NYX 0:85b3fd62ea1a 179 */
NYX 0:85b3fd62ea1a 180
NYX 0:85b3fd62ea1a 181 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
NYX 0:85b3fd62ea1a 182 * @{
NYX 0:85b3fd62ea1a 183 */
NYX 0:85b3fd62ea1a 184 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
NYX 0:85b3fd62ea1a 185 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
NYX 0:85b3fd62ea1a 186 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
NYX 0:85b3fd62ea1a 187 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
NYX 0:85b3fd62ea1a 188 /**
NYX 0:85b3fd62ea1a 189 * @}
NYX 0:85b3fd62ea1a 190 */
NYX 0:85b3fd62ea1a 191
NYX 0:85b3fd62ea1a 192 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
NYX 0:85b3fd62ea1a 193 * @{
NYX 0:85b3fd62ea1a 194 */
NYX 0:85b3fd62ea1a 195 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
NYX 0:85b3fd62ea1a 196 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
NYX 0:85b3fd62ea1a 197 /**
NYX 0:85b3fd62ea1a 198 * @}
NYX 0:85b3fd62ea1a 199 */
NYX 0:85b3fd62ea1a 200
NYX 0:85b3fd62ea1a 201 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
NYX 0:85b3fd62ea1a 202 * @{
NYX 0:85b3fd62ea1a 203 */
NYX 0:85b3fd62ea1a 204 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
NYX 0:85b3fd62ea1a 205 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
NYX 0:85b3fd62ea1a 206 /**
NYX 0:85b3fd62ea1a 207 * @}
NYX 0:85b3fd62ea1a 208 */
NYX 0:85b3fd62ea1a 209
NYX 0:85b3fd62ea1a 210 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
NYX 0:85b3fd62ea1a 211 * @{
NYX 0:85b3fd62ea1a 212 */
NYX 0:85b3fd62ea1a 213 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
NYX 0:85b3fd62ea1a 214 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
NYX 0:85b3fd62ea1a 215 /**
NYX 0:85b3fd62ea1a 216 * @}
NYX 0:85b3fd62ea1a 217 */
NYX 0:85b3fd62ea1a 218
NYX 0:85b3fd62ea1a 219 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
NYX 0:85b3fd62ea1a 220 * @{
NYX 0:85b3fd62ea1a 221 */
NYX 0:85b3fd62ea1a 222 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
NYX 0:85b3fd62ea1a 223 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
NYX 0:85b3fd62ea1a 224 /**
NYX 0:85b3fd62ea1a 225 * @}
NYX 0:85b3fd62ea1a 226 */
NYX 0:85b3fd62ea1a 227 #endif /* __MPU_PRESENT */
NYX 0:85b3fd62ea1a 228 /**
NYX 0:85b3fd62ea1a 229 * @}
NYX 0:85b3fd62ea1a 230 */
NYX 0:85b3fd62ea1a 231
NYX 0:85b3fd62ea1a 232 /* Exported macro ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 233
NYX 0:85b3fd62ea1a 234 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 235 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
NYX 0:85b3fd62ea1a 236 * @{
NYX 0:85b3fd62ea1a 237 */
NYX 0:85b3fd62ea1a 238
NYX 0:85b3fd62ea1a 239 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
NYX 0:85b3fd62ea1a 240 * @{
NYX 0:85b3fd62ea1a 241 */
NYX 0:85b3fd62ea1a 242
NYX 0:85b3fd62ea1a 243 /**
NYX 0:85b3fd62ea1a 244 * @brief This function checks if the Systick counter flag is active or not.
NYX 0:85b3fd62ea1a 245 * @note It can be used in timeout function on application side.
NYX 0:85b3fd62ea1a 246 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
NYX 0:85b3fd62ea1a 247 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 248 */
NYX 0:85b3fd62ea1a 249 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
NYX 0:85b3fd62ea1a 250 {
NYX 0:85b3fd62ea1a 251 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
NYX 0:85b3fd62ea1a 252 }
NYX 0:85b3fd62ea1a 253
NYX 0:85b3fd62ea1a 254 /**
NYX 0:85b3fd62ea1a 255 * @brief Configures the SysTick clock source
NYX 0:85b3fd62ea1a 256 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
NYX 0:85b3fd62ea1a 257 * @param Source This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
NYX 0:85b3fd62ea1a 259 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
NYX 0:85b3fd62ea1a 260 * @retval None
NYX 0:85b3fd62ea1a 261 */
NYX 0:85b3fd62ea1a 262 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
NYX 0:85b3fd62ea1a 263 {
NYX 0:85b3fd62ea1a 264 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
NYX 0:85b3fd62ea1a 265 {
NYX 0:85b3fd62ea1a 266 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
NYX 0:85b3fd62ea1a 267 }
NYX 0:85b3fd62ea1a 268 else
NYX 0:85b3fd62ea1a 269 {
NYX 0:85b3fd62ea1a 270 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
NYX 0:85b3fd62ea1a 271 }
NYX 0:85b3fd62ea1a 272 }
NYX 0:85b3fd62ea1a 273
NYX 0:85b3fd62ea1a 274 /**
NYX 0:85b3fd62ea1a 275 * @brief Get the SysTick clock source
NYX 0:85b3fd62ea1a 276 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
NYX 0:85b3fd62ea1a 277 * @retval Returned value can be one of the following values:
NYX 0:85b3fd62ea1a 278 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
NYX 0:85b3fd62ea1a 279 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
NYX 0:85b3fd62ea1a 280 */
NYX 0:85b3fd62ea1a 281 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
NYX 0:85b3fd62ea1a 282 {
NYX 0:85b3fd62ea1a 283 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
NYX 0:85b3fd62ea1a 284 }
NYX 0:85b3fd62ea1a 285
NYX 0:85b3fd62ea1a 286 /**
NYX 0:85b3fd62ea1a 287 * @brief Enable SysTick exception request
NYX 0:85b3fd62ea1a 288 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
NYX 0:85b3fd62ea1a 289 * @retval None
NYX 0:85b3fd62ea1a 290 */
NYX 0:85b3fd62ea1a 291 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
NYX 0:85b3fd62ea1a 292 {
NYX 0:85b3fd62ea1a 293 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
NYX 0:85b3fd62ea1a 294 }
NYX 0:85b3fd62ea1a 295
NYX 0:85b3fd62ea1a 296 /**
NYX 0:85b3fd62ea1a 297 * @brief Disable SysTick exception request
NYX 0:85b3fd62ea1a 298 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
NYX 0:85b3fd62ea1a 299 * @retval None
NYX 0:85b3fd62ea1a 300 */
NYX 0:85b3fd62ea1a 301 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
NYX 0:85b3fd62ea1a 302 {
NYX 0:85b3fd62ea1a 303 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
NYX 0:85b3fd62ea1a 304 }
NYX 0:85b3fd62ea1a 305
NYX 0:85b3fd62ea1a 306 /**
NYX 0:85b3fd62ea1a 307 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
NYX 0:85b3fd62ea1a 308 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
NYX 0:85b3fd62ea1a 309 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 310 */
NYX 0:85b3fd62ea1a 311 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
NYX 0:85b3fd62ea1a 312 {
NYX 0:85b3fd62ea1a 313 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
NYX 0:85b3fd62ea1a 314 }
NYX 0:85b3fd62ea1a 315
NYX 0:85b3fd62ea1a 316 /**
NYX 0:85b3fd62ea1a 317 * @}
NYX 0:85b3fd62ea1a 318 */
NYX 0:85b3fd62ea1a 319
NYX 0:85b3fd62ea1a 320 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
NYX 0:85b3fd62ea1a 321 * @{
NYX 0:85b3fd62ea1a 322 */
NYX 0:85b3fd62ea1a 323
NYX 0:85b3fd62ea1a 324 /**
NYX 0:85b3fd62ea1a 325 * @brief Processor uses sleep as its low power mode
NYX 0:85b3fd62ea1a 326 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
NYX 0:85b3fd62ea1a 327 * @retval None
NYX 0:85b3fd62ea1a 328 */
NYX 0:85b3fd62ea1a 329 __STATIC_INLINE void LL_LPM_EnableSleep(void)
NYX 0:85b3fd62ea1a 330 {
NYX 0:85b3fd62ea1a 331 /* Clear SLEEPDEEP bit of Cortex System Control Register */
NYX 0:85b3fd62ea1a 332 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
NYX 0:85b3fd62ea1a 333 }
NYX 0:85b3fd62ea1a 334
NYX 0:85b3fd62ea1a 335 /**
NYX 0:85b3fd62ea1a 336 * @brief Processor uses deep sleep as its low power mode
NYX 0:85b3fd62ea1a 337 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
NYX 0:85b3fd62ea1a 338 * @retval None
NYX 0:85b3fd62ea1a 339 */
NYX 0:85b3fd62ea1a 340 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
NYX 0:85b3fd62ea1a 341 {
NYX 0:85b3fd62ea1a 342 /* Set SLEEPDEEP bit of Cortex System Control Register */
NYX 0:85b3fd62ea1a 343 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
NYX 0:85b3fd62ea1a 344 }
NYX 0:85b3fd62ea1a 345
NYX 0:85b3fd62ea1a 346 /**
NYX 0:85b3fd62ea1a 347 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
NYX 0:85b3fd62ea1a 348 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
NYX 0:85b3fd62ea1a 349 * empty main application.
NYX 0:85b3fd62ea1a 350 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
NYX 0:85b3fd62ea1a 351 * @retval None
NYX 0:85b3fd62ea1a 352 */
NYX 0:85b3fd62ea1a 353 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
NYX 0:85b3fd62ea1a 354 {
NYX 0:85b3fd62ea1a 355 /* Set SLEEPONEXIT bit of Cortex System Control Register */
NYX 0:85b3fd62ea1a 356 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
NYX 0:85b3fd62ea1a 357 }
NYX 0:85b3fd62ea1a 358
NYX 0:85b3fd62ea1a 359 /**
NYX 0:85b3fd62ea1a 360 * @brief Do not sleep when returning to Thread mode.
NYX 0:85b3fd62ea1a 361 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
NYX 0:85b3fd62ea1a 362 * @retval None
NYX 0:85b3fd62ea1a 363 */
NYX 0:85b3fd62ea1a 364 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
NYX 0:85b3fd62ea1a 365 {
NYX 0:85b3fd62ea1a 366 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
NYX 0:85b3fd62ea1a 367 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
NYX 0:85b3fd62ea1a 368 }
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 /**
NYX 0:85b3fd62ea1a 371 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
NYX 0:85b3fd62ea1a 372 * processor.
NYX 0:85b3fd62ea1a 373 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
NYX 0:85b3fd62ea1a 374 * @retval None
NYX 0:85b3fd62ea1a 375 */
NYX 0:85b3fd62ea1a 376 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
NYX 0:85b3fd62ea1a 377 {
NYX 0:85b3fd62ea1a 378 /* Set SEVEONPEND bit of Cortex System Control Register */
NYX 0:85b3fd62ea1a 379 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
NYX 0:85b3fd62ea1a 380 }
NYX 0:85b3fd62ea1a 381
NYX 0:85b3fd62ea1a 382 /**
NYX 0:85b3fd62ea1a 383 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
NYX 0:85b3fd62ea1a 384 * excluded
NYX 0:85b3fd62ea1a 385 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
NYX 0:85b3fd62ea1a 386 * @retval None
NYX 0:85b3fd62ea1a 387 */
NYX 0:85b3fd62ea1a 388 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
NYX 0:85b3fd62ea1a 389 {
NYX 0:85b3fd62ea1a 390 /* Clear SEVEONPEND bit of Cortex System Control Register */
NYX 0:85b3fd62ea1a 391 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
NYX 0:85b3fd62ea1a 392 }
NYX 0:85b3fd62ea1a 393
NYX 0:85b3fd62ea1a 394 /**
NYX 0:85b3fd62ea1a 395 * @}
NYX 0:85b3fd62ea1a 396 */
NYX 0:85b3fd62ea1a 397
NYX 0:85b3fd62ea1a 398 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
NYX 0:85b3fd62ea1a 399 * @{
NYX 0:85b3fd62ea1a 400 */
NYX 0:85b3fd62ea1a 401
NYX 0:85b3fd62ea1a 402 /**
NYX 0:85b3fd62ea1a 403 * @brief Enable a fault in System handler control register (SHCSR)
NYX 0:85b3fd62ea1a 404 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
NYX 0:85b3fd62ea1a 405 * @param Fault This parameter can be a combination of the following values:
NYX 0:85b3fd62ea1a 406 * @arg @ref LL_HANDLER_FAULT_USG
NYX 0:85b3fd62ea1a 407 * @arg @ref LL_HANDLER_FAULT_BUS
NYX 0:85b3fd62ea1a 408 * @arg @ref LL_HANDLER_FAULT_MEM
NYX 0:85b3fd62ea1a 409 * @retval None
NYX 0:85b3fd62ea1a 410 */
NYX 0:85b3fd62ea1a 411 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
NYX 0:85b3fd62ea1a 412 {
NYX 0:85b3fd62ea1a 413 /* Enable the system handler fault */
NYX 0:85b3fd62ea1a 414 SET_BIT(SCB->SHCSR, Fault);
NYX 0:85b3fd62ea1a 415 }
NYX 0:85b3fd62ea1a 416
NYX 0:85b3fd62ea1a 417 /**
NYX 0:85b3fd62ea1a 418 * @brief Disable a fault in System handler control register (SHCSR)
NYX 0:85b3fd62ea1a 419 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
NYX 0:85b3fd62ea1a 420 * @param Fault This parameter can be a combination of the following values:
NYX 0:85b3fd62ea1a 421 * @arg @ref LL_HANDLER_FAULT_USG
NYX 0:85b3fd62ea1a 422 * @arg @ref LL_HANDLER_FAULT_BUS
NYX 0:85b3fd62ea1a 423 * @arg @ref LL_HANDLER_FAULT_MEM
NYX 0:85b3fd62ea1a 424 * @retval None
NYX 0:85b3fd62ea1a 425 */
NYX 0:85b3fd62ea1a 426 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
NYX 0:85b3fd62ea1a 427 {
NYX 0:85b3fd62ea1a 428 /* Disable the system handler fault */
NYX 0:85b3fd62ea1a 429 CLEAR_BIT(SCB->SHCSR, Fault);
NYX 0:85b3fd62ea1a 430 }
NYX 0:85b3fd62ea1a 431
NYX 0:85b3fd62ea1a 432 /**
NYX 0:85b3fd62ea1a 433 * @}
NYX 0:85b3fd62ea1a 434 */
NYX 0:85b3fd62ea1a 435
NYX 0:85b3fd62ea1a 436 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
NYX 0:85b3fd62ea1a 437 * @{
NYX 0:85b3fd62ea1a 438 */
NYX 0:85b3fd62ea1a 439
NYX 0:85b3fd62ea1a 440 /**
NYX 0:85b3fd62ea1a 441 * @brief Get Implementer code
NYX 0:85b3fd62ea1a 442 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
NYX 0:85b3fd62ea1a 443 * @retval Value should be equal to 0x41 for ARM
NYX 0:85b3fd62ea1a 444 */
NYX 0:85b3fd62ea1a 445 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
NYX 0:85b3fd62ea1a 446 {
NYX 0:85b3fd62ea1a 447 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
NYX 0:85b3fd62ea1a 448 }
NYX 0:85b3fd62ea1a 449
NYX 0:85b3fd62ea1a 450 /**
NYX 0:85b3fd62ea1a 451 * @brief Get Variant number (The r value in the rnpn product revision identifier)
NYX 0:85b3fd62ea1a 452 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
NYX 0:85b3fd62ea1a 453 * @retval Value between 0 and 255 (0x0: revision 0)
NYX 0:85b3fd62ea1a 454 */
NYX 0:85b3fd62ea1a 455 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
NYX 0:85b3fd62ea1a 456 {
NYX 0:85b3fd62ea1a 457 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
NYX 0:85b3fd62ea1a 458 }
NYX 0:85b3fd62ea1a 459
NYX 0:85b3fd62ea1a 460 /**
NYX 0:85b3fd62ea1a 461 * @brief Get Constant number
NYX 0:85b3fd62ea1a 462 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
NYX 0:85b3fd62ea1a 463 * @retval Value should be equal to 0xF for Cortex-M4 devices
NYX 0:85b3fd62ea1a 464 */
NYX 0:85b3fd62ea1a 465 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
NYX 0:85b3fd62ea1a 466 {
NYX 0:85b3fd62ea1a 467 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
NYX 0:85b3fd62ea1a 468 }
NYX 0:85b3fd62ea1a 469
NYX 0:85b3fd62ea1a 470 /**
NYX 0:85b3fd62ea1a 471 * @brief Get Part number
NYX 0:85b3fd62ea1a 472 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
NYX 0:85b3fd62ea1a 473 * @retval Value should be equal to 0xC24 for Cortex-M4
NYX 0:85b3fd62ea1a 474 */
NYX 0:85b3fd62ea1a 475 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
NYX 0:85b3fd62ea1a 476 {
NYX 0:85b3fd62ea1a 477 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
NYX 0:85b3fd62ea1a 478 }
NYX 0:85b3fd62ea1a 479
NYX 0:85b3fd62ea1a 480 /**
NYX 0:85b3fd62ea1a 481 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
NYX 0:85b3fd62ea1a 482 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
NYX 0:85b3fd62ea1a 483 * @retval Value between 0 and 255 (0x1: patch 1)
NYX 0:85b3fd62ea1a 484 */
NYX 0:85b3fd62ea1a 485 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
NYX 0:85b3fd62ea1a 486 {
NYX 0:85b3fd62ea1a 487 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
NYX 0:85b3fd62ea1a 488 }
NYX 0:85b3fd62ea1a 489
NYX 0:85b3fd62ea1a 490 /**
NYX 0:85b3fd62ea1a 491 * @}
NYX 0:85b3fd62ea1a 492 */
NYX 0:85b3fd62ea1a 493
NYX 0:85b3fd62ea1a 494 #if __MPU_PRESENT
NYX 0:85b3fd62ea1a 495 /** @defgroup CORTEX_LL_EF_MPU MPU
NYX 0:85b3fd62ea1a 496 * @{
NYX 0:85b3fd62ea1a 497 */
NYX 0:85b3fd62ea1a 498
NYX 0:85b3fd62ea1a 499 /**
NYX 0:85b3fd62ea1a 500 * @brief Enable MPU with input options
NYX 0:85b3fd62ea1a 501 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
NYX 0:85b3fd62ea1a 502 * @param Options This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
NYX 0:85b3fd62ea1a 504 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
NYX 0:85b3fd62ea1a 505 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
NYX 0:85b3fd62ea1a 506 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
NYX 0:85b3fd62ea1a 507 * @retval None
NYX 0:85b3fd62ea1a 508 */
NYX 0:85b3fd62ea1a 509 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
NYX 0:85b3fd62ea1a 510 {
NYX 0:85b3fd62ea1a 511 /* Enable the MPU*/
NYX 0:85b3fd62ea1a 512 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
NYX 0:85b3fd62ea1a 513 /* Ensure MPU settings take effects */
NYX 0:85b3fd62ea1a 514 __DSB();
NYX 0:85b3fd62ea1a 515 /* Sequence instruction fetches using update settings */
NYX 0:85b3fd62ea1a 516 __ISB();
NYX 0:85b3fd62ea1a 517 }
NYX 0:85b3fd62ea1a 518
NYX 0:85b3fd62ea1a 519 /**
NYX 0:85b3fd62ea1a 520 * @brief Disable MPU
NYX 0:85b3fd62ea1a 521 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
NYX 0:85b3fd62ea1a 522 * @retval None
NYX 0:85b3fd62ea1a 523 */
NYX 0:85b3fd62ea1a 524 __STATIC_INLINE void LL_MPU_Disable(void)
NYX 0:85b3fd62ea1a 525 {
NYX 0:85b3fd62ea1a 526 /* Make sure outstanding transfers are done */
NYX 0:85b3fd62ea1a 527 __DMB();
NYX 0:85b3fd62ea1a 528 /* Disable MPU*/
NYX 0:85b3fd62ea1a 529 WRITE_REG(MPU->CTRL, 0U);
NYX 0:85b3fd62ea1a 530 }
NYX 0:85b3fd62ea1a 531
NYX 0:85b3fd62ea1a 532 /**
NYX 0:85b3fd62ea1a 533 * @brief Check if MPU is enabled or not
NYX 0:85b3fd62ea1a 534 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
NYX 0:85b3fd62ea1a 535 * @retval State of bit (1 or 0).
NYX 0:85b3fd62ea1a 536 */
NYX 0:85b3fd62ea1a 537 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
NYX 0:85b3fd62ea1a 538 {
NYX 0:85b3fd62ea1a 539 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
NYX 0:85b3fd62ea1a 540 }
NYX 0:85b3fd62ea1a 541
NYX 0:85b3fd62ea1a 542 /**
NYX 0:85b3fd62ea1a 543 * @brief Enable a MPU region
NYX 0:85b3fd62ea1a 544 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
NYX 0:85b3fd62ea1a 545 * @param Region This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 546 * @arg @ref LL_MPU_REGION_NUMBER0
NYX 0:85b3fd62ea1a 547 * @arg @ref LL_MPU_REGION_NUMBER1
NYX 0:85b3fd62ea1a 548 * @arg @ref LL_MPU_REGION_NUMBER2
NYX 0:85b3fd62ea1a 549 * @arg @ref LL_MPU_REGION_NUMBER3
NYX 0:85b3fd62ea1a 550 * @arg @ref LL_MPU_REGION_NUMBER4
NYX 0:85b3fd62ea1a 551 * @arg @ref LL_MPU_REGION_NUMBER5
NYX 0:85b3fd62ea1a 552 * @arg @ref LL_MPU_REGION_NUMBER6
NYX 0:85b3fd62ea1a 553 * @arg @ref LL_MPU_REGION_NUMBER7
NYX 0:85b3fd62ea1a 554 * @retval None
NYX 0:85b3fd62ea1a 555 */
NYX 0:85b3fd62ea1a 556 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
NYX 0:85b3fd62ea1a 557 {
NYX 0:85b3fd62ea1a 558 /* Set Region number */
NYX 0:85b3fd62ea1a 559 WRITE_REG(MPU->RNR, Region);
NYX 0:85b3fd62ea1a 560 /* Enable the MPU region */
NYX 0:85b3fd62ea1a 561 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
NYX 0:85b3fd62ea1a 562 }
NYX 0:85b3fd62ea1a 563
NYX 0:85b3fd62ea1a 564 /**
NYX 0:85b3fd62ea1a 565 * @brief Configure and enable a region
NYX 0:85b3fd62ea1a 566 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
NYX 0:85b3fd62ea1a 567 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
NYX 0:85b3fd62ea1a 568 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
NYX 0:85b3fd62ea1a 569 * MPU_RASR XN LL_MPU_ConfigRegion\n
NYX 0:85b3fd62ea1a 570 * MPU_RASR AP LL_MPU_ConfigRegion\n
NYX 0:85b3fd62ea1a 571 * MPU_RASR S LL_MPU_ConfigRegion\n
NYX 0:85b3fd62ea1a 572 * MPU_RASR C LL_MPU_ConfigRegion\n
NYX 0:85b3fd62ea1a 573 * MPU_RASR B LL_MPU_ConfigRegion\n
NYX 0:85b3fd62ea1a 574 * MPU_RASR SIZE LL_MPU_ConfigRegion
NYX 0:85b3fd62ea1a 575 * @param Region This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 576 * @arg @ref LL_MPU_REGION_NUMBER0
NYX 0:85b3fd62ea1a 577 * @arg @ref LL_MPU_REGION_NUMBER1
NYX 0:85b3fd62ea1a 578 * @arg @ref LL_MPU_REGION_NUMBER2
NYX 0:85b3fd62ea1a 579 * @arg @ref LL_MPU_REGION_NUMBER3
NYX 0:85b3fd62ea1a 580 * @arg @ref LL_MPU_REGION_NUMBER4
NYX 0:85b3fd62ea1a 581 * @arg @ref LL_MPU_REGION_NUMBER5
NYX 0:85b3fd62ea1a 582 * @arg @ref LL_MPU_REGION_NUMBER6
NYX 0:85b3fd62ea1a 583 * @arg @ref LL_MPU_REGION_NUMBER7
NYX 0:85b3fd62ea1a 584 * @param Address Value of region base address
NYX 0:85b3fd62ea1a 585 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
NYX 0:85b3fd62ea1a 586 * @param Attributes This parameter can be a combination of the following values:
NYX 0:85b3fd62ea1a 587 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
NYX 0:85b3fd62ea1a 588 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
NYX 0:85b3fd62ea1a 589 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
NYX 0:85b3fd62ea1a 590 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
NYX 0:85b3fd62ea1a 591 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
NYX 0:85b3fd62ea1a 592 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
NYX 0:85b3fd62ea1a 593 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
NYX 0:85b3fd62ea1a 594 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
NYX 0:85b3fd62ea1a 595 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
NYX 0:85b3fd62ea1a 596 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
NYX 0:85b3fd62ea1a 597 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
NYX 0:85b3fd62ea1a 598 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
NYX 0:85b3fd62ea1a 599 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
NYX 0:85b3fd62ea1a 600 * @retval None
NYX 0:85b3fd62ea1a 601 */
NYX 0:85b3fd62ea1a 602 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
NYX 0:85b3fd62ea1a 603 {
NYX 0:85b3fd62ea1a 604 /* Set Region number */
NYX 0:85b3fd62ea1a 605 WRITE_REG(MPU->RNR, Region);
NYX 0:85b3fd62ea1a 606 /* Set base address */
NYX 0:85b3fd62ea1a 607 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
NYX 0:85b3fd62ea1a 608 /* Configure MPU */
NYX 0:85b3fd62ea1a 609 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
NYX 0:85b3fd62ea1a 610 }
NYX 0:85b3fd62ea1a 611
NYX 0:85b3fd62ea1a 612 /**
NYX 0:85b3fd62ea1a 613 * @brief Disable a region
NYX 0:85b3fd62ea1a 614 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
NYX 0:85b3fd62ea1a 615 * MPU_RASR ENABLE LL_MPU_DisableRegion
NYX 0:85b3fd62ea1a 616 * @param Region This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 617 * @arg @ref LL_MPU_REGION_NUMBER0
NYX 0:85b3fd62ea1a 618 * @arg @ref LL_MPU_REGION_NUMBER1
NYX 0:85b3fd62ea1a 619 * @arg @ref LL_MPU_REGION_NUMBER2
NYX 0:85b3fd62ea1a 620 * @arg @ref LL_MPU_REGION_NUMBER3
NYX 0:85b3fd62ea1a 621 * @arg @ref LL_MPU_REGION_NUMBER4
NYX 0:85b3fd62ea1a 622 * @arg @ref LL_MPU_REGION_NUMBER5
NYX 0:85b3fd62ea1a 623 * @arg @ref LL_MPU_REGION_NUMBER6
NYX 0:85b3fd62ea1a 624 * @arg @ref LL_MPU_REGION_NUMBER7
NYX 0:85b3fd62ea1a 625 * @retval None
NYX 0:85b3fd62ea1a 626 */
NYX 0:85b3fd62ea1a 627 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
NYX 0:85b3fd62ea1a 628 {
NYX 0:85b3fd62ea1a 629 /* Set Region number */
NYX 0:85b3fd62ea1a 630 WRITE_REG(MPU->RNR, Region);
NYX 0:85b3fd62ea1a 631 /* Disable the MPU region */
NYX 0:85b3fd62ea1a 632 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
NYX 0:85b3fd62ea1a 633 }
NYX 0:85b3fd62ea1a 634
NYX 0:85b3fd62ea1a 635 /**
NYX 0:85b3fd62ea1a 636 * @}
NYX 0:85b3fd62ea1a 637 */
NYX 0:85b3fd62ea1a 638
NYX 0:85b3fd62ea1a 639 #endif /* __MPU_PRESENT */
NYX 0:85b3fd62ea1a 640 /**
NYX 0:85b3fd62ea1a 641 * @}
NYX 0:85b3fd62ea1a 642 */
NYX 0:85b3fd62ea1a 643
NYX 0:85b3fd62ea1a 644 /**
NYX 0:85b3fd62ea1a 645 * @}
NYX 0:85b3fd62ea1a 646 */
NYX 0:85b3fd62ea1a 647
NYX 0:85b3fd62ea1a 648 /**
NYX 0:85b3fd62ea1a 649 * @}
NYX 0:85b3fd62ea1a 650 */
NYX 0:85b3fd62ea1a 651
NYX 0:85b3fd62ea1a 652 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 653 }
NYX 0:85b3fd62ea1a 654 #endif
NYX 0:85b3fd62ea1a 655
NYX 0:85b3fd62ea1a 656 #endif /* __STM32F4xx_LL_CORTEX_H */
NYX 0:85b3fd62ea1a 657
NYX 0:85b3fd62ea1a 658 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/