Takaaki Numai
inport from local
Dependents: Hobbyking_Cheetah_0511
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h@0:85b3fd62ea1a, 2020-03-16 (annotated)
- Committer:
- NYX
- Date:
- Mon Mar 16 06:35:48 2020 +0000
- Revision:
- 0:85b3fd62ea1a
reinport to mbed;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| NYX | 0:85b3fd62ea1a | 1 | /** |
| NYX | 0:85b3fd62ea1a | 2 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 3 | * @file stm32f4xx_ll_bus.h |
| NYX | 0:85b3fd62ea1a | 4 | * @author MCD Application Team |
| NYX | 0:85b3fd62ea1a | 5 | * @version V1.7.1 |
| NYX | 0:85b3fd62ea1a | 6 | * @date 14-April-2017 |
| NYX | 0:85b3fd62ea1a | 7 | * @brief Header file of BUS LL module. |
| NYX | 0:85b3fd62ea1a | 8 | |
| NYX | 0:85b3fd62ea1a | 9 | @verbatim |
| NYX | 0:85b3fd62ea1a | 10 | ##### RCC Limitations ##### |
| NYX | 0:85b3fd62ea1a | 11 | ============================================================================== |
| NYX | 0:85b3fd62ea1a | 12 | [..] |
| NYX | 0:85b3fd62ea1a | 13 | A delay between an RCC peripheral clock enable and the effective peripheral |
| NYX | 0:85b3fd62ea1a | 14 | enabling should be taken into account in order to manage the peripheral read/write |
| NYX | 0:85b3fd62ea1a | 15 | from/to registers. |
| NYX | 0:85b3fd62ea1a | 16 | (+) This delay depends on the peripheral mapping. |
| NYX | 0:85b3fd62ea1a | 17 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| NYX | 0:85b3fd62ea1a | 18 | |
| NYX | 0:85b3fd62ea1a | 19 | [..] |
| NYX | 0:85b3fd62ea1a | 20 | Workarounds: |
| NYX | 0:85b3fd62ea1a | 21 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| NYX | 0:85b3fd62ea1a | 22 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| NYX | 0:85b3fd62ea1a | 23 | |
| NYX | 0:85b3fd62ea1a | 24 | @endverbatim |
| NYX | 0:85b3fd62ea1a | 25 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 26 | * @attention |
| NYX | 0:85b3fd62ea1a | 27 | * |
| NYX | 0:85b3fd62ea1a | 28 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| NYX | 0:85b3fd62ea1a | 29 | * |
| NYX | 0:85b3fd62ea1a | 30 | * Redistribution and use in source and binary forms, with or without modification, |
| NYX | 0:85b3fd62ea1a | 31 | * are permitted provided that the following conditions are met: |
| NYX | 0:85b3fd62ea1a | 32 | * 1. Redistributions of source code must retain the above copyright notice, |
| NYX | 0:85b3fd62ea1a | 33 | * this list of conditions and the following disclaimer. |
| NYX | 0:85b3fd62ea1a | 34 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| NYX | 0:85b3fd62ea1a | 35 | * this list of conditions and the following disclaimer in the documentation |
| NYX | 0:85b3fd62ea1a | 36 | * and/or other materials provided with the distribution. |
| NYX | 0:85b3fd62ea1a | 37 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| NYX | 0:85b3fd62ea1a | 38 | * may be used to endorse or promote products derived from this software |
| NYX | 0:85b3fd62ea1a | 39 | * without specific prior written permission. |
| NYX | 0:85b3fd62ea1a | 40 | * |
| NYX | 0:85b3fd62ea1a | 41 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| NYX | 0:85b3fd62ea1a | 42 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| NYX | 0:85b3fd62ea1a | 43 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| NYX | 0:85b3fd62ea1a | 44 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| NYX | 0:85b3fd62ea1a | 45 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| NYX | 0:85b3fd62ea1a | 46 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| NYX | 0:85b3fd62ea1a | 47 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| NYX | 0:85b3fd62ea1a | 48 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| NYX | 0:85b3fd62ea1a | 49 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| NYX | 0:85b3fd62ea1a | 50 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| NYX | 0:85b3fd62ea1a | 51 | * |
| NYX | 0:85b3fd62ea1a | 52 | ****************************************************************************** |
| NYX | 0:85b3fd62ea1a | 53 | */ |
| NYX | 0:85b3fd62ea1a | 54 | |
| NYX | 0:85b3fd62ea1a | 55 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 56 | #ifndef __STM32F4xx_LL_BUS_H |
| NYX | 0:85b3fd62ea1a | 57 | #define __STM32F4xx_LL_BUS_H |
| NYX | 0:85b3fd62ea1a | 58 | |
| NYX | 0:85b3fd62ea1a | 59 | #ifdef __cplusplus |
| NYX | 0:85b3fd62ea1a | 60 | extern "C" { |
| NYX | 0:85b3fd62ea1a | 61 | #endif |
| NYX | 0:85b3fd62ea1a | 62 | |
| NYX | 0:85b3fd62ea1a | 63 | /* Includes ------------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 64 | #include "stm32f4xx.h" |
| NYX | 0:85b3fd62ea1a | 65 | |
| NYX | 0:85b3fd62ea1a | 66 | /** @addtogroup STM32F4xx_LL_Driver |
| NYX | 0:85b3fd62ea1a | 67 | * @{ |
| NYX | 0:85b3fd62ea1a | 68 | */ |
| NYX | 0:85b3fd62ea1a | 69 | |
| NYX | 0:85b3fd62ea1a | 70 | #if defined(RCC) |
| NYX | 0:85b3fd62ea1a | 71 | |
| NYX | 0:85b3fd62ea1a | 72 | /** @defgroup BUS_LL BUS |
| NYX | 0:85b3fd62ea1a | 73 | * @{ |
| NYX | 0:85b3fd62ea1a | 74 | */ |
| NYX | 0:85b3fd62ea1a | 75 | |
| NYX | 0:85b3fd62ea1a | 76 | /* Private types -------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 77 | /* Private variables ---------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 78 | /* Private constants ---------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 79 | /* Private macros ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 80 | /* Exported types ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 81 | /* Exported constants --------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 82 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| NYX | 0:85b3fd62ea1a | 83 | * @{ |
| NYX | 0:85b3fd62ea1a | 84 | */ |
| NYX | 0:85b3fd62ea1a | 85 | |
| NYX | 0:85b3fd62ea1a | 86 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| NYX | 0:85b3fd62ea1a | 87 | * @{ |
| NYX | 0:85b3fd62ea1a | 88 | */ |
| NYX | 0:85b3fd62ea1a | 89 | #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| NYX | 0:85b3fd62ea1a | 90 | #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN |
| NYX | 0:85b3fd62ea1a | 91 | #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN |
| NYX | 0:85b3fd62ea1a | 92 | #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN |
| NYX | 0:85b3fd62ea1a | 93 | #if defined(GPIOD) |
| NYX | 0:85b3fd62ea1a | 94 | #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN |
| NYX | 0:85b3fd62ea1a | 95 | #endif /* GPIOD */ |
| NYX | 0:85b3fd62ea1a | 96 | #if defined(GPIOE) |
| NYX | 0:85b3fd62ea1a | 97 | #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN |
| NYX | 0:85b3fd62ea1a | 98 | #endif /* GPIOE */ |
| NYX | 0:85b3fd62ea1a | 99 | #if defined(GPIOF) |
| NYX | 0:85b3fd62ea1a | 100 | #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN |
| NYX | 0:85b3fd62ea1a | 101 | #endif /* GPIOF */ |
| NYX | 0:85b3fd62ea1a | 102 | #if defined(GPIOG) |
| NYX | 0:85b3fd62ea1a | 103 | #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN |
| NYX | 0:85b3fd62ea1a | 104 | #endif /* GPIOG */ |
| NYX | 0:85b3fd62ea1a | 105 | #if defined(GPIOH) |
| NYX | 0:85b3fd62ea1a | 106 | #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN |
| NYX | 0:85b3fd62ea1a | 107 | #endif /* GPIOH */ |
| NYX | 0:85b3fd62ea1a | 108 | #if defined(GPIOI) |
| NYX | 0:85b3fd62ea1a | 109 | #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN |
| NYX | 0:85b3fd62ea1a | 110 | #endif /* GPIOI */ |
| NYX | 0:85b3fd62ea1a | 111 | #if defined(GPIOJ) |
| NYX | 0:85b3fd62ea1a | 112 | #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN |
| NYX | 0:85b3fd62ea1a | 113 | #endif /* GPIOJ */ |
| NYX | 0:85b3fd62ea1a | 114 | #if defined(GPIOK) |
| NYX | 0:85b3fd62ea1a | 115 | #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN |
| NYX | 0:85b3fd62ea1a | 116 | #endif /* GPIOK */ |
| NYX | 0:85b3fd62ea1a | 117 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN |
| NYX | 0:85b3fd62ea1a | 118 | #if defined(RCC_AHB1ENR_BKPSRAMEN) |
| NYX | 0:85b3fd62ea1a | 119 | #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN |
| NYX | 0:85b3fd62ea1a | 120 | #endif /* RCC_AHB1ENR_BKPSRAMEN */ |
| NYX | 0:85b3fd62ea1a | 121 | #if defined(RCC_AHB1ENR_CCMDATARAMEN) |
| NYX | 0:85b3fd62ea1a | 122 | #define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN |
| NYX | 0:85b3fd62ea1a | 123 | #endif /* RCC_AHB1ENR_CCMDATARAMEN */ |
| NYX | 0:85b3fd62ea1a | 124 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN |
| NYX | 0:85b3fd62ea1a | 125 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN |
| NYX | 0:85b3fd62ea1a | 126 | #if defined(RCC_AHB1ENR_RNGEN) |
| NYX | 0:85b3fd62ea1a | 127 | #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN |
| NYX | 0:85b3fd62ea1a | 128 | #endif /* RCC_AHB1ENR_RNGEN */ |
| NYX | 0:85b3fd62ea1a | 129 | #if defined(DMA2D) |
| NYX | 0:85b3fd62ea1a | 130 | #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN |
| NYX | 0:85b3fd62ea1a | 131 | #endif /* DMA2D */ |
| NYX | 0:85b3fd62ea1a | 132 | #if defined(ETH) |
| NYX | 0:85b3fd62ea1a | 133 | #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN |
| NYX | 0:85b3fd62ea1a | 134 | #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN |
| NYX | 0:85b3fd62ea1a | 135 | #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN |
| NYX | 0:85b3fd62ea1a | 136 | #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN |
| NYX | 0:85b3fd62ea1a | 137 | #endif /* ETH */ |
| NYX | 0:85b3fd62ea1a | 138 | #if defined(USB_OTG_HS) |
| NYX | 0:85b3fd62ea1a | 139 | #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN |
| NYX | 0:85b3fd62ea1a | 140 | #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN |
| NYX | 0:85b3fd62ea1a | 141 | #endif /* USB_OTG_HS */ |
| NYX | 0:85b3fd62ea1a | 142 | #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN |
| NYX | 0:85b3fd62ea1a | 143 | #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN |
| NYX | 0:85b3fd62ea1a | 144 | #if defined(RCC_AHB1LPENR_SRAM2LPEN) |
| NYX | 0:85b3fd62ea1a | 145 | #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN |
| NYX | 0:85b3fd62ea1a | 146 | #endif /* RCC_AHB1LPENR_SRAM2LPEN */ |
| NYX | 0:85b3fd62ea1a | 147 | #if defined(RCC_AHB1LPENR_SRAM3LPEN) |
| NYX | 0:85b3fd62ea1a | 148 | #define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN |
| NYX | 0:85b3fd62ea1a | 149 | #endif /* RCC_AHB1LPENR_SRAM3LPEN */ |
| NYX | 0:85b3fd62ea1a | 150 | /** |
| NYX | 0:85b3fd62ea1a | 151 | * @} |
| NYX | 0:85b3fd62ea1a | 152 | */ |
| NYX | 0:85b3fd62ea1a | 153 | |
| NYX | 0:85b3fd62ea1a | 154 | #if defined(RCC_AHB2_SUPPORT) |
| NYX | 0:85b3fd62ea1a | 155 | /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH |
| NYX | 0:85b3fd62ea1a | 156 | * @{ |
| NYX | 0:85b3fd62ea1a | 157 | */ |
| NYX | 0:85b3fd62ea1a | 158 | #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| NYX | 0:85b3fd62ea1a | 159 | #if defined(DCMI) |
| NYX | 0:85b3fd62ea1a | 160 | #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN |
| NYX | 0:85b3fd62ea1a | 161 | #endif /* DCMI */ |
| NYX | 0:85b3fd62ea1a | 162 | #if defined(CRYP) |
| NYX | 0:85b3fd62ea1a | 163 | #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN |
| NYX | 0:85b3fd62ea1a | 164 | #endif /* CRYP */ |
| NYX | 0:85b3fd62ea1a | 165 | #if defined(AES) |
| NYX | 0:85b3fd62ea1a | 166 | #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN |
| NYX | 0:85b3fd62ea1a | 167 | #endif /* AES */ |
| NYX | 0:85b3fd62ea1a | 168 | #if defined(HASH) |
| NYX | 0:85b3fd62ea1a | 169 | #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN |
| NYX | 0:85b3fd62ea1a | 170 | #endif /* HASH */ |
| NYX | 0:85b3fd62ea1a | 171 | #if defined(RCC_AHB2ENR_RNGEN) |
| NYX | 0:85b3fd62ea1a | 172 | #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN |
| NYX | 0:85b3fd62ea1a | 173 | #endif /* RCC_AHB2ENR_RNGEN */ |
| NYX | 0:85b3fd62ea1a | 174 | #if defined(USB_OTG_FS) |
| NYX | 0:85b3fd62ea1a | 175 | #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN |
| NYX | 0:85b3fd62ea1a | 176 | #endif /* USB_OTG_FS */ |
| NYX | 0:85b3fd62ea1a | 177 | /** |
| NYX | 0:85b3fd62ea1a | 178 | * @} |
| NYX | 0:85b3fd62ea1a | 179 | */ |
| NYX | 0:85b3fd62ea1a | 180 | #endif /* RCC_AHB2_SUPPORT */ |
| NYX | 0:85b3fd62ea1a | 181 | |
| NYX | 0:85b3fd62ea1a | 182 | #if defined(RCC_AHB3_SUPPORT) |
| NYX | 0:85b3fd62ea1a | 183 | /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH |
| NYX | 0:85b3fd62ea1a | 184 | * @{ |
| NYX | 0:85b3fd62ea1a | 185 | */ |
| NYX | 0:85b3fd62ea1a | 186 | #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| NYX | 0:85b3fd62ea1a | 187 | #if defined(FSMC_Bank1) |
| NYX | 0:85b3fd62ea1a | 188 | #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN |
| NYX | 0:85b3fd62ea1a | 189 | #endif /* FSMC_Bank1 */ |
| NYX | 0:85b3fd62ea1a | 190 | #if defined(FMC_Bank1) |
| NYX | 0:85b3fd62ea1a | 191 | #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN |
| NYX | 0:85b3fd62ea1a | 192 | #endif /* FMC_Bank1 */ |
| NYX | 0:85b3fd62ea1a | 193 | #if defined(QUADSPI) |
| NYX | 0:85b3fd62ea1a | 194 | #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN |
| NYX | 0:85b3fd62ea1a | 195 | #endif /* QUADSPI */ |
| NYX | 0:85b3fd62ea1a | 196 | /** |
| NYX | 0:85b3fd62ea1a | 197 | * @} |
| NYX | 0:85b3fd62ea1a | 198 | */ |
| NYX | 0:85b3fd62ea1a | 199 | #endif /* RCC_AHB3_SUPPORT */ |
| NYX | 0:85b3fd62ea1a | 200 | |
| NYX | 0:85b3fd62ea1a | 201 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| NYX | 0:85b3fd62ea1a | 202 | * @{ |
| NYX | 0:85b3fd62ea1a | 203 | */ |
| NYX | 0:85b3fd62ea1a | 204 | #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| NYX | 0:85b3fd62ea1a | 205 | #if defined(TIM2) |
| NYX | 0:85b3fd62ea1a | 206 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN |
| NYX | 0:85b3fd62ea1a | 207 | #endif /* TIM2 */ |
| NYX | 0:85b3fd62ea1a | 208 | #if defined(TIM3) |
| NYX | 0:85b3fd62ea1a | 209 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN |
| NYX | 0:85b3fd62ea1a | 210 | #endif /* TIM3 */ |
| NYX | 0:85b3fd62ea1a | 211 | #if defined(TIM4) |
| NYX | 0:85b3fd62ea1a | 212 | #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN |
| NYX | 0:85b3fd62ea1a | 213 | #endif /* TIM4 */ |
| NYX | 0:85b3fd62ea1a | 214 | #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN |
| NYX | 0:85b3fd62ea1a | 215 | #if defined(TIM6) |
| NYX | 0:85b3fd62ea1a | 216 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN |
| NYX | 0:85b3fd62ea1a | 217 | #endif /* TIM6 */ |
| NYX | 0:85b3fd62ea1a | 218 | #if defined(TIM7) |
| NYX | 0:85b3fd62ea1a | 219 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN |
| NYX | 0:85b3fd62ea1a | 220 | #endif /* TIM7 */ |
| NYX | 0:85b3fd62ea1a | 221 | #if defined(TIM12) |
| NYX | 0:85b3fd62ea1a | 222 | #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN |
| NYX | 0:85b3fd62ea1a | 223 | #endif /* TIM12 */ |
| NYX | 0:85b3fd62ea1a | 224 | #if defined(TIM13) |
| NYX | 0:85b3fd62ea1a | 225 | #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN |
| NYX | 0:85b3fd62ea1a | 226 | #endif /* TIM13 */ |
| NYX | 0:85b3fd62ea1a | 227 | #if defined(TIM14) |
| NYX | 0:85b3fd62ea1a | 228 | #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN |
| NYX | 0:85b3fd62ea1a | 229 | #endif /* TIM14 */ |
| NYX | 0:85b3fd62ea1a | 230 | #if defined(LPTIM1) |
| NYX | 0:85b3fd62ea1a | 231 | #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN |
| NYX | 0:85b3fd62ea1a | 232 | #endif /* LPTIM1 */ |
| NYX | 0:85b3fd62ea1a | 233 | #if defined(RCC_APB1ENR_RTCAPBEN) |
| NYX | 0:85b3fd62ea1a | 234 | #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN |
| NYX | 0:85b3fd62ea1a | 235 | #endif /* RCC_APB1ENR_RTCAPBEN */ |
| NYX | 0:85b3fd62ea1a | 236 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN |
| NYX | 0:85b3fd62ea1a | 237 | #if defined(SPI2) |
| NYX | 0:85b3fd62ea1a | 238 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN |
| NYX | 0:85b3fd62ea1a | 239 | #endif /* SPI2 */ |
| NYX | 0:85b3fd62ea1a | 240 | #if defined(SPI3) |
| NYX | 0:85b3fd62ea1a | 241 | #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN |
| NYX | 0:85b3fd62ea1a | 242 | #endif /* SPI3 */ |
| NYX | 0:85b3fd62ea1a | 243 | #if defined(SPDIFRX) |
| NYX | 0:85b3fd62ea1a | 244 | #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN |
| NYX | 0:85b3fd62ea1a | 245 | #endif /* SPDIFRX */ |
| NYX | 0:85b3fd62ea1a | 246 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN |
| NYX | 0:85b3fd62ea1a | 247 | #if defined(USART3) |
| NYX | 0:85b3fd62ea1a | 248 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN |
| NYX | 0:85b3fd62ea1a | 249 | #endif /* USART3 */ |
| NYX | 0:85b3fd62ea1a | 250 | #if defined(UART4) |
| NYX | 0:85b3fd62ea1a | 251 | #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN |
| NYX | 0:85b3fd62ea1a | 252 | #endif /* UART4 */ |
| NYX | 0:85b3fd62ea1a | 253 | #if defined(UART5) |
| NYX | 0:85b3fd62ea1a | 254 | #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN |
| NYX | 0:85b3fd62ea1a | 255 | #endif /* UART5 */ |
| NYX | 0:85b3fd62ea1a | 256 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN |
| NYX | 0:85b3fd62ea1a | 257 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN |
| NYX | 0:85b3fd62ea1a | 258 | #if defined(I2C3) |
| NYX | 0:85b3fd62ea1a | 259 | #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN |
| NYX | 0:85b3fd62ea1a | 260 | #endif /* I2C3 */ |
| NYX | 0:85b3fd62ea1a | 261 | #if defined(FMPI2C1) |
| NYX | 0:85b3fd62ea1a | 262 | #define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN |
| NYX | 0:85b3fd62ea1a | 263 | #endif /* FMPI2C1 */ |
| NYX | 0:85b3fd62ea1a | 264 | #if defined(CAN1) |
| NYX | 0:85b3fd62ea1a | 265 | #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN |
| NYX | 0:85b3fd62ea1a | 266 | #endif /* CAN1 */ |
| NYX | 0:85b3fd62ea1a | 267 | #if defined(CAN2) |
| NYX | 0:85b3fd62ea1a | 268 | #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN |
| NYX | 0:85b3fd62ea1a | 269 | #endif /* CAN2 */ |
| NYX | 0:85b3fd62ea1a | 270 | #if defined(CAN3) |
| NYX | 0:85b3fd62ea1a | 271 | #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN |
| NYX | 0:85b3fd62ea1a | 272 | #endif /* CAN3 */ |
| NYX | 0:85b3fd62ea1a | 273 | #if defined(CEC) |
| NYX | 0:85b3fd62ea1a | 274 | #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN |
| NYX | 0:85b3fd62ea1a | 275 | #endif /* CEC */ |
| NYX | 0:85b3fd62ea1a | 276 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN |
| NYX | 0:85b3fd62ea1a | 277 | #if defined(DAC1) |
| NYX | 0:85b3fd62ea1a | 278 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN |
| NYX | 0:85b3fd62ea1a | 279 | #endif /* DAC1 */ |
| NYX | 0:85b3fd62ea1a | 280 | #if defined(UART7) |
| NYX | 0:85b3fd62ea1a | 281 | #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN |
| NYX | 0:85b3fd62ea1a | 282 | #endif /* UART7 */ |
| NYX | 0:85b3fd62ea1a | 283 | #if defined(UART8) |
| NYX | 0:85b3fd62ea1a | 284 | #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN |
| NYX | 0:85b3fd62ea1a | 285 | #endif /* UART8 */ |
| NYX | 0:85b3fd62ea1a | 286 | /** |
| NYX | 0:85b3fd62ea1a | 287 | * @} |
| NYX | 0:85b3fd62ea1a | 288 | */ |
| NYX | 0:85b3fd62ea1a | 289 | |
| NYX | 0:85b3fd62ea1a | 290 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
| NYX | 0:85b3fd62ea1a | 291 | * @{ |
| NYX | 0:85b3fd62ea1a | 292 | */ |
| NYX | 0:85b3fd62ea1a | 293 | #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| NYX | 0:85b3fd62ea1a | 294 | #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN |
| NYX | 0:85b3fd62ea1a | 295 | #if defined(TIM8) |
| NYX | 0:85b3fd62ea1a | 296 | #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN |
| NYX | 0:85b3fd62ea1a | 297 | #endif /* TIM8 */ |
| NYX | 0:85b3fd62ea1a | 298 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN |
| NYX | 0:85b3fd62ea1a | 299 | #if defined(USART6) |
| NYX | 0:85b3fd62ea1a | 300 | #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN |
| NYX | 0:85b3fd62ea1a | 301 | #endif /* USART6 */ |
| NYX | 0:85b3fd62ea1a | 302 | #if defined(UART9) |
| NYX | 0:85b3fd62ea1a | 303 | #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN |
| NYX | 0:85b3fd62ea1a | 304 | #endif /* UART9 */ |
| NYX | 0:85b3fd62ea1a | 305 | #if defined(UART10) |
| NYX | 0:85b3fd62ea1a | 306 | #define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN |
| NYX | 0:85b3fd62ea1a | 307 | #endif /* UART10 */ |
| NYX | 0:85b3fd62ea1a | 308 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN |
| NYX | 0:85b3fd62ea1a | 309 | #if defined(ADC2) |
| NYX | 0:85b3fd62ea1a | 310 | #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN |
| NYX | 0:85b3fd62ea1a | 311 | #endif /* ADC2 */ |
| NYX | 0:85b3fd62ea1a | 312 | #if defined(ADC3) |
| NYX | 0:85b3fd62ea1a | 313 | #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN |
| NYX | 0:85b3fd62ea1a | 314 | #endif /* ADC3 */ |
| NYX | 0:85b3fd62ea1a | 315 | #if defined(SDIO) |
| NYX | 0:85b3fd62ea1a | 316 | #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN |
| NYX | 0:85b3fd62ea1a | 317 | #endif /* SDIO */ |
| NYX | 0:85b3fd62ea1a | 318 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
| NYX | 0:85b3fd62ea1a | 319 | #if defined(SPI4) |
| NYX | 0:85b3fd62ea1a | 320 | #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN |
| NYX | 0:85b3fd62ea1a | 321 | #endif /* SPI4 */ |
| NYX | 0:85b3fd62ea1a | 322 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN |
| NYX | 0:85b3fd62ea1a | 323 | #if defined(RCC_APB2ENR_EXTITEN) |
| NYX | 0:85b3fd62ea1a | 324 | #define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN |
| NYX | 0:85b3fd62ea1a | 325 | #endif /* RCC_APB2ENR_EXTITEN */ |
| NYX | 0:85b3fd62ea1a | 326 | #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN |
| NYX | 0:85b3fd62ea1a | 327 | #if defined(TIM10) |
| NYX | 0:85b3fd62ea1a | 328 | #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN |
| NYX | 0:85b3fd62ea1a | 329 | #endif /* TIM10 */ |
| NYX | 0:85b3fd62ea1a | 330 | #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN |
| NYX | 0:85b3fd62ea1a | 331 | #if defined(SPI5) |
| NYX | 0:85b3fd62ea1a | 332 | #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN |
| NYX | 0:85b3fd62ea1a | 333 | #endif /* SPI5 */ |
| NYX | 0:85b3fd62ea1a | 334 | #if defined(SPI6) |
| NYX | 0:85b3fd62ea1a | 335 | #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN |
| NYX | 0:85b3fd62ea1a | 336 | #endif /* SPI6 */ |
| NYX | 0:85b3fd62ea1a | 337 | #if defined(SAI1) |
| NYX | 0:85b3fd62ea1a | 338 | #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN |
| NYX | 0:85b3fd62ea1a | 339 | #endif /* SAI1 */ |
| NYX | 0:85b3fd62ea1a | 340 | #if defined(SAI2) |
| NYX | 0:85b3fd62ea1a | 341 | #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN |
| NYX | 0:85b3fd62ea1a | 342 | #endif /* SAI2 */ |
| NYX | 0:85b3fd62ea1a | 343 | #if defined(LTDC) |
| NYX | 0:85b3fd62ea1a | 344 | #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN |
| NYX | 0:85b3fd62ea1a | 345 | #endif /* LTDC */ |
| NYX | 0:85b3fd62ea1a | 346 | #if defined(DSI) |
| NYX | 0:85b3fd62ea1a | 347 | #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN |
| NYX | 0:85b3fd62ea1a | 348 | #endif /* DSI */ |
| NYX | 0:85b3fd62ea1a | 349 | #if defined(DFSDM1_Channel0) |
| NYX | 0:85b3fd62ea1a | 350 | #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN |
| NYX | 0:85b3fd62ea1a | 351 | #endif /* DFSDM1_Channel0 */ |
| NYX | 0:85b3fd62ea1a | 352 | #if defined(DFSDM2_Channel0) |
| NYX | 0:85b3fd62ea1a | 353 | #define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN |
| NYX | 0:85b3fd62ea1a | 354 | #endif /* DFSDM2_Channel0 */ |
| NYX | 0:85b3fd62ea1a | 355 | #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST |
| NYX | 0:85b3fd62ea1a | 356 | /** |
| NYX | 0:85b3fd62ea1a | 357 | * @} |
| NYX | 0:85b3fd62ea1a | 358 | */ |
| NYX | 0:85b3fd62ea1a | 359 | |
| NYX | 0:85b3fd62ea1a | 360 | /** |
| NYX | 0:85b3fd62ea1a | 361 | * @} |
| NYX | 0:85b3fd62ea1a | 362 | */ |
| NYX | 0:85b3fd62ea1a | 363 | |
| NYX | 0:85b3fd62ea1a | 364 | /* Exported macro ------------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 365 | /* Exported functions --------------------------------------------------------*/ |
| NYX | 0:85b3fd62ea1a | 366 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| NYX | 0:85b3fd62ea1a | 367 | * @{ |
| NYX | 0:85b3fd62ea1a | 368 | */ |
| NYX | 0:85b3fd62ea1a | 369 | |
| NYX | 0:85b3fd62ea1a | 370 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| NYX | 0:85b3fd62ea1a | 371 | * @{ |
| NYX | 0:85b3fd62ea1a | 372 | */ |
| NYX | 0:85b3fd62ea1a | 373 | |
| NYX | 0:85b3fd62ea1a | 374 | /** |
| NYX | 0:85b3fd62ea1a | 375 | * @brief Enable AHB1 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 376 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 377 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 378 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 379 | * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 380 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 381 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 382 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 383 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 384 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 385 | * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 386 | * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 387 | * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 388 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 389 | * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 390 | * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 391 | * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 392 | * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 393 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 394 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 395 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 396 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 397 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 398 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 399 | * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock |
| NYX | 0:85b3fd62ea1a | 400 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 401 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| NYX | 0:85b3fd62ea1a | 402 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| NYX | 0:85b3fd62ea1a | 403 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| NYX | 0:85b3fd62ea1a | 404 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| NYX | 0:85b3fd62ea1a | 405 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| NYX | 0:85b3fd62ea1a | 406 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| NYX | 0:85b3fd62ea1a | 407 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| NYX | 0:85b3fd62ea1a | 408 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| NYX | 0:85b3fd62ea1a | 409 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) |
| NYX | 0:85b3fd62ea1a | 410 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| NYX | 0:85b3fd62ea1a | 411 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| NYX | 0:85b3fd62ea1a | 412 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| NYX | 0:85b3fd62ea1a | 413 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) |
| NYX | 0:85b3fd62ea1a | 414 | * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) |
| NYX | 0:85b3fd62ea1a | 415 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| NYX | 0:85b3fd62ea1a | 416 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| NYX | 0:85b3fd62ea1a | 417 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 418 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| NYX | 0:85b3fd62ea1a | 419 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| NYX | 0:85b3fd62ea1a | 420 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| NYX | 0:85b3fd62ea1a | 421 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| NYX | 0:85b3fd62ea1a | 422 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| NYX | 0:85b3fd62ea1a | 423 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) |
| NYX | 0:85b3fd62ea1a | 424 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) |
| NYX | 0:85b3fd62ea1a | 425 | * |
| NYX | 0:85b3fd62ea1a | 426 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 427 | * @retval None |
| NYX | 0:85b3fd62ea1a | 428 | */ |
| NYX | 0:85b3fd62ea1a | 429 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 430 | { |
| NYX | 0:85b3fd62ea1a | 431 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 432 | SET_BIT(RCC->AHB1ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 433 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 434 | tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 435 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 436 | } |
| NYX | 0:85b3fd62ea1a | 437 | |
| NYX | 0:85b3fd62ea1a | 438 | /** |
| NYX | 0:85b3fd62ea1a | 439 | * @brief Check if AHB1 peripheral clock is enabled or not |
| NYX | 0:85b3fd62ea1a | 440 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 441 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 442 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 443 | * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 444 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 445 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 446 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 447 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 448 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 449 | * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 450 | * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 451 | * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 452 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 453 | * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 454 | * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 455 | * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 456 | * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 457 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 458 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 459 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 460 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 461 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 462 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 463 | * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock |
| NYX | 0:85b3fd62ea1a | 464 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 465 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| NYX | 0:85b3fd62ea1a | 466 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| NYX | 0:85b3fd62ea1a | 467 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| NYX | 0:85b3fd62ea1a | 468 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| NYX | 0:85b3fd62ea1a | 469 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| NYX | 0:85b3fd62ea1a | 470 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| NYX | 0:85b3fd62ea1a | 471 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| NYX | 0:85b3fd62ea1a | 472 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| NYX | 0:85b3fd62ea1a | 473 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) |
| NYX | 0:85b3fd62ea1a | 474 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| NYX | 0:85b3fd62ea1a | 475 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| NYX | 0:85b3fd62ea1a | 476 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| NYX | 0:85b3fd62ea1a | 477 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) |
| NYX | 0:85b3fd62ea1a | 478 | * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) |
| NYX | 0:85b3fd62ea1a | 479 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| NYX | 0:85b3fd62ea1a | 480 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| NYX | 0:85b3fd62ea1a | 481 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 482 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| NYX | 0:85b3fd62ea1a | 483 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| NYX | 0:85b3fd62ea1a | 484 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| NYX | 0:85b3fd62ea1a | 485 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| NYX | 0:85b3fd62ea1a | 486 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| NYX | 0:85b3fd62ea1a | 487 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) |
| NYX | 0:85b3fd62ea1a | 488 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) |
| NYX | 0:85b3fd62ea1a | 489 | * |
| NYX | 0:85b3fd62ea1a | 490 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 491 | * @retval State of Periphs (1 or 0). |
| NYX | 0:85b3fd62ea1a | 492 | */ |
| NYX | 0:85b3fd62ea1a | 493 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 494 | { |
| NYX | 0:85b3fd62ea1a | 495 | return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); |
| NYX | 0:85b3fd62ea1a | 496 | } |
| NYX | 0:85b3fd62ea1a | 497 | |
| NYX | 0:85b3fd62ea1a | 498 | /** |
| NYX | 0:85b3fd62ea1a | 499 | * @brief Disable AHB1 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 500 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 501 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 502 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 503 | * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 504 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 505 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 506 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 507 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 508 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 509 | * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 510 | * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 511 | * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 512 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 513 | * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 514 | * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 515 | * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 516 | * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 517 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 518 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 519 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 520 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 521 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 522 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 523 | * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock |
| NYX | 0:85b3fd62ea1a | 524 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 525 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| NYX | 0:85b3fd62ea1a | 526 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| NYX | 0:85b3fd62ea1a | 527 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| NYX | 0:85b3fd62ea1a | 528 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| NYX | 0:85b3fd62ea1a | 529 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| NYX | 0:85b3fd62ea1a | 530 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| NYX | 0:85b3fd62ea1a | 531 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| NYX | 0:85b3fd62ea1a | 532 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| NYX | 0:85b3fd62ea1a | 533 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) |
| NYX | 0:85b3fd62ea1a | 534 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| NYX | 0:85b3fd62ea1a | 535 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| NYX | 0:85b3fd62ea1a | 536 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| NYX | 0:85b3fd62ea1a | 537 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) |
| NYX | 0:85b3fd62ea1a | 538 | * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) |
| NYX | 0:85b3fd62ea1a | 539 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| NYX | 0:85b3fd62ea1a | 540 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| NYX | 0:85b3fd62ea1a | 541 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 542 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| NYX | 0:85b3fd62ea1a | 543 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| NYX | 0:85b3fd62ea1a | 544 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| NYX | 0:85b3fd62ea1a | 545 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| NYX | 0:85b3fd62ea1a | 546 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| NYX | 0:85b3fd62ea1a | 547 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) |
| NYX | 0:85b3fd62ea1a | 548 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) |
| NYX | 0:85b3fd62ea1a | 549 | * |
| NYX | 0:85b3fd62ea1a | 550 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 551 | * @retval None |
| NYX | 0:85b3fd62ea1a | 552 | */ |
| NYX | 0:85b3fd62ea1a | 553 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 554 | { |
| NYX | 0:85b3fd62ea1a | 555 | CLEAR_BIT(RCC->AHB1ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 556 | } |
| NYX | 0:85b3fd62ea1a | 557 | |
| NYX | 0:85b3fd62ea1a | 558 | /** |
| NYX | 0:85b3fd62ea1a | 559 | * @brief Force AHB1 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 560 | * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 561 | * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 562 | * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 563 | * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 564 | * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 565 | * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 566 | * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 567 | * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 568 | * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 569 | * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 570 | * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 571 | * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 572 | * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 573 | * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 574 | * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 575 | * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 576 | * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 577 | * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset |
| NYX | 0:85b3fd62ea1a | 578 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 579 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| NYX | 0:85b3fd62ea1a | 580 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| NYX | 0:85b3fd62ea1a | 581 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| NYX | 0:85b3fd62ea1a | 582 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| NYX | 0:85b3fd62ea1a | 583 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| NYX | 0:85b3fd62ea1a | 584 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| NYX | 0:85b3fd62ea1a | 585 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| NYX | 0:85b3fd62ea1a | 586 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| NYX | 0:85b3fd62ea1a | 587 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| NYX | 0:85b3fd62ea1a | 588 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) |
| NYX | 0:85b3fd62ea1a | 589 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| NYX | 0:85b3fd62ea1a | 590 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| NYX | 0:85b3fd62ea1a | 591 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| NYX | 0:85b3fd62ea1a | 592 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| NYX | 0:85b3fd62ea1a | 593 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| NYX | 0:85b3fd62ea1a | 594 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 595 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| NYX | 0:85b3fd62ea1a | 596 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| NYX | 0:85b3fd62ea1a | 597 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) |
| NYX | 0:85b3fd62ea1a | 598 | * |
| NYX | 0:85b3fd62ea1a | 599 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 600 | * @retval None |
| NYX | 0:85b3fd62ea1a | 601 | */ |
| NYX | 0:85b3fd62ea1a | 602 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 603 | { |
| NYX | 0:85b3fd62ea1a | 604 | SET_BIT(RCC->AHB1RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 605 | } |
| NYX | 0:85b3fd62ea1a | 606 | |
| NYX | 0:85b3fd62ea1a | 607 | /** |
| NYX | 0:85b3fd62ea1a | 608 | * @brief Release AHB1 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 609 | * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 610 | * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 611 | * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 612 | * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 613 | * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 614 | * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 615 | * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 616 | * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 617 | * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 618 | * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 619 | * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 620 | * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 621 | * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 622 | * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 623 | * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 624 | * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 625 | * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 626 | * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset |
| NYX | 0:85b3fd62ea1a | 627 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 628 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| NYX | 0:85b3fd62ea1a | 629 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| NYX | 0:85b3fd62ea1a | 630 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| NYX | 0:85b3fd62ea1a | 631 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| NYX | 0:85b3fd62ea1a | 632 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| NYX | 0:85b3fd62ea1a | 633 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| NYX | 0:85b3fd62ea1a | 634 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| NYX | 0:85b3fd62ea1a | 635 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| NYX | 0:85b3fd62ea1a | 636 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| NYX | 0:85b3fd62ea1a | 637 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) |
| NYX | 0:85b3fd62ea1a | 638 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| NYX | 0:85b3fd62ea1a | 639 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| NYX | 0:85b3fd62ea1a | 640 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| NYX | 0:85b3fd62ea1a | 641 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| NYX | 0:85b3fd62ea1a | 642 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| NYX | 0:85b3fd62ea1a | 643 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 644 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| NYX | 0:85b3fd62ea1a | 645 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| NYX | 0:85b3fd62ea1a | 646 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) |
| NYX | 0:85b3fd62ea1a | 647 | * |
| NYX | 0:85b3fd62ea1a | 648 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 649 | * @retval None |
| NYX | 0:85b3fd62ea1a | 650 | */ |
| NYX | 0:85b3fd62ea1a | 651 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 652 | { |
| NYX | 0:85b3fd62ea1a | 653 | CLEAR_BIT(RCC->AHB1RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 654 | } |
| NYX | 0:85b3fd62ea1a | 655 | |
| NYX | 0:85b3fd62ea1a | 656 | /** |
| NYX | 0:85b3fd62ea1a | 657 | * @brief Enable AHB1 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 658 | * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 659 | * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 660 | * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 661 | * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 662 | * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 663 | * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 664 | * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 665 | * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 666 | * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 667 | * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 668 | * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 669 | * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 670 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 671 | * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 672 | * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 673 | * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 674 | * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 675 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 676 | * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 677 | * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 678 | * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 679 | * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 680 | * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 681 | * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 682 | * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 683 | * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 684 | * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 685 | * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower |
| NYX | 0:85b3fd62ea1a | 686 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 687 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| NYX | 0:85b3fd62ea1a | 688 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| NYX | 0:85b3fd62ea1a | 689 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| NYX | 0:85b3fd62ea1a | 690 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| NYX | 0:85b3fd62ea1a | 691 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| NYX | 0:85b3fd62ea1a | 692 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| NYX | 0:85b3fd62ea1a | 693 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| NYX | 0:85b3fd62ea1a | 694 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| NYX | 0:85b3fd62ea1a | 695 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) |
| NYX | 0:85b3fd62ea1a | 696 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| NYX | 0:85b3fd62ea1a | 697 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| NYX | 0:85b3fd62ea1a | 698 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| NYX | 0:85b3fd62ea1a | 699 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) |
| NYX | 0:85b3fd62ea1a | 700 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF |
| NYX | 0:85b3fd62ea1a | 701 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 |
| NYX | 0:85b3fd62ea1a | 702 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) |
| NYX | 0:85b3fd62ea1a | 703 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) |
| NYX | 0:85b3fd62ea1a | 704 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| NYX | 0:85b3fd62ea1a | 705 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| NYX | 0:85b3fd62ea1a | 706 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 707 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| NYX | 0:85b3fd62ea1a | 708 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| NYX | 0:85b3fd62ea1a | 709 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| NYX | 0:85b3fd62ea1a | 710 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| NYX | 0:85b3fd62ea1a | 711 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| NYX | 0:85b3fd62ea1a | 712 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) |
| NYX | 0:85b3fd62ea1a | 713 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) |
| NYX | 0:85b3fd62ea1a | 714 | * |
| NYX | 0:85b3fd62ea1a | 715 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 716 | * @retval None |
| NYX | 0:85b3fd62ea1a | 717 | */ |
| NYX | 0:85b3fd62ea1a | 718 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 719 | { |
| NYX | 0:85b3fd62ea1a | 720 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 721 | SET_BIT(RCC->AHB1LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 722 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 723 | tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 724 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 725 | } |
| NYX | 0:85b3fd62ea1a | 726 | |
| NYX | 0:85b3fd62ea1a | 727 | /** |
| NYX | 0:85b3fd62ea1a | 728 | * @brief Disable AHB1 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 729 | * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 730 | * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 731 | * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 732 | * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 733 | * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 734 | * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 735 | * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 736 | * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 737 | * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 738 | * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 739 | * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 740 | * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 741 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 742 | * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 743 | * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 744 | * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 745 | * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 746 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 747 | * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 748 | * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 749 | * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 750 | * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 751 | * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 752 | * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 753 | * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 754 | * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 755 | * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 756 | * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower |
| NYX | 0:85b3fd62ea1a | 757 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 758 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| NYX | 0:85b3fd62ea1a | 759 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| NYX | 0:85b3fd62ea1a | 760 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| NYX | 0:85b3fd62ea1a | 761 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| NYX | 0:85b3fd62ea1a | 762 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| NYX | 0:85b3fd62ea1a | 763 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| NYX | 0:85b3fd62ea1a | 764 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| NYX | 0:85b3fd62ea1a | 765 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) |
| NYX | 0:85b3fd62ea1a | 766 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) |
| NYX | 0:85b3fd62ea1a | 767 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| NYX | 0:85b3fd62ea1a | 768 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| NYX | 0:85b3fd62ea1a | 769 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| NYX | 0:85b3fd62ea1a | 770 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) |
| NYX | 0:85b3fd62ea1a | 771 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF |
| NYX | 0:85b3fd62ea1a | 772 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 |
| NYX | 0:85b3fd62ea1a | 773 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) |
| NYX | 0:85b3fd62ea1a | 774 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) |
| NYX | 0:85b3fd62ea1a | 775 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| NYX | 0:85b3fd62ea1a | 776 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| NYX | 0:85b3fd62ea1a | 777 | * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 778 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| NYX | 0:85b3fd62ea1a | 779 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| NYX | 0:85b3fd62ea1a | 780 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| NYX | 0:85b3fd62ea1a | 781 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| NYX | 0:85b3fd62ea1a | 782 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| NYX | 0:85b3fd62ea1a | 783 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) |
| NYX | 0:85b3fd62ea1a | 784 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) |
| NYX | 0:85b3fd62ea1a | 785 | * |
| NYX | 0:85b3fd62ea1a | 786 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 787 | * @retval None |
| NYX | 0:85b3fd62ea1a | 788 | */ |
| NYX | 0:85b3fd62ea1a | 789 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 790 | { |
| NYX | 0:85b3fd62ea1a | 791 | CLEAR_BIT(RCC->AHB1LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 792 | } |
| NYX | 0:85b3fd62ea1a | 793 | |
| NYX | 0:85b3fd62ea1a | 794 | /** |
| NYX | 0:85b3fd62ea1a | 795 | * @} |
| NYX | 0:85b3fd62ea1a | 796 | */ |
| NYX | 0:85b3fd62ea1a | 797 | |
| NYX | 0:85b3fd62ea1a | 798 | #if defined(RCC_AHB2_SUPPORT) |
| NYX | 0:85b3fd62ea1a | 799 | /** @defgroup BUS_LL_EF_AHB2 AHB2 |
| NYX | 0:85b3fd62ea1a | 800 | * @{ |
| NYX | 0:85b3fd62ea1a | 801 | */ |
| NYX | 0:85b3fd62ea1a | 802 | |
| NYX | 0:85b3fd62ea1a | 803 | /** |
| NYX | 0:85b3fd62ea1a | 804 | * @brief Enable AHB2 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 805 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 806 | * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 807 | * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 808 | * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 809 | * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 810 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock |
| NYX | 0:85b3fd62ea1a | 811 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 812 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| NYX | 0:85b3fd62ea1a | 813 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| NYX | 0:85b3fd62ea1a | 814 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| NYX | 0:85b3fd62ea1a | 815 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| NYX | 0:85b3fd62ea1a | 816 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 817 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| NYX | 0:85b3fd62ea1a | 818 | * |
| NYX | 0:85b3fd62ea1a | 819 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 820 | * @retval None |
| NYX | 0:85b3fd62ea1a | 821 | */ |
| NYX | 0:85b3fd62ea1a | 822 | __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 823 | { |
| NYX | 0:85b3fd62ea1a | 824 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 825 | SET_BIT(RCC->AHB2ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 826 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 827 | tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 828 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 829 | } |
| NYX | 0:85b3fd62ea1a | 830 | |
| NYX | 0:85b3fd62ea1a | 831 | /** |
| NYX | 0:85b3fd62ea1a | 832 | * @brief Check if AHB2 peripheral clock is enabled or not |
| NYX | 0:85b3fd62ea1a | 833 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 834 | * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 835 | * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 836 | * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 837 | * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 838 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock |
| NYX | 0:85b3fd62ea1a | 839 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 840 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| NYX | 0:85b3fd62ea1a | 841 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| NYX | 0:85b3fd62ea1a | 842 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| NYX | 0:85b3fd62ea1a | 843 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| NYX | 0:85b3fd62ea1a | 844 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 845 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| NYX | 0:85b3fd62ea1a | 846 | * |
| NYX | 0:85b3fd62ea1a | 847 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 848 | * @retval State of Periphs (1 or 0). |
| NYX | 0:85b3fd62ea1a | 849 | */ |
| NYX | 0:85b3fd62ea1a | 850 | __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 851 | { |
| NYX | 0:85b3fd62ea1a | 852 | return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); |
| NYX | 0:85b3fd62ea1a | 853 | } |
| NYX | 0:85b3fd62ea1a | 854 | |
| NYX | 0:85b3fd62ea1a | 855 | /** |
| NYX | 0:85b3fd62ea1a | 856 | * @brief Disable AHB2 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 857 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 858 | * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 859 | * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 860 | * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 861 | * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 862 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock |
| NYX | 0:85b3fd62ea1a | 863 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 864 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| NYX | 0:85b3fd62ea1a | 865 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| NYX | 0:85b3fd62ea1a | 866 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| NYX | 0:85b3fd62ea1a | 867 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| NYX | 0:85b3fd62ea1a | 868 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 869 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| NYX | 0:85b3fd62ea1a | 870 | * |
| NYX | 0:85b3fd62ea1a | 871 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 872 | * @retval None |
| NYX | 0:85b3fd62ea1a | 873 | */ |
| NYX | 0:85b3fd62ea1a | 874 | __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 875 | { |
| NYX | 0:85b3fd62ea1a | 876 | CLEAR_BIT(RCC->AHB2ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 877 | } |
| NYX | 0:85b3fd62ea1a | 878 | |
| NYX | 0:85b3fd62ea1a | 879 | /** |
| NYX | 0:85b3fd62ea1a | 880 | * @brief Force AHB2 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 881 | * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 882 | * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 883 | * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 884 | * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 885 | * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 886 | * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset |
| NYX | 0:85b3fd62ea1a | 887 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 888 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| NYX | 0:85b3fd62ea1a | 889 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| NYX | 0:85b3fd62ea1a | 890 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| NYX | 0:85b3fd62ea1a | 891 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| NYX | 0:85b3fd62ea1a | 892 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| NYX | 0:85b3fd62ea1a | 893 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 894 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| NYX | 0:85b3fd62ea1a | 895 | * |
| NYX | 0:85b3fd62ea1a | 896 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 897 | * @retval None |
| NYX | 0:85b3fd62ea1a | 898 | */ |
| NYX | 0:85b3fd62ea1a | 899 | __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 900 | { |
| NYX | 0:85b3fd62ea1a | 901 | SET_BIT(RCC->AHB2RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 902 | } |
| NYX | 0:85b3fd62ea1a | 903 | |
| NYX | 0:85b3fd62ea1a | 904 | /** |
| NYX | 0:85b3fd62ea1a | 905 | * @brief Release AHB2 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 906 | * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 907 | * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 908 | * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 909 | * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 910 | * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 911 | * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset |
| NYX | 0:85b3fd62ea1a | 912 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 913 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| NYX | 0:85b3fd62ea1a | 914 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| NYX | 0:85b3fd62ea1a | 915 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| NYX | 0:85b3fd62ea1a | 916 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| NYX | 0:85b3fd62ea1a | 917 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| NYX | 0:85b3fd62ea1a | 918 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 919 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| NYX | 0:85b3fd62ea1a | 920 | * |
| NYX | 0:85b3fd62ea1a | 921 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 922 | * @retval None |
| NYX | 0:85b3fd62ea1a | 923 | */ |
| NYX | 0:85b3fd62ea1a | 924 | __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 925 | { |
| NYX | 0:85b3fd62ea1a | 926 | CLEAR_BIT(RCC->AHB2RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 927 | } |
| NYX | 0:85b3fd62ea1a | 928 | |
| NYX | 0:85b3fd62ea1a | 929 | /** |
| NYX | 0:85b3fd62ea1a | 930 | * @brief Enable AHB2 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 931 | * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 932 | * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 933 | * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 934 | * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 935 | * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 936 | * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower |
| NYX | 0:85b3fd62ea1a | 937 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 938 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| NYX | 0:85b3fd62ea1a | 939 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| NYX | 0:85b3fd62ea1a | 940 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| NYX | 0:85b3fd62ea1a | 941 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| NYX | 0:85b3fd62ea1a | 942 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 943 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| NYX | 0:85b3fd62ea1a | 944 | * |
| NYX | 0:85b3fd62ea1a | 945 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 946 | * @retval None |
| NYX | 0:85b3fd62ea1a | 947 | */ |
| NYX | 0:85b3fd62ea1a | 948 | __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 949 | { |
| NYX | 0:85b3fd62ea1a | 950 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 951 | SET_BIT(RCC->AHB2LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 952 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 953 | tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 954 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 955 | } |
| NYX | 0:85b3fd62ea1a | 956 | |
| NYX | 0:85b3fd62ea1a | 957 | /** |
| NYX | 0:85b3fd62ea1a | 958 | * @brief Disable AHB2 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 959 | * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 960 | * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 961 | * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 962 | * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 963 | * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 964 | * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower |
| NYX | 0:85b3fd62ea1a | 965 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 966 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| NYX | 0:85b3fd62ea1a | 967 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| NYX | 0:85b3fd62ea1a | 968 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| NYX | 0:85b3fd62ea1a | 969 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| NYX | 0:85b3fd62ea1a | 970 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) |
| NYX | 0:85b3fd62ea1a | 971 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| NYX | 0:85b3fd62ea1a | 972 | * |
| NYX | 0:85b3fd62ea1a | 973 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 974 | * @retval None |
| NYX | 0:85b3fd62ea1a | 975 | */ |
| NYX | 0:85b3fd62ea1a | 976 | __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 977 | { |
| NYX | 0:85b3fd62ea1a | 978 | CLEAR_BIT(RCC->AHB2LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 979 | } |
| NYX | 0:85b3fd62ea1a | 980 | |
| NYX | 0:85b3fd62ea1a | 981 | /** |
| NYX | 0:85b3fd62ea1a | 982 | * @} |
| NYX | 0:85b3fd62ea1a | 983 | */ |
| NYX | 0:85b3fd62ea1a | 984 | #endif /* RCC_AHB2_SUPPORT */ |
| NYX | 0:85b3fd62ea1a | 985 | |
| NYX | 0:85b3fd62ea1a | 986 | #if defined(RCC_AHB3_SUPPORT) |
| NYX | 0:85b3fd62ea1a | 987 | /** @defgroup BUS_LL_EF_AHB3 AHB3 |
| NYX | 0:85b3fd62ea1a | 988 | * @{ |
| NYX | 0:85b3fd62ea1a | 989 | */ |
| NYX | 0:85b3fd62ea1a | 990 | |
| NYX | 0:85b3fd62ea1a | 991 | /** |
| NYX | 0:85b3fd62ea1a | 992 | * @brief Enable AHB3 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 993 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 994 | * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 995 | * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock |
| NYX | 0:85b3fd62ea1a | 996 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 997 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| NYX | 0:85b3fd62ea1a | 998 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) |
| NYX | 0:85b3fd62ea1a | 999 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) |
| NYX | 0:85b3fd62ea1a | 1000 | * |
| NYX | 0:85b3fd62ea1a | 1001 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1002 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1003 | */ |
| NYX | 0:85b3fd62ea1a | 1004 | __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1005 | { |
| NYX | 0:85b3fd62ea1a | 1006 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 1007 | SET_BIT(RCC->AHB3ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1008 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 1009 | tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1010 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 1011 | } |
| NYX | 0:85b3fd62ea1a | 1012 | |
| NYX | 0:85b3fd62ea1a | 1013 | /** |
| NYX | 0:85b3fd62ea1a | 1014 | * @brief Check if AHB3 peripheral clock is enabled or not |
| NYX | 0:85b3fd62ea1a | 1015 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1016 | * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1017 | * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock |
| NYX | 0:85b3fd62ea1a | 1018 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1019 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| NYX | 0:85b3fd62ea1a | 1020 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) |
| NYX | 0:85b3fd62ea1a | 1021 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) |
| NYX | 0:85b3fd62ea1a | 1022 | * |
| NYX | 0:85b3fd62ea1a | 1023 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1024 | * @retval State of Periphs (1 or 0). |
| NYX | 0:85b3fd62ea1a | 1025 | */ |
| NYX | 0:85b3fd62ea1a | 1026 | __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1027 | { |
| NYX | 0:85b3fd62ea1a | 1028 | return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); |
| NYX | 0:85b3fd62ea1a | 1029 | } |
| NYX | 0:85b3fd62ea1a | 1030 | |
| NYX | 0:85b3fd62ea1a | 1031 | /** |
| NYX | 0:85b3fd62ea1a | 1032 | * @brief Disable AHB3 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 1033 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1034 | * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1035 | * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock |
| NYX | 0:85b3fd62ea1a | 1036 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1037 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| NYX | 0:85b3fd62ea1a | 1038 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) |
| NYX | 0:85b3fd62ea1a | 1039 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) |
| NYX | 0:85b3fd62ea1a | 1040 | * |
| NYX | 0:85b3fd62ea1a | 1041 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1042 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1043 | */ |
| NYX | 0:85b3fd62ea1a | 1044 | __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1045 | { |
| NYX | 0:85b3fd62ea1a | 1046 | CLEAR_BIT(RCC->AHB3ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1047 | } |
| NYX | 0:85b3fd62ea1a | 1048 | |
| NYX | 0:85b3fd62ea1a | 1049 | /** |
| NYX | 0:85b3fd62ea1a | 1050 | * @brief Force AHB3 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 1051 | * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1052 | * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1053 | * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset |
| NYX | 0:85b3fd62ea1a | 1054 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1055 | * @arg @ref LL_AHB3_GRP1_PERIPH_ALL |
| NYX | 0:85b3fd62ea1a | 1056 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| NYX | 0:85b3fd62ea1a | 1057 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) |
| NYX | 0:85b3fd62ea1a | 1058 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) |
| NYX | 0:85b3fd62ea1a | 1059 | * |
| NYX | 0:85b3fd62ea1a | 1060 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1061 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1062 | */ |
| NYX | 0:85b3fd62ea1a | 1063 | __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1064 | { |
| NYX | 0:85b3fd62ea1a | 1065 | SET_BIT(RCC->AHB3RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1066 | } |
| NYX | 0:85b3fd62ea1a | 1067 | |
| NYX | 0:85b3fd62ea1a | 1068 | /** |
| NYX | 0:85b3fd62ea1a | 1069 | * @brief Release AHB3 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 1070 | * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1071 | * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1072 | * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset |
| NYX | 0:85b3fd62ea1a | 1073 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1074 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| NYX | 0:85b3fd62ea1a | 1075 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| NYX | 0:85b3fd62ea1a | 1076 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) |
| NYX | 0:85b3fd62ea1a | 1077 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) |
| NYX | 0:85b3fd62ea1a | 1078 | * |
| NYX | 0:85b3fd62ea1a | 1079 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1080 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1081 | */ |
| NYX | 0:85b3fd62ea1a | 1082 | __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1083 | { |
| NYX | 0:85b3fd62ea1a | 1084 | CLEAR_BIT(RCC->AHB3RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1085 | } |
| NYX | 0:85b3fd62ea1a | 1086 | |
| NYX | 0:85b3fd62ea1a | 1087 | /** |
| NYX | 0:85b3fd62ea1a | 1088 | * @brief Enable AHB3 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 1089 | * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1090 | * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1091 | * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower |
| NYX | 0:85b3fd62ea1a | 1092 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1093 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| NYX | 0:85b3fd62ea1a | 1094 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) |
| NYX | 0:85b3fd62ea1a | 1095 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) |
| NYX | 0:85b3fd62ea1a | 1096 | * |
| NYX | 0:85b3fd62ea1a | 1097 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1098 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1099 | */ |
| NYX | 0:85b3fd62ea1a | 1100 | __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1101 | { |
| NYX | 0:85b3fd62ea1a | 1102 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 1103 | SET_BIT(RCC->AHB3LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1104 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 1105 | tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1106 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 1107 | } |
| NYX | 0:85b3fd62ea1a | 1108 | |
| NYX | 0:85b3fd62ea1a | 1109 | /** |
| NYX | 0:85b3fd62ea1a | 1110 | * @brief Disable AHB3 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 1111 | * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1112 | * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1113 | * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower |
| NYX | 0:85b3fd62ea1a | 1114 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1115 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| NYX | 0:85b3fd62ea1a | 1116 | * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) |
| NYX | 0:85b3fd62ea1a | 1117 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) |
| NYX | 0:85b3fd62ea1a | 1118 | * |
| NYX | 0:85b3fd62ea1a | 1119 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1120 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1121 | */ |
| NYX | 0:85b3fd62ea1a | 1122 | __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1123 | { |
| NYX | 0:85b3fd62ea1a | 1124 | CLEAR_BIT(RCC->AHB3LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1125 | } |
| NYX | 0:85b3fd62ea1a | 1126 | |
| NYX | 0:85b3fd62ea1a | 1127 | /** |
| NYX | 0:85b3fd62ea1a | 1128 | * @} |
| NYX | 0:85b3fd62ea1a | 1129 | */ |
| NYX | 0:85b3fd62ea1a | 1130 | #endif /* RCC_AHB3_SUPPORT */ |
| NYX | 0:85b3fd62ea1a | 1131 | |
| NYX | 0:85b3fd62ea1a | 1132 | /** @defgroup BUS_LL_EF_APB1 APB1 |
| NYX | 0:85b3fd62ea1a | 1133 | * @{ |
| NYX | 0:85b3fd62ea1a | 1134 | */ |
| NYX | 0:85b3fd62ea1a | 1135 | |
| NYX | 0:85b3fd62ea1a | 1136 | /** |
| NYX | 0:85b3fd62ea1a | 1137 | * @brief Enable APB1 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 1138 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1139 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1140 | * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1141 | * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1142 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1143 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1144 | * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1145 | * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1146 | * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1147 | * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1148 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1149 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1150 | * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1151 | * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1152 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1153 | * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1154 | * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1155 | * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1156 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1157 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1158 | * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1159 | * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1160 | * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1161 | * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1162 | * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1163 | * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1164 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1165 | * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1166 | * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1167 | * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1168 | * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock |
| NYX | 0:85b3fd62ea1a | 1169 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1170 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| NYX | 0:85b3fd62ea1a | 1171 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| NYX | 0:85b3fd62ea1a | 1172 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| NYX | 0:85b3fd62ea1a | 1173 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| NYX | 0:85b3fd62ea1a | 1174 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| NYX | 0:85b3fd62ea1a | 1175 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| NYX | 0:85b3fd62ea1a | 1176 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| NYX | 0:85b3fd62ea1a | 1177 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| NYX | 0:85b3fd62ea1a | 1178 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| NYX | 0:85b3fd62ea1a | 1179 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) |
| NYX | 0:85b3fd62ea1a | 1180 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| NYX | 0:85b3fd62ea1a | 1181 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| NYX | 0:85b3fd62ea1a | 1182 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| NYX | 0:85b3fd62ea1a | 1183 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| NYX | 0:85b3fd62ea1a | 1184 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| NYX | 0:85b3fd62ea1a | 1185 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| NYX | 0:85b3fd62ea1a | 1186 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| NYX | 0:85b3fd62ea1a | 1187 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| NYX | 0:85b3fd62ea1a | 1188 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| NYX | 0:85b3fd62ea1a | 1189 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| NYX | 0:85b3fd62ea1a | 1190 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| NYX | 0:85b3fd62ea1a | 1191 | * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) |
| NYX | 0:85b3fd62ea1a | 1192 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
| NYX | 0:85b3fd62ea1a | 1193 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| NYX | 0:85b3fd62ea1a | 1194 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| NYX | 0:85b3fd62ea1a | 1195 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| NYX | 0:85b3fd62ea1a | 1196 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| NYX | 0:85b3fd62ea1a | 1197 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| NYX | 0:85b3fd62ea1a | 1198 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) |
| NYX | 0:85b3fd62ea1a | 1199 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) |
| NYX | 0:85b3fd62ea1a | 1200 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| NYX | 0:85b3fd62ea1a | 1201 | * |
| NYX | 0:85b3fd62ea1a | 1202 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1203 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1204 | */ |
| NYX | 0:85b3fd62ea1a | 1205 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1206 | { |
| NYX | 0:85b3fd62ea1a | 1207 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 1208 | SET_BIT(RCC->APB1ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1209 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 1210 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1211 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 1212 | } |
| NYX | 0:85b3fd62ea1a | 1213 | |
| NYX | 0:85b3fd62ea1a | 1214 | /** |
| NYX | 0:85b3fd62ea1a | 1215 | * @brief Check if APB1 peripheral clock is enabled or not |
| NYX | 0:85b3fd62ea1a | 1216 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1217 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1218 | * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1219 | * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1220 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1221 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1222 | * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1223 | * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1224 | * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1225 | * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1226 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1227 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1228 | * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1229 | * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1230 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1231 | * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1232 | * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1233 | * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1234 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1235 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1236 | * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1237 | * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1238 | * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1239 | * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1240 | * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1241 | * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1242 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1243 | * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1244 | * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1245 | * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1246 | * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock |
| NYX | 0:85b3fd62ea1a | 1247 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1248 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| NYX | 0:85b3fd62ea1a | 1249 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| NYX | 0:85b3fd62ea1a | 1250 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| NYX | 0:85b3fd62ea1a | 1251 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| NYX | 0:85b3fd62ea1a | 1252 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| NYX | 0:85b3fd62ea1a | 1253 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| NYX | 0:85b3fd62ea1a | 1254 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| NYX | 0:85b3fd62ea1a | 1255 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| NYX | 0:85b3fd62ea1a | 1256 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| NYX | 0:85b3fd62ea1a | 1257 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) |
| NYX | 0:85b3fd62ea1a | 1258 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| NYX | 0:85b3fd62ea1a | 1259 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| NYX | 0:85b3fd62ea1a | 1260 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| NYX | 0:85b3fd62ea1a | 1261 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| NYX | 0:85b3fd62ea1a | 1262 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| NYX | 0:85b3fd62ea1a | 1263 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| NYX | 0:85b3fd62ea1a | 1264 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| NYX | 0:85b3fd62ea1a | 1265 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| NYX | 0:85b3fd62ea1a | 1266 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| NYX | 0:85b3fd62ea1a | 1267 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| NYX | 0:85b3fd62ea1a | 1268 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| NYX | 0:85b3fd62ea1a | 1269 | * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) |
| NYX | 0:85b3fd62ea1a | 1270 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
| NYX | 0:85b3fd62ea1a | 1271 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| NYX | 0:85b3fd62ea1a | 1272 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| NYX | 0:85b3fd62ea1a | 1273 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| NYX | 0:85b3fd62ea1a | 1274 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| NYX | 0:85b3fd62ea1a | 1275 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| NYX | 0:85b3fd62ea1a | 1276 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) |
| NYX | 0:85b3fd62ea1a | 1277 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) |
| NYX | 0:85b3fd62ea1a | 1278 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| NYX | 0:85b3fd62ea1a | 1279 | * |
| NYX | 0:85b3fd62ea1a | 1280 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1281 | * @retval State of Periphs (1 or 0). |
| NYX | 0:85b3fd62ea1a | 1282 | */ |
| NYX | 0:85b3fd62ea1a | 1283 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1284 | { |
| NYX | 0:85b3fd62ea1a | 1285 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
| NYX | 0:85b3fd62ea1a | 1286 | } |
| NYX | 0:85b3fd62ea1a | 1287 | |
| NYX | 0:85b3fd62ea1a | 1288 | /** |
| NYX | 0:85b3fd62ea1a | 1289 | * @brief Disable APB1 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 1290 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1291 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1292 | * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1293 | * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1294 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1295 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1296 | * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1297 | * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1298 | * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1299 | * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1300 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1301 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1302 | * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1303 | * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1304 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1305 | * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1306 | * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1307 | * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1308 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1309 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1310 | * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1311 | * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1312 | * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1313 | * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1314 | * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1315 | * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1316 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1317 | * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1318 | * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1319 | * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1320 | * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock |
| NYX | 0:85b3fd62ea1a | 1321 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1322 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| NYX | 0:85b3fd62ea1a | 1323 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| NYX | 0:85b3fd62ea1a | 1324 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| NYX | 0:85b3fd62ea1a | 1325 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| NYX | 0:85b3fd62ea1a | 1326 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| NYX | 0:85b3fd62ea1a | 1327 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| NYX | 0:85b3fd62ea1a | 1328 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| NYX | 0:85b3fd62ea1a | 1329 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| NYX | 0:85b3fd62ea1a | 1330 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| NYX | 0:85b3fd62ea1a | 1331 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) |
| NYX | 0:85b3fd62ea1a | 1332 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| NYX | 0:85b3fd62ea1a | 1333 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| NYX | 0:85b3fd62ea1a | 1334 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| NYX | 0:85b3fd62ea1a | 1335 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| NYX | 0:85b3fd62ea1a | 1336 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| NYX | 0:85b3fd62ea1a | 1337 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| NYX | 0:85b3fd62ea1a | 1338 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| NYX | 0:85b3fd62ea1a | 1339 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| NYX | 0:85b3fd62ea1a | 1340 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| NYX | 0:85b3fd62ea1a | 1341 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| NYX | 0:85b3fd62ea1a | 1342 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| NYX | 0:85b3fd62ea1a | 1343 | * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) |
| NYX | 0:85b3fd62ea1a | 1344 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
| NYX | 0:85b3fd62ea1a | 1345 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| NYX | 0:85b3fd62ea1a | 1346 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| NYX | 0:85b3fd62ea1a | 1347 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| NYX | 0:85b3fd62ea1a | 1348 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| NYX | 0:85b3fd62ea1a | 1349 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| NYX | 0:85b3fd62ea1a | 1350 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) |
| NYX | 0:85b3fd62ea1a | 1351 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) |
| NYX | 0:85b3fd62ea1a | 1352 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| NYX | 0:85b3fd62ea1a | 1353 | * |
| NYX | 0:85b3fd62ea1a | 1354 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1355 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1356 | */ |
| NYX | 0:85b3fd62ea1a | 1357 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1358 | { |
| NYX | 0:85b3fd62ea1a | 1359 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1360 | } |
| NYX | 0:85b3fd62ea1a | 1361 | |
| NYX | 0:85b3fd62ea1a | 1362 | /** |
| NYX | 0:85b3fd62ea1a | 1363 | * @brief Force APB1 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 1364 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1365 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1366 | * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1367 | * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1368 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1369 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1370 | * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1371 | * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1372 | * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1373 | * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1374 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1375 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1376 | * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1377 | * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1378 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1379 | * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1380 | * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1381 | * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1382 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1383 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1384 | * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1385 | * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1386 | * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1387 | * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1388 | * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1389 | * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1390 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1391 | * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1392 | * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1393 | * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset |
| NYX | 0:85b3fd62ea1a | 1394 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1395 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| NYX | 0:85b3fd62ea1a | 1396 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| NYX | 0:85b3fd62ea1a | 1397 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| NYX | 0:85b3fd62ea1a | 1398 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| NYX | 0:85b3fd62ea1a | 1399 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| NYX | 0:85b3fd62ea1a | 1400 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| NYX | 0:85b3fd62ea1a | 1401 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| NYX | 0:85b3fd62ea1a | 1402 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| NYX | 0:85b3fd62ea1a | 1403 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| NYX | 0:85b3fd62ea1a | 1404 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) |
| NYX | 0:85b3fd62ea1a | 1405 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| NYX | 0:85b3fd62ea1a | 1406 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| NYX | 0:85b3fd62ea1a | 1407 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| NYX | 0:85b3fd62ea1a | 1408 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| NYX | 0:85b3fd62ea1a | 1409 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| NYX | 0:85b3fd62ea1a | 1410 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| NYX | 0:85b3fd62ea1a | 1411 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| NYX | 0:85b3fd62ea1a | 1412 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| NYX | 0:85b3fd62ea1a | 1413 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| NYX | 0:85b3fd62ea1a | 1414 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| NYX | 0:85b3fd62ea1a | 1415 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| NYX | 0:85b3fd62ea1a | 1416 | * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) |
| NYX | 0:85b3fd62ea1a | 1417 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
| NYX | 0:85b3fd62ea1a | 1418 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| NYX | 0:85b3fd62ea1a | 1419 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| NYX | 0:85b3fd62ea1a | 1420 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| NYX | 0:85b3fd62ea1a | 1421 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| NYX | 0:85b3fd62ea1a | 1422 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| NYX | 0:85b3fd62ea1a | 1423 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) |
| NYX | 0:85b3fd62ea1a | 1424 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) |
| NYX | 0:85b3fd62ea1a | 1425 | * |
| NYX | 0:85b3fd62ea1a | 1426 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1427 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1428 | */ |
| NYX | 0:85b3fd62ea1a | 1429 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1430 | { |
| NYX | 0:85b3fd62ea1a | 1431 | SET_BIT(RCC->APB1RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1432 | } |
| NYX | 0:85b3fd62ea1a | 1433 | |
| NYX | 0:85b3fd62ea1a | 1434 | /** |
| NYX | 0:85b3fd62ea1a | 1435 | * @brief Release APB1 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 1436 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1437 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1438 | * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1439 | * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1440 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1441 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1442 | * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1443 | * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1444 | * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1445 | * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1446 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1447 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1448 | * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1449 | * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1450 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1451 | * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1452 | * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1453 | * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1454 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1455 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1456 | * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1457 | * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1458 | * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1459 | * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1460 | * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1461 | * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1462 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1463 | * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1464 | * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1465 | * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset |
| NYX | 0:85b3fd62ea1a | 1466 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1467 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| NYX | 0:85b3fd62ea1a | 1468 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| NYX | 0:85b3fd62ea1a | 1469 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| NYX | 0:85b3fd62ea1a | 1470 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| NYX | 0:85b3fd62ea1a | 1471 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| NYX | 0:85b3fd62ea1a | 1472 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| NYX | 0:85b3fd62ea1a | 1473 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| NYX | 0:85b3fd62ea1a | 1474 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| NYX | 0:85b3fd62ea1a | 1475 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| NYX | 0:85b3fd62ea1a | 1476 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) |
| NYX | 0:85b3fd62ea1a | 1477 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| NYX | 0:85b3fd62ea1a | 1478 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| NYX | 0:85b3fd62ea1a | 1479 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| NYX | 0:85b3fd62ea1a | 1480 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| NYX | 0:85b3fd62ea1a | 1481 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| NYX | 0:85b3fd62ea1a | 1482 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| NYX | 0:85b3fd62ea1a | 1483 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| NYX | 0:85b3fd62ea1a | 1484 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| NYX | 0:85b3fd62ea1a | 1485 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| NYX | 0:85b3fd62ea1a | 1486 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| NYX | 0:85b3fd62ea1a | 1487 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| NYX | 0:85b3fd62ea1a | 1488 | * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) |
| NYX | 0:85b3fd62ea1a | 1489 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
| NYX | 0:85b3fd62ea1a | 1490 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| NYX | 0:85b3fd62ea1a | 1491 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| NYX | 0:85b3fd62ea1a | 1492 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| NYX | 0:85b3fd62ea1a | 1493 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| NYX | 0:85b3fd62ea1a | 1494 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| NYX | 0:85b3fd62ea1a | 1495 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) |
| NYX | 0:85b3fd62ea1a | 1496 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) |
| NYX | 0:85b3fd62ea1a | 1497 | * |
| NYX | 0:85b3fd62ea1a | 1498 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1499 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1500 | */ |
| NYX | 0:85b3fd62ea1a | 1501 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1502 | { |
| NYX | 0:85b3fd62ea1a | 1503 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1504 | } |
| NYX | 0:85b3fd62ea1a | 1505 | |
| NYX | 0:85b3fd62ea1a | 1506 | /** |
| NYX | 0:85b3fd62ea1a | 1507 | * @brief Enable APB1 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 1508 | * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1509 | * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1510 | * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1511 | * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1512 | * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1513 | * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1514 | * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1515 | * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1516 | * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1517 | * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1518 | * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1519 | * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1520 | * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1521 | * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1522 | * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1523 | * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1524 | * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1525 | * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1526 | * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1527 | * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1528 | * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1529 | * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1530 | * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1531 | * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1532 | * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1533 | * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1534 | * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1535 | * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1536 | * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1537 | * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1538 | * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower |
| NYX | 0:85b3fd62ea1a | 1539 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1540 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| NYX | 0:85b3fd62ea1a | 1541 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| NYX | 0:85b3fd62ea1a | 1542 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| NYX | 0:85b3fd62ea1a | 1543 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| NYX | 0:85b3fd62ea1a | 1544 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| NYX | 0:85b3fd62ea1a | 1545 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| NYX | 0:85b3fd62ea1a | 1546 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| NYX | 0:85b3fd62ea1a | 1547 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| NYX | 0:85b3fd62ea1a | 1548 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| NYX | 0:85b3fd62ea1a | 1549 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) |
| NYX | 0:85b3fd62ea1a | 1550 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| NYX | 0:85b3fd62ea1a | 1551 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| NYX | 0:85b3fd62ea1a | 1552 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| NYX | 0:85b3fd62ea1a | 1553 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| NYX | 0:85b3fd62ea1a | 1554 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| NYX | 0:85b3fd62ea1a | 1555 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| NYX | 0:85b3fd62ea1a | 1556 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| NYX | 0:85b3fd62ea1a | 1557 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| NYX | 0:85b3fd62ea1a | 1558 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| NYX | 0:85b3fd62ea1a | 1559 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| NYX | 0:85b3fd62ea1a | 1560 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| NYX | 0:85b3fd62ea1a | 1561 | * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) |
| NYX | 0:85b3fd62ea1a | 1562 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
| NYX | 0:85b3fd62ea1a | 1563 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| NYX | 0:85b3fd62ea1a | 1564 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| NYX | 0:85b3fd62ea1a | 1565 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| NYX | 0:85b3fd62ea1a | 1566 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| NYX | 0:85b3fd62ea1a | 1567 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| NYX | 0:85b3fd62ea1a | 1568 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) |
| NYX | 0:85b3fd62ea1a | 1569 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) |
| NYX | 0:85b3fd62ea1a | 1570 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| NYX | 0:85b3fd62ea1a | 1571 | * |
| NYX | 0:85b3fd62ea1a | 1572 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1573 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1574 | */ |
| NYX | 0:85b3fd62ea1a | 1575 | __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1576 | { |
| NYX | 0:85b3fd62ea1a | 1577 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 1578 | SET_BIT(RCC->APB1LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1579 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 1580 | tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1581 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 1582 | } |
| NYX | 0:85b3fd62ea1a | 1583 | |
| NYX | 0:85b3fd62ea1a | 1584 | /** |
| NYX | 0:85b3fd62ea1a | 1585 | * @brief Disable APB1 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 1586 | * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1587 | * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1588 | * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1589 | * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1590 | * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1591 | * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1592 | * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1593 | * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1594 | * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1595 | * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1596 | * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1597 | * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1598 | * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1599 | * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1600 | * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1601 | * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1602 | * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1603 | * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1604 | * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1605 | * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1606 | * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1607 | * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1608 | * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1609 | * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1610 | * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1611 | * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1612 | * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1613 | * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1614 | * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1615 | * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1616 | * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower |
| NYX | 0:85b3fd62ea1a | 1617 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1618 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| NYX | 0:85b3fd62ea1a | 1619 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| NYX | 0:85b3fd62ea1a | 1620 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| NYX | 0:85b3fd62ea1a | 1621 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| NYX | 0:85b3fd62ea1a | 1622 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| NYX | 0:85b3fd62ea1a | 1623 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| NYX | 0:85b3fd62ea1a | 1624 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) |
| NYX | 0:85b3fd62ea1a | 1625 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) |
| NYX | 0:85b3fd62ea1a | 1626 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) |
| NYX | 0:85b3fd62ea1a | 1627 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) |
| NYX | 0:85b3fd62ea1a | 1628 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| NYX | 0:85b3fd62ea1a | 1629 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| NYX | 0:85b3fd62ea1a | 1630 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| NYX | 0:85b3fd62ea1a | 1631 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| NYX | 0:85b3fd62ea1a | 1632 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| NYX | 0:85b3fd62ea1a | 1633 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| NYX | 0:85b3fd62ea1a | 1634 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| NYX | 0:85b3fd62ea1a | 1635 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| NYX | 0:85b3fd62ea1a | 1636 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| NYX | 0:85b3fd62ea1a | 1637 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| NYX | 0:85b3fd62ea1a | 1638 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) |
| NYX | 0:85b3fd62ea1a | 1639 | * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) |
| NYX | 0:85b3fd62ea1a | 1640 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) |
| NYX | 0:85b3fd62ea1a | 1641 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| NYX | 0:85b3fd62ea1a | 1642 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| NYX | 0:85b3fd62ea1a | 1643 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| NYX | 0:85b3fd62ea1a | 1644 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| NYX | 0:85b3fd62ea1a | 1645 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| NYX | 0:85b3fd62ea1a | 1646 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) |
| NYX | 0:85b3fd62ea1a | 1647 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) |
| NYX | 0:85b3fd62ea1a | 1648 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| NYX | 0:85b3fd62ea1a | 1649 | * |
| NYX | 0:85b3fd62ea1a | 1650 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1651 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1652 | */ |
| NYX | 0:85b3fd62ea1a | 1653 | __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1654 | { |
| NYX | 0:85b3fd62ea1a | 1655 | CLEAR_BIT(RCC->APB1LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1656 | } |
| NYX | 0:85b3fd62ea1a | 1657 | |
| NYX | 0:85b3fd62ea1a | 1658 | /** |
| NYX | 0:85b3fd62ea1a | 1659 | * @} |
| NYX | 0:85b3fd62ea1a | 1660 | */ |
| NYX | 0:85b3fd62ea1a | 1661 | |
| NYX | 0:85b3fd62ea1a | 1662 | /** @defgroup BUS_LL_EF_APB2 APB2 |
| NYX | 0:85b3fd62ea1a | 1663 | * @{ |
| NYX | 0:85b3fd62ea1a | 1664 | */ |
| NYX | 0:85b3fd62ea1a | 1665 | |
| NYX | 0:85b3fd62ea1a | 1666 | /** |
| NYX | 0:85b3fd62ea1a | 1667 | * @brief Enable APB2 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 1668 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1669 | * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1670 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1671 | * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1672 | * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1673 | * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1674 | * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1675 | * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1676 | * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1677 | * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1678 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1679 | * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1680 | * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1681 | * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1682 | * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1683 | * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1684 | * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1685 | * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1686 | * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1687 | * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1688 | * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1689 | * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1690 | * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1691 | * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n |
| NYX | 0:85b3fd62ea1a | 1692 | * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock |
| NYX | 0:85b3fd62ea1a | 1693 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1694 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| NYX | 0:85b3fd62ea1a | 1695 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| NYX | 0:85b3fd62ea1a | 1696 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| NYX | 0:85b3fd62ea1a | 1697 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) |
| NYX | 0:85b3fd62ea1a | 1698 | * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) |
| NYX | 0:85b3fd62ea1a | 1699 | * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) |
| NYX | 0:85b3fd62ea1a | 1700 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| NYX | 0:85b3fd62ea1a | 1701 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
| NYX | 0:85b3fd62ea1a | 1702 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
| NYX | 0:85b3fd62ea1a | 1703 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| NYX | 0:85b3fd62ea1a | 1704 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| NYX | 0:85b3fd62ea1a | 1705 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| NYX | 0:85b3fd62ea1a | 1706 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| NYX | 0:85b3fd62ea1a | 1707 | * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) |
| NYX | 0:85b3fd62ea1a | 1708 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| NYX | 0:85b3fd62ea1a | 1709 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
| NYX | 0:85b3fd62ea1a | 1710 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| NYX | 0:85b3fd62ea1a | 1711 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) |
| NYX | 0:85b3fd62ea1a | 1712 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| NYX | 0:85b3fd62ea1a | 1713 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) |
| NYX | 0:85b3fd62ea1a | 1714 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| NYX | 0:85b3fd62ea1a | 1715 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| NYX | 0:85b3fd62ea1a | 1716 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| NYX | 0:85b3fd62ea1a | 1717 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| NYX | 0:85b3fd62ea1a | 1718 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) |
| NYX | 0:85b3fd62ea1a | 1719 | |
| NYX | 0:85b3fd62ea1a | 1720 | * |
| NYX | 0:85b3fd62ea1a | 1721 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1722 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1723 | */ |
| NYX | 0:85b3fd62ea1a | 1724 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1725 | { |
| NYX | 0:85b3fd62ea1a | 1726 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 1727 | SET_BIT(RCC->APB2ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1728 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 1729 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1730 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 1731 | } |
| NYX | 0:85b3fd62ea1a | 1732 | |
| NYX | 0:85b3fd62ea1a | 1733 | /** |
| NYX | 0:85b3fd62ea1a | 1734 | * @brief Check if APB2 peripheral clock is enabled or not |
| NYX | 0:85b3fd62ea1a | 1735 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1736 | * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1737 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1738 | * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1739 | * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1740 | * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1741 | * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1742 | * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1743 | * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1744 | * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1745 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1746 | * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1747 | * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1748 | * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1749 | * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1750 | * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1751 | * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1752 | * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1753 | * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1754 | * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1755 | * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1756 | * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1757 | * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1758 | * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n |
| NYX | 0:85b3fd62ea1a | 1759 | * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock |
| NYX | 0:85b3fd62ea1a | 1760 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1761 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| NYX | 0:85b3fd62ea1a | 1762 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| NYX | 0:85b3fd62ea1a | 1763 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| NYX | 0:85b3fd62ea1a | 1764 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) |
| NYX | 0:85b3fd62ea1a | 1765 | * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) |
| NYX | 0:85b3fd62ea1a | 1766 | * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) |
| NYX | 0:85b3fd62ea1a | 1767 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| NYX | 0:85b3fd62ea1a | 1768 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
| NYX | 0:85b3fd62ea1a | 1769 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
| NYX | 0:85b3fd62ea1a | 1770 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| NYX | 0:85b3fd62ea1a | 1771 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| NYX | 0:85b3fd62ea1a | 1772 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| NYX | 0:85b3fd62ea1a | 1773 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| NYX | 0:85b3fd62ea1a | 1774 | * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) |
| NYX | 0:85b3fd62ea1a | 1775 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| NYX | 0:85b3fd62ea1a | 1776 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
| NYX | 0:85b3fd62ea1a | 1777 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| NYX | 0:85b3fd62ea1a | 1778 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) |
| NYX | 0:85b3fd62ea1a | 1779 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| NYX | 0:85b3fd62ea1a | 1780 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) |
| NYX | 0:85b3fd62ea1a | 1781 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| NYX | 0:85b3fd62ea1a | 1782 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| NYX | 0:85b3fd62ea1a | 1783 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| NYX | 0:85b3fd62ea1a | 1784 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| NYX | 0:85b3fd62ea1a | 1785 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) |
| NYX | 0:85b3fd62ea1a | 1786 | * |
| NYX | 0:85b3fd62ea1a | 1787 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1788 | * @retval State of Periphs (1 or 0). |
| NYX | 0:85b3fd62ea1a | 1789 | */ |
| NYX | 0:85b3fd62ea1a | 1790 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1791 | { |
| NYX | 0:85b3fd62ea1a | 1792 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| NYX | 0:85b3fd62ea1a | 1793 | } |
| NYX | 0:85b3fd62ea1a | 1794 | |
| NYX | 0:85b3fd62ea1a | 1795 | /** |
| NYX | 0:85b3fd62ea1a | 1796 | * @brief Disable APB2 peripherals clock. |
| NYX | 0:85b3fd62ea1a | 1797 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1798 | * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1799 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1800 | * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1801 | * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1802 | * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1803 | * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1804 | * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1805 | * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1806 | * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1807 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1808 | * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1809 | * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1810 | * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1811 | * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1812 | * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1813 | * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1814 | * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1815 | * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1816 | * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1817 | * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1818 | * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1819 | * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1820 | * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n |
| NYX | 0:85b3fd62ea1a | 1821 | * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock |
| NYX | 0:85b3fd62ea1a | 1822 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1823 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| NYX | 0:85b3fd62ea1a | 1824 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| NYX | 0:85b3fd62ea1a | 1825 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| NYX | 0:85b3fd62ea1a | 1826 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) |
| NYX | 0:85b3fd62ea1a | 1827 | * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) |
| NYX | 0:85b3fd62ea1a | 1828 | * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) |
| NYX | 0:85b3fd62ea1a | 1829 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| NYX | 0:85b3fd62ea1a | 1830 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
| NYX | 0:85b3fd62ea1a | 1831 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
| NYX | 0:85b3fd62ea1a | 1832 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| NYX | 0:85b3fd62ea1a | 1833 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| NYX | 0:85b3fd62ea1a | 1834 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| NYX | 0:85b3fd62ea1a | 1835 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| NYX | 0:85b3fd62ea1a | 1836 | * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) |
| NYX | 0:85b3fd62ea1a | 1837 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| NYX | 0:85b3fd62ea1a | 1838 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
| NYX | 0:85b3fd62ea1a | 1839 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| NYX | 0:85b3fd62ea1a | 1840 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) |
| NYX | 0:85b3fd62ea1a | 1841 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| NYX | 0:85b3fd62ea1a | 1842 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) |
| NYX | 0:85b3fd62ea1a | 1843 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| NYX | 0:85b3fd62ea1a | 1844 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| NYX | 0:85b3fd62ea1a | 1845 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| NYX | 0:85b3fd62ea1a | 1846 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| NYX | 0:85b3fd62ea1a | 1847 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) |
| NYX | 0:85b3fd62ea1a | 1848 | * |
| NYX | 0:85b3fd62ea1a | 1849 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1850 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1851 | */ |
| NYX | 0:85b3fd62ea1a | 1852 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1853 | { |
| NYX | 0:85b3fd62ea1a | 1854 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1855 | } |
| NYX | 0:85b3fd62ea1a | 1856 | |
| NYX | 0:85b3fd62ea1a | 1857 | /** |
| NYX | 0:85b3fd62ea1a | 1858 | * @brief Force APB2 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 1859 | * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1860 | * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1861 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1862 | * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1863 | * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1864 | * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1865 | * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1866 | * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1867 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1868 | * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1869 | * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1870 | * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1871 | * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1872 | * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1873 | * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1874 | * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1875 | * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1876 | * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1877 | * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1878 | * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1879 | * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n |
| NYX | 0:85b3fd62ea1a | 1880 | * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset |
| NYX | 0:85b3fd62ea1a | 1881 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1882 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| NYX | 0:85b3fd62ea1a | 1883 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| NYX | 0:85b3fd62ea1a | 1884 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| NYX | 0:85b3fd62ea1a | 1885 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| NYX | 0:85b3fd62ea1a | 1886 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) |
| NYX | 0:85b3fd62ea1a | 1887 | * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) |
| NYX | 0:85b3fd62ea1a | 1888 | * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) |
| NYX | 0:85b3fd62ea1a | 1889 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC |
| NYX | 0:85b3fd62ea1a | 1890 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| NYX | 0:85b3fd62ea1a | 1891 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| NYX | 0:85b3fd62ea1a | 1892 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| NYX | 0:85b3fd62ea1a | 1893 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| NYX | 0:85b3fd62ea1a | 1894 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| NYX | 0:85b3fd62ea1a | 1895 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
| NYX | 0:85b3fd62ea1a | 1896 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| NYX | 0:85b3fd62ea1a | 1897 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) |
| NYX | 0:85b3fd62ea1a | 1898 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| NYX | 0:85b3fd62ea1a | 1899 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) |
| NYX | 0:85b3fd62ea1a | 1900 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| NYX | 0:85b3fd62ea1a | 1901 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| NYX | 0:85b3fd62ea1a | 1902 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| NYX | 0:85b3fd62ea1a | 1903 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| NYX | 0:85b3fd62ea1a | 1904 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) |
| NYX | 0:85b3fd62ea1a | 1905 | * |
| NYX | 0:85b3fd62ea1a | 1906 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1907 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1908 | */ |
| NYX | 0:85b3fd62ea1a | 1909 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1910 | { |
| NYX | 0:85b3fd62ea1a | 1911 | SET_BIT(RCC->APB2RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1912 | } |
| NYX | 0:85b3fd62ea1a | 1913 | |
| NYX | 0:85b3fd62ea1a | 1914 | /** |
| NYX | 0:85b3fd62ea1a | 1915 | * @brief Release APB2 peripherals reset. |
| NYX | 0:85b3fd62ea1a | 1916 | * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1917 | * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1918 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1919 | * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1920 | * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1921 | * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1922 | * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1923 | * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1924 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1925 | * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1926 | * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1927 | * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1928 | * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1929 | * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1930 | * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1931 | * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1932 | * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1933 | * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1934 | * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1935 | * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1936 | * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n |
| NYX | 0:85b3fd62ea1a | 1937 | * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset |
| NYX | 0:85b3fd62ea1a | 1938 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 1939 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| NYX | 0:85b3fd62ea1a | 1940 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| NYX | 0:85b3fd62ea1a | 1941 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| NYX | 0:85b3fd62ea1a | 1942 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| NYX | 0:85b3fd62ea1a | 1943 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) |
| NYX | 0:85b3fd62ea1a | 1944 | * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) |
| NYX | 0:85b3fd62ea1a | 1945 | * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) |
| NYX | 0:85b3fd62ea1a | 1946 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC |
| NYX | 0:85b3fd62ea1a | 1947 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| NYX | 0:85b3fd62ea1a | 1948 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| NYX | 0:85b3fd62ea1a | 1949 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| NYX | 0:85b3fd62ea1a | 1950 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| NYX | 0:85b3fd62ea1a | 1951 | * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) |
| NYX | 0:85b3fd62ea1a | 1952 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| NYX | 0:85b3fd62ea1a | 1953 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
| NYX | 0:85b3fd62ea1a | 1954 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| NYX | 0:85b3fd62ea1a | 1955 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) |
| NYX | 0:85b3fd62ea1a | 1956 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| NYX | 0:85b3fd62ea1a | 1957 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) |
| NYX | 0:85b3fd62ea1a | 1958 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| NYX | 0:85b3fd62ea1a | 1959 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| NYX | 0:85b3fd62ea1a | 1960 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| NYX | 0:85b3fd62ea1a | 1961 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| NYX | 0:85b3fd62ea1a | 1962 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) |
| NYX | 0:85b3fd62ea1a | 1963 | * |
| NYX | 0:85b3fd62ea1a | 1964 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 1965 | * @retval None |
| NYX | 0:85b3fd62ea1a | 1966 | */ |
| NYX | 0:85b3fd62ea1a | 1967 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 1968 | { |
| NYX | 0:85b3fd62ea1a | 1969 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| NYX | 0:85b3fd62ea1a | 1970 | } |
| NYX | 0:85b3fd62ea1a | 1971 | |
| NYX | 0:85b3fd62ea1a | 1972 | /** |
| NYX | 0:85b3fd62ea1a | 1973 | * @brief Enable APB2 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 1974 | * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1975 | * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1976 | * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1977 | * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1978 | * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1979 | * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1980 | * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1981 | * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1982 | * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1983 | * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1984 | * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1985 | * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1986 | * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1987 | * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1988 | * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1989 | * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1990 | * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1991 | * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1992 | * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1993 | * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1994 | * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1995 | * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1996 | * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1997 | * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1998 | * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 1999 | * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower |
| NYX | 0:85b3fd62ea1a | 2000 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 2001 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| NYX | 0:85b3fd62ea1a | 2002 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| NYX | 0:85b3fd62ea1a | 2003 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| NYX | 0:85b3fd62ea1a | 2004 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) |
| NYX | 0:85b3fd62ea1a | 2005 | * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) |
| NYX | 0:85b3fd62ea1a | 2006 | * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) |
| NYX | 0:85b3fd62ea1a | 2007 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| NYX | 0:85b3fd62ea1a | 2008 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
| NYX | 0:85b3fd62ea1a | 2009 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
| NYX | 0:85b3fd62ea1a | 2010 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| NYX | 0:85b3fd62ea1a | 2011 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| NYX | 0:85b3fd62ea1a | 2012 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| NYX | 0:85b3fd62ea1a | 2013 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| NYX | 0:85b3fd62ea1a | 2014 | * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) |
| NYX | 0:85b3fd62ea1a | 2015 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| NYX | 0:85b3fd62ea1a | 2016 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
| NYX | 0:85b3fd62ea1a | 2017 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| NYX | 0:85b3fd62ea1a | 2018 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) |
| NYX | 0:85b3fd62ea1a | 2019 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| NYX | 0:85b3fd62ea1a | 2020 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) |
| NYX | 0:85b3fd62ea1a | 2021 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| NYX | 0:85b3fd62ea1a | 2022 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| NYX | 0:85b3fd62ea1a | 2023 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| NYX | 0:85b3fd62ea1a | 2024 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| NYX | 0:85b3fd62ea1a | 2025 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) |
| NYX | 0:85b3fd62ea1a | 2026 | * |
| NYX | 0:85b3fd62ea1a | 2027 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 2028 | * @retval None |
| NYX | 0:85b3fd62ea1a | 2029 | */ |
| NYX | 0:85b3fd62ea1a | 2030 | __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 2031 | { |
| NYX | 0:85b3fd62ea1a | 2032 | __IO uint32_t tmpreg; |
| NYX | 0:85b3fd62ea1a | 2033 | SET_BIT(RCC->APB2LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 2034 | /* Delay after an RCC peripheral clock enabling */ |
| NYX | 0:85b3fd62ea1a | 2035 | tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 2036 | (void)tmpreg; |
| NYX | 0:85b3fd62ea1a | 2037 | } |
| NYX | 0:85b3fd62ea1a | 2038 | |
| NYX | 0:85b3fd62ea1a | 2039 | /** |
| NYX | 0:85b3fd62ea1a | 2040 | * @brief Disable APB2 peripheral clocks in low-power mode |
| NYX | 0:85b3fd62ea1a | 2041 | * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2042 | * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2043 | * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2044 | * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2045 | * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2046 | * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2047 | * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2048 | * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2049 | * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2050 | * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2051 | * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2052 | * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2053 | * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2054 | * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2055 | * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2056 | * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2057 | * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2058 | * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2059 | * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2060 | * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2061 | * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2062 | * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2063 | * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2064 | * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2065 | * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n |
| NYX | 0:85b3fd62ea1a | 2066 | * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower |
| NYX | 0:85b3fd62ea1a | 2067 | * @param Periphs This parameter can be a combination of the following values: |
| NYX | 0:85b3fd62ea1a | 2068 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| NYX | 0:85b3fd62ea1a | 2069 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| NYX | 0:85b3fd62ea1a | 2070 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| NYX | 0:85b3fd62ea1a | 2071 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) |
| NYX | 0:85b3fd62ea1a | 2072 | * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) |
| NYX | 0:85b3fd62ea1a | 2073 | * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) |
| NYX | 0:85b3fd62ea1a | 2074 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| NYX | 0:85b3fd62ea1a | 2075 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) |
| NYX | 0:85b3fd62ea1a | 2076 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) |
| NYX | 0:85b3fd62ea1a | 2077 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| NYX | 0:85b3fd62ea1a | 2078 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| NYX | 0:85b3fd62ea1a | 2079 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) |
| NYX | 0:85b3fd62ea1a | 2080 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| NYX | 0:85b3fd62ea1a | 2081 | * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) |
| NYX | 0:85b3fd62ea1a | 2082 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| NYX | 0:85b3fd62ea1a | 2083 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) |
| NYX | 0:85b3fd62ea1a | 2084 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| NYX | 0:85b3fd62ea1a | 2085 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) |
| NYX | 0:85b3fd62ea1a | 2086 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| NYX | 0:85b3fd62ea1a | 2087 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) |
| NYX | 0:85b3fd62ea1a | 2088 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| NYX | 0:85b3fd62ea1a | 2089 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| NYX | 0:85b3fd62ea1a | 2090 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| NYX | 0:85b3fd62ea1a | 2091 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| NYX | 0:85b3fd62ea1a | 2092 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) |
| NYX | 0:85b3fd62ea1a | 2093 | * |
| NYX | 0:85b3fd62ea1a | 2094 | * (*) value not defined in all devices. |
| NYX | 0:85b3fd62ea1a | 2095 | * @retval None |
| NYX | 0:85b3fd62ea1a | 2096 | */ |
| NYX | 0:85b3fd62ea1a | 2097 | __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) |
| NYX | 0:85b3fd62ea1a | 2098 | { |
| NYX | 0:85b3fd62ea1a | 2099 | CLEAR_BIT(RCC->APB2LPENR, Periphs); |
| NYX | 0:85b3fd62ea1a | 2100 | } |
| NYX | 0:85b3fd62ea1a | 2101 | |
| NYX | 0:85b3fd62ea1a | 2102 | /** |
| NYX | 0:85b3fd62ea1a | 2103 | * @} |
| NYX | 0:85b3fd62ea1a | 2104 | */ |
| NYX | 0:85b3fd62ea1a | 2105 | |
| NYX | 0:85b3fd62ea1a | 2106 | /** |
| NYX | 0:85b3fd62ea1a | 2107 | * @} |
| NYX | 0:85b3fd62ea1a | 2108 | */ |
| NYX | 0:85b3fd62ea1a | 2109 | |
| NYX | 0:85b3fd62ea1a | 2110 | /** |
| NYX | 0:85b3fd62ea1a | 2111 | * @} |
| NYX | 0:85b3fd62ea1a | 2112 | */ |
| NYX | 0:85b3fd62ea1a | 2113 | |
| NYX | 0:85b3fd62ea1a | 2114 | #endif /* defined(RCC) */ |
| NYX | 0:85b3fd62ea1a | 2115 | |
| NYX | 0:85b3fd62ea1a | 2116 | /** |
| NYX | 0:85b3fd62ea1a | 2117 | * @} |
| NYX | 0:85b3fd62ea1a | 2118 | */ |
| NYX | 0:85b3fd62ea1a | 2119 | |
| NYX | 0:85b3fd62ea1a | 2120 | #ifdef __cplusplus |
| NYX | 0:85b3fd62ea1a | 2121 | } |
| NYX | 0:85b3fd62ea1a | 2122 | #endif |
| NYX | 0:85b3fd62ea1a | 2123 | |
| NYX | 0:85b3fd62ea1a | 2124 | #endif /* __STM32F4xx_LL_BUS_H */ |
| NYX | 0:85b3fd62ea1a | 2125 | |
| NYX | 0:85b3fd62ea1a | 2126 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |