Takaaki Numai / mbed-dev

inport from local

Dependents:   Hobbyking_Cheetah_0511

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_ll_adc.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief ADC LL module driver
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37 #if defined(USE_FULL_LL_DRIVER)
NYX 0:85b3fd62ea1a 38
NYX 0:85b3fd62ea1a 39 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 40 #include "stm32f4xx_ll_adc.h"
NYX 0:85b3fd62ea1a 41 #include "stm32f4xx_ll_bus.h"
NYX 0:85b3fd62ea1a 42
NYX 0:85b3fd62ea1a 43 #ifdef USE_FULL_ASSERT
NYX 0:85b3fd62ea1a 44 #include "stm32_assert.h"
NYX 0:85b3fd62ea1a 45 #else
NYX 0:85b3fd62ea1a 46 #define assert_param(expr) ((void)0U)
NYX 0:85b3fd62ea1a 47 #endif
NYX 0:85b3fd62ea1a 48
NYX 0:85b3fd62ea1a 49 /** @addtogroup STM32F4xx_LL_Driver
NYX 0:85b3fd62ea1a 50 * @{
NYX 0:85b3fd62ea1a 51 */
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 /** @addtogroup ADC_LL ADC
NYX 0:85b3fd62ea1a 56 * @{
NYX 0:85b3fd62ea1a 57 */
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 60 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 61 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 62 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 63
NYX 0:85b3fd62ea1a 64 /** @addtogroup ADC_LL_Private_Macros
NYX 0:85b3fd62ea1a 65 * @{
NYX 0:85b3fd62ea1a 66 */
NYX 0:85b3fd62ea1a 67
NYX 0:85b3fd62ea1a 68 /* Check of parameters for configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 69 /* common to several ADC instances. */
NYX 0:85b3fd62ea1a 70 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
NYX 0:85b3fd62ea1a 71 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
NYX 0:85b3fd62ea1a 72 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
NYX 0:85b3fd62ea1a 73 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
NYX 0:85b3fd62ea1a 74 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
NYX 0:85b3fd62ea1a 75 )
NYX 0:85b3fd62ea1a 76
NYX 0:85b3fd62ea1a 77 /* Check of parameters for configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 78 /* ADC instance. */
NYX 0:85b3fd62ea1a 79 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
NYX 0:85b3fd62ea1a 80 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
NYX 0:85b3fd62ea1a 81 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
NYX 0:85b3fd62ea1a 82 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
NYX 0:85b3fd62ea1a 83 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
NYX 0:85b3fd62ea1a 84 )
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
NYX 0:85b3fd62ea1a 87 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
NYX 0:85b3fd62ea1a 88 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
NYX 0:85b3fd62ea1a 89 )
NYX 0:85b3fd62ea1a 90
NYX 0:85b3fd62ea1a 91 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
NYX 0:85b3fd62ea1a 92 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
NYX 0:85b3fd62ea1a 93 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
NYX 0:85b3fd62ea1a 94 )
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
NYX 0:85b3fd62ea1a 97 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
NYX 0:85b3fd62ea1a 98 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
NYX 0:85b3fd62ea1a 99 )
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 /* Check of parameters for configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 102 /* ADC group regular */
NYX 0:85b3fd62ea1a 103 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
NYX 0:85b3fd62ea1a 104 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
NYX 0:85b3fd62ea1a 105 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
NYX 0:85b3fd62ea1a 106 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
NYX 0:85b3fd62ea1a 107 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
NYX 0:85b3fd62ea1a 108 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
NYX 0:85b3fd62ea1a 109 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
NYX 0:85b3fd62ea1a 110 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
NYX 0:85b3fd62ea1a 111 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
NYX 0:85b3fd62ea1a 112 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
NYX 0:85b3fd62ea1a 113 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
NYX 0:85b3fd62ea1a 114 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
NYX 0:85b3fd62ea1a 115 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
NYX 0:85b3fd62ea1a 116 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
NYX 0:85b3fd62ea1a 117 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
NYX 0:85b3fd62ea1a 118 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
NYX 0:85b3fd62ea1a 119 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
NYX 0:85b3fd62ea1a 120 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
NYX 0:85b3fd62ea1a 121 )
NYX 0:85b3fd62ea1a 122 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
NYX 0:85b3fd62ea1a 123 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
NYX 0:85b3fd62ea1a 124 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
NYX 0:85b3fd62ea1a 125 )
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
NYX 0:85b3fd62ea1a 128 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
NYX 0:85b3fd62ea1a 129 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
NYX 0:85b3fd62ea1a 130 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
NYX 0:85b3fd62ea1a 131 )
NYX 0:85b3fd62ea1a 132
NYX 0:85b3fd62ea1a 133 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
NYX 0:85b3fd62ea1a 134 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
NYX 0:85b3fd62ea1a 135 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
NYX 0:85b3fd62ea1a 136 )
NYX 0:85b3fd62ea1a 137
NYX 0:85b3fd62ea1a 138 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
NYX 0:85b3fd62ea1a 139 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
NYX 0:85b3fd62ea1a 140 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
NYX 0:85b3fd62ea1a 141 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
NYX 0:85b3fd62ea1a 142 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
NYX 0:85b3fd62ea1a 143 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
NYX 0:85b3fd62ea1a 144 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
NYX 0:85b3fd62ea1a 145 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
NYX 0:85b3fd62ea1a 146 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
NYX 0:85b3fd62ea1a 147 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
NYX 0:85b3fd62ea1a 148 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
NYX 0:85b3fd62ea1a 149 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
NYX 0:85b3fd62ea1a 150 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
NYX 0:85b3fd62ea1a 151 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
NYX 0:85b3fd62ea1a 152 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
NYX 0:85b3fd62ea1a 153 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
NYX 0:85b3fd62ea1a 154 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
NYX 0:85b3fd62ea1a 155 )
NYX 0:85b3fd62ea1a 156
NYX 0:85b3fd62ea1a 157 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
NYX 0:85b3fd62ea1a 158 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
NYX 0:85b3fd62ea1a 159 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
NYX 0:85b3fd62ea1a 160 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
NYX 0:85b3fd62ea1a 161 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
NYX 0:85b3fd62ea1a 162 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
NYX 0:85b3fd62ea1a 163 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
NYX 0:85b3fd62ea1a 164 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
NYX 0:85b3fd62ea1a 165 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
NYX 0:85b3fd62ea1a 166 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
NYX 0:85b3fd62ea1a 167 )
NYX 0:85b3fd62ea1a 168
NYX 0:85b3fd62ea1a 169 /* Check of parameters for configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 170 /* ADC group injected */
NYX 0:85b3fd62ea1a 171 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
NYX 0:85b3fd62ea1a 172 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
NYX 0:85b3fd62ea1a 173 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
NYX 0:85b3fd62ea1a 174 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
NYX 0:85b3fd62ea1a 175 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
NYX 0:85b3fd62ea1a 176 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
NYX 0:85b3fd62ea1a 177 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
NYX 0:85b3fd62ea1a 178 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
NYX 0:85b3fd62ea1a 179 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
NYX 0:85b3fd62ea1a 180 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
NYX 0:85b3fd62ea1a 181 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
NYX 0:85b3fd62ea1a 182 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
NYX 0:85b3fd62ea1a 183 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
NYX 0:85b3fd62ea1a 184 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
NYX 0:85b3fd62ea1a 185 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
NYX 0:85b3fd62ea1a 186 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
NYX 0:85b3fd62ea1a 187 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
NYX 0:85b3fd62ea1a 188 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
NYX 0:85b3fd62ea1a 189 )
NYX 0:85b3fd62ea1a 190
NYX 0:85b3fd62ea1a 191 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
NYX 0:85b3fd62ea1a 192 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
NYX 0:85b3fd62ea1a 193 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
NYX 0:85b3fd62ea1a 194 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
NYX 0:85b3fd62ea1a 195 )
NYX 0:85b3fd62ea1a 196
NYX 0:85b3fd62ea1a 197 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
NYX 0:85b3fd62ea1a 198 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
NYX 0:85b3fd62ea1a 199 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
NYX 0:85b3fd62ea1a 200 )
NYX 0:85b3fd62ea1a 201
NYX 0:85b3fd62ea1a 202 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
NYX 0:85b3fd62ea1a 203 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
NYX 0:85b3fd62ea1a 204 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
NYX 0:85b3fd62ea1a 205 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
NYX 0:85b3fd62ea1a 206 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
NYX 0:85b3fd62ea1a 207 )
NYX 0:85b3fd62ea1a 208
NYX 0:85b3fd62ea1a 209 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
NYX 0:85b3fd62ea1a 210 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
NYX 0:85b3fd62ea1a 211 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
NYX 0:85b3fd62ea1a 212 )
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 #if defined(ADC_MULTIMODE_SUPPORT)
NYX 0:85b3fd62ea1a 215 /* Check of parameters for configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 216 /* multimode. */
NYX 0:85b3fd62ea1a 217 #if defined(ADC3)
NYX 0:85b3fd62ea1a 218 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
NYX 0:85b3fd62ea1a 219 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
NYX 0:85b3fd62ea1a 220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
NYX 0:85b3fd62ea1a 221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
NYX 0:85b3fd62ea1a 222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
NYX 0:85b3fd62ea1a 223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
NYX 0:85b3fd62ea1a 224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
NYX 0:85b3fd62ea1a 225 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
NYX 0:85b3fd62ea1a 226 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
NYX 0:85b3fd62ea1a 227 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
NYX 0:85b3fd62ea1a 228 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
NYX 0:85b3fd62ea1a 229 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
NYX 0:85b3fd62ea1a 230 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
NYX 0:85b3fd62ea1a 231 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
NYX 0:85b3fd62ea1a 232 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
NYX 0:85b3fd62ea1a 233 )
NYX 0:85b3fd62ea1a 234 #else
NYX 0:85b3fd62ea1a 235 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
NYX 0:85b3fd62ea1a 236 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
NYX 0:85b3fd62ea1a 237 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
NYX 0:85b3fd62ea1a 238 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
NYX 0:85b3fd62ea1a 239 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
NYX 0:85b3fd62ea1a 240 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
NYX 0:85b3fd62ea1a 241 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
NYX 0:85b3fd62ea1a 242 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
NYX 0:85b3fd62ea1a 243 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
NYX 0:85b3fd62ea1a 244 )
NYX 0:85b3fd62ea1a 245 #endif
NYX 0:85b3fd62ea1a 246
NYX 0:85b3fd62ea1a 247 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
NYX 0:85b3fd62ea1a 248 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
NYX 0:85b3fd62ea1a 249 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
NYX 0:85b3fd62ea1a 250 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
NYX 0:85b3fd62ea1a 251 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
NYX 0:85b3fd62ea1a 252 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
NYX 0:85b3fd62ea1a 253 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
NYX 0:85b3fd62ea1a 254 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
NYX 0:85b3fd62ea1a 255 )
NYX 0:85b3fd62ea1a 256
NYX 0:85b3fd62ea1a 257 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
NYX 0:85b3fd62ea1a 258 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
NYX 0:85b3fd62ea1a 259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
NYX 0:85b3fd62ea1a 260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
NYX 0:85b3fd62ea1a 261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
NYX 0:85b3fd62ea1a 262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
NYX 0:85b3fd62ea1a 263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
NYX 0:85b3fd62ea1a 264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
NYX 0:85b3fd62ea1a 265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
NYX 0:85b3fd62ea1a 266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
NYX 0:85b3fd62ea1a 267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
NYX 0:85b3fd62ea1a 268 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
NYX 0:85b3fd62ea1a 269 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
NYX 0:85b3fd62ea1a 270 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
NYX 0:85b3fd62ea1a 271 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
NYX 0:85b3fd62ea1a 272 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
NYX 0:85b3fd62ea1a 273 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
NYX 0:85b3fd62ea1a 274 )
NYX 0:85b3fd62ea1a 275
NYX 0:85b3fd62ea1a 276 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
NYX 0:85b3fd62ea1a 277 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
NYX 0:85b3fd62ea1a 278 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
NYX 0:85b3fd62ea1a 279 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
NYX 0:85b3fd62ea1a 280 )
NYX 0:85b3fd62ea1a 281
NYX 0:85b3fd62ea1a 282 #endif /* ADC_MULTIMODE_SUPPORT */
NYX 0:85b3fd62ea1a 283 /**
NYX 0:85b3fd62ea1a 284 * @}
NYX 0:85b3fd62ea1a 285 */
NYX 0:85b3fd62ea1a 286
NYX 0:85b3fd62ea1a 287
NYX 0:85b3fd62ea1a 288 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 289
NYX 0:85b3fd62ea1a 290 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 291 /** @addtogroup ADC_LL_Exported_Functions
NYX 0:85b3fd62ea1a 292 * @{
NYX 0:85b3fd62ea1a 293 */
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /** @addtogroup ADC_LL_EF_Init
NYX 0:85b3fd62ea1a 296 * @{
NYX 0:85b3fd62ea1a 297 */
NYX 0:85b3fd62ea1a 298
NYX 0:85b3fd62ea1a 299 /**
NYX 0:85b3fd62ea1a 300 * @brief De-initialize registers of all ADC instances belonging to
NYX 0:85b3fd62ea1a 301 * the same ADC common instance to their default reset values.
NYX 0:85b3fd62ea1a 302 * @param ADCxy_COMMON ADC common instance
NYX 0:85b3fd62ea1a 303 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
NYX 0:85b3fd62ea1a 304 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 305 * - SUCCESS: ADC common registers are de-initialized
NYX 0:85b3fd62ea1a 306 * - ERROR: not applicable
NYX 0:85b3fd62ea1a 307 */
NYX 0:85b3fd62ea1a 308 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
NYX 0:85b3fd62ea1a 309 {
NYX 0:85b3fd62ea1a 310 /* Check the parameters */
NYX 0:85b3fd62ea1a 311 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
NYX 0:85b3fd62ea1a 312
NYX 0:85b3fd62ea1a 313
NYX 0:85b3fd62ea1a 314 /* Force reset of ADC clock (core clock) */
NYX 0:85b3fd62ea1a 315 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
NYX 0:85b3fd62ea1a 316
NYX 0:85b3fd62ea1a 317 /* Release reset of ADC clock (core clock) */
NYX 0:85b3fd62ea1a 318 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
NYX 0:85b3fd62ea1a 319
NYX 0:85b3fd62ea1a 320 return SUCCESS;
NYX 0:85b3fd62ea1a 321 }
NYX 0:85b3fd62ea1a 322
NYX 0:85b3fd62ea1a 323 /**
NYX 0:85b3fd62ea1a 324 * @brief Initialize some features of ADC common parameters
NYX 0:85b3fd62ea1a 325 * (all ADC instances belonging to the same ADC common instance)
NYX 0:85b3fd62ea1a 326 * and multimode (for devices with several ADC instances available).
NYX 0:85b3fd62ea1a 327 * @note The setting of ADC common parameters is conditioned to
NYX 0:85b3fd62ea1a 328 * ADC instances state:
NYX 0:85b3fd62ea1a 329 * All ADC instances belonging to the same ADC common instance
NYX 0:85b3fd62ea1a 330 * must be disabled.
NYX 0:85b3fd62ea1a 331 * @param ADCxy_COMMON ADC common instance
NYX 0:85b3fd62ea1a 332 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
NYX 0:85b3fd62ea1a 333 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
NYX 0:85b3fd62ea1a 334 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 335 * - SUCCESS: ADC common registers are initialized
NYX 0:85b3fd62ea1a 336 * - ERROR: ADC common registers are not initialized
NYX 0:85b3fd62ea1a 337 */
NYX 0:85b3fd62ea1a 338 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
NYX 0:85b3fd62ea1a 339 {
NYX 0:85b3fd62ea1a 340 ErrorStatus status = SUCCESS;
NYX 0:85b3fd62ea1a 341
NYX 0:85b3fd62ea1a 342 /* Check the parameters */
NYX 0:85b3fd62ea1a 343 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
NYX 0:85b3fd62ea1a 344 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
NYX 0:85b3fd62ea1a 345
NYX 0:85b3fd62ea1a 346 #if defined(ADC_MULTIMODE_SUPPORT)
NYX 0:85b3fd62ea1a 347 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
NYX 0:85b3fd62ea1a 348 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
NYX 0:85b3fd62ea1a 349 {
NYX 0:85b3fd62ea1a 350 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
NYX 0:85b3fd62ea1a 351 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
NYX 0:85b3fd62ea1a 352 }
NYX 0:85b3fd62ea1a 353 #endif /* ADC_MULTIMODE_SUPPORT */
NYX 0:85b3fd62ea1a 354
NYX 0:85b3fd62ea1a 355 /* Note: Hardware constraint (refer to description of functions */
NYX 0:85b3fd62ea1a 356 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
NYX 0:85b3fd62ea1a 357 /* On this STM32 serie, setting of these features is conditioned to */
NYX 0:85b3fd62ea1a 358 /* ADC state: */
NYX 0:85b3fd62ea1a 359 /* All ADC instances of the ADC common group must be disabled. */
NYX 0:85b3fd62ea1a 360 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
NYX 0:85b3fd62ea1a 361 {
NYX 0:85b3fd62ea1a 362 /* Configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 363 /* - common to several ADC */
NYX 0:85b3fd62ea1a 364 /* (all ADC instances belonging to the same ADC common instance) */
NYX 0:85b3fd62ea1a 365 /* - Set ADC clock (conversion clock) */
NYX 0:85b3fd62ea1a 366 /* - multimode (if several ADC instances available on the */
NYX 0:85b3fd62ea1a 367 /* selected device) */
NYX 0:85b3fd62ea1a 368 /* - Set ADC multimode configuration */
NYX 0:85b3fd62ea1a 369 /* - Set ADC multimode DMA transfer */
NYX 0:85b3fd62ea1a 370 /* - Set ADC multimode: delay between 2 sampling phases */
NYX 0:85b3fd62ea1a 371 #if defined(ADC_MULTIMODE_SUPPORT)
NYX 0:85b3fd62ea1a 372 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
NYX 0:85b3fd62ea1a 373 {
NYX 0:85b3fd62ea1a 374 MODIFY_REG(ADCxy_COMMON->CCR,
NYX 0:85b3fd62ea1a 375 ADC_CCR_ADCPRE
NYX 0:85b3fd62ea1a 376 | ADC_CCR_MULTI
NYX 0:85b3fd62ea1a 377 | ADC_CCR_DMA
NYX 0:85b3fd62ea1a 378 | ADC_CCR_DDS
NYX 0:85b3fd62ea1a 379 | ADC_CCR_DELAY
NYX 0:85b3fd62ea1a 380 ,
NYX 0:85b3fd62ea1a 381 ADC_CommonInitStruct->CommonClock
NYX 0:85b3fd62ea1a 382 | ADC_CommonInitStruct->Multimode
NYX 0:85b3fd62ea1a 383 | ADC_CommonInitStruct->MultiDMATransfer
NYX 0:85b3fd62ea1a 384 | ADC_CommonInitStruct->MultiTwoSamplingDelay
NYX 0:85b3fd62ea1a 385 );
NYX 0:85b3fd62ea1a 386 }
NYX 0:85b3fd62ea1a 387 else
NYX 0:85b3fd62ea1a 388 {
NYX 0:85b3fd62ea1a 389 MODIFY_REG(ADCxy_COMMON->CCR,
NYX 0:85b3fd62ea1a 390 ADC_CCR_ADCPRE
NYX 0:85b3fd62ea1a 391 | ADC_CCR_MULTI
NYX 0:85b3fd62ea1a 392 | ADC_CCR_DMA
NYX 0:85b3fd62ea1a 393 | ADC_CCR_DDS
NYX 0:85b3fd62ea1a 394 | ADC_CCR_DELAY
NYX 0:85b3fd62ea1a 395 ,
NYX 0:85b3fd62ea1a 396 ADC_CommonInitStruct->CommonClock
NYX 0:85b3fd62ea1a 397 | LL_ADC_MULTI_INDEPENDENT
NYX 0:85b3fd62ea1a 398 );
NYX 0:85b3fd62ea1a 399 }
NYX 0:85b3fd62ea1a 400 #else
NYX 0:85b3fd62ea1a 401 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
NYX 0:85b3fd62ea1a 402 #endif
NYX 0:85b3fd62ea1a 403 }
NYX 0:85b3fd62ea1a 404 else
NYX 0:85b3fd62ea1a 405 {
NYX 0:85b3fd62ea1a 406 /* Initialization error: One or several ADC instances belonging to */
NYX 0:85b3fd62ea1a 407 /* the same ADC common instance are not disabled. */
NYX 0:85b3fd62ea1a 408 status = ERROR;
NYX 0:85b3fd62ea1a 409 }
NYX 0:85b3fd62ea1a 410
NYX 0:85b3fd62ea1a 411 return status;
NYX 0:85b3fd62ea1a 412 }
NYX 0:85b3fd62ea1a 413
NYX 0:85b3fd62ea1a 414 /**
NYX 0:85b3fd62ea1a 415 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
NYX 0:85b3fd62ea1a 416 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
NYX 0:85b3fd62ea1a 417 * whose fields will be set to default values.
NYX 0:85b3fd62ea1a 418 * @retval None
NYX 0:85b3fd62ea1a 419 */
NYX 0:85b3fd62ea1a 420 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
NYX 0:85b3fd62ea1a 421 {
NYX 0:85b3fd62ea1a 422 /* Set ADC_CommonInitStruct fields to default values */
NYX 0:85b3fd62ea1a 423 /* Set fields of ADC common */
NYX 0:85b3fd62ea1a 424 /* (all ADC instances belonging to the same ADC common instance) */
NYX 0:85b3fd62ea1a 425 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
NYX 0:85b3fd62ea1a 426
NYX 0:85b3fd62ea1a 427 #if defined(ADC_MULTIMODE_SUPPORT)
NYX 0:85b3fd62ea1a 428 /* Set fields of ADC multimode */
NYX 0:85b3fd62ea1a 429 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
NYX 0:85b3fd62ea1a 430 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
NYX 0:85b3fd62ea1a 431 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
NYX 0:85b3fd62ea1a 432 #endif /* ADC_MULTIMODE_SUPPORT */
NYX 0:85b3fd62ea1a 433 }
NYX 0:85b3fd62ea1a 434
NYX 0:85b3fd62ea1a 435 /**
NYX 0:85b3fd62ea1a 436 * @brief De-initialize registers of the selected ADC instance
NYX 0:85b3fd62ea1a 437 * to their default reset values.
NYX 0:85b3fd62ea1a 438 * @note To reset all ADC instances quickly (perform a hard reset),
NYX 0:85b3fd62ea1a 439 * use function @ref LL_ADC_CommonDeInit().
NYX 0:85b3fd62ea1a 440 * @param ADCx ADC instance
NYX 0:85b3fd62ea1a 441 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 442 * - SUCCESS: ADC registers are de-initialized
NYX 0:85b3fd62ea1a 443 * - ERROR: ADC registers are not de-initialized
NYX 0:85b3fd62ea1a 444 */
NYX 0:85b3fd62ea1a 445 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
NYX 0:85b3fd62ea1a 446 {
NYX 0:85b3fd62ea1a 447 ErrorStatus status = SUCCESS;
NYX 0:85b3fd62ea1a 448
NYX 0:85b3fd62ea1a 449 /* Check the parameters */
NYX 0:85b3fd62ea1a 450 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
NYX 0:85b3fd62ea1a 451
NYX 0:85b3fd62ea1a 452 /* Disable ADC instance if not already disabled. */
NYX 0:85b3fd62ea1a 453 if(LL_ADC_IsEnabled(ADCx) == 1U)
NYX 0:85b3fd62ea1a 454 {
NYX 0:85b3fd62ea1a 455 /* Set ADC group regular trigger source to SW start to ensure to not */
NYX 0:85b3fd62ea1a 456 /* have an external trigger event occurring during the conversion stop */
NYX 0:85b3fd62ea1a 457 /* ADC disable process. */
NYX 0:85b3fd62ea1a 458 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
NYX 0:85b3fd62ea1a 459
NYX 0:85b3fd62ea1a 460 /* Set ADC group injected trigger source to SW start to ensure to not */
NYX 0:85b3fd62ea1a 461 /* have an external trigger event occurring during the conversion stop */
NYX 0:85b3fd62ea1a 462 /* ADC disable process. */
NYX 0:85b3fd62ea1a 463 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
NYX 0:85b3fd62ea1a 464
NYX 0:85b3fd62ea1a 465 /* Disable the ADC instance */
NYX 0:85b3fd62ea1a 466 LL_ADC_Disable(ADCx);
NYX 0:85b3fd62ea1a 467 }
NYX 0:85b3fd62ea1a 468
NYX 0:85b3fd62ea1a 469 /* Check whether ADC state is compliant with expected state */
NYX 0:85b3fd62ea1a 470 /* (hardware requirements of bits state to reset registers below) */
NYX 0:85b3fd62ea1a 471 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
NYX 0:85b3fd62ea1a 472 {
NYX 0:85b3fd62ea1a 473 /* ========== Reset ADC registers ========== */
NYX 0:85b3fd62ea1a 474 /* Reset register SR */
NYX 0:85b3fd62ea1a 475 CLEAR_BIT(ADCx->SR,
NYX 0:85b3fd62ea1a 476 ( LL_ADC_FLAG_STRT
NYX 0:85b3fd62ea1a 477 | LL_ADC_FLAG_JSTRT
NYX 0:85b3fd62ea1a 478 | LL_ADC_FLAG_EOCS
NYX 0:85b3fd62ea1a 479 | LL_ADC_FLAG_OVR
NYX 0:85b3fd62ea1a 480 | LL_ADC_FLAG_JEOS
NYX 0:85b3fd62ea1a 481 | LL_ADC_FLAG_AWD1 )
NYX 0:85b3fd62ea1a 482 );
NYX 0:85b3fd62ea1a 483
NYX 0:85b3fd62ea1a 484 /* Reset register CR1 */
NYX 0:85b3fd62ea1a 485 CLEAR_BIT(ADCx->CR1,
NYX 0:85b3fd62ea1a 486 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
NYX 0:85b3fd62ea1a 487 | ADC_CR1_JAWDEN
NYX 0:85b3fd62ea1a 488 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
NYX 0:85b3fd62ea1a 489 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
NYX 0:85b3fd62ea1a 490 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
NYX 0:85b3fd62ea1a 491 | ADC_CR1_AWDCH )
NYX 0:85b3fd62ea1a 492 );
NYX 0:85b3fd62ea1a 493
NYX 0:85b3fd62ea1a 494 /* Reset register CR2 */
NYX 0:85b3fd62ea1a 495 CLEAR_BIT(ADCx->CR2,
NYX 0:85b3fd62ea1a 496 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
NYX 0:85b3fd62ea1a 497 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
NYX 0:85b3fd62ea1a 498 | ADC_CR2_ALIGN | ADC_CR2_EOCS
NYX 0:85b3fd62ea1a 499 | ADC_CR2_DDS | ADC_CR2_DMA
NYX 0:85b3fd62ea1a 500 | ADC_CR2_CONT | ADC_CR2_ADON )
NYX 0:85b3fd62ea1a 501 );
NYX 0:85b3fd62ea1a 502
NYX 0:85b3fd62ea1a 503 /* Reset register SMPR1 */
NYX 0:85b3fd62ea1a 504 CLEAR_BIT(ADCx->SMPR1,
NYX 0:85b3fd62ea1a 505 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
NYX 0:85b3fd62ea1a 506 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
NYX 0:85b3fd62ea1a 507 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
NYX 0:85b3fd62ea1a 508 );
NYX 0:85b3fd62ea1a 509
NYX 0:85b3fd62ea1a 510 /* Reset register SMPR2 */
NYX 0:85b3fd62ea1a 511 CLEAR_BIT(ADCx->SMPR2,
NYX 0:85b3fd62ea1a 512 ( ADC_SMPR2_SMP9
NYX 0:85b3fd62ea1a 513 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
NYX 0:85b3fd62ea1a 514 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
NYX 0:85b3fd62ea1a 515 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
NYX 0:85b3fd62ea1a 516 );
NYX 0:85b3fd62ea1a 517
NYX 0:85b3fd62ea1a 518 /* Reset register JOFR1 */
NYX 0:85b3fd62ea1a 519 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
NYX 0:85b3fd62ea1a 520 /* Reset register JOFR2 */
NYX 0:85b3fd62ea1a 521 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
NYX 0:85b3fd62ea1a 522 /* Reset register JOFR3 */
NYX 0:85b3fd62ea1a 523 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
NYX 0:85b3fd62ea1a 524 /* Reset register JOFR4 */
NYX 0:85b3fd62ea1a 525 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
NYX 0:85b3fd62ea1a 526
NYX 0:85b3fd62ea1a 527 /* Reset register HTR */
NYX 0:85b3fd62ea1a 528 SET_BIT(ADCx->HTR, ADC_HTR_HT);
NYX 0:85b3fd62ea1a 529 /* Reset register LTR */
NYX 0:85b3fd62ea1a 530 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
NYX 0:85b3fd62ea1a 531
NYX 0:85b3fd62ea1a 532 /* Reset register SQR1 */
NYX 0:85b3fd62ea1a 533 CLEAR_BIT(ADCx->SQR1,
NYX 0:85b3fd62ea1a 534 ( ADC_SQR1_L
NYX 0:85b3fd62ea1a 535 | ADC_SQR1_SQ16
NYX 0:85b3fd62ea1a 536 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
NYX 0:85b3fd62ea1a 537 );
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 /* Reset register SQR2 */
NYX 0:85b3fd62ea1a 540 CLEAR_BIT(ADCx->SQR2,
NYX 0:85b3fd62ea1a 541 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
NYX 0:85b3fd62ea1a 542 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
NYX 0:85b3fd62ea1a 543 );
NYX 0:85b3fd62ea1a 544
NYX 0:85b3fd62ea1a 545
NYX 0:85b3fd62ea1a 546 /* Reset register JSQR */
NYX 0:85b3fd62ea1a 547 CLEAR_BIT(ADCx->JSQR,
NYX 0:85b3fd62ea1a 548 ( ADC_JSQR_JL
NYX 0:85b3fd62ea1a 549 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
NYX 0:85b3fd62ea1a 550 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
NYX 0:85b3fd62ea1a 551 );
NYX 0:85b3fd62ea1a 552
NYX 0:85b3fd62ea1a 553 /* Reset register DR */
NYX 0:85b3fd62ea1a 554 /* bits in access mode read only, no direct reset applicable */
NYX 0:85b3fd62ea1a 555
NYX 0:85b3fd62ea1a 556 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
NYX 0:85b3fd62ea1a 557 /* bits in access mode read only, no direct reset applicable */
NYX 0:85b3fd62ea1a 558
NYX 0:85b3fd62ea1a 559 /* Reset register CCR */
NYX 0:85b3fd62ea1a 560 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
NYX 0:85b3fd62ea1a 561 }
NYX 0:85b3fd62ea1a 562
NYX 0:85b3fd62ea1a 563 return status;
NYX 0:85b3fd62ea1a 564 }
NYX 0:85b3fd62ea1a 565
NYX 0:85b3fd62ea1a 566 /**
NYX 0:85b3fd62ea1a 567 * @brief Initialize some features of ADC instance.
NYX 0:85b3fd62ea1a 568 * @note These parameters have an impact on ADC scope: ADC instance.
NYX 0:85b3fd62ea1a 569 * Affects both group regular and group injected (availability
NYX 0:85b3fd62ea1a 570 * of ADC group injected depends on STM32 families).
NYX 0:85b3fd62ea1a 571 * Refer to corresponding unitary functions into
NYX 0:85b3fd62ea1a 572 * @ref ADC_LL_EF_Configuration_ADC_Instance .
NYX 0:85b3fd62ea1a 573 * @note The setting of these parameters by function @ref LL_ADC_Init()
NYX 0:85b3fd62ea1a 574 * is conditioned to ADC state:
NYX 0:85b3fd62ea1a 575 * ADC instance must be disabled.
NYX 0:85b3fd62ea1a 576 * This condition is applied to all ADC features, for efficiency
NYX 0:85b3fd62ea1a 577 * and compatibility over all STM32 families. However, the different
NYX 0:85b3fd62ea1a 578 * features can be set under different ADC state conditions
NYX 0:85b3fd62ea1a 579 * (setting possible with ADC enabled without conversion on going,
NYX 0:85b3fd62ea1a 580 * ADC enabled with conversion on going, ...)
NYX 0:85b3fd62ea1a 581 * Each feature can be updated afterwards with a unitary function
NYX 0:85b3fd62ea1a 582 * and potentially with ADC in a different state than disabled,
NYX 0:85b3fd62ea1a 583 * refer to description of each function for setting
NYX 0:85b3fd62ea1a 584 * conditioned to ADC state.
NYX 0:85b3fd62ea1a 585 * @note After using this function, some other features must be configured
NYX 0:85b3fd62ea1a 586 * using LL unitary functions.
NYX 0:85b3fd62ea1a 587 * The minimum configuration remaining to be done is:
NYX 0:85b3fd62ea1a 588 * - Set ADC group regular or group injected sequencer:
NYX 0:85b3fd62ea1a 589 * map channel on the selected sequencer rank.
NYX 0:85b3fd62ea1a 590 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
NYX 0:85b3fd62ea1a 591 * - Set ADC channel sampling time
NYX 0:85b3fd62ea1a 592 * Refer to function LL_ADC_SetChannelSamplingTime();
NYX 0:85b3fd62ea1a 593 * @param ADCx ADC instance
NYX 0:85b3fd62ea1a 594 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
NYX 0:85b3fd62ea1a 595 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 596 * - SUCCESS: ADC registers are initialized
NYX 0:85b3fd62ea1a 597 * - ERROR: ADC registers are not initialized
NYX 0:85b3fd62ea1a 598 */
NYX 0:85b3fd62ea1a 599 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
NYX 0:85b3fd62ea1a 600 {
NYX 0:85b3fd62ea1a 601 ErrorStatus status = SUCCESS;
NYX 0:85b3fd62ea1a 602
NYX 0:85b3fd62ea1a 603 /* Check the parameters */
NYX 0:85b3fd62ea1a 604 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
NYX 0:85b3fd62ea1a 605
NYX 0:85b3fd62ea1a 606 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
NYX 0:85b3fd62ea1a 607 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
NYX 0:85b3fd62ea1a 608 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
NYX 0:85b3fd62ea1a 609
NYX 0:85b3fd62ea1a 610 /* Note: Hardware constraint (refer to description of this function): */
NYX 0:85b3fd62ea1a 611 /* ADC instance must be disabled. */
NYX 0:85b3fd62ea1a 612 if(LL_ADC_IsEnabled(ADCx) == 0U)
NYX 0:85b3fd62ea1a 613 {
NYX 0:85b3fd62ea1a 614 /* Configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 615 /* - ADC instance */
NYX 0:85b3fd62ea1a 616 /* - Set ADC data resolution */
NYX 0:85b3fd62ea1a 617 /* - Set ADC conversion data alignment */
NYX 0:85b3fd62ea1a 618 MODIFY_REG(ADCx->CR1,
NYX 0:85b3fd62ea1a 619 ADC_CR1_RES
NYX 0:85b3fd62ea1a 620 | ADC_CR1_SCAN
NYX 0:85b3fd62ea1a 621 ,
NYX 0:85b3fd62ea1a 622 ADC_InitStruct->Resolution
NYX 0:85b3fd62ea1a 623 | ADC_InitStruct->SequencersScanMode
NYX 0:85b3fd62ea1a 624 );
NYX 0:85b3fd62ea1a 625
NYX 0:85b3fd62ea1a 626 MODIFY_REG(ADCx->CR2,
NYX 0:85b3fd62ea1a 627 ADC_CR2_ALIGN
NYX 0:85b3fd62ea1a 628 ,
NYX 0:85b3fd62ea1a 629 ADC_InitStruct->DataAlignment
NYX 0:85b3fd62ea1a 630 );
NYX 0:85b3fd62ea1a 631
NYX 0:85b3fd62ea1a 632 }
NYX 0:85b3fd62ea1a 633 else
NYX 0:85b3fd62ea1a 634 {
NYX 0:85b3fd62ea1a 635 /* Initialization error: ADC instance is not disabled. */
NYX 0:85b3fd62ea1a 636 status = ERROR;
NYX 0:85b3fd62ea1a 637 }
NYX 0:85b3fd62ea1a 638 return status;
NYX 0:85b3fd62ea1a 639 }
NYX 0:85b3fd62ea1a 640
NYX 0:85b3fd62ea1a 641 /**
NYX 0:85b3fd62ea1a 642 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
NYX 0:85b3fd62ea1a 643 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
NYX 0:85b3fd62ea1a 644 * whose fields will be set to default values.
NYX 0:85b3fd62ea1a 645 * @retval None
NYX 0:85b3fd62ea1a 646 */
NYX 0:85b3fd62ea1a 647 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
NYX 0:85b3fd62ea1a 648 {
NYX 0:85b3fd62ea1a 649 /* Set ADC_InitStruct fields to default values */
NYX 0:85b3fd62ea1a 650 /* Set fields of ADC instance */
NYX 0:85b3fd62ea1a 651 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
NYX 0:85b3fd62ea1a 652 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
NYX 0:85b3fd62ea1a 653
NYX 0:85b3fd62ea1a 654 /* Enable scan mode to have a generic behavior with ADC of other */
NYX 0:85b3fd62ea1a 655 /* STM32 families, without this setting available: */
NYX 0:85b3fd62ea1a 656 /* ADC group regular sequencer and ADC group injected sequencer depend */
NYX 0:85b3fd62ea1a 657 /* only of their own configuration. */
NYX 0:85b3fd62ea1a 658 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
NYX 0:85b3fd62ea1a 659
NYX 0:85b3fd62ea1a 660 }
NYX 0:85b3fd62ea1a 661
NYX 0:85b3fd62ea1a 662 /**
NYX 0:85b3fd62ea1a 663 * @brief Initialize some features of ADC group regular.
NYX 0:85b3fd62ea1a 664 * @note These parameters have an impact on ADC scope: ADC group regular.
NYX 0:85b3fd62ea1a 665 * Refer to corresponding unitary functions into
NYX 0:85b3fd62ea1a 666 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
NYX 0:85b3fd62ea1a 667 * (functions with prefix "REG").
NYX 0:85b3fd62ea1a 668 * @note The setting of these parameters by function @ref LL_ADC_Init()
NYX 0:85b3fd62ea1a 669 * is conditioned to ADC state:
NYX 0:85b3fd62ea1a 670 * ADC instance must be disabled.
NYX 0:85b3fd62ea1a 671 * This condition is applied to all ADC features, for efficiency
NYX 0:85b3fd62ea1a 672 * and compatibility over all STM32 families. However, the different
NYX 0:85b3fd62ea1a 673 * features can be set under different ADC state conditions
NYX 0:85b3fd62ea1a 674 * (setting possible with ADC enabled without conversion on going,
NYX 0:85b3fd62ea1a 675 * ADC enabled with conversion on going, ...)
NYX 0:85b3fd62ea1a 676 * Each feature can be updated afterwards with a unitary function
NYX 0:85b3fd62ea1a 677 * and potentially with ADC in a different state than disabled,
NYX 0:85b3fd62ea1a 678 * refer to description of each function for setting
NYX 0:85b3fd62ea1a 679 * conditioned to ADC state.
NYX 0:85b3fd62ea1a 680 * @note After using this function, other features must be configured
NYX 0:85b3fd62ea1a 681 * using LL unitary functions.
NYX 0:85b3fd62ea1a 682 * The minimum configuration remaining to be done is:
NYX 0:85b3fd62ea1a 683 * - Set ADC group regular or group injected sequencer:
NYX 0:85b3fd62ea1a 684 * map channel on the selected sequencer rank.
NYX 0:85b3fd62ea1a 685 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
NYX 0:85b3fd62ea1a 686 * - Set ADC channel sampling time
NYX 0:85b3fd62ea1a 687 * Refer to function LL_ADC_SetChannelSamplingTime();
NYX 0:85b3fd62ea1a 688 * @param ADCx ADC instance
NYX 0:85b3fd62ea1a 689 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
NYX 0:85b3fd62ea1a 690 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 691 * - SUCCESS: ADC registers are initialized
NYX 0:85b3fd62ea1a 692 * - ERROR: ADC registers are not initialized
NYX 0:85b3fd62ea1a 693 */
NYX 0:85b3fd62ea1a 694 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
NYX 0:85b3fd62ea1a 695 {
NYX 0:85b3fd62ea1a 696 ErrorStatus status = SUCCESS;
NYX 0:85b3fd62ea1a 697
NYX 0:85b3fd62ea1a 698 /* Check the parameters */
NYX 0:85b3fd62ea1a 699 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
NYX 0:85b3fd62ea1a 700 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
NYX 0:85b3fd62ea1a 701 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
NYX 0:85b3fd62ea1a 702 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
NYX 0:85b3fd62ea1a 703 {
NYX 0:85b3fd62ea1a 704 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
NYX 0:85b3fd62ea1a 705 }
NYX 0:85b3fd62ea1a 706 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
NYX 0:85b3fd62ea1a 707 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
NYX 0:85b3fd62ea1a 708
NYX 0:85b3fd62ea1a 709 /* Note: Hardware constraint (refer to description of this function): */
NYX 0:85b3fd62ea1a 710 /* ADC instance must be disabled. */
NYX 0:85b3fd62ea1a 711 if(LL_ADC_IsEnabled(ADCx) == 0U)
NYX 0:85b3fd62ea1a 712 {
NYX 0:85b3fd62ea1a 713 /* Configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 714 /* - ADC group regular */
NYX 0:85b3fd62ea1a 715 /* - Set ADC group regular trigger source */
NYX 0:85b3fd62ea1a 716 /* - Set ADC group regular sequencer length */
NYX 0:85b3fd62ea1a 717 /* - Set ADC group regular sequencer discontinuous mode */
NYX 0:85b3fd62ea1a 718 /* - Set ADC group regular continuous mode */
NYX 0:85b3fd62ea1a 719 /* - Set ADC group regular conversion data transfer: no transfer or */
NYX 0:85b3fd62ea1a 720 /* transfer by DMA, and DMA requests mode */
NYX 0:85b3fd62ea1a 721 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
NYX 0:85b3fd62ea1a 722 /* ADC conversion. */
NYX 0:85b3fd62ea1a 723 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
NYX 0:85b3fd62ea1a 724 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
NYX 0:85b3fd62ea1a 725 {
NYX 0:85b3fd62ea1a 726 MODIFY_REG(ADCx->CR1,
NYX 0:85b3fd62ea1a 727 ADC_CR1_DISCEN
NYX 0:85b3fd62ea1a 728 | ADC_CR1_DISCNUM
NYX 0:85b3fd62ea1a 729 ,
NYX 0:85b3fd62ea1a 730 ADC_REG_InitStruct->SequencerLength
NYX 0:85b3fd62ea1a 731 | ADC_REG_InitStruct->SequencerDiscont
NYX 0:85b3fd62ea1a 732 );
NYX 0:85b3fd62ea1a 733 }
NYX 0:85b3fd62ea1a 734 else
NYX 0:85b3fd62ea1a 735 {
NYX 0:85b3fd62ea1a 736 MODIFY_REG(ADCx->CR1,
NYX 0:85b3fd62ea1a 737 ADC_CR1_DISCEN
NYX 0:85b3fd62ea1a 738 | ADC_CR1_DISCNUM
NYX 0:85b3fd62ea1a 739 ,
NYX 0:85b3fd62ea1a 740 ADC_REG_InitStruct->SequencerLength
NYX 0:85b3fd62ea1a 741 | LL_ADC_REG_SEQ_DISCONT_DISABLE
NYX 0:85b3fd62ea1a 742 );
NYX 0:85b3fd62ea1a 743 }
NYX 0:85b3fd62ea1a 744
NYX 0:85b3fd62ea1a 745 MODIFY_REG(ADCx->CR2,
NYX 0:85b3fd62ea1a 746 ADC_CR2_EXTSEL
NYX 0:85b3fd62ea1a 747 | ADC_CR2_EXTEN
NYX 0:85b3fd62ea1a 748 | ADC_CR2_CONT
NYX 0:85b3fd62ea1a 749 | ADC_CR2_DMA
NYX 0:85b3fd62ea1a 750 | ADC_CR2_DDS
NYX 0:85b3fd62ea1a 751 ,
NYX 0:85b3fd62ea1a 752 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
NYX 0:85b3fd62ea1a 753 | ADC_REG_InitStruct->ContinuousMode
NYX 0:85b3fd62ea1a 754 | ADC_REG_InitStruct->DMATransfer
NYX 0:85b3fd62ea1a 755 );
NYX 0:85b3fd62ea1a 756
NYX 0:85b3fd62ea1a 757 /* Set ADC group regular sequencer length and scan direction */
NYX 0:85b3fd62ea1a 758 /* Note: Hardware constraint (refer to description of this function): */
NYX 0:85b3fd62ea1a 759 /* Note: If ADC instance feature scan mode is disabled */
NYX 0:85b3fd62ea1a 760 /* (refer to ADC instance initialization structure */
NYX 0:85b3fd62ea1a 761 /* parameter @ref SequencersScanMode */
NYX 0:85b3fd62ea1a 762 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
NYX 0:85b3fd62ea1a 763 /* this parameter is discarded. */
NYX 0:85b3fd62ea1a 764 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
NYX 0:85b3fd62ea1a 765 }
NYX 0:85b3fd62ea1a 766 else
NYX 0:85b3fd62ea1a 767 {
NYX 0:85b3fd62ea1a 768 /* Initialization error: ADC instance is not disabled. */
NYX 0:85b3fd62ea1a 769 status = ERROR;
NYX 0:85b3fd62ea1a 770 }
NYX 0:85b3fd62ea1a 771 return status;
NYX 0:85b3fd62ea1a 772 }
NYX 0:85b3fd62ea1a 773
NYX 0:85b3fd62ea1a 774 /**
NYX 0:85b3fd62ea1a 775 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
NYX 0:85b3fd62ea1a 776 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
NYX 0:85b3fd62ea1a 777 * whose fields will be set to default values.
NYX 0:85b3fd62ea1a 778 * @retval None
NYX 0:85b3fd62ea1a 779 */
NYX 0:85b3fd62ea1a 780 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
NYX 0:85b3fd62ea1a 781 {
NYX 0:85b3fd62ea1a 782 /* Set ADC_REG_InitStruct fields to default values */
NYX 0:85b3fd62ea1a 783 /* Set fields of ADC group regular */
NYX 0:85b3fd62ea1a 784 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
NYX 0:85b3fd62ea1a 785 /* ADC conversion. */
NYX 0:85b3fd62ea1a 786 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
NYX 0:85b3fd62ea1a 787 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
NYX 0:85b3fd62ea1a 788 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
NYX 0:85b3fd62ea1a 789 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
NYX 0:85b3fd62ea1a 790 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
NYX 0:85b3fd62ea1a 791 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
NYX 0:85b3fd62ea1a 792 }
NYX 0:85b3fd62ea1a 793
NYX 0:85b3fd62ea1a 794 /**
NYX 0:85b3fd62ea1a 795 * @brief Initialize some features of ADC group injected.
NYX 0:85b3fd62ea1a 796 * @note These parameters have an impact on ADC scope: ADC group injected.
NYX 0:85b3fd62ea1a 797 * Refer to corresponding unitary functions into
NYX 0:85b3fd62ea1a 798 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
NYX 0:85b3fd62ea1a 799 * (functions with prefix "INJ").
NYX 0:85b3fd62ea1a 800 * @note The setting of these parameters by function @ref LL_ADC_Init()
NYX 0:85b3fd62ea1a 801 * is conditioned to ADC state:
NYX 0:85b3fd62ea1a 802 * ADC instance must be disabled.
NYX 0:85b3fd62ea1a 803 * This condition is applied to all ADC features, for efficiency
NYX 0:85b3fd62ea1a 804 * and compatibility over all STM32 families. However, the different
NYX 0:85b3fd62ea1a 805 * features can be set under different ADC state conditions
NYX 0:85b3fd62ea1a 806 * (setting possible with ADC enabled without conversion on going,
NYX 0:85b3fd62ea1a 807 * ADC enabled with conversion on going, ...)
NYX 0:85b3fd62ea1a 808 * Each feature can be updated afterwards with a unitary function
NYX 0:85b3fd62ea1a 809 * and potentially with ADC in a different state than disabled,
NYX 0:85b3fd62ea1a 810 * refer to description of each function for setting
NYX 0:85b3fd62ea1a 811 * conditioned to ADC state.
NYX 0:85b3fd62ea1a 812 * @note After using this function, other features must be configured
NYX 0:85b3fd62ea1a 813 * using LL unitary functions.
NYX 0:85b3fd62ea1a 814 * The minimum configuration remaining to be done is:
NYX 0:85b3fd62ea1a 815 * - Set ADC group injected sequencer:
NYX 0:85b3fd62ea1a 816 * map channel on the selected sequencer rank.
NYX 0:85b3fd62ea1a 817 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
NYX 0:85b3fd62ea1a 818 * - Set ADC channel sampling time
NYX 0:85b3fd62ea1a 819 * Refer to function LL_ADC_SetChannelSamplingTime();
NYX 0:85b3fd62ea1a 820 * @param ADCx ADC instance
NYX 0:85b3fd62ea1a 821 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
NYX 0:85b3fd62ea1a 822 * @retval An ErrorStatus enumeration value:
NYX 0:85b3fd62ea1a 823 * - SUCCESS: ADC registers are initialized
NYX 0:85b3fd62ea1a 824 * - ERROR: ADC registers are not initialized
NYX 0:85b3fd62ea1a 825 */
NYX 0:85b3fd62ea1a 826 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
NYX 0:85b3fd62ea1a 827 {
NYX 0:85b3fd62ea1a 828 ErrorStatus status = SUCCESS;
NYX 0:85b3fd62ea1a 829
NYX 0:85b3fd62ea1a 830 /* Check the parameters */
NYX 0:85b3fd62ea1a 831 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
NYX 0:85b3fd62ea1a 832 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
NYX 0:85b3fd62ea1a 833 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
NYX 0:85b3fd62ea1a 834 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
NYX 0:85b3fd62ea1a 835 {
NYX 0:85b3fd62ea1a 836 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
NYX 0:85b3fd62ea1a 837 }
NYX 0:85b3fd62ea1a 838 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
NYX 0:85b3fd62ea1a 839
NYX 0:85b3fd62ea1a 840 /* Note: Hardware constraint (refer to description of this function): */
NYX 0:85b3fd62ea1a 841 /* ADC instance must be disabled. */
NYX 0:85b3fd62ea1a 842 if(LL_ADC_IsEnabled(ADCx) == 0U)
NYX 0:85b3fd62ea1a 843 {
NYX 0:85b3fd62ea1a 844 /* Configuration of ADC hierarchical scope: */
NYX 0:85b3fd62ea1a 845 /* - ADC group injected */
NYX 0:85b3fd62ea1a 846 /* - Set ADC group injected trigger source */
NYX 0:85b3fd62ea1a 847 /* - Set ADC group injected sequencer length */
NYX 0:85b3fd62ea1a 848 /* - Set ADC group injected sequencer discontinuous mode */
NYX 0:85b3fd62ea1a 849 /* - Set ADC group injected conversion trigger: independent or */
NYX 0:85b3fd62ea1a 850 /* from ADC group regular */
NYX 0:85b3fd62ea1a 851 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
NYX 0:85b3fd62ea1a 852 /* ADC conversion. */
NYX 0:85b3fd62ea1a 853 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
NYX 0:85b3fd62ea1a 854 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
NYX 0:85b3fd62ea1a 855 {
NYX 0:85b3fd62ea1a 856 MODIFY_REG(ADCx->CR1,
NYX 0:85b3fd62ea1a 857 ADC_CR1_JDISCEN
NYX 0:85b3fd62ea1a 858 | ADC_CR1_JAUTO
NYX 0:85b3fd62ea1a 859 ,
NYX 0:85b3fd62ea1a 860 ADC_INJ_InitStruct->SequencerDiscont
NYX 0:85b3fd62ea1a 861 | ADC_INJ_InitStruct->TrigAuto
NYX 0:85b3fd62ea1a 862 );
NYX 0:85b3fd62ea1a 863 }
NYX 0:85b3fd62ea1a 864 else
NYX 0:85b3fd62ea1a 865 {
NYX 0:85b3fd62ea1a 866 MODIFY_REG(ADCx->CR1,
NYX 0:85b3fd62ea1a 867 ADC_CR1_JDISCEN
NYX 0:85b3fd62ea1a 868 | ADC_CR1_JAUTO
NYX 0:85b3fd62ea1a 869 ,
NYX 0:85b3fd62ea1a 870 LL_ADC_REG_SEQ_DISCONT_DISABLE
NYX 0:85b3fd62ea1a 871 | ADC_INJ_InitStruct->TrigAuto
NYX 0:85b3fd62ea1a 872 );
NYX 0:85b3fd62ea1a 873 }
NYX 0:85b3fd62ea1a 874
NYX 0:85b3fd62ea1a 875 MODIFY_REG(ADCx->CR2,
NYX 0:85b3fd62ea1a 876 ADC_CR2_JEXTSEL
NYX 0:85b3fd62ea1a 877 | ADC_CR2_JEXTEN
NYX 0:85b3fd62ea1a 878 ,
NYX 0:85b3fd62ea1a 879 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
NYX 0:85b3fd62ea1a 880 );
NYX 0:85b3fd62ea1a 881
NYX 0:85b3fd62ea1a 882 /* Note: Hardware constraint (refer to description of this function): */
NYX 0:85b3fd62ea1a 883 /* Note: If ADC instance feature scan mode is disabled */
NYX 0:85b3fd62ea1a 884 /* (refer to ADC instance initialization structure */
NYX 0:85b3fd62ea1a 885 /* parameter @ref SequencersScanMode */
NYX 0:85b3fd62ea1a 886 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
NYX 0:85b3fd62ea1a 887 /* this parameter is discarded. */
NYX 0:85b3fd62ea1a 888 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
NYX 0:85b3fd62ea1a 889 }
NYX 0:85b3fd62ea1a 890 else
NYX 0:85b3fd62ea1a 891 {
NYX 0:85b3fd62ea1a 892 /* Initialization error: ADC instance is not disabled. */
NYX 0:85b3fd62ea1a 893 status = ERROR;
NYX 0:85b3fd62ea1a 894 }
NYX 0:85b3fd62ea1a 895 return status;
NYX 0:85b3fd62ea1a 896 }
NYX 0:85b3fd62ea1a 897
NYX 0:85b3fd62ea1a 898 /**
NYX 0:85b3fd62ea1a 899 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
NYX 0:85b3fd62ea1a 900 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
NYX 0:85b3fd62ea1a 901 * whose fields will be set to default values.
NYX 0:85b3fd62ea1a 902 * @retval None
NYX 0:85b3fd62ea1a 903 */
NYX 0:85b3fd62ea1a 904 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
NYX 0:85b3fd62ea1a 905 {
NYX 0:85b3fd62ea1a 906 /* Set ADC_INJ_InitStruct fields to default values */
NYX 0:85b3fd62ea1a 907 /* Set fields of ADC group injected */
NYX 0:85b3fd62ea1a 908 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
NYX 0:85b3fd62ea1a 909 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
NYX 0:85b3fd62ea1a 910 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
NYX 0:85b3fd62ea1a 911 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
NYX 0:85b3fd62ea1a 912 }
NYX 0:85b3fd62ea1a 913
NYX 0:85b3fd62ea1a 914 /**
NYX 0:85b3fd62ea1a 915 * @}
NYX 0:85b3fd62ea1a 916 */
NYX 0:85b3fd62ea1a 917
NYX 0:85b3fd62ea1a 918 /**
NYX 0:85b3fd62ea1a 919 * @}
NYX 0:85b3fd62ea1a 920 */
NYX 0:85b3fd62ea1a 921
NYX 0:85b3fd62ea1a 922 /**
NYX 0:85b3fd62ea1a 923 * @}
NYX 0:85b3fd62ea1a 924 */
NYX 0:85b3fd62ea1a 925
NYX 0:85b3fd62ea1a 926 #endif /* ADC1 || ADC2 || ADC3 */
NYX 0:85b3fd62ea1a 927
NYX 0:85b3fd62ea1a 928 /**
NYX 0:85b3fd62ea1a 929 * @}
NYX 0:85b3fd62ea1a 930 */
NYX 0:85b3fd62ea1a 931
NYX 0:85b3fd62ea1a 932 #endif /* USE_FULL_LL_DRIVER */
NYX 0:85b3fd62ea1a 933
NYX 0:85b3fd62ea1a 934 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/