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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

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User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_tim.h
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief Header file of TIM HAL module.
NYX	0:85b3fd62ea1a	8	******************************************************************************
NYX	0:85b3fd62ea1a	9	* @attention
NYX	0:85b3fd62ea1a	10	*
NYX	0:85b3fd62ea1a	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	12	*
NYX	0:85b3fd62ea1a	13	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	14	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	15	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	16	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	18	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	19	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	21	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	22	* without specific prior written permission.
NYX	0:85b3fd62ea1a	23	*
NYX	0:85b3fd62ea1a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	34	*
NYX	0:85b3fd62ea1a	35	******************************************************************************
NYX	0:85b3fd62ea1a	36	*/
NYX	0:85b3fd62ea1a	37
NYX	0:85b3fd62ea1a	38	/* Define to prevent recursive inclusion -------------------------------------*/
NYX	0:85b3fd62ea1a	39	#ifndef __STM32F4xx_HAL_TIM_H
NYX	0:85b3fd62ea1a	40	#define __STM32F4xx_HAL_TIM_H
NYX	0:85b3fd62ea1a	41
NYX	0:85b3fd62ea1a	42	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	43	extern "C" {
NYX	0:85b3fd62ea1a	44	#endif
NYX	0:85b3fd62ea1a	45
NYX	0:85b3fd62ea1a	46	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	47	#include "stm32f4xx_hal_def.h"
NYX	0:85b3fd62ea1a	48
NYX	0:85b3fd62ea1a	49	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	50	* @{
NYX	0:85b3fd62ea1a	51	*/
NYX	0:85b3fd62ea1a	52
NYX	0:85b3fd62ea1a	53	/** @addtogroup TIM
NYX	0:85b3fd62ea1a	54	* @{
NYX	0:85b3fd62ea1a	55	*/
NYX	0:85b3fd62ea1a	56
NYX	0:85b3fd62ea1a	57	/* Exported types ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	58	/** @defgroup TIM_Exported_Types TIM Exported Types
NYX	0:85b3fd62ea1a	59	* @{
NYX	0:85b3fd62ea1a	60	*/
NYX	0:85b3fd62ea1a	61
NYX	0:85b3fd62ea1a	62	/**
NYX	0:85b3fd62ea1a	63	* @brief TIM Time base Configuration Structure definition
NYX	0:85b3fd62ea1a	64	*/
NYX	0:85b3fd62ea1a	65	typedef struct
NYX	0:85b3fd62ea1a	66	{
NYX	0:85b3fd62ea1a	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
NYX	0:85b3fd62ea1a	68	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
NYX	0:85b3fd62ea1a	69
NYX	0:85b3fd62ea1a	70	uint32_t CounterMode; /*!< Specifies the counter mode.
NYX	0:85b3fd62ea1a	71	This parameter can be a value of @ref TIM_Counter_Mode */
NYX	0:85b3fd62ea1a	72
NYX	0:85b3fd62ea1a	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
NYX	0:85b3fd62ea1a	74	Auto-Reload Register at the next update event.
NYX	0:85b3fd62ea1a	75	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
NYX	0:85b3fd62ea1a	76
NYX	0:85b3fd62ea1a	77	uint32_t ClockDivision; /*!< Specifies the clock division.
NYX	0:85b3fd62ea1a	78	This parameter can be a value of @ref TIM_ClockDivision */
NYX	0:85b3fd62ea1a	79
NYX	0:85b3fd62ea1a	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
NYX	0:85b3fd62ea1a	81	reaches zero, an update event is generated and counting restarts
NYX	0:85b3fd62ea1a	82	from the RCR value (N).
NYX	0:85b3fd62ea1a	83	This means in PWM mode that (N+1) corresponds to:
NYX	0:85b3fd62ea1a	84	- the number of PWM periods in edge-aligned mode
NYX	0:85b3fd62ea1a	85	- the number of half PWM period in center-aligned mode
NYX	0:85b3fd62ea1a	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
NYX	0:85b3fd62ea1a	87	@note This parameter is valid only for TIM1 and TIM8. */
NYX	0:85b3fd62ea1a	88	} TIM_Base_InitTypeDef;
NYX	0:85b3fd62ea1a	89
NYX	0:85b3fd62ea1a	90	/**
NYX	0:85b3fd62ea1a	91	* @brief TIM Output Compare Configuration Structure definition
NYX	0:85b3fd62ea1a	92	*/
NYX	0:85b3fd62ea1a	93
NYX	0:85b3fd62ea1a	94	typedef struct
NYX	0:85b3fd62ea1a	95	{
NYX	0:85b3fd62ea1a	96	uint32_t OCMode; /*!< Specifies the TIM mode.
NYX	0:85b3fd62ea1a	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
NYX	0:85b3fd62ea1a	98
NYX	0:85b3fd62ea1a	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
NYX	0:85b3fd62ea1a	100	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
NYX	0:85b3fd62ea1a	101
NYX	0:85b3fd62ea1a	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
NYX	0:85b3fd62ea1a	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
NYX	0:85b3fd62ea1a	104
NYX	0:85b3fd62ea1a	105	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
NYX	0:85b3fd62ea1a	106	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
NYX	0:85b3fd62ea1a	107	@note This parameter is valid only for TIM1 and TIM8. */
NYX	0:85b3fd62ea1a	108
NYX	0:85b3fd62ea1a	109	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
NYX	0:85b3fd62ea1a	110	This parameter can be a value of @ref TIM_Output_Fast_State
NYX	0:85b3fd62ea1a	111	@note This parameter is valid only in PWM1 and PWM2 mode. */
NYX	0:85b3fd62ea1a	112
NYX	0:85b3fd62ea1a	113
NYX	0:85b3fd62ea1a	114	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
NYX	0:85b3fd62ea1a	115	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
NYX	0:85b3fd62ea1a	116	@note This parameter is valid only for TIM1 and TIM8. */
NYX	0:85b3fd62ea1a	117
NYX	0:85b3fd62ea1a	118	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
NYX	0:85b3fd62ea1a	119	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
NYX	0:85b3fd62ea1a	120	@note This parameter is valid only for TIM1 and TIM8. */
NYX	0:85b3fd62ea1a	121	} TIM_OC_InitTypeDef;
NYX	0:85b3fd62ea1a	122
NYX	0:85b3fd62ea1a	123	/**
NYX	0:85b3fd62ea1a	124	* @brief TIM One Pulse Mode Configuration Structure definition
NYX	0:85b3fd62ea1a	125	*/
NYX	0:85b3fd62ea1a	126	typedef struct
NYX	0:85b3fd62ea1a	127	{
NYX	0:85b3fd62ea1a	128	uint32_t OCMode; /*!< Specifies the TIM mode.
NYX	0:85b3fd62ea1a	129	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
NYX	0:85b3fd62ea1a	130
NYX	0:85b3fd62ea1a	131	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
NYX	0:85b3fd62ea1a	132	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
NYX	0:85b3fd62ea1a	133
NYX	0:85b3fd62ea1a	134	uint32_t OCPolarity; /*!< Specifies the output polarity.
NYX	0:85b3fd62ea1a	135	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
NYX	0:85b3fd62ea1a	136
NYX	0:85b3fd62ea1a	137	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
NYX	0:85b3fd62ea1a	138	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
NYX	0:85b3fd62ea1a	139	@note This parameter is valid only for TIM1 and TIM8. */
NYX	0:85b3fd62ea1a	140
NYX	0:85b3fd62ea1a	141	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
NYX	0:85b3fd62ea1a	142	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
NYX	0:85b3fd62ea1a	143	@note This parameter is valid only for TIM1 and TIM8. */
NYX	0:85b3fd62ea1a	144
NYX	0:85b3fd62ea1a	145	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
NYX	0:85b3fd62ea1a	146	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
NYX	0:85b3fd62ea1a	147	@note This parameter is valid only for TIM1 and TIM8. */
NYX	0:85b3fd62ea1a	148
NYX	0:85b3fd62ea1a	149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
NYX	0:85b3fd62ea1a	150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
NYX	0:85b3fd62ea1a	151
NYX	0:85b3fd62ea1a	152	uint32_t ICSelection; /*!< Specifies the input.
NYX	0:85b3fd62ea1a	153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
NYX	0:85b3fd62ea1a	154
NYX	0:85b3fd62ea1a	155	uint32_t ICFilter; /*!< Specifies the input capture filter.
NYX	0:85b3fd62ea1a	156	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
NYX	0:85b3fd62ea1a	157	} TIM_OnePulse_InitTypeDef;
NYX	0:85b3fd62ea1a	158
NYX	0:85b3fd62ea1a	159
NYX	0:85b3fd62ea1a	160	/**
NYX	0:85b3fd62ea1a	161	* @brief TIM Input Capture Configuration Structure definition
NYX	0:85b3fd62ea1a	162	*/
NYX	0:85b3fd62ea1a	163
NYX	0:85b3fd62ea1a	164	typedef struct
NYX	0:85b3fd62ea1a	165	{
NYX	0:85b3fd62ea1a	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
NYX	0:85b3fd62ea1a	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
NYX	0:85b3fd62ea1a	168
NYX	0:85b3fd62ea1a	169	uint32_t ICSelection; /*!< Specifies the input.
NYX	0:85b3fd62ea1a	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
NYX	0:85b3fd62ea1a	171
NYX	0:85b3fd62ea1a	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
NYX	0:85b3fd62ea1a	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
NYX	0:85b3fd62ea1a	174
NYX	0:85b3fd62ea1a	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
NYX	0:85b3fd62ea1a	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
NYX	0:85b3fd62ea1a	177	} TIM_IC_InitTypeDef;
NYX	0:85b3fd62ea1a	178
NYX	0:85b3fd62ea1a	179	/**
NYX	0:85b3fd62ea1a	180	* @brief TIM Encoder Configuration Structure definition
NYX	0:85b3fd62ea1a	181	*/
NYX	0:85b3fd62ea1a	182
NYX	0:85b3fd62ea1a	183	typedef struct
NYX	0:85b3fd62ea1a	184	{
NYX	0:85b3fd62ea1a	185	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
NYX	0:85b3fd62ea1a	186	This parameter can be a value of @ref TIM_Encoder_Mode */
NYX	0:85b3fd62ea1a	187
NYX	0:85b3fd62ea1a	188	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
NYX	0:85b3fd62ea1a	189	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
NYX	0:85b3fd62ea1a	190
NYX	0:85b3fd62ea1a	191	uint32_t IC1Selection; /*!< Specifies the input.
NYX	0:85b3fd62ea1a	192	This parameter can be a value of @ref TIM_Input_Capture_Selection */
NYX	0:85b3fd62ea1a	193
NYX	0:85b3fd62ea1a	194	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
NYX	0:85b3fd62ea1a	195	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
NYX	0:85b3fd62ea1a	196
NYX	0:85b3fd62ea1a	197	uint32_t IC1Filter; /*!< Specifies the input capture filter.
NYX	0:85b3fd62ea1a	198	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
NYX	0:85b3fd62ea1a	199
NYX	0:85b3fd62ea1a	200	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
NYX	0:85b3fd62ea1a	201	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
NYX	0:85b3fd62ea1a	202
NYX	0:85b3fd62ea1a	203	uint32_t IC2Selection; /*!< Specifies the input.
NYX	0:85b3fd62ea1a	204	This parameter can be a value of @ref TIM_Input_Capture_Selection */
NYX	0:85b3fd62ea1a	205
NYX	0:85b3fd62ea1a	206	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
NYX	0:85b3fd62ea1a	207	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
NYX	0:85b3fd62ea1a	208
NYX	0:85b3fd62ea1a	209	uint32_t IC2Filter; /*!< Specifies the input capture filter.
NYX	0:85b3fd62ea1a	210	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
NYX	0:85b3fd62ea1a	211	} TIM_Encoder_InitTypeDef;
NYX	0:85b3fd62ea1a	212
NYX	0:85b3fd62ea1a	213	/**
NYX	0:85b3fd62ea1a	214	* @brief Clock Configuration Handle Structure definition
NYX	0:85b3fd62ea1a	215	*/
NYX	0:85b3fd62ea1a	216	typedef struct
NYX	0:85b3fd62ea1a	217	{
NYX	0:85b3fd62ea1a	218	uint32_t ClockSource; /*!< TIM clock sources.
NYX	0:85b3fd62ea1a	219	This parameter can be a value of @ref TIM_Clock_Source */
NYX	0:85b3fd62ea1a	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
NYX	0:85b3fd62ea1a	221	This parameter can be a value of @ref TIM_Clock_Polarity */
NYX	0:85b3fd62ea1a	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
NYX	0:85b3fd62ea1a	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
NYX	0:85b3fd62ea1a	224	uint32_t ClockFilter; /*!< TIM clock filter.
NYX	0:85b3fd62ea1a	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
NYX	0:85b3fd62ea1a	226	}TIM_ClockConfigTypeDef;
NYX	0:85b3fd62ea1a	227
NYX	0:85b3fd62ea1a	228	/**
NYX	0:85b3fd62ea1a	229	* @brief Clear Input Configuration Handle Structure definition
NYX	0:85b3fd62ea1a	230	*/
NYX	0:85b3fd62ea1a	231	typedef struct
NYX	0:85b3fd62ea1a	232	{
NYX	0:85b3fd62ea1a	233	uint32_t ClearInputState; /*!< TIM clear Input state.
NYX	0:85b3fd62ea1a	234	This parameter can be ENABLE or DISABLE */
NYX	0:85b3fd62ea1a	235	uint32_t ClearInputSource; /*!< TIM clear Input sources.
NYX	0:85b3fd62ea1a	236	This parameter can be a value of @ref TIM_ClearInput_Source */
NYX	0:85b3fd62ea1a	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
NYX	0:85b3fd62ea1a	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
NYX	0:85b3fd62ea1a	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
NYX	0:85b3fd62ea1a	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
NYX	0:85b3fd62ea1a	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
NYX	0:85b3fd62ea1a	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
NYX	0:85b3fd62ea1a	243	}TIM_ClearInputConfigTypeDef;
NYX	0:85b3fd62ea1a	244
NYX	0:85b3fd62ea1a	245	/**
NYX	0:85b3fd62ea1a	246	* @brief TIM Slave configuration Structure definition
NYX	0:85b3fd62ea1a	247	*/
NYX	0:85b3fd62ea1a	248	typedef struct {
NYX	0:85b3fd62ea1a	249	uint32_t SlaveMode; /*!< Slave mode selection
NYX	0:85b3fd62ea1a	250	This parameter can be a value of @ref TIM_Slave_Mode */
NYX	0:85b3fd62ea1a	251	uint32_t InputTrigger; /*!< Input Trigger source
NYX	0:85b3fd62ea1a	252	This parameter can be a value of @ref TIM_Trigger_Selection */
NYX	0:85b3fd62ea1a	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
NYX	0:85b3fd62ea1a	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
NYX	0:85b3fd62ea1a	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
NYX	0:85b3fd62ea1a	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
NYX	0:85b3fd62ea1a	257	uint32_t TriggerFilter; /*!< Input trigger filter
NYX	0:85b3fd62ea1a	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
NYX	0:85b3fd62ea1a	259
NYX	0:85b3fd62ea1a	260	}TIM_SlaveConfigTypeDef;
NYX	0:85b3fd62ea1a	261
NYX	0:85b3fd62ea1a	262	/**
NYX	0:85b3fd62ea1a	263	* @brief HAL State structures definition
NYX	0:85b3fd62ea1a	264	*/
NYX	0:85b3fd62ea1a	265	typedef enum
NYX	0:85b3fd62ea1a	266	{
NYX	0:85b3fd62ea1a	267	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
NYX	0:85b3fd62ea1a	268	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
NYX	0:85b3fd62ea1a	269	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
NYX	0:85b3fd62ea1a	270	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
NYX	0:85b3fd62ea1a	271	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
NYX	0:85b3fd62ea1a	272	}HAL_TIM_StateTypeDef;
NYX	0:85b3fd62ea1a	273
NYX	0:85b3fd62ea1a	274	/**
NYX	0:85b3fd62ea1a	275	* @brief HAL Active channel structures definition
NYX	0:85b3fd62ea1a	276	*/
NYX	0:85b3fd62ea1a	277	typedef enum
NYX	0:85b3fd62ea1a	278	{
NYX	0:85b3fd62ea1a	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
NYX	0:85b3fd62ea1a	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
NYX	0:85b3fd62ea1a	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
NYX	0:85b3fd62ea1a	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
NYX	0:85b3fd62ea1a	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
NYX	0:85b3fd62ea1a	284	}HAL_TIM_ActiveChannel;
NYX	0:85b3fd62ea1a	285
NYX	0:85b3fd62ea1a	286	/**
NYX	0:85b3fd62ea1a	287	* @brief TIM Time Base Handle Structure definition
NYX	0:85b3fd62ea1a	288	*/
NYX	0:85b3fd62ea1a	289	typedef struct
NYX	0:85b3fd62ea1a	290	{
NYX	0:85b3fd62ea1a	291	TIM_TypeDef Instance; /!< Register base address */
NYX	0:85b3fd62ea1a	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
NYX	0:85b3fd62ea1a	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
NYX	0:85b3fd62ea1a	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
NYX	0:85b3fd62ea1a	295	This array is accessed by a @ref DMA_Handle_index */
NYX	0:85b3fd62ea1a	296	HAL_LockTypeDef Lock; /!< Locking object /
NYX	0:85b3fd62ea1a	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
NYX	0:85b3fd62ea1a	298	}TIM_HandleTypeDef;
NYX	0:85b3fd62ea1a	299	/**
NYX	0:85b3fd62ea1a	300	* @}
NYX	0:85b3fd62ea1a	301	*/
NYX	0:85b3fd62ea1a	302
NYX	0:85b3fd62ea1a	303	/* Exported constants --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	304	/** @defgroup TIM_Exported_Constants TIM Exported Constants
NYX	0:85b3fd62ea1a	305	* @{
NYX	0:85b3fd62ea1a	306	*/
NYX	0:85b3fd62ea1a	307
NYX	0:85b3fd62ea1a	308	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
NYX	0:85b3fd62ea1a	309	* @{
NYX	0:85b3fd62ea1a	310	*/
NYX	0:85b3fd62ea1a	311	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
NYX	0:85b3fd62ea1a	312	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
NYX	0:85b3fd62ea1a	313	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
NYX	0:85b3fd62ea1a	314	/**
NYX	0:85b3fd62ea1a	315	* @}
NYX	0:85b3fd62ea1a	316	*/
NYX	0:85b3fd62ea1a	317
NYX	0:85b3fd62ea1a	318	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
NYX	0:85b3fd62ea1a	319	* @{
NYX	0:85b3fd62ea1a	320	*/
NYX	0:85b3fd62ea1a	321	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
NYX	0:85b3fd62ea1a	322	#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /!< Polarity for ETR source /
NYX	0:85b3fd62ea1a	323	/**
NYX	0:85b3fd62ea1a	324	* @}
NYX	0:85b3fd62ea1a	325	*/
NYX	0:85b3fd62ea1a	326
NYX	0:85b3fd62ea1a	327	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
NYX	0:85b3fd62ea1a	328	* @{
NYX	0:85b3fd62ea1a	329	*/
NYX	0:85b3fd62ea1a	330	#define TIM_ETRPRESCALER_DIV1 0x00000000U /!< No prescaler is used /
NYX	0:85b3fd62ea1a	331	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
NYX	0:85b3fd62ea1a	332	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
NYX	0:85b3fd62ea1a	333	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
NYX	0:85b3fd62ea1a	334	/**
NYX	0:85b3fd62ea1a	335	* @}
NYX	0:85b3fd62ea1a	336	*/
NYX	0:85b3fd62ea1a	337
NYX	0:85b3fd62ea1a	338	/** @defgroup TIM_Counter_Mode TIM Counter Mode
NYX	0:85b3fd62ea1a	339	* @{
NYX	0:85b3fd62ea1a	340	*/
NYX	0:85b3fd62ea1a	341	#define TIM_COUNTERMODE_UP 0x00000000U
NYX	0:85b3fd62ea1a	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
NYX	0:85b3fd62ea1a	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
NYX	0:85b3fd62ea1a	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
NYX	0:85b3fd62ea1a	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
NYX	0:85b3fd62ea1a	346	/**
NYX	0:85b3fd62ea1a	347	* @}
NYX	0:85b3fd62ea1a	348	*/
NYX	0:85b3fd62ea1a	349
NYX	0:85b3fd62ea1a	350	/** @defgroup TIM_ClockDivision TIM Clock Division
NYX	0:85b3fd62ea1a	351	* @{
NYX	0:85b3fd62ea1a	352	*/
NYX	0:85b3fd62ea1a	353	#define TIM_CLOCKDIVISION_DIV1 0x00000000U
NYX	0:85b3fd62ea1a	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
NYX	0:85b3fd62ea1a	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
NYX	0:85b3fd62ea1a	356	/**
NYX	0:85b3fd62ea1a	357	* @}
NYX	0:85b3fd62ea1a	358	*/
NYX	0:85b3fd62ea1a	359
NYX	0:85b3fd62ea1a	360	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
NYX	0:85b3fd62ea1a	361	* @{
NYX	0:85b3fd62ea1a	362	*/
NYX	0:85b3fd62ea1a	363	#define TIM_OCMODE_TIMING 0x00000000U
NYX	0:85b3fd62ea1a	364	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
NYX	0:85b3fd62ea1a	365	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
NYX	0:85b3fd62ea1a	366	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
NYX	0:85b3fd62ea1a	367	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
NYX	0:85b3fd62ea1a	368	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
NYX	0:85b3fd62ea1a	369	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
NYX	0:85b3fd62ea1a	370	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
NYX	0:85b3fd62ea1a	371
NYX	0:85b3fd62ea1a	372	/**
NYX	0:85b3fd62ea1a	373	* @}
NYX	0:85b3fd62ea1a	374	*/
NYX	0:85b3fd62ea1a	375
NYX	0:85b3fd62ea1a	376	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
NYX	0:85b3fd62ea1a	377	* @{
NYX	0:85b3fd62ea1a	378	*/
NYX	0:85b3fd62ea1a	379	#define TIM_OCFAST_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	380	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
NYX	0:85b3fd62ea1a	381	/**
NYX	0:85b3fd62ea1a	382	* @}
NYX	0:85b3fd62ea1a	383	*/
NYX	0:85b3fd62ea1a	384
NYX	0:85b3fd62ea1a	385	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
NYX	0:85b3fd62ea1a	386	* @{
NYX	0:85b3fd62ea1a	387	*/
NYX	0:85b3fd62ea1a	388	#define TIM_OCPOLARITY_HIGH 0x00000000U
NYX	0:85b3fd62ea1a	389	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
NYX	0:85b3fd62ea1a	390	/**
NYX	0:85b3fd62ea1a	391	* @}
NYX	0:85b3fd62ea1a	392	*/
NYX	0:85b3fd62ea1a	393
NYX	0:85b3fd62ea1a	394	/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
NYX	0:85b3fd62ea1a	395	* @{
NYX	0:85b3fd62ea1a	396	*/
NYX	0:85b3fd62ea1a	397	#define TIM_OCNPOLARITY_HIGH 0x00000000U
NYX	0:85b3fd62ea1a	398	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
NYX	0:85b3fd62ea1a	399	/**
NYX	0:85b3fd62ea1a	400	* @}
NYX	0:85b3fd62ea1a	401	*/
NYX	0:85b3fd62ea1a	402
NYX	0:85b3fd62ea1a	403	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
NYX	0:85b3fd62ea1a	404	* @{
NYX	0:85b3fd62ea1a	405	*/
NYX	0:85b3fd62ea1a	406	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
NYX	0:85b3fd62ea1a	407	#define TIM_OCIDLESTATE_RESET 0x00000000U
NYX	0:85b3fd62ea1a	408	/**
NYX	0:85b3fd62ea1a	409	* @}
NYX	0:85b3fd62ea1a	410	*/
NYX	0:85b3fd62ea1a	411
NYX	0:85b3fd62ea1a	412	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
NYX	0:85b3fd62ea1a	413	* @{
NYX	0:85b3fd62ea1a	414	*/
NYX	0:85b3fd62ea1a	415	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
NYX	0:85b3fd62ea1a	416	#define TIM_OCNIDLESTATE_RESET 0x00000000U
NYX	0:85b3fd62ea1a	417	/**
NYX	0:85b3fd62ea1a	418	* @}
NYX	0:85b3fd62ea1a	419	*/
NYX	0:85b3fd62ea1a	420
NYX	0:85b3fd62ea1a	421	/** @defgroup TIM_Channel TIM Channel
NYX	0:85b3fd62ea1a	422	* @{
NYX	0:85b3fd62ea1a	423	*/
NYX	0:85b3fd62ea1a	424	#define TIM_CHANNEL_1 0x00000000U
NYX	0:85b3fd62ea1a	425	#define TIM_CHANNEL_2 0x00000004U
NYX	0:85b3fd62ea1a	426	#define TIM_CHANNEL_3 0x00000008U
NYX	0:85b3fd62ea1a	427	#define TIM_CHANNEL_4 0x0000000CU
NYX	0:85b3fd62ea1a	428	#define TIM_CHANNEL_ALL 0x00000018U
NYX	0:85b3fd62ea1a	429
NYX	0:85b3fd62ea1a	430	/**
NYX	0:85b3fd62ea1a	431	* @}
NYX	0:85b3fd62ea1a	432	*/
NYX	0:85b3fd62ea1a	433
NYX	0:85b3fd62ea1a	434	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
NYX	0:85b3fd62ea1a	435	* @{
NYX	0:85b3fd62ea1a	436	*/
NYX	0:85b3fd62ea1a	437	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
NYX	0:85b3fd62ea1a	438	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
NYX	0:85b3fd62ea1a	439	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
NYX	0:85b3fd62ea1a	440	/**
NYX	0:85b3fd62ea1a	441	* @}
NYX	0:85b3fd62ea1a	442	*/
NYX	0:85b3fd62ea1a	443
NYX	0:85b3fd62ea1a	444	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
NYX	0:85b3fd62ea1a	445	* @{
NYX	0:85b3fd62ea1a	446	*/
NYX	0:85b3fd62ea1a	447	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
NYX	0:85b3fd62ea1a	448	connected to IC1, IC2, IC3 or IC4, respectively */
NYX	0:85b3fd62ea1a	449	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
NYX	0:85b3fd62ea1a	450	connected to IC2, IC1, IC4 or IC3, respectively */
NYX	0:85b3fd62ea1a	451	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
NYX	0:85b3fd62ea1a	452
NYX	0:85b3fd62ea1a	453	/**
NYX	0:85b3fd62ea1a	454	* @}
NYX	0:85b3fd62ea1a	455	*/
NYX	0:85b3fd62ea1a	456
NYX	0:85b3fd62ea1a	457	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
NYX	0:85b3fd62ea1a	458	* @{
NYX	0:85b3fd62ea1a	459	*/
NYX	0:85b3fd62ea1a	460	#define TIM_ICPSC_DIV1 0x00000000U /!< Capture performed each time an edge is detected on the capture input /
NYX	0:85b3fd62ea1a	461	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
NYX	0:85b3fd62ea1a	462	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
NYX	0:85b3fd62ea1a	463	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
NYX	0:85b3fd62ea1a	464	/**
NYX	0:85b3fd62ea1a	465	* @}
NYX	0:85b3fd62ea1a	466	*/
NYX	0:85b3fd62ea1a	467
NYX	0:85b3fd62ea1a	468	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
NYX	0:85b3fd62ea1a	469	* @{
NYX	0:85b3fd62ea1a	470	*/
NYX	0:85b3fd62ea1a	471	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
NYX	0:85b3fd62ea1a	472	#define TIM_OPMODE_REPETITIVE 0x00000000U
NYX	0:85b3fd62ea1a	473	/**
NYX	0:85b3fd62ea1a	474	* @}
NYX	0:85b3fd62ea1a	475	*/
NYX	0:85b3fd62ea1a	476
NYX	0:85b3fd62ea1a	477	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
NYX	0:85b3fd62ea1a	478	* @{
NYX	0:85b3fd62ea1a	479	*/
NYX	0:85b3fd62ea1a	480	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
NYX	0:85b3fd62ea1a	481	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
NYX	0:85b3fd62ea1a	482	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
NYX	0:85b3fd62ea1a	483
NYX	0:85b3fd62ea1a	484	/**
NYX	0:85b3fd62ea1a	485	* @}
NYX	0:85b3fd62ea1a	486	*/
NYX	0:85b3fd62ea1a	487
NYX	0:85b3fd62ea1a	488	/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
NYX	0:85b3fd62ea1a	489	* @{
NYX	0:85b3fd62ea1a	490	*/
NYX	0:85b3fd62ea1a	491	#define TIM_IT_UPDATE (TIM_DIER_UIE)
NYX	0:85b3fd62ea1a	492	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
NYX	0:85b3fd62ea1a	493	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
NYX	0:85b3fd62ea1a	494	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
NYX	0:85b3fd62ea1a	495	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
NYX	0:85b3fd62ea1a	496	#define TIM_IT_COM (TIM_DIER_COMIE)
NYX	0:85b3fd62ea1a	497	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
NYX	0:85b3fd62ea1a	498	#define TIM_IT_BREAK (TIM_DIER_BIE)
NYX	0:85b3fd62ea1a	499	/**
NYX	0:85b3fd62ea1a	500	* @}
NYX	0:85b3fd62ea1a	501	*/
NYX	0:85b3fd62ea1a	502
NYX	0:85b3fd62ea1a	503	/** @defgroup TIM_Commutation_Source TIM Commutation Source
NYX	0:85b3fd62ea1a	504	* @{
NYX	0:85b3fd62ea1a	505	*/
NYX	0:85b3fd62ea1a	506	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
NYX	0:85b3fd62ea1a	507	#define TIM_COMMUTATION_SOFTWARE 0x00000000U
NYX	0:85b3fd62ea1a	508	/**
NYX	0:85b3fd62ea1a	509	* @}
NYX	0:85b3fd62ea1a	510	*/
NYX	0:85b3fd62ea1a	511
NYX	0:85b3fd62ea1a	512	/** @defgroup TIM_DMA_sources TIM DMA sources
NYX	0:85b3fd62ea1a	513	* @{
NYX	0:85b3fd62ea1a	514	*/
NYX	0:85b3fd62ea1a	515	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
NYX	0:85b3fd62ea1a	516	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
NYX	0:85b3fd62ea1a	517	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
NYX	0:85b3fd62ea1a	518	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
NYX	0:85b3fd62ea1a	519	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
NYX	0:85b3fd62ea1a	520	#define TIM_DMA_COM (TIM_DIER_COMDE)
NYX	0:85b3fd62ea1a	521	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
NYX	0:85b3fd62ea1a	522	/**
NYX	0:85b3fd62ea1a	523	* @}
NYX	0:85b3fd62ea1a	524	*/
NYX	0:85b3fd62ea1a	525
NYX	0:85b3fd62ea1a	526	/** @defgroup TIM_Event_Source TIM Event Source
NYX	0:85b3fd62ea1a	527	* @{
NYX	0:85b3fd62ea1a	528	*/
NYX	0:85b3fd62ea1a	529	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
NYX	0:85b3fd62ea1a	530	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
NYX	0:85b3fd62ea1a	531	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
NYX	0:85b3fd62ea1a	532	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
NYX	0:85b3fd62ea1a	533	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
NYX	0:85b3fd62ea1a	534	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
NYX	0:85b3fd62ea1a	535	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
NYX	0:85b3fd62ea1a	536	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
NYX	0:85b3fd62ea1a	537
NYX	0:85b3fd62ea1a	538	/**
NYX	0:85b3fd62ea1a	539	* @}
NYX	0:85b3fd62ea1a	540	*/
NYX	0:85b3fd62ea1a	541
NYX	0:85b3fd62ea1a	542	/** @defgroup TIM_Flag_definition TIM Flag definition
NYX	0:85b3fd62ea1a	543	* @{
NYX	0:85b3fd62ea1a	544	*/
NYX	0:85b3fd62ea1a	545	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
NYX	0:85b3fd62ea1a	546	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
NYX	0:85b3fd62ea1a	547	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
NYX	0:85b3fd62ea1a	548	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
NYX	0:85b3fd62ea1a	549	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
NYX	0:85b3fd62ea1a	550	#define TIM_FLAG_COM (TIM_SR_COMIF)
NYX	0:85b3fd62ea1a	551	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
NYX	0:85b3fd62ea1a	552	#define TIM_FLAG_BREAK (TIM_SR_BIF)
NYX	0:85b3fd62ea1a	553	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
NYX	0:85b3fd62ea1a	554	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
NYX	0:85b3fd62ea1a	555	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
NYX	0:85b3fd62ea1a	556	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
NYX	0:85b3fd62ea1a	557	/**
NYX	0:85b3fd62ea1a	558	* @}
NYX	0:85b3fd62ea1a	559	*/
NYX	0:85b3fd62ea1a	560
NYX	0:85b3fd62ea1a	561	/** @defgroup TIM_Clock_Source TIM Clock Source
NYX	0:85b3fd62ea1a	562	* @{
NYX	0:85b3fd62ea1a	563	*/
NYX	0:85b3fd62ea1a	564	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
NYX	0:85b3fd62ea1a	565	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
NYX	0:85b3fd62ea1a	566	#define TIM_CLOCKSOURCE_ITR0 0x00000000U
NYX	0:85b3fd62ea1a	567	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
NYX	0:85b3fd62ea1a	568	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
NYX	0:85b3fd62ea1a	569	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
NYX	0:85b3fd62ea1a	570	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
NYX	0:85b3fd62ea1a	571	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
NYX	0:85b3fd62ea1a	572	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
NYX	0:85b3fd62ea1a	573	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
NYX	0:85b3fd62ea1a	574	/**
NYX	0:85b3fd62ea1a	575	* @}
NYX	0:85b3fd62ea1a	576	*/
NYX	0:85b3fd62ea1a	577
NYX	0:85b3fd62ea1a	578	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
NYX	0:85b3fd62ea1a	579	* @{
NYX	0:85b3fd62ea1a	580	*/
NYX	0:85b3fd62ea1a	581	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
NYX	0:85b3fd62ea1a	582	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
NYX	0:85b3fd62ea1a	583	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
NYX	0:85b3fd62ea1a	584	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
NYX	0:85b3fd62ea1a	585	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
NYX	0:85b3fd62ea1a	586	/**
NYX	0:85b3fd62ea1a	587	* @}
NYX	0:85b3fd62ea1a	588	*/
NYX	0:85b3fd62ea1a	589
NYX	0:85b3fd62ea1a	590	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
NYX	0:85b3fd62ea1a	591	* @{
NYX	0:85b3fd62ea1a	592	*/
NYX	0:85b3fd62ea1a	593	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
NYX	0:85b3fd62ea1a	594	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
NYX	0:85b3fd62ea1a	595	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
NYX	0:85b3fd62ea1a	596	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
NYX	0:85b3fd62ea1a	597	/**
NYX	0:85b3fd62ea1a	598	* @}
NYX	0:85b3fd62ea1a	599	*/
NYX	0:85b3fd62ea1a	600
NYX	0:85b3fd62ea1a	601	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
NYX	0:85b3fd62ea1a	602	* @{
NYX	0:85b3fd62ea1a	603	*/
NYX	0:85b3fd62ea1a	604	#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
NYX	0:85b3fd62ea1a	605	#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
NYX	0:85b3fd62ea1a	606	/**
NYX	0:85b3fd62ea1a	607	* @}
NYX	0:85b3fd62ea1a	608	*/
NYX	0:85b3fd62ea1a	609
NYX	0:85b3fd62ea1a	610	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
NYX	0:85b3fd62ea1a	611	* @{
NYX	0:85b3fd62ea1a	612	*/
NYX	0:85b3fd62ea1a	613	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
NYX	0:85b3fd62ea1a	614	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
NYX	0:85b3fd62ea1a	615	/**
NYX	0:85b3fd62ea1a	616	* @}
NYX	0:85b3fd62ea1a	617	*/
NYX	0:85b3fd62ea1a	618
NYX	0:85b3fd62ea1a	619	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
NYX	0:85b3fd62ea1a	620	* @{
NYX	0:85b3fd62ea1a	621	*/
NYX	0:85b3fd62ea1a	622	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
NYX	0:85b3fd62ea1a	623	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
NYX	0:85b3fd62ea1a	624	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
NYX	0:85b3fd62ea1a	625	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
NYX	0:85b3fd62ea1a	626	/**
NYX	0:85b3fd62ea1a	627	* @}
NYX	0:85b3fd62ea1a	628	*/
NYX	0:85b3fd62ea1a	629
NYX	0:85b3fd62ea1a	630	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
NYX	0:85b3fd62ea1a	631	* @{
NYX	0:85b3fd62ea1a	632	*/
NYX	0:85b3fd62ea1a	633	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
NYX	0:85b3fd62ea1a	634	#define TIM_OSSR_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	635	/**
NYX	0:85b3fd62ea1a	636	* @}
NYX	0:85b3fd62ea1a	637	*/
NYX	0:85b3fd62ea1a	638
NYX	0:85b3fd62ea1a	639	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
NYX	0:85b3fd62ea1a	640	* @{
NYX	0:85b3fd62ea1a	641	*/
NYX	0:85b3fd62ea1a	642	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
NYX	0:85b3fd62ea1a	643	#define TIM_OSSI_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	644	/**
NYX	0:85b3fd62ea1a	645	* @}
NYX	0:85b3fd62ea1a	646	*/
NYX	0:85b3fd62ea1a	647
NYX	0:85b3fd62ea1a	648	/** @defgroup TIM_Lock_level TIM Lock level
NYX	0:85b3fd62ea1a	649	* @{
NYX	0:85b3fd62ea1a	650	*/
NYX	0:85b3fd62ea1a	651	#define TIM_LOCKLEVEL_OFF 0x00000000U
NYX	0:85b3fd62ea1a	652	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
NYX	0:85b3fd62ea1a	653	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
NYX	0:85b3fd62ea1a	654	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
NYX	0:85b3fd62ea1a	655	/**
NYX	0:85b3fd62ea1a	656	* @}
NYX	0:85b3fd62ea1a	657	*/
NYX	0:85b3fd62ea1a	658	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
NYX	0:85b3fd62ea1a	659	* @{
NYX	0:85b3fd62ea1a	660	*/
NYX	0:85b3fd62ea1a	661	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
NYX	0:85b3fd62ea1a	662	#define TIM_BREAK_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	663	/**
NYX	0:85b3fd62ea1a	664	* @}
NYX	0:85b3fd62ea1a	665	*/
NYX	0:85b3fd62ea1a	666
NYX	0:85b3fd62ea1a	667	/** @defgroup TIM_Break_Polarity TIM Break Polarity
NYX	0:85b3fd62ea1a	668	* @{
NYX	0:85b3fd62ea1a	669	*/
NYX	0:85b3fd62ea1a	670	#define TIM_BREAKPOLARITY_LOW 0x00000000U
NYX	0:85b3fd62ea1a	671	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
NYX	0:85b3fd62ea1a	672	/**
NYX	0:85b3fd62ea1a	673	* @}
NYX	0:85b3fd62ea1a	674	*/
NYX	0:85b3fd62ea1a	675
NYX	0:85b3fd62ea1a	676	/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
NYX	0:85b3fd62ea1a	677	* @{
NYX	0:85b3fd62ea1a	678	*/
NYX	0:85b3fd62ea1a	679	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
NYX	0:85b3fd62ea1a	680	#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	681	/**
NYX	0:85b3fd62ea1a	682	* @}
NYX	0:85b3fd62ea1a	683	*/
NYX	0:85b3fd62ea1a	684
NYX	0:85b3fd62ea1a	685	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
NYX	0:85b3fd62ea1a	686	* @{
NYX	0:85b3fd62ea1a	687	*/
NYX	0:85b3fd62ea1a	688	#define TIM_TRGO_RESET 0x00000000U
NYX	0:85b3fd62ea1a	689	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
NYX	0:85b3fd62ea1a	690	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
NYX	0:85b3fd62ea1a	691	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
NYX	0:85b3fd62ea1a	692	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
NYX	0:85b3fd62ea1a	693	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
NYX	0:85b3fd62ea1a	694	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
NYX	0:85b3fd62ea1a	695	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
NYX	0:85b3fd62ea1a	696	/**
NYX	0:85b3fd62ea1a	697	* @}
NYX	0:85b3fd62ea1a	698	*/
NYX	0:85b3fd62ea1a	699
NYX	0:85b3fd62ea1a	700	/** @defgroup TIM_Slave_Mode TIM Slave Mode
NYX	0:85b3fd62ea1a	701	* @{
NYX	0:85b3fd62ea1a	702	*/
NYX	0:85b3fd62ea1a	703	#define TIM_SLAVEMODE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	704	#define TIM_SLAVEMODE_RESET 0x00000004U
NYX	0:85b3fd62ea1a	705	#define TIM_SLAVEMODE_GATED 0x00000005U
NYX	0:85b3fd62ea1a	706	#define TIM_SLAVEMODE_TRIGGER 0x00000006U
NYX	0:85b3fd62ea1a	707	#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
NYX	0:85b3fd62ea1a	708	/**
NYX	0:85b3fd62ea1a	709	* @}
NYX	0:85b3fd62ea1a	710	*/
NYX	0:85b3fd62ea1a	711
NYX	0:85b3fd62ea1a	712	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
NYX	0:85b3fd62ea1a	713	* @{
NYX	0:85b3fd62ea1a	714	*/
NYX	0:85b3fd62ea1a	715	#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
NYX	0:85b3fd62ea1a	716	#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	717	/**
NYX	0:85b3fd62ea1a	718	* @}
NYX	0:85b3fd62ea1a	719	*/
NYX	0:85b3fd62ea1a	720
NYX	0:85b3fd62ea1a	721	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
NYX	0:85b3fd62ea1a	722	* @{
NYX	0:85b3fd62ea1a	723	*/
NYX	0:85b3fd62ea1a	724	#define TIM_TS_ITR0 0x00000000U
NYX	0:85b3fd62ea1a	725	#define TIM_TS_ITR1 0x00000010U
NYX	0:85b3fd62ea1a	726	#define TIM_TS_ITR2 0x00000020U
NYX	0:85b3fd62ea1a	727	#define TIM_TS_ITR3 0x00000030U
NYX	0:85b3fd62ea1a	728	#define TIM_TS_TI1F_ED 0x00000040U
NYX	0:85b3fd62ea1a	729	#define TIM_TS_TI1FP1 0x00000050U
NYX	0:85b3fd62ea1a	730	#define TIM_TS_TI2FP2 0x00000060U
NYX	0:85b3fd62ea1a	731	#define TIM_TS_ETRF 0x00000070U
NYX	0:85b3fd62ea1a	732	#define TIM_TS_NONE 0x0000FFFFU
NYX	0:85b3fd62ea1a	733	/**
NYX	0:85b3fd62ea1a	734	* @}
NYX	0:85b3fd62ea1a	735	*/
NYX	0:85b3fd62ea1a	736
NYX	0:85b3fd62ea1a	737	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
NYX	0:85b3fd62ea1a	738	* @{
NYX	0:85b3fd62ea1a	739	*/
NYX	0:85b3fd62ea1a	740	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
NYX	0:85b3fd62ea1a	741	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
NYX	0:85b3fd62ea1a	742	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
NYX	0:85b3fd62ea1a	743	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
NYX	0:85b3fd62ea1a	744	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
NYX	0:85b3fd62ea1a	745	/**
NYX	0:85b3fd62ea1a	746	* @}
NYX	0:85b3fd62ea1a	747	*/
NYX	0:85b3fd62ea1a	748
NYX	0:85b3fd62ea1a	749	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
NYX	0:85b3fd62ea1a	750	* @{
NYX	0:85b3fd62ea1a	751	*/
NYX	0:85b3fd62ea1a	752	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
NYX	0:85b3fd62ea1a	753	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
NYX	0:85b3fd62ea1a	754	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
NYX	0:85b3fd62ea1a	755	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
NYX	0:85b3fd62ea1a	756	/**
NYX	0:85b3fd62ea1a	757	* @}
NYX	0:85b3fd62ea1a	758	*/
NYX	0:85b3fd62ea1a	759
NYX	0:85b3fd62ea1a	760
NYX	0:85b3fd62ea1a	761	/** @defgroup TIM_TI1_Selection TIM TI1 Selection
NYX	0:85b3fd62ea1a	762	* @{
NYX	0:85b3fd62ea1a	763	*/
NYX	0:85b3fd62ea1a	764	#define TIM_TI1SELECTION_CH1 0x00000000U
NYX	0:85b3fd62ea1a	765	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
NYX	0:85b3fd62ea1a	766	/**
NYX	0:85b3fd62ea1a	767	* @}
NYX	0:85b3fd62ea1a	768	*/
NYX	0:85b3fd62ea1a	769
NYX	0:85b3fd62ea1a	770	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
NYX	0:85b3fd62ea1a	771	* @{
NYX	0:85b3fd62ea1a	772	*/
NYX	0:85b3fd62ea1a	773	#define TIM_DMABASE_CR1 0x00000000U
NYX	0:85b3fd62ea1a	774	#define TIM_DMABASE_CR2 0x00000001U
NYX	0:85b3fd62ea1a	775	#define TIM_DMABASE_SMCR 0x00000002U
NYX	0:85b3fd62ea1a	776	#define TIM_DMABASE_DIER 0x00000003U
NYX	0:85b3fd62ea1a	777	#define TIM_DMABASE_SR 0x00000004U
NYX	0:85b3fd62ea1a	778	#define TIM_DMABASE_EGR 0x00000005U
NYX	0:85b3fd62ea1a	779	#define TIM_DMABASE_CCMR1 0x00000006U
NYX	0:85b3fd62ea1a	780	#define TIM_DMABASE_CCMR2 0x00000007U
NYX	0:85b3fd62ea1a	781	#define TIM_DMABASE_CCER 0x00000008U
NYX	0:85b3fd62ea1a	782	#define TIM_DMABASE_CNT 0x00000009U
NYX	0:85b3fd62ea1a	783	#define TIM_DMABASE_PSC 0x0000000AU
NYX	0:85b3fd62ea1a	784	#define TIM_DMABASE_ARR 0x0000000BU
NYX	0:85b3fd62ea1a	785	#define TIM_DMABASE_RCR 0x0000000CU
NYX	0:85b3fd62ea1a	786	#define TIM_DMABASE_CCR1 0x0000000DU
NYX	0:85b3fd62ea1a	787	#define TIM_DMABASE_CCR2 0x0000000EU
NYX	0:85b3fd62ea1a	788	#define TIM_DMABASE_CCR3 0x0000000FU
NYX	0:85b3fd62ea1a	789	#define TIM_DMABASE_CCR4 0x00000010U
NYX	0:85b3fd62ea1a	790	#define TIM_DMABASE_BDTR 0x00000011U
NYX	0:85b3fd62ea1a	791	#define TIM_DMABASE_DCR 0x00000012U
NYX	0:85b3fd62ea1a	792	#define TIM_DMABASE_OR 0x00000013U
NYX	0:85b3fd62ea1a	793	/**
NYX	0:85b3fd62ea1a	794	* @}
NYX	0:85b3fd62ea1a	795	*/
NYX	0:85b3fd62ea1a	796
NYX	0:85b3fd62ea1a	797	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
NYX	0:85b3fd62ea1a	798	* @{
NYX	0:85b3fd62ea1a	799	*/
NYX	0:85b3fd62ea1a	800	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
NYX	0:85b3fd62ea1a	801	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
NYX	0:85b3fd62ea1a	802	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
NYX	0:85b3fd62ea1a	803	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
NYX	0:85b3fd62ea1a	804	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
NYX	0:85b3fd62ea1a	805	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
NYX	0:85b3fd62ea1a	806	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
NYX	0:85b3fd62ea1a	807	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
NYX	0:85b3fd62ea1a	808	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
NYX	0:85b3fd62ea1a	809	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
NYX	0:85b3fd62ea1a	810	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
NYX	0:85b3fd62ea1a	811	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
NYX	0:85b3fd62ea1a	812	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
NYX	0:85b3fd62ea1a	813	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
NYX	0:85b3fd62ea1a	814	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
NYX	0:85b3fd62ea1a	815	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
NYX	0:85b3fd62ea1a	816	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
NYX	0:85b3fd62ea1a	817	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
NYX	0:85b3fd62ea1a	818	/**
NYX	0:85b3fd62ea1a	819	* @}
NYX	0:85b3fd62ea1a	820	*/
NYX	0:85b3fd62ea1a	821
NYX	0:85b3fd62ea1a	822	/** @defgroup DMA_Handle_index DMA Handle index
NYX	0:85b3fd62ea1a	823	* @{
NYX	0:85b3fd62ea1a	824	*/
NYX	0:85b3fd62ea1a	825	#define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /!< Index of the DMA handle used for Update DMA requests /
NYX	0:85b3fd62ea1a	826	#define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
NYX	0:85b3fd62ea1a	827	#define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
NYX	0:85b3fd62ea1a	828	#define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
NYX	0:85b3fd62ea1a	829	#define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
NYX	0:85b3fd62ea1a	830	#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /!< Index of the DMA handle used for Commutation DMA requests /
NYX	0:85b3fd62ea1a	831	#define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /!< Index of the DMA handle used for Trigger DMA requests /
NYX	0:85b3fd62ea1a	832	/**
NYX	0:85b3fd62ea1a	833	* @}
NYX	0:85b3fd62ea1a	834	*/
NYX	0:85b3fd62ea1a	835
NYX	0:85b3fd62ea1a	836	/** @defgroup Channel_CC_State Channel CC State
NYX	0:85b3fd62ea1a	837	* @{
NYX	0:85b3fd62ea1a	838	*/
NYX	0:85b3fd62ea1a	839	#define TIM_CCx_ENABLE 0x00000001U
NYX	0:85b3fd62ea1a	840	#define TIM_CCx_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	841	#define TIM_CCxN_ENABLE 0x00000004U
NYX	0:85b3fd62ea1a	842	#define TIM_CCxN_DISABLE 0x00000000U
NYX	0:85b3fd62ea1a	843	/**
NYX	0:85b3fd62ea1a	844	* @}
NYX	0:85b3fd62ea1a	845	*/
NYX	0:85b3fd62ea1a	846
NYX	0:85b3fd62ea1a	847	/**
NYX	0:85b3fd62ea1a	848	* @}
NYX	0:85b3fd62ea1a	849	*/
NYX	0:85b3fd62ea1a	850
NYX	0:85b3fd62ea1a	851	/* Exported macro ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	852	/** @defgroup TIM_Exported_Macros TIM Exported Macros
NYX	0:85b3fd62ea1a	853	* @{
NYX	0:85b3fd62ea1a	854	*/
NYX	0:85b3fd62ea1a	855	/** @brief Reset TIM handle state
NYX	0:85b3fd62ea1a	856	* @param __HANDLE__: TIM handle
NYX	0:85b3fd62ea1a	857	* @retval None
NYX	0:85b3fd62ea1a	858	*/
NYX	0:85b3fd62ea1a	859	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
NYX	0:85b3fd62ea1a	860
NYX	0:85b3fd62ea1a	861	/**
NYX	0:85b3fd62ea1a	862	* @brief Enable the TIM peripheral.
NYX	0:85b3fd62ea1a	863	* @param __HANDLE__: TIM handle
NYX	0:85b3fd62ea1a	864	* @retval None
NYX	0:85b3fd62ea1a	865	*/
NYX	0:85b3fd62ea1a	866	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
NYX	0:85b3fd62ea1a	867
NYX	0:85b3fd62ea1a	868	/**
NYX	0:85b3fd62ea1a	869	* @brief Enable the TIM main Output.
NYX	0:85b3fd62ea1a	870	* @param __HANDLE__: TIM handle
NYX	0:85b3fd62ea1a	871	* @retval None
NYX	0:85b3fd62ea1a	872	*/
NYX	0:85b3fd62ea1a	873	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
NYX	0:85b3fd62ea1a	874
NYX	0:85b3fd62ea1a	875
NYX	0:85b3fd62ea1a	876	/**
NYX	0:85b3fd62ea1a	877	* @brief Disable the TIM peripheral.
NYX	0:85b3fd62ea1a	878	* @param __HANDLE__: TIM handle
NYX	0:85b3fd62ea1a	879	* @retval None
NYX	0:85b3fd62ea1a	880	*/
NYX	0:85b3fd62ea1a	881	#define __HAL_TIM_DISABLE(__HANDLE__) \
NYX	0:85b3fd62ea1a	882	do { \
NYX	0:85b3fd62ea1a	883	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
NYX	0:85b3fd62ea1a	884	{ \
NYX	0:85b3fd62ea1a	885	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
NYX	0:85b3fd62ea1a	886	{ \
NYX	0:85b3fd62ea1a	887	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
NYX	0:85b3fd62ea1a	888	} \
NYX	0:85b3fd62ea1a	889	} \
NYX	0:85b3fd62ea1a	890	} while(0U)
NYX	0:85b3fd62ea1a	891
NYX	0:85b3fd62ea1a	892	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
NYX	0:85b3fd62ea1a	893	channels have been disabled */
NYX	0:85b3fd62ea1a	894	/**
NYX	0:85b3fd62ea1a	895	* @brief Disable the TIM main Output.
NYX	0:85b3fd62ea1a	896	* @param __HANDLE__: TIM handle
NYX	0:85b3fd62ea1a	897	* @retval None
NYX	0:85b3fd62ea1a	898	*/
NYX	0:85b3fd62ea1a	899	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
NYX	0:85b3fd62ea1a	900	do { \
NYX	0:85b3fd62ea1a	901	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
NYX	0:85b3fd62ea1a	902	{ \
NYX	0:85b3fd62ea1a	903	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
NYX	0:85b3fd62ea1a	904	{ \
NYX	0:85b3fd62ea1a	905	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
NYX	0:85b3fd62ea1a	906	} \
NYX	0:85b3fd62ea1a	907	} \
NYX	0:85b3fd62ea1a	908	} while(0U)
NYX	0:85b3fd62ea1a	909
NYX	0:85b3fd62ea1a	910	/**
NYX	0:85b3fd62ea1a	911	* @brief Disable the TIM main Output.
NYX	0:85b3fd62ea1a	912	* @param __HANDLE__: TIM handle
NYX	0:85b3fd62ea1a	913	* @retval None
NYX	0:85b3fd62ea1a	914	* @note The Main Output Enable of a timer instance is disabled unconditionally
NYX	0:85b3fd62ea1a	915	*/
NYX	0:85b3fd62ea1a	916	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
NYX	0:85b3fd62ea1a	917
NYX	0:85b3fd62ea1a	918	/** @brief Enable the specified TIM interrupt.
NYX	0:85b3fd62ea1a	919	* @param __HANDLE__: specifies the TIM Handle.
NYX	0:85b3fd62ea1a	920	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
NYX	0:85b3fd62ea1a	921	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	922	* @arg TIM_IT_UPDATE: Update interrupt
NYX	0:85b3fd62ea1a	923	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
NYX	0:85b3fd62ea1a	924	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
NYX	0:85b3fd62ea1a	925	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
NYX	0:85b3fd62ea1a	926	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
NYX	0:85b3fd62ea1a	927	* @arg TIM_IT_COM: Commutation interrupt
NYX	0:85b3fd62ea1a	928	* @arg TIM_IT_TRIGGER: Trigger interrupt
NYX	0:85b3fd62ea1a	929	* @arg TIM_IT_BREAK: Break interrupt
NYX	0:85b3fd62ea1a	930	* @retval None
NYX	0:85b3fd62ea1a	931	*/
NYX	0:85b3fd62ea1a	932	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
NYX	0:85b3fd62ea1a	933
NYX	0:85b3fd62ea1a	934
NYX	0:85b3fd62ea1a	935	/** @brief Disable the specified TIM interrupt.
NYX	0:85b3fd62ea1a	936	* @param __HANDLE__: specifies the TIM Handle.
NYX	0:85b3fd62ea1a	937	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
NYX	0:85b3fd62ea1a	938	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	939	* @arg TIM_IT_UPDATE: Update interrupt
NYX	0:85b3fd62ea1a	940	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
NYX	0:85b3fd62ea1a	941	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
NYX	0:85b3fd62ea1a	942	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
NYX	0:85b3fd62ea1a	943	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
NYX	0:85b3fd62ea1a	944	* @arg TIM_IT_COM: Commutation interrupt
NYX	0:85b3fd62ea1a	945	* @arg TIM_IT_TRIGGER: Trigger interrupt
NYX	0:85b3fd62ea1a	946	* @arg TIM_IT_BREAK: Break interrupt
NYX	0:85b3fd62ea1a	947	* @retval None
NYX	0:85b3fd62ea1a	948	*/
NYX	0:85b3fd62ea1a	949	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
NYX	0:85b3fd62ea1a	950
NYX	0:85b3fd62ea1a	951	/** @brief Enable the specified DMA request.
NYX	0:85b3fd62ea1a	952	* @param __HANDLE__: specifies the TIM Handle.
NYX	0:85b3fd62ea1a	953	* @param __DMA__: specifies the TIM DMA request to enable.
NYX	0:85b3fd62ea1a	954	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	955	* @arg TIM_DMA_UPDATE: Update DMA request
NYX	0:85b3fd62ea1a	956	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
NYX	0:85b3fd62ea1a	957	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
NYX	0:85b3fd62ea1a	958	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
NYX	0:85b3fd62ea1a	959	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
NYX	0:85b3fd62ea1a	960	* @arg TIM_DMA_COM: Commutation DMA request
NYX	0:85b3fd62ea1a	961	* @arg TIM_DMA_TRIGGER: Trigger DMA request
NYX	0:85b3fd62ea1a	962	* @retval None
NYX	0:85b3fd62ea1a	963	*/
NYX	0:85b3fd62ea1a	964	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
NYX	0:85b3fd62ea1a	965
NYX	0:85b3fd62ea1a	966	/** @brief Disable the specified DMA request.
NYX	0:85b3fd62ea1a	967	* @param __HANDLE__: specifies the TIM Handle.
NYX	0:85b3fd62ea1a	968	* @param __DMA__: specifies the TIM DMA request to disable.
NYX	0:85b3fd62ea1a	969	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	970	* @arg TIM_DMA_UPDATE: Update DMA request
NYX	0:85b3fd62ea1a	971	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
NYX	0:85b3fd62ea1a	972	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
NYX	0:85b3fd62ea1a	973	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
NYX	0:85b3fd62ea1a	974	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
NYX	0:85b3fd62ea1a	975	* @arg TIM_DMA_COM: Commutation DMA request
NYX	0:85b3fd62ea1a	976	* @arg TIM_DMA_TRIGGER: Trigger DMA request
NYX	0:85b3fd62ea1a	977	* @retval None
NYX	0:85b3fd62ea1a	978	*/
NYX	0:85b3fd62ea1a	979	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
NYX	0:85b3fd62ea1a	980
NYX	0:85b3fd62ea1a	981	/** @brief Check whether the specified TIM interrupt flag is set or not.
NYX	0:85b3fd62ea1a	982	* @param __HANDLE__: specifies the TIM Handle.
NYX	0:85b3fd62ea1a	983	* @param __FLAG__: specifies the TIM interrupt flag to check.
NYX	0:85b3fd62ea1a	984	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	985	* @arg TIM_FLAG_UPDATE: Update interrupt flag
NYX	0:85b3fd62ea1a	986	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
NYX	0:85b3fd62ea1a	987	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
NYX	0:85b3fd62ea1a	988	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
NYX	0:85b3fd62ea1a	989	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
NYX	0:85b3fd62ea1a	990	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
NYX	0:85b3fd62ea1a	991	* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
NYX	0:85b3fd62ea1a	992	* @arg TIM_FLAG_COM: Commutation interrupt flag
NYX	0:85b3fd62ea1a	993	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
NYX	0:85b3fd62ea1a	994	* @arg TIM_FLAG_BREAK: Break interrupt flag
NYX	0:85b3fd62ea1a	995	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
NYX	0:85b3fd62ea1a	996	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
NYX	0:85b3fd62ea1a	997	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
NYX	0:85b3fd62ea1a	998	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
NYX	0:85b3fd62ea1a	999	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
NYX	0:85b3fd62ea1a	1000	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
NYX	0:85b3fd62ea1a	1001	* @retval The new state of __FLAG__ (TRUE or FALSE).
NYX	0:85b3fd62ea1a	1002	*/
NYX	0:85b3fd62ea1a	1003	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
NYX	0:85b3fd62ea1a	1004
NYX	0:85b3fd62ea1a	1005	/** @brief Clear the specified TIM interrupt flag.
NYX	0:85b3fd62ea1a	1006	* @param __HANDLE__: specifies the TIM Handle.
NYX	0:85b3fd62ea1a	1007	* @param __FLAG__: specifies the TIM interrupt flag to clear.
NYX	0:85b3fd62ea1a	1008	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1009	* @arg TIM_FLAG_UPDATE: Update interrupt flag
NYX	0:85b3fd62ea1a	1010	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
NYX	0:85b3fd62ea1a	1011	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
NYX	0:85b3fd62ea1a	1012	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
NYX	0:85b3fd62ea1a	1013	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
NYX	0:85b3fd62ea1a	1014	* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
NYX	0:85b3fd62ea1a	1015	* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
NYX	0:85b3fd62ea1a	1016	* @arg TIM_FLAG_COM: Commutation interrupt flag
NYX	0:85b3fd62ea1a	1017	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
NYX	0:85b3fd62ea1a	1018	* @arg TIM_FLAG_BREAK: Break interrupt flag
NYX	0:85b3fd62ea1a	1019	* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
NYX	0:85b3fd62ea1a	1020	* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
NYX	0:85b3fd62ea1a	1021	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
NYX	0:85b3fd62ea1a	1022	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
NYX	0:85b3fd62ea1a	1023	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
NYX	0:85b3fd62ea1a	1024	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
NYX	0:85b3fd62ea1a	1025	* @retval The new state of __FLAG__ (TRUE or FALSE).
NYX	0:85b3fd62ea1a	1026	*/
NYX	0:85b3fd62ea1a	1027	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
NYX	0:85b3fd62ea1a	1028
NYX	0:85b3fd62ea1a	1029	/**
NYX	0:85b3fd62ea1a	1030	* @brief Check whether the specified TIM interrupt source is enabled or not.
NYX	0:85b3fd62ea1a	1031	* @param __HANDLE__: TIM handle
NYX	0:85b3fd62ea1a	1032	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
NYX	0:85b3fd62ea1a	1033	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1034	* @arg TIM_IT_UPDATE: Update interrupt
NYX	0:85b3fd62ea1a	1035	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
NYX	0:85b3fd62ea1a	1036	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
NYX	0:85b3fd62ea1a	1037	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
NYX	0:85b3fd62ea1a	1038	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
NYX	0:85b3fd62ea1a	1039	* @arg TIM_IT_COM: Commutation interrupt
NYX	0:85b3fd62ea1a	1040	* @arg TIM_IT_TRIGGER: Trigger interrupt
NYX	0:85b3fd62ea1a	1041	* @arg TIM_IT_BREAK: Break interrupt
NYX	0:85b3fd62ea1a	1042	* @retval The state of TIM_IT (SET or RESET).
NYX	0:85b3fd62ea1a	1043	*/
NYX	0:85b3fd62ea1a	1044	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
NYX	0:85b3fd62ea1a	1045
NYX	0:85b3fd62ea1a	1046	/** @brief Clear the TIM interrupt pending bits.
NYX	0:85b3fd62ea1a	1047	* @param __HANDLE__: TIM handle
NYX	0:85b3fd62ea1a	1048	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
NYX	0:85b3fd62ea1a	1049	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1050	* @arg TIM_IT_UPDATE: Update interrupt
NYX	0:85b3fd62ea1a	1051	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
NYX	0:85b3fd62ea1a	1052	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
NYX	0:85b3fd62ea1a	1053	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
NYX	0:85b3fd62ea1a	1054	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
NYX	0:85b3fd62ea1a	1055	* @arg TIM_IT_COM: Commutation interrupt
NYX	0:85b3fd62ea1a	1056	* @arg TIM_IT_TRIGGER: Trigger interrupt
NYX	0:85b3fd62ea1a	1057	* @arg TIM_IT_BREAK: Break interrupt
NYX	0:85b3fd62ea1a	1058	* @retval None
NYX	0:85b3fd62ea1a	1059	*/
NYX	0:85b3fd62ea1a	1060	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
NYX	0:85b3fd62ea1a	1061
NYX	0:85b3fd62ea1a	1062	/**
NYX	0:85b3fd62ea1a	1063	* @brief Indicates whether or not the TIM Counter is used as downcounter.
NYX	0:85b3fd62ea1a	1064	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1065	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
NYX	0:85b3fd62ea1a	1066	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
NYX	0:85b3fd62ea1a	1067	mode.
NYX	0:85b3fd62ea1a	1068	*/
NYX	0:85b3fd62ea1a	1069	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
NYX	0:85b3fd62ea1a	1070
NYX	0:85b3fd62ea1a	1071	/**
NYX	0:85b3fd62ea1a	1072	* @brief Set the TIM Prescaler on runtime.
NYX	0:85b3fd62ea1a	1073	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1074	* @param __PRESC__: specifies the Prescaler new value.
NYX	0:85b3fd62ea1a	1075	* @retval None
NYX	0:85b3fd62ea1a	1076	*/
NYX	0:85b3fd62ea1a	1077	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
NYX	0:85b3fd62ea1a	1078
NYX	0:85b3fd62ea1a	1079	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
NYX	0:85b3fd62ea1a	1080	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
NYX	0:85b3fd62ea1a	1081	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
NYX	0:85b3fd62ea1a	1082	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
NYX	0:85b3fd62ea1a	1083	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
NYX	0:85b3fd62ea1a	1084
NYX	0:85b3fd62ea1a	1085	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
NYX	0:85b3fd62ea1a	1086	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
NYX	0:85b3fd62ea1a	1087	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
NYX	0:85b3fd62ea1a	1088	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
NYX	0:85b3fd62ea1a	1089	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
NYX	0:85b3fd62ea1a	1090
NYX	0:85b3fd62ea1a	1091	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
NYX	0:85b3fd62ea1a	1092	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
NYX	0:85b3fd62ea1a	1093	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
NYX	0:85b3fd62ea1a	1094	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
NYX	0:85b3fd62ea1a	1095	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
NYX	0:85b3fd62ea1a	1096
NYX	0:85b3fd62ea1a	1097	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
NYX	0:85b3fd62ea1a	1098	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
NYX	0:85b3fd62ea1a	1099	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
NYX	0:85b3fd62ea1a	1100	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
NYX	0:85b3fd62ea1a	1101	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
NYX	0:85b3fd62ea1a	1102
NYX	0:85b3fd62ea1a	1103	/**
NYX	0:85b3fd62ea1a	1104	* @brief Sets the TIM Capture Compare Register value on runtime without
NYX	0:85b3fd62ea1a	1105	* calling another time ConfigChannel function.
NYX	0:85b3fd62ea1a	1106	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1107	* @param __CHANNEL__ : TIM Channels to be configured.
NYX	0:85b3fd62ea1a	1108	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1109	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX	0:85b3fd62ea1a	1110	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX	0:85b3fd62ea1a	1111	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX	0:85b3fd62ea1a	1112	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX	0:85b3fd62ea1a	1113	* @param __COMPARE__: specifies the Capture Compare register new value.
NYX	0:85b3fd62ea1a	1114	* @retval None
NYX	0:85b3fd62ea1a	1115	*/
NYX	0:85b3fd62ea1a	1116	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
NYX	0:85b3fd62ea1a	1117	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
NYX	0:85b3fd62ea1a	1118
NYX	0:85b3fd62ea1a	1119	/**
NYX	0:85b3fd62ea1a	1120	* @brief Gets the TIM Capture Compare Register value on runtime.
NYX	0:85b3fd62ea1a	1121	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1122	* @param __CHANNEL__: TIM Channel associated with the capture compare register
NYX	0:85b3fd62ea1a	1123	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1124	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
NYX	0:85b3fd62ea1a	1125	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
NYX	0:85b3fd62ea1a	1126	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
NYX	0:85b3fd62ea1a	1127	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
NYX	0:85b3fd62ea1a	1128	* @arg TIM_CHANNEL_5: get capture/compare 5 register value
NYX	0:85b3fd62ea1a	1129	* @arg TIM_CHANNEL_6: get capture/compare 6 register value
NYX	0:85b3fd62ea1a	1130	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
NYX	0:85b3fd62ea1a	1131	*/
NYX	0:85b3fd62ea1a	1132	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
NYX	0:85b3fd62ea1a	1133	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
NYX	0:85b3fd62ea1a	1134
NYX	0:85b3fd62ea1a	1135	/**
NYX	0:85b3fd62ea1a	1136	* @brief Sets the TIM Counter Register value on runtime.
NYX	0:85b3fd62ea1a	1137	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1138	* @param __COUNTER__: specifies the Counter register new value.
NYX	0:85b3fd62ea1a	1139	* @retval None
NYX	0:85b3fd62ea1a	1140	*/
NYX	0:85b3fd62ea1a	1141	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
NYX	0:85b3fd62ea1a	1142
NYX	0:85b3fd62ea1a	1143	/**
NYX	0:85b3fd62ea1a	1144	* @brief Gets the TIM Counter Register value on runtime.
NYX	0:85b3fd62ea1a	1145	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1146	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
NYX	0:85b3fd62ea1a	1147	*/
NYX	0:85b3fd62ea1a	1148	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
NYX	0:85b3fd62ea1a	1149
NYX	0:85b3fd62ea1a	1150	/**
NYX	0:85b3fd62ea1a	1151	* @brief Sets the TIM Autoreload Register value on runtime without calling
NYX	0:85b3fd62ea1a	1152	* another time any Init function.
NYX	0:85b3fd62ea1a	1153	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1154	* @param __AUTORELOAD__: specifies the Counter register new value.
NYX	0:85b3fd62ea1a	1155	* @retval None
NYX	0:85b3fd62ea1a	1156	*/
NYX	0:85b3fd62ea1a	1157	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
NYX	0:85b3fd62ea1a	1158	do{ \
NYX	0:85b3fd62ea1a	1159	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
NYX	0:85b3fd62ea1a	1160	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
NYX	0:85b3fd62ea1a	1161	} while(0U)
NYX	0:85b3fd62ea1a	1162	/**
NYX	0:85b3fd62ea1a	1163	* @brief Gets the TIM Autoreload Register value on runtime.
NYX	0:85b3fd62ea1a	1164	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1165	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
NYX	0:85b3fd62ea1a	1166	*/
NYX	0:85b3fd62ea1a	1167	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
NYX	0:85b3fd62ea1a	1168
NYX	0:85b3fd62ea1a	1169	/**
NYX	0:85b3fd62ea1a	1170	* @brief Sets the TIM Clock Division value on runtime without calling another time any Init function.
NYX	0:85b3fd62ea1a	1171	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1172	* @param __CKD__: specifies the clock division value.
NYX	0:85b3fd62ea1a	1173	* This parameter can be one of the following value:
NYX	0:85b3fd62ea1a	1174	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
NYX	0:85b3fd62ea1a	1175	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
NYX	0:85b3fd62ea1a	1176	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
NYX	0:85b3fd62ea1a	1177	* @retval None
NYX	0:85b3fd62ea1a	1178	*/
NYX	0:85b3fd62ea1a	1179	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
NYX	0:85b3fd62ea1a	1180	do{ \
NYX	0:85b3fd62ea1a	1181	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
NYX	0:85b3fd62ea1a	1182	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
NYX	0:85b3fd62ea1a	1183	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
NYX	0:85b3fd62ea1a	1184	} while(0U)
NYX	0:85b3fd62ea1a	1185	/**
NYX	0:85b3fd62ea1a	1186	* @brief Gets the TIM Clock Division value on runtime.
NYX	0:85b3fd62ea1a	1187	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1188	* @retval The clock division can be one of the following values:
NYX	0:85b3fd62ea1a	1189	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
NYX	0:85b3fd62ea1a	1190	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
NYX	0:85b3fd62ea1a	1191	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
NYX	0:85b3fd62ea1a	1192	*/
NYX	0:85b3fd62ea1a	1193	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
NYX	0:85b3fd62ea1a	1194
NYX	0:85b3fd62ea1a	1195	/**
NYX	0:85b3fd62ea1a	1196	* @brief Sets the TIM Input Capture prescaler on runtime without calling
NYX	0:85b3fd62ea1a	1197	* another time HAL_TIM_IC_ConfigChannel() function.
NYX	0:85b3fd62ea1a	1198	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1199	* @param __CHANNEL__ : TIM Channels to be configured.
NYX	0:85b3fd62ea1a	1200	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1201	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX	0:85b3fd62ea1a	1202	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX	0:85b3fd62ea1a	1203	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX	0:85b3fd62ea1a	1204	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX	0:85b3fd62ea1a	1205	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
NYX	0:85b3fd62ea1a	1206	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1207	* @arg TIM_ICPSC_DIV1: no prescaler
NYX	0:85b3fd62ea1a	1208	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
NYX	0:85b3fd62ea1a	1209	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
NYX	0:85b3fd62ea1a	1210	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
NYX	0:85b3fd62ea1a	1211	* @retval None
NYX	0:85b3fd62ea1a	1212	*/
NYX	0:85b3fd62ea1a	1213	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
NYX	0:85b3fd62ea1a	1214	do{ \
NYX	0:85b3fd62ea1a	1215	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
NYX	0:85b3fd62ea1a	1216	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
NYX	0:85b3fd62ea1a	1217	} while(0U)
NYX	0:85b3fd62ea1a	1218
NYX	0:85b3fd62ea1a	1219	/**
NYX	0:85b3fd62ea1a	1220	* @brief Get the TIM Input Capture prescaler on runtime.
NYX	0:85b3fd62ea1a	1221	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1222	* @param __CHANNEL__: TIM Channels to be configured.
NYX	0:85b3fd62ea1a	1223	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1224	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
NYX	0:85b3fd62ea1a	1225	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
NYX	0:85b3fd62ea1a	1226	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
NYX	0:85b3fd62ea1a	1227	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
NYX	0:85b3fd62ea1a	1228	* @retval The input capture prescaler can be one of the following values:
NYX	0:85b3fd62ea1a	1229	* @arg TIM_ICPSC_DIV1: no prescaler
NYX	0:85b3fd62ea1a	1230	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
NYX	0:85b3fd62ea1a	1231	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
NYX	0:85b3fd62ea1a	1232	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
NYX	0:85b3fd62ea1a	1233	*/
NYX	0:85b3fd62ea1a	1234	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
NYX	0:85b3fd62ea1a	1235	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
NYX	0:85b3fd62ea1a	1236	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
NYX	0:85b3fd62ea1a	1237	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
NYX	0:85b3fd62ea1a	1238	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
NYX	0:85b3fd62ea1a	1239
NYX	0:85b3fd62ea1a	1240	/**
NYX	0:85b3fd62ea1a	1241	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
NYX	0:85b3fd62ea1a	1242	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1243	* @note When the USR bit of the TIMx_CR1 register is set, only counter
NYX	0:85b3fd62ea1a	1244	* overflow/underflow generates an update interrupt or DMA request (if
NYX	0:85b3fd62ea1a	1245	* enabled)
NYX	0:85b3fd62ea1a	1246	* @retval None
NYX	0:85b3fd62ea1a	1247	*/
NYX	0:85b3fd62ea1a	1248	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
NYX	0:85b3fd62ea1a	1249	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
NYX	0:85b3fd62ea1a	1250
NYX	0:85b3fd62ea1a	1251	/**
NYX	0:85b3fd62ea1a	1252	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
NYX	0:85b3fd62ea1a	1253	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1254	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
NYX	0:85b3fd62ea1a	1255	* following events generate an update interrupt or DMA request (if
NYX	0:85b3fd62ea1a	1256	* enabled):
NYX	0:85b3fd62ea1a	1257	* _ Counter overflow/underflow
NYX	0:85b3fd62ea1a	1258	* _ Setting the UG bit
NYX	0:85b3fd62ea1a	1259	* _ Update generation through the slave mode controller
NYX	0:85b3fd62ea1a	1260	* @retval None
NYX	0:85b3fd62ea1a	1261	*/
NYX	0:85b3fd62ea1a	1262	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
NYX	0:85b3fd62ea1a	1263	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
NYX	0:85b3fd62ea1a	1264
NYX	0:85b3fd62ea1a	1265	/**
NYX	0:85b3fd62ea1a	1266	* @brief Sets the TIM Capture x input polarity on runtime.
NYX	0:85b3fd62ea1a	1267	* @param __HANDLE__: TIM handle.
NYX	0:85b3fd62ea1a	1268	* @param __CHANNEL__: TIM Channels to be configured.
NYX	0:85b3fd62ea1a	1269	* This parameter can be one of the following values:
NYX	0:85b3fd62ea1a	1270	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX	0:85b3fd62ea1a	1271	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX	0:85b3fd62ea1a	1272	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX	0:85b3fd62ea1a	1273	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX	0:85b3fd62ea1a	1274	* @param __POLARITY__: Polarity for TIx source
NYX	0:85b3fd62ea1a	1275	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
NYX	0:85b3fd62ea1a	1276	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
NYX	0:85b3fd62ea1a	1277	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
NYX	0:85b3fd62ea1a	1278	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
NYX	0:85b3fd62ea1a	1279	* @retval None
NYX	0:85b3fd62ea1a	1280	*/
NYX	0:85b3fd62ea1a	1281	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
NYX	0:85b3fd62ea1a	1282	do{ \
NYX	0:85b3fd62ea1a	1283	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
NYX	0:85b3fd62ea1a	1284	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
NYX	0:85b3fd62ea1a	1285	}while(0U)
NYX	0:85b3fd62ea1a	1286	/**
NYX	0:85b3fd62ea1a	1287	* @}
NYX	0:85b3fd62ea1a	1288	*/
NYX	0:85b3fd62ea1a	1289
NYX	0:85b3fd62ea1a	1290	/* Include TIM HAL Extension module */
NYX	0:85b3fd62ea1a	1291	#include "stm32f4xx_hal_tim_ex.h"
NYX	0:85b3fd62ea1a	1292
NYX	0:85b3fd62ea1a	1293	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1294	/** @addtogroup TIM_Exported_Functions
NYX	0:85b3fd62ea1a	1295	* @{
NYX	0:85b3fd62ea1a	1296	*/
NYX	0:85b3fd62ea1a	1297
NYX	0:85b3fd62ea1a	1298	/** @addtogroup TIM_Exported_Functions_Group1
NYX	0:85b3fd62ea1a	1299	* @{
NYX	0:85b3fd62ea1a	1300	*/
NYX	0:85b3fd62ea1a	1301
NYX	0:85b3fd62ea1a	1302	/* Time Base functions ********************************************************/
NYX	0:85b3fd62ea1a	1303	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1304	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1305	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1306	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1307	/* Blocking mode: Polling */
NYX	0:85b3fd62ea1a	1308	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1309	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1310	/* Non-Blocking mode: Interrupt */
NYX	0:85b3fd62ea1a	1311	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1312	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1313	/* Non-Blocking mode: DMA */
NYX	0:85b3fd62ea1a	1314	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
NYX	0:85b3fd62ea1a	1315	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1316	/**
NYX	0:85b3fd62ea1a	1317	* @}
NYX	0:85b3fd62ea1a	1318	*/
NYX	0:85b3fd62ea1a	1319
NYX	0:85b3fd62ea1a	1320	/** @addtogroup TIM_Exported_Functions_Group2
NYX	0:85b3fd62ea1a	1321	* @{
NYX	0:85b3fd62ea1a	1322	*/
NYX	0:85b3fd62ea1a	1323	/* Timer Output Compare functions **********************************************/
NYX	0:85b3fd62ea1a	1324	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1325	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1326	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1327	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1328	/* Blocking mode: Polling */
NYX	0:85b3fd62ea1a	1329	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1330	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1331	/* Non-Blocking mode: Interrupt */
NYX	0:85b3fd62ea1a	1332	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1333	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1334	/* Non-Blocking mode: DMA */
NYX	0:85b3fd62ea1a	1335	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
NYX	0:85b3fd62ea1a	1336	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1337
NYX	0:85b3fd62ea1a	1338	/**
NYX	0:85b3fd62ea1a	1339	* @}
NYX	0:85b3fd62ea1a	1340	*/
NYX	0:85b3fd62ea1a	1341
NYX	0:85b3fd62ea1a	1342	/** @addtogroup TIM_Exported_Functions_Group3
NYX	0:85b3fd62ea1a	1343	* @{
NYX	0:85b3fd62ea1a	1344	*/
NYX	0:85b3fd62ea1a	1345	/* Timer PWM functions *********************************************************/
NYX	0:85b3fd62ea1a	1346	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1347	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1348	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1349	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1350	/* Blocking mode: Polling */
NYX	0:85b3fd62ea1a	1351	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1352	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1353	/* Non-Blocking mode: Interrupt */
NYX	0:85b3fd62ea1a	1354	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1355	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1356	/* Non-Blocking mode: DMA */
NYX	0:85b3fd62ea1a	1357	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
NYX	0:85b3fd62ea1a	1358	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1359
NYX	0:85b3fd62ea1a	1360	/**
NYX	0:85b3fd62ea1a	1361	* @}
NYX	0:85b3fd62ea1a	1362	*/
NYX	0:85b3fd62ea1a	1363
NYX	0:85b3fd62ea1a	1364	/** @addtogroup TIM_Exported_Functions_Group4
NYX	0:85b3fd62ea1a	1365	* @{
NYX	0:85b3fd62ea1a	1366	*/
NYX	0:85b3fd62ea1a	1367	/* Timer Input Capture functions ***********************************************/
NYX	0:85b3fd62ea1a	1368	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1369	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1370	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1371	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1372	/* Blocking mode: Polling */
NYX	0:85b3fd62ea1a	1373	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1374	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1375	/* Non-Blocking mode: Interrupt */
NYX	0:85b3fd62ea1a	1376	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1377	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1378	/* Non-Blocking mode: DMA */
NYX	0:85b3fd62ea1a	1379	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
NYX	0:85b3fd62ea1a	1380	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1381
NYX	0:85b3fd62ea1a	1382	/**
NYX	0:85b3fd62ea1a	1383	* @}
NYX	0:85b3fd62ea1a	1384	*/
NYX	0:85b3fd62ea1a	1385
NYX	0:85b3fd62ea1a	1386	/** @addtogroup TIM_Exported_Functions_Group5
NYX	0:85b3fd62ea1a	1387	* @{
NYX	0:85b3fd62ea1a	1388	*/
NYX	0:85b3fd62ea1a	1389	/* Timer One Pulse functions ***************************************************/
NYX	0:85b3fd62ea1a	1390	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
NYX	0:85b3fd62ea1a	1391	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1392	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1393	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1394	/* Blocking mode: Polling */
NYX	0:85b3fd62ea1a	1395	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
NYX	0:85b3fd62ea1a	1396	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
NYX	0:85b3fd62ea1a	1397
NYX	0:85b3fd62ea1a	1398	/* Non-Blocking mode: Interrupt */
NYX	0:85b3fd62ea1a	1399	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
NYX	0:85b3fd62ea1a	1400	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
NYX	0:85b3fd62ea1a	1401
NYX	0:85b3fd62ea1a	1402	/**
NYX	0:85b3fd62ea1a	1403	* @}
NYX	0:85b3fd62ea1a	1404	*/
NYX	0:85b3fd62ea1a	1405
NYX	0:85b3fd62ea1a	1406	/** @addtogroup TIM_Exported_Functions_Group6
NYX	0:85b3fd62ea1a	1407	* @{
NYX	0:85b3fd62ea1a	1408	*/
NYX	0:85b3fd62ea1a	1409	/* Timer Encoder functions *****************************************************/
NYX	0:85b3fd62ea1a	1410	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
NYX	0:85b3fd62ea1a	1411	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1412	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1413	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1414	/* Blocking mode: Polling */
NYX	0:85b3fd62ea1a	1415	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1416	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1417	/* Non-Blocking mode: Interrupt */
NYX	0:85b3fd62ea1a	1418	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1419	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1420	/* Non-Blocking mode: DMA */
NYX	0:85b3fd62ea1a	1421	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
NYX	0:85b3fd62ea1a	1422	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1423
NYX	0:85b3fd62ea1a	1424	/**
NYX	0:85b3fd62ea1a	1425	* @}
NYX	0:85b3fd62ea1a	1426	*/
NYX	0:85b3fd62ea1a	1427
NYX	0:85b3fd62ea1a	1428	/** @addtogroup TIM_Exported_Functions_Group7
NYX	0:85b3fd62ea1a	1429	* @{
NYX	0:85b3fd62ea1a	1430	*/
NYX	0:85b3fd62ea1a	1431	/* Interrupt Handler functions **********************************************/
NYX	0:85b3fd62ea1a	1432	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1433
NYX	0:85b3fd62ea1a	1434	/**
NYX	0:85b3fd62ea1a	1435	* @}
NYX	0:85b3fd62ea1a	1436	*/
NYX	0:85b3fd62ea1a	1437
NYX	0:85b3fd62ea1a	1438	/** @addtogroup TIM_Exported_Functions_Group8
NYX	0:85b3fd62ea1a	1439	* @{
NYX	0:85b3fd62ea1a	1440	*/
NYX	0:85b3fd62ea1a	1441	/* Control functions *********************************************************/
NYX	0:85b3fd62ea1a	1442	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
NYX	0:85b3fd62ea1a	1443	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
NYX	0:85b3fd62ea1a	1444	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
NYX	0:85b3fd62ea1a	1445	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
NYX	0:85b3fd62ea1a	1446	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
NYX	0:85b3fd62ea1a	1447	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
NYX	0:85b3fd62ea1a	1448	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
NYX	0:85b3fd62ea1a	1449	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
NYX	0:85b3fd62ea1a	1450	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
NYX	0:85b3fd62ea1a	1451	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
NYX	0:85b3fd62ea1a	1452	uint32_t *BurstBuffer, uint32_t BurstLength);
NYX	0:85b3fd62ea1a	1453	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
NYX	0:85b3fd62ea1a	1454	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
NYX	0:85b3fd62ea1a	1455	uint32_t *BurstBuffer, uint32_t BurstLength);
NYX	0:85b3fd62ea1a	1456	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
NYX	0:85b3fd62ea1a	1457	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
NYX	0:85b3fd62ea1a	1458	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
NYX	0:85b3fd62ea1a	1459
NYX	0:85b3fd62ea1a	1460	/**
NYX	0:85b3fd62ea1a	1461	* @}
NYX	0:85b3fd62ea1a	1462	*/
NYX	0:85b3fd62ea1a	1463
NYX	0:85b3fd62ea1a	1464	/** @addtogroup TIM_Exported_Functions_Group9
NYX	0:85b3fd62ea1a	1465	* @{
NYX	0:85b3fd62ea1a	1466	*/
NYX	0:85b3fd62ea1a	1467	/* Callback in non blocking modes (Interrupt and DMA) *************************/
NYX	0:85b3fd62ea1a	1468	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1469	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1470	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1471	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1472	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1473	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1474
NYX	0:85b3fd62ea1a	1475	/**
NYX	0:85b3fd62ea1a	1476	* @}
NYX	0:85b3fd62ea1a	1477	*/
NYX	0:85b3fd62ea1a	1478
NYX	0:85b3fd62ea1a	1479	/** @addtogroup TIM_Exported_Functions_Group10
NYX	0:85b3fd62ea1a	1480	* @{
NYX	0:85b3fd62ea1a	1481	*/
NYX	0:85b3fd62ea1a	1482	/* Peripheral State functions **************************************************/
NYX	0:85b3fd62ea1a	1483	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1484	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1485	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1486	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1487	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1488	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
NYX	0:85b3fd62ea1a	1489
NYX	0:85b3fd62ea1a	1490	/**
NYX	0:85b3fd62ea1a	1491	* @}
NYX	0:85b3fd62ea1a	1492	*/
NYX	0:85b3fd62ea1a	1493
NYX	0:85b3fd62ea1a	1494	/**
NYX	0:85b3fd62ea1a	1495	* @}
NYX	0:85b3fd62ea1a	1496	*/
NYX	0:85b3fd62ea1a	1497
NYX	0:85b3fd62ea1a	1498	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1499	/** @defgroup TIM_Private_Macros TIM Private Macros
NYX	0:85b3fd62ea1a	1500	* @{
NYX	0:85b3fd62ea1a	1501	*/
NYX	0:85b3fd62ea1a	1502
NYX	0:85b3fd62ea1a	1503	/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
NYX	0:85b3fd62ea1a	1504	* @{
NYX	0:85b3fd62ea1a	1505	*/
NYX	0:85b3fd62ea1a	1506	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
NYX	0:85b3fd62ea1a	1507	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
NYX	0:85b3fd62ea1a	1508	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
NYX	0:85b3fd62ea1a	1509	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
NYX	0:85b3fd62ea1a	1510	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
NYX	0:85b3fd62ea1a	1511
NYX	0:85b3fd62ea1a	1512	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
NYX	0:85b3fd62ea1a	1513	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
NYX	0:85b3fd62ea1a	1514	((DIV) == TIM_CLOCKDIVISION_DIV4))
NYX	0:85b3fd62ea1a	1515
NYX	0:85b3fd62ea1a	1516	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
NYX	0:85b3fd62ea1a	1517	((MODE) == TIM_OCMODE_PWM2))
NYX	0:85b3fd62ea1a	1518
NYX	0:85b3fd62ea1a	1519	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
NYX	0:85b3fd62ea1a	1520	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
NYX	0:85b3fd62ea1a	1521	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
NYX	0:85b3fd62ea1a	1522	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
NYX	0:85b3fd62ea1a	1523	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
NYX	0:85b3fd62ea1a	1524	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
NYX	0:85b3fd62ea1a	1525
NYX	0:85b3fd62ea1a	1526	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1527	((STATE) == TIM_OCFAST_ENABLE))
NYX	0:85b3fd62ea1a	1528
NYX	0:85b3fd62ea1a	1529	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
NYX	0:85b3fd62ea1a	1530	((POLARITY) == TIM_OCPOLARITY_LOW))
NYX	0:85b3fd62ea1a	1531
NYX	0:85b3fd62ea1a	1532	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
NYX	0:85b3fd62ea1a	1533	((POLARITY) == TIM_OCNPOLARITY_LOW))
NYX	0:85b3fd62ea1a	1534
NYX	0:85b3fd62ea1a	1535	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
NYX	0:85b3fd62ea1a	1536	((STATE) == TIM_OCIDLESTATE_RESET))
NYX	0:85b3fd62ea1a	1537
NYX	0:85b3fd62ea1a	1538	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
NYX	0:85b3fd62ea1a	1539	((STATE) == TIM_OCNIDLESTATE_RESET))
NYX	0:85b3fd62ea1a	1540
NYX	0:85b3fd62ea1a	1541	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
NYX	0:85b3fd62ea1a	1542	((CHANNEL) == TIM_CHANNEL_2) \|\| \
NYX	0:85b3fd62ea1a	1543	((CHANNEL) == TIM_CHANNEL_3) \|\| \
NYX	0:85b3fd62ea1a	1544	((CHANNEL) == TIM_CHANNEL_4) \|\| \
NYX	0:85b3fd62ea1a	1545	((CHANNEL) == TIM_CHANNEL_ALL))
NYX	0:85b3fd62ea1a	1546
NYX	0:85b3fd62ea1a	1547	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
NYX	0:85b3fd62ea1a	1548	((CHANNEL) == TIM_CHANNEL_2))
NYX	0:85b3fd62ea1a	1549
NYX	0:85b3fd62ea1a	1550	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
NYX	0:85b3fd62ea1a	1551	((CHANNEL) == TIM_CHANNEL_2) \|\| \
NYX	0:85b3fd62ea1a	1552	((CHANNEL) == TIM_CHANNEL_3))
NYX	0:85b3fd62ea1a	1553
NYX	0:85b3fd62ea1a	1554	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
NYX	0:85b3fd62ea1a	1555	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
NYX	0:85b3fd62ea1a	1556	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
NYX	0:85b3fd62ea1a	1557
NYX	0:85b3fd62ea1a	1558	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
NYX	0:85b3fd62ea1a	1559	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
NYX	0:85b3fd62ea1a	1560	((SELECTION) == TIM_ICSELECTION_TRC))
NYX	0:85b3fd62ea1a	1561
NYX	0:85b3fd62ea1a	1562	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
NYX	0:85b3fd62ea1a	1563	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
NYX	0:85b3fd62ea1a	1564	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
NYX	0:85b3fd62ea1a	1565	((PRESCALER) == TIM_ICPSC_DIV8))
NYX	0:85b3fd62ea1a	1566
NYX	0:85b3fd62ea1a	1567	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
NYX	0:85b3fd62ea1a	1568	((MODE) == TIM_OPMODE_REPETITIVE))
NYX	0:85b3fd62ea1a	1569
NYX	0:85b3fd62ea1a	1570	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
NYX	0:85b3fd62ea1a	1571
NYX	0:85b3fd62ea1a	1572	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
NYX	0:85b3fd62ea1a	1573	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
NYX	0:85b3fd62ea1a	1574	((MODE) == TIM_ENCODERMODE_TI12))
NYX	0:85b3fd62ea1a	1575
NYX	0:85b3fd62ea1a	1576	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
NYX	0:85b3fd62ea1a	1577
NYX	0:85b3fd62ea1a	1578	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
NYX	0:85b3fd62ea1a	1579	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
NYX	0:85b3fd62ea1a	1580	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
NYX	0:85b3fd62ea1a	1581	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
NYX	0:85b3fd62ea1a	1582	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
NYX	0:85b3fd62ea1a	1583	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
NYX	0:85b3fd62ea1a	1584	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
NYX	0:85b3fd62ea1a	1585	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
NYX	0:85b3fd62ea1a	1586	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
NYX	0:85b3fd62ea1a	1587	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
NYX	0:85b3fd62ea1a	1588
NYX	0:85b3fd62ea1a	1589	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
NYX	0:85b3fd62ea1a	1590	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
NYX	0:85b3fd62ea1a	1591	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
NYX	0:85b3fd62ea1a	1592	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
NYX	0:85b3fd62ea1a	1593	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
NYX	0:85b3fd62ea1a	1594
NYX	0:85b3fd62ea1a	1595	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
NYX	0:85b3fd62ea1a	1596	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
NYX	0:85b3fd62ea1a	1597	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
NYX	0:85b3fd62ea1a	1598	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
NYX	0:85b3fd62ea1a	1599
NYX	0:85b3fd62ea1a	1600	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
NYX	0:85b3fd62ea1a	1601
NYX	0:85b3fd62ea1a	1602	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
NYX	0:85b3fd62ea1a	1603	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
NYX	0:85b3fd62ea1a	1604
NYX	0:85b3fd62ea1a	1605	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
NYX	0:85b3fd62ea1a	1606	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
NYX	0:85b3fd62ea1a	1607
NYX	0:85b3fd62ea1a	1608	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
NYX	0:85b3fd62ea1a	1609	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
NYX	0:85b3fd62ea1a	1610	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
NYX	0:85b3fd62ea1a	1611	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
NYX	0:85b3fd62ea1a	1612
NYX	0:85b3fd62ea1a	1613	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
NYX	0:85b3fd62ea1a	1614
NYX	0:85b3fd62ea1a	1615	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	1616	((STATE) == TIM_OSSR_DISABLE))
NYX	0:85b3fd62ea1a	1617
NYX	0:85b3fd62ea1a	1618	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	1619	((STATE) == TIM_OSSI_DISABLE))
NYX	0:85b3fd62ea1a	1620
NYX	0:85b3fd62ea1a	1621	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
NYX	0:85b3fd62ea1a	1622	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
NYX	0:85b3fd62ea1a	1623	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
NYX	0:85b3fd62ea1a	1624	((LEVEL) == TIM_LOCKLEVEL_3))
NYX	0:85b3fd62ea1a	1625
NYX	0:85b3fd62ea1a	1626	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	1627	((STATE) == TIM_BREAK_DISABLE))
NYX	0:85b3fd62ea1a	1628
NYX	0:85b3fd62ea1a	1629	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
NYX	0:85b3fd62ea1a	1630	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
NYX	0:85b3fd62ea1a	1631
NYX	0:85b3fd62ea1a	1632	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	1633	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
NYX	0:85b3fd62ea1a	1634
NYX	0:85b3fd62ea1a	1635	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
NYX	0:85b3fd62ea1a	1636	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	1637	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
NYX	0:85b3fd62ea1a	1638	((SOURCE) == TIM_TRGO_OC1) \|\| \
NYX	0:85b3fd62ea1a	1639	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
NYX	0:85b3fd62ea1a	1640	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
NYX	0:85b3fd62ea1a	1641	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
NYX	0:85b3fd62ea1a	1642	((SOURCE) == TIM_TRGO_OC4REF))
NYX	0:85b3fd62ea1a	1643
NYX	0:85b3fd62ea1a	1644	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
NYX	0:85b3fd62ea1a	1645	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
NYX	0:85b3fd62ea1a	1646	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
NYX	0:85b3fd62ea1a	1647	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
NYX	0:85b3fd62ea1a	1648	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
NYX	0:85b3fd62ea1a	1649
NYX	0:85b3fd62ea1a	1650	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
NYX	0:85b3fd62ea1a	1651	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
NYX	0:85b3fd62ea1a	1652
NYX	0:85b3fd62ea1a	1653	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
NYX	0:85b3fd62ea1a	1654	((SELECTION) == TIM_TS_ITR1) \|\| \
NYX	0:85b3fd62ea1a	1655	((SELECTION) == TIM_TS_ITR2) \|\| \
NYX	0:85b3fd62ea1a	1656	((SELECTION) == TIM_TS_ITR3) \|\| \
NYX	0:85b3fd62ea1a	1657	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
NYX	0:85b3fd62ea1a	1658	((SELECTION) == TIM_TS_TI1FP1) \|\| \
NYX	0:85b3fd62ea1a	1659	((SELECTION) == TIM_TS_TI2FP2) \|\| \
NYX	0:85b3fd62ea1a	1660	((SELECTION) == TIM_TS_ETRF))
NYX	0:85b3fd62ea1a	1661
NYX	0:85b3fd62ea1a	1662	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
NYX	0:85b3fd62ea1a	1663	((SELECTION) == TIM_TS_ITR1) \|\| \
NYX	0:85b3fd62ea1a	1664	((SELECTION) == TIM_TS_ITR2) \|\| \
NYX	0:85b3fd62ea1a	1665	((SELECTION) == TIM_TS_ITR3) \|\| \
NYX	0:85b3fd62ea1a	1666	((SELECTION) == TIM_TS_NONE))
NYX	0:85b3fd62ea1a	1667
NYX	0:85b3fd62ea1a	1668	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
NYX	0:85b3fd62ea1a	1669	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
NYX	0:85b3fd62ea1a	1670	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
NYX	0:85b3fd62ea1a	1671	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
NYX	0:85b3fd62ea1a	1672	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
NYX	0:85b3fd62ea1a	1673
NYX	0:85b3fd62ea1a	1674	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
NYX	0:85b3fd62ea1a	1675	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
NYX	0:85b3fd62ea1a	1676	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
NYX	0:85b3fd62ea1a	1677	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
NYX	0:85b3fd62ea1a	1678
NYX	0:85b3fd62ea1a	1679	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
NYX	0:85b3fd62ea1a	1680
NYX	0:85b3fd62ea1a	1681	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
NYX	0:85b3fd62ea1a	1682	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
NYX	0:85b3fd62ea1a	1683
NYX	0:85b3fd62ea1a	1684	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
NYX	0:85b3fd62ea1a	1685	((BASE) == TIM_DMABASE_CR2) \|\| \
NYX	0:85b3fd62ea1a	1686	((BASE) == TIM_DMABASE_SMCR) \|\| \
NYX	0:85b3fd62ea1a	1687	((BASE) == TIM_DMABASE_DIER) \|\| \
NYX	0:85b3fd62ea1a	1688	((BASE) == TIM_DMABASE_SR) \|\| \
NYX	0:85b3fd62ea1a	1689	((BASE) == TIM_DMABASE_EGR) \|\| \
NYX	0:85b3fd62ea1a	1690	((BASE) == TIM_DMABASE_CCMR1) \|\| \
NYX	0:85b3fd62ea1a	1691	((BASE) == TIM_DMABASE_CCMR2) \|\| \
NYX	0:85b3fd62ea1a	1692	((BASE) == TIM_DMABASE_CCER) \|\| \
NYX	0:85b3fd62ea1a	1693	((BASE) == TIM_DMABASE_CNT) \|\| \
NYX	0:85b3fd62ea1a	1694	((BASE) == TIM_DMABASE_PSC) \|\| \
NYX	0:85b3fd62ea1a	1695	((BASE) == TIM_DMABASE_ARR) \|\| \
NYX	0:85b3fd62ea1a	1696	((BASE) == TIM_DMABASE_RCR) \|\| \
NYX	0:85b3fd62ea1a	1697	((BASE) == TIM_DMABASE_CCR1) \|\| \
NYX	0:85b3fd62ea1a	1698	((BASE) == TIM_DMABASE_CCR2) \|\| \
NYX	0:85b3fd62ea1a	1699	((BASE) == TIM_DMABASE_CCR3) \|\| \
NYX	0:85b3fd62ea1a	1700	((BASE) == TIM_DMABASE_CCR4) \|\| \
NYX	0:85b3fd62ea1a	1701	((BASE) == TIM_DMABASE_BDTR) \|\| \
NYX	0:85b3fd62ea1a	1702	((BASE) == TIM_DMABASE_DCR) \|\| \
NYX	0:85b3fd62ea1a	1703	((BASE) == TIM_DMABASE_OR))
NYX	0:85b3fd62ea1a	1704
NYX	0:85b3fd62ea1a	1705	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
NYX	0:85b3fd62ea1a	1706	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1707	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1708	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1709	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1710	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1711	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1712	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1713	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1714	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1715	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1716	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1717	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1718	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1719	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1720	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1721	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
NYX	0:85b3fd62ea1a	1722	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
NYX	0:85b3fd62ea1a	1723
NYX	0:85b3fd62ea1a	1724	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
NYX	0:85b3fd62ea1a	1725	/**
NYX	0:85b3fd62ea1a	1726	* @}
NYX	0:85b3fd62ea1a	1727	*/
NYX	0:85b3fd62ea1a	1728
NYX	0:85b3fd62ea1a	1729	/** @defgroup TIM_Mask_Definitions TIM Mask Definition
NYX	0:85b3fd62ea1a	1730	* @{
NYX	0:85b3fd62ea1a	1731	*/
NYX	0:85b3fd62ea1a	1732	/* The counter of a timer instance is disabled only if all the CCx and CCxN
NYX	0:85b3fd62ea1a	1733	channels have been disabled */
NYX	0:85b3fd62ea1a	1734	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
NYX	0:85b3fd62ea1a	1735	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
NYX	0:85b3fd62ea1a	1736	/**
NYX	0:85b3fd62ea1a	1737	* @}
NYX	0:85b3fd62ea1a	1738	*/
NYX	0:85b3fd62ea1a	1739
NYX	0:85b3fd62ea1a	1740	/**
NYX	0:85b3fd62ea1a	1741	* @}
NYX	0:85b3fd62ea1a	1742	*/
NYX	0:85b3fd62ea1a	1743
NYX	0:85b3fd62ea1a	1744	/* Private functions ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	1745	/** @defgroup TIM_Private_Functions TIM Private Functions
NYX	0:85b3fd62ea1a	1746	* @{
NYX	0:85b3fd62ea1a	1747	*/
NYX	0:85b3fd62ea1a	1748	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
NYX	0:85b3fd62ea1a	1749	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
NYX	0:85b3fd62ea1a	1750	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
NYX	0:85b3fd62ea1a	1751	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	1752	void TIM_DMAError(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	1753	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	1754	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
NYX	0:85b3fd62ea1a	1755	/**
NYX	0:85b3fd62ea1a	1756	* @}
NYX	0:85b3fd62ea1a	1757	*/
NYX	0:85b3fd62ea1a	1758
NYX	0:85b3fd62ea1a	1759	/**
NYX	0:85b3fd62ea1a	1760	* @}
NYX	0:85b3fd62ea1a	1761	*/
NYX	0:85b3fd62ea1a	1762
NYX	0:85b3fd62ea1a	1763	/**
NYX	0:85b3fd62ea1a	1764	* @}
NYX	0:85b3fd62ea1a	1765	*/
NYX	0:85b3fd62ea1a	1766
NYX	0:85b3fd62ea1a	1767	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	1768	}
NYX	0:85b3fd62ea1a	1769	#endif
NYX	0:85b3fd62ea1a	1770
NYX	0:85b3fd62ea1a	1771	#endif /* __STM32F4xx_HAL_TIM_H */
NYX	0:85b3fd62ea1a	1772
NYX	0:85b3fd62ea1a	1773	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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