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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_tim.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief TIM HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides firmware functions to manage the following
NYX 0:85b3fd62ea1a 9 * functionalities of the Timer (TIM) peripheral:
NYX 0:85b3fd62ea1a 10 * + Time Base Initialization
NYX 0:85b3fd62ea1a 11 * + Time Base Start
NYX 0:85b3fd62ea1a 12 * + Time Base Start Interruption
NYX 0:85b3fd62ea1a 13 * + Time Base Start DMA
NYX 0:85b3fd62ea1a 14 * + Time Output Compare/PWM Initialization
NYX 0:85b3fd62ea1a 15 * + Time Output Compare/PWM Channel Configuration
NYX 0:85b3fd62ea1a 16 * + Time Output Compare/PWM Start
NYX 0:85b3fd62ea1a 17 * + Time Output Compare/PWM Start Interruption
NYX 0:85b3fd62ea1a 18 * + Time Output Compare/PWM Start DMA
NYX 0:85b3fd62ea1a 19 * + Time Input Capture Initialization
NYX 0:85b3fd62ea1a 20 * + Time Input Capture Channel Configuration
NYX 0:85b3fd62ea1a 21 * + Time Input Capture Start
NYX 0:85b3fd62ea1a 22 * + Time Input Capture Start Interruption
NYX 0:85b3fd62ea1a 23 * + Time Input Capture Start DMA
NYX 0:85b3fd62ea1a 24 * + Time One Pulse Initialization
NYX 0:85b3fd62ea1a 25 * + Time One Pulse Channel Configuration
NYX 0:85b3fd62ea1a 26 * + Time One Pulse Start
NYX 0:85b3fd62ea1a 27 * + Time Encoder Interface Initialization
NYX 0:85b3fd62ea1a 28 * + Time Encoder Interface Start
NYX 0:85b3fd62ea1a 29 * + Time Encoder Interface Start Interruption
NYX 0:85b3fd62ea1a 30 * + Time Encoder Interface Start DMA
NYX 0:85b3fd62ea1a 31 * + Commutation Event configuration with Interruption and DMA
NYX 0:85b3fd62ea1a 32 * + Time OCRef clear configuration
NYX 0:85b3fd62ea1a 33 * + Time External Clock configuration
NYX 0:85b3fd62ea1a 34 @verbatim
NYX 0:85b3fd62ea1a 35 ==============================================================================
NYX 0:85b3fd62ea1a 36 ##### TIMER Generic features #####
NYX 0:85b3fd62ea1a 37 ==============================================================================
NYX 0:85b3fd62ea1a 38 [..] The Timer features include:
NYX 0:85b3fd62ea1a 39 (#) 16-bit up, down, up/down auto-reload counter.
NYX 0:85b3fd62ea1a 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
NYX 0:85b3fd62ea1a 41 counter clock frequency either by any factor between 1 and 65536.
NYX 0:85b3fd62ea1a 42 (#) Up to 4 independent channels for:
NYX 0:85b3fd62ea1a 43 (++) Input Capture
NYX 0:85b3fd62ea1a 44 (++) Output Compare
NYX 0:85b3fd62ea1a 45 (++) PWM generation (Edge and Center-aligned Mode)
NYX 0:85b3fd62ea1a 46 (++) One-pulse mode output
NYX 0:85b3fd62ea1a 47
NYX 0:85b3fd62ea1a 48 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 49 ==============================================================================
NYX 0:85b3fd62ea1a 50 [..]
NYX 0:85b3fd62ea1a 51 (#) Initialize the TIM low level resources by implementing the following functions
NYX 0:85b3fd62ea1a 52 depending from feature used :
NYX 0:85b3fd62ea1a 53 (++) Time Base : HAL_TIM_Base_MspInit()
NYX 0:85b3fd62ea1a 54 (++) Input Capture : HAL_TIM_IC_MspInit()
NYX 0:85b3fd62ea1a 55 (++) Output Compare : HAL_TIM_OC_MspInit()
NYX 0:85b3fd62ea1a 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
NYX 0:85b3fd62ea1a 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
NYX 0:85b3fd62ea1a 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
NYX 0:85b3fd62ea1a 59
NYX 0:85b3fd62ea1a 60 (#) Initialize the TIM low level resources :
NYX 0:85b3fd62ea1a 61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
NYX 0:85b3fd62ea1a 62 (##) TIM pins configuration
NYX 0:85b3fd62ea1a 63 (+++) Enable the clock for the TIM GPIOs using the following function:
NYX 0:85b3fd62ea1a 64 __GPIOx_CLK_ENABLE();
NYX 0:85b3fd62ea1a 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
NYX 0:85b3fd62ea1a 66
NYX 0:85b3fd62ea1a 67 (#) The external Clock can be configured, if needed (the default clock is the
NYX 0:85b3fd62ea1a 68 internal clock from the APBx), using the following function:
NYX 0:85b3fd62ea1a 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
NYX 0:85b3fd62ea1a 70 any start function.
NYX 0:85b3fd62ea1a 71
NYX 0:85b3fd62ea1a 72 (#) Configure the TIM in the desired functioning mode using one of the
NYX 0:85b3fd62ea1a 73 initialization function of this driver:
NYX 0:85b3fd62ea1a 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
NYX 0:85b3fd62ea1a 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
NYX 0:85b3fd62ea1a 76 Output Compare signal.
NYX 0:85b3fd62ea1a 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
NYX 0:85b3fd62ea1a 78 PWM signal.
NYX 0:85b3fd62ea1a 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
NYX 0:85b3fd62ea1a 80 external signal.
NYX 0:85b3fd62ea1a 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
NYX 0:85b3fd62ea1a 82 in One Pulse Mode.
NYX 0:85b3fd62ea1a 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
NYX 0:85b3fd62ea1a 84
NYX 0:85b3fd62ea1a 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
NYX 0:85b3fd62ea1a 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
NYX 0:85b3fd62ea1a 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
NYX 0:85b3fd62ea1a 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
NYX 0:85b3fd62ea1a 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
NYX 0:85b3fd62ea1a 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
NYX 0:85b3fd62ea1a 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
NYX 0:85b3fd62ea1a 92
NYX 0:85b3fd62ea1a 93 (#) The DMA Burst is managed with the two following functions:
NYX 0:85b3fd62ea1a 94 HAL_TIM_DMABurst_WriteStart()
NYX 0:85b3fd62ea1a 95 HAL_TIM_DMABurst_ReadStart()
NYX 0:85b3fd62ea1a 96
NYX 0:85b3fd62ea1a 97 @endverbatim
NYX 0:85b3fd62ea1a 98 ******************************************************************************
NYX 0:85b3fd62ea1a 99 * @attention
NYX 0:85b3fd62ea1a 100 *
NYX 0:85b3fd62ea1a 101 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 102 *
NYX 0:85b3fd62ea1a 103 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 104 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 105 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 106 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 108 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 109 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 111 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 112 * without specific prior written permission.
NYX 0:85b3fd62ea1a 113 *
NYX 0:85b3fd62ea1a 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 124 *
NYX 0:85b3fd62ea1a 125 ******************************************************************************
NYX 0:85b3fd62ea1a 126 */
NYX 0:85b3fd62ea1a 127
NYX 0:85b3fd62ea1a 128 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 129 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 130
NYX 0:85b3fd62ea1a 131 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 132 * @{
NYX 0:85b3fd62ea1a 133 */
NYX 0:85b3fd62ea1a 134
NYX 0:85b3fd62ea1a 135 /** @defgroup TIM TIM
NYX 0:85b3fd62ea1a 136 * @brief TIM HAL module driver
NYX 0:85b3fd62ea1a 137 * @{
NYX 0:85b3fd62ea1a 138 */
NYX 0:85b3fd62ea1a 139
NYX 0:85b3fd62ea1a 140 #ifdef HAL_TIM_MODULE_ENABLED
NYX 0:85b3fd62ea1a 141
NYX 0:85b3fd62ea1a 142 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 143 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 144 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 145 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 146 /** @addtogroup TIM_Private_Functions
NYX 0:85b3fd62ea1a 147 * @{
NYX 0:85b3fd62ea1a 148 */
NYX 0:85b3fd62ea1a 149 /* Private function prototypes -----------------------------------------------*/
NYX 0:85b3fd62ea1a 150 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
NYX 0:85b3fd62ea1a 151 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
NYX 0:85b3fd62ea1a 152 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
NYX 0:85b3fd62ea1a 153
NYX 0:85b3fd62ea1a 154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
NYX 0:85b3fd62ea1a 155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
NYX 0:85b3fd62ea1a 156 uint32_t TIM_ICFilter);
NYX 0:85b3fd62ea1a 157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
NYX 0:85b3fd62ea1a 158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
NYX 0:85b3fd62ea1a 159 uint32_t TIM_ICFilter);
NYX 0:85b3fd62ea1a 160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
NYX 0:85b3fd62ea1a 161 uint32_t TIM_ICFilter);
NYX 0:85b3fd62ea1a 162
NYX 0:85b3fd62ea1a 163 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
NYX 0:85b3fd62ea1a 164 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
NYX 0:85b3fd62ea1a 165
NYX 0:85b3fd62ea1a 166 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
NYX 0:85b3fd62ea1a 167 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 168 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 169 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
NYX 0:85b3fd62ea1a 170 TIM_SlaveConfigTypeDef * sSlaveConfig);
NYX 0:85b3fd62ea1a 171 /**
NYX 0:85b3fd62ea1a 172 * @}
NYX 0:85b3fd62ea1a 173 */
NYX 0:85b3fd62ea1a 174
NYX 0:85b3fd62ea1a 175 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
NYX 0:85b3fd62ea1a 177 * @{
NYX 0:85b3fd62ea1a 178 */
NYX 0:85b3fd62ea1a 179
NYX 0:85b3fd62ea1a 180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
NYX 0:85b3fd62ea1a 181 * @brief Time Base functions
NYX 0:85b3fd62ea1a 182 *
NYX 0:85b3fd62ea1a 183 @verbatim
NYX 0:85b3fd62ea1a 184 ==============================================================================
NYX 0:85b3fd62ea1a 185 ##### Time Base functions #####
NYX 0:85b3fd62ea1a 186 ==============================================================================
NYX 0:85b3fd62ea1a 187 [..]
NYX 0:85b3fd62ea1a 188 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 189 (+) Initialize and configure the TIM base.
NYX 0:85b3fd62ea1a 190 (+) De-initialize the TIM base.
NYX 0:85b3fd62ea1a 191 (+) Start the Time Base.
NYX 0:85b3fd62ea1a 192 (+) Stop the Time Base.
NYX 0:85b3fd62ea1a 193 (+) Start the Time Base and enable interrupt.
NYX 0:85b3fd62ea1a 194 (+) Stop the Time Base and disable interrupt.
NYX 0:85b3fd62ea1a 195 (+) Start the Time Base and enable DMA transfer.
NYX 0:85b3fd62ea1a 196 (+) Stop the Time Base and disable DMA transfer.
NYX 0:85b3fd62ea1a 197
NYX 0:85b3fd62ea1a 198 @endverbatim
NYX 0:85b3fd62ea1a 199 * @{
NYX 0:85b3fd62ea1a 200 */
NYX 0:85b3fd62ea1a 201 /**
NYX 0:85b3fd62ea1a 202 * @brief Initializes the TIM Time base Unit according to the specified
NYX 0:85b3fd62ea1a 203 * parameters in the TIM_HandleTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 204 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 205 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 206 * @retval HAL status
NYX 0:85b3fd62ea1a 207 */
NYX 0:85b3fd62ea1a 208 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 209 {
NYX 0:85b3fd62ea1a 210 /* Check the TIM handle allocation */
NYX 0:85b3fd62ea1a 211 if(htim == NULL)
NYX 0:85b3fd62ea1a 212 {
NYX 0:85b3fd62ea1a 213 return HAL_ERROR;
NYX 0:85b3fd62ea1a 214 }
NYX 0:85b3fd62ea1a 215
NYX 0:85b3fd62ea1a 216 /* Check the parameters */
NYX 0:85b3fd62ea1a 217 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 218 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
NYX 0:85b3fd62ea1a 219 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
NYX 0:85b3fd62ea1a 220
NYX 0:85b3fd62ea1a 221 if(htim->State == HAL_TIM_STATE_RESET)
NYX 0:85b3fd62ea1a 222 {
NYX 0:85b3fd62ea1a 223 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 224 htim->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 225 /* Init the low level hardware : GPIO, CLOCK, NVIC */
NYX 0:85b3fd62ea1a 226 HAL_TIM_Base_MspInit(htim);
NYX 0:85b3fd62ea1a 227 }
NYX 0:85b3fd62ea1a 228
NYX 0:85b3fd62ea1a 229 /* Set the TIM state */
NYX 0:85b3fd62ea1a 230 htim->State= HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 231
NYX 0:85b3fd62ea1a 232 /* Set the Time Base configuration */
NYX 0:85b3fd62ea1a 233 TIM_Base_SetConfig(htim->Instance, &htim->Init);
NYX 0:85b3fd62ea1a 234
NYX 0:85b3fd62ea1a 235 /* Initialize the TIM state*/
NYX 0:85b3fd62ea1a 236 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 237
NYX 0:85b3fd62ea1a 238 return HAL_OK;
NYX 0:85b3fd62ea1a 239 }
NYX 0:85b3fd62ea1a 240
NYX 0:85b3fd62ea1a 241 /**
NYX 0:85b3fd62ea1a 242 * @brief DeInitializes the TIM Base peripheral
NYX 0:85b3fd62ea1a 243 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 244 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 245 * @retval HAL status
NYX 0:85b3fd62ea1a 246 */
NYX 0:85b3fd62ea1a 247 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 248 {
NYX 0:85b3fd62ea1a 249 /* Check the parameters */
NYX 0:85b3fd62ea1a 250 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 251
NYX 0:85b3fd62ea1a 252 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 253
NYX 0:85b3fd62ea1a 254 /* Disable the TIM Peripheral Clock */
NYX 0:85b3fd62ea1a 255 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 256
NYX 0:85b3fd62ea1a 257 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
NYX 0:85b3fd62ea1a 258 HAL_TIM_Base_MspDeInit(htim);
NYX 0:85b3fd62ea1a 259
NYX 0:85b3fd62ea1a 260 /* Change TIM state */
NYX 0:85b3fd62ea1a 261 htim->State = HAL_TIM_STATE_RESET;
NYX 0:85b3fd62ea1a 262
NYX 0:85b3fd62ea1a 263 /* Release Lock */
NYX 0:85b3fd62ea1a 264 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 265
NYX 0:85b3fd62ea1a 266 return HAL_OK;
NYX 0:85b3fd62ea1a 267 }
NYX 0:85b3fd62ea1a 268
NYX 0:85b3fd62ea1a 269 /**
NYX 0:85b3fd62ea1a 270 * @brief Initializes the TIM Base MSP.
NYX 0:85b3fd62ea1a 271 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 272 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 273 * @retval None
NYX 0:85b3fd62ea1a 274 */
NYX 0:85b3fd62ea1a 275 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 276 {
NYX 0:85b3fd62ea1a 277 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 278 UNUSED(htim);
NYX 0:85b3fd62ea1a 279 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 280 the HAL_TIM_Base_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 281 */
NYX 0:85b3fd62ea1a 282 }
NYX 0:85b3fd62ea1a 283
NYX 0:85b3fd62ea1a 284 /**
NYX 0:85b3fd62ea1a 285 * @brief DeInitializes TIM Base MSP.
NYX 0:85b3fd62ea1a 286 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 287 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 288 * @retval None
NYX 0:85b3fd62ea1a 289 */
NYX 0:85b3fd62ea1a 290 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 291 {
NYX 0:85b3fd62ea1a 292 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 293 UNUSED(htim);
NYX 0:85b3fd62ea1a 294 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 295 the HAL_TIM_Base_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 296 */
NYX 0:85b3fd62ea1a 297 }
NYX 0:85b3fd62ea1a 298
NYX 0:85b3fd62ea1a 299 /**
NYX 0:85b3fd62ea1a 300 * @brief Starts the TIM Base generation.
NYX 0:85b3fd62ea1a 301 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 302 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 303 * @retval HAL status
NYX 0:85b3fd62ea1a 304 */
NYX 0:85b3fd62ea1a 305 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 306 {
NYX 0:85b3fd62ea1a 307 /* Check the parameters */
NYX 0:85b3fd62ea1a 308 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 309
NYX 0:85b3fd62ea1a 310 /* Set the TIM state */
NYX 0:85b3fd62ea1a 311 htim->State= HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 312
NYX 0:85b3fd62ea1a 313 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 314 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 315
NYX 0:85b3fd62ea1a 316 /* Change the TIM state*/
NYX 0:85b3fd62ea1a 317 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 318
NYX 0:85b3fd62ea1a 319 /* Return function status */
NYX 0:85b3fd62ea1a 320 return HAL_OK;
NYX 0:85b3fd62ea1a 321 }
NYX 0:85b3fd62ea1a 322
NYX 0:85b3fd62ea1a 323 /**
NYX 0:85b3fd62ea1a 324 * @brief Stops the TIM Base generation.
NYX 0:85b3fd62ea1a 325 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 326 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 327 * @retval HAL status
NYX 0:85b3fd62ea1a 328 */
NYX 0:85b3fd62ea1a 329 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 330 {
NYX 0:85b3fd62ea1a 331 /* Check the parameters */
NYX 0:85b3fd62ea1a 332 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 333
NYX 0:85b3fd62ea1a 334 /* Set the TIM state */
NYX 0:85b3fd62ea1a 335 htim->State= HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 336
NYX 0:85b3fd62ea1a 337 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 338 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 339
NYX 0:85b3fd62ea1a 340 /* Change the TIM state*/
NYX 0:85b3fd62ea1a 341 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 342
NYX 0:85b3fd62ea1a 343 /* Return function status */
NYX 0:85b3fd62ea1a 344 return HAL_OK;
NYX 0:85b3fd62ea1a 345 }
NYX 0:85b3fd62ea1a 346
NYX 0:85b3fd62ea1a 347 /**
NYX 0:85b3fd62ea1a 348 * @brief Starts the TIM Base generation in interrupt mode.
NYX 0:85b3fd62ea1a 349 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 350 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 351 * @retval HAL status
NYX 0:85b3fd62ea1a 352 */
NYX 0:85b3fd62ea1a 353 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 354 {
NYX 0:85b3fd62ea1a 355 /* Check the parameters */
NYX 0:85b3fd62ea1a 356 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 357
NYX 0:85b3fd62ea1a 358 /* Enable the TIM Update interrupt */
NYX 0:85b3fd62ea1a 359 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
NYX 0:85b3fd62ea1a 360
NYX 0:85b3fd62ea1a 361 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 362 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 363
NYX 0:85b3fd62ea1a 364 /* Return function status */
NYX 0:85b3fd62ea1a 365 return HAL_OK;
NYX 0:85b3fd62ea1a 366 }
NYX 0:85b3fd62ea1a 367
NYX 0:85b3fd62ea1a 368 /**
NYX 0:85b3fd62ea1a 369 * @brief Stops the TIM Base generation in interrupt mode.
NYX 0:85b3fd62ea1a 370 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 371 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 372 * @retval HAL status
NYX 0:85b3fd62ea1a 373 */
NYX 0:85b3fd62ea1a 374 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 375 {
NYX 0:85b3fd62ea1a 376 /* Check the parameters */
NYX 0:85b3fd62ea1a 377 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 378 /* Disable the TIM Update interrupt */
NYX 0:85b3fd62ea1a 379 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
NYX 0:85b3fd62ea1a 380
NYX 0:85b3fd62ea1a 381 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 382 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 383
NYX 0:85b3fd62ea1a 384 /* Return function status */
NYX 0:85b3fd62ea1a 385 return HAL_OK;
NYX 0:85b3fd62ea1a 386 }
NYX 0:85b3fd62ea1a 387
NYX 0:85b3fd62ea1a 388 /**
NYX 0:85b3fd62ea1a 389 * @brief Starts the TIM Base generation in DMA mode.
NYX 0:85b3fd62ea1a 390 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 391 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 392 * @param pData: The source Buffer address.
NYX 0:85b3fd62ea1a 393 * @param Length: The length of data to be transferred from memory to peripheral.
NYX 0:85b3fd62ea1a 394 * @retval HAL status
NYX 0:85b3fd62ea1a 395 */
NYX 0:85b3fd62ea1a 396 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
NYX 0:85b3fd62ea1a 397 {
NYX 0:85b3fd62ea1a 398 /* Check the parameters */
NYX 0:85b3fd62ea1a 399 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 400
NYX 0:85b3fd62ea1a 401 if((htim->State == HAL_TIM_STATE_BUSY))
NYX 0:85b3fd62ea1a 402 {
NYX 0:85b3fd62ea1a 403 return HAL_BUSY;
NYX 0:85b3fd62ea1a 404 }
NYX 0:85b3fd62ea1a 405 else if((htim->State == HAL_TIM_STATE_READY))
NYX 0:85b3fd62ea1a 406 {
NYX 0:85b3fd62ea1a 407 if((pData == 0U) && (Length > 0))
NYX 0:85b3fd62ea1a 408 {
NYX 0:85b3fd62ea1a 409 return HAL_ERROR;
NYX 0:85b3fd62ea1a 410 }
NYX 0:85b3fd62ea1a 411 else
NYX 0:85b3fd62ea1a 412 {
NYX 0:85b3fd62ea1a 413 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 414 }
NYX 0:85b3fd62ea1a 415 }
NYX 0:85b3fd62ea1a 416 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 417 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
NYX 0:85b3fd62ea1a 418
NYX 0:85b3fd62ea1a 419 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 420 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 421
NYX 0:85b3fd62ea1a 422 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 423 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
NYX 0:85b3fd62ea1a 424
NYX 0:85b3fd62ea1a 425 /* Enable the TIM Update DMA request */
NYX 0:85b3fd62ea1a 426 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 429 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 430
NYX 0:85b3fd62ea1a 431 /* Return function status */
NYX 0:85b3fd62ea1a 432 return HAL_OK;
NYX 0:85b3fd62ea1a 433 }
NYX 0:85b3fd62ea1a 434
NYX 0:85b3fd62ea1a 435 /**
NYX 0:85b3fd62ea1a 436 * @brief Stops the TIM Base generation in DMA mode.
NYX 0:85b3fd62ea1a 437 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 438 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 439 * @retval HAL status
NYX 0:85b3fd62ea1a 440 */
NYX 0:85b3fd62ea1a 441 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 442 {
NYX 0:85b3fd62ea1a 443 /* Check the parameters */
NYX 0:85b3fd62ea1a 444 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 445
NYX 0:85b3fd62ea1a 446 /* Disable the TIM Update DMA request */
NYX 0:85b3fd62ea1a 447 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
NYX 0:85b3fd62ea1a 448
NYX 0:85b3fd62ea1a 449 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 450 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 451
NYX 0:85b3fd62ea1a 452 /* Change the htim state */
NYX 0:85b3fd62ea1a 453 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 454
NYX 0:85b3fd62ea1a 455 /* Return function status */
NYX 0:85b3fd62ea1a 456 return HAL_OK;
NYX 0:85b3fd62ea1a 457 }
NYX 0:85b3fd62ea1a 458 /**
NYX 0:85b3fd62ea1a 459 * @}
NYX 0:85b3fd62ea1a 460 */
NYX 0:85b3fd62ea1a 461
NYX 0:85b3fd62ea1a 462 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
NYX 0:85b3fd62ea1a 463 * @brief Time Output Compare functions
NYX 0:85b3fd62ea1a 464 *
NYX 0:85b3fd62ea1a 465 @verbatim
NYX 0:85b3fd62ea1a 466 ==============================================================================
NYX 0:85b3fd62ea1a 467 ##### Time Output Compare functions #####
NYX 0:85b3fd62ea1a 468 ==============================================================================
NYX 0:85b3fd62ea1a 469 [..]
NYX 0:85b3fd62ea1a 470 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 471 (+) Initialize and configure the TIM Output Compare.
NYX 0:85b3fd62ea1a 472 (+) De-initialize the TIM Output Compare.
NYX 0:85b3fd62ea1a 473 (+) Start the Time Output Compare.
NYX 0:85b3fd62ea1a 474 (+) Stop the Time Output Compare.
NYX 0:85b3fd62ea1a 475 (+) Start the Time Output Compare and enable interrupt.
NYX 0:85b3fd62ea1a 476 (+) Stop the Time Output Compare and disable interrupt.
NYX 0:85b3fd62ea1a 477 (+) Start the Time Output Compare and enable DMA transfer.
NYX 0:85b3fd62ea1a 478 (+) Stop the Time Output Compare and disable DMA transfer.
NYX 0:85b3fd62ea1a 479
NYX 0:85b3fd62ea1a 480 @endverbatim
NYX 0:85b3fd62ea1a 481 * @{
NYX 0:85b3fd62ea1a 482 */
NYX 0:85b3fd62ea1a 483 /**
NYX 0:85b3fd62ea1a 484 * @brief Initializes the TIM Output Compare according to the specified
NYX 0:85b3fd62ea1a 485 * parameters in the TIM_HandleTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 486 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 487 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 488 * @retval HAL status
NYX 0:85b3fd62ea1a 489 */
NYX 0:85b3fd62ea1a 490 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
NYX 0:85b3fd62ea1a 491 {
NYX 0:85b3fd62ea1a 492 /* Check the TIM handle allocation */
NYX 0:85b3fd62ea1a 493 if(htim == NULL)
NYX 0:85b3fd62ea1a 494 {
NYX 0:85b3fd62ea1a 495 return HAL_ERROR;
NYX 0:85b3fd62ea1a 496 }
NYX 0:85b3fd62ea1a 497
NYX 0:85b3fd62ea1a 498 /* Check the parameters */
NYX 0:85b3fd62ea1a 499 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 500 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
NYX 0:85b3fd62ea1a 501 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
NYX 0:85b3fd62ea1a 502
NYX 0:85b3fd62ea1a 503 if(htim->State == HAL_TIM_STATE_RESET)
NYX 0:85b3fd62ea1a 504 {
NYX 0:85b3fd62ea1a 505 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 506 htim->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 507 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
NYX 0:85b3fd62ea1a 508 HAL_TIM_OC_MspInit(htim);
NYX 0:85b3fd62ea1a 509 }
NYX 0:85b3fd62ea1a 510
NYX 0:85b3fd62ea1a 511 /* Set the TIM state */
NYX 0:85b3fd62ea1a 512 htim->State= HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 513
NYX 0:85b3fd62ea1a 514 /* Init the base time for the Output Compare */
NYX 0:85b3fd62ea1a 515 TIM_Base_SetConfig(htim->Instance, &htim->Init);
NYX 0:85b3fd62ea1a 516
NYX 0:85b3fd62ea1a 517 /* Initialize the TIM state*/
NYX 0:85b3fd62ea1a 518 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 519
NYX 0:85b3fd62ea1a 520 return HAL_OK;
NYX 0:85b3fd62ea1a 521 }
NYX 0:85b3fd62ea1a 522
NYX 0:85b3fd62ea1a 523 /**
NYX 0:85b3fd62ea1a 524 * @brief DeInitializes the TIM peripheral
NYX 0:85b3fd62ea1a 525 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 526 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 527 * @retval HAL status
NYX 0:85b3fd62ea1a 528 */
NYX 0:85b3fd62ea1a 529 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 530 {
NYX 0:85b3fd62ea1a 531 /* Check the parameters */
NYX 0:85b3fd62ea1a 532 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 533
NYX 0:85b3fd62ea1a 534 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 535
NYX 0:85b3fd62ea1a 536 /* Disable the TIM Peripheral Clock */
NYX 0:85b3fd62ea1a 537 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
NYX 0:85b3fd62ea1a 540 HAL_TIM_OC_MspDeInit(htim);
NYX 0:85b3fd62ea1a 541
NYX 0:85b3fd62ea1a 542 /* Change TIM state */
NYX 0:85b3fd62ea1a 543 htim->State = HAL_TIM_STATE_RESET;
NYX 0:85b3fd62ea1a 544
NYX 0:85b3fd62ea1a 545 /* Release Lock */
NYX 0:85b3fd62ea1a 546 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 547
NYX 0:85b3fd62ea1a 548 return HAL_OK;
NYX 0:85b3fd62ea1a 549 }
NYX 0:85b3fd62ea1a 550
NYX 0:85b3fd62ea1a 551 /**
NYX 0:85b3fd62ea1a 552 * @brief Initializes the TIM Output Compare MSP.
NYX 0:85b3fd62ea1a 553 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 554 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 555 * @retval None
NYX 0:85b3fd62ea1a 556 */
NYX 0:85b3fd62ea1a 557 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 558 {
NYX 0:85b3fd62ea1a 559 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 560 UNUSED(htim);
NYX 0:85b3fd62ea1a 561 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 562 the HAL_TIM_OC_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 563 */
NYX 0:85b3fd62ea1a 564 }
NYX 0:85b3fd62ea1a 565
NYX 0:85b3fd62ea1a 566 /**
NYX 0:85b3fd62ea1a 567 * @brief DeInitializes TIM Output Compare MSP.
NYX 0:85b3fd62ea1a 568 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 569 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 570 * @retval None
NYX 0:85b3fd62ea1a 571 */
NYX 0:85b3fd62ea1a 572 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 573 {
NYX 0:85b3fd62ea1a 574 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 575 UNUSED(htim);
NYX 0:85b3fd62ea1a 576 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 577 the HAL_TIM_OC_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 578 */
NYX 0:85b3fd62ea1a 579 }
NYX 0:85b3fd62ea1a 580
NYX 0:85b3fd62ea1a 581 /**
NYX 0:85b3fd62ea1a 582 * @brief Starts the TIM Output Compare signal generation.
NYX 0:85b3fd62ea1a 583 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 584 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 585 * @param Channel: TIM Channel to be enabled.
NYX 0:85b3fd62ea1a 586 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 587 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 588 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 589 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 590 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 591 * @retval HAL status
NYX 0:85b3fd62ea1a 592 */
NYX 0:85b3fd62ea1a 593 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 594 {
NYX 0:85b3fd62ea1a 595 /* Check the parameters */
NYX 0:85b3fd62ea1a 596 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 597
NYX 0:85b3fd62ea1a 598 /* Enable the Output compare channel */
NYX 0:85b3fd62ea1a 599 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 600
NYX 0:85b3fd62ea1a 601 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 602 {
NYX 0:85b3fd62ea1a 603 /* Enable the main output */
NYX 0:85b3fd62ea1a 604 __HAL_TIM_MOE_ENABLE(htim);
NYX 0:85b3fd62ea1a 605 }
NYX 0:85b3fd62ea1a 606
NYX 0:85b3fd62ea1a 607 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 608 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 609
NYX 0:85b3fd62ea1a 610 /* Return function status */
NYX 0:85b3fd62ea1a 611 return HAL_OK;
NYX 0:85b3fd62ea1a 612 }
NYX 0:85b3fd62ea1a 613
NYX 0:85b3fd62ea1a 614 /**
NYX 0:85b3fd62ea1a 615 * @brief Stops the TIM Output Compare signal generation.
NYX 0:85b3fd62ea1a 616 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 617 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 618 * @param Channel: TIM Channel to be disabled.
NYX 0:85b3fd62ea1a 619 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 620 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 621 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 622 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 623 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 624 * @retval HAL status
NYX 0:85b3fd62ea1a 625 */
NYX 0:85b3fd62ea1a 626 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 627 {
NYX 0:85b3fd62ea1a 628 /* Check the parameters */
NYX 0:85b3fd62ea1a 629 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 630
NYX 0:85b3fd62ea1a 631 /* Disable the Output compare channel */
NYX 0:85b3fd62ea1a 632 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 633
NYX 0:85b3fd62ea1a 634 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 635 {
NYX 0:85b3fd62ea1a 636 /* Disable the Main Output */
NYX 0:85b3fd62ea1a 637 __HAL_TIM_MOE_DISABLE(htim);
NYX 0:85b3fd62ea1a 638 }
NYX 0:85b3fd62ea1a 639
NYX 0:85b3fd62ea1a 640 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 641 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 642
NYX 0:85b3fd62ea1a 643 /* Return function status */
NYX 0:85b3fd62ea1a 644 return HAL_OK;
NYX 0:85b3fd62ea1a 645 }
NYX 0:85b3fd62ea1a 646
NYX 0:85b3fd62ea1a 647 /**
NYX 0:85b3fd62ea1a 648 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
NYX 0:85b3fd62ea1a 649 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 650 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 651 * @param Channel: TIM Channel to be enabled.
NYX 0:85b3fd62ea1a 652 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 653 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 654 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 655 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 656 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 657 * @retval HAL status
NYX 0:85b3fd62ea1a 658 */
NYX 0:85b3fd62ea1a 659 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 660 {
NYX 0:85b3fd62ea1a 661 /* Check the parameters */
NYX 0:85b3fd62ea1a 662 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 663
NYX 0:85b3fd62ea1a 664 switch (Channel)
NYX 0:85b3fd62ea1a 665 {
NYX 0:85b3fd62ea1a 666 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 667 {
NYX 0:85b3fd62ea1a 668 /* Enable the TIM Capture/Compare 1 interrupt */
NYX 0:85b3fd62ea1a 669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 670 }
NYX 0:85b3fd62ea1a 671 break;
NYX 0:85b3fd62ea1a 672
NYX 0:85b3fd62ea1a 673 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 674 {
NYX 0:85b3fd62ea1a 675 /* Enable the TIM Capture/Compare 2 interrupt */
NYX 0:85b3fd62ea1a 676 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 677 }
NYX 0:85b3fd62ea1a 678 break;
NYX 0:85b3fd62ea1a 679
NYX 0:85b3fd62ea1a 680 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 681 {
NYX 0:85b3fd62ea1a 682 /* Enable the TIM Capture/Compare 3 interrupt */
NYX 0:85b3fd62ea1a 683 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
NYX 0:85b3fd62ea1a 684 }
NYX 0:85b3fd62ea1a 685 break;
NYX 0:85b3fd62ea1a 686
NYX 0:85b3fd62ea1a 687 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 688 {
NYX 0:85b3fd62ea1a 689 /* Enable the TIM Capture/Compare 4 interrupt */
NYX 0:85b3fd62ea1a 690 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
NYX 0:85b3fd62ea1a 691 }
NYX 0:85b3fd62ea1a 692 break;
NYX 0:85b3fd62ea1a 693
NYX 0:85b3fd62ea1a 694 default:
NYX 0:85b3fd62ea1a 695 break;
NYX 0:85b3fd62ea1a 696 }
NYX 0:85b3fd62ea1a 697
NYX 0:85b3fd62ea1a 698 /* Enable the Output compare channel */
NYX 0:85b3fd62ea1a 699 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 700
NYX 0:85b3fd62ea1a 701 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 702 {
NYX 0:85b3fd62ea1a 703 /* Enable the main output */
NYX 0:85b3fd62ea1a 704 __HAL_TIM_MOE_ENABLE(htim);
NYX 0:85b3fd62ea1a 705 }
NYX 0:85b3fd62ea1a 706
NYX 0:85b3fd62ea1a 707 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 708 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 709
NYX 0:85b3fd62ea1a 710 /* Return function status */
NYX 0:85b3fd62ea1a 711 return HAL_OK;
NYX 0:85b3fd62ea1a 712 }
NYX 0:85b3fd62ea1a 713
NYX 0:85b3fd62ea1a 714 /**
NYX 0:85b3fd62ea1a 715 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
NYX 0:85b3fd62ea1a 716 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 717 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 718 * @param Channel: TIM Channel to be disabled.
NYX 0:85b3fd62ea1a 719 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 720 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 721 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 722 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 723 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 724 * @retval HAL status
NYX 0:85b3fd62ea1a 725 */
NYX 0:85b3fd62ea1a 726 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 727 {
NYX 0:85b3fd62ea1a 728 /* Check the parameters */
NYX 0:85b3fd62ea1a 729 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 730
NYX 0:85b3fd62ea1a 731 switch (Channel)
NYX 0:85b3fd62ea1a 732 {
NYX 0:85b3fd62ea1a 733 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 734 {
NYX 0:85b3fd62ea1a 735 /* Disable the TIM Capture/Compare 1 interrupt */
NYX 0:85b3fd62ea1a 736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 737 }
NYX 0:85b3fd62ea1a 738 break;
NYX 0:85b3fd62ea1a 739
NYX 0:85b3fd62ea1a 740 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 741 {
NYX 0:85b3fd62ea1a 742 /* Disable the TIM Capture/Compare 2 interrupt */
NYX 0:85b3fd62ea1a 743 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 744 }
NYX 0:85b3fd62ea1a 745 break;
NYX 0:85b3fd62ea1a 746
NYX 0:85b3fd62ea1a 747 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 748 {
NYX 0:85b3fd62ea1a 749 /* Disable the TIM Capture/Compare 3 interrupt */
NYX 0:85b3fd62ea1a 750 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
NYX 0:85b3fd62ea1a 751 }
NYX 0:85b3fd62ea1a 752 break;
NYX 0:85b3fd62ea1a 753
NYX 0:85b3fd62ea1a 754 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 755 {
NYX 0:85b3fd62ea1a 756 /* Disable the TIM Capture/Compare 4 interrupt */
NYX 0:85b3fd62ea1a 757 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
NYX 0:85b3fd62ea1a 758 }
NYX 0:85b3fd62ea1a 759 break;
NYX 0:85b3fd62ea1a 760
NYX 0:85b3fd62ea1a 761 default:
NYX 0:85b3fd62ea1a 762 break;
NYX 0:85b3fd62ea1a 763 }
NYX 0:85b3fd62ea1a 764
NYX 0:85b3fd62ea1a 765 /* Disable the Output compare channel */
NYX 0:85b3fd62ea1a 766 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 767
NYX 0:85b3fd62ea1a 768 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 769 {
NYX 0:85b3fd62ea1a 770 /* Disable the Main Output */
NYX 0:85b3fd62ea1a 771 __HAL_TIM_MOE_DISABLE(htim);
NYX 0:85b3fd62ea1a 772 }
NYX 0:85b3fd62ea1a 773
NYX 0:85b3fd62ea1a 774 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 775 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 776
NYX 0:85b3fd62ea1a 777 /* Return function status */
NYX 0:85b3fd62ea1a 778 return HAL_OK;
NYX 0:85b3fd62ea1a 779 }
NYX 0:85b3fd62ea1a 780
NYX 0:85b3fd62ea1a 781 /**
NYX 0:85b3fd62ea1a 782 * @brief Starts the TIM Output Compare signal generation in DMA mode.
NYX 0:85b3fd62ea1a 783 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 784 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 785 * @param Channel: TIM Channel to be enabled.
NYX 0:85b3fd62ea1a 786 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 787 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 788 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 789 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 790 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 791 * @param pData: The source Buffer address.
NYX 0:85b3fd62ea1a 792 * @param Length: The length of data to be transferred from memory to TIM peripheral
NYX 0:85b3fd62ea1a 793 * @retval HAL status
NYX 0:85b3fd62ea1a 794 */
NYX 0:85b3fd62ea1a 795 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
NYX 0:85b3fd62ea1a 796 {
NYX 0:85b3fd62ea1a 797 /* Check the parameters */
NYX 0:85b3fd62ea1a 798 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 799
NYX 0:85b3fd62ea1a 800 if((htim->State == HAL_TIM_STATE_BUSY))
NYX 0:85b3fd62ea1a 801 {
NYX 0:85b3fd62ea1a 802 return HAL_BUSY;
NYX 0:85b3fd62ea1a 803 }
NYX 0:85b3fd62ea1a 804 else if((htim->State == HAL_TIM_STATE_READY))
NYX 0:85b3fd62ea1a 805 {
NYX 0:85b3fd62ea1a 806 if(((uint32_t)pData == 0U) && (Length > 0))
NYX 0:85b3fd62ea1a 807 {
NYX 0:85b3fd62ea1a 808 return HAL_ERROR;
NYX 0:85b3fd62ea1a 809 }
NYX 0:85b3fd62ea1a 810 else
NYX 0:85b3fd62ea1a 811 {
NYX 0:85b3fd62ea1a 812 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 813 }
NYX 0:85b3fd62ea1a 814 }
NYX 0:85b3fd62ea1a 815 switch (Channel)
NYX 0:85b3fd62ea1a 816 {
NYX 0:85b3fd62ea1a 817 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 818 {
NYX 0:85b3fd62ea1a 819 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 820 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 821
NYX 0:85b3fd62ea1a 822 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 823 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 824
NYX 0:85b3fd62ea1a 825 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 826 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
NYX 0:85b3fd62ea1a 827
NYX 0:85b3fd62ea1a 828 /* Enable the TIM Capture/Compare 1 DMA request */
NYX 0:85b3fd62ea1a 829 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 830 }
NYX 0:85b3fd62ea1a 831 break;
NYX 0:85b3fd62ea1a 832
NYX 0:85b3fd62ea1a 833 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 834 {
NYX 0:85b3fd62ea1a 835 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 836 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 837
NYX 0:85b3fd62ea1a 838 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 839 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 840
NYX 0:85b3fd62ea1a 841 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 842 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
NYX 0:85b3fd62ea1a 843
NYX 0:85b3fd62ea1a 844 /* Enable the TIM Capture/Compare 2 DMA request */
NYX 0:85b3fd62ea1a 845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 846 }
NYX 0:85b3fd62ea1a 847 break;
NYX 0:85b3fd62ea1a 848
NYX 0:85b3fd62ea1a 849 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 850 {
NYX 0:85b3fd62ea1a 851 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 852 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 853
NYX 0:85b3fd62ea1a 854 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 855 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 856
NYX 0:85b3fd62ea1a 857 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 858 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
NYX 0:85b3fd62ea1a 859
NYX 0:85b3fd62ea1a 860 /* Enable the TIM Capture/Compare 3 DMA request */
NYX 0:85b3fd62ea1a 861 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
NYX 0:85b3fd62ea1a 862 }
NYX 0:85b3fd62ea1a 863 break;
NYX 0:85b3fd62ea1a 864
NYX 0:85b3fd62ea1a 865 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 866 {
NYX 0:85b3fd62ea1a 867 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 868 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 869
NYX 0:85b3fd62ea1a 870 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 871 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 872
NYX 0:85b3fd62ea1a 873 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 874 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
NYX 0:85b3fd62ea1a 875
NYX 0:85b3fd62ea1a 876 /* Enable the TIM Capture/Compare 4 DMA request */
NYX 0:85b3fd62ea1a 877 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
NYX 0:85b3fd62ea1a 878 }
NYX 0:85b3fd62ea1a 879 break;
NYX 0:85b3fd62ea1a 880
NYX 0:85b3fd62ea1a 881 default:
NYX 0:85b3fd62ea1a 882 break;
NYX 0:85b3fd62ea1a 883 }
NYX 0:85b3fd62ea1a 884
NYX 0:85b3fd62ea1a 885 /* Enable the Output compare channel */
NYX 0:85b3fd62ea1a 886 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 887
NYX 0:85b3fd62ea1a 888 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 889 {
NYX 0:85b3fd62ea1a 890 /* Enable the main output */
NYX 0:85b3fd62ea1a 891 __HAL_TIM_MOE_ENABLE(htim);
NYX 0:85b3fd62ea1a 892 }
NYX 0:85b3fd62ea1a 893
NYX 0:85b3fd62ea1a 894 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 895 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 896
NYX 0:85b3fd62ea1a 897 /* Return function status */
NYX 0:85b3fd62ea1a 898 return HAL_OK;
NYX 0:85b3fd62ea1a 899 }
NYX 0:85b3fd62ea1a 900
NYX 0:85b3fd62ea1a 901 /**
NYX 0:85b3fd62ea1a 902 * @brief Stops the TIM Output Compare signal generation in DMA mode.
NYX 0:85b3fd62ea1a 903 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 904 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 905 * @param Channel: TIM Channel to be disabled.
NYX 0:85b3fd62ea1a 906 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 907 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 908 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 909 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 910 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 911 * @retval HAL status
NYX 0:85b3fd62ea1a 912 */
NYX 0:85b3fd62ea1a 913 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 914 {
NYX 0:85b3fd62ea1a 915 /* Check the parameters */
NYX 0:85b3fd62ea1a 916 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 917
NYX 0:85b3fd62ea1a 918 switch (Channel)
NYX 0:85b3fd62ea1a 919 {
NYX 0:85b3fd62ea1a 920 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 921 {
NYX 0:85b3fd62ea1a 922 /* Disable the TIM Capture/Compare 1 DMA request */
NYX 0:85b3fd62ea1a 923 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 924 }
NYX 0:85b3fd62ea1a 925 break;
NYX 0:85b3fd62ea1a 926
NYX 0:85b3fd62ea1a 927 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 928 {
NYX 0:85b3fd62ea1a 929 /* Disable the TIM Capture/Compare 2 DMA request */
NYX 0:85b3fd62ea1a 930 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 931 }
NYX 0:85b3fd62ea1a 932 break;
NYX 0:85b3fd62ea1a 933
NYX 0:85b3fd62ea1a 934 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 935 {
NYX 0:85b3fd62ea1a 936 /* Disable the TIM Capture/Compare 3 DMA request */
NYX 0:85b3fd62ea1a 937 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
NYX 0:85b3fd62ea1a 938 }
NYX 0:85b3fd62ea1a 939 break;
NYX 0:85b3fd62ea1a 940
NYX 0:85b3fd62ea1a 941 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 942 {
NYX 0:85b3fd62ea1a 943 /* Disable the TIM Capture/Compare 4 interrupt */
NYX 0:85b3fd62ea1a 944 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
NYX 0:85b3fd62ea1a 945 }
NYX 0:85b3fd62ea1a 946 break;
NYX 0:85b3fd62ea1a 947
NYX 0:85b3fd62ea1a 948 default:
NYX 0:85b3fd62ea1a 949 break;
NYX 0:85b3fd62ea1a 950 }
NYX 0:85b3fd62ea1a 951
NYX 0:85b3fd62ea1a 952 /* Disable the Output compare channel */
NYX 0:85b3fd62ea1a 953 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 954
NYX 0:85b3fd62ea1a 955 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 956 {
NYX 0:85b3fd62ea1a 957 /* Disable the Main Output */
NYX 0:85b3fd62ea1a 958 __HAL_TIM_MOE_DISABLE(htim);
NYX 0:85b3fd62ea1a 959 }
NYX 0:85b3fd62ea1a 960
NYX 0:85b3fd62ea1a 961 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 962 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 963
NYX 0:85b3fd62ea1a 964 /* Change the htim state */
NYX 0:85b3fd62ea1a 965 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 966
NYX 0:85b3fd62ea1a 967 /* Return function status */
NYX 0:85b3fd62ea1a 968 return HAL_OK;
NYX 0:85b3fd62ea1a 969 }
NYX 0:85b3fd62ea1a 970 /**
NYX 0:85b3fd62ea1a 971 * @}
NYX 0:85b3fd62ea1a 972 */
NYX 0:85b3fd62ea1a 973
NYX 0:85b3fd62ea1a 974 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
NYX 0:85b3fd62ea1a 975 * @brief Time PWM functions
NYX 0:85b3fd62ea1a 976 *
NYX 0:85b3fd62ea1a 977 @verbatim
NYX 0:85b3fd62ea1a 978 ==============================================================================
NYX 0:85b3fd62ea1a 979 ##### Time PWM functions #####
NYX 0:85b3fd62ea1a 980 ==============================================================================
NYX 0:85b3fd62ea1a 981 [..]
NYX 0:85b3fd62ea1a 982 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 983 (+) Initialize and configure the TIM OPWM.
NYX 0:85b3fd62ea1a 984 (+) De-initialize the TIM PWM.
NYX 0:85b3fd62ea1a 985 (+) Start the Time PWM.
NYX 0:85b3fd62ea1a 986 (+) Stop the Time PWM.
NYX 0:85b3fd62ea1a 987 (+) Start the Time PWM and enable interrupt.
NYX 0:85b3fd62ea1a 988 (+) Stop the Time PWM and disable interrupt.
NYX 0:85b3fd62ea1a 989 (+) Start the Time PWM and enable DMA transfer.
NYX 0:85b3fd62ea1a 990 (+) Stop the Time PWM and disable DMA transfer.
NYX 0:85b3fd62ea1a 991
NYX 0:85b3fd62ea1a 992 @endverbatim
NYX 0:85b3fd62ea1a 993 * @{
NYX 0:85b3fd62ea1a 994 */
NYX 0:85b3fd62ea1a 995 /**
NYX 0:85b3fd62ea1a 996 * @brief Initializes the TIM PWM Time Base according to the specified
NYX 0:85b3fd62ea1a 997 * parameters in the TIM_HandleTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 998 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 999 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1000 * @retval HAL status
NYX 0:85b3fd62ea1a 1001 */
NYX 0:85b3fd62ea1a 1002 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 1003 {
NYX 0:85b3fd62ea1a 1004 /* Check the TIM handle allocation */
NYX 0:85b3fd62ea1a 1005 if(htim == NULL)
NYX 0:85b3fd62ea1a 1006 {
NYX 0:85b3fd62ea1a 1007 return HAL_ERROR;
NYX 0:85b3fd62ea1a 1008 }
NYX 0:85b3fd62ea1a 1009
NYX 0:85b3fd62ea1a 1010 /* Check the parameters */
NYX 0:85b3fd62ea1a 1011 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 1012 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
NYX 0:85b3fd62ea1a 1013 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
NYX 0:85b3fd62ea1a 1014
NYX 0:85b3fd62ea1a 1015 if(htim->State == HAL_TIM_STATE_RESET)
NYX 0:85b3fd62ea1a 1016 {
NYX 0:85b3fd62ea1a 1017 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 1018 htim->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 1019 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
NYX 0:85b3fd62ea1a 1020 HAL_TIM_PWM_MspInit(htim);
NYX 0:85b3fd62ea1a 1021 }
NYX 0:85b3fd62ea1a 1022
NYX 0:85b3fd62ea1a 1023 /* Set the TIM state */
NYX 0:85b3fd62ea1a 1024 htim->State= HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 1025
NYX 0:85b3fd62ea1a 1026 /* Init the base time for the PWM */
NYX 0:85b3fd62ea1a 1027 TIM_Base_SetConfig(htim->Instance, &htim->Init);
NYX 0:85b3fd62ea1a 1028
NYX 0:85b3fd62ea1a 1029 /* Initialize the TIM state*/
NYX 0:85b3fd62ea1a 1030 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 1031
NYX 0:85b3fd62ea1a 1032 return HAL_OK;
NYX 0:85b3fd62ea1a 1033 }
NYX 0:85b3fd62ea1a 1034
NYX 0:85b3fd62ea1a 1035 /**
NYX 0:85b3fd62ea1a 1036 * @brief DeInitializes the TIM peripheral
NYX 0:85b3fd62ea1a 1037 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1038 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1039 * @retval HAL status
NYX 0:85b3fd62ea1a 1040 */
NYX 0:85b3fd62ea1a 1041 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 1042 {
NYX 0:85b3fd62ea1a 1043 /* Check the parameters */
NYX 0:85b3fd62ea1a 1044 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 1045
NYX 0:85b3fd62ea1a 1046 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 1047
NYX 0:85b3fd62ea1a 1048 /* Disable the TIM Peripheral Clock */
NYX 0:85b3fd62ea1a 1049 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 1050
NYX 0:85b3fd62ea1a 1051 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
NYX 0:85b3fd62ea1a 1052 HAL_TIM_PWM_MspDeInit(htim);
NYX 0:85b3fd62ea1a 1053
NYX 0:85b3fd62ea1a 1054 /* Change TIM state */
NYX 0:85b3fd62ea1a 1055 htim->State = HAL_TIM_STATE_RESET;
NYX 0:85b3fd62ea1a 1056
NYX 0:85b3fd62ea1a 1057 /* Release Lock */
NYX 0:85b3fd62ea1a 1058 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 1059
NYX 0:85b3fd62ea1a 1060 return HAL_OK;
NYX 0:85b3fd62ea1a 1061 }
NYX 0:85b3fd62ea1a 1062
NYX 0:85b3fd62ea1a 1063 /**
NYX 0:85b3fd62ea1a 1064 * @brief Initializes the TIM PWM MSP.
NYX 0:85b3fd62ea1a 1065 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1066 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1067 * @retval None
NYX 0:85b3fd62ea1a 1068 */
NYX 0:85b3fd62ea1a 1069 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 1070 {
NYX 0:85b3fd62ea1a 1071 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1072 UNUSED(htim);
NYX 0:85b3fd62ea1a 1073 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1074 the HAL_TIM_PWM_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 1075 */
NYX 0:85b3fd62ea1a 1076 }
NYX 0:85b3fd62ea1a 1077
NYX 0:85b3fd62ea1a 1078 /**
NYX 0:85b3fd62ea1a 1079 * @brief DeInitializes TIM PWM MSP.
NYX 0:85b3fd62ea1a 1080 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1081 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1082 * @retval None
NYX 0:85b3fd62ea1a 1083 */
NYX 0:85b3fd62ea1a 1084 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 1085 {
NYX 0:85b3fd62ea1a 1086 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1087 UNUSED(htim);
NYX 0:85b3fd62ea1a 1088 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1089 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 1090 */
NYX 0:85b3fd62ea1a 1091 }
NYX 0:85b3fd62ea1a 1092
NYX 0:85b3fd62ea1a 1093 /**
NYX 0:85b3fd62ea1a 1094 * @brief Starts the PWM signal generation.
NYX 0:85b3fd62ea1a 1095 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1096 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1097 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 1098 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1099 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1100 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1101 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1102 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1103 * @retval HAL status
NYX 0:85b3fd62ea1a 1104 */
NYX 0:85b3fd62ea1a 1105 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1106 {
NYX 0:85b3fd62ea1a 1107 /* Check the parameters */
NYX 0:85b3fd62ea1a 1108 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1109
NYX 0:85b3fd62ea1a 1110 /* Enable the Capture compare channel */
NYX 0:85b3fd62ea1a 1111 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 1112
NYX 0:85b3fd62ea1a 1113 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 1114 {
NYX 0:85b3fd62ea1a 1115 /* Enable the main output */
NYX 0:85b3fd62ea1a 1116 __HAL_TIM_MOE_ENABLE(htim);
NYX 0:85b3fd62ea1a 1117 }
NYX 0:85b3fd62ea1a 1118
NYX 0:85b3fd62ea1a 1119 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 1120 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 1121
NYX 0:85b3fd62ea1a 1122 /* Return function status */
NYX 0:85b3fd62ea1a 1123 return HAL_OK;
NYX 0:85b3fd62ea1a 1124 }
NYX 0:85b3fd62ea1a 1125
NYX 0:85b3fd62ea1a 1126 /**
NYX 0:85b3fd62ea1a 1127 * @brief Stops the PWM signal generation.
NYX 0:85b3fd62ea1a 1128 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1129 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1130 * @param Channel: TIM Channels to be disabled.
NYX 0:85b3fd62ea1a 1131 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1132 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1133 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1134 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1135 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1136 * @retval HAL status
NYX 0:85b3fd62ea1a 1137 */
NYX 0:85b3fd62ea1a 1138 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1139 {
NYX 0:85b3fd62ea1a 1140 /* Check the parameters */
NYX 0:85b3fd62ea1a 1141 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1142
NYX 0:85b3fd62ea1a 1143 /* Disable the Capture compare channel */
NYX 0:85b3fd62ea1a 1144 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 1145
NYX 0:85b3fd62ea1a 1146 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 1147 {
NYX 0:85b3fd62ea1a 1148 /* Disable the Main Output */
NYX 0:85b3fd62ea1a 1149 __HAL_TIM_MOE_DISABLE(htim);
NYX 0:85b3fd62ea1a 1150 }
NYX 0:85b3fd62ea1a 1151
NYX 0:85b3fd62ea1a 1152 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 1153 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 1154
NYX 0:85b3fd62ea1a 1155 /* Change the htim state */
NYX 0:85b3fd62ea1a 1156 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 1157
NYX 0:85b3fd62ea1a 1158 /* Return function status */
NYX 0:85b3fd62ea1a 1159 return HAL_OK;
NYX 0:85b3fd62ea1a 1160 }
NYX 0:85b3fd62ea1a 1161
NYX 0:85b3fd62ea1a 1162 /**
NYX 0:85b3fd62ea1a 1163 * @brief Starts the PWM signal generation in interrupt mode.
NYX 0:85b3fd62ea1a 1164 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1165 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1166 * @param Channel: TIM Channel to be enabled.
NYX 0:85b3fd62ea1a 1167 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1168 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1169 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1170 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1171 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1172 * @retval HAL status
NYX 0:85b3fd62ea1a 1173 */
NYX 0:85b3fd62ea1a 1174 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1175 {
NYX 0:85b3fd62ea1a 1176 /* Check the parameters */
NYX 0:85b3fd62ea1a 1177 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1178
NYX 0:85b3fd62ea1a 1179 switch (Channel)
NYX 0:85b3fd62ea1a 1180 {
NYX 0:85b3fd62ea1a 1181 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 1182 {
NYX 0:85b3fd62ea1a 1183 /* Enable the TIM Capture/Compare 1 interrupt */
NYX 0:85b3fd62ea1a 1184 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 1185 }
NYX 0:85b3fd62ea1a 1186 break;
NYX 0:85b3fd62ea1a 1187
NYX 0:85b3fd62ea1a 1188 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 1189 {
NYX 0:85b3fd62ea1a 1190 /* Enable the TIM Capture/Compare 2 interrupt */
NYX 0:85b3fd62ea1a 1191 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 1192 }
NYX 0:85b3fd62ea1a 1193 break;
NYX 0:85b3fd62ea1a 1194
NYX 0:85b3fd62ea1a 1195 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 1196 {
NYX 0:85b3fd62ea1a 1197 /* Enable the TIM Capture/Compare 3 interrupt */
NYX 0:85b3fd62ea1a 1198 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
NYX 0:85b3fd62ea1a 1199 }
NYX 0:85b3fd62ea1a 1200 break;
NYX 0:85b3fd62ea1a 1201
NYX 0:85b3fd62ea1a 1202 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 1203 {
NYX 0:85b3fd62ea1a 1204 /* Enable the TIM Capture/Compare 4 interrupt */
NYX 0:85b3fd62ea1a 1205 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
NYX 0:85b3fd62ea1a 1206 }
NYX 0:85b3fd62ea1a 1207 break;
NYX 0:85b3fd62ea1a 1208
NYX 0:85b3fd62ea1a 1209 default:
NYX 0:85b3fd62ea1a 1210 break;
NYX 0:85b3fd62ea1a 1211 }
NYX 0:85b3fd62ea1a 1212
NYX 0:85b3fd62ea1a 1213 /* Enable the Capture compare channel */
NYX 0:85b3fd62ea1a 1214 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 1215
NYX 0:85b3fd62ea1a 1216 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 1217 {
NYX 0:85b3fd62ea1a 1218 /* Enable the main output */
NYX 0:85b3fd62ea1a 1219 __HAL_TIM_MOE_ENABLE(htim);
NYX 0:85b3fd62ea1a 1220 }
NYX 0:85b3fd62ea1a 1221
NYX 0:85b3fd62ea1a 1222 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 1223 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 1224
NYX 0:85b3fd62ea1a 1225 /* Return function status */
NYX 0:85b3fd62ea1a 1226 return HAL_OK;
NYX 0:85b3fd62ea1a 1227 }
NYX 0:85b3fd62ea1a 1228
NYX 0:85b3fd62ea1a 1229 /**
NYX 0:85b3fd62ea1a 1230 * @brief Stops the PWM signal generation in interrupt mode.
NYX 0:85b3fd62ea1a 1231 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1232 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1233 * @param Channel: TIM Channels to be disabled.
NYX 0:85b3fd62ea1a 1234 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1235 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1236 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1237 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1238 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1239 * @retval HAL status
NYX 0:85b3fd62ea1a 1240 */
NYX 0:85b3fd62ea1a 1241 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1242 {
NYX 0:85b3fd62ea1a 1243 /* Check the parameters */
NYX 0:85b3fd62ea1a 1244 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1245
NYX 0:85b3fd62ea1a 1246 switch (Channel)
NYX 0:85b3fd62ea1a 1247 {
NYX 0:85b3fd62ea1a 1248 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 1249 {
NYX 0:85b3fd62ea1a 1250 /* Disable the TIM Capture/Compare 1 interrupt */
NYX 0:85b3fd62ea1a 1251 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 1252 }
NYX 0:85b3fd62ea1a 1253 break;
NYX 0:85b3fd62ea1a 1254
NYX 0:85b3fd62ea1a 1255 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 1256 {
NYX 0:85b3fd62ea1a 1257 /* Disable the TIM Capture/Compare 2 interrupt */
NYX 0:85b3fd62ea1a 1258 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 1259 }
NYX 0:85b3fd62ea1a 1260 break;
NYX 0:85b3fd62ea1a 1261
NYX 0:85b3fd62ea1a 1262 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 1263 {
NYX 0:85b3fd62ea1a 1264 /* Disable the TIM Capture/Compare 3 interrupt */
NYX 0:85b3fd62ea1a 1265 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
NYX 0:85b3fd62ea1a 1266 }
NYX 0:85b3fd62ea1a 1267 break;
NYX 0:85b3fd62ea1a 1268
NYX 0:85b3fd62ea1a 1269 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 1270 {
NYX 0:85b3fd62ea1a 1271 /* Disable the TIM Capture/Compare 4 interrupt */
NYX 0:85b3fd62ea1a 1272 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
NYX 0:85b3fd62ea1a 1273 }
NYX 0:85b3fd62ea1a 1274 break;
NYX 0:85b3fd62ea1a 1275
NYX 0:85b3fd62ea1a 1276 default:
NYX 0:85b3fd62ea1a 1277 break;
NYX 0:85b3fd62ea1a 1278 }
NYX 0:85b3fd62ea1a 1279
NYX 0:85b3fd62ea1a 1280 /* Disable the Capture compare channel */
NYX 0:85b3fd62ea1a 1281 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 1282
NYX 0:85b3fd62ea1a 1283 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 1284 {
NYX 0:85b3fd62ea1a 1285 /* Disable the Main Output */
NYX 0:85b3fd62ea1a 1286 __HAL_TIM_MOE_DISABLE(htim);
NYX 0:85b3fd62ea1a 1287 }
NYX 0:85b3fd62ea1a 1288
NYX 0:85b3fd62ea1a 1289 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 1290 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 1291
NYX 0:85b3fd62ea1a 1292 /* Return function status */
NYX 0:85b3fd62ea1a 1293 return HAL_OK;
NYX 0:85b3fd62ea1a 1294 }
NYX 0:85b3fd62ea1a 1295
NYX 0:85b3fd62ea1a 1296 /**
NYX 0:85b3fd62ea1a 1297 * @brief Starts the TIM PWM signal generation in DMA mode.
NYX 0:85b3fd62ea1a 1298 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1299 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1300 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 1301 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1302 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1303 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1304 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1305 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1306 * @param pData: The source Buffer address.
NYX 0:85b3fd62ea1a 1307 * @param Length: The length of data to be transferred from memory to TIM peripheral
NYX 0:85b3fd62ea1a 1308 * @retval HAL status
NYX 0:85b3fd62ea1a 1309 */
NYX 0:85b3fd62ea1a 1310 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
NYX 0:85b3fd62ea1a 1311 {
NYX 0:85b3fd62ea1a 1312 /* Check the parameters */
NYX 0:85b3fd62ea1a 1313 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1314
NYX 0:85b3fd62ea1a 1315 if((htim->State == HAL_TIM_STATE_BUSY))
NYX 0:85b3fd62ea1a 1316 {
NYX 0:85b3fd62ea1a 1317 return HAL_BUSY;
NYX 0:85b3fd62ea1a 1318 }
NYX 0:85b3fd62ea1a 1319 else if((htim->State == HAL_TIM_STATE_READY))
NYX 0:85b3fd62ea1a 1320 {
NYX 0:85b3fd62ea1a 1321 if(((uint32_t)pData == 0U) && (Length > 0))
NYX 0:85b3fd62ea1a 1322 {
NYX 0:85b3fd62ea1a 1323 return HAL_ERROR;
NYX 0:85b3fd62ea1a 1324 }
NYX 0:85b3fd62ea1a 1325 else
NYX 0:85b3fd62ea1a 1326 {
NYX 0:85b3fd62ea1a 1327 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 1328 }
NYX 0:85b3fd62ea1a 1329 }
NYX 0:85b3fd62ea1a 1330 switch (Channel)
NYX 0:85b3fd62ea1a 1331 {
NYX 0:85b3fd62ea1a 1332 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 1333 {
NYX 0:85b3fd62ea1a 1334 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 1335 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 1336
NYX 0:85b3fd62ea1a 1337 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 1338 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 1339
NYX 0:85b3fd62ea1a 1340 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 1341 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
NYX 0:85b3fd62ea1a 1342
NYX 0:85b3fd62ea1a 1343 /* Enable the TIM Capture/Compare 1 DMA request */
NYX 0:85b3fd62ea1a 1344 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 1345 }
NYX 0:85b3fd62ea1a 1346 break;
NYX 0:85b3fd62ea1a 1347
NYX 0:85b3fd62ea1a 1348 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 1349 {
NYX 0:85b3fd62ea1a 1350 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 1351 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 1352
NYX 0:85b3fd62ea1a 1353 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 1354 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 1355
NYX 0:85b3fd62ea1a 1356 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 1357 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
NYX 0:85b3fd62ea1a 1358
NYX 0:85b3fd62ea1a 1359 /* Enable the TIM Capture/Compare 2 DMA request */
NYX 0:85b3fd62ea1a 1360 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 1361 }
NYX 0:85b3fd62ea1a 1362 break;
NYX 0:85b3fd62ea1a 1363
NYX 0:85b3fd62ea1a 1364 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 1365 {
NYX 0:85b3fd62ea1a 1366 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 1367 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 1368
NYX 0:85b3fd62ea1a 1369 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 1370 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 1371
NYX 0:85b3fd62ea1a 1372 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 1373 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
NYX 0:85b3fd62ea1a 1374
NYX 0:85b3fd62ea1a 1375 /* Enable the TIM Output Capture/Compare 3 request */
NYX 0:85b3fd62ea1a 1376 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
NYX 0:85b3fd62ea1a 1377 }
NYX 0:85b3fd62ea1a 1378 break;
NYX 0:85b3fd62ea1a 1379
NYX 0:85b3fd62ea1a 1380 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 1381 {
NYX 0:85b3fd62ea1a 1382 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 1383 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 1384
NYX 0:85b3fd62ea1a 1385 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 1386 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 1387
NYX 0:85b3fd62ea1a 1388 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 1389 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
NYX 0:85b3fd62ea1a 1390
NYX 0:85b3fd62ea1a 1391 /* Enable the TIM Capture/Compare 4 DMA request */
NYX 0:85b3fd62ea1a 1392 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
NYX 0:85b3fd62ea1a 1393 }
NYX 0:85b3fd62ea1a 1394 break;
NYX 0:85b3fd62ea1a 1395
NYX 0:85b3fd62ea1a 1396 default:
NYX 0:85b3fd62ea1a 1397 break;
NYX 0:85b3fd62ea1a 1398 }
NYX 0:85b3fd62ea1a 1399
NYX 0:85b3fd62ea1a 1400 /* Enable the Capture compare channel */
NYX 0:85b3fd62ea1a 1401 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 1402
NYX 0:85b3fd62ea1a 1403 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 1404 {
NYX 0:85b3fd62ea1a 1405 /* Enable the main output */
NYX 0:85b3fd62ea1a 1406 __HAL_TIM_MOE_ENABLE(htim);
NYX 0:85b3fd62ea1a 1407 }
NYX 0:85b3fd62ea1a 1408
NYX 0:85b3fd62ea1a 1409 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 1410 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 1411
NYX 0:85b3fd62ea1a 1412 /* Return function status */
NYX 0:85b3fd62ea1a 1413 return HAL_OK;
NYX 0:85b3fd62ea1a 1414 }
NYX 0:85b3fd62ea1a 1415
NYX 0:85b3fd62ea1a 1416 /**
NYX 0:85b3fd62ea1a 1417 * @brief Stops the TIM PWM signal generation in DMA mode.
NYX 0:85b3fd62ea1a 1418 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1419 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1420 * @param Channel: TIM Channels to be disabled.
NYX 0:85b3fd62ea1a 1421 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1422 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1423 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1424 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1425 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1426 * @retval HAL status
NYX 0:85b3fd62ea1a 1427 */
NYX 0:85b3fd62ea1a 1428 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1429 {
NYX 0:85b3fd62ea1a 1430 /* Check the parameters */
NYX 0:85b3fd62ea1a 1431 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1432
NYX 0:85b3fd62ea1a 1433 switch (Channel)
NYX 0:85b3fd62ea1a 1434 {
NYX 0:85b3fd62ea1a 1435 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 1436 {
NYX 0:85b3fd62ea1a 1437 /* Disable the TIM Capture/Compare 1 DMA request */
NYX 0:85b3fd62ea1a 1438 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 1439 }
NYX 0:85b3fd62ea1a 1440 break;
NYX 0:85b3fd62ea1a 1441
NYX 0:85b3fd62ea1a 1442 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 1443 {
NYX 0:85b3fd62ea1a 1444 /* Disable the TIM Capture/Compare 2 DMA request */
NYX 0:85b3fd62ea1a 1445 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 1446 }
NYX 0:85b3fd62ea1a 1447 break;
NYX 0:85b3fd62ea1a 1448
NYX 0:85b3fd62ea1a 1449 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 1450 {
NYX 0:85b3fd62ea1a 1451 /* Disable the TIM Capture/Compare 3 DMA request */
NYX 0:85b3fd62ea1a 1452 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
NYX 0:85b3fd62ea1a 1453 }
NYX 0:85b3fd62ea1a 1454 break;
NYX 0:85b3fd62ea1a 1455
NYX 0:85b3fd62ea1a 1456 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 1457 {
NYX 0:85b3fd62ea1a 1458 /* Disable the TIM Capture/Compare 4 interrupt */
NYX 0:85b3fd62ea1a 1459 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
NYX 0:85b3fd62ea1a 1460 }
NYX 0:85b3fd62ea1a 1461 break;
NYX 0:85b3fd62ea1a 1462
NYX 0:85b3fd62ea1a 1463 default:
NYX 0:85b3fd62ea1a 1464 break;
NYX 0:85b3fd62ea1a 1465 }
NYX 0:85b3fd62ea1a 1466
NYX 0:85b3fd62ea1a 1467 /* Disable the Capture compare channel */
NYX 0:85b3fd62ea1a 1468 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 1469
NYX 0:85b3fd62ea1a 1470 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 1471 {
NYX 0:85b3fd62ea1a 1472 /* Disable the Main Output */
NYX 0:85b3fd62ea1a 1473 __HAL_TIM_MOE_DISABLE(htim);
NYX 0:85b3fd62ea1a 1474 }
NYX 0:85b3fd62ea1a 1475
NYX 0:85b3fd62ea1a 1476 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 1477 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 1478
NYX 0:85b3fd62ea1a 1479 /* Change the htim state */
NYX 0:85b3fd62ea1a 1480 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 1481
NYX 0:85b3fd62ea1a 1482 /* Return function status */
NYX 0:85b3fd62ea1a 1483 return HAL_OK;
NYX 0:85b3fd62ea1a 1484 }
NYX 0:85b3fd62ea1a 1485 /**
NYX 0:85b3fd62ea1a 1486 * @}
NYX 0:85b3fd62ea1a 1487 */
NYX 0:85b3fd62ea1a 1488
NYX 0:85b3fd62ea1a 1489 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
NYX 0:85b3fd62ea1a 1490 * @brief Time Input Capture functions
NYX 0:85b3fd62ea1a 1491 *
NYX 0:85b3fd62ea1a 1492 @verbatim
NYX 0:85b3fd62ea1a 1493 ==============================================================================
NYX 0:85b3fd62ea1a 1494 ##### Time Input Capture functions #####
NYX 0:85b3fd62ea1a 1495 ==============================================================================
NYX 0:85b3fd62ea1a 1496 [..]
NYX 0:85b3fd62ea1a 1497 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 1498 (+) Initialize and configure the TIM Input Capture.
NYX 0:85b3fd62ea1a 1499 (+) De-initialize the TIM Input Capture.
NYX 0:85b3fd62ea1a 1500 (+) Start the Time Input Capture.
NYX 0:85b3fd62ea1a 1501 (+) Stop the Time Input Capture.
NYX 0:85b3fd62ea1a 1502 (+) Start the Time Input Capture and enable interrupt.
NYX 0:85b3fd62ea1a 1503 (+) Stop the Time Input Capture and disable interrupt.
NYX 0:85b3fd62ea1a 1504 (+) Start the Time Input Capture and enable DMA transfer.
NYX 0:85b3fd62ea1a 1505 (+) Stop the Time Input Capture and disable DMA transfer.
NYX 0:85b3fd62ea1a 1506
NYX 0:85b3fd62ea1a 1507 @endverbatim
NYX 0:85b3fd62ea1a 1508 * @{
NYX 0:85b3fd62ea1a 1509 */
NYX 0:85b3fd62ea1a 1510 /**
NYX 0:85b3fd62ea1a 1511 * @brief Initializes the TIM Input Capture Time base according to the specified
NYX 0:85b3fd62ea1a 1512 * parameters in the TIM_HandleTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 1513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1514 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1515 * @retval HAL status
NYX 0:85b3fd62ea1a 1516 */
NYX 0:85b3fd62ea1a 1517 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 1518 {
NYX 0:85b3fd62ea1a 1519 /* Check the TIM handle allocation */
NYX 0:85b3fd62ea1a 1520 if(htim == NULL)
NYX 0:85b3fd62ea1a 1521 {
NYX 0:85b3fd62ea1a 1522 return HAL_ERROR;
NYX 0:85b3fd62ea1a 1523 }
NYX 0:85b3fd62ea1a 1524
NYX 0:85b3fd62ea1a 1525 /* Check the parameters */
NYX 0:85b3fd62ea1a 1526 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 1527 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
NYX 0:85b3fd62ea1a 1528 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
NYX 0:85b3fd62ea1a 1529
NYX 0:85b3fd62ea1a 1530 if(htim->State == HAL_TIM_STATE_RESET)
NYX 0:85b3fd62ea1a 1531 {
NYX 0:85b3fd62ea1a 1532 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 1533 htim->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 1534 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
NYX 0:85b3fd62ea1a 1535 HAL_TIM_IC_MspInit(htim);
NYX 0:85b3fd62ea1a 1536 }
NYX 0:85b3fd62ea1a 1537
NYX 0:85b3fd62ea1a 1538 /* Set the TIM state */
NYX 0:85b3fd62ea1a 1539 htim->State= HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 1540
NYX 0:85b3fd62ea1a 1541 /* Init the base time for the input capture */
NYX 0:85b3fd62ea1a 1542 TIM_Base_SetConfig(htim->Instance, &htim->Init);
NYX 0:85b3fd62ea1a 1543
NYX 0:85b3fd62ea1a 1544 /* Initialize the TIM state*/
NYX 0:85b3fd62ea1a 1545 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 1546
NYX 0:85b3fd62ea1a 1547 return HAL_OK;
NYX 0:85b3fd62ea1a 1548 }
NYX 0:85b3fd62ea1a 1549
NYX 0:85b3fd62ea1a 1550 /**
NYX 0:85b3fd62ea1a 1551 * @brief DeInitializes the TIM peripheral
NYX 0:85b3fd62ea1a 1552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1553 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1554 * @retval HAL status
NYX 0:85b3fd62ea1a 1555 */
NYX 0:85b3fd62ea1a 1556 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 1557 {
NYX 0:85b3fd62ea1a 1558 /* Check the parameters */
NYX 0:85b3fd62ea1a 1559 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 1560
NYX 0:85b3fd62ea1a 1561 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 1562
NYX 0:85b3fd62ea1a 1563 /* Disable the TIM Peripheral Clock */
NYX 0:85b3fd62ea1a 1564 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 1565
NYX 0:85b3fd62ea1a 1566 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
NYX 0:85b3fd62ea1a 1567 HAL_TIM_IC_MspDeInit(htim);
NYX 0:85b3fd62ea1a 1568
NYX 0:85b3fd62ea1a 1569 /* Change TIM state */
NYX 0:85b3fd62ea1a 1570 htim->State = HAL_TIM_STATE_RESET;
NYX 0:85b3fd62ea1a 1571
NYX 0:85b3fd62ea1a 1572 /* Release Lock */
NYX 0:85b3fd62ea1a 1573 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 1574
NYX 0:85b3fd62ea1a 1575 return HAL_OK;
NYX 0:85b3fd62ea1a 1576 }
NYX 0:85b3fd62ea1a 1577
NYX 0:85b3fd62ea1a 1578 /**
NYX 0:85b3fd62ea1a 1579 * @brief Initializes the TIM INput Capture MSP.
NYX 0:85b3fd62ea1a 1580 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1581 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1582 * @retval None
NYX 0:85b3fd62ea1a 1583 */
NYX 0:85b3fd62ea1a 1584 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 1585 {
NYX 0:85b3fd62ea1a 1586 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1587 UNUSED(htim);
NYX 0:85b3fd62ea1a 1588 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1589 the HAL_TIM_IC_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 1590 */
NYX 0:85b3fd62ea1a 1591 }
NYX 0:85b3fd62ea1a 1592
NYX 0:85b3fd62ea1a 1593 /**
NYX 0:85b3fd62ea1a 1594 * @brief DeInitializes TIM Input Capture MSP.
NYX 0:85b3fd62ea1a 1595 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1596 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1597 * @retval None
NYX 0:85b3fd62ea1a 1598 */
NYX 0:85b3fd62ea1a 1599 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 1600 {
NYX 0:85b3fd62ea1a 1601 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 1602 UNUSED(htim);
NYX 0:85b3fd62ea1a 1603 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 1604 the HAL_TIM_IC_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 1605 */
NYX 0:85b3fd62ea1a 1606 }
NYX 0:85b3fd62ea1a 1607
NYX 0:85b3fd62ea1a 1608 /**
NYX 0:85b3fd62ea1a 1609 * @brief Starts the TIM Input Capture measurement.
NYX 0:85b3fd62ea1a 1610 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1611 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1612 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 1613 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1614 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1615 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1616 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1617 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1618 * @retval HAL status
NYX 0:85b3fd62ea1a 1619 */
NYX 0:85b3fd62ea1a 1620 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1621 {
NYX 0:85b3fd62ea1a 1622 /* Check the parameters */
NYX 0:85b3fd62ea1a 1623 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1624
NYX 0:85b3fd62ea1a 1625 /* Enable the Input Capture channel */
NYX 0:85b3fd62ea1a 1626 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 1627
NYX 0:85b3fd62ea1a 1628 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 1629 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 1630
NYX 0:85b3fd62ea1a 1631 /* Return function status */
NYX 0:85b3fd62ea1a 1632 return HAL_OK;
NYX 0:85b3fd62ea1a 1633 }
NYX 0:85b3fd62ea1a 1634
NYX 0:85b3fd62ea1a 1635 /**
NYX 0:85b3fd62ea1a 1636 * @brief Stops the TIM Input Capture measurement.
NYX 0:85b3fd62ea1a 1637 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1638 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1639 * @param Channel: TIM Channels to be disabled.
NYX 0:85b3fd62ea1a 1640 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1641 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1642 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1643 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1644 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1645 * @retval HAL status
NYX 0:85b3fd62ea1a 1646 */
NYX 0:85b3fd62ea1a 1647 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1648 {
NYX 0:85b3fd62ea1a 1649 /* Check the parameters */
NYX 0:85b3fd62ea1a 1650 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1651
NYX 0:85b3fd62ea1a 1652 /* Disable the Input Capture channel */
NYX 0:85b3fd62ea1a 1653 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 1654
NYX 0:85b3fd62ea1a 1655 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 1656 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 1657
NYX 0:85b3fd62ea1a 1658 /* Return function status */
NYX 0:85b3fd62ea1a 1659 return HAL_OK;
NYX 0:85b3fd62ea1a 1660 }
NYX 0:85b3fd62ea1a 1661
NYX 0:85b3fd62ea1a 1662 /**
NYX 0:85b3fd62ea1a 1663 * @brief Starts the TIM Input Capture measurement in interrupt mode.
NYX 0:85b3fd62ea1a 1664 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1665 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1666 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 1667 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1668 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1669 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1670 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1671 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1672 * @retval HAL status
NYX 0:85b3fd62ea1a 1673 */
NYX 0:85b3fd62ea1a 1674 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1675 {
NYX 0:85b3fd62ea1a 1676 /* Check the parameters */
NYX 0:85b3fd62ea1a 1677 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1678
NYX 0:85b3fd62ea1a 1679 switch (Channel)
NYX 0:85b3fd62ea1a 1680 {
NYX 0:85b3fd62ea1a 1681 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 1682 {
NYX 0:85b3fd62ea1a 1683 /* Enable the TIM Capture/Compare 1 interrupt */
NYX 0:85b3fd62ea1a 1684 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 1685 }
NYX 0:85b3fd62ea1a 1686 break;
NYX 0:85b3fd62ea1a 1687
NYX 0:85b3fd62ea1a 1688 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 1689 {
NYX 0:85b3fd62ea1a 1690 /* Enable the TIM Capture/Compare 2 interrupt */
NYX 0:85b3fd62ea1a 1691 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 1692 }
NYX 0:85b3fd62ea1a 1693 break;
NYX 0:85b3fd62ea1a 1694
NYX 0:85b3fd62ea1a 1695 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 1696 {
NYX 0:85b3fd62ea1a 1697 /* Enable the TIM Capture/Compare 3 interrupt */
NYX 0:85b3fd62ea1a 1698 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
NYX 0:85b3fd62ea1a 1699 }
NYX 0:85b3fd62ea1a 1700 break;
NYX 0:85b3fd62ea1a 1701
NYX 0:85b3fd62ea1a 1702 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 1703 {
NYX 0:85b3fd62ea1a 1704 /* Enable the TIM Capture/Compare 4 interrupt */
NYX 0:85b3fd62ea1a 1705 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
NYX 0:85b3fd62ea1a 1706 }
NYX 0:85b3fd62ea1a 1707 break;
NYX 0:85b3fd62ea1a 1708
NYX 0:85b3fd62ea1a 1709 default:
NYX 0:85b3fd62ea1a 1710 break;
NYX 0:85b3fd62ea1a 1711 }
NYX 0:85b3fd62ea1a 1712 /* Enable the Input Capture channel */
NYX 0:85b3fd62ea1a 1713 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 1714
NYX 0:85b3fd62ea1a 1715 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 1716 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 1717
NYX 0:85b3fd62ea1a 1718 /* Return function status */
NYX 0:85b3fd62ea1a 1719 return HAL_OK;
NYX 0:85b3fd62ea1a 1720 }
NYX 0:85b3fd62ea1a 1721
NYX 0:85b3fd62ea1a 1722 /**
NYX 0:85b3fd62ea1a 1723 * @brief Stops the TIM Input Capture measurement in interrupt mode.
NYX 0:85b3fd62ea1a 1724 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1725 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1726 * @param Channel: TIM Channels to be disabled.
NYX 0:85b3fd62ea1a 1727 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1728 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1729 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1730 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1731 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1732 * @retval HAL status
NYX 0:85b3fd62ea1a 1733 */
NYX 0:85b3fd62ea1a 1734 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1735 {
NYX 0:85b3fd62ea1a 1736 /* Check the parameters */
NYX 0:85b3fd62ea1a 1737 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1738
NYX 0:85b3fd62ea1a 1739 switch (Channel)
NYX 0:85b3fd62ea1a 1740 {
NYX 0:85b3fd62ea1a 1741 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 1742 {
NYX 0:85b3fd62ea1a 1743 /* Disable the TIM Capture/Compare 1 interrupt */
NYX 0:85b3fd62ea1a 1744 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 1745 }
NYX 0:85b3fd62ea1a 1746 break;
NYX 0:85b3fd62ea1a 1747
NYX 0:85b3fd62ea1a 1748 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 1749 {
NYX 0:85b3fd62ea1a 1750 /* Disable the TIM Capture/Compare 2 interrupt */
NYX 0:85b3fd62ea1a 1751 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 1752 }
NYX 0:85b3fd62ea1a 1753 break;
NYX 0:85b3fd62ea1a 1754
NYX 0:85b3fd62ea1a 1755 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 1756 {
NYX 0:85b3fd62ea1a 1757 /* Disable the TIM Capture/Compare 3 interrupt */
NYX 0:85b3fd62ea1a 1758 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
NYX 0:85b3fd62ea1a 1759 }
NYX 0:85b3fd62ea1a 1760 break;
NYX 0:85b3fd62ea1a 1761
NYX 0:85b3fd62ea1a 1762 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 1763 {
NYX 0:85b3fd62ea1a 1764 /* Disable the TIM Capture/Compare 4 interrupt */
NYX 0:85b3fd62ea1a 1765 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
NYX 0:85b3fd62ea1a 1766 }
NYX 0:85b3fd62ea1a 1767 break;
NYX 0:85b3fd62ea1a 1768
NYX 0:85b3fd62ea1a 1769 default:
NYX 0:85b3fd62ea1a 1770 break;
NYX 0:85b3fd62ea1a 1771 }
NYX 0:85b3fd62ea1a 1772
NYX 0:85b3fd62ea1a 1773 /* Disable the Input Capture channel */
NYX 0:85b3fd62ea1a 1774 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 1775
NYX 0:85b3fd62ea1a 1776 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 1777 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 1778
NYX 0:85b3fd62ea1a 1779 /* Return function status */
NYX 0:85b3fd62ea1a 1780 return HAL_OK;
NYX 0:85b3fd62ea1a 1781 }
NYX 0:85b3fd62ea1a 1782
NYX 0:85b3fd62ea1a 1783 /**
NYX 0:85b3fd62ea1a 1784 * @brief Starts the TIM Input Capture measurement on in DMA mode.
NYX 0:85b3fd62ea1a 1785 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1786 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1787 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 1788 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1789 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1790 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1791 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1792 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1793 * @param pData: The destination Buffer address.
NYX 0:85b3fd62ea1a 1794 * @param Length: The length of data to be transferred from TIM peripheral to memory.
NYX 0:85b3fd62ea1a 1795 * @retval HAL status
NYX 0:85b3fd62ea1a 1796 */
NYX 0:85b3fd62ea1a 1797 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
NYX 0:85b3fd62ea1a 1798 {
NYX 0:85b3fd62ea1a 1799 /* Check the parameters */
NYX 0:85b3fd62ea1a 1800 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1801 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 1802
NYX 0:85b3fd62ea1a 1803 if((htim->State == HAL_TIM_STATE_BUSY))
NYX 0:85b3fd62ea1a 1804 {
NYX 0:85b3fd62ea1a 1805 return HAL_BUSY;
NYX 0:85b3fd62ea1a 1806 }
NYX 0:85b3fd62ea1a 1807 else if((htim->State == HAL_TIM_STATE_READY))
NYX 0:85b3fd62ea1a 1808 {
NYX 0:85b3fd62ea1a 1809 if((pData == 0U) && (Length > 0))
NYX 0:85b3fd62ea1a 1810 {
NYX 0:85b3fd62ea1a 1811 return HAL_ERROR;
NYX 0:85b3fd62ea1a 1812 }
NYX 0:85b3fd62ea1a 1813 else
NYX 0:85b3fd62ea1a 1814 {
NYX 0:85b3fd62ea1a 1815 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 1816 }
NYX 0:85b3fd62ea1a 1817 }
NYX 0:85b3fd62ea1a 1818
NYX 0:85b3fd62ea1a 1819 switch (Channel)
NYX 0:85b3fd62ea1a 1820 {
NYX 0:85b3fd62ea1a 1821 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 1822 {
NYX 0:85b3fd62ea1a 1823 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 1824 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 1825
NYX 0:85b3fd62ea1a 1826 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 1827 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 1828
NYX 0:85b3fd62ea1a 1829 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 1830 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
NYX 0:85b3fd62ea1a 1831
NYX 0:85b3fd62ea1a 1832 /* Enable the TIM Capture/Compare 1 DMA request */
NYX 0:85b3fd62ea1a 1833 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 1834 }
NYX 0:85b3fd62ea1a 1835 break;
NYX 0:85b3fd62ea1a 1836
NYX 0:85b3fd62ea1a 1837 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 1838 {
NYX 0:85b3fd62ea1a 1839 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 1840 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 1841
NYX 0:85b3fd62ea1a 1842 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 1843 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 1844
NYX 0:85b3fd62ea1a 1845 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 1846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
NYX 0:85b3fd62ea1a 1847
NYX 0:85b3fd62ea1a 1848 /* Enable the TIM Capture/Compare 2 DMA request */
NYX 0:85b3fd62ea1a 1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 1850 }
NYX 0:85b3fd62ea1a 1851 break;
NYX 0:85b3fd62ea1a 1852
NYX 0:85b3fd62ea1a 1853 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 1854 {
NYX 0:85b3fd62ea1a 1855 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 1856 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 1857
NYX 0:85b3fd62ea1a 1858 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 1859 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 1860
NYX 0:85b3fd62ea1a 1861 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 1862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
NYX 0:85b3fd62ea1a 1863
NYX 0:85b3fd62ea1a 1864 /* Enable the TIM Capture/Compare 3 DMA request */
NYX 0:85b3fd62ea1a 1865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
NYX 0:85b3fd62ea1a 1866 }
NYX 0:85b3fd62ea1a 1867 break;
NYX 0:85b3fd62ea1a 1868
NYX 0:85b3fd62ea1a 1869 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 1870 {
NYX 0:85b3fd62ea1a 1871 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 1872 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 1873
NYX 0:85b3fd62ea1a 1874 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 1875 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 1876
NYX 0:85b3fd62ea1a 1877 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 1878 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
NYX 0:85b3fd62ea1a 1879
NYX 0:85b3fd62ea1a 1880 /* Enable the TIM Capture/Compare 4 DMA request */
NYX 0:85b3fd62ea1a 1881 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
NYX 0:85b3fd62ea1a 1882 }
NYX 0:85b3fd62ea1a 1883 break;
NYX 0:85b3fd62ea1a 1884
NYX 0:85b3fd62ea1a 1885 default:
NYX 0:85b3fd62ea1a 1886 break;
NYX 0:85b3fd62ea1a 1887 }
NYX 0:85b3fd62ea1a 1888
NYX 0:85b3fd62ea1a 1889 /* Enable the Input Capture channel */
NYX 0:85b3fd62ea1a 1890 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 1891
NYX 0:85b3fd62ea1a 1892 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 1893 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 1894
NYX 0:85b3fd62ea1a 1895 /* Return function status */
NYX 0:85b3fd62ea1a 1896 return HAL_OK;
NYX 0:85b3fd62ea1a 1897 }
NYX 0:85b3fd62ea1a 1898
NYX 0:85b3fd62ea1a 1899 /**
NYX 0:85b3fd62ea1a 1900 * @brief Stops the TIM Input Capture measurement on in DMA mode.
NYX 0:85b3fd62ea1a 1901 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1902 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1903 * @param Channel: TIM Channels to be disabled.
NYX 0:85b3fd62ea1a 1904 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1905 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 1906 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 1907 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 1908 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 1909 * @retval HAL status
NYX 0:85b3fd62ea1a 1910 */
NYX 0:85b3fd62ea1a 1911 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 1912 {
NYX 0:85b3fd62ea1a 1913 /* Check the parameters */
NYX 0:85b3fd62ea1a 1914 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
NYX 0:85b3fd62ea1a 1915 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 1916
NYX 0:85b3fd62ea1a 1917 switch (Channel)
NYX 0:85b3fd62ea1a 1918 {
NYX 0:85b3fd62ea1a 1919 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 1920 {
NYX 0:85b3fd62ea1a 1921 /* Disable the TIM Capture/Compare 1 DMA request */
NYX 0:85b3fd62ea1a 1922 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 1923 }
NYX 0:85b3fd62ea1a 1924 break;
NYX 0:85b3fd62ea1a 1925
NYX 0:85b3fd62ea1a 1926 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 1927 {
NYX 0:85b3fd62ea1a 1928 /* Disable the TIM Capture/Compare 2 DMA request */
NYX 0:85b3fd62ea1a 1929 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 1930 }
NYX 0:85b3fd62ea1a 1931 break;
NYX 0:85b3fd62ea1a 1932
NYX 0:85b3fd62ea1a 1933 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 1934 {
NYX 0:85b3fd62ea1a 1935 /* Disable the TIM Capture/Compare 3 DMA request */
NYX 0:85b3fd62ea1a 1936 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
NYX 0:85b3fd62ea1a 1937 }
NYX 0:85b3fd62ea1a 1938 break;
NYX 0:85b3fd62ea1a 1939
NYX 0:85b3fd62ea1a 1940 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 1941 {
NYX 0:85b3fd62ea1a 1942 /* Disable the TIM Capture/Compare 4 DMA request */
NYX 0:85b3fd62ea1a 1943 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
NYX 0:85b3fd62ea1a 1944 }
NYX 0:85b3fd62ea1a 1945 break;
NYX 0:85b3fd62ea1a 1946
NYX 0:85b3fd62ea1a 1947 default:
NYX 0:85b3fd62ea1a 1948 break;
NYX 0:85b3fd62ea1a 1949 }
NYX 0:85b3fd62ea1a 1950
NYX 0:85b3fd62ea1a 1951 /* Disable the Input Capture channel */
NYX 0:85b3fd62ea1a 1952 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 1953
NYX 0:85b3fd62ea1a 1954 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 1955 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 1956
NYX 0:85b3fd62ea1a 1957 /* Change the htim state */
NYX 0:85b3fd62ea1a 1958 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 1959
NYX 0:85b3fd62ea1a 1960 /* Return function status */
NYX 0:85b3fd62ea1a 1961 return HAL_OK;
NYX 0:85b3fd62ea1a 1962 }
NYX 0:85b3fd62ea1a 1963 /**
NYX 0:85b3fd62ea1a 1964 * @}
NYX 0:85b3fd62ea1a 1965 */
NYX 0:85b3fd62ea1a 1966
NYX 0:85b3fd62ea1a 1967 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
NYX 0:85b3fd62ea1a 1968 * @brief Time One Pulse functions
NYX 0:85b3fd62ea1a 1969 *
NYX 0:85b3fd62ea1a 1970 @verbatim
NYX 0:85b3fd62ea1a 1971 ==============================================================================
NYX 0:85b3fd62ea1a 1972 ##### Time One Pulse functions #####
NYX 0:85b3fd62ea1a 1973 ==============================================================================
NYX 0:85b3fd62ea1a 1974 [..]
NYX 0:85b3fd62ea1a 1975 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 1976 (+) Initialize and configure the TIM One Pulse.
NYX 0:85b3fd62ea1a 1977 (+) De-initialize the TIM One Pulse.
NYX 0:85b3fd62ea1a 1978 (+) Start the Time One Pulse.
NYX 0:85b3fd62ea1a 1979 (+) Stop the Time One Pulse.
NYX 0:85b3fd62ea1a 1980 (+) Start the Time One Pulse and enable interrupt.
NYX 0:85b3fd62ea1a 1981 (+) Stop the Time One Pulse and disable interrupt.
NYX 0:85b3fd62ea1a 1982 (+) Start the Time One Pulse and enable DMA transfer.
NYX 0:85b3fd62ea1a 1983 (+) Stop the Time One Pulse and disable DMA transfer.
NYX 0:85b3fd62ea1a 1984
NYX 0:85b3fd62ea1a 1985 @endverbatim
NYX 0:85b3fd62ea1a 1986 * @{
NYX 0:85b3fd62ea1a 1987 */
NYX 0:85b3fd62ea1a 1988 /**
NYX 0:85b3fd62ea1a 1989 * @brief Initializes the TIM One Pulse Time Base according to the specified
NYX 0:85b3fd62ea1a 1990 * parameters in the TIM_HandleTypeDef and create the associated handle.
NYX 0:85b3fd62ea1a 1991 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 1992 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 1993 * @param OnePulseMode: Select the One pulse mode.
NYX 0:85b3fd62ea1a 1994 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 1995 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
NYX 0:85b3fd62ea1a 1996 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
NYX 0:85b3fd62ea1a 1997 * @retval HAL status
NYX 0:85b3fd62ea1a 1998 */
NYX 0:85b3fd62ea1a 1999 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
NYX 0:85b3fd62ea1a 2000 {
NYX 0:85b3fd62ea1a 2001 /* Check the TIM handle allocation */
NYX 0:85b3fd62ea1a 2002 if(htim == NULL)
NYX 0:85b3fd62ea1a 2003 {
NYX 0:85b3fd62ea1a 2004 return HAL_ERROR;
NYX 0:85b3fd62ea1a 2005 }
NYX 0:85b3fd62ea1a 2006
NYX 0:85b3fd62ea1a 2007 /* Check the parameters */
NYX 0:85b3fd62ea1a 2008 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2009 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
NYX 0:85b3fd62ea1a 2010 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
NYX 0:85b3fd62ea1a 2011 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
NYX 0:85b3fd62ea1a 2012
NYX 0:85b3fd62ea1a 2013 if(htim->State == HAL_TIM_STATE_RESET)
NYX 0:85b3fd62ea1a 2014 {
NYX 0:85b3fd62ea1a 2015 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 2016 htim->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 2017 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
NYX 0:85b3fd62ea1a 2018 HAL_TIM_OnePulse_MspInit(htim);
NYX 0:85b3fd62ea1a 2019 }
NYX 0:85b3fd62ea1a 2020
NYX 0:85b3fd62ea1a 2021 /* Set the TIM state */
NYX 0:85b3fd62ea1a 2022 htim->State= HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 2023
NYX 0:85b3fd62ea1a 2024 /* Configure the Time base in the One Pulse Mode */
NYX 0:85b3fd62ea1a 2025 TIM_Base_SetConfig(htim->Instance, &htim->Init);
NYX 0:85b3fd62ea1a 2026
NYX 0:85b3fd62ea1a 2027 /* Reset the OPM Bit */
NYX 0:85b3fd62ea1a 2028 htim->Instance->CR1 &= ~TIM_CR1_OPM;
NYX 0:85b3fd62ea1a 2029
NYX 0:85b3fd62ea1a 2030 /* Configure the OPM Mode */
NYX 0:85b3fd62ea1a 2031 htim->Instance->CR1 |= OnePulseMode;
NYX 0:85b3fd62ea1a 2032
NYX 0:85b3fd62ea1a 2033 /* Initialize the TIM state*/
NYX 0:85b3fd62ea1a 2034 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 2035
NYX 0:85b3fd62ea1a 2036 return HAL_OK;
NYX 0:85b3fd62ea1a 2037 }
NYX 0:85b3fd62ea1a 2038
NYX 0:85b3fd62ea1a 2039 /**
NYX 0:85b3fd62ea1a 2040 * @brief DeInitializes the TIM One Pulse
NYX 0:85b3fd62ea1a 2041 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2042 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2043 * @retval HAL status
NYX 0:85b3fd62ea1a 2044 */
NYX 0:85b3fd62ea1a 2045 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 2046 {
NYX 0:85b3fd62ea1a 2047 /* Check the parameters */
NYX 0:85b3fd62ea1a 2048 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2049
NYX 0:85b3fd62ea1a 2050 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 2051
NYX 0:85b3fd62ea1a 2052 /* Disable the TIM Peripheral Clock */
NYX 0:85b3fd62ea1a 2053 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 2054
NYX 0:85b3fd62ea1a 2055 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
NYX 0:85b3fd62ea1a 2056 HAL_TIM_OnePulse_MspDeInit(htim);
NYX 0:85b3fd62ea1a 2057
NYX 0:85b3fd62ea1a 2058 /* Change TIM state */
NYX 0:85b3fd62ea1a 2059 htim->State = HAL_TIM_STATE_RESET;
NYX 0:85b3fd62ea1a 2060
NYX 0:85b3fd62ea1a 2061 /* Release Lock */
NYX 0:85b3fd62ea1a 2062 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 2063
NYX 0:85b3fd62ea1a 2064 return HAL_OK;
NYX 0:85b3fd62ea1a 2065 }
NYX 0:85b3fd62ea1a 2066
NYX 0:85b3fd62ea1a 2067 /**
NYX 0:85b3fd62ea1a 2068 * @brief Initializes the TIM One Pulse MSP.
NYX 0:85b3fd62ea1a 2069 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2070 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2071 * @retval None
NYX 0:85b3fd62ea1a 2072 */
NYX 0:85b3fd62ea1a 2073 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 2074 {
NYX 0:85b3fd62ea1a 2075 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 2076 UNUSED(htim);
NYX 0:85b3fd62ea1a 2077 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 2078 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 2079 */
NYX 0:85b3fd62ea1a 2080 }
NYX 0:85b3fd62ea1a 2081
NYX 0:85b3fd62ea1a 2082 /**
NYX 0:85b3fd62ea1a 2083 * @brief DeInitializes TIM One Pulse MSP.
NYX 0:85b3fd62ea1a 2084 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2085 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2086 * @retval None
NYX 0:85b3fd62ea1a 2087 */
NYX 0:85b3fd62ea1a 2088 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 2089 {
NYX 0:85b3fd62ea1a 2090 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 2091 UNUSED(htim);
NYX 0:85b3fd62ea1a 2092 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 2093 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 2094 */
NYX 0:85b3fd62ea1a 2095 }
NYX 0:85b3fd62ea1a 2096
NYX 0:85b3fd62ea1a 2097 /**
NYX 0:85b3fd62ea1a 2098 * @brief Starts the TIM One Pulse signal generation.
NYX 0:85b3fd62ea1a 2099 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2100 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2101 * @param OutputChannel : TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 2102 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2103 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2104 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2105 * @retval HAL status
NYX 0:85b3fd62ea1a 2106 */
NYX 0:85b3fd62ea1a 2107 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
NYX 0:85b3fd62ea1a 2108 {
NYX 0:85b3fd62ea1a 2109 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 2110 UNUSED(OutputChannel);
NYX 0:85b3fd62ea1a 2111
NYX 0:85b3fd62ea1a 2112 /* Enable the Capture compare and the Input Capture channels
NYX 0:85b3fd62ea1a 2113 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
NYX 0:85b3fd62ea1a 2114 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
NYX 0:85b3fd62ea1a 2115 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
NYX 0:85b3fd62ea1a 2116 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
NYX 0:85b3fd62ea1a 2117
NYX 0:85b3fd62ea1a 2118 No need to enable the counter, it's enabled automatically by hardware
NYX 0:85b3fd62ea1a 2119 (the counter starts in response to a stimulus and generate a pulse */
NYX 0:85b3fd62ea1a 2120
NYX 0:85b3fd62ea1a 2121 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2122 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2123
NYX 0:85b3fd62ea1a 2124 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 2125 {
NYX 0:85b3fd62ea1a 2126 /* Enable the main output */
NYX 0:85b3fd62ea1a 2127 __HAL_TIM_MOE_ENABLE(htim);
NYX 0:85b3fd62ea1a 2128 }
NYX 0:85b3fd62ea1a 2129
NYX 0:85b3fd62ea1a 2130 /* Return function status */
NYX 0:85b3fd62ea1a 2131 return HAL_OK;
NYX 0:85b3fd62ea1a 2132 }
NYX 0:85b3fd62ea1a 2133
NYX 0:85b3fd62ea1a 2134 /**
NYX 0:85b3fd62ea1a 2135 * @brief Stops the TIM One Pulse signal generation.
NYX 0:85b3fd62ea1a 2136 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2137 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2138 * @param OutputChannel : TIM Channels to be disable.
NYX 0:85b3fd62ea1a 2139 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2140 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2141 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2142 * @retval HAL status
NYX 0:85b3fd62ea1a 2143 */
NYX 0:85b3fd62ea1a 2144 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
NYX 0:85b3fd62ea1a 2145 {
NYX 0:85b3fd62ea1a 2146 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 2147 UNUSED(OutputChannel);
NYX 0:85b3fd62ea1a 2148
NYX 0:85b3fd62ea1a 2149 /* Disable the Capture compare and the Input Capture channels
NYX 0:85b3fd62ea1a 2150 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
NYX 0:85b3fd62ea1a 2151 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
NYX 0:85b3fd62ea1a 2152 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
NYX 0:85b3fd62ea1a 2153 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
NYX 0:85b3fd62ea1a 2154
NYX 0:85b3fd62ea1a 2155 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2156 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2157
NYX 0:85b3fd62ea1a 2158 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 2159 {
NYX 0:85b3fd62ea1a 2160 /* Disable the Main Output */
NYX 0:85b3fd62ea1a 2161 __HAL_TIM_MOE_DISABLE(htim);
NYX 0:85b3fd62ea1a 2162 }
NYX 0:85b3fd62ea1a 2163
NYX 0:85b3fd62ea1a 2164 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 2165 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 2166
NYX 0:85b3fd62ea1a 2167 /* Return function status */
NYX 0:85b3fd62ea1a 2168 return HAL_OK;
NYX 0:85b3fd62ea1a 2169 }
NYX 0:85b3fd62ea1a 2170
NYX 0:85b3fd62ea1a 2171 /**
NYX 0:85b3fd62ea1a 2172 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
NYX 0:85b3fd62ea1a 2173 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2174 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2175 * @param OutputChannel : TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 2176 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2177 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2178 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2179 * @retval HAL status
NYX 0:85b3fd62ea1a 2180 */
NYX 0:85b3fd62ea1a 2181 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
NYX 0:85b3fd62ea1a 2182 {
NYX 0:85b3fd62ea1a 2183 /* Enable the Capture compare and the Input Capture channels
NYX 0:85b3fd62ea1a 2184 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
NYX 0:85b3fd62ea1a 2185 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
NYX 0:85b3fd62ea1a 2186 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
NYX 0:85b3fd62ea1a 2187 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
NYX 0:85b3fd62ea1a 2188
NYX 0:85b3fd62ea1a 2189 No need to enable the counter, it's enabled automatically by hardware
NYX 0:85b3fd62ea1a 2190 (the counter starts in response to a stimulus and generate a pulse */
NYX 0:85b3fd62ea1a 2191
NYX 0:85b3fd62ea1a 2192 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 2193 UNUSED(OutputChannel);
NYX 0:85b3fd62ea1a 2194
NYX 0:85b3fd62ea1a 2195 /* Enable the TIM Capture/Compare 1 interrupt */
NYX 0:85b3fd62ea1a 2196 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 2197
NYX 0:85b3fd62ea1a 2198 /* Enable the TIM Capture/Compare 2 interrupt */
NYX 0:85b3fd62ea1a 2199 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 2200
NYX 0:85b3fd62ea1a 2201 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2202 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2203
NYX 0:85b3fd62ea1a 2204 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 2205 {
NYX 0:85b3fd62ea1a 2206 /* Enable the main output */
NYX 0:85b3fd62ea1a 2207 __HAL_TIM_MOE_ENABLE(htim);
NYX 0:85b3fd62ea1a 2208 }
NYX 0:85b3fd62ea1a 2209
NYX 0:85b3fd62ea1a 2210 /* Return function status */
NYX 0:85b3fd62ea1a 2211 return HAL_OK;
NYX 0:85b3fd62ea1a 2212 }
NYX 0:85b3fd62ea1a 2213
NYX 0:85b3fd62ea1a 2214 /**
NYX 0:85b3fd62ea1a 2215 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
NYX 0:85b3fd62ea1a 2216 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2217 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2218 * @param OutputChannel : TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 2219 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2220 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2221 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2222 * @retval HAL status
NYX 0:85b3fd62ea1a 2223 */
NYX 0:85b3fd62ea1a 2224 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
NYX 0:85b3fd62ea1a 2225 {
NYX 0:85b3fd62ea1a 2226 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 2227 UNUSED(OutputChannel);
NYX 0:85b3fd62ea1a 2228
NYX 0:85b3fd62ea1a 2229 /* Disable the TIM Capture/Compare 1 interrupt */
NYX 0:85b3fd62ea1a 2230 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 2231
NYX 0:85b3fd62ea1a 2232 /* Disable the TIM Capture/Compare 2 interrupt */
NYX 0:85b3fd62ea1a 2233 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 2234
NYX 0:85b3fd62ea1a 2235 /* Disable the Capture compare and the Input Capture channels
NYX 0:85b3fd62ea1a 2236 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
NYX 0:85b3fd62ea1a 2237 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
NYX 0:85b3fd62ea1a 2238 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
NYX 0:85b3fd62ea1a 2239 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
NYX 0:85b3fd62ea1a 2240 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2241 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2242
NYX 0:85b3fd62ea1a 2243 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
NYX 0:85b3fd62ea1a 2244 {
NYX 0:85b3fd62ea1a 2245 /* Disable the Main Output */
NYX 0:85b3fd62ea1a 2246 __HAL_TIM_MOE_DISABLE(htim);
NYX 0:85b3fd62ea1a 2247 }
NYX 0:85b3fd62ea1a 2248
NYX 0:85b3fd62ea1a 2249 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 2250 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 2251
NYX 0:85b3fd62ea1a 2252 /* Return function status */
NYX 0:85b3fd62ea1a 2253 return HAL_OK;
NYX 0:85b3fd62ea1a 2254 }
NYX 0:85b3fd62ea1a 2255 /**
NYX 0:85b3fd62ea1a 2256 * @}
NYX 0:85b3fd62ea1a 2257 */
NYX 0:85b3fd62ea1a 2258
NYX 0:85b3fd62ea1a 2259 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
NYX 0:85b3fd62ea1a 2260 * @brief Time Encoder functions
NYX 0:85b3fd62ea1a 2261 *
NYX 0:85b3fd62ea1a 2262 @verbatim
NYX 0:85b3fd62ea1a 2263 ==============================================================================
NYX 0:85b3fd62ea1a 2264 ##### Time Encoder functions #####
NYX 0:85b3fd62ea1a 2265 ==============================================================================
NYX 0:85b3fd62ea1a 2266 [..]
NYX 0:85b3fd62ea1a 2267 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 2268 (+) Initialize and configure the TIM Encoder.
NYX 0:85b3fd62ea1a 2269 (+) De-initialize the TIM Encoder.
NYX 0:85b3fd62ea1a 2270 (+) Start the Time Encoder.
NYX 0:85b3fd62ea1a 2271 (+) Stop the Time Encoder.
NYX 0:85b3fd62ea1a 2272 (+) Start the Time Encoder and enable interrupt.
NYX 0:85b3fd62ea1a 2273 (+) Stop the Time Encoder and disable interrupt.
NYX 0:85b3fd62ea1a 2274 (+) Start the Time Encoder and enable DMA transfer.
NYX 0:85b3fd62ea1a 2275 (+) Stop the Time Encoder and disable DMA transfer.
NYX 0:85b3fd62ea1a 2276
NYX 0:85b3fd62ea1a 2277 @endverbatim
NYX 0:85b3fd62ea1a 2278 * @{
NYX 0:85b3fd62ea1a 2279 */
NYX 0:85b3fd62ea1a 2280 /**
NYX 0:85b3fd62ea1a 2281 * @brief Initializes the TIM Encoder Interface and create the associated handle.
NYX 0:85b3fd62ea1a 2282 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2283 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2284 * @param sConfig: TIM Encoder Interface configuration structure
NYX 0:85b3fd62ea1a 2285 * @retval HAL status
NYX 0:85b3fd62ea1a 2286 */
NYX 0:85b3fd62ea1a 2287 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
NYX 0:85b3fd62ea1a 2288 {
NYX 0:85b3fd62ea1a 2289 uint32_t tmpsmcr = 0U;
NYX 0:85b3fd62ea1a 2290 uint32_t tmpccmr1 = 0U;
NYX 0:85b3fd62ea1a 2291 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 2292
NYX 0:85b3fd62ea1a 2293 /* Check the TIM handle allocation */
NYX 0:85b3fd62ea1a 2294 if(htim == NULL)
NYX 0:85b3fd62ea1a 2295 {
NYX 0:85b3fd62ea1a 2296 return HAL_ERROR;
NYX 0:85b3fd62ea1a 2297 }
NYX 0:85b3fd62ea1a 2298
NYX 0:85b3fd62ea1a 2299 /* Check the parameters */
NYX 0:85b3fd62ea1a 2300 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2301 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
NYX 0:85b3fd62ea1a 2302 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
NYX 0:85b3fd62ea1a 2303 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
NYX 0:85b3fd62ea1a 2304 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
NYX 0:85b3fd62ea1a 2305 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
NYX 0:85b3fd62ea1a 2306 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
NYX 0:85b3fd62ea1a 2307 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
NYX 0:85b3fd62ea1a 2308 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
NYX 0:85b3fd62ea1a 2309 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
NYX 0:85b3fd62ea1a 2310
NYX 0:85b3fd62ea1a 2311 if(htim->State == HAL_TIM_STATE_RESET)
NYX 0:85b3fd62ea1a 2312 {
NYX 0:85b3fd62ea1a 2313 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 2314 htim->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 2315 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
NYX 0:85b3fd62ea1a 2316 HAL_TIM_Encoder_MspInit(htim);
NYX 0:85b3fd62ea1a 2317 }
NYX 0:85b3fd62ea1a 2318
NYX 0:85b3fd62ea1a 2319 /* Set the TIM state */
NYX 0:85b3fd62ea1a 2320 htim->State= HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 2321
NYX 0:85b3fd62ea1a 2322 /* Reset the SMS bits */
NYX 0:85b3fd62ea1a 2323 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
NYX 0:85b3fd62ea1a 2324
NYX 0:85b3fd62ea1a 2325 /* Configure the Time base in the Encoder Mode */
NYX 0:85b3fd62ea1a 2326 TIM_Base_SetConfig(htim->Instance, &htim->Init);
NYX 0:85b3fd62ea1a 2327
NYX 0:85b3fd62ea1a 2328 /* Get the TIMx SMCR register value */
NYX 0:85b3fd62ea1a 2329 tmpsmcr = htim->Instance->SMCR;
NYX 0:85b3fd62ea1a 2330
NYX 0:85b3fd62ea1a 2331 /* Get the TIMx CCMR1 register value */
NYX 0:85b3fd62ea1a 2332 tmpccmr1 = htim->Instance->CCMR1;
NYX 0:85b3fd62ea1a 2333
NYX 0:85b3fd62ea1a 2334 /* Get the TIMx CCER register value */
NYX 0:85b3fd62ea1a 2335 tmpccer = htim->Instance->CCER;
NYX 0:85b3fd62ea1a 2336
NYX 0:85b3fd62ea1a 2337 /* Set the encoder Mode */
NYX 0:85b3fd62ea1a 2338 tmpsmcr |= sConfig->EncoderMode;
NYX 0:85b3fd62ea1a 2339
NYX 0:85b3fd62ea1a 2340 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
NYX 0:85b3fd62ea1a 2341 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
NYX 0:85b3fd62ea1a 2342 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
NYX 0:85b3fd62ea1a 2343
NYX 0:85b3fd62ea1a 2344 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
NYX 0:85b3fd62ea1a 2345 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
NYX 0:85b3fd62ea1a 2346 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
NYX 0:85b3fd62ea1a 2347 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
NYX 0:85b3fd62ea1a 2348 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
NYX 0:85b3fd62ea1a 2349
NYX 0:85b3fd62ea1a 2350 /* Set the TI1 and the TI2 Polarities */
NYX 0:85b3fd62ea1a 2351 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
NYX 0:85b3fd62ea1a 2352 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
NYX 0:85b3fd62ea1a 2353 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
NYX 0:85b3fd62ea1a 2354
NYX 0:85b3fd62ea1a 2355 /* Write to TIMx SMCR */
NYX 0:85b3fd62ea1a 2356 htim->Instance->SMCR = tmpsmcr;
NYX 0:85b3fd62ea1a 2357
NYX 0:85b3fd62ea1a 2358 /* Write to TIMx CCMR1 */
NYX 0:85b3fd62ea1a 2359 htim->Instance->CCMR1 = tmpccmr1;
NYX 0:85b3fd62ea1a 2360
NYX 0:85b3fd62ea1a 2361 /* Write to TIMx CCER */
NYX 0:85b3fd62ea1a 2362 htim->Instance->CCER = tmpccer;
NYX 0:85b3fd62ea1a 2363
NYX 0:85b3fd62ea1a 2364 /* Initialize the TIM state*/
NYX 0:85b3fd62ea1a 2365 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 2366
NYX 0:85b3fd62ea1a 2367 return HAL_OK;
NYX 0:85b3fd62ea1a 2368 }
NYX 0:85b3fd62ea1a 2369
NYX 0:85b3fd62ea1a 2370 /**
NYX 0:85b3fd62ea1a 2371 * @brief DeInitializes the TIM Encoder interface
NYX 0:85b3fd62ea1a 2372 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2373 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2374 * @retval HAL status
NYX 0:85b3fd62ea1a 2375 */
NYX 0:85b3fd62ea1a 2376 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 2377 {
NYX 0:85b3fd62ea1a 2378 /* Check the parameters */
NYX 0:85b3fd62ea1a 2379 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2380
NYX 0:85b3fd62ea1a 2381 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 2382
NYX 0:85b3fd62ea1a 2383 /* Disable the TIM Peripheral Clock */
NYX 0:85b3fd62ea1a 2384 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 2385
NYX 0:85b3fd62ea1a 2386 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
NYX 0:85b3fd62ea1a 2387 HAL_TIM_Encoder_MspDeInit(htim);
NYX 0:85b3fd62ea1a 2388
NYX 0:85b3fd62ea1a 2389 /* Change TIM state */
NYX 0:85b3fd62ea1a 2390 htim->State = HAL_TIM_STATE_RESET;
NYX 0:85b3fd62ea1a 2391
NYX 0:85b3fd62ea1a 2392 /* Release Lock */
NYX 0:85b3fd62ea1a 2393 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 2394
NYX 0:85b3fd62ea1a 2395 return HAL_OK;
NYX 0:85b3fd62ea1a 2396 }
NYX 0:85b3fd62ea1a 2397
NYX 0:85b3fd62ea1a 2398 /**
NYX 0:85b3fd62ea1a 2399 * @brief Initializes the TIM Encoder Interface MSP.
NYX 0:85b3fd62ea1a 2400 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2401 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2402 * @retval None
NYX 0:85b3fd62ea1a 2403 */
NYX 0:85b3fd62ea1a 2404 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 2405 {
NYX 0:85b3fd62ea1a 2406 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 2407 UNUSED(htim);
NYX 0:85b3fd62ea1a 2408 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 2409 the HAL_TIM_Encoder_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 2410 */
NYX 0:85b3fd62ea1a 2411 }
NYX 0:85b3fd62ea1a 2412
NYX 0:85b3fd62ea1a 2413 /**
NYX 0:85b3fd62ea1a 2414 * @brief DeInitializes TIM Encoder Interface MSP.
NYX 0:85b3fd62ea1a 2415 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2416 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2417 * @retval None
NYX 0:85b3fd62ea1a 2418 */
NYX 0:85b3fd62ea1a 2419 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 2420 {
NYX 0:85b3fd62ea1a 2421 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 2422 UNUSED(htim);
NYX 0:85b3fd62ea1a 2423 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 2424 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 2425 */
NYX 0:85b3fd62ea1a 2426 }
NYX 0:85b3fd62ea1a 2427
NYX 0:85b3fd62ea1a 2428 /**
NYX 0:85b3fd62ea1a 2429 * @brief Starts the TIM Encoder Interface.
NYX 0:85b3fd62ea1a 2430 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2431 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2432 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 2433 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2434 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2435 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2436 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
NYX 0:85b3fd62ea1a 2437 * @retval HAL status
NYX 0:85b3fd62ea1a 2438 */
NYX 0:85b3fd62ea1a 2439 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 2440 {
NYX 0:85b3fd62ea1a 2441 /* Check the parameters */
NYX 0:85b3fd62ea1a 2442 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2443
NYX 0:85b3fd62ea1a 2444 /* Enable the encoder interface channels */
NYX 0:85b3fd62ea1a 2445 switch (Channel)
NYX 0:85b3fd62ea1a 2446 {
NYX 0:85b3fd62ea1a 2447 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 2448 {
NYX 0:85b3fd62ea1a 2449 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2450 break;
NYX 0:85b3fd62ea1a 2451 }
NYX 0:85b3fd62ea1a 2452 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 2453 {
NYX 0:85b3fd62ea1a 2454 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2455 break;
NYX 0:85b3fd62ea1a 2456 }
NYX 0:85b3fd62ea1a 2457 default :
NYX 0:85b3fd62ea1a 2458 {
NYX 0:85b3fd62ea1a 2459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2460 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2461 break;
NYX 0:85b3fd62ea1a 2462 }
NYX 0:85b3fd62ea1a 2463 }
NYX 0:85b3fd62ea1a 2464 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 2465 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 2466
NYX 0:85b3fd62ea1a 2467 /* Return function status */
NYX 0:85b3fd62ea1a 2468 return HAL_OK;
NYX 0:85b3fd62ea1a 2469 }
NYX 0:85b3fd62ea1a 2470
NYX 0:85b3fd62ea1a 2471 /**
NYX 0:85b3fd62ea1a 2472 * @brief Stops the TIM Encoder Interface.
NYX 0:85b3fd62ea1a 2473 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2474 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2475 * @param Channel: TIM Channels to be disabled.
NYX 0:85b3fd62ea1a 2476 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2477 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2478 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2479 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
NYX 0:85b3fd62ea1a 2480 * @retval HAL status
NYX 0:85b3fd62ea1a 2481 */
NYX 0:85b3fd62ea1a 2482 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 2483 {
NYX 0:85b3fd62ea1a 2484 /* Check the parameters */
NYX 0:85b3fd62ea1a 2485 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2486
NYX 0:85b3fd62ea1a 2487 /* Disable the Input Capture channels 1 and 2
NYX 0:85b3fd62ea1a 2488 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
NYX 0:85b3fd62ea1a 2489 switch (Channel)
NYX 0:85b3fd62ea1a 2490 {
NYX 0:85b3fd62ea1a 2491 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 2492 {
NYX 0:85b3fd62ea1a 2493 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2494 break;
NYX 0:85b3fd62ea1a 2495 }
NYX 0:85b3fd62ea1a 2496 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 2497 {
NYX 0:85b3fd62ea1a 2498 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2499 break;
NYX 0:85b3fd62ea1a 2500 }
NYX 0:85b3fd62ea1a 2501 default :
NYX 0:85b3fd62ea1a 2502 {
NYX 0:85b3fd62ea1a 2503 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2504 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2505 break;
NYX 0:85b3fd62ea1a 2506 }
NYX 0:85b3fd62ea1a 2507 }
NYX 0:85b3fd62ea1a 2508 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 2509 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 2510
NYX 0:85b3fd62ea1a 2511 /* Return function status */
NYX 0:85b3fd62ea1a 2512 return HAL_OK;
NYX 0:85b3fd62ea1a 2513 }
NYX 0:85b3fd62ea1a 2514
NYX 0:85b3fd62ea1a 2515 /**
NYX 0:85b3fd62ea1a 2516 * @brief Starts the TIM Encoder Interface in interrupt mode.
NYX 0:85b3fd62ea1a 2517 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2518 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2519 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 2520 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2521 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2522 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2523 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
NYX 0:85b3fd62ea1a 2524 * @retval HAL status
NYX 0:85b3fd62ea1a 2525 */
NYX 0:85b3fd62ea1a 2526 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 2527 {
NYX 0:85b3fd62ea1a 2528 /* Check the parameters */
NYX 0:85b3fd62ea1a 2529 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2530
NYX 0:85b3fd62ea1a 2531 /* Enable the encoder interface channels */
NYX 0:85b3fd62ea1a 2532 /* Enable the capture compare Interrupts 1 and/or 2 */
NYX 0:85b3fd62ea1a 2533 switch (Channel)
NYX 0:85b3fd62ea1a 2534 {
NYX 0:85b3fd62ea1a 2535 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 2536 {
NYX 0:85b3fd62ea1a 2537 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2538 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 2539 break;
NYX 0:85b3fd62ea1a 2540 }
NYX 0:85b3fd62ea1a 2541 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 2542 {
NYX 0:85b3fd62ea1a 2543 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2544 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 2545 break;
NYX 0:85b3fd62ea1a 2546 }
NYX 0:85b3fd62ea1a 2547 default :
NYX 0:85b3fd62ea1a 2548 {
NYX 0:85b3fd62ea1a 2549 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2550 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2551 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 2552 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 2553 break;
NYX 0:85b3fd62ea1a 2554 }
NYX 0:85b3fd62ea1a 2555 }
NYX 0:85b3fd62ea1a 2556
NYX 0:85b3fd62ea1a 2557 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 2558 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 2559
NYX 0:85b3fd62ea1a 2560 /* Return function status */
NYX 0:85b3fd62ea1a 2561 return HAL_OK;
NYX 0:85b3fd62ea1a 2562 }
NYX 0:85b3fd62ea1a 2563
NYX 0:85b3fd62ea1a 2564 /**
NYX 0:85b3fd62ea1a 2565 * @brief Stops the TIM Encoder Interface in interrupt mode.
NYX 0:85b3fd62ea1a 2566 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2567 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2568 * @param Channel: TIM Channels to be disabled.
NYX 0:85b3fd62ea1a 2569 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2570 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2571 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2572 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
NYX 0:85b3fd62ea1a 2573 * @retval HAL status
NYX 0:85b3fd62ea1a 2574 */
NYX 0:85b3fd62ea1a 2575 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 2576 {
NYX 0:85b3fd62ea1a 2577 /* Check the parameters */
NYX 0:85b3fd62ea1a 2578 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2579
NYX 0:85b3fd62ea1a 2580 /* Disable the Input Capture channels 1 and 2
NYX 0:85b3fd62ea1a 2581 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
NYX 0:85b3fd62ea1a 2582 if(Channel == TIM_CHANNEL_1)
NYX 0:85b3fd62ea1a 2583 {
NYX 0:85b3fd62ea1a 2584 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2585
NYX 0:85b3fd62ea1a 2586 /* Disable the capture compare Interrupts 1 */
NYX 0:85b3fd62ea1a 2587 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 2588 }
NYX 0:85b3fd62ea1a 2589 else if(Channel == TIM_CHANNEL_2)
NYX 0:85b3fd62ea1a 2590 {
NYX 0:85b3fd62ea1a 2591 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2592
NYX 0:85b3fd62ea1a 2593 /* Disable the capture compare Interrupts 2 */
NYX 0:85b3fd62ea1a 2594 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 2595 }
NYX 0:85b3fd62ea1a 2596 else
NYX 0:85b3fd62ea1a 2597 {
NYX 0:85b3fd62ea1a 2598 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2599 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2600
NYX 0:85b3fd62ea1a 2601 /* Disable the capture compare Interrupts 1 and 2 */
NYX 0:85b3fd62ea1a 2602 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 2603 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 2604 }
NYX 0:85b3fd62ea1a 2605
NYX 0:85b3fd62ea1a 2606 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 2607 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 2608
NYX 0:85b3fd62ea1a 2609 /* Change the htim state */
NYX 0:85b3fd62ea1a 2610 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 2611
NYX 0:85b3fd62ea1a 2612 /* Return function status */
NYX 0:85b3fd62ea1a 2613 return HAL_OK;
NYX 0:85b3fd62ea1a 2614 }
NYX 0:85b3fd62ea1a 2615
NYX 0:85b3fd62ea1a 2616 /**
NYX 0:85b3fd62ea1a 2617 * @brief Starts the TIM Encoder Interface in DMA mode.
NYX 0:85b3fd62ea1a 2618 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2619 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2620 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 2621 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2622 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2623 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2624 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
NYX 0:85b3fd62ea1a 2625 * @param pData1: The destination Buffer address for IC1.
NYX 0:85b3fd62ea1a 2626 * @param pData2: The destination Buffer address for IC2.
NYX 0:85b3fd62ea1a 2627 * @param Length: The length of data to be transferred from TIM peripheral to memory.
NYX 0:85b3fd62ea1a 2628 * @retval HAL status
NYX 0:85b3fd62ea1a 2629 */
NYX 0:85b3fd62ea1a 2630 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
NYX 0:85b3fd62ea1a 2631 {
NYX 0:85b3fd62ea1a 2632 /* Check the parameters */
NYX 0:85b3fd62ea1a 2633 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2634
NYX 0:85b3fd62ea1a 2635 if((htim->State == HAL_TIM_STATE_BUSY))
NYX 0:85b3fd62ea1a 2636 {
NYX 0:85b3fd62ea1a 2637 return HAL_BUSY;
NYX 0:85b3fd62ea1a 2638 }
NYX 0:85b3fd62ea1a 2639 else if((htim->State == HAL_TIM_STATE_READY))
NYX 0:85b3fd62ea1a 2640 {
NYX 0:85b3fd62ea1a 2641 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0))
NYX 0:85b3fd62ea1a 2642 {
NYX 0:85b3fd62ea1a 2643 return HAL_ERROR;
NYX 0:85b3fd62ea1a 2644 }
NYX 0:85b3fd62ea1a 2645 else
NYX 0:85b3fd62ea1a 2646 {
NYX 0:85b3fd62ea1a 2647 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 2648 }
NYX 0:85b3fd62ea1a 2649 }
NYX 0:85b3fd62ea1a 2650
NYX 0:85b3fd62ea1a 2651 switch (Channel)
NYX 0:85b3fd62ea1a 2652 {
NYX 0:85b3fd62ea1a 2653 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 2654 {
NYX 0:85b3fd62ea1a 2655 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 2656 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 2657
NYX 0:85b3fd62ea1a 2658 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 2659 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 2660
NYX 0:85b3fd62ea1a 2661 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 2662 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
NYX 0:85b3fd62ea1a 2663
NYX 0:85b3fd62ea1a 2664 /* Enable the TIM Input Capture DMA request */
NYX 0:85b3fd62ea1a 2665 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 2666
NYX 0:85b3fd62ea1a 2667 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 2668 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 2669
NYX 0:85b3fd62ea1a 2670 /* Enable the Capture compare channel */
NYX 0:85b3fd62ea1a 2671 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2672 }
NYX 0:85b3fd62ea1a 2673 break;
NYX 0:85b3fd62ea1a 2674
NYX 0:85b3fd62ea1a 2675 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 2676 {
NYX 0:85b3fd62ea1a 2677 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 2678 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 2679
NYX 0:85b3fd62ea1a 2680 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 2681 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
NYX 0:85b3fd62ea1a 2682 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 2683 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
NYX 0:85b3fd62ea1a 2684
NYX 0:85b3fd62ea1a 2685 /* Enable the TIM Input Capture DMA request */
NYX 0:85b3fd62ea1a 2686 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 2687
NYX 0:85b3fd62ea1a 2688 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 2689 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 2690
NYX 0:85b3fd62ea1a 2691 /* Enable the Capture compare channel */
NYX 0:85b3fd62ea1a 2692 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2693 }
NYX 0:85b3fd62ea1a 2694 break;
NYX 0:85b3fd62ea1a 2695
NYX 0:85b3fd62ea1a 2696 case TIM_CHANNEL_ALL:
NYX 0:85b3fd62ea1a 2697 {
NYX 0:85b3fd62ea1a 2698 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 2699 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 2700
NYX 0:85b3fd62ea1a 2701 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 2702 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 2703
NYX 0:85b3fd62ea1a 2704 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 2705 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
NYX 0:85b3fd62ea1a 2706
NYX 0:85b3fd62ea1a 2707 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 2708 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 2709
NYX 0:85b3fd62ea1a 2710 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 2711 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 2712
NYX 0:85b3fd62ea1a 2713 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 2714 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
NYX 0:85b3fd62ea1a 2715
NYX 0:85b3fd62ea1a 2716 /* Enable the Peripheral */
NYX 0:85b3fd62ea1a 2717 __HAL_TIM_ENABLE(htim);
NYX 0:85b3fd62ea1a 2718
NYX 0:85b3fd62ea1a 2719 /* Enable the Capture compare channel */
NYX 0:85b3fd62ea1a 2720 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2721 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
NYX 0:85b3fd62ea1a 2722
NYX 0:85b3fd62ea1a 2723 /* Enable the TIM Input Capture DMA request */
NYX 0:85b3fd62ea1a 2724 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 2725 /* Enable the TIM Input Capture DMA request */
NYX 0:85b3fd62ea1a 2726 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 2727 }
NYX 0:85b3fd62ea1a 2728 break;
NYX 0:85b3fd62ea1a 2729
NYX 0:85b3fd62ea1a 2730 default:
NYX 0:85b3fd62ea1a 2731 break;
NYX 0:85b3fd62ea1a 2732 }
NYX 0:85b3fd62ea1a 2733 /* Return function status */
NYX 0:85b3fd62ea1a 2734 return HAL_OK;
NYX 0:85b3fd62ea1a 2735 }
NYX 0:85b3fd62ea1a 2736
NYX 0:85b3fd62ea1a 2737 /**
NYX 0:85b3fd62ea1a 2738 * @brief Stops the TIM Encoder Interface in DMA mode.
NYX 0:85b3fd62ea1a 2739 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2740 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2741 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 2742 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2743 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2744 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2745 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
NYX 0:85b3fd62ea1a 2746 * @retval HAL status
NYX 0:85b3fd62ea1a 2747 */
NYX 0:85b3fd62ea1a 2748 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 2749 {
NYX 0:85b3fd62ea1a 2750 /* Check the parameters */
NYX 0:85b3fd62ea1a 2751 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2752
NYX 0:85b3fd62ea1a 2753 /* Disable the Input Capture channels 1 and 2
NYX 0:85b3fd62ea1a 2754 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
NYX 0:85b3fd62ea1a 2755 if(Channel == TIM_CHANNEL_1)
NYX 0:85b3fd62ea1a 2756 {
NYX 0:85b3fd62ea1a 2757 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2758
NYX 0:85b3fd62ea1a 2759 /* Disable the capture compare DMA Request 1 */
NYX 0:85b3fd62ea1a 2760 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 2761 }
NYX 0:85b3fd62ea1a 2762 else if(Channel == TIM_CHANNEL_2)
NYX 0:85b3fd62ea1a 2763 {
NYX 0:85b3fd62ea1a 2764 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2765
NYX 0:85b3fd62ea1a 2766 /* Disable the capture compare DMA Request 2 */
NYX 0:85b3fd62ea1a 2767 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 2768 }
NYX 0:85b3fd62ea1a 2769 else
NYX 0:85b3fd62ea1a 2770 {
NYX 0:85b3fd62ea1a 2771 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2772 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
NYX 0:85b3fd62ea1a 2773
NYX 0:85b3fd62ea1a 2774 /* Disable the capture compare DMA Request 1 and 2 */
NYX 0:85b3fd62ea1a 2775 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
NYX 0:85b3fd62ea1a 2776 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
NYX 0:85b3fd62ea1a 2777 }
NYX 0:85b3fd62ea1a 2778
NYX 0:85b3fd62ea1a 2779 /* Disable the Peripheral */
NYX 0:85b3fd62ea1a 2780 __HAL_TIM_DISABLE(htim);
NYX 0:85b3fd62ea1a 2781
NYX 0:85b3fd62ea1a 2782 /* Change the htim state */
NYX 0:85b3fd62ea1a 2783 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 2784
NYX 0:85b3fd62ea1a 2785 /* Return function status */
NYX 0:85b3fd62ea1a 2786 return HAL_OK;
NYX 0:85b3fd62ea1a 2787 }
NYX 0:85b3fd62ea1a 2788 /**
NYX 0:85b3fd62ea1a 2789 * @}
NYX 0:85b3fd62ea1a 2790 */
NYX 0:85b3fd62ea1a 2791
NYX 0:85b3fd62ea1a 2792 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
NYX 0:85b3fd62ea1a 2793 * @brief IRQ handler management
NYX 0:85b3fd62ea1a 2794 *
NYX 0:85b3fd62ea1a 2795 @verbatim
NYX 0:85b3fd62ea1a 2796 ==============================================================================
NYX 0:85b3fd62ea1a 2797 ##### IRQ handler management #####
NYX 0:85b3fd62ea1a 2798 ==============================================================================
NYX 0:85b3fd62ea1a 2799 [..]
NYX 0:85b3fd62ea1a 2800 This section provides Timer IRQ handler function.
NYX 0:85b3fd62ea1a 2801
NYX 0:85b3fd62ea1a 2802 @endverbatim
NYX 0:85b3fd62ea1a 2803 * @{
NYX 0:85b3fd62ea1a 2804 */
NYX 0:85b3fd62ea1a 2805 /**
NYX 0:85b3fd62ea1a 2806 * @brief This function handles TIM interrupts requests.
NYX 0:85b3fd62ea1a 2807 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2808 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2809 * @retval None
NYX 0:85b3fd62ea1a 2810 */
NYX 0:85b3fd62ea1a 2811 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 2812 {
NYX 0:85b3fd62ea1a 2813 /* Capture compare 1 event */
NYX 0:85b3fd62ea1a 2814 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
NYX 0:85b3fd62ea1a 2815 {
NYX 0:85b3fd62ea1a 2816 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
NYX 0:85b3fd62ea1a 2817 {
NYX 0:85b3fd62ea1a 2818 {
NYX 0:85b3fd62ea1a 2819 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
NYX 0:85b3fd62ea1a 2820 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
NYX 0:85b3fd62ea1a 2821
NYX 0:85b3fd62ea1a 2822 /* Input capture event */
NYX 0:85b3fd62ea1a 2823 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
NYX 0:85b3fd62ea1a 2824 {
NYX 0:85b3fd62ea1a 2825 HAL_TIM_IC_CaptureCallback(htim);
NYX 0:85b3fd62ea1a 2826 }
NYX 0:85b3fd62ea1a 2827 /* Output compare event */
NYX 0:85b3fd62ea1a 2828 else
NYX 0:85b3fd62ea1a 2829 {
NYX 0:85b3fd62ea1a 2830 HAL_TIM_OC_DelayElapsedCallback(htim);
NYX 0:85b3fd62ea1a 2831 HAL_TIM_PWM_PulseFinishedCallback(htim);
NYX 0:85b3fd62ea1a 2832 }
NYX 0:85b3fd62ea1a 2833 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
NYX 0:85b3fd62ea1a 2834 }
NYX 0:85b3fd62ea1a 2835 }
NYX 0:85b3fd62ea1a 2836 }
NYX 0:85b3fd62ea1a 2837 /* Capture compare 2 event */
NYX 0:85b3fd62ea1a 2838 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
NYX 0:85b3fd62ea1a 2839 {
NYX 0:85b3fd62ea1a 2840 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
NYX 0:85b3fd62ea1a 2841 {
NYX 0:85b3fd62ea1a 2842 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
NYX 0:85b3fd62ea1a 2843 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
NYX 0:85b3fd62ea1a 2844 /* Input capture event */
NYX 0:85b3fd62ea1a 2845 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
NYX 0:85b3fd62ea1a 2846 {
NYX 0:85b3fd62ea1a 2847 HAL_TIM_IC_CaptureCallback(htim);
NYX 0:85b3fd62ea1a 2848 }
NYX 0:85b3fd62ea1a 2849 /* Output compare event */
NYX 0:85b3fd62ea1a 2850 else
NYX 0:85b3fd62ea1a 2851 {
NYX 0:85b3fd62ea1a 2852 HAL_TIM_OC_DelayElapsedCallback(htim);
NYX 0:85b3fd62ea1a 2853 HAL_TIM_PWM_PulseFinishedCallback(htim);
NYX 0:85b3fd62ea1a 2854 }
NYX 0:85b3fd62ea1a 2855 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
NYX 0:85b3fd62ea1a 2856 }
NYX 0:85b3fd62ea1a 2857 }
NYX 0:85b3fd62ea1a 2858 /* Capture compare 3 event */
NYX 0:85b3fd62ea1a 2859 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
NYX 0:85b3fd62ea1a 2860 {
NYX 0:85b3fd62ea1a 2861 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
NYX 0:85b3fd62ea1a 2862 {
NYX 0:85b3fd62ea1a 2863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
NYX 0:85b3fd62ea1a 2864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
NYX 0:85b3fd62ea1a 2865 /* Input capture event */
NYX 0:85b3fd62ea1a 2866 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
NYX 0:85b3fd62ea1a 2867 {
NYX 0:85b3fd62ea1a 2868 HAL_TIM_IC_CaptureCallback(htim);
NYX 0:85b3fd62ea1a 2869 }
NYX 0:85b3fd62ea1a 2870 /* Output compare event */
NYX 0:85b3fd62ea1a 2871 else
NYX 0:85b3fd62ea1a 2872 {
NYX 0:85b3fd62ea1a 2873 HAL_TIM_OC_DelayElapsedCallback(htim);
NYX 0:85b3fd62ea1a 2874 HAL_TIM_PWM_PulseFinishedCallback(htim);
NYX 0:85b3fd62ea1a 2875 }
NYX 0:85b3fd62ea1a 2876 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
NYX 0:85b3fd62ea1a 2877 }
NYX 0:85b3fd62ea1a 2878 }
NYX 0:85b3fd62ea1a 2879 /* Capture compare 4 event */
NYX 0:85b3fd62ea1a 2880 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
NYX 0:85b3fd62ea1a 2881 {
NYX 0:85b3fd62ea1a 2882 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
NYX 0:85b3fd62ea1a 2883 {
NYX 0:85b3fd62ea1a 2884 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
NYX 0:85b3fd62ea1a 2885 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
NYX 0:85b3fd62ea1a 2886 /* Input capture event */
NYX 0:85b3fd62ea1a 2887 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
NYX 0:85b3fd62ea1a 2888 {
NYX 0:85b3fd62ea1a 2889 HAL_TIM_IC_CaptureCallback(htim);
NYX 0:85b3fd62ea1a 2890 }
NYX 0:85b3fd62ea1a 2891 /* Output compare event */
NYX 0:85b3fd62ea1a 2892 else
NYX 0:85b3fd62ea1a 2893 {
NYX 0:85b3fd62ea1a 2894 HAL_TIM_OC_DelayElapsedCallback(htim);
NYX 0:85b3fd62ea1a 2895 HAL_TIM_PWM_PulseFinishedCallback(htim);
NYX 0:85b3fd62ea1a 2896 }
NYX 0:85b3fd62ea1a 2897 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
NYX 0:85b3fd62ea1a 2898 }
NYX 0:85b3fd62ea1a 2899 }
NYX 0:85b3fd62ea1a 2900 /* TIM Update event */
NYX 0:85b3fd62ea1a 2901 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
NYX 0:85b3fd62ea1a 2902 {
NYX 0:85b3fd62ea1a 2903 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
NYX 0:85b3fd62ea1a 2904 {
NYX 0:85b3fd62ea1a 2905 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
NYX 0:85b3fd62ea1a 2906 HAL_TIM_PeriodElapsedCallback(htim);
NYX 0:85b3fd62ea1a 2907 }
NYX 0:85b3fd62ea1a 2908 }
NYX 0:85b3fd62ea1a 2909 /* TIM Break input event */
NYX 0:85b3fd62ea1a 2910 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
NYX 0:85b3fd62ea1a 2911 {
NYX 0:85b3fd62ea1a 2912 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
NYX 0:85b3fd62ea1a 2913 {
NYX 0:85b3fd62ea1a 2914 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
NYX 0:85b3fd62ea1a 2915 HAL_TIMEx_BreakCallback(htim);
NYX 0:85b3fd62ea1a 2916 }
NYX 0:85b3fd62ea1a 2917 }
NYX 0:85b3fd62ea1a 2918 /* TIM Trigger detection event */
NYX 0:85b3fd62ea1a 2919 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
NYX 0:85b3fd62ea1a 2920 {
NYX 0:85b3fd62ea1a 2921 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
NYX 0:85b3fd62ea1a 2922 {
NYX 0:85b3fd62ea1a 2923 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
NYX 0:85b3fd62ea1a 2924 HAL_TIM_TriggerCallback(htim);
NYX 0:85b3fd62ea1a 2925 }
NYX 0:85b3fd62ea1a 2926 }
NYX 0:85b3fd62ea1a 2927 /* TIM commutation event */
NYX 0:85b3fd62ea1a 2928 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
NYX 0:85b3fd62ea1a 2929 {
NYX 0:85b3fd62ea1a 2930 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
NYX 0:85b3fd62ea1a 2931 {
NYX 0:85b3fd62ea1a 2932 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
NYX 0:85b3fd62ea1a 2933 HAL_TIMEx_CommutationCallback(htim);
NYX 0:85b3fd62ea1a 2934 }
NYX 0:85b3fd62ea1a 2935 }
NYX 0:85b3fd62ea1a 2936 }
NYX 0:85b3fd62ea1a 2937 /**
NYX 0:85b3fd62ea1a 2938 * @}
NYX 0:85b3fd62ea1a 2939 */
NYX 0:85b3fd62ea1a 2940
NYX 0:85b3fd62ea1a 2941 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
NYX 0:85b3fd62ea1a 2942 * @brief Peripheral Control functions
NYX 0:85b3fd62ea1a 2943 *
NYX 0:85b3fd62ea1a 2944 @verbatim
NYX 0:85b3fd62ea1a 2945 ==============================================================================
NYX 0:85b3fd62ea1a 2946 ##### Peripheral Control functions #####
NYX 0:85b3fd62ea1a 2947 ==============================================================================
NYX 0:85b3fd62ea1a 2948 [..]
NYX 0:85b3fd62ea1a 2949 This section provides functions allowing to:
NYX 0:85b3fd62ea1a 2950 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
NYX 0:85b3fd62ea1a 2951 (+) Configure External Clock source.
NYX 0:85b3fd62ea1a 2952 (+) Configure Complementary channels, break features and dead time.
NYX 0:85b3fd62ea1a 2953 (+) Configure Master and the Slave synchronization.
NYX 0:85b3fd62ea1a 2954 (+) Configure the DMA Burst Mode.
NYX 0:85b3fd62ea1a 2955
NYX 0:85b3fd62ea1a 2956 @endverbatim
NYX 0:85b3fd62ea1a 2957 * @{
NYX 0:85b3fd62ea1a 2958 */
NYX 0:85b3fd62ea1a 2959
NYX 0:85b3fd62ea1a 2960 /**
NYX 0:85b3fd62ea1a 2961 * @brief Initializes the TIM Output Compare Channels according to the specified
NYX 0:85b3fd62ea1a 2962 * parameters in the TIM_OC_InitTypeDef.
NYX 0:85b3fd62ea1a 2963 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 2964 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 2965 * @param sConfig: TIM Output Compare configuration structure
NYX 0:85b3fd62ea1a 2966 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 2967 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 2968 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 2969 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 2970 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 2971 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 2972 * @retval HAL status
NYX 0:85b3fd62ea1a 2973 */
NYX 0:85b3fd62ea1a 2974 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
NYX 0:85b3fd62ea1a 2975 {
NYX 0:85b3fd62ea1a 2976 /* Check the parameters */
NYX 0:85b3fd62ea1a 2977 assert_param(IS_TIM_CHANNELS(Channel));
NYX 0:85b3fd62ea1a 2978 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
NYX 0:85b3fd62ea1a 2979 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
NYX 0:85b3fd62ea1a 2980
NYX 0:85b3fd62ea1a 2981 /* Check input state */
NYX 0:85b3fd62ea1a 2982 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 2983
NYX 0:85b3fd62ea1a 2984 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 2985
NYX 0:85b3fd62ea1a 2986 switch (Channel)
NYX 0:85b3fd62ea1a 2987 {
NYX 0:85b3fd62ea1a 2988 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 2989 {
NYX 0:85b3fd62ea1a 2990 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2991 /* Configure the TIM Channel 1 in Output Compare */
NYX 0:85b3fd62ea1a 2992 TIM_OC1_SetConfig(htim->Instance, sConfig);
NYX 0:85b3fd62ea1a 2993 }
NYX 0:85b3fd62ea1a 2994 break;
NYX 0:85b3fd62ea1a 2995
NYX 0:85b3fd62ea1a 2996 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 2997 {
NYX 0:85b3fd62ea1a 2998 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 2999 /* Configure the TIM Channel 2 in Output Compare */
NYX 0:85b3fd62ea1a 3000 TIM_OC2_SetConfig(htim->Instance, sConfig);
NYX 0:85b3fd62ea1a 3001 }
NYX 0:85b3fd62ea1a 3002 break;
NYX 0:85b3fd62ea1a 3003
NYX 0:85b3fd62ea1a 3004 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 3005 {
NYX 0:85b3fd62ea1a 3006 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3007 /* Configure the TIM Channel 3 in Output Compare */
NYX 0:85b3fd62ea1a 3008 TIM_OC3_SetConfig(htim->Instance, sConfig);
NYX 0:85b3fd62ea1a 3009 }
NYX 0:85b3fd62ea1a 3010 break;
NYX 0:85b3fd62ea1a 3011
NYX 0:85b3fd62ea1a 3012 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 3013 {
NYX 0:85b3fd62ea1a 3014 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3015 /* Configure the TIM Channel 4 in Output Compare */
NYX 0:85b3fd62ea1a 3016 TIM_OC4_SetConfig(htim->Instance, sConfig);
NYX 0:85b3fd62ea1a 3017 }
NYX 0:85b3fd62ea1a 3018 break;
NYX 0:85b3fd62ea1a 3019
NYX 0:85b3fd62ea1a 3020 default:
NYX 0:85b3fd62ea1a 3021 break;
NYX 0:85b3fd62ea1a 3022 }
NYX 0:85b3fd62ea1a 3023 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 3024
NYX 0:85b3fd62ea1a 3025 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 3026
NYX 0:85b3fd62ea1a 3027 return HAL_OK;
NYX 0:85b3fd62ea1a 3028 }
NYX 0:85b3fd62ea1a 3029
NYX 0:85b3fd62ea1a 3030 /**
NYX 0:85b3fd62ea1a 3031 * @brief Initializes the TIM Input Capture Channels according to the specified
NYX 0:85b3fd62ea1a 3032 * parameters in the TIM_IC_InitTypeDef.
NYX 0:85b3fd62ea1a 3033 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3034 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3035 * @param sConfig: TIM Input Capture configuration structure
NYX 0:85b3fd62ea1a 3036 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 3037 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 3038 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 3039 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 3040 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 3041 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 3042 * @retval HAL status
NYX 0:85b3fd62ea1a 3043 */
NYX 0:85b3fd62ea1a 3044 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
NYX 0:85b3fd62ea1a 3045 {
NYX 0:85b3fd62ea1a 3046 /* Check the parameters */
NYX 0:85b3fd62ea1a 3047 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3048 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
NYX 0:85b3fd62ea1a 3049 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
NYX 0:85b3fd62ea1a 3050 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
NYX 0:85b3fd62ea1a 3051 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
NYX 0:85b3fd62ea1a 3052
NYX 0:85b3fd62ea1a 3053 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 3054
NYX 0:85b3fd62ea1a 3055 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 3056
NYX 0:85b3fd62ea1a 3057 if (Channel == TIM_CHANNEL_1)
NYX 0:85b3fd62ea1a 3058 {
NYX 0:85b3fd62ea1a 3059 /* TI1 Configuration */
NYX 0:85b3fd62ea1a 3060 TIM_TI1_SetConfig(htim->Instance,
NYX 0:85b3fd62ea1a 3061 sConfig->ICPolarity,
NYX 0:85b3fd62ea1a 3062 sConfig->ICSelection,
NYX 0:85b3fd62ea1a 3063 sConfig->ICFilter);
NYX 0:85b3fd62ea1a 3064
NYX 0:85b3fd62ea1a 3065 /* Reset the IC1PSC Bits */
NYX 0:85b3fd62ea1a 3066 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
NYX 0:85b3fd62ea1a 3067
NYX 0:85b3fd62ea1a 3068 /* Set the IC1PSC value */
NYX 0:85b3fd62ea1a 3069 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
NYX 0:85b3fd62ea1a 3070 }
NYX 0:85b3fd62ea1a 3071 else if (Channel == TIM_CHANNEL_2)
NYX 0:85b3fd62ea1a 3072 {
NYX 0:85b3fd62ea1a 3073 /* TI2 Configuration */
NYX 0:85b3fd62ea1a 3074 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3075
NYX 0:85b3fd62ea1a 3076 TIM_TI2_SetConfig(htim->Instance,
NYX 0:85b3fd62ea1a 3077 sConfig->ICPolarity,
NYX 0:85b3fd62ea1a 3078 sConfig->ICSelection,
NYX 0:85b3fd62ea1a 3079 sConfig->ICFilter);
NYX 0:85b3fd62ea1a 3080
NYX 0:85b3fd62ea1a 3081 /* Reset the IC2PSC Bits */
NYX 0:85b3fd62ea1a 3082 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
NYX 0:85b3fd62ea1a 3083
NYX 0:85b3fd62ea1a 3084 /* Set the IC2PSC value */
NYX 0:85b3fd62ea1a 3085 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
NYX 0:85b3fd62ea1a 3086 }
NYX 0:85b3fd62ea1a 3087 else if (Channel == TIM_CHANNEL_3)
NYX 0:85b3fd62ea1a 3088 {
NYX 0:85b3fd62ea1a 3089 /* TI3 Configuration */
NYX 0:85b3fd62ea1a 3090 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3091
NYX 0:85b3fd62ea1a 3092 TIM_TI3_SetConfig(htim->Instance,
NYX 0:85b3fd62ea1a 3093 sConfig->ICPolarity,
NYX 0:85b3fd62ea1a 3094 sConfig->ICSelection,
NYX 0:85b3fd62ea1a 3095 sConfig->ICFilter);
NYX 0:85b3fd62ea1a 3096
NYX 0:85b3fd62ea1a 3097 /* Reset the IC3PSC Bits */
NYX 0:85b3fd62ea1a 3098 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
NYX 0:85b3fd62ea1a 3099
NYX 0:85b3fd62ea1a 3100 /* Set the IC3PSC value */
NYX 0:85b3fd62ea1a 3101 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
NYX 0:85b3fd62ea1a 3102 }
NYX 0:85b3fd62ea1a 3103 else
NYX 0:85b3fd62ea1a 3104 {
NYX 0:85b3fd62ea1a 3105 /* TI4 Configuration */
NYX 0:85b3fd62ea1a 3106 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3107
NYX 0:85b3fd62ea1a 3108 TIM_TI4_SetConfig(htim->Instance,
NYX 0:85b3fd62ea1a 3109 sConfig->ICPolarity,
NYX 0:85b3fd62ea1a 3110 sConfig->ICSelection,
NYX 0:85b3fd62ea1a 3111 sConfig->ICFilter);
NYX 0:85b3fd62ea1a 3112
NYX 0:85b3fd62ea1a 3113 /* Reset the IC4PSC Bits */
NYX 0:85b3fd62ea1a 3114 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
NYX 0:85b3fd62ea1a 3115
NYX 0:85b3fd62ea1a 3116 /* Set the IC4PSC value */
NYX 0:85b3fd62ea1a 3117 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
NYX 0:85b3fd62ea1a 3118 }
NYX 0:85b3fd62ea1a 3119
NYX 0:85b3fd62ea1a 3120 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 3121
NYX 0:85b3fd62ea1a 3122 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 3123
NYX 0:85b3fd62ea1a 3124 return HAL_OK;
NYX 0:85b3fd62ea1a 3125 }
NYX 0:85b3fd62ea1a 3126
NYX 0:85b3fd62ea1a 3127 /**
NYX 0:85b3fd62ea1a 3128 * @brief Initializes the TIM PWM channels according to the specified
NYX 0:85b3fd62ea1a 3129 * parameters in the TIM_OC_InitTypeDef.
NYX 0:85b3fd62ea1a 3130 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3131 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3132 * @param sConfig: TIM PWM configuration structure
NYX 0:85b3fd62ea1a 3133 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 3134 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 3135 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 3136 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 3137 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 3138 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 3139 * @retval HAL status
NYX 0:85b3fd62ea1a 3140 */
NYX 0:85b3fd62ea1a 3141 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
NYX 0:85b3fd62ea1a 3142 {
NYX 0:85b3fd62ea1a 3143 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 3144
NYX 0:85b3fd62ea1a 3145 /* Check the parameters */
NYX 0:85b3fd62ea1a 3146 assert_param(IS_TIM_CHANNELS(Channel));
NYX 0:85b3fd62ea1a 3147 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
NYX 0:85b3fd62ea1a 3148 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
NYX 0:85b3fd62ea1a 3149 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
NYX 0:85b3fd62ea1a 3150
NYX 0:85b3fd62ea1a 3151 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 3152
NYX 0:85b3fd62ea1a 3153 switch (Channel)
NYX 0:85b3fd62ea1a 3154 {
NYX 0:85b3fd62ea1a 3155 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 3156 {
NYX 0:85b3fd62ea1a 3157 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3158 /* Configure the Channel 1 in PWM mode */
NYX 0:85b3fd62ea1a 3159 TIM_OC1_SetConfig(htim->Instance, sConfig);
NYX 0:85b3fd62ea1a 3160
NYX 0:85b3fd62ea1a 3161 /* Set the Preload enable bit for channel1 */
NYX 0:85b3fd62ea1a 3162 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
NYX 0:85b3fd62ea1a 3163
NYX 0:85b3fd62ea1a 3164 /* Configure the Output Fast mode */
NYX 0:85b3fd62ea1a 3165 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
NYX 0:85b3fd62ea1a 3166 htim->Instance->CCMR1 |= sConfig->OCFastMode;
NYX 0:85b3fd62ea1a 3167 }
NYX 0:85b3fd62ea1a 3168 break;
NYX 0:85b3fd62ea1a 3169
NYX 0:85b3fd62ea1a 3170 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 3171 {
NYX 0:85b3fd62ea1a 3172 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3173 /* Configure the Channel 2 in PWM mode */
NYX 0:85b3fd62ea1a 3174 TIM_OC2_SetConfig(htim->Instance, sConfig);
NYX 0:85b3fd62ea1a 3175
NYX 0:85b3fd62ea1a 3176 /* Set the Preload enable bit for channel2 */
NYX 0:85b3fd62ea1a 3177 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
NYX 0:85b3fd62ea1a 3178
NYX 0:85b3fd62ea1a 3179 /* Configure the Output Fast mode */
NYX 0:85b3fd62ea1a 3180 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
NYX 0:85b3fd62ea1a 3181 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
NYX 0:85b3fd62ea1a 3182 }
NYX 0:85b3fd62ea1a 3183 break;
NYX 0:85b3fd62ea1a 3184
NYX 0:85b3fd62ea1a 3185 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 3186 {
NYX 0:85b3fd62ea1a 3187 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3188 /* Configure the Channel 3 in PWM mode */
NYX 0:85b3fd62ea1a 3189 TIM_OC3_SetConfig(htim->Instance, sConfig);
NYX 0:85b3fd62ea1a 3190
NYX 0:85b3fd62ea1a 3191 /* Set the Preload enable bit for channel3 */
NYX 0:85b3fd62ea1a 3192 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
NYX 0:85b3fd62ea1a 3193
NYX 0:85b3fd62ea1a 3194 /* Configure the Output Fast mode */
NYX 0:85b3fd62ea1a 3195 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
NYX 0:85b3fd62ea1a 3196 htim->Instance->CCMR2 |= sConfig->OCFastMode;
NYX 0:85b3fd62ea1a 3197 }
NYX 0:85b3fd62ea1a 3198 break;
NYX 0:85b3fd62ea1a 3199
NYX 0:85b3fd62ea1a 3200 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 3201 {
NYX 0:85b3fd62ea1a 3202 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3203 /* Configure the Channel 4 in PWM mode */
NYX 0:85b3fd62ea1a 3204 TIM_OC4_SetConfig(htim->Instance, sConfig);
NYX 0:85b3fd62ea1a 3205
NYX 0:85b3fd62ea1a 3206 /* Set the Preload enable bit for channel4 */
NYX 0:85b3fd62ea1a 3207 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
NYX 0:85b3fd62ea1a 3208
NYX 0:85b3fd62ea1a 3209 /* Configure the Output Fast mode */
NYX 0:85b3fd62ea1a 3210 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
NYX 0:85b3fd62ea1a 3211 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
NYX 0:85b3fd62ea1a 3212 }
NYX 0:85b3fd62ea1a 3213 break;
NYX 0:85b3fd62ea1a 3214
NYX 0:85b3fd62ea1a 3215 default:
NYX 0:85b3fd62ea1a 3216 break;
NYX 0:85b3fd62ea1a 3217 }
NYX 0:85b3fd62ea1a 3218
NYX 0:85b3fd62ea1a 3219 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 3220
NYX 0:85b3fd62ea1a 3221 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 3222
NYX 0:85b3fd62ea1a 3223 return HAL_OK;
NYX 0:85b3fd62ea1a 3224 }
NYX 0:85b3fd62ea1a 3225
NYX 0:85b3fd62ea1a 3226 /**
NYX 0:85b3fd62ea1a 3227 * @brief Initializes the TIM One Pulse Channels according to the specified
NYX 0:85b3fd62ea1a 3228 * parameters in the TIM_OnePulse_InitTypeDef.
NYX 0:85b3fd62ea1a 3229 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3230 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3231 * @param sConfig: TIM One Pulse configuration structure
NYX 0:85b3fd62ea1a 3232 * @param OutputChannel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 3233 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 3234 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 3235 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 3236 * @param InputChannel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 3237 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 3238 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 3239 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 3240 * @retval HAL status
NYX 0:85b3fd62ea1a 3241 */
NYX 0:85b3fd62ea1a 3242 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
NYX 0:85b3fd62ea1a 3243 {
NYX 0:85b3fd62ea1a 3244 TIM_OC_InitTypeDef temp1;
NYX 0:85b3fd62ea1a 3245
NYX 0:85b3fd62ea1a 3246 /* Check the parameters */
NYX 0:85b3fd62ea1a 3247 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
NYX 0:85b3fd62ea1a 3248 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
NYX 0:85b3fd62ea1a 3249
NYX 0:85b3fd62ea1a 3250 if(OutputChannel != InputChannel)
NYX 0:85b3fd62ea1a 3251 {
NYX 0:85b3fd62ea1a 3252 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 3253
NYX 0:85b3fd62ea1a 3254 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 3255
NYX 0:85b3fd62ea1a 3256 /* Extract the Output compare configuration from sConfig structure */
NYX 0:85b3fd62ea1a 3257 temp1.OCMode = sConfig->OCMode;
NYX 0:85b3fd62ea1a 3258 temp1.Pulse = sConfig->Pulse;
NYX 0:85b3fd62ea1a 3259 temp1.OCPolarity = sConfig->OCPolarity;
NYX 0:85b3fd62ea1a 3260 temp1.OCNPolarity = sConfig->OCNPolarity;
NYX 0:85b3fd62ea1a 3261 temp1.OCIdleState = sConfig->OCIdleState;
NYX 0:85b3fd62ea1a 3262 temp1.OCNIdleState = sConfig->OCNIdleState;
NYX 0:85b3fd62ea1a 3263
NYX 0:85b3fd62ea1a 3264 switch (OutputChannel)
NYX 0:85b3fd62ea1a 3265 {
NYX 0:85b3fd62ea1a 3266 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 3267 {
NYX 0:85b3fd62ea1a 3268 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3269
NYX 0:85b3fd62ea1a 3270 TIM_OC1_SetConfig(htim->Instance, &temp1);
NYX 0:85b3fd62ea1a 3271 }
NYX 0:85b3fd62ea1a 3272 break;
NYX 0:85b3fd62ea1a 3273 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 3274 {
NYX 0:85b3fd62ea1a 3275 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3276
NYX 0:85b3fd62ea1a 3277 TIM_OC2_SetConfig(htim->Instance, &temp1);
NYX 0:85b3fd62ea1a 3278 }
NYX 0:85b3fd62ea1a 3279 break;
NYX 0:85b3fd62ea1a 3280 default:
NYX 0:85b3fd62ea1a 3281 break;
NYX 0:85b3fd62ea1a 3282 }
NYX 0:85b3fd62ea1a 3283 switch (InputChannel)
NYX 0:85b3fd62ea1a 3284 {
NYX 0:85b3fd62ea1a 3285 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 3286 {
NYX 0:85b3fd62ea1a 3287 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3288
NYX 0:85b3fd62ea1a 3289 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
NYX 0:85b3fd62ea1a 3290 sConfig->ICSelection, sConfig->ICFilter);
NYX 0:85b3fd62ea1a 3291
NYX 0:85b3fd62ea1a 3292 /* Reset the IC1PSC Bits */
NYX 0:85b3fd62ea1a 3293 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
NYX 0:85b3fd62ea1a 3294
NYX 0:85b3fd62ea1a 3295 /* Select the Trigger source */
NYX 0:85b3fd62ea1a 3296 htim->Instance->SMCR &= ~TIM_SMCR_TS;
NYX 0:85b3fd62ea1a 3297 htim->Instance->SMCR |= TIM_TS_TI1FP1;
NYX 0:85b3fd62ea1a 3298
NYX 0:85b3fd62ea1a 3299 /* Select the Slave Mode */
NYX 0:85b3fd62ea1a 3300 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
NYX 0:85b3fd62ea1a 3301 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
NYX 0:85b3fd62ea1a 3302 }
NYX 0:85b3fd62ea1a 3303 break;
NYX 0:85b3fd62ea1a 3304 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 3305 {
NYX 0:85b3fd62ea1a 3306 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3307
NYX 0:85b3fd62ea1a 3308 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
NYX 0:85b3fd62ea1a 3309 sConfig->ICSelection, sConfig->ICFilter);
NYX 0:85b3fd62ea1a 3310
NYX 0:85b3fd62ea1a 3311 /* Reset the IC2PSC Bits */
NYX 0:85b3fd62ea1a 3312 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
NYX 0:85b3fd62ea1a 3313
NYX 0:85b3fd62ea1a 3314 /* Select the Trigger source */
NYX 0:85b3fd62ea1a 3315 htim->Instance->SMCR &= ~TIM_SMCR_TS;
NYX 0:85b3fd62ea1a 3316 htim->Instance->SMCR |= TIM_TS_TI2FP2;
NYX 0:85b3fd62ea1a 3317
NYX 0:85b3fd62ea1a 3318 /* Select the Slave Mode */
NYX 0:85b3fd62ea1a 3319 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
NYX 0:85b3fd62ea1a 3320 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
NYX 0:85b3fd62ea1a 3321 }
NYX 0:85b3fd62ea1a 3322 break;
NYX 0:85b3fd62ea1a 3323
NYX 0:85b3fd62ea1a 3324 default:
NYX 0:85b3fd62ea1a 3325 break;
NYX 0:85b3fd62ea1a 3326 }
NYX 0:85b3fd62ea1a 3327
NYX 0:85b3fd62ea1a 3328 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 3329
NYX 0:85b3fd62ea1a 3330 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 3331
NYX 0:85b3fd62ea1a 3332 return HAL_OK;
NYX 0:85b3fd62ea1a 3333 }
NYX 0:85b3fd62ea1a 3334 else
NYX 0:85b3fd62ea1a 3335 {
NYX 0:85b3fd62ea1a 3336 return HAL_ERROR;
NYX 0:85b3fd62ea1a 3337 }
NYX 0:85b3fd62ea1a 3338 }
NYX 0:85b3fd62ea1a 3339
NYX 0:85b3fd62ea1a 3340 /**
NYX 0:85b3fd62ea1a 3341 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
NYX 0:85b3fd62ea1a 3342 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3343 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3344 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
NYX 0:85b3fd62ea1a 3345 * This parameters can be on of the following values:
NYX 0:85b3fd62ea1a 3346 * @arg TIM_DMABASE_CR1
NYX 0:85b3fd62ea1a 3347 * @arg TIM_DMABASE_CR2
NYX 0:85b3fd62ea1a 3348 * @arg TIM_DMABASE_SMCR
NYX 0:85b3fd62ea1a 3349 * @arg TIM_DMABASE_DIER
NYX 0:85b3fd62ea1a 3350 * @arg TIM_DMABASE_SR
NYX 0:85b3fd62ea1a 3351 * @arg TIM_DMABASE_EGR
NYX 0:85b3fd62ea1a 3352 * @arg TIM_DMABASE_CCMR1
NYX 0:85b3fd62ea1a 3353 * @arg TIM_DMABASE_CCMR2
NYX 0:85b3fd62ea1a 3354 * @arg TIM_DMABASE_CCER
NYX 0:85b3fd62ea1a 3355 * @arg TIM_DMABASE_CNT
NYX 0:85b3fd62ea1a 3356 * @arg TIM_DMABASE_PSC
NYX 0:85b3fd62ea1a 3357 * @arg TIM_DMABASE_ARR
NYX 0:85b3fd62ea1a 3358 * @arg TIM_DMABASE_RCR
NYX 0:85b3fd62ea1a 3359 * @arg TIM_DMABASE_CCR1
NYX 0:85b3fd62ea1a 3360 * @arg TIM_DMABASE_CCR2
NYX 0:85b3fd62ea1a 3361 * @arg TIM_DMABASE_CCR3
NYX 0:85b3fd62ea1a 3362 * @arg TIM_DMABASE_CCR4
NYX 0:85b3fd62ea1a 3363 * @arg TIM_DMABASE_BDTR
NYX 0:85b3fd62ea1a 3364 * @arg TIM_DMABASE_DCR
NYX 0:85b3fd62ea1a 3365 * @param BurstRequestSrc: TIM DMA Request sources.
NYX 0:85b3fd62ea1a 3366 * This parameters can be on of the following values:
NYX 0:85b3fd62ea1a 3367 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
NYX 0:85b3fd62ea1a 3368 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
NYX 0:85b3fd62ea1a 3369 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
NYX 0:85b3fd62ea1a 3370 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
NYX 0:85b3fd62ea1a 3371 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
NYX 0:85b3fd62ea1a 3372 * @arg TIM_DMA_COM: TIM Commutation DMA source
NYX 0:85b3fd62ea1a 3373 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
NYX 0:85b3fd62ea1a 3374 * @param BurstBuffer: The Buffer address.
NYX 0:85b3fd62ea1a 3375 * @param BurstLength: DMA Burst length. This parameter can be one value
NYX 0:85b3fd62ea1a 3376 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
NYX 0:85b3fd62ea1a 3377 * @retval HAL status
NYX 0:85b3fd62ea1a 3378 */
NYX 0:85b3fd62ea1a 3379 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
NYX 0:85b3fd62ea1a 3380 uint32_t* BurstBuffer, uint32_t BurstLength)
NYX 0:85b3fd62ea1a 3381 {
NYX 0:85b3fd62ea1a 3382 /* Check the parameters */
NYX 0:85b3fd62ea1a 3383 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3384 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
NYX 0:85b3fd62ea1a 3385 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
NYX 0:85b3fd62ea1a 3386 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
NYX 0:85b3fd62ea1a 3387
NYX 0:85b3fd62ea1a 3388 if((htim->State == HAL_TIM_STATE_BUSY))
NYX 0:85b3fd62ea1a 3389 {
NYX 0:85b3fd62ea1a 3390 return HAL_BUSY;
NYX 0:85b3fd62ea1a 3391 }
NYX 0:85b3fd62ea1a 3392 else if((htim->State == HAL_TIM_STATE_READY))
NYX 0:85b3fd62ea1a 3393 {
NYX 0:85b3fd62ea1a 3394 if((BurstBuffer == 0U) && (BurstLength > 0U))
NYX 0:85b3fd62ea1a 3395 {
NYX 0:85b3fd62ea1a 3396 return HAL_ERROR;
NYX 0:85b3fd62ea1a 3397 }
NYX 0:85b3fd62ea1a 3398 else
NYX 0:85b3fd62ea1a 3399 {
NYX 0:85b3fd62ea1a 3400 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 3401 }
NYX 0:85b3fd62ea1a 3402 }
NYX 0:85b3fd62ea1a 3403 switch(BurstRequestSrc)
NYX 0:85b3fd62ea1a 3404 {
NYX 0:85b3fd62ea1a 3405 case TIM_DMA_UPDATE:
NYX 0:85b3fd62ea1a 3406 {
NYX 0:85b3fd62ea1a 3407 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3408 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
NYX 0:85b3fd62ea1a 3409
NYX 0:85b3fd62ea1a 3410 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3411 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3412
NYX 0:85b3fd62ea1a 3413 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3414 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3415 }
NYX 0:85b3fd62ea1a 3416 break;
NYX 0:85b3fd62ea1a 3417 case TIM_DMA_CC1:
NYX 0:85b3fd62ea1a 3418 {
NYX 0:85b3fd62ea1a 3419 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3420 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 3421
NYX 0:85b3fd62ea1a 3422 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3423 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3424
NYX 0:85b3fd62ea1a 3425 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3426 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3427 }
NYX 0:85b3fd62ea1a 3428 break;
NYX 0:85b3fd62ea1a 3429 case TIM_DMA_CC2:
NYX 0:85b3fd62ea1a 3430 {
NYX 0:85b3fd62ea1a 3431 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3432 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 3433
NYX 0:85b3fd62ea1a 3434 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3435 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3436
NYX 0:85b3fd62ea1a 3437 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3438 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3439 }
NYX 0:85b3fd62ea1a 3440 break;
NYX 0:85b3fd62ea1a 3441 case TIM_DMA_CC3:
NYX 0:85b3fd62ea1a 3442 {
NYX 0:85b3fd62ea1a 3443 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3444 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 3445
NYX 0:85b3fd62ea1a 3446 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3447 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3448
NYX 0:85b3fd62ea1a 3449 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3450 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3451 }
NYX 0:85b3fd62ea1a 3452 break;
NYX 0:85b3fd62ea1a 3453 case TIM_DMA_CC4:
NYX 0:85b3fd62ea1a 3454 {
NYX 0:85b3fd62ea1a 3455 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3456 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
NYX 0:85b3fd62ea1a 3457
NYX 0:85b3fd62ea1a 3458 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3459 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3460
NYX 0:85b3fd62ea1a 3461 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3462 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3463 }
NYX 0:85b3fd62ea1a 3464 break;
NYX 0:85b3fd62ea1a 3465 case TIM_DMA_COM:
NYX 0:85b3fd62ea1a 3466 {
NYX 0:85b3fd62ea1a 3467 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3468 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
NYX 0:85b3fd62ea1a 3469
NYX 0:85b3fd62ea1a 3470 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3471 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3472
NYX 0:85b3fd62ea1a 3473 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3474 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3475 }
NYX 0:85b3fd62ea1a 3476 break;
NYX 0:85b3fd62ea1a 3477 case TIM_DMA_TRIGGER:
NYX 0:85b3fd62ea1a 3478 {
NYX 0:85b3fd62ea1a 3479 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3480 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
NYX 0:85b3fd62ea1a 3481
NYX 0:85b3fd62ea1a 3482 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3483 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3484
NYX 0:85b3fd62ea1a 3485 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3486 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3487 }
NYX 0:85b3fd62ea1a 3488 break;
NYX 0:85b3fd62ea1a 3489 default:
NYX 0:85b3fd62ea1a 3490 break;
NYX 0:85b3fd62ea1a 3491 }
NYX 0:85b3fd62ea1a 3492 /* configure the DMA Burst Mode */
NYX 0:85b3fd62ea1a 3493 htim->Instance->DCR = BurstBaseAddress | BurstLength;
NYX 0:85b3fd62ea1a 3494
NYX 0:85b3fd62ea1a 3495 /* Enable the TIM DMA Request */
NYX 0:85b3fd62ea1a 3496 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
NYX 0:85b3fd62ea1a 3497
NYX 0:85b3fd62ea1a 3498 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 3499
NYX 0:85b3fd62ea1a 3500 /* Return function status */
NYX 0:85b3fd62ea1a 3501 return HAL_OK;
NYX 0:85b3fd62ea1a 3502 }
NYX 0:85b3fd62ea1a 3503
NYX 0:85b3fd62ea1a 3504 /**
NYX 0:85b3fd62ea1a 3505 * @brief Stops the TIM DMA Burst mode
NYX 0:85b3fd62ea1a 3506 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3507 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3508 * @param BurstRequestSrc: TIM DMA Request sources to disable
NYX 0:85b3fd62ea1a 3509 * @retval HAL status
NYX 0:85b3fd62ea1a 3510 */
NYX 0:85b3fd62ea1a 3511 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
NYX 0:85b3fd62ea1a 3512 {
NYX 0:85b3fd62ea1a 3513 /* Check the parameters */
NYX 0:85b3fd62ea1a 3514 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
NYX 0:85b3fd62ea1a 3515
NYX 0:85b3fd62ea1a 3516 /* Abort the DMA transfer (at least disable the DMA channel) */
NYX 0:85b3fd62ea1a 3517 switch(BurstRequestSrc)
NYX 0:85b3fd62ea1a 3518 {
NYX 0:85b3fd62ea1a 3519 case TIM_DMA_UPDATE:
NYX 0:85b3fd62ea1a 3520 {
NYX 0:85b3fd62ea1a 3521 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
NYX 0:85b3fd62ea1a 3522 }
NYX 0:85b3fd62ea1a 3523 break;
NYX 0:85b3fd62ea1a 3524 case TIM_DMA_CC1:
NYX 0:85b3fd62ea1a 3525 {
NYX 0:85b3fd62ea1a 3526 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
NYX 0:85b3fd62ea1a 3527 }
NYX 0:85b3fd62ea1a 3528 break;
NYX 0:85b3fd62ea1a 3529 case TIM_DMA_CC2:
NYX 0:85b3fd62ea1a 3530 {
NYX 0:85b3fd62ea1a 3531 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
NYX 0:85b3fd62ea1a 3532 }
NYX 0:85b3fd62ea1a 3533 break;
NYX 0:85b3fd62ea1a 3534 case TIM_DMA_CC3:
NYX 0:85b3fd62ea1a 3535 {
NYX 0:85b3fd62ea1a 3536 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
NYX 0:85b3fd62ea1a 3537 }
NYX 0:85b3fd62ea1a 3538 break;
NYX 0:85b3fd62ea1a 3539 case TIM_DMA_CC4:
NYX 0:85b3fd62ea1a 3540 {
NYX 0:85b3fd62ea1a 3541 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
NYX 0:85b3fd62ea1a 3542 }
NYX 0:85b3fd62ea1a 3543 break;
NYX 0:85b3fd62ea1a 3544 case TIM_DMA_COM:
NYX 0:85b3fd62ea1a 3545 {
NYX 0:85b3fd62ea1a 3546 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
NYX 0:85b3fd62ea1a 3547 }
NYX 0:85b3fd62ea1a 3548 break;
NYX 0:85b3fd62ea1a 3549 case TIM_DMA_TRIGGER:
NYX 0:85b3fd62ea1a 3550 {
NYX 0:85b3fd62ea1a 3551 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
NYX 0:85b3fd62ea1a 3552 }
NYX 0:85b3fd62ea1a 3553 break;
NYX 0:85b3fd62ea1a 3554 default:
NYX 0:85b3fd62ea1a 3555 break;
NYX 0:85b3fd62ea1a 3556 }
NYX 0:85b3fd62ea1a 3557
NYX 0:85b3fd62ea1a 3558 /* Disable the TIM Update DMA request */
NYX 0:85b3fd62ea1a 3559 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
NYX 0:85b3fd62ea1a 3560
NYX 0:85b3fd62ea1a 3561 /* Return function status */
NYX 0:85b3fd62ea1a 3562 return HAL_OK;
NYX 0:85b3fd62ea1a 3563 }
NYX 0:85b3fd62ea1a 3564
NYX 0:85b3fd62ea1a 3565 /**
NYX 0:85b3fd62ea1a 3566 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
NYX 0:85b3fd62ea1a 3567 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3568 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3569 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
NYX 0:85b3fd62ea1a 3570 * This parameters can be on of the following values:
NYX 0:85b3fd62ea1a 3571 * @arg TIM_DMABASE_CR1
NYX 0:85b3fd62ea1a 3572 * @arg TIM_DMABASE_CR2
NYX 0:85b3fd62ea1a 3573 * @arg TIM_DMABASE_SMCR
NYX 0:85b3fd62ea1a 3574 * @arg TIM_DMABASE_DIER
NYX 0:85b3fd62ea1a 3575 * @arg TIM_DMABASE_SR
NYX 0:85b3fd62ea1a 3576 * @arg TIM_DMABASE_EGR
NYX 0:85b3fd62ea1a 3577 * @arg TIM_DMABASE_CCMR1
NYX 0:85b3fd62ea1a 3578 * @arg TIM_DMABASE_CCMR2
NYX 0:85b3fd62ea1a 3579 * @arg TIM_DMABASE_CCER
NYX 0:85b3fd62ea1a 3580 * @arg TIM_DMABASE_CNT
NYX 0:85b3fd62ea1a 3581 * @arg TIM_DMABASE_PSC
NYX 0:85b3fd62ea1a 3582 * @arg TIM_DMABASE_ARR
NYX 0:85b3fd62ea1a 3583 * @arg TIM_DMABASE_RCR
NYX 0:85b3fd62ea1a 3584 * @arg TIM_DMABASE_CCR1
NYX 0:85b3fd62ea1a 3585 * @arg TIM_DMABASE_CCR2
NYX 0:85b3fd62ea1a 3586 * @arg TIM_DMABASE_CCR3
NYX 0:85b3fd62ea1a 3587 * @arg TIM_DMABASE_CCR4
NYX 0:85b3fd62ea1a 3588 * @arg TIM_DMABASE_BDTR
NYX 0:85b3fd62ea1a 3589 * @arg TIM_DMABASE_DCR
NYX 0:85b3fd62ea1a 3590 * @param BurstRequestSrc: TIM DMA Request sources.
NYX 0:85b3fd62ea1a 3591 * This parameters can be on of the following values:
NYX 0:85b3fd62ea1a 3592 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
NYX 0:85b3fd62ea1a 3593 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
NYX 0:85b3fd62ea1a 3594 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
NYX 0:85b3fd62ea1a 3595 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
NYX 0:85b3fd62ea1a 3596 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
NYX 0:85b3fd62ea1a 3597 * @arg TIM_DMA_COM: TIM Commutation DMA source
NYX 0:85b3fd62ea1a 3598 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
NYX 0:85b3fd62ea1a 3599 * @param BurstBuffer: The Buffer address.
NYX 0:85b3fd62ea1a 3600 * @param BurstLength: DMA Burst length. This parameter can be one value
NYX 0:85b3fd62ea1a 3601 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
NYX 0:85b3fd62ea1a 3602 * @retval HAL status
NYX 0:85b3fd62ea1a 3603 */
NYX 0:85b3fd62ea1a 3604 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
NYX 0:85b3fd62ea1a 3605 uint32_t *BurstBuffer, uint32_t BurstLength)
NYX 0:85b3fd62ea1a 3606 {
NYX 0:85b3fd62ea1a 3607 /* Check the parameters */
NYX 0:85b3fd62ea1a 3608 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3609 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
NYX 0:85b3fd62ea1a 3610 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
NYX 0:85b3fd62ea1a 3611 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
NYX 0:85b3fd62ea1a 3612
NYX 0:85b3fd62ea1a 3613 if((htim->State == HAL_TIM_STATE_BUSY))
NYX 0:85b3fd62ea1a 3614 {
NYX 0:85b3fd62ea1a 3615 return HAL_BUSY;
NYX 0:85b3fd62ea1a 3616 }
NYX 0:85b3fd62ea1a 3617 else if((htim->State == HAL_TIM_STATE_READY))
NYX 0:85b3fd62ea1a 3618 {
NYX 0:85b3fd62ea1a 3619 if((BurstBuffer == 0U) && (BurstLength > 0U))
NYX 0:85b3fd62ea1a 3620 {
NYX 0:85b3fd62ea1a 3621 return HAL_ERROR;
NYX 0:85b3fd62ea1a 3622 }
NYX 0:85b3fd62ea1a 3623 else
NYX 0:85b3fd62ea1a 3624 {
NYX 0:85b3fd62ea1a 3625 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 3626 }
NYX 0:85b3fd62ea1a 3627 }
NYX 0:85b3fd62ea1a 3628 switch(BurstRequestSrc)
NYX 0:85b3fd62ea1a 3629 {
NYX 0:85b3fd62ea1a 3630 case TIM_DMA_UPDATE:
NYX 0:85b3fd62ea1a 3631 {
NYX 0:85b3fd62ea1a 3632 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3633 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
NYX 0:85b3fd62ea1a 3634
NYX 0:85b3fd62ea1a 3635 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3636 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3637
NYX 0:85b3fd62ea1a 3638 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3639 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3640 }
NYX 0:85b3fd62ea1a 3641 break;
NYX 0:85b3fd62ea1a 3642 case TIM_DMA_CC1:
NYX 0:85b3fd62ea1a 3643 {
NYX 0:85b3fd62ea1a 3644 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3645 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 3646
NYX 0:85b3fd62ea1a 3647 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3648 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3649
NYX 0:85b3fd62ea1a 3650 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3651 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3652 }
NYX 0:85b3fd62ea1a 3653 break;
NYX 0:85b3fd62ea1a 3654 case TIM_DMA_CC2:
NYX 0:85b3fd62ea1a 3655 {
NYX 0:85b3fd62ea1a 3656 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3657 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 3658
NYX 0:85b3fd62ea1a 3659 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3660 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3661
NYX 0:85b3fd62ea1a 3662 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3663 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3664 }
NYX 0:85b3fd62ea1a 3665 break;
NYX 0:85b3fd62ea1a 3666 case TIM_DMA_CC3:
NYX 0:85b3fd62ea1a 3667 {
NYX 0:85b3fd62ea1a 3668 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3669 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 3670
NYX 0:85b3fd62ea1a 3671 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3672 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3673
NYX 0:85b3fd62ea1a 3674 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3675 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3676 }
NYX 0:85b3fd62ea1a 3677 break;
NYX 0:85b3fd62ea1a 3678 case TIM_DMA_CC4:
NYX 0:85b3fd62ea1a 3679 {
NYX 0:85b3fd62ea1a 3680 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3681 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
NYX 0:85b3fd62ea1a 3682
NYX 0:85b3fd62ea1a 3683 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3684 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3685
NYX 0:85b3fd62ea1a 3686 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3687 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3688 }
NYX 0:85b3fd62ea1a 3689 break;
NYX 0:85b3fd62ea1a 3690 case TIM_DMA_COM:
NYX 0:85b3fd62ea1a 3691 {
NYX 0:85b3fd62ea1a 3692 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3693 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
NYX 0:85b3fd62ea1a 3694
NYX 0:85b3fd62ea1a 3695 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3696 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3697
NYX 0:85b3fd62ea1a 3698 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3699 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
NYX 0:85b3fd62ea1a 3700 }
NYX 0:85b3fd62ea1a 3701 break;
NYX 0:85b3fd62ea1a 3702 case TIM_DMA_TRIGGER:
NYX 0:85b3fd62ea1a 3703 {
NYX 0:85b3fd62ea1a 3704 /* Set the DMA Period elapsed callback */
NYX 0:85b3fd62ea1a 3705 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
NYX 0:85b3fd62ea1a 3706
NYX 0:85b3fd62ea1a 3707 /* Set the DMA error callback */
NYX 0:85b3fd62ea1a 3708 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
NYX 0:85b3fd62ea1a 3709
NYX 0:85b3fd62ea1a 3710 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 3711 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1);
NYX 0:85b3fd62ea1a 3712 }
NYX 0:85b3fd62ea1a 3713 break;
NYX 0:85b3fd62ea1a 3714 default:
NYX 0:85b3fd62ea1a 3715 break;
NYX 0:85b3fd62ea1a 3716 }
NYX 0:85b3fd62ea1a 3717
NYX 0:85b3fd62ea1a 3718 /* configure the DMA Burst Mode */
NYX 0:85b3fd62ea1a 3719 htim->Instance->DCR = BurstBaseAddress | BurstLength;
NYX 0:85b3fd62ea1a 3720
NYX 0:85b3fd62ea1a 3721 /* Enable the TIM DMA Request */
NYX 0:85b3fd62ea1a 3722 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
NYX 0:85b3fd62ea1a 3723
NYX 0:85b3fd62ea1a 3724 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 3725
NYX 0:85b3fd62ea1a 3726 /* Return function status */
NYX 0:85b3fd62ea1a 3727 return HAL_OK;
NYX 0:85b3fd62ea1a 3728 }
NYX 0:85b3fd62ea1a 3729
NYX 0:85b3fd62ea1a 3730 /**
NYX 0:85b3fd62ea1a 3731 * @brief Stop the DMA burst reading
NYX 0:85b3fd62ea1a 3732 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3733 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3734 * @param BurstRequestSrc: TIM DMA Request sources to disable.
NYX 0:85b3fd62ea1a 3735 * @retval HAL status
NYX 0:85b3fd62ea1a 3736 */
NYX 0:85b3fd62ea1a 3737 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
NYX 0:85b3fd62ea1a 3738 {
NYX 0:85b3fd62ea1a 3739 /* Check the parameters */
NYX 0:85b3fd62ea1a 3740 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
NYX 0:85b3fd62ea1a 3741
NYX 0:85b3fd62ea1a 3742 /* Abort the DMA transfer (at least disable the DMA channel) */
NYX 0:85b3fd62ea1a 3743 switch(BurstRequestSrc)
NYX 0:85b3fd62ea1a 3744 {
NYX 0:85b3fd62ea1a 3745 case TIM_DMA_UPDATE:
NYX 0:85b3fd62ea1a 3746 {
NYX 0:85b3fd62ea1a 3747 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
NYX 0:85b3fd62ea1a 3748 }
NYX 0:85b3fd62ea1a 3749 break;
NYX 0:85b3fd62ea1a 3750 case TIM_DMA_CC1:
NYX 0:85b3fd62ea1a 3751 {
NYX 0:85b3fd62ea1a 3752 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
NYX 0:85b3fd62ea1a 3753 }
NYX 0:85b3fd62ea1a 3754 break;
NYX 0:85b3fd62ea1a 3755 case TIM_DMA_CC2:
NYX 0:85b3fd62ea1a 3756 {
NYX 0:85b3fd62ea1a 3757 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
NYX 0:85b3fd62ea1a 3758 }
NYX 0:85b3fd62ea1a 3759 break;
NYX 0:85b3fd62ea1a 3760 case TIM_DMA_CC3:
NYX 0:85b3fd62ea1a 3761 {
NYX 0:85b3fd62ea1a 3762 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
NYX 0:85b3fd62ea1a 3763 }
NYX 0:85b3fd62ea1a 3764 break;
NYX 0:85b3fd62ea1a 3765 case TIM_DMA_CC4:
NYX 0:85b3fd62ea1a 3766 {
NYX 0:85b3fd62ea1a 3767 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
NYX 0:85b3fd62ea1a 3768 }
NYX 0:85b3fd62ea1a 3769 break;
NYX 0:85b3fd62ea1a 3770 case TIM_DMA_COM:
NYX 0:85b3fd62ea1a 3771 {
NYX 0:85b3fd62ea1a 3772 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
NYX 0:85b3fd62ea1a 3773 }
NYX 0:85b3fd62ea1a 3774 break;
NYX 0:85b3fd62ea1a 3775 case TIM_DMA_TRIGGER:
NYX 0:85b3fd62ea1a 3776 {
NYX 0:85b3fd62ea1a 3777 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
NYX 0:85b3fd62ea1a 3778 }
NYX 0:85b3fd62ea1a 3779 break;
NYX 0:85b3fd62ea1a 3780 default:
NYX 0:85b3fd62ea1a 3781 break;
NYX 0:85b3fd62ea1a 3782 }
NYX 0:85b3fd62ea1a 3783
NYX 0:85b3fd62ea1a 3784 /* Disable the TIM Update DMA request */
NYX 0:85b3fd62ea1a 3785 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
NYX 0:85b3fd62ea1a 3786
NYX 0:85b3fd62ea1a 3787 /* Return function status */
NYX 0:85b3fd62ea1a 3788 return HAL_OK;
NYX 0:85b3fd62ea1a 3789 }
NYX 0:85b3fd62ea1a 3790
NYX 0:85b3fd62ea1a 3791 /**
NYX 0:85b3fd62ea1a 3792 * @brief Generate a software event
NYX 0:85b3fd62ea1a 3793 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3794 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3795 * @param EventSource: specifies the event source.
NYX 0:85b3fd62ea1a 3796 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 3797 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
NYX 0:85b3fd62ea1a 3798 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
NYX 0:85b3fd62ea1a 3799 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
NYX 0:85b3fd62ea1a 3800 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
NYX 0:85b3fd62ea1a 3801 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
NYX 0:85b3fd62ea1a 3802 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
NYX 0:85b3fd62ea1a 3803 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
NYX 0:85b3fd62ea1a 3804 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
NYX 0:85b3fd62ea1a 3805 * @note TIM6 and TIM7 can only generate an update event.
NYX 0:85b3fd62ea1a 3806 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
NYX 0:85b3fd62ea1a 3807 * @retval HAL status
NYX 0:85b3fd62ea1a 3808 */
NYX 0:85b3fd62ea1a 3809
NYX 0:85b3fd62ea1a 3810 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
NYX 0:85b3fd62ea1a 3811 {
NYX 0:85b3fd62ea1a 3812 /* Check the parameters */
NYX 0:85b3fd62ea1a 3813 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3814 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
NYX 0:85b3fd62ea1a 3815
NYX 0:85b3fd62ea1a 3816 /* Process Locked */
NYX 0:85b3fd62ea1a 3817 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 3818
NYX 0:85b3fd62ea1a 3819 /* Change the TIM state */
NYX 0:85b3fd62ea1a 3820 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 3821
NYX 0:85b3fd62ea1a 3822 /* Set the event sources */
NYX 0:85b3fd62ea1a 3823 htim->Instance->EGR = EventSource;
NYX 0:85b3fd62ea1a 3824
NYX 0:85b3fd62ea1a 3825 /* Change the TIM state */
NYX 0:85b3fd62ea1a 3826 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 3827
NYX 0:85b3fd62ea1a 3828 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 3829
NYX 0:85b3fd62ea1a 3830 /* Return function status */
NYX 0:85b3fd62ea1a 3831 return HAL_OK;
NYX 0:85b3fd62ea1a 3832 }
NYX 0:85b3fd62ea1a 3833
NYX 0:85b3fd62ea1a 3834 /**
NYX 0:85b3fd62ea1a 3835 * @brief Configures the OCRef clear feature
NYX 0:85b3fd62ea1a 3836 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3837 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3838 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
NYX 0:85b3fd62ea1a 3839 * contains the OCREF clear feature and parameters for the TIM peripheral.
NYX 0:85b3fd62ea1a 3840 * @param Channel: specifies the TIM Channel.
NYX 0:85b3fd62ea1a 3841 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 3842 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 3843 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 3844 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 3845 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 3846 * @retval HAL status
NYX 0:85b3fd62ea1a 3847 */
NYX 0:85b3fd62ea1a 3848 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
NYX 0:85b3fd62ea1a 3849 {
NYX 0:85b3fd62ea1a 3850 /* Check the parameters */
NYX 0:85b3fd62ea1a 3851 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3852 assert_param(IS_TIM_CHANNELS(Channel));
NYX 0:85b3fd62ea1a 3853 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
NYX 0:85b3fd62ea1a 3854 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
NYX 0:85b3fd62ea1a 3855 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
NYX 0:85b3fd62ea1a 3856 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
NYX 0:85b3fd62ea1a 3857
NYX 0:85b3fd62ea1a 3858 /* Process Locked */
NYX 0:85b3fd62ea1a 3859 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 3860
NYX 0:85b3fd62ea1a 3861 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 3862
NYX 0:85b3fd62ea1a 3863 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
NYX 0:85b3fd62ea1a 3864 {
NYX 0:85b3fd62ea1a 3865 TIM_ETR_SetConfig(htim->Instance,
NYX 0:85b3fd62ea1a 3866 sClearInputConfig->ClearInputPrescaler,
NYX 0:85b3fd62ea1a 3867 sClearInputConfig->ClearInputPolarity,
NYX 0:85b3fd62ea1a 3868 sClearInputConfig->ClearInputFilter);
NYX 0:85b3fd62ea1a 3869 }
NYX 0:85b3fd62ea1a 3870
NYX 0:85b3fd62ea1a 3871 switch (Channel)
NYX 0:85b3fd62ea1a 3872 {
NYX 0:85b3fd62ea1a 3873 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 3874 {
NYX 0:85b3fd62ea1a 3875 if(sClearInputConfig->ClearInputState != RESET)
NYX 0:85b3fd62ea1a 3876 {
NYX 0:85b3fd62ea1a 3877 /* Enable the Ocref clear feature for Channel 1 */
NYX 0:85b3fd62ea1a 3878 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
NYX 0:85b3fd62ea1a 3879 }
NYX 0:85b3fd62ea1a 3880 else
NYX 0:85b3fd62ea1a 3881 {
NYX 0:85b3fd62ea1a 3882 /* Disable the Ocref clear feature for Channel 1 */
NYX 0:85b3fd62ea1a 3883 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
NYX 0:85b3fd62ea1a 3884 }
NYX 0:85b3fd62ea1a 3885 }
NYX 0:85b3fd62ea1a 3886 break;
NYX 0:85b3fd62ea1a 3887 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 3888 {
NYX 0:85b3fd62ea1a 3889 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3890 if(sClearInputConfig->ClearInputState != RESET)
NYX 0:85b3fd62ea1a 3891 {
NYX 0:85b3fd62ea1a 3892 /* Enable the Ocref clear feature for Channel 2 */
NYX 0:85b3fd62ea1a 3893 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
NYX 0:85b3fd62ea1a 3894 }
NYX 0:85b3fd62ea1a 3895 else
NYX 0:85b3fd62ea1a 3896 {
NYX 0:85b3fd62ea1a 3897 /* Disable the Ocref clear feature for Channel 2 */
NYX 0:85b3fd62ea1a 3898 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
NYX 0:85b3fd62ea1a 3899 }
NYX 0:85b3fd62ea1a 3900 }
NYX 0:85b3fd62ea1a 3901 break;
NYX 0:85b3fd62ea1a 3902 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 3903 {
NYX 0:85b3fd62ea1a 3904 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3905 if(sClearInputConfig->ClearInputState != RESET)
NYX 0:85b3fd62ea1a 3906 {
NYX 0:85b3fd62ea1a 3907 /* Enable the Ocref clear feature for Channel 3 */
NYX 0:85b3fd62ea1a 3908 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
NYX 0:85b3fd62ea1a 3909 }
NYX 0:85b3fd62ea1a 3910 else
NYX 0:85b3fd62ea1a 3911 {
NYX 0:85b3fd62ea1a 3912 /* Disable the Ocref clear feature for Channel 3 */
NYX 0:85b3fd62ea1a 3913 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
NYX 0:85b3fd62ea1a 3914 }
NYX 0:85b3fd62ea1a 3915 }
NYX 0:85b3fd62ea1a 3916 break;
NYX 0:85b3fd62ea1a 3917 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 3918 {
NYX 0:85b3fd62ea1a 3919 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3920 if(sClearInputConfig->ClearInputState != RESET)
NYX 0:85b3fd62ea1a 3921 {
NYX 0:85b3fd62ea1a 3922 /* Enable the Ocref clear feature for Channel 4 */
NYX 0:85b3fd62ea1a 3923 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
NYX 0:85b3fd62ea1a 3924 }
NYX 0:85b3fd62ea1a 3925 else
NYX 0:85b3fd62ea1a 3926 {
NYX 0:85b3fd62ea1a 3927 /* Disable the Ocref clear feature for Channel 4 */
NYX 0:85b3fd62ea1a 3928 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
NYX 0:85b3fd62ea1a 3929 }
NYX 0:85b3fd62ea1a 3930 }
NYX 0:85b3fd62ea1a 3931 break;
NYX 0:85b3fd62ea1a 3932 default:
NYX 0:85b3fd62ea1a 3933 break;
NYX 0:85b3fd62ea1a 3934 }
NYX 0:85b3fd62ea1a 3935
NYX 0:85b3fd62ea1a 3936 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 3937
NYX 0:85b3fd62ea1a 3938 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 3939
NYX 0:85b3fd62ea1a 3940 return HAL_OK;
NYX 0:85b3fd62ea1a 3941 }
NYX 0:85b3fd62ea1a 3942
NYX 0:85b3fd62ea1a 3943 /**
NYX 0:85b3fd62ea1a 3944 * @brief Configures the clock source to be used
NYX 0:85b3fd62ea1a 3945 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 3946 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 3947 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
NYX 0:85b3fd62ea1a 3948 * contains the clock source information for the TIM peripheral.
NYX 0:85b3fd62ea1a 3949 * @retval HAL status
NYX 0:85b3fd62ea1a 3950 */
NYX 0:85b3fd62ea1a 3951 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
NYX 0:85b3fd62ea1a 3952 {
NYX 0:85b3fd62ea1a 3953 uint32_t tmpsmcr = 0U;
NYX 0:85b3fd62ea1a 3954
NYX 0:85b3fd62ea1a 3955 /* Process Locked */
NYX 0:85b3fd62ea1a 3956 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 3957
NYX 0:85b3fd62ea1a 3958 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 3959
NYX 0:85b3fd62ea1a 3960 /* Check the parameters */
NYX 0:85b3fd62ea1a 3961 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
NYX 0:85b3fd62ea1a 3962
NYX 0:85b3fd62ea1a 3963 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
NYX 0:85b3fd62ea1a 3964 tmpsmcr = htim->Instance->SMCR;
NYX 0:85b3fd62ea1a 3965 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
NYX 0:85b3fd62ea1a 3966 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
NYX 0:85b3fd62ea1a 3967 htim->Instance->SMCR = tmpsmcr;
NYX 0:85b3fd62ea1a 3968
NYX 0:85b3fd62ea1a 3969 switch (sClockSourceConfig->ClockSource)
NYX 0:85b3fd62ea1a 3970 {
NYX 0:85b3fd62ea1a 3971 case TIM_CLOCKSOURCE_INTERNAL:
NYX 0:85b3fd62ea1a 3972 {
NYX 0:85b3fd62ea1a 3973 assert_param(IS_TIM_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3974
NYX 0:85b3fd62ea1a 3975 /* Disable slave mode to clock the prescaler directly with the internal clock */
NYX 0:85b3fd62ea1a 3976 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
NYX 0:85b3fd62ea1a 3977 }
NYX 0:85b3fd62ea1a 3978 break;
NYX 0:85b3fd62ea1a 3979
NYX 0:85b3fd62ea1a 3980 case TIM_CLOCKSOURCE_ETRMODE1:
NYX 0:85b3fd62ea1a 3981 {
NYX 0:85b3fd62ea1a 3982 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 3983
NYX 0:85b3fd62ea1a 3984 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
NYX 0:85b3fd62ea1a 3985 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
NYX 0:85b3fd62ea1a 3986 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
NYX 0:85b3fd62ea1a 3987
NYX 0:85b3fd62ea1a 3988 /* Configure the ETR Clock source */
NYX 0:85b3fd62ea1a 3989 TIM_ETR_SetConfig(htim->Instance,
NYX 0:85b3fd62ea1a 3990 sClockSourceConfig->ClockPrescaler,
NYX 0:85b3fd62ea1a 3991 sClockSourceConfig->ClockPolarity,
NYX 0:85b3fd62ea1a 3992 sClockSourceConfig->ClockFilter);
NYX 0:85b3fd62ea1a 3993 /* Get the TIMx SMCR register value */
NYX 0:85b3fd62ea1a 3994 tmpsmcr = htim->Instance->SMCR;
NYX 0:85b3fd62ea1a 3995 /* Reset the SMS and TS Bits */
NYX 0:85b3fd62ea1a 3996 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
NYX 0:85b3fd62ea1a 3997 /* Select the External clock mode1 and the ETRF trigger */
NYX 0:85b3fd62ea1a 3998 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
NYX 0:85b3fd62ea1a 3999 /* Write to TIMx SMCR */
NYX 0:85b3fd62ea1a 4000 htim->Instance->SMCR = tmpsmcr;
NYX 0:85b3fd62ea1a 4001 }
NYX 0:85b3fd62ea1a 4002 break;
NYX 0:85b3fd62ea1a 4003
NYX 0:85b3fd62ea1a 4004 case TIM_CLOCKSOURCE_ETRMODE2:
NYX 0:85b3fd62ea1a 4005 {
NYX 0:85b3fd62ea1a 4006 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4007
NYX 0:85b3fd62ea1a 4008 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
NYX 0:85b3fd62ea1a 4009 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
NYX 0:85b3fd62ea1a 4010 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
NYX 0:85b3fd62ea1a 4011
NYX 0:85b3fd62ea1a 4012 /* Configure the ETR Clock source */
NYX 0:85b3fd62ea1a 4013 TIM_ETR_SetConfig(htim->Instance,
NYX 0:85b3fd62ea1a 4014 sClockSourceConfig->ClockPrescaler,
NYX 0:85b3fd62ea1a 4015 sClockSourceConfig->ClockPolarity,
NYX 0:85b3fd62ea1a 4016 sClockSourceConfig->ClockFilter);
NYX 0:85b3fd62ea1a 4017 /* Enable the External clock mode2 */
NYX 0:85b3fd62ea1a 4018 htim->Instance->SMCR |= TIM_SMCR_ECE;
NYX 0:85b3fd62ea1a 4019 }
NYX 0:85b3fd62ea1a 4020 break;
NYX 0:85b3fd62ea1a 4021
NYX 0:85b3fd62ea1a 4022 case TIM_CLOCKSOURCE_TI1:
NYX 0:85b3fd62ea1a 4023 {
NYX 0:85b3fd62ea1a 4024 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4025
NYX 0:85b3fd62ea1a 4026 /* Check TI1 input conditioning related parameters */
NYX 0:85b3fd62ea1a 4027 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
NYX 0:85b3fd62ea1a 4028 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
NYX 0:85b3fd62ea1a 4029
NYX 0:85b3fd62ea1a 4030 TIM_TI1_ConfigInputStage(htim->Instance,
NYX 0:85b3fd62ea1a 4031 sClockSourceConfig->ClockPolarity,
NYX 0:85b3fd62ea1a 4032 sClockSourceConfig->ClockFilter);
NYX 0:85b3fd62ea1a 4033 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
NYX 0:85b3fd62ea1a 4034 }
NYX 0:85b3fd62ea1a 4035 break;
NYX 0:85b3fd62ea1a 4036 case TIM_CLOCKSOURCE_TI2:
NYX 0:85b3fd62ea1a 4037 {
NYX 0:85b3fd62ea1a 4038 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4039
NYX 0:85b3fd62ea1a 4040 /* Check TI1 input conditioning related parameters */
NYX 0:85b3fd62ea1a 4041 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
NYX 0:85b3fd62ea1a 4042 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
NYX 0:85b3fd62ea1a 4043
NYX 0:85b3fd62ea1a 4044 TIM_TI2_ConfigInputStage(htim->Instance,
NYX 0:85b3fd62ea1a 4045 sClockSourceConfig->ClockPolarity,
NYX 0:85b3fd62ea1a 4046 sClockSourceConfig->ClockFilter);
NYX 0:85b3fd62ea1a 4047 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
NYX 0:85b3fd62ea1a 4048 }
NYX 0:85b3fd62ea1a 4049 break;
NYX 0:85b3fd62ea1a 4050 case TIM_CLOCKSOURCE_TI1ED:
NYX 0:85b3fd62ea1a 4051 {
NYX 0:85b3fd62ea1a 4052 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4053
NYX 0:85b3fd62ea1a 4054 /* Check TI1 input conditioning related parameters */
NYX 0:85b3fd62ea1a 4055 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
NYX 0:85b3fd62ea1a 4056 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
NYX 0:85b3fd62ea1a 4057
NYX 0:85b3fd62ea1a 4058 TIM_TI1_ConfigInputStage(htim->Instance,
NYX 0:85b3fd62ea1a 4059 sClockSourceConfig->ClockPolarity,
NYX 0:85b3fd62ea1a 4060 sClockSourceConfig->ClockFilter);
NYX 0:85b3fd62ea1a 4061 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
NYX 0:85b3fd62ea1a 4062 }
NYX 0:85b3fd62ea1a 4063 break;
NYX 0:85b3fd62ea1a 4064 case TIM_CLOCKSOURCE_ITR0:
NYX 0:85b3fd62ea1a 4065 {
NYX 0:85b3fd62ea1a 4066 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4067 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
NYX 0:85b3fd62ea1a 4068 }
NYX 0:85b3fd62ea1a 4069 break;
NYX 0:85b3fd62ea1a 4070 case TIM_CLOCKSOURCE_ITR1:
NYX 0:85b3fd62ea1a 4071 {
NYX 0:85b3fd62ea1a 4072 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4073 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
NYX 0:85b3fd62ea1a 4074 }
NYX 0:85b3fd62ea1a 4075 break;
NYX 0:85b3fd62ea1a 4076 case TIM_CLOCKSOURCE_ITR2:
NYX 0:85b3fd62ea1a 4077 {
NYX 0:85b3fd62ea1a 4078 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4079 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
NYX 0:85b3fd62ea1a 4080 }
NYX 0:85b3fd62ea1a 4081 break;
NYX 0:85b3fd62ea1a 4082 case TIM_CLOCKSOURCE_ITR3:
NYX 0:85b3fd62ea1a 4083 {
NYX 0:85b3fd62ea1a 4084 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4085 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
NYX 0:85b3fd62ea1a 4086 }
NYX 0:85b3fd62ea1a 4087 break;
NYX 0:85b3fd62ea1a 4088
NYX 0:85b3fd62ea1a 4089 default:
NYX 0:85b3fd62ea1a 4090 break;
NYX 0:85b3fd62ea1a 4091 }
NYX 0:85b3fd62ea1a 4092 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 4093
NYX 0:85b3fd62ea1a 4094 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 4095
NYX 0:85b3fd62ea1a 4096 return HAL_OK;
NYX 0:85b3fd62ea1a 4097 }
NYX 0:85b3fd62ea1a 4098
NYX 0:85b3fd62ea1a 4099 /**
NYX 0:85b3fd62ea1a 4100 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
NYX 0:85b3fd62ea1a 4101 * or a XOR combination between CH1_input, CH2_input & CH3_input
NYX 0:85b3fd62ea1a 4102 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4103 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4104 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
NYX 0:85b3fd62ea1a 4105 * output of a XOR gate.
NYX 0:85b3fd62ea1a 4106 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 4107 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
NYX 0:85b3fd62ea1a 4108 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
NYX 0:85b3fd62ea1a 4109 * pins are connected to the TI1 input (XOR combination)
NYX 0:85b3fd62ea1a 4110 * @retval HAL status
NYX 0:85b3fd62ea1a 4111 */
NYX 0:85b3fd62ea1a 4112 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
NYX 0:85b3fd62ea1a 4113 {
NYX 0:85b3fd62ea1a 4114 uint32_t tmpcr2 = 0U;
NYX 0:85b3fd62ea1a 4115
NYX 0:85b3fd62ea1a 4116 /* Check the parameters */
NYX 0:85b3fd62ea1a 4117 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4118 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
NYX 0:85b3fd62ea1a 4119
NYX 0:85b3fd62ea1a 4120 /* Get the TIMx CR2 register value */
NYX 0:85b3fd62ea1a 4121 tmpcr2 = htim->Instance->CR2;
NYX 0:85b3fd62ea1a 4122
NYX 0:85b3fd62ea1a 4123 /* Reset the TI1 selection */
NYX 0:85b3fd62ea1a 4124 tmpcr2 &= ~TIM_CR2_TI1S;
NYX 0:85b3fd62ea1a 4125
NYX 0:85b3fd62ea1a 4126 /* Set the TI1 selection */
NYX 0:85b3fd62ea1a 4127 tmpcr2 |= TI1_Selection;
NYX 0:85b3fd62ea1a 4128
NYX 0:85b3fd62ea1a 4129 /* Write to TIMxCR2 */
NYX 0:85b3fd62ea1a 4130 htim->Instance->CR2 = tmpcr2;
NYX 0:85b3fd62ea1a 4131
NYX 0:85b3fd62ea1a 4132 return HAL_OK;
NYX 0:85b3fd62ea1a 4133 }
NYX 0:85b3fd62ea1a 4134
NYX 0:85b3fd62ea1a 4135 /**
NYX 0:85b3fd62ea1a 4136 * @brief Configures the TIM in Slave mode
NYX 0:85b3fd62ea1a 4137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4138 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4139 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
NYX 0:85b3fd62ea1a 4140 * contains the selected trigger (internal trigger input, filtered
NYX 0:85b3fd62ea1a 4141 * timer input or external trigger input) and the ) and the Slave
NYX 0:85b3fd62ea1a 4142 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
NYX 0:85b3fd62ea1a 4143 * @retval HAL status
NYX 0:85b3fd62ea1a 4144 */
NYX 0:85b3fd62ea1a 4145 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
NYX 0:85b3fd62ea1a 4146 {
NYX 0:85b3fd62ea1a 4147 /* Check the parameters */
NYX 0:85b3fd62ea1a 4148 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4149 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
NYX 0:85b3fd62ea1a 4150 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
NYX 0:85b3fd62ea1a 4151
NYX 0:85b3fd62ea1a 4152 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 4153
NYX 0:85b3fd62ea1a 4154 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 4155
NYX 0:85b3fd62ea1a 4156 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
NYX 0:85b3fd62ea1a 4157
NYX 0:85b3fd62ea1a 4158 /* Disable Trigger Interrupt */
NYX 0:85b3fd62ea1a 4159 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
NYX 0:85b3fd62ea1a 4160
NYX 0:85b3fd62ea1a 4161 /* Disable Trigger DMA request */
NYX 0:85b3fd62ea1a 4162 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
NYX 0:85b3fd62ea1a 4163
NYX 0:85b3fd62ea1a 4164 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 4165
NYX 0:85b3fd62ea1a 4166 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 4167
NYX 0:85b3fd62ea1a 4168 return HAL_OK;
NYX 0:85b3fd62ea1a 4169 }
NYX 0:85b3fd62ea1a 4170
NYX 0:85b3fd62ea1a 4171 /**
NYX 0:85b3fd62ea1a 4172 * @brief Configures the TIM in Slave mode in interrupt mode
NYX 0:85b3fd62ea1a 4173 * @param htim: TIM handle.
NYX 0:85b3fd62ea1a 4174 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
NYX 0:85b3fd62ea1a 4175 * contains the selected trigger (internal trigger input, filtered
NYX 0:85b3fd62ea1a 4176 * timer input or external trigger input) and the ) and the Slave
NYX 0:85b3fd62ea1a 4177 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
NYX 0:85b3fd62ea1a 4178 * @retval HAL status
NYX 0:85b3fd62ea1a 4179 */
NYX 0:85b3fd62ea1a 4180 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
NYX 0:85b3fd62ea1a 4181 TIM_SlaveConfigTypeDef * sSlaveConfig)
NYX 0:85b3fd62ea1a 4182 {
NYX 0:85b3fd62ea1a 4183 /* Check the parameters */
NYX 0:85b3fd62ea1a 4184 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4185 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
NYX 0:85b3fd62ea1a 4186 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
NYX 0:85b3fd62ea1a 4187
NYX 0:85b3fd62ea1a 4188 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 4189
NYX 0:85b3fd62ea1a 4190 htim->State = HAL_TIM_STATE_BUSY;
NYX 0:85b3fd62ea1a 4191
NYX 0:85b3fd62ea1a 4192 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
NYX 0:85b3fd62ea1a 4193
NYX 0:85b3fd62ea1a 4194 /* Enable Trigger Interrupt */
NYX 0:85b3fd62ea1a 4195 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
NYX 0:85b3fd62ea1a 4196
NYX 0:85b3fd62ea1a 4197 /* Disable Trigger DMA request */
NYX 0:85b3fd62ea1a 4198 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
NYX 0:85b3fd62ea1a 4199
NYX 0:85b3fd62ea1a 4200 htim->State = HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 4201
NYX 0:85b3fd62ea1a 4202 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 4203
NYX 0:85b3fd62ea1a 4204 return HAL_OK;
NYX 0:85b3fd62ea1a 4205 }
NYX 0:85b3fd62ea1a 4206
NYX 0:85b3fd62ea1a 4207 /**
NYX 0:85b3fd62ea1a 4208 * @brief Read the captured value from Capture Compare unit
NYX 0:85b3fd62ea1a 4209 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4210 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4211 * @param Channel: TIM Channels to be enabled.
NYX 0:85b3fd62ea1a 4212 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 4213 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
NYX 0:85b3fd62ea1a 4214 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
NYX 0:85b3fd62ea1a 4215 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
NYX 0:85b3fd62ea1a 4216 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
NYX 0:85b3fd62ea1a 4217 * @retval Captured value
NYX 0:85b3fd62ea1a 4218 */
NYX 0:85b3fd62ea1a 4219 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
NYX 0:85b3fd62ea1a 4220 {
NYX 0:85b3fd62ea1a 4221 uint32_t tmpreg = 0U;
NYX 0:85b3fd62ea1a 4222
NYX 0:85b3fd62ea1a 4223 __HAL_LOCK(htim);
NYX 0:85b3fd62ea1a 4224
NYX 0:85b3fd62ea1a 4225 switch (Channel)
NYX 0:85b3fd62ea1a 4226 {
NYX 0:85b3fd62ea1a 4227 case TIM_CHANNEL_1:
NYX 0:85b3fd62ea1a 4228 {
NYX 0:85b3fd62ea1a 4229 /* Check the parameters */
NYX 0:85b3fd62ea1a 4230 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4231
NYX 0:85b3fd62ea1a 4232 /* Return the capture 1 value */
NYX 0:85b3fd62ea1a 4233 tmpreg = htim->Instance->CCR1;
NYX 0:85b3fd62ea1a 4234
NYX 0:85b3fd62ea1a 4235 break;
NYX 0:85b3fd62ea1a 4236 }
NYX 0:85b3fd62ea1a 4237 case TIM_CHANNEL_2:
NYX 0:85b3fd62ea1a 4238 {
NYX 0:85b3fd62ea1a 4239 /* Check the parameters */
NYX 0:85b3fd62ea1a 4240 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4241
NYX 0:85b3fd62ea1a 4242 /* Return the capture 2 value */
NYX 0:85b3fd62ea1a 4243 tmpreg = htim->Instance->CCR2;
NYX 0:85b3fd62ea1a 4244
NYX 0:85b3fd62ea1a 4245 break;
NYX 0:85b3fd62ea1a 4246 }
NYX 0:85b3fd62ea1a 4247
NYX 0:85b3fd62ea1a 4248 case TIM_CHANNEL_3:
NYX 0:85b3fd62ea1a 4249 {
NYX 0:85b3fd62ea1a 4250 /* Check the parameters */
NYX 0:85b3fd62ea1a 4251 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4252
NYX 0:85b3fd62ea1a 4253 /* Return the capture 3 value */
NYX 0:85b3fd62ea1a 4254 tmpreg = htim->Instance->CCR3;
NYX 0:85b3fd62ea1a 4255
NYX 0:85b3fd62ea1a 4256 break;
NYX 0:85b3fd62ea1a 4257 }
NYX 0:85b3fd62ea1a 4258
NYX 0:85b3fd62ea1a 4259 case TIM_CHANNEL_4:
NYX 0:85b3fd62ea1a 4260 {
NYX 0:85b3fd62ea1a 4261 /* Check the parameters */
NYX 0:85b3fd62ea1a 4262 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 4263
NYX 0:85b3fd62ea1a 4264 /* Return the capture 4 value */
NYX 0:85b3fd62ea1a 4265 tmpreg = htim->Instance->CCR4;
NYX 0:85b3fd62ea1a 4266
NYX 0:85b3fd62ea1a 4267 break;
NYX 0:85b3fd62ea1a 4268 }
NYX 0:85b3fd62ea1a 4269
NYX 0:85b3fd62ea1a 4270 default:
NYX 0:85b3fd62ea1a 4271 break;
NYX 0:85b3fd62ea1a 4272 }
NYX 0:85b3fd62ea1a 4273
NYX 0:85b3fd62ea1a 4274 __HAL_UNLOCK(htim);
NYX 0:85b3fd62ea1a 4275 return tmpreg;
NYX 0:85b3fd62ea1a 4276 }
NYX 0:85b3fd62ea1a 4277 /**
NYX 0:85b3fd62ea1a 4278 * @}
NYX 0:85b3fd62ea1a 4279 */
NYX 0:85b3fd62ea1a 4280
NYX 0:85b3fd62ea1a 4281 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
NYX 0:85b3fd62ea1a 4282 * @brief TIM Callbacks functions
NYX 0:85b3fd62ea1a 4283 *
NYX 0:85b3fd62ea1a 4284 @verbatim
NYX 0:85b3fd62ea1a 4285 ==============================================================================
NYX 0:85b3fd62ea1a 4286 ##### TIM Callbacks functions #####
NYX 0:85b3fd62ea1a 4287 ==============================================================================
NYX 0:85b3fd62ea1a 4288 [..]
NYX 0:85b3fd62ea1a 4289 This section provides TIM callback functions:
NYX 0:85b3fd62ea1a 4290 (+) Timer Period elapsed callback
NYX 0:85b3fd62ea1a 4291 (+) Timer Output Compare callback
NYX 0:85b3fd62ea1a 4292 (+) Timer Input capture callback
NYX 0:85b3fd62ea1a 4293 (+) Timer Trigger callback
NYX 0:85b3fd62ea1a 4294 (+) Timer Error callback
NYX 0:85b3fd62ea1a 4295
NYX 0:85b3fd62ea1a 4296 @endverbatim
NYX 0:85b3fd62ea1a 4297 * @{
NYX 0:85b3fd62ea1a 4298 */
NYX 0:85b3fd62ea1a 4299
NYX 0:85b3fd62ea1a 4300 /**
NYX 0:85b3fd62ea1a 4301 * @brief Period elapsed callback in non blocking mode
NYX 0:85b3fd62ea1a 4302 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4303 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4304 * @retval None
NYX 0:85b3fd62ea1a 4305 */
NYX 0:85b3fd62ea1a 4306 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4307 {
NYX 0:85b3fd62ea1a 4308 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 4309 UNUSED(htim);
NYX 0:85b3fd62ea1a 4310 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 4311 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 4312 */
NYX 0:85b3fd62ea1a 4313 }
NYX 0:85b3fd62ea1a 4314
NYX 0:85b3fd62ea1a 4315 /**
NYX 0:85b3fd62ea1a 4316 * @brief Output Compare callback in non blocking mode
NYX 0:85b3fd62ea1a 4317 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4318 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4319 * @retval None
NYX 0:85b3fd62ea1a 4320 */
NYX 0:85b3fd62ea1a 4321 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4322 {
NYX 0:85b3fd62ea1a 4323 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 4324 UNUSED(htim);
NYX 0:85b3fd62ea1a 4325 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 4326 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 4327 */
NYX 0:85b3fd62ea1a 4328 }
NYX 0:85b3fd62ea1a 4329
NYX 0:85b3fd62ea1a 4330 /**
NYX 0:85b3fd62ea1a 4331 * @brief Input Capture callback in non blocking mode
NYX 0:85b3fd62ea1a 4332 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4333 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4334 * @retval None
NYX 0:85b3fd62ea1a 4335 */
NYX 0:85b3fd62ea1a 4336 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4337 {
NYX 0:85b3fd62ea1a 4338 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 4339 UNUSED(htim);
NYX 0:85b3fd62ea1a 4340 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 4341 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 4342 */
NYX 0:85b3fd62ea1a 4343 }
NYX 0:85b3fd62ea1a 4344
NYX 0:85b3fd62ea1a 4345 /**
NYX 0:85b3fd62ea1a 4346 * @brief PWM Pulse finished callback in non blocking mode
NYX 0:85b3fd62ea1a 4347 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4348 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4349 * @retval None
NYX 0:85b3fd62ea1a 4350 */
NYX 0:85b3fd62ea1a 4351 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4352 {
NYX 0:85b3fd62ea1a 4353 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 4354 UNUSED(htim);
NYX 0:85b3fd62ea1a 4355 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 4356 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 4357 */
NYX 0:85b3fd62ea1a 4358 }
NYX 0:85b3fd62ea1a 4359
NYX 0:85b3fd62ea1a 4360 /**
NYX 0:85b3fd62ea1a 4361 * @brief Hall Trigger detection callback in non blocking mode
NYX 0:85b3fd62ea1a 4362 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4363 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4364 * @retval None
NYX 0:85b3fd62ea1a 4365 */
NYX 0:85b3fd62ea1a 4366 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4367 {
NYX 0:85b3fd62ea1a 4368 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 4369 UNUSED(htim);
NYX 0:85b3fd62ea1a 4370 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 4371 the HAL_TIM_TriggerCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 4372 */
NYX 0:85b3fd62ea1a 4373 }
NYX 0:85b3fd62ea1a 4374
NYX 0:85b3fd62ea1a 4375 /**
NYX 0:85b3fd62ea1a 4376 * @brief Timer error callback in non blocking mode
NYX 0:85b3fd62ea1a 4377 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4378 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4379 * @retval None
NYX 0:85b3fd62ea1a 4380 */
NYX 0:85b3fd62ea1a 4381 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4382 {
NYX 0:85b3fd62ea1a 4383 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 4384 UNUSED(htim);
NYX 0:85b3fd62ea1a 4385 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 4386 the HAL_TIM_ErrorCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 4387 */
NYX 0:85b3fd62ea1a 4388 }
NYX 0:85b3fd62ea1a 4389 /**
NYX 0:85b3fd62ea1a 4390 * @}
NYX 0:85b3fd62ea1a 4391 */
NYX 0:85b3fd62ea1a 4392
NYX 0:85b3fd62ea1a 4393 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
NYX 0:85b3fd62ea1a 4394 * @brief Peripheral State functions
NYX 0:85b3fd62ea1a 4395 *
NYX 0:85b3fd62ea1a 4396 @verbatim
NYX 0:85b3fd62ea1a 4397 ==============================================================================
NYX 0:85b3fd62ea1a 4398 ##### Peripheral State functions #####
NYX 0:85b3fd62ea1a 4399 ==============================================================================
NYX 0:85b3fd62ea1a 4400 [..]
NYX 0:85b3fd62ea1a 4401 This subsection permits to get in run-time the status of the peripheral
NYX 0:85b3fd62ea1a 4402 and the data flow.
NYX 0:85b3fd62ea1a 4403
NYX 0:85b3fd62ea1a 4404 @endverbatim
NYX 0:85b3fd62ea1a 4405 * @{
NYX 0:85b3fd62ea1a 4406 */
NYX 0:85b3fd62ea1a 4407
NYX 0:85b3fd62ea1a 4408 /**
NYX 0:85b3fd62ea1a 4409 * @brief Return the TIM Base state
NYX 0:85b3fd62ea1a 4410 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4411 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4412 * @retval HAL state
NYX 0:85b3fd62ea1a 4413 */
NYX 0:85b3fd62ea1a 4414 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4415 {
NYX 0:85b3fd62ea1a 4416 return htim->State;
NYX 0:85b3fd62ea1a 4417 }
NYX 0:85b3fd62ea1a 4418
NYX 0:85b3fd62ea1a 4419 /**
NYX 0:85b3fd62ea1a 4420 * @brief Return the TIM OC state
NYX 0:85b3fd62ea1a 4421 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4422 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4423 * @retval HAL state
NYX 0:85b3fd62ea1a 4424 */
NYX 0:85b3fd62ea1a 4425 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4426 {
NYX 0:85b3fd62ea1a 4427 return htim->State;
NYX 0:85b3fd62ea1a 4428 }
NYX 0:85b3fd62ea1a 4429
NYX 0:85b3fd62ea1a 4430 /**
NYX 0:85b3fd62ea1a 4431 * @brief Return the TIM PWM state
NYX 0:85b3fd62ea1a 4432 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4433 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4434 * @retval HAL state
NYX 0:85b3fd62ea1a 4435 */
NYX 0:85b3fd62ea1a 4436 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4437 {
NYX 0:85b3fd62ea1a 4438 return htim->State;
NYX 0:85b3fd62ea1a 4439 }
NYX 0:85b3fd62ea1a 4440
NYX 0:85b3fd62ea1a 4441 /**
NYX 0:85b3fd62ea1a 4442 * @brief Return the TIM Input Capture state
NYX 0:85b3fd62ea1a 4443 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4444 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4445 * @retval HAL state
NYX 0:85b3fd62ea1a 4446 */
NYX 0:85b3fd62ea1a 4447 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4448 {
NYX 0:85b3fd62ea1a 4449 return htim->State;
NYX 0:85b3fd62ea1a 4450 }
NYX 0:85b3fd62ea1a 4451
NYX 0:85b3fd62ea1a 4452 /**
NYX 0:85b3fd62ea1a 4453 * @brief Return the TIM One Pulse Mode state
NYX 0:85b3fd62ea1a 4454 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4455 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4456 * @retval HAL state
NYX 0:85b3fd62ea1a 4457 */
NYX 0:85b3fd62ea1a 4458 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4459 {
NYX 0:85b3fd62ea1a 4460 return htim->State;
NYX 0:85b3fd62ea1a 4461 }
NYX 0:85b3fd62ea1a 4462
NYX 0:85b3fd62ea1a 4463 /**
NYX 0:85b3fd62ea1a 4464 * @brief Return the TIM Encoder Mode state
NYX 0:85b3fd62ea1a 4465 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4466 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4467 * @retval HAL state
NYX 0:85b3fd62ea1a 4468 */
NYX 0:85b3fd62ea1a 4469 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
NYX 0:85b3fd62ea1a 4470 {
NYX 0:85b3fd62ea1a 4471 return htim->State;
NYX 0:85b3fd62ea1a 4472 }
NYX 0:85b3fd62ea1a 4473 /**
NYX 0:85b3fd62ea1a 4474 * @}
NYX 0:85b3fd62ea1a 4475 */
NYX 0:85b3fd62ea1a 4476
NYX 0:85b3fd62ea1a 4477 /**
NYX 0:85b3fd62ea1a 4478 * @brief Time Base configuration
NYX 0:85b3fd62ea1a 4479 * @param TIMx: TIM peripheral
NYX 0:85b3fd62ea1a 4480 * @param Structure: pointer on TIM Time Base required parameters
NYX 0:85b3fd62ea1a 4481 * @retval None
NYX 0:85b3fd62ea1a 4482 */
NYX 0:85b3fd62ea1a 4483 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
NYX 0:85b3fd62ea1a 4484 {
NYX 0:85b3fd62ea1a 4485 uint32_t tmpcr1 = 0U;
NYX 0:85b3fd62ea1a 4486 tmpcr1 = TIMx->CR1;
NYX 0:85b3fd62ea1a 4487
NYX 0:85b3fd62ea1a 4488 /* Set TIM Time Base Unit parameters ---------------------------------------*/
NYX 0:85b3fd62ea1a 4489 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
NYX 0:85b3fd62ea1a 4490 {
NYX 0:85b3fd62ea1a 4491 /* Select the Counter Mode */
NYX 0:85b3fd62ea1a 4492 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
NYX 0:85b3fd62ea1a 4493 tmpcr1 |= Structure->CounterMode;
NYX 0:85b3fd62ea1a 4494 }
NYX 0:85b3fd62ea1a 4495
NYX 0:85b3fd62ea1a 4496 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
NYX 0:85b3fd62ea1a 4497 {
NYX 0:85b3fd62ea1a 4498 /* Set the clock division */
NYX 0:85b3fd62ea1a 4499 tmpcr1 &= ~TIM_CR1_CKD;
NYX 0:85b3fd62ea1a 4500 tmpcr1 |= (uint32_t)Structure->ClockDivision;
NYX 0:85b3fd62ea1a 4501 }
NYX 0:85b3fd62ea1a 4502
NYX 0:85b3fd62ea1a 4503 TIMx->CR1 = tmpcr1;
NYX 0:85b3fd62ea1a 4504
NYX 0:85b3fd62ea1a 4505 /* Set the Auto-reload value */
NYX 0:85b3fd62ea1a 4506 TIMx->ARR = (uint32_t)Structure->Period ;
NYX 0:85b3fd62ea1a 4507
NYX 0:85b3fd62ea1a 4508 /* Set the Prescaler value */
NYX 0:85b3fd62ea1a 4509 TIMx->PSC = (uint32_t)Structure->Prescaler;
NYX 0:85b3fd62ea1a 4510
NYX 0:85b3fd62ea1a 4511 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
NYX 0:85b3fd62ea1a 4512 {
NYX 0:85b3fd62ea1a 4513 /* Set the Repetition Counter value */
NYX 0:85b3fd62ea1a 4514 TIMx->RCR = Structure->RepetitionCounter;
NYX 0:85b3fd62ea1a 4515 }
NYX 0:85b3fd62ea1a 4516
NYX 0:85b3fd62ea1a 4517 /* Generate an update event to reload the Prescaler
NYX 0:85b3fd62ea1a 4518 and the repetition counter(only for TIM1 and TIM8) value immediately */
NYX 0:85b3fd62ea1a 4519 TIMx->EGR = TIM_EGR_UG;
NYX 0:85b3fd62ea1a 4520 }
NYX 0:85b3fd62ea1a 4521
NYX 0:85b3fd62ea1a 4522 /**
NYX 0:85b3fd62ea1a 4523 * @brief Configure the TI1 as Input.
NYX 0:85b3fd62ea1a 4524 * @param TIMx to select the TIM peripheral.
NYX 0:85b3fd62ea1a 4525 * @param TIM_ICPolarity : The Input Polarity.
NYX 0:85b3fd62ea1a 4526 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 4527 * @arg TIM_ICPolarity_Rising
NYX 0:85b3fd62ea1a 4528 * @arg TIM_ICPolarity_Falling
NYX 0:85b3fd62ea1a 4529 * @arg TIM_ICPolarity_BothEdge
NYX 0:85b3fd62ea1a 4530 * @param TIM_ICSelection: specifies the input to be used.
NYX 0:85b3fd62ea1a 4531 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 4532 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
NYX 0:85b3fd62ea1a 4533 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
NYX 0:85b3fd62ea1a 4534 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
NYX 0:85b3fd62ea1a 4535 * @param TIM_ICFilter: Specifies the Input Capture Filter.
NYX 0:85b3fd62ea1a 4536 * This parameter must be a value between 0x00 and 0x0F.
NYX 0:85b3fd62ea1a 4537 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
NYX 0:85b3fd62ea1a 4538 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
NYX 0:85b3fd62ea1a 4539 * protected against un-initialized filter and polarity values.
NYX 0:85b3fd62ea1a 4540 * @retval None
NYX 0:85b3fd62ea1a 4541 */
NYX 0:85b3fd62ea1a 4542 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
NYX 0:85b3fd62ea1a 4543 uint32_t TIM_ICFilter)
NYX 0:85b3fd62ea1a 4544 {
NYX 0:85b3fd62ea1a 4545 uint32_t tmpccmr1 = 0U;
NYX 0:85b3fd62ea1a 4546 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 4547
NYX 0:85b3fd62ea1a 4548 /* Disable the Channel 1: Reset the CC1E Bit */
NYX 0:85b3fd62ea1a 4549 TIMx->CCER &= ~TIM_CCER_CC1E;
NYX 0:85b3fd62ea1a 4550 tmpccmr1 = TIMx->CCMR1;
NYX 0:85b3fd62ea1a 4551 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 4552
NYX 0:85b3fd62ea1a 4553 /* Select the Input */
NYX 0:85b3fd62ea1a 4554 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
NYX 0:85b3fd62ea1a 4555 {
NYX 0:85b3fd62ea1a 4556 tmpccmr1 &= ~TIM_CCMR1_CC1S;
NYX 0:85b3fd62ea1a 4557 tmpccmr1 |= TIM_ICSelection;
NYX 0:85b3fd62ea1a 4558 }
NYX 0:85b3fd62ea1a 4559 else
NYX 0:85b3fd62ea1a 4560 {
NYX 0:85b3fd62ea1a 4561 tmpccmr1 &= ~TIM_CCMR1_CC1S;
NYX 0:85b3fd62ea1a 4562 tmpccmr1 |= TIM_CCMR1_CC1S_0;
NYX 0:85b3fd62ea1a 4563 }
NYX 0:85b3fd62ea1a 4564
NYX 0:85b3fd62ea1a 4565 /* Set the filter */
NYX 0:85b3fd62ea1a 4566 tmpccmr1 &= ~TIM_CCMR1_IC1F;
NYX 0:85b3fd62ea1a 4567 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
NYX 0:85b3fd62ea1a 4568
NYX 0:85b3fd62ea1a 4569 /* Select the Polarity and set the CC1E Bit */
NYX 0:85b3fd62ea1a 4570 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
NYX 0:85b3fd62ea1a 4571 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
NYX 0:85b3fd62ea1a 4572
NYX 0:85b3fd62ea1a 4573 /* Write to TIMx CCMR1 and CCER registers */
NYX 0:85b3fd62ea1a 4574 TIMx->CCMR1 = tmpccmr1;
NYX 0:85b3fd62ea1a 4575 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 4576 }
NYX 0:85b3fd62ea1a 4577
NYX 0:85b3fd62ea1a 4578 /**
NYX 0:85b3fd62ea1a 4579 * @brief Time Output Compare 2 configuration
NYX 0:85b3fd62ea1a 4580 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 4581 * @param OC_Config: The output configuration structure
NYX 0:85b3fd62ea1a 4582 * @retval None
NYX 0:85b3fd62ea1a 4583 */
NYX 0:85b3fd62ea1a 4584 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
NYX 0:85b3fd62ea1a 4585 {
NYX 0:85b3fd62ea1a 4586 uint32_t tmpccmrx = 0U;
NYX 0:85b3fd62ea1a 4587 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 4588 uint32_t tmpcr2 = 0U;
NYX 0:85b3fd62ea1a 4589
NYX 0:85b3fd62ea1a 4590 /* Disable the Channel 2: Reset the CC2E Bit */
NYX 0:85b3fd62ea1a 4591 TIMx->CCER &= ~TIM_CCER_CC2E;
NYX 0:85b3fd62ea1a 4592
NYX 0:85b3fd62ea1a 4593 /* Get the TIMx CCER register value */
NYX 0:85b3fd62ea1a 4594 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 4595 /* Get the TIMx CR2 register value */
NYX 0:85b3fd62ea1a 4596 tmpcr2 = TIMx->CR2;
NYX 0:85b3fd62ea1a 4597
NYX 0:85b3fd62ea1a 4598 /* Get the TIMx CCMR1 register value */
NYX 0:85b3fd62ea1a 4599 tmpccmrx = TIMx->CCMR1;
NYX 0:85b3fd62ea1a 4600
NYX 0:85b3fd62ea1a 4601 /* Reset the Output Compare mode and Capture/Compare selection Bits */
NYX 0:85b3fd62ea1a 4602 tmpccmrx &= ~TIM_CCMR1_OC2M;
NYX 0:85b3fd62ea1a 4603 tmpccmrx &= ~TIM_CCMR1_CC2S;
NYX 0:85b3fd62ea1a 4604
NYX 0:85b3fd62ea1a 4605 /* Select the Output Compare Mode */
NYX 0:85b3fd62ea1a 4606 tmpccmrx |= (OC_Config->OCMode << 8U);
NYX 0:85b3fd62ea1a 4607
NYX 0:85b3fd62ea1a 4608 /* Reset the Output Polarity level */
NYX 0:85b3fd62ea1a 4609 tmpccer &= ~TIM_CCER_CC2P;
NYX 0:85b3fd62ea1a 4610 /* Set the Output Compare Polarity */
NYX 0:85b3fd62ea1a 4611 tmpccer |= (OC_Config->OCPolarity << 4U);
NYX 0:85b3fd62ea1a 4612
NYX 0:85b3fd62ea1a 4613 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
NYX 0:85b3fd62ea1a 4614 {
NYX 0:85b3fd62ea1a 4615 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
NYX 0:85b3fd62ea1a 4616
NYX 0:85b3fd62ea1a 4617 /* Reset the Output N Polarity level */
NYX 0:85b3fd62ea1a 4618 tmpccer &= ~TIM_CCER_CC2NP;
NYX 0:85b3fd62ea1a 4619 /* Set the Output N Polarity */
NYX 0:85b3fd62ea1a 4620 tmpccer |= (OC_Config->OCNPolarity << 4U);
NYX 0:85b3fd62ea1a 4621 /* Reset the Output N State */
NYX 0:85b3fd62ea1a 4622 tmpccer &= ~TIM_CCER_CC2NE;
NYX 0:85b3fd62ea1a 4623
NYX 0:85b3fd62ea1a 4624 /* Reset the Output Compare and Output Compare N IDLE State */
NYX 0:85b3fd62ea1a 4625 tmpcr2 &= ~TIM_CR2_OIS2;
NYX 0:85b3fd62ea1a 4626 tmpcr2 &= ~TIM_CR2_OIS2N;
NYX 0:85b3fd62ea1a 4627 /* Set the Output Idle state */
NYX 0:85b3fd62ea1a 4628 tmpcr2 |= (OC_Config->OCIdleState << 2U);
NYX 0:85b3fd62ea1a 4629 /* Set the Output N Idle state */
NYX 0:85b3fd62ea1a 4630 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
NYX 0:85b3fd62ea1a 4631 }
NYX 0:85b3fd62ea1a 4632 /* Write to TIMx CR2 */
NYX 0:85b3fd62ea1a 4633 TIMx->CR2 = tmpcr2;
NYX 0:85b3fd62ea1a 4634
NYX 0:85b3fd62ea1a 4635 /* Write to TIMx CCMR1 */
NYX 0:85b3fd62ea1a 4636 TIMx->CCMR1 = tmpccmrx;
NYX 0:85b3fd62ea1a 4637
NYX 0:85b3fd62ea1a 4638 /* Set the Capture Compare Register value */
NYX 0:85b3fd62ea1a 4639 TIMx->CCR2 = OC_Config->Pulse;
NYX 0:85b3fd62ea1a 4640
NYX 0:85b3fd62ea1a 4641 /* Write to TIMx CCER */
NYX 0:85b3fd62ea1a 4642 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 4643 }
NYX 0:85b3fd62ea1a 4644
NYX 0:85b3fd62ea1a 4645 /**
NYX 0:85b3fd62ea1a 4646 * @brief TIM DMA Delay Pulse complete callback.
NYX 0:85b3fd62ea1a 4647 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4648 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 4649 * @retval None
NYX 0:85b3fd62ea1a 4650 */
NYX 0:85b3fd62ea1a 4651 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 4652 {
NYX 0:85b3fd62ea1a 4653 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX 0:85b3fd62ea1a 4654
NYX 0:85b3fd62ea1a 4655 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 4656
NYX 0:85b3fd62ea1a 4657 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
NYX 0:85b3fd62ea1a 4658 {
NYX 0:85b3fd62ea1a 4659 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
NYX 0:85b3fd62ea1a 4660 }
NYX 0:85b3fd62ea1a 4661 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
NYX 0:85b3fd62ea1a 4662 {
NYX 0:85b3fd62ea1a 4663 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
NYX 0:85b3fd62ea1a 4664 }
NYX 0:85b3fd62ea1a 4665 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
NYX 0:85b3fd62ea1a 4666 {
NYX 0:85b3fd62ea1a 4667 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
NYX 0:85b3fd62ea1a 4668 }
NYX 0:85b3fd62ea1a 4669 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
NYX 0:85b3fd62ea1a 4670 {
NYX 0:85b3fd62ea1a 4671 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
NYX 0:85b3fd62ea1a 4672 }
NYX 0:85b3fd62ea1a 4673
NYX 0:85b3fd62ea1a 4674 HAL_TIM_PWM_PulseFinishedCallback(htim);
NYX 0:85b3fd62ea1a 4675
NYX 0:85b3fd62ea1a 4676 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
NYX 0:85b3fd62ea1a 4677 }
NYX 0:85b3fd62ea1a 4678
NYX 0:85b3fd62ea1a 4679 /**
NYX 0:85b3fd62ea1a 4680 * @brief TIM DMA error callback
NYX 0:85b3fd62ea1a 4681 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4682 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 4683 * @retval None
NYX 0:85b3fd62ea1a 4684 */
NYX 0:85b3fd62ea1a 4685 void TIM_DMAError(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 4686 {
NYX 0:85b3fd62ea1a 4687 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX 0:85b3fd62ea1a 4688
NYX 0:85b3fd62ea1a 4689 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 4690
NYX 0:85b3fd62ea1a 4691 HAL_TIM_ErrorCallback(htim);
NYX 0:85b3fd62ea1a 4692 }
NYX 0:85b3fd62ea1a 4693
NYX 0:85b3fd62ea1a 4694 /**
NYX 0:85b3fd62ea1a 4695 * @brief TIM DMA Capture complete callback.
NYX 0:85b3fd62ea1a 4696 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4697 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 4698 * @retval None
NYX 0:85b3fd62ea1a 4699 */
NYX 0:85b3fd62ea1a 4700 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 4701 {
NYX 0:85b3fd62ea1a 4702 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX 0:85b3fd62ea1a 4703
NYX 0:85b3fd62ea1a 4704 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 4705
NYX 0:85b3fd62ea1a 4706 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
NYX 0:85b3fd62ea1a 4707 {
NYX 0:85b3fd62ea1a 4708 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
NYX 0:85b3fd62ea1a 4709 }
NYX 0:85b3fd62ea1a 4710 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
NYX 0:85b3fd62ea1a 4711 {
NYX 0:85b3fd62ea1a 4712 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
NYX 0:85b3fd62ea1a 4713 }
NYX 0:85b3fd62ea1a 4714 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
NYX 0:85b3fd62ea1a 4715 {
NYX 0:85b3fd62ea1a 4716 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
NYX 0:85b3fd62ea1a 4717 }
NYX 0:85b3fd62ea1a 4718 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
NYX 0:85b3fd62ea1a 4719 {
NYX 0:85b3fd62ea1a 4720 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
NYX 0:85b3fd62ea1a 4721 }
NYX 0:85b3fd62ea1a 4722
NYX 0:85b3fd62ea1a 4723 HAL_TIM_IC_CaptureCallback(htim);
NYX 0:85b3fd62ea1a 4724
NYX 0:85b3fd62ea1a 4725 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
NYX 0:85b3fd62ea1a 4726 }
NYX 0:85b3fd62ea1a 4727
NYX 0:85b3fd62ea1a 4728 /**
NYX 0:85b3fd62ea1a 4729 * @brief Enables or disables the TIM Capture Compare Channel x.
NYX 0:85b3fd62ea1a 4730 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 4731 * @param Channel: specifies the TIM Channel
NYX 0:85b3fd62ea1a 4732 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 4733 * @arg TIM_Channel_1: TIM Channel 1
NYX 0:85b3fd62ea1a 4734 * @arg TIM_Channel_2: TIM Channel 2
NYX 0:85b3fd62ea1a 4735 * @arg TIM_Channel_3: TIM Channel 3
NYX 0:85b3fd62ea1a 4736 * @arg TIM_Channel_4: TIM Channel 4
NYX 0:85b3fd62ea1a 4737 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
NYX 0:85b3fd62ea1a 4738 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
NYX 0:85b3fd62ea1a 4739 * @retval None
NYX 0:85b3fd62ea1a 4740 */
NYX 0:85b3fd62ea1a 4741 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
NYX 0:85b3fd62ea1a 4742 {
NYX 0:85b3fd62ea1a 4743 uint32_t tmp = 0U;
NYX 0:85b3fd62ea1a 4744
NYX 0:85b3fd62ea1a 4745 /* Check the parameters */
NYX 0:85b3fd62ea1a 4746 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
NYX 0:85b3fd62ea1a 4747 assert_param(IS_TIM_CHANNELS(Channel));
NYX 0:85b3fd62ea1a 4748
NYX 0:85b3fd62ea1a 4749 tmp = TIM_CCER_CC1E << Channel;
NYX 0:85b3fd62ea1a 4750
NYX 0:85b3fd62ea1a 4751 /* Reset the CCxE Bit */
NYX 0:85b3fd62ea1a 4752 TIMx->CCER &= ~tmp;
NYX 0:85b3fd62ea1a 4753
NYX 0:85b3fd62ea1a 4754 /* Set or reset the CCxE Bit */
NYX 0:85b3fd62ea1a 4755 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
NYX 0:85b3fd62ea1a 4756 }
NYX 0:85b3fd62ea1a 4757
NYX 0:85b3fd62ea1a 4758 /**
NYX 0:85b3fd62ea1a 4759 * @brief TIM DMA Period Elapse complete callback.
NYX 0:85b3fd62ea1a 4760 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4761 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 4762 * @retval None
NYX 0:85b3fd62ea1a 4763 */
NYX 0:85b3fd62ea1a 4764 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 4765 {
NYX 0:85b3fd62ea1a 4766 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX 0:85b3fd62ea1a 4767
NYX 0:85b3fd62ea1a 4768 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 4769
NYX 0:85b3fd62ea1a 4770 HAL_TIM_PeriodElapsedCallback(htim);
NYX 0:85b3fd62ea1a 4771 }
NYX 0:85b3fd62ea1a 4772
NYX 0:85b3fd62ea1a 4773 /**
NYX 0:85b3fd62ea1a 4774 * @brief TIM DMA Trigger callback.
NYX 0:85b3fd62ea1a 4775 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4776 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 4777 * @retval None
NYX 0:85b3fd62ea1a 4778 */
NYX 0:85b3fd62ea1a 4779 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 4780 {
NYX 0:85b3fd62ea1a 4781 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX 0:85b3fd62ea1a 4782
NYX 0:85b3fd62ea1a 4783 htim->State= HAL_TIM_STATE_READY;
NYX 0:85b3fd62ea1a 4784
NYX 0:85b3fd62ea1a 4785 HAL_TIM_TriggerCallback(htim);
NYX 0:85b3fd62ea1a 4786 }
NYX 0:85b3fd62ea1a 4787
NYX 0:85b3fd62ea1a 4788 /**
NYX 0:85b3fd62ea1a 4789 * @brief Time Output Compare 1 configuration
NYX 0:85b3fd62ea1a 4790 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 4791 * @param OC_Config: The output configuration structure
NYX 0:85b3fd62ea1a 4792 * @retval None
NYX 0:85b3fd62ea1a 4793 */
NYX 0:85b3fd62ea1a 4794 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
NYX 0:85b3fd62ea1a 4795 {
NYX 0:85b3fd62ea1a 4796 uint32_t tmpccmrx = 0U;
NYX 0:85b3fd62ea1a 4797 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 4798 uint32_t tmpcr2 = 0U;
NYX 0:85b3fd62ea1a 4799
NYX 0:85b3fd62ea1a 4800 /* Disable the Channel 1: Reset the CC1E Bit */
NYX 0:85b3fd62ea1a 4801 TIMx->CCER &= ~TIM_CCER_CC1E;
NYX 0:85b3fd62ea1a 4802
NYX 0:85b3fd62ea1a 4803 /* Get the TIMx CCER register value */
NYX 0:85b3fd62ea1a 4804 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 4805 /* Get the TIMx CR2 register value */
NYX 0:85b3fd62ea1a 4806 tmpcr2 = TIMx->CR2;
NYX 0:85b3fd62ea1a 4807
NYX 0:85b3fd62ea1a 4808 /* Get the TIMx CCMR1 register value */
NYX 0:85b3fd62ea1a 4809 tmpccmrx = TIMx->CCMR1;
NYX 0:85b3fd62ea1a 4810
NYX 0:85b3fd62ea1a 4811 /* Reset the Output Compare Mode Bits */
NYX 0:85b3fd62ea1a 4812 tmpccmrx &= ~TIM_CCMR1_OC1M;
NYX 0:85b3fd62ea1a 4813 tmpccmrx &= ~TIM_CCMR1_CC1S;
NYX 0:85b3fd62ea1a 4814 /* Select the Output Compare Mode */
NYX 0:85b3fd62ea1a 4815 tmpccmrx |= OC_Config->OCMode;
NYX 0:85b3fd62ea1a 4816
NYX 0:85b3fd62ea1a 4817 /* Reset the Output Polarity level */
NYX 0:85b3fd62ea1a 4818 tmpccer &= ~TIM_CCER_CC1P;
NYX 0:85b3fd62ea1a 4819 /* Set the Output Compare Polarity */
NYX 0:85b3fd62ea1a 4820 tmpccer |= OC_Config->OCPolarity;
NYX 0:85b3fd62ea1a 4821
NYX 0:85b3fd62ea1a 4822
NYX 0:85b3fd62ea1a 4823 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
NYX 0:85b3fd62ea1a 4824 {
NYX 0:85b3fd62ea1a 4825 /* Reset the Output N Polarity level */
NYX 0:85b3fd62ea1a 4826 tmpccer &= ~TIM_CCER_CC1NP;
NYX 0:85b3fd62ea1a 4827 /* Set the Output N Polarity */
NYX 0:85b3fd62ea1a 4828 tmpccer |= OC_Config->OCNPolarity;
NYX 0:85b3fd62ea1a 4829 /* Reset the Output N State */
NYX 0:85b3fd62ea1a 4830 tmpccer &= ~TIM_CCER_CC1NE;
NYX 0:85b3fd62ea1a 4831
NYX 0:85b3fd62ea1a 4832 /* Reset the Output Compare and Output Compare N IDLE State */
NYX 0:85b3fd62ea1a 4833 tmpcr2 &= ~TIM_CR2_OIS1;
NYX 0:85b3fd62ea1a 4834 tmpcr2 &= ~TIM_CR2_OIS1N;
NYX 0:85b3fd62ea1a 4835 /* Set the Output Idle state */
NYX 0:85b3fd62ea1a 4836 tmpcr2 |= OC_Config->OCIdleState;
NYX 0:85b3fd62ea1a 4837 /* Set the Output N Idle state */
NYX 0:85b3fd62ea1a 4838 tmpcr2 |= OC_Config->OCNIdleState;
NYX 0:85b3fd62ea1a 4839 }
NYX 0:85b3fd62ea1a 4840 /* Write to TIMx CR2 */
NYX 0:85b3fd62ea1a 4841 TIMx->CR2 = tmpcr2;
NYX 0:85b3fd62ea1a 4842
NYX 0:85b3fd62ea1a 4843 /* Write to TIMx CCMR1 */
NYX 0:85b3fd62ea1a 4844 TIMx->CCMR1 = tmpccmrx;
NYX 0:85b3fd62ea1a 4845
NYX 0:85b3fd62ea1a 4846 /* Set the Capture Compare Register value */
NYX 0:85b3fd62ea1a 4847 TIMx->CCR1 = OC_Config->Pulse;
NYX 0:85b3fd62ea1a 4848
NYX 0:85b3fd62ea1a 4849 /* Write to TIMx CCER */
NYX 0:85b3fd62ea1a 4850 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 4851 }
NYX 0:85b3fd62ea1a 4852
NYX 0:85b3fd62ea1a 4853 /**
NYX 0:85b3fd62ea1a 4854 * @brief Time Output Compare 3 configuration
NYX 0:85b3fd62ea1a 4855 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 4856 * @param OC_Config: The output configuration structure
NYX 0:85b3fd62ea1a 4857 * @retval None
NYX 0:85b3fd62ea1a 4858 */
NYX 0:85b3fd62ea1a 4859 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
NYX 0:85b3fd62ea1a 4860 {
NYX 0:85b3fd62ea1a 4861 uint32_t tmpccmrx = 0U;
NYX 0:85b3fd62ea1a 4862 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 4863 uint32_t tmpcr2 = 0U;
NYX 0:85b3fd62ea1a 4864
NYX 0:85b3fd62ea1a 4865 /* Disable the Channel 3: Reset the CC2E Bit */
NYX 0:85b3fd62ea1a 4866 TIMx->CCER &= ~TIM_CCER_CC3E;
NYX 0:85b3fd62ea1a 4867
NYX 0:85b3fd62ea1a 4868 /* Get the TIMx CCER register value */
NYX 0:85b3fd62ea1a 4869 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 4870 /* Get the TIMx CR2 register value */
NYX 0:85b3fd62ea1a 4871 tmpcr2 = TIMx->CR2;
NYX 0:85b3fd62ea1a 4872
NYX 0:85b3fd62ea1a 4873 /* Get the TIMx CCMR2 register value */
NYX 0:85b3fd62ea1a 4874 tmpccmrx = TIMx->CCMR2;
NYX 0:85b3fd62ea1a 4875
NYX 0:85b3fd62ea1a 4876 /* Reset the Output Compare mode and Capture/Compare selection Bits */
NYX 0:85b3fd62ea1a 4877 tmpccmrx &= ~TIM_CCMR2_OC3M;
NYX 0:85b3fd62ea1a 4878 tmpccmrx &= ~TIM_CCMR2_CC3S;
NYX 0:85b3fd62ea1a 4879 /* Select the Output Compare Mode */
NYX 0:85b3fd62ea1a 4880 tmpccmrx |= OC_Config->OCMode;
NYX 0:85b3fd62ea1a 4881
NYX 0:85b3fd62ea1a 4882 /* Reset the Output Polarity level */
NYX 0:85b3fd62ea1a 4883 tmpccer &= ~TIM_CCER_CC3P;
NYX 0:85b3fd62ea1a 4884 /* Set the Output Compare Polarity */
NYX 0:85b3fd62ea1a 4885 tmpccer |= (OC_Config->OCPolarity << 8U);
NYX 0:85b3fd62ea1a 4886
NYX 0:85b3fd62ea1a 4887 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
NYX 0:85b3fd62ea1a 4888 {
NYX 0:85b3fd62ea1a 4889 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
NYX 0:85b3fd62ea1a 4890 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
NYX 0:85b3fd62ea1a 4891 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
NYX 0:85b3fd62ea1a 4892
NYX 0:85b3fd62ea1a 4893 /* Reset the Output N Polarity level */
NYX 0:85b3fd62ea1a 4894 tmpccer &= ~TIM_CCER_CC3NP;
NYX 0:85b3fd62ea1a 4895 /* Set the Output N Polarity */
NYX 0:85b3fd62ea1a 4896 tmpccer |= (OC_Config->OCNPolarity << 8U);
NYX 0:85b3fd62ea1a 4897 /* Reset the Output N State */
NYX 0:85b3fd62ea1a 4898 tmpccer &= ~TIM_CCER_CC3NE;
NYX 0:85b3fd62ea1a 4899
NYX 0:85b3fd62ea1a 4900 /* Reset the Output Compare and Output Compare N IDLE State */
NYX 0:85b3fd62ea1a 4901 tmpcr2 &= ~TIM_CR2_OIS3;
NYX 0:85b3fd62ea1a 4902 tmpcr2 &= ~TIM_CR2_OIS3N;
NYX 0:85b3fd62ea1a 4903 /* Set the Output Idle state */
NYX 0:85b3fd62ea1a 4904 tmpcr2 |= (OC_Config->OCIdleState << 4U);
NYX 0:85b3fd62ea1a 4905 /* Set the Output N Idle state */
NYX 0:85b3fd62ea1a 4906 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
NYX 0:85b3fd62ea1a 4907 }
NYX 0:85b3fd62ea1a 4908 /* Write to TIMx CR2 */
NYX 0:85b3fd62ea1a 4909 TIMx->CR2 = tmpcr2;
NYX 0:85b3fd62ea1a 4910
NYX 0:85b3fd62ea1a 4911 /* Write to TIMx CCMR2 */
NYX 0:85b3fd62ea1a 4912 TIMx->CCMR2 = tmpccmrx;
NYX 0:85b3fd62ea1a 4913
NYX 0:85b3fd62ea1a 4914 /* Set the Capture Compare Register value */
NYX 0:85b3fd62ea1a 4915 TIMx->CCR3 = OC_Config->Pulse;
NYX 0:85b3fd62ea1a 4916
NYX 0:85b3fd62ea1a 4917 /* Write to TIMx CCER */
NYX 0:85b3fd62ea1a 4918 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 4919 }
NYX 0:85b3fd62ea1a 4920
NYX 0:85b3fd62ea1a 4921 /**
NYX 0:85b3fd62ea1a 4922 * @brief Time Output Compare 4 configuration
NYX 0:85b3fd62ea1a 4923 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 4924 * @param OC_Config: The output configuration structure
NYX 0:85b3fd62ea1a 4925 * @retval None
NYX 0:85b3fd62ea1a 4926 */
NYX 0:85b3fd62ea1a 4927 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
NYX 0:85b3fd62ea1a 4928 {
NYX 0:85b3fd62ea1a 4929 uint32_t tmpccmrx = 0U;
NYX 0:85b3fd62ea1a 4930 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 4931 uint32_t tmpcr2 = 0U;
NYX 0:85b3fd62ea1a 4932
NYX 0:85b3fd62ea1a 4933 /* Disable the Channel 4: Reset the CC4E Bit */
NYX 0:85b3fd62ea1a 4934 TIMx->CCER &= ~TIM_CCER_CC4E;
NYX 0:85b3fd62ea1a 4935
NYX 0:85b3fd62ea1a 4936 /* Get the TIMx CCER register value */
NYX 0:85b3fd62ea1a 4937 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 4938 /* Get the TIMx CR2 register value */
NYX 0:85b3fd62ea1a 4939 tmpcr2 = TIMx->CR2;
NYX 0:85b3fd62ea1a 4940
NYX 0:85b3fd62ea1a 4941 /* Get the TIMx CCMR2 register value */
NYX 0:85b3fd62ea1a 4942 tmpccmrx = TIMx->CCMR2;
NYX 0:85b3fd62ea1a 4943
NYX 0:85b3fd62ea1a 4944 /* Reset the Output Compare mode and Capture/Compare selection Bits */
NYX 0:85b3fd62ea1a 4945 tmpccmrx &= ~TIM_CCMR2_OC4M;
NYX 0:85b3fd62ea1a 4946 tmpccmrx &= ~TIM_CCMR2_CC4S;
NYX 0:85b3fd62ea1a 4947
NYX 0:85b3fd62ea1a 4948 /* Select the Output Compare Mode */
NYX 0:85b3fd62ea1a 4949 tmpccmrx |= (OC_Config->OCMode << 8U);
NYX 0:85b3fd62ea1a 4950
NYX 0:85b3fd62ea1a 4951 /* Reset the Output Polarity level */
NYX 0:85b3fd62ea1a 4952 tmpccer &= ~TIM_CCER_CC4P;
NYX 0:85b3fd62ea1a 4953 /* Set the Output Compare Polarity */
NYX 0:85b3fd62ea1a 4954 tmpccer |= (OC_Config->OCPolarity << 12U);
NYX 0:85b3fd62ea1a 4955
NYX 0:85b3fd62ea1a 4956 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
NYX 0:85b3fd62ea1a 4957 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
NYX 0:85b3fd62ea1a 4958 {
NYX 0:85b3fd62ea1a 4959 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
NYX 0:85b3fd62ea1a 4960 /* Reset the Output Compare IDLE State */
NYX 0:85b3fd62ea1a 4961 tmpcr2 &= ~TIM_CR2_OIS4;
NYX 0:85b3fd62ea1a 4962 /* Set the Output Idle state */
NYX 0:85b3fd62ea1a 4963 tmpcr2 |= (OC_Config->OCIdleState << 6U);
NYX 0:85b3fd62ea1a 4964 }
NYX 0:85b3fd62ea1a 4965 /* Write to TIMx CR2 */
NYX 0:85b3fd62ea1a 4966 TIMx->CR2 = tmpcr2;
NYX 0:85b3fd62ea1a 4967
NYX 0:85b3fd62ea1a 4968 /* Write to TIMx CCMR2 */
NYX 0:85b3fd62ea1a 4969 TIMx->CCMR2 = tmpccmrx;
NYX 0:85b3fd62ea1a 4970
NYX 0:85b3fd62ea1a 4971 /* Set the Capture Compare Register value */
NYX 0:85b3fd62ea1a 4972 TIMx->CCR4 = OC_Config->Pulse;
NYX 0:85b3fd62ea1a 4973
NYX 0:85b3fd62ea1a 4974 /* Write to TIMx CCER */
NYX 0:85b3fd62ea1a 4975 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 4976 }
NYX 0:85b3fd62ea1a 4977
NYX 0:85b3fd62ea1a 4978 /**
NYX 0:85b3fd62ea1a 4979 * @brief Time Output Compare 4 configuration
NYX 0:85b3fd62ea1a 4980 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 4981 * the configuration information for TIM module.
NYX 0:85b3fd62ea1a 4982 * @param sSlaveConfig: The slave configuration structure
NYX 0:85b3fd62ea1a 4983 * @retval None
NYX 0:85b3fd62ea1a 4984 */
NYX 0:85b3fd62ea1a 4985 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
NYX 0:85b3fd62ea1a 4986 TIM_SlaveConfigTypeDef * sSlaveConfig)
NYX 0:85b3fd62ea1a 4987 {
NYX 0:85b3fd62ea1a 4988 uint32_t tmpsmcr = 0U;
NYX 0:85b3fd62ea1a 4989 uint32_t tmpccmr1 = 0U;
NYX 0:85b3fd62ea1a 4990 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 4991
NYX 0:85b3fd62ea1a 4992 /* Get the TIMx SMCR register value */
NYX 0:85b3fd62ea1a 4993 tmpsmcr = htim->Instance->SMCR;
NYX 0:85b3fd62ea1a 4994
NYX 0:85b3fd62ea1a 4995 /* Reset the Trigger Selection Bits */
NYX 0:85b3fd62ea1a 4996 tmpsmcr &= ~TIM_SMCR_TS;
NYX 0:85b3fd62ea1a 4997 /* Set the Input Trigger source */
NYX 0:85b3fd62ea1a 4998 tmpsmcr |= sSlaveConfig->InputTrigger;
NYX 0:85b3fd62ea1a 4999
NYX 0:85b3fd62ea1a 5000 /* Reset the slave mode Bits */
NYX 0:85b3fd62ea1a 5001 tmpsmcr &= ~TIM_SMCR_SMS;
NYX 0:85b3fd62ea1a 5002 /* Set the slave mode */
NYX 0:85b3fd62ea1a 5003 tmpsmcr |= sSlaveConfig->SlaveMode;
NYX 0:85b3fd62ea1a 5004
NYX 0:85b3fd62ea1a 5005 /* Write to TIMx SMCR */
NYX 0:85b3fd62ea1a 5006 htim->Instance->SMCR = tmpsmcr;
NYX 0:85b3fd62ea1a 5007
NYX 0:85b3fd62ea1a 5008 /* Configure the trigger prescaler, filter, and polarity */
NYX 0:85b3fd62ea1a 5009 switch (sSlaveConfig->InputTrigger)
NYX 0:85b3fd62ea1a 5010 {
NYX 0:85b3fd62ea1a 5011 case TIM_TS_ETRF:
NYX 0:85b3fd62ea1a 5012 {
NYX 0:85b3fd62ea1a 5013 /* Check the parameters */
NYX 0:85b3fd62ea1a 5014 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 5015 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
NYX 0:85b3fd62ea1a 5016 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
NYX 0:85b3fd62ea1a 5017 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
NYX 0:85b3fd62ea1a 5018 /* Configure the ETR Trigger source */
NYX 0:85b3fd62ea1a 5019 TIM_ETR_SetConfig(htim->Instance,
NYX 0:85b3fd62ea1a 5020 sSlaveConfig->TriggerPrescaler,
NYX 0:85b3fd62ea1a 5021 sSlaveConfig->TriggerPolarity,
NYX 0:85b3fd62ea1a 5022 sSlaveConfig->TriggerFilter);
NYX 0:85b3fd62ea1a 5023 }
NYX 0:85b3fd62ea1a 5024 break;
NYX 0:85b3fd62ea1a 5025
NYX 0:85b3fd62ea1a 5026 case TIM_TS_TI1F_ED:
NYX 0:85b3fd62ea1a 5027 {
NYX 0:85b3fd62ea1a 5028 /* Check the parameters */
NYX 0:85b3fd62ea1a 5029 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 5030 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
NYX 0:85b3fd62ea1a 5031
NYX 0:85b3fd62ea1a 5032 /* Disable the Channel 1: Reset the CC1E Bit */
NYX 0:85b3fd62ea1a 5033 tmpccer = htim->Instance->CCER;
NYX 0:85b3fd62ea1a 5034 htim->Instance->CCER &= ~TIM_CCER_CC1E;
NYX 0:85b3fd62ea1a 5035 tmpccmr1 = htim->Instance->CCMR1;
NYX 0:85b3fd62ea1a 5036
NYX 0:85b3fd62ea1a 5037 /* Set the filter */
NYX 0:85b3fd62ea1a 5038 tmpccmr1 &= ~TIM_CCMR1_IC1F;
NYX 0:85b3fd62ea1a 5039 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
NYX 0:85b3fd62ea1a 5040
NYX 0:85b3fd62ea1a 5041 /* Write to TIMx CCMR1 and CCER registers */
NYX 0:85b3fd62ea1a 5042 htim->Instance->CCMR1 = tmpccmr1;
NYX 0:85b3fd62ea1a 5043 htim->Instance->CCER = tmpccer;
NYX 0:85b3fd62ea1a 5044
NYX 0:85b3fd62ea1a 5045 }
NYX 0:85b3fd62ea1a 5046 break;
NYX 0:85b3fd62ea1a 5047
NYX 0:85b3fd62ea1a 5048 case TIM_TS_TI1FP1:
NYX 0:85b3fd62ea1a 5049 {
NYX 0:85b3fd62ea1a 5050 /* Check the parameters */
NYX 0:85b3fd62ea1a 5051 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 5052 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
NYX 0:85b3fd62ea1a 5053 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
NYX 0:85b3fd62ea1a 5054
NYX 0:85b3fd62ea1a 5055 /* Configure TI1 Filter and Polarity */
NYX 0:85b3fd62ea1a 5056 TIM_TI1_ConfigInputStage(htim->Instance,
NYX 0:85b3fd62ea1a 5057 sSlaveConfig->TriggerPolarity,
NYX 0:85b3fd62ea1a 5058 sSlaveConfig->TriggerFilter);
NYX 0:85b3fd62ea1a 5059 }
NYX 0:85b3fd62ea1a 5060 break;
NYX 0:85b3fd62ea1a 5061
NYX 0:85b3fd62ea1a 5062 case TIM_TS_TI2FP2:
NYX 0:85b3fd62ea1a 5063 {
NYX 0:85b3fd62ea1a 5064 /* Check the parameters */
NYX 0:85b3fd62ea1a 5065 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 5066 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
NYX 0:85b3fd62ea1a 5067 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
NYX 0:85b3fd62ea1a 5068
NYX 0:85b3fd62ea1a 5069 /* Configure TI2 Filter and Polarity */
NYX 0:85b3fd62ea1a 5070 TIM_TI2_ConfigInputStage(htim->Instance,
NYX 0:85b3fd62ea1a 5071 sSlaveConfig->TriggerPolarity,
NYX 0:85b3fd62ea1a 5072 sSlaveConfig->TriggerFilter);
NYX 0:85b3fd62ea1a 5073 }
NYX 0:85b3fd62ea1a 5074 break;
NYX 0:85b3fd62ea1a 5075
NYX 0:85b3fd62ea1a 5076 case TIM_TS_ITR0:
NYX 0:85b3fd62ea1a 5077 {
NYX 0:85b3fd62ea1a 5078 /* Check the parameter */
NYX 0:85b3fd62ea1a 5079 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 5080 }
NYX 0:85b3fd62ea1a 5081 break;
NYX 0:85b3fd62ea1a 5082
NYX 0:85b3fd62ea1a 5083 case TIM_TS_ITR1:
NYX 0:85b3fd62ea1a 5084 {
NYX 0:85b3fd62ea1a 5085 /* Check the parameter */
NYX 0:85b3fd62ea1a 5086 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 5087 }
NYX 0:85b3fd62ea1a 5088 break;
NYX 0:85b3fd62ea1a 5089
NYX 0:85b3fd62ea1a 5090 case TIM_TS_ITR2:
NYX 0:85b3fd62ea1a 5091 {
NYX 0:85b3fd62ea1a 5092 /* Check the parameter */
NYX 0:85b3fd62ea1a 5093 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 5094 }
NYX 0:85b3fd62ea1a 5095 break;
NYX 0:85b3fd62ea1a 5096
NYX 0:85b3fd62ea1a 5097 case TIM_TS_ITR3:
NYX 0:85b3fd62ea1a 5098 {
NYX 0:85b3fd62ea1a 5099 /* Check the parameter */
NYX 0:85b3fd62ea1a 5100 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
NYX 0:85b3fd62ea1a 5101 }
NYX 0:85b3fd62ea1a 5102 break;
NYX 0:85b3fd62ea1a 5103
NYX 0:85b3fd62ea1a 5104 default:
NYX 0:85b3fd62ea1a 5105 break;
NYX 0:85b3fd62ea1a 5106 }
NYX 0:85b3fd62ea1a 5107 }
NYX 0:85b3fd62ea1a 5108
NYX 0:85b3fd62ea1a 5109
NYX 0:85b3fd62ea1a 5110 /**
NYX 0:85b3fd62ea1a 5111 * @brief Configure the Polarity and Filter for TI1.
NYX 0:85b3fd62ea1a 5112 * @param TIMx to select the TIM peripheral.
NYX 0:85b3fd62ea1a 5113 * @param TIM_ICPolarity : The Input Polarity.
NYX 0:85b3fd62ea1a 5114 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5115 * @arg TIM_ICPolarity_Rising
NYX 0:85b3fd62ea1a 5116 * @arg TIM_ICPolarity_Falling
NYX 0:85b3fd62ea1a 5117 * @arg TIM_ICPolarity_BothEdge
NYX 0:85b3fd62ea1a 5118 * @param TIM_ICFilter: Specifies the Input Capture Filter.
NYX 0:85b3fd62ea1a 5119 * This parameter must be a value between 0x00 and 0x0F.
NYX 0:85b3fd62ea1a 5120 * @retval None
NYX 0:85b3fd62ea1a 5121 */
NYX 0:85b3fd62ea1a 5122 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
NYX 0:85b3fd62ea1a 5123 {
NYX 0:85b3fd62ea1a 5124 uint32_t tmpccmr1 = 0U;
NYX 0:85b3fd62ea1a 5125 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 5126
NYX 0:85b3fd62ea1a 5127 /* Disable the Channel 1: Reset the CC1E Bit */
NYX 0:85b3fd62ea1a 5128 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 5129 TIMx->CCER &= ~TIM_CCER_CC1E;
NYX 0:85b3fd62ea1a 5130 tmpccmr1 = TIMx->CCMR1;
NYX 0:85b3fd62ea1a 5131
NYX 0:85b3fd62ea1a 5132 /* Set the filter */
NYX 0:85b3fd62ea1a 5133 tmpccmr1 &= ~TIM_CCMR1_IC1F;
NYX 0:85b3fd62ea1a 5134 tmpccmr1 |= (TIM_ICFilter << 4U);
NYX 0:85b3fd62ea1a 5135
NYX 0:85b3fd62ea1a 5136 /* Select the Polarity and set the CC1E Bit */
NYX 0:85b3fd62ea1a 5137 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
NYX 0:85b3fd62ea1a 5138 tmpccer |= TIM_ICPolarity;
NYX 0:85b3fd62ea1a 5139
NYX 0:85b3fd62ea1a 5140 /* Write to TIMx CCMR1 and CCER registers */
NYX 0:85b3fd62ea1a 5141 TIMx->CCMR1 = tmpccmr1;
NYX 0:85b3fd62ea1a 5142 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 5143 }
NYX 0:85b3fd62ea1a 5144
NYX 0:85b3fd62ea1a 5145 /**
NYX 0:85b3fd62ea1a 5146 * @brief Configure the TI2 as Input.
NYX 0:85b3fd62ea1a 5147 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 5148 * @param TIM_ICPolarity : The Input Polarity.
NYX 0:85b3fd62ea1a 5149 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5150 * @arg TIM_ICPolarity_Rising
NYX 0:85b3fd62ea1a 5151 * @arg TIM_ICPolarity_Falling
NYX 0:85b3fd62ea1a 5152 * @arg TIM_ICPolarity_BothEdge
NYX 0:85b3fd62ea1a 5153 * @param TIM_ICSelection: specifies the input to be used.
NYX 0:85b3fd62ea1a 5154 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5155 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
NYX 0:85b3fd62ea1a 5156 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
NYX 0:85b3fd62ea1a 5157 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
NYX 0:85b3fd62ea1a 5158 * @param TIM_ICFilter: Specifies the Input Capture Filter.
NYX 0:85b3fd62ea1a 5159 * This parameter must be a value between 0x00 and 0x0F.
NYX 0:85b3fd62ea1a 5160 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
NYX 0:85b3fd62ea1a 5161 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
NYX 0:85b3fd62ea1a 5162 * protected against un-initialized filter and polarity values.
NYX 0:85b3fd62ea1a 5163 * @retval None
NYX 0:85b3fd62ea1a 5164 */
NYX 0:85b3fd62ea1a 5165 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
NYX 0:85b3fd62ea1a 5166 uint32_t TIM_ICFilter)
NYX 0:85b3fd62ea1a 5167 {
NYX 0:85b3fd62ea1a 5168 uint32_t tmpccmr1 = 0U;
NYX 0:85b3fd62ea1a 5169 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 5170
NYX 0:85b3fd62ea1a 5171 /* Disable the Channel 2: Reset the CC2E Bit */
NYX 0:85b3fd62ea1a 5172 TIMx->CCER &= ~TIM_CCER_CC2E;
NYX 0:85b3fd62ea1a 5173 tmpccmr1 = TIMx->CCMR1;
NYX 0:85b3fd62ea1a 5174 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 5175
NYX 0:85b3fd62ea1a 5176 /* Select the Input */
NYX 0:85b3fd62ea1a 5177 tmpccmr1 &= ~TIM_CCMR1_CC2S;
NYX 0:85b3fd62ea1a 5178 tmpccmr1 |= (TIM_ICSelection << 8U);
NYX 0:85b3fd62ea1a 5179
NYX 0:85b3fd62ea1a 5180 /* Set the filter */
NYX 0:85b3fd62ea1a 5181 tmpccmr1 &= ~TIM_CCMR1_IC2F;
NYX 0:85b3fd62ea1a 5182 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
NYX 0:85b3fd62ea1a 5183
NYX 0:85b3fd62ea1a 5184 /* Select the Polarity and set the CC2E Bit */
NYX 0:85b3fd62ea1a 5185 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
NYX 0:85b3fd62ea1a 5186 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
NYX 0:85b3fd62ea1a 5187
NYX 0:85b3fd62ea1a 5188 /* Write to TIMx CCMR1 and CCER registers */
NYX 0:85b3fd62ea1a 5189 TIMx->CCMR1 = tmpccmr1 ;
NYX 0:85b3fd62ea1a 5190 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 5191 }
NYX 0:85b3fd62ea1a 5192
NYX 0:85b3fd62ea1a 5193 /**
NYX 0:85b3fd62ea1a 5194 * @brief Configure the Polarity and Filter for TI2.
NYX 0:85b3fd62ea1a 5195 * @param TIMx to select the TIM peripheral.
NYX 0:85b3fd62ea1a 5196 * @param TIM_ICPolarity : The Input Polarity.
NYX 0:85b3fd62ea1a 5197 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5198 * @arg TIM_ICPolarity_Rising
NYX 0:85b3fd62ea1a 5199 * @arg TIM_ICPolarity_Falling
NYX 0:85b3fd62ea1a 5200 * @arg TIM_ICPolarity_BothEdge
NYX 0:85b3fd62ea1a 5201 * @param TIM_ICFilter: Specifies the Input Capture Filter.
NYX 0:85b3fd62ea1a 5202 * This parameter must be a value between 0x00 and 0x0F.
NYX 0:85b3fd62ea1a 5203 * @retval None
NYX 0:85b3fd62ea1a 5204 */
NYX 0:85b3fd62ea1a 5205 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
NYX 0:85b3fd62ea1a 5206 {
NYX 0:85b3fd62ea1a 5207 uint32_t tmpccmr1 = 0U;
NYX 0:85b3fd62ea1a 5208 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 5209
NYX 0:85b3fd62ea1a 5210 /* Disable the Channel 2: Reset the CC2E Bit */
NYX 0:85b3fd62ea1a 5211 TIMx->CCER &= ~TIM_CCER_CC2E;
NYX 0:85b3fd62ea1a 5212 tmpccmr1 = TIMx->CCMR1;
NYX 0:85b3fd62ea1a 5213 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 5214
NYX 0:85b3fd62ea1a 5215 /* Set the filter */
NYX 0:85b3fd62ea1a 5216 tmpccmr1 &= ~TIM_CCMR1_IC2F;
NYX 0:85b3fd62ea1a 5217 tmpccmr1 |= (TIM_ICFilter << 12U);
NYX 0:85b3fd62ea1a 5218
NYX 0:85b3fd62ea1a 5219 /* Select the Polarity and set the CC2E Bit */
NYX 0:85b3fd62ea1a 5220 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
NYX 0:85b3fd62ea1a 5221 tmpccer |= (TIM_ICPolarity << 4U);
NYX 0:85b3fd62ea1a 5222
NYX 0:85b3fd62ea1a 5223 /* Write to TIMx CCMR1 and CCER registers */
NYX 0:85b3fd62ea1a 5224 TIMx->CCMR1 = tmpccmr1 ;
NYX 0:85b3fd62ea1a 5225 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 5226 }
NYX 0:85b3fd62ea1a 5227
NYX 0:85b3fd62ea1a 5228 /**
NYX 0:85b3fd62ea1a 5229 * @brief Configure the TI3 as Input.
NYX 0:85b3fd62ea1a 5230 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 5231 * @param TIM_ICPolarity : The Input Polarity.
NYX 0:85b3fd62ea1a 5232 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5233 * @arg TIM_ICPolarity_Rising
NYX 0:85b3fd62ea1a 5234 * @arg TIM_ICPolarity_Falling
NYX 0:85b3fd62ea1a 5235 * @arg TIM_ICPolarity_BothEdge
NYX 0:85b3fd62ea1a 5236 * @param TIM_ICSelection: specifies the input to be used.
NYX 0:85b3fd62ea1a 5237 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5238 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
NYX 0:85b3fd62ea1a 5239 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
NYX 0:85b3fd62ea1a 5240 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
NYX 0:85b3fd62ea1a 5241 * @param TIM_ICFilter: Specifies the Input Capture Filter.
NYX 0:85b3fd62ea1a 5242 * This parameter must be a value between 0x00 and 0x0F.
NYX 0:85b3fd62ea1a 5243 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
NYX 0:85b3fd62ea1a 5244 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
NYX 0:85b3fd62ea1a 5245 * protected against un-initialized filter and polarity values.
NYX 0:85b3fd62ea1a 5246 * @retval None
NYX 0:85b3fd62ea1a 5247 */
NYX 0:85b3fd62ea1a 5248 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
NYX 0:85b3fd62ea1a 5249 uint32_t TIM_ICFilter)
NYX 0:85b3fd62ea1a 5250 {
NYX 0:85b3fd62ea1a 5251 uint32_t tmpccmr2 = 0U;
NYX 0:85b3fd62ea1a 5252 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 5253
NYX 0:85b3fd62ea1a 5254 /* Disable the Channel 3: Reset the CC3E Bit */
NYX 0:85b3fd62ea1a 5255 TIMx->CCER &= ~TIM_CCER_CC3E;
NYX 0:85b3fd62ea1a 5256 tmpccmr2 = TIMx->CCMR2;
NYX 0:85b3fd62ea1a 5257 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 5258
NYX 0:85b3fd62ea1a 5259 /* Select the Input */
NYX 0:85b3fd62ea1a 5260 tmpccmr2 &= ~TIM_CCMR2_CC3S;
NYX 0:85b3fd62ea1a 5261 tmpccmr2 |= TIM_ICSelection;
NYX 0:85b3fd62ea1a 5262
NYX 0:85b3fd62ea1a 5263 /* Set the filter */
NYX 0:85b3fd62ea1a 5264 tmpccmr2 &= ~TIM_CCMR2_IC3F;
NYX 0:85b3fd62ea1a 5265 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
NYX 0:85b3fd62ea1a 5266
NYX 0:85b3fd62ea1a 5267 /* Select the Polarity and set the CC3E Bit */
NYX 0:85b3fd62ea1a 5268 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
NYX 0:85b3fd62ea1a 5269 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
NYX 0:85b3fd62ea1a 5270
NYX 0:85b3fd62ea1a 5271 /* Write to TIMx CCMR2 and CCER registers */
NYX 0:85b3fd62ea1a 5272 TIMx->CCMR2 = tmpccmr2;
NYX 0:85b3fd62ea1a 5273 TIMx->CCER = tmpccer;
NYX 0:85b3fd62ea1a 5274 }
NYX 0:85b3fd62ea1a 5275
NYX 0:85b3fd62ea1a 5276 /**
NYX 0:85b3fd62ea1a 5277 * @brief Configure the TI4 as Input.
NYX 0:85b3fd62ea1a 5278 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 5279 * @param TIM_ICPolarity : The Input Polarity.
NYX 0:85b3fd62ea1a 5280 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5281 * @arg TIM_ICPolarity_Rising
NYX 0:85b3fd62ea1a 5282 * @arg TIM_ICPolarity_Falling
NYX 0:85b3fd62ea1a 5283 * @arg TIM_ICPolarity_BothEdge
NYX 0:85b3fd62ea1a 5284 * @param TIM_ICSelection: specifies the input to be used.
NYX 0:85b3fd62ea1a 5285 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5286 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
NYX 0:85b3fd62ea1a 5287 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
NYX 0:85b3fd62ea1a 5288 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
NYX 0:85b3fd62ea1a 5289 * @param TIM_ICFilter: Specifies the Input Capture Filter.
NYX 0:85b3fd62ea1a 5290 * This parameter must be a value between 0x00 and 0x0F.
NYX 0:85b3fd62ea1a 5291 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
NYX 0:85b3fd62ea1a 5292 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
NYX 0:85b3fd62ea1a 5293 * protected against un-initialized filter and polarity values.
NYX 0:85b3fd62ea1a 5294 * @retval None
NYX 0:85b3fd62ea1a 5295 */
NYX 0:85b3fd62ea1a 5296 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
NYX 0:85b3fd62ea1a 5297 uint32_t TIM_ICFilter)
NYX 0:85b3fd62ea1a 5298 {
NYX 0:85b3fd62ea1a 5299 uint32_t tmpccmr2 = 0U;
NYX 0:85b3fd62ea1a 5300 uint32_t tmpccer = 0U;
NYX 0:85b3fd62ea1a 5301
NYX 0:85b3fd62ea1a 5302 /* Disable the Channel 4: Reset the CC4E Bit */
NYX 0:85b3fd62ea1a 5303 TIMx->CCER &= ~TIM_CCER_CC4E;
NYX 0:85b3fd62ea1a 5304 tmpccmr2 = TIMx->CCMR2;
NYX 0:85b3fd62ea1a 5305 tmpccer = TIMx->CCER;
NYX 0:85b3fd62ea1a 5306
NYX 0:85b3fd62ea1a 5307 /* Select the Input */
NYX 0:85b3fd62ea1a 5308 tmpccmr2 &= ~TIM_CCMR2_CC4S;
NYX 0:85b3fd62ea1a 5309 tmpccmr2 |= (TIM_ICSelection << 8U);
NYX 0:85b3fd62ea1a 5310
NYX 0:85b3fd62ea1a 5311 /* Set the filter */
NYX 0:85b3fd62ea1a 5312 tmpccmr2 &= ~TIM_CCMR2_IC4F;
NYX 0:85b3fd62ea1a 5313 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
NYX 0:85b3fd62ea1a 5314
NYX 0:85b3fd62ea1a 5315 /* Select the Polarity and set the CC4E Bit */
NYX 0:85b3fd62ea1a 5316 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
NYX 0:85b3fd62ea1a 5317 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
NYX 0:85b3fd62ea1a 5318
NYX 0:85b3fd62ea1a 5319 /* Write to TIMx CCMR2 and CCER registers */
NYX 0:85b3fd62ea1a 5320 TIMx->CCMR2 = tmpccmr2;
NYX 0:85b3fd62ea1a 5321 TIMx->CCER = tmpccer ;
NYX 0:85b3fd62ea1a 5322 }
NYX 0:85b3fd62ea1a 5323
NYX 0:85b3fd62ea1a 5324 /**
NYX 0:85b3fd62ea1a 5325 * @brief Selects the Input Trigger source
NYX 0:85b3fd62ea1a 5326 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 5327 * @param TIM_ITRx: The Input Trigger source.
NYX 0:85b3fd62ea1a 5328 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5329 * @arg TIM_TS_ITR0: Internal Trigger 0
NYX 0:85b3fd62ea1a 5330 * @arg TIM_TS_ITR1: Internal Trigger 1
NYX 0:85b3fd62ea1a 5331 * @arg TIM_TS_ITR2: Internal Trigger 2
NYX 0:85b3fd62ea1a 5332 * @arg TIM_TS_ITR3: Internal Trigger 3
NYX 0:85b3fd62ea1a 5333 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
NYX 0:85b3fd62ea1a 5334 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
NYX 0:85b3fd62ea1a 5335 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
NYX 0:85b3fd62ea1a 5336 * @arg TIM_TS_ETRF: External Trigger input
NYX 0:85b3fd62ea1a 5337 * @retval None
NYX 0:85b3fd62ea1a 5338 */
NYX 0:85b3fd62ea1a 5339 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
NYX 0:85b3fd62ea1a 5340 {
NYX 0:85b3fd62ea1a 5341 uint32_t tmpsmcr = 0U;
NYX 0:85b3fd62ea1a 5342
NYX 0:85b3fd62ea1a 5343 /* Get the TIMx SMCR register value */
NYX 0:85b3fd62ea1a 5344 tmpsmcr = TIMx->SMCR;
NYX 0:85b3fd62ea1a 5345 /* Reset the TS Bits */
NYX 0:85b3fd62ea1a 5346 tmpsmcr &= ~TIM_SMCR_TS;
NYX 0:85b3fd62ea1a 5347 /* Set the Input Trigger source and the slave mode*/
NYX 0:85b3fd62ea1a 5348 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
NYX 0:85b3fd62ea1a 5349 /* Write to TIMx SMCR */
NYX 0:85b3fd62ea1a 5350 TIMx->SMCR = tmpsmcr;
NYX 0:85b3fd62ea1a 5351 }
NYX 0:85b3fd62ea1a 5352
NYX 0:85b3fd62ea1a 5353 /**
NYX 0:85b3fd62ea1a 5354 * @brief Configures the TIMx External Trigger (ETR).
NYX 0:85b3fd62ea1a 5355 * @param TIMx to select the TIM peripheral
NYX 0:85b3fd62ea1a 5356 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
NYX 0:85b3fd62ea1a 5357 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5358 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
NYX 0:85b3fd62ea1a 5359 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
NYX 0:85b3fd62ea1a 5360 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
NYX 0:85b3fd62ea1a 5361 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
NYX 0:85b3fd62ea1a 5362 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
NYX 0:85b3fd62ea1a 5363 * This parameter can be one of the following values:
NYX 0:85b3fd62ea1a 5364 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
NYX 0:85b3fd62ea1a 5365 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
NYX 0:85b3fd62ea1a 5366 * @param ExtTRGFilter: External Trigger Filter.
NYX 0:85b3fd62ea1a 5367 * This parameter must be a value between 0x00 and 0x0F
NYX 0:85b3fd62ea1a 5368 * @retval None
NYX 0:85b3fd62ea1a 5369 */
NYX 0:85b3fd62ea1a 5370 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
NYX 0:85b3fd62ea1a 5371 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
NYX 0:85b3fd62ea1a 5372 {
NYX 0:85b3fd62ea1a 5373 uint32_t tmpsmcr = 0U;
NYX 0:85b3fd62ea1a 5374
NYX 0:85b3fd62ea1a 5375 tmpsmcr = TIMx->SMCR;
NYX 0:85b3fd62ea1a 5376
NYX 0:85b3fd62ea1a 5377 /* Reset the ETR Bits */
NYX 0:85b3fd62ea1a 5378 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
NYX 0:85b3fd62ea1a 5379
NYX 0:85b3fd62ea1a 5380 /* Set the Prescaler, the Filter value and the Polarity */
NYX 0:85b3fd62ea1a 5381 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
NYX 0:85b3fd62ea1a 5382
NYX 0:85b3fd62ea1a 5383 /* Write to TIMx SMCR */
NYX 0:85b3fd62ea1a 5384 TIMx->SMCR = tmpsmcr;
NYX 0:85b3fd62ea1a 5385 }
NYX 0:85b3fd62ea1a 5386
NYX 0:85b3fd62ea1a 5387 /**
NYX 0:85b3fd62ea1a 5388 * @}
NYX 0:85b3fd62ea1a 5389 */
NYX 0:85b3fd62ea1a 5390
NYX 0:85b3fd62ea1a 5391 #endif /* HAL_TIM_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 5392 /**
NYX 0:85b3fd62ea1a 5393 * @}
NYX 0:85b3fd62ea1a 5394 */
NYX 0:85b3fd62ea1a 5395
NYX 0:85b3fd62ea1a 5396 /**
NYX 0:85b3fd62ea1a 5397 * @}
NYX 0:85b3fd62ea1a 5398 */
NYX 0:85b3fd62ea1a 5399 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/