Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

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NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_sram.h
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief Header file of SRAM HAL module.
NYX 0:85b3fd62ea1a 8 ******************************************************************************
NYX 0:85b3fd62ea1a 9 * @attention
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 12 *
NYX 0:85b3fd62ea1a 13 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 14 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 15 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 16 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 18 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 19 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 21 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 22 * without specific prior written permission.
NYX 0:85b3fd62ea1a 23 *
NYX 0:85b3fd62ea1a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 34 *
NYX 0:85b3fd62ea1a 35 ******************************************************************************
NYX 0:85b3fd62ea1a 36 */
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 /* Define to prevent recursive inclusion -------------------------------------*/
NYX 0:85b3fd62ea1a 39 #ifndef __STM32F4xx_HAL_SRAM_H
NYX 0:85b3fd62ea1a 40 #define __STM32F4xx_HAL_SRAM_H
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 43 extern "C" {
NYX 0:85b3fd62ea1a 44 #endif
NYX 0:85b3fd62ea1a 45
NYX 0:85b3fd62ea1a 46 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
NYX 0:85b3fd62ea1a 48 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 49 #include "stm32f4xx_ll_fsmc.h"
NYX 0:85b3fd62ea1a 50 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 51
NYX 0:85b3fd62ea1a 52 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
NYX 0:85b3fd62ea1a 53 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 54 #include "stm32f4xx_ll_fmc.h"
NYX 0:85b3fd62ea1a 55 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 56
NYX 0:85b3fd62ea1a 57
NYX 0:85b3fd62ea1a 58 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 59 * @{
NYX 0:85b3fd62ea1a 60 */
NYX 0:85b3fd62ea1a 61
NYX 0:85b3fd62ea1a 62 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
NYX 0:85b3fd62ea1a 63 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
NYX 0:85b3fd62ea1a 64 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
NYX 0:85b3fd62ea1a 65 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 66
NYX 0:85b3fd62ea1a 67 /** @addtogroup SRAM
NYX 0:85b3fd62ea1a 68 * @{
NYX 0:85b3fd62ea1a 69 */
NYX 0:85b3fd62ea1a 70
NYX 0:85b3fd62ea1a 71 /* Exported typedef ----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 72
NYX 0:85b3fd62ea1a 73 /** @defgroup SRAM_Exported_Types SRAM Exported Types
NYX 0:85b3fd62ea1a 74 * @{
NYX 0:85b3fd62ea1a 75 */
NYX 0:85b3fd62ea1a 76 /**
NYX 0:85b3fd62ea1a 77 * @brief HAL SRAM State structures definition
NYX 0:85b3fd62ea1a 78 */
NYX 0:85b3fd62ea1a 79 typedef enum
NYX 0:85b3fd62ea1a 80 {
NYX 0:85b3fd62ea1a 81 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
NYX 0:85b3fd62ea1a 82 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
NYX 0:85b3fd62ea1a 83 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
NYX 0:85b3fd62ea1a 84 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
NYX 0:85b3fd62ea1a 85 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
NYX 0:85b3fd62ea1a 86
NYX 0:85b3fd62ea1a 87 }HAL_SRAM_StateTypeDef;
NYX 0:85b3fd62ea1a 88
NYX 0:85b3fd62ea1a 89 /**
NYX 0:85b3fd62ea1a 90 * @brief SRAM handle Structure definition
NYX 0:85b3fd62ea1a 91 */
NYX 0:85b3fd62ea1a 92 typedef struct
NYX 0:85b3fd62ea1a 93 {
NYX 0:85b3fd62ea1a 94 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
NYX 0:85b3fd62ea1a 97
NYX 0:85b3fd62ea1a 98 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
NYX 0:85b3fd62ea1a 99
NYX 0:85b3fd62ea1a 100 HAL_LockTypeDef Lock; /*!< SRAM locking object */
NYX 0:85b3fd62ea1a 101
NYX 0:85b3fd62ea1a 102 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
NYX 0:85b3fd62ea1a 103
NYX 0:85b3fd62ea1a 104 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
NYX 0:85b3fd62ea1a 105
NYX 0:85b3fd62ea1a 106 }SRAM_HandleTypeDef;
NYX 0:85b3fd62ea1a 107
NYX 0:85b3fd62ea1a 108 /**
NYX 0:85b3fd62ea1a 109 * @}
NYX 0:85b3fd62ea1a 110 */
NYX 0:85b3fd62ea1a 111
NYX 0:85b3fd62ea1a 112 /* Exported constants --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 113 /* Exported macro ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
NYX 0:85b3fd62ea1a 116 * @{
NYX 0:85b3fd62ea1a 117 */
NYX 0:85b3fd62ea1a 118 /** @brief Reset SRAM handle state
NYX 0:85b3fd62ea1a 119 * @param __HANDLE__: SRAM handle
NYX 0:85b3fd62ea1a 120 * @retval None
NYX 0:85b3fd62ea1a 121 */
NYX 0:85b3fd62ea1a 122 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
NYX 0:85b3fd62ea1a 123
NYX 0:85b3fd62ea1a 124 /**
NYX 0:85b3fd62ea1a 125 * @}
NYX 0:85b3fd62ea1a 126 */
NYX 0:85b3fd62ea1a 127 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 128
NYX 0:85b3fd62ea1a 129 /** @addtogroup SRAM_Exported_Functions
NYX 0:85b3fd62ea1a 130 * @{
NYX 0:85b3fd62ea1a 131 */
NYX 0:85b3fd62ea1a 132
NYX 0:85b3fd62ea1a 133 /** @addtogroup SRAM_Exported_Functions_Group1
NYX 0:85b3fd62ea1a 134 * @{
NYX 0:85b3fd62ea1a 135 */
NYX 0:85b3fd62ea1a 136 /* Initialization/de-initialization functions **********************************/
NYX 0:85b3fd62ea1a 137 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
NYX 0:85b3fd62ea1a 138 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
NYX 0:85b3fd62ea1a 139 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
NYX 0:85b3fd62ea1a 140 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
NYX 0:85b3fd62ea1a 141
NYX 0:85b3fd62ea1a 142 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 143 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
NYX 0:85b3fd62ea1a 144 /**
NYX 0:85b3fd62ea1a 145 * @}
NYX 0:85b3fd62ea1a 146 */
NYX 0:85b3fd62ea1a 147
NYX 0:85b3fd62ea1a 148 /** @addtogroup SRAM_Exported_Functions_Group2
NYX 0:85b3fd62ea1a 149 * @{
NYX 0:85b3fd62ea1a 150 */
NYX 0:85b3fd62ea1a 151 /* I/O operation functions *****************************************************/
NYX 0:85b3fd62ea1a 152 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
NYX 0:85b3fd62ea1a 153 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
NYX 0:85b3fd62ea1a 154 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
NYX 0:85b3fd62ea1a 155 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
NYX 0:85b3fd62ea1a 156 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
NYX 0:85b3fd62ea1a 157 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
NYX 0:85b3fd62ea1a 158 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
NYX 0:85b3fd62ea1a 159 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
NYX 0:85b3fd62ea1a 160 /**
NYX 0:85b3fd62ea1a 161 * @}
NYX 0:85b3fd62ea1a 162 */
NYX 0:85b3fd62ea1a 163
NYX 0:85b3fd62ea1a 164 /** @addtogroup SRAM_Exported_Functions_Group3
NYX 0:85b3fd62ea1a 165 * @{
NYX 0:85b3fd62ea1a 166 */
NYX 0:85b3fd62ea1a 167 /* SRAM Control functions ******************************************************/
NYX 0:85b3fd62ea1a 168 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
NYX 0:85b3fd62ea1a 169 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
NYX 0:85b3fd62ea1a 170 /**
NYX 0:85b3fd62ea1a 171 * @}
NYX 0:85b3fd62ea1a 172 */
NYX 0:85b3fd62ea1a 173
NYX 0:85b3fd62ea1a 174 /** @addtogroup SRAM_Exported_Functions_Group4
NYX 0:85b3fd62ea1a 175 * @{
NYX 0:85b3fd62ea1a 176 */
NYX 0:85b3fd62ea1a 177 /* SRAM State functions *********************************************************/
NYX 0:85b3fd62ea1a 178 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
NYX 0:85b3fd62ea1a 179 /**
NYX 0:85b3fd62ea1a 180 * @}
NYX 0:85b3fd62ea1a 181 */
NYX 0:85b3fd62ea1a 182
NYX 0:85b3fd62ea1a 183 /**
NYX 0:85b3fd62ea1a 184 * @}
NYX 0:85b3fd62ea1a 185 */
NYX 0:85b3fd62ea1a 186
NYX 0:85b3fd62ea1a 187 /* Private types -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 188 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 189 /* Private constants ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 190 /* Private macros ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 191 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 192 /**
NYX 0:85b3fd62ea1a 193 * @}
NYX 0:85b3fd62ea1a 194 */
NYX 0:85b3fd62ea1a 195
NYX 0:85b3fd62ea1a 196 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
NYX 0:85b3fd62ea1a 197 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
NYX 0:85b3fd62ea1a 198 STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 199 /**
NYX 0:85b3fd62ea1a 200 * @}
NYX 0:85b3fd62ea1a 201 */
NYX 0:85b3fd62ea1a 202 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 203 }
NYX 0:85b3fd62ea1a 204 #endif
NYX 0:85b3fd62ea1a 205
NYX 0:85b3fd62ea1a 206 #endif /* __STM32F4xx_HAL_SRAM_H */
NYX 0:85b3fd62ea1a 207
NYX 0:85b3fd62ea1a 208 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/