Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_sram.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief SRAM HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides a generic firmware to drive SRAM memories
NYX 0:85b3fd62ea1a 9 * mounted as external device.
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 @verbatim
NYX 0:85b3fd62ea1a 12 ==============================================================================
NYX 0:85b3fd62ea1a 13 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 14 ==============================================================================
NYX 0:85b3fd62ea1a 15 [..]
NYX 0:85b3fd62ea1a 16 This driver is a generic layered driver which contains a set of APIs used to
NYX 0:85b3fd62ea1a 17 control SRAM memories. It uses the FMC layer functions to interface
NYX 0:85b3fd62ea1a 18 with SRAM devices.
NYX 0:85b3fd62ea1a 19 The following sequence should be followed to configure the FMC/FSMC to interface
NYX 0:85b3fd62ea1a 20 with SRAM/PSRAM memories:
NYX 0:85b3fd62ea1a 21
NYX 0:85b3fd62ea1a 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
NYX 0:85b3fd62ea1a 23 SRAM_HandleTypeDef hsram; and:
NYX 0:85b3fd62ea1a 24
NYX 0:85b3fd62ea1a 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
NYX 0:85b3fd62ea1a 26 values of the structure member.
NYX 0:85b3fd62ea1a 27
NYX 0:85b3fd62ea1a 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
NYX 0:85b3fd62ea1a 29 base register instance for NOR or SRAM device
NYX 0:85b3fd62ea1a 30
NYX 0:85b3fd62ea1a 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
NYX 0:85b3fd62ea1a 32 base register instance for NOR or SRAM extended mode
NYX 0:85b3fd62ea1a 33
NYX 0:85b3fd62ea1a 34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
NYX 0:85b3fd62ea1a 35 mode timings; for example:
NYX 0:85b3fd62ea1a 36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
NYX 0:85b3fd62ea1a 37 and fill its fields with the allowed values of the structure member.
NYX 0:85b3fd62ea1a 38
NYX 0:85b3fd62ea1a 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
NYX 0:85b3fd62ea1a 40 performs the following sequence:
NYX 0:85b3fd62ea1a 41
NYX 0:85b3fd62ea1a 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
NYX 0:85b3fd62ea1a 43 (##) Control register configuration using the FMC NORSRAM interface function
NYX 0:85b3fd62ea1a 44 FMC_NORSRAM_Init()
NYX 0:85b3fd62ea1a 45 (##) Timing register configuration using the FMC NORSRAM interface function
NYX 0:85b3fd62ea1a 46 FMC_NORSRAM_Timing_Init()
NYX 0:85b3fd62ea1a 47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
NYX 0:85b3fd62ea1a 48 FMC_NORSRAM_Extended_Timing_Init()
NYX 0:85b3fd62ea1a 49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
NYX 0:85b3fd62ea1a 50
NYX 0:85b3fd62ea1a 51 (#) At this stage you can perform read/write accesses from/to the memory connected
NYX 0:85b3fd62ea1a 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
NYX 0:85b3fd62ea1a 53 following APIs:
NYX 0:85b3fd62ea1a 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
NYX 0:85b3fd62ea1a 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
NYX 0:85b3fd62ea1a 56
NYX 0:85b3fd62ea1a 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
NYX 0:85b3fd62ea1a 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
NYX 0:85b3fd62ea1a 59
NYX 0:85b3fd62ea1a 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
NYX 0:85b3fd62ea1a 61 HAL_SRAM_GetState()
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63 @endverbatim
NYX 0:85b3fd62ea1a 64 ******************************************************************************
NYX 0:85b3fd62ea1a 65 * @attention
NYX 0:85b3fd62ea1a 66 *
NYX 0:85b3fd62ea1a 67 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 68 *
NYX 0:85b3fd62ea1a 69 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 70 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 71 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 72 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 74 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 75 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 77 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 78 * without specific prior written permission.
NYX 0:85b3fd62ea1a 79 *
NYX 0:85b3fd62ea1a 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 90 *
NYX 0:85b3fd62ea1a 91 ******************************************************************************
NYX 0:85b3fd62ea1a 92 */
NYX 0:85b3fd62ea1a 93
NYX 0:85b3fd62ea1a 94 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 95 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 96
NYX 0:85b3fd62ea1a 97 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 98 * @{
NYX 0:85b3fd62ea1a 99 */
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 /** @defgroup SRAM SRAM
NYX 0:85b3fd62ea1a 102 * @brief SRAM driver modules
NYX 0:85b3fd62ea1a 103 * @{
NYX 0:85b3fd62ea1a 104 */
NYX 0:85b3fd62ea1a 105 #ifdef HAL_SRAM_MODULE_ENABLED
NYX 0:85b3fd62ea1a 106
NYX 0:85b3fd62ea1a 107 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
NYX 0:85b3fd62ea1a 108 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
NYX 0:85b3fd62ea1a 109 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
NYX 0:85b3fd62ea1a 110 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
NYX 0:85b3fd62ea1a 111
NYX 0:85b3fd62ea1a 112 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 113 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 114 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 115 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 116 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 119 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
NYX 0:85b3fd62ea1a 120 * @{
NYX 0:85b3fd62ea1a 121 */
NYX 0:85b3fd62ea1a 122 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 123 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 124 *
NYX 0:85b3fd62ea1a 125 @verbatim
NYX 0:85b3fd62ea1a 126 ==============================================================================
NYX 0:85b3fd62ea1a 127 ##### SRAM Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 128 ==============================================================================
NYX 0:85b3fd62ea1a 129 [..] This section provides functions allowing to initialize/de-initialize
NYX 0:85b3fd62ea1a 130 the SRAM memory
NYX 0:85b3fd62ea1a 131
NYX 0:85b3fd62ea1a 132 @endverbatim
NYX 0:85b3fd62ea1a 133 * @{
NYX 0:85b3fd62ea1a 134 */
NYX 0:85b3fd62ea1a 135
NYX 0:85b3fd62ea1a 136 /**
NYX 0:85b3fd62ea1a 137 * @brief Performs the SRAM device initialization sequence
NYX 0:85b3fd62ea1a 138 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 139 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 140 * @param Timing: Pointer to SRAM control timing structure
NYX 0:85b3fd62ea1a 141 * @param ExtTiming: Pointer to SRAM extended mode timing structure
NYX 0:85b3fd62ea1a 142 * @retval HAL status
NYX 0:85b3fd62ea1a 143 */
NYX 0:85b3fd62ea1a 144 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
NYX 0:85b3fd62ea1a 145 {
NYX 0:85b3fd62ea1a 146 /* Check the SRAM handle parameter */
NYX 0:85b3fd62ea1a 147 if(hsram == NULL)
NYX 0:85b3fd62ea1a 148 {
NYX 0:85b3fd62ea1a 149 return HAL_ERROR;
NYX 0:85b3fd62ea1a 150 }
NYX 0:85b3fd62ea1a 151
NYX 0:85b3fd62ea1a 152 if(hsram->State == HAL_SRAM_STATE_RESET)
NYX 0:85b3fd62ea1a 153 {
NYX 0:85b3fd62ea1a 154 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 155 hsram->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 156 /* Initialize the low level hardware (MSP) */
NYX 0:85b3fd62ea1a 157 HAL_SRAM_MspInit(hsram);
NYX 0:85b3fd62ea1a 158 }
NYX 0:85b3fd62ea1a 159
NYX 0:85b3fd62ea1a 160 /* Initialize SRAM control Interface */
NYX 0:85b3fd62ea1a 161 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
NYX 0:85b3fd62ea1a 162
NYX 0:85b3fd62ea1a 163 /* Initialize SRAM timing Interface */
NYX 0:85b3fd62ea1a 164 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
NYX 0:85b3fd62ea1a 165
NYX 0:85b3fd62ea1a 166 /* Initialize SRAM extended mode timing Interface */
NYX 0:85b3fd62ea1a 167 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
NYX 0:85b3fd62ea1a 168
NYX 0:85b3fd62ea1a 169 /* Enable the NORSRAM device */
NYX 0:85b3fd62ea1a 170 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
NYX 0:85b3fd62ea1a 171
NYX 0:85b3fd62ea1a 172 return HAL_OK;
NYX 0:85b3fd62ea1a 173 }
NYX 0:85b3fd62ea1a 174
NYX 0:85b3fd62ea1a 175 /**
NYX 0:85b3fd62ea1a 176 * @brief Performs the SRAM device De-initialization sequence.
NYX 0:85b3fd62ea1a 177 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 178 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 179 * @retval HAL status
NYX 0:85b3fd62ea1a 180 */
NYX 0:85b3fd62ea1a 181 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
NYX 0:85b3fd62ea1a 182 {
NYX 0:85b3fd62ea1a 183 /* De-Initialize the low level hardware (MSP) */
NYX 0:85b3fd62ea1a 184 HAL_SRAM_MspDeInit(hsram);
NYX 0:85b3fd62ea1a 185
NYX 0:85b3fd62ea1a 186 /* Configure the SRAM registers with their reset values */
NYX 0:85b3fd62ea1a 187 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
NYX 0:85b3fd62ea1a 188
NYX 0:85b3fd62ea1a 189 hsram->State = HAL_SRAM_STATE_RESET;
NYX 0:85b3fd62ea1a 190
NYX 0:85b3fd62ea1a 191 /* Release Lock */
NYX 0:85b3fd62ea1a 192 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 193
NYX 0:85b3fd62ea1a 194 return HAL_OK;
NYX 0:85b3fd62ea1a 195 }
NYX 0:85b3fd62ea1a 196
NYX 0:85b3fd62ea1a 197 /**
NYX 0:85b3fd62ea1a 198 * @brief SRAM MSP Init.
NYX 0:85b3fd62ea1a 199 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 200 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 201 * @retval None
NYX 0:85b3fd62ea1a 202 */
NYX 0:85b3fd62ea1a 203 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
NYX 0:85b3fd62ea1a 204 {
NYX 0:85b3fd62ea1a 205 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 206 UNUSED(hsram);
NYX 0:85b3fd62ea1a 207 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 208 the HAL_SRAM_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 209 */
NYX 0:85b3fd62ea1a 210 }
NYX 0:85b3fd62ea1a 211
NYX 0:85b3fd62ea1a 212 /**
NYX 0:85b3fd62ea1a 213 * @brief SRAM MSP DeInit.
NYX 0:85b3fd62ea1a 214 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 215 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 216 * @retval None
NYX 0:85b3fd62ea1a 217 */
NYX 0:85b3fd62ea1a 218 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
NYX 0:85b3fd62ea1a 219 {
NYX 0:85b3fd62ea1a 220 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 221 UNUSED(hsram);
NYX 0:85b3fd62ea1a 222 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 223 the HAL_SRAM_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 224 */
NYX 0:85b3fd62ea1a 225 }
NYX 0:85b3fd62ea1a 226
NYX 0:85b3fd62ea1a 227 /**
NYX 0:85b3fd62ea1a 228 * @brief DMA transfer complete callback.
NYX 0:85b3fd62ea1a 229 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 230 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 231 * @retval None
NYX 0:85b3fd62ea1a 232 */
NYX 0:85b3fd62ea1a 233 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 234 {
NYX 0:85b3fd62ea1a 235 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 236 UNUSED(hdma);
NYX 0:85b3fd62ea1a 237 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 238 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 239 */
NYX 0:85b3fd62ea1a 240 }
NYX 0:85b3fd62ea1a 241
NYX 0:85b3fd62ea1a 242 /**
NYX 0:85b3fd62ea1a 243 * @brief DMA transfer complete error callback.
NYX 0:85b3fd62ea1a 244 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 245 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 246 * @retval None
NYX 0:85b3fd62ea1a 247 */
NYX 0:85b3fd62ea1a 248 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 249 {
NYX 0:85b3fd62ea1a 250 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 251 UNUSED(hdma);
NYX 0:85b3fd62ea1a 252 /* NOTE : This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 253 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 254 */
NYX 0:85b3fd62ea1a 255 }
NYX 0:85b3fd62ea1a 256
NYX 0:85b3fd62ea1a 257 /**
NYX 0:85b3fd62ea1a 258 * @}
NYX 0:85b3fd62ea1a 259 */
NYX 0:85b3fd62ea1a 260
NYX 0:85b3fd62ea1a 261 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions
NYX 0:85b3fd62ea1a 262 * @brief Input Output and memory control functions
NYX 0:85b3fd62ea1a 263 *
NYX 0:85b3fd62ea1a 264 @verbatim
NYX 0:85b3fd62ea1a 265 ==============================================================================
NYX 0:85b3fd62ea1a 266 ##### SRAM Input and Output functions #####
NYX 0:85b3fd62ea1a 267 ==============================================================================
NYX 0:85b3fd62ea1a 268 [..]
NYX 0:85b3fd62ea1a 269 This section provides functions allowing to use and control the SRAM memory
NYX 0:85b3fd62ea1a 270
NYX 0:85b3fd62ea1a 271 @endverbatim
NYX 0:85b3fd62ea1a 272 * @{
NYX 0:85b3fd62ea1a 273 */
NYX 0:85b3fd62ea1a 274
NYX 0:85b3fd62ea1a 275 /**
NYX 0:85b3fd62ea1a 276 * @brief Reads 8-bit buffer from SRAM memory.
NYX 0:85b3fd62ea1a 277 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 278 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 279 * @param pAddress: Pointer to read start address
NYX 0:85b3fd62ea1a 280 * @param pDstBuffer: Pointer to destination buffer
NYX 0:85b3fd62ea1a 281 * @param BufferSize: Size of the buffer to read from memory
NYX 0:85b3fd62ea1a 282 * @retval HAL status
NYX 0:85b3fd62ea1a 283 */
NYX 0:85b3fd62ea1a 284 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 285 {
NYX 0:85b3fd62ea1a 286 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
NYX 0:85b3fd62ea1a 287
NYX 0:85b3fd62ea1a 288 /* Process Locked */
NYX 0:85b3fd62ea1a 289 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 290
NYX 0:85b3fd62ea1a 291 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 292 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 293
NYX 0:85b3fd62ea1a 294 /* Read data from memory */
NYX 0:85b3fd62ea1a 295 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 296 {
NYX 0:85b3fd62ea1a 297 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
NYX 0:85b3fd62ea1a 298 pDstBuffer++;
NYX 0:85b3fd62ea1a 299 pSramAddress++;
NYX 0:85b3fd62ea1a 300 }
NYX 0:85b3fd62ea1a 301
NYX 0:85b3fd62ea1a 302 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 303 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 304
NYX 0:85b3fd62ea1a 305 /* Process unlocked */
NYX 0:85b3fd62ea1a 306 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 307
NYX 0:85b3fd62ea1a 308 return HAL_OK;
NYX 0:85b3fd62ea1a 309 }
NYX 0:85b3fd62ea1a 310
NYX 0:85b3fd62ea1a 311 /**
NYX 0:85b3fd62ea1a 312 * @brief Writes 8-bit buffer to SRAM memory.
NYX 0:85b3fd62ea1a 313 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 314 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 315 * @param pAddress: Pointer to write start address
NYX 0:85b3fd62ea1a 316 * @param pSrcBuffer: Pointer to source buffer to write
NYX 0:85b3fd62ea1a 317 * @param BufferSize: Size of the buffer to write to memory
NYX 0:85b3fd62ea1a 318 * @retval HAL status
NYX 0:85b3fd62ea1a 319 */
NYX 0:85b3fd62ea1a 320 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 321 {
NYX 0:85b3fd62ea1a 322 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
NYX 0:85b3fd62ea1a 323
NYX 0:85b3fd62ea1a 324 /* Check the SRAM controller state */
NYX 0:85b3fd62ea1a 325 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
NYX 0:85b3fd62ea1a 326 {
NYX 0:85b3fd62ea1a 327 return HAL_ERROR;
NYX 0:85b3fd62ea1a 328 }
NYX 0:85b3fd62ea1a 329
NYX 0:85b3fd62ea1a 330 /* Process Locked */
NYX 0:85b3fd62ea1a 331 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 332
NYX 0:85b3fd62ea1a 333 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 334 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 335
NYX 0:85b3fd62ea1a 336 /* Write data to memory */
NYX 0:85b3fd62ea1a 337 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 338 {
NYX 0:85b3fd62ea1a 339 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
NYX 0:85b3fd62ea1a 340 pSrcBuffer++;
NYX 0:85b3fd62ea1a 341 pSramAddress++;
NYX 0:85b3fd62ea1a 342 }
NYX 0:85b3fd62ea1a 343
NYX 0:85b3fd62ea1a 344 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 345 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 346
NYX 0:85b3fd62ea1a 347 /* Process unlocked */
NYX 0:85b3fd62ea1a 348 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 349
NYX 0:85b3fd62ea1a 350 return HAL_OK;
NYX 0:85b3fd62ea1a 351 }
NYX 0:85b3fd62ea1a 352
NYX 0:85b3fd62ea1a 353 /**
NYX 0:85b3fd62ea1a 354 * @brief Reads 16-bit buffer from SRAM memory.
NYX 0:85b3fd62ea1a 355 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 356 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 357 * @param pAddress: Pointer to read start address
NYX 0:85b3fd62ea1a 358 * @param pDstBuffer: Pointer to destination buffer
NYX 0:85b3fd62ea1a 359 * @param BufferSize: Size of the buffer to read from memory
NYX 0:85b3fd62ea1a 360 * @retval HAL status
NYX 0:85b3fd62ea1a 361 */
NYX 0:85b3fd62ea1a 362 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 363 {
NYX 0:85b3fd62ea1a 364 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
NYX 0:85b3fd62ea1a 365
NYX 0:85b3fd62ea1a 366 /* Process Locked */
NYX 0:85b3fd62ea1a 367 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 368
NYX 0:85b3fd62ea1a 369 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 370 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 371
NYX 0:85b3fd62ea1a 372 /* Read data from memory */
NYX 0:85b3fd62ea1a 373 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 374 {
NYX 0:85b3fd62ea1a 375 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
NYX 0:85b3fd62ea1a 376 pDstBuffer++;
NYX 0:85b3fd62ea1a 377 pSramAddress++;
NYX 0:85b3fd62ea1a 378 }
NYX 0:85b3fd62ea1a 379
NYX 0:85b3fd62ea1a 380 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 381 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 382
NYX 0:85b3fd62ea1a 383 /* Process unlocked */
NYX 0:85b3fd62ea1a 384 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 return HAL_OK;
NYX 0:85b3fd62ea1a 387 }
NYX 0:85b3fd62ea1a 388
NYX 0:85b3fd62ea1a 389 /**
NYX 0:85b3fd62ea1a 390 * @brief Writes 16-bit buffer to SRAM memory.
NYX 0:85b3fd62ea1a 391 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 392 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 393 * @param pAddress: Pointer to write start address
NYX 0:85b3fd62ea1a 394 * @param pSrcBuffer: Pointer to source buffer to write
NYX 0:85b3fd62ea1a 395 * @param BufferSize: Size of the buffer to write to memory
NYX 0:85b3fd62ea1a 396 * @retval HAL status
NYX 0:85b3fd62ea1a 397 */
NYX 0:85b3fd62ea1a 398 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 399 {
NYX 0:85b3fd62ea1a 400 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
NYX 0:85b3fd62ea1a 401
NYX 0:85b3fd62ea1a 402 /* Check the SRAM controller state */
NYX 0:85b3fd62ea1a 403 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
NYX 0:85b3fd62ea1a 404 {
NYX 0:85b3fd62ea1a 405 return HAL_ERROR;
NYX 0:85b3fd62ea1a 406 }
NYX 0:85b3fd62ea1a 407
NYX 0:85b3fd62ea1a 408 /* Process Locked */
NYX 0:85b3fd62ea1a 409 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 410
NYX 0:85b3fd62ea1a 411 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 412 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 413
NYX 0:85b3fd62ea1a 414 /* Write data to memory */
NYX 0:85b3fd62ea1a 415 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 416 {
NYX 0:85b3fd62ea1a 417 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
NYX 0:85b3fd62ea1a 418 pSrcBuffer++;
NYX 0:85b3fd62ea1a 419 pSramAddress++;
NYX 0:85b3fd62ea1a 420 }
NYX 0:85b3fd62ea1a 421
NYX 0:85b3fd62ea1a 422 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 423 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 424
NYX 0:85b3fd62ea1a 425 /* Process unlocked */
NYX 0:85b3fd62ea1a 426 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 return HAL_OK;
NYX 0:85b3fd62ea1a 429 }
NYX 0:85b3fd62ea1a 430
NYX 0:85b3fd62ea1a 431 /**
NYX 0:85b3fd62ea1a 432 * @brief Reads 32-bit buffer from SRAM memory.
NYX 0:85b3fd62ea1a 433 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 434 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 435 * @param pAddress: Pointer to read start address
NYX 0:85b3fd62ea1a 436 * @param pDstBuffer: Pointer to destination buffer
NYX 0:85b3fd62ea1a 437 * @param BufferSize: Size of the buffer to read from memory
NYX 0:85b3fd62ea1a 438 * @retval HAL status
NYX 0:85b3fd62ea1a 439 */
NYX 0:85b3fd62ea1a 440 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 441 {
NYX 0:85b3fd62ea1a 442 /* Process Locked */
NYX 0:85b3fd62ea1a 443 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 444
NYX 0:85b3fd62ea1a 445 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 446 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 447
NYX 0:85b3fd62ea1a 448 /* Read data from memory */
NYX 0:85b3fd62ea1a 449 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 450 {
NYX 0:85b3fd62ea1a 451 *pDstBuffer = *(__IO uint32_t *)pAddress;
NYX 0:85b3fd62ea1a 452 pDstBuffer++;
NYX 0:85b3fd62ea1a 453 pAddress++;
NYX 0:85b3fd62ea1a 454 }
NYX 0:85b3fd62ea1a 455
NYX 0:85b3fd62ea1a 456 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 457 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 458
NYX 0:85b3fd62ea1a 459 /* Process unlocked */
NYX 0:85b3fd62ea1a 460 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 461
NYX 0:85b3fd62ea1a 462 return HAL_OK;
NYX 0:85b3fd62ea1a 463 }
NYX 0:85b3fd62ea1a 464
NYX 0:85b3fd62ea1a 465 /**
NYX 0:85b3fd62ea1a 466 * @brief Writes 32-bit buffer to SRAM memory.
NYX 0:85b3fd62ea1a 467 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 468 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 469 * @param pAddress: Pointer to write start address
NYX 0:85b3fd62ea1a 470 * @param pSrcBuffer: Pointer to source buffer to write
NYX 0:85b3fd62ea1a 471 * @param BufferSize: Size of the buffer to write to memory
NYX 0:85b3fd62ea1a 472 * @retval HAL status
NYX 0:85b3fd62ea1a 473 */
NYX 0:85b3fd62ea1a 474 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 475 {
NYX 0:85b3fd62ea1a 476 /* Check the SRAM controller state */
NYX 0:85b3fd62ea1a 477 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
NYX 0:85b3fd62ea1a 478 {
NYX 0:85b3fd62ea1a 479 return HAL_ERROR;
NYX 0:85b3fd62ea1a 480 }
NYX 0:85b3fd62ea1a 481
NYX 0:85b3fd62ea1a 482 /* Process Locked */
NYX 0:85b3fd62ea1a 483 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 484
NYX 0:85b3fd62ea1a 485 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 486 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 487
NYX 0:85b3fd62ea1a 488 /* Write data to memory */
NYX 0:85b3fd62ea1a 489 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 490 {
NYX 0:85b3fd62ea1a 491 *(__IO uint32_t *)pAddress = *pSrcBuffer;
NYX 0:85b3fd62ea1a 492 pSrcBuffer++;
NYX 0:85b3fd62ea1a 493 pAddress++;
NYX 0:85b3fd62ea1a 494 }
NYX 0:85b3fd62ea1a 495
NYX 0:85b3fd62ea1a 496 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 497 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 498
NYX 0:85b3fd62ea1a 499 /* Process unlocked */
NYX 0:85b3fd62ea1a 500 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 501
NYX 0:85b3fd62ea1a 502 return HAL_OK;
NYX 0:85b3fd62ea1a 503 }
NYX 0:85b3fd62ea1a 504
NYX 0:85b3fd62ea1a 505 /**
NYX 0:85b3fd62ea1a 506 * @brief Reads a Words data from the SRAM memory using DMA transfer.
NYX 0:85b3fd62ea1a 507 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 508 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 509 * @param pAddress: Pointer to read start address
NYX 0:85b3fd62ea1a 510 * @param pDstBuffer: Pointer to destination buffer
NYX 0:85b3fd62ea1a 511 * @param BufferSize: Size of the buffer to read from memory
NYX 0:85b3fd62ea1a 512 * @retval HAL status
NYX 0:85b3fd62ea1a 513 */
NYX 0:85b3fd62ea1a 514 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 515 {
NYX 0:85b3fd62ea1a 516 /* Process Locked */
NYX 0:85b3fd62ea1a 517 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 518
NYX 0:85b3fd62ea1a 519 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 520 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 521
NYX 0:85b3fd62ea1a 522 /* Configure DMA user callbacks */
NYX 0:85b3fd62ea1a 523 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
NYX 0:85b3fd62ea1a 524 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
NYX 0:85b3fd62ea1a 525
NYX 0:85b3fd62ea1a 526 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 527 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
NYX 0:85b3fd62ea1a 528
NYX 0:85b3fd62ea1a 529 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 530 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 531
NYX 0:85b3fd62ea1a 532 /* Process unlocked */
NYX 0:85b3fd62ea1a 533 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 534
NYX 0:85b3fd62ea1a 535 return HAL_OK;
NYX 0:85b3fd62ea1a 536 }
NYX 0:85b3fd62ea1a 537
NYX 0:85b3fd62ea1a 538 /**
NYX 0:85b3fd62ea1a 539 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
NYX 0:85b3fd62ea1a 540 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 541 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 542 * @param pAddress: Pointer to write start address
NYX 0:85b3fd62ea1a 543 * @param pSrcBuffer: Pointer to source buffer to write
NYX 0:85b3fd62ea1a 544 * @param BufferSize: Size of the buffer to write to memory
NYX 0:85b3fd62ea1a 545 * @retval HAL status
NYX 0:85b3fd62ea1a 546 */
NYX 0:85b3fd62ea1a 547 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 548 {
NYX 0:85b3fd62ea1a 549 /* Check the SRAM controller state */
NYX 0:85b3fd62ea1a 550 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
NYX 0:85b3fd62ea1a 551 {
NYX 0:85b3fd62ea1a 552 return HAL_ERROR;
NYX 0:85b3fd62ea1a 553 }
NYX 0:85b3fd62ea1a 554
NYX 0:85b3fd62ea1a 555 /* Process Locked */
NYX 0:85b3fd62ea1a 556 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 557
NYX 0:85b3fd62ea1a 558 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 559 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 560
NYX 0:85b3fd62ea1a 561 /* Configure DMA user callbacks */
NYX 0:85b3fd62ea1a 562 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
NYX 0:85b3fd62ea1a 563 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
NYX 0:85b3fd62ea1a 564
NYX 0:85b3fd62ea1a 565 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 566 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
NYX 0:85b3fd62ea1a 567
NYX 0:85b3fd62ea1a 568 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 569 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 570
NYX 0:85b3fd62ea1a 571 /* Process unlocked */
NYX 0:85b3fd62ea1a 572 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 573
NYX 0:85b3fd62ea1a 574 return HAL_OK;
NYX 0:85b3fd62ea1a 575 }
NYX 0:85b3fd62ea1a 576
NYX 0:85b3fd62ea1a 577 /**
NYX 0:85b3fd62ea1a 578 * @}
NYX 0:85b3fd62ea1a 579 */
NYX 0:85b3fd62ea1a 580
NYX 0:85b3fd62ea1a 581 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
NYX 0:85b3fd62ea1a 582 * @brief management functions
NYX 0:85b3fd62ea1a 583 *
NYX 0:85b3fd62ea1a 584 @verbatim
NYX 0:85b3fd62ea1a 585 ==============================================================================
NYX 0:85b3fd62ea1a 586 ##### SRAM Control functions #####
NYX 0:85b3fd62ea1a 587 ==============================================================================
NYX 0:85b3fd62ea1a 588 [..]
NYX 0:85b3fd62ea1a 589 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 590 the SRAM interface.
NYX 0:85b3fd62ea1a 591
NYX 0:85b3fd62ea1a 592 @endverbatim
NYX 0:85b3fd62ea1a 593 * @{
NYX 0:85b3fd62ea1a 594 */
NYX 0:85b3fd62ea1a 595
NYX 0:85b3fd62ea1a 596 /**
NYX 0:85b3fd62ea1a 597 * @brief Enables dynamically SRAM write operation.
NYX 0:85b3fd62ea1a 598 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 599 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 600 * @retval HAL status
NYX 0:85b3fd62ea1a 601 */
NYX 0:85b3fd62ea1a 602 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
NYX 0:85b3fd62ea1a 603 {
NYX 0:85b3fd62ea1a 604 /* Process Locked */
NYX 0:85b3fd62ea1a 605 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 606
NYX 0:85b3fd62ea1a 607 /* Enable write operation */
NYX 0:85b3fd62ea1a 608 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
NYX 0:85b3fd62ea1a 609
NYX 0:85b3fd62ea1a 610 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 611 hsram->State = HAL_SRAM_STATE_READY;
NYX 0:85b3fd62ea1a 612
NYX 0:85b3fd62ea1a 613 /* Process unlocked */
NYX 0:85b3fd62ea1a 614 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 615
NYX 0:85b3fd62ea1a 616 return HAL_OK;
NYX 0:85b3fd62ea1a 617 }
NYX 0:85b3fd62ea1a 618
NYX 0:85b3fd62ea1a 619 /**
NYX 0:85b3fd62ea1a 620 * @brief Disables dynamically SRAM write operation.
NYX 0:85b3fd62ea1a 621 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 622 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 623 * @retval HAL status
NYX 0:85b3fd62ea1a 624 */
NYX 0:85b3fd62ea1a 625 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
NYX 0:85b3fd62ea1a 626 {
NYX 0:85b3fd62ea1a 627 /* Process Locked */
NYX 0:85b3fd62ea1a 628 __HAL_LOCK(hsram);
NYX 0:85b3fd62ea1a 629
NYX 0:85b3fd62ea1a 630 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 631 hsram->State = HAL_SRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 632
NYX 0:85b3fd62ea1a 633 /* Disable write operation */
NYX 0:85b3fd62ea1a 634 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
NYX 0:85b3fd62ea1a 635
NYX 0:85b3fd62ea1a 636 /* Update the SRAM controller state */
NYX 0:85b3fd62ea1a 637 hsram->State = HAL_SRAM_STATE_PROTECTED;
NYX 0:85b3fd62ea1a 638
NYX 0:85b3fd62ea1a 639 /* Process unlocked */
NYX 0:85b3fd62ea1a 640 __HAL_UNLOCK(hsram);
NYX 0:85b3fd62ea1a 641
NYX 0:85b3fd62ea1a 642 return HAL_OK;
NYX 0:85b3fd62ea1a 643 }
NYX 0:85b3fd62ea1a 644
NYX 0:85b3fd62ea1a 645 /**
NYX 0:85b3fd62ea1a 646 * @}
NYX 0:85b3fd62ea1a 647 */
NYX 0:85b3fd62ea1a 648
NYX 0:85b3fd62ea1a 649 /** @defgroup SRAM_Exported_Functions_Group4 State functions
NYX 0:85b3fd62ea1a 650 * @brief Peripheral State functions
NYX 0:85b3fd62ea1a 651 *
NYX 0:85b3fd62ea1a 652 @verbatim
NYX 0:85b3fd62ea1a 653 ==============================================================================
NYX 0:85b3fd62ea1a 654 ##### SRAM State functions #####
NYX 0:85b3fd62ea1a 655 ==============================================================================
NYX 0:85b3fd62ea1a 656 [..]
NYX 0:85b3fd62ea1a 657 This subsection permits to get in run-time the status of the SRAM controller
NYX 0:85b3fd62ea1a 658 and the data flow.
NYX 0:85b3fd62ea1a 659
NYX 0:85b3fd62ea1a 660 @endverbatim
NYX 0:85b3fd62ea1a 661 * @{
NYX 0:85b3fd62ea1a 662 */
NYX 0:85b3fd62ea1a 663
NYX 0:85b3fd62ea1a 664 /**
NYX 0:85b3fd62ea1a 665 * @brief Returns the SRAM controller state
NYX 0:85b3fd62ea1a 666 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 667 * the configuration information for SRAM module.
NYX 0:85b3fd62ea1a 668 * @retval HAL state
NYX 0:85b3fd62ea1a 669 */
NYX 0:85b3fd62ea1a 670 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
NYX 0:85b3fd62ea1a 671 {
NYX 0:85b3fd62ea1a 672 return hsram->State;
NYX 0:85b3fd62ea1a 673 }
NYX 0:85b3fd62ea1a 674 /**
NYX 0:85b3fd62ea1a 675 * @}
NYX 0:85b3fd62ea1a 676 */
NYX 0:85b3fd62ea1a 677
NYX 0:85b3fd62ea1a 678 /**
NYX 0:85b3fd62ea1a 679 * @}
NYX 0:85b3fd62ea1a 680 */
NYX 0:85b3fd62ea1a 681 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
NYX 0:85b3fd62ea1a 682 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
NYX 0:85b3fd62ea1a 683 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
NYX 0:85b3fd62ea1a 684 #endif /* HAL_SRAM_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 685 /**
NYX 0:85b3fd62ea1a 686 * @}
NYX 0:85b3fd62ea1a 687 */
NYX 0:85b3fd62ea1a 688
NYX 0:85b3fd62ea1a 689 /**
NYX 0:85b3fd62ea1a 690 * @}
NYX 0:85b3fd62ea1a 691 */
NYX 0:85b3fd62ea1a 692
NYX 0:85b3fd62ea1a 693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/