mbed-dev - inport from local

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inport from local

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/**
NYX	0:85b3fd62ea1a	2	******************************************************************************
NYX	0:85b3fd62ea1a	3	* @file stm32f4xx_hal_spi.c
NYX	0:85b3fd62ea1a	4	* @author MCD Application Team
NYX	0:85b3fd62ea1a	5	* @version V1.7.1
NYX	0:85b3fd62ea1a	6	* @date 14-April-2017
NYX	0:85b3fd62ea1a	7	* @brief SPI HAL module driver.
NYX	0:85b3fd62ea1a	8	* This file provides firmware functions to manage the following
NYX	0:85b3fd62ea1a	9	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
NYX	0:85b3fd62ea1a	10	* + Initialization and de-initialization functions
NYX	0:85b3fd62ea1a	11	* + IO operation functions
NYX	0:85b3fd62ea1a	12	* + Peripheral Control functions
NYX	0:85b3fd62ea1a	13	* + Peripheral State functions
NYX	0:85b3fd62ea1a	14	*
NYX	0:85b3fd62ea1a	15	@verbatim
NYX	0:85b3fd62ea1a	16	==============================================================================
NYX	0:85b3fd62ea1a	17	##### How to use this driver #####
NYX	0:85b3fd62ea1a	18	==============================================================================
NYX	0:85b3fd62ea1a	19	[..]
NYX	0:85b3fd62ea1a	20	The SPI HAL driver can be used as follows:
NYX	0:85b3fd62ea1a	21
NYX	0:85b3fd62ea1a	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
NYX	0:85b3fd62ea1a	23	SPI_HandleTypeDef hspi;
NYX	0:85b3fd62ea1a	24
NYX	0:85b3fd62ea1a	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
NYX	0:85b3fd62ea1a	26	(##) Enable the SPIx interface clock
NYX	0:85b3fd62ea1a	27	(##) SPI pins configuration
NYX	0:85b3fd62ea1a	28	(+++) Enable the clock for the SPI GPIOs
NYX	0:85b3fd62ea1a	29	(+++) Configure these SPI pins as alternate function push-pull
NYX	0:85b3fd62ea1a	30	(##) NVIC configuration if you need to use interrupt process
NYX	0:85b3fd62ea1a	31	(+++) Configure the SPIx interrupt priority
NYX	0:85b3fd62ea1a	32	(+++) Enable the NVIC SPI IRQ handle
NYX	0:85b3fd62ea1a	33	(##) DMA Configuration if you need to use DMA process
NYX	0:85b3fd62ea1a	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
NYX	0:85b3fd62ea1a	35	(+++) Enable the DMAx clock
NYX	0:85b3fd62ea1a	36	(+++) Configure the DMA handle parameters
NYX	0:85b3fd62ea1a	37	(+++) Configure the DMA Tx or Rx stream
NYX	0:85b3fd62ea1a	38	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
NYX	0:85b3fd62ea1a	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream
NYX	0:85b3fd62ea1a	40
NYX	0:85b3fd62ea1a	41	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
NYX	0:85b3fd62ea1a	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
NYX	0:85b3fd62ea1a	43
NYX	0:85b3fd62ea1a	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
NYX	0:85b3fd62ea1a	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
NYX	0:85b3fd62ea1a	46	by calling the customized HAL_SPI_MspInit() API.
NYX	0:85b3fd62ea1a	47	[..]
NYX	0:85b3fd62ea1a	48	Circular mode restriction:
NYX	0:85b3fd62ea1a	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
NYX	0:85b3fd62ea1a	50	(##) Master 2Lines RxOnly
NYX	0:85b3fd62ea1a	51	(##) Master 1Line Rx
NYX	0:85b3fd62ea1a	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
NYX	0:85b3fd62ea1a	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
NYX	0:85b3fd62ea1a	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
NYX	0:85b3fd62ea1a	55	[..]
NYX	0:85b3fd62ea1a	56	Master Receive mode restriction:
NYX	0:85b3fd62ea1a	57	(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
NYX	0:85b3fd62ea1a	58	bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
NYX	0:85b3fd62ea1a	59	does not initiate a new transfer the following procedure has to be respected:
NYX	0:85b3fd62ea1a	60	(##) HAL_SPI_DeInit()
NYX	0:85b3fd62ea1a	61	(##) HAL_SPI_Init()
NYX	0:85b3fd62ea1a	62
NYX	0:85b3fd62ea1a	63	@endverbatim
NYX	0:85b3fd62ea1a	64
NYX	0:85b3fd62ea1a	65	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
NYX	0:85b3fd62ea1a	66	the following tables resume the max SPI frequency reached with data size 8bits/16bits,
NYX	0:85b3fd62ea1a	67	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
NYX	0:85b3fd62ea1a	68
NYX	0:85b3fd62ea1a	69	DataSize = SPI_DATASIZE_8BIT:
NYX	0:85b3fd62ea1a	70	+----------------------------------------------------------------------------------------------+
NYX	0:85b3fd62ea1a	71	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
NYX	0:85b3fd62ea1a	72	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
NYX	0:85b3fd62ea1a	73	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
NYX	0:85b3fd62ea1a	74	\|==============================================================================================\|
NYX	0:85b3fd62ea1a	75	\| T \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
NYX	0:85b3fd62ea1a	76	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	77	\| / \| Interrupt \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
NYX	0:85b3fd62ea1a	78	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	79	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
NYX	0:85b3fd62ea1a	80	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
NYX	0:85b3fd62ea1a	81	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
NYX	0:85b3fd62ea1a	82	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	83	\| R \| Interrupt \| Fpclk/8 \| Fpclk/8 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
NYX	0:85b3fd62ea1a	84	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	85	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/128 \| Fpclk/2 \|
NYX	0:85b3fd62ea1a	86	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
NYX	0:85b3fd62ea1a	87	\| \| Polling \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
NYX	0:85b3fd62ea1a	88	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	89	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
NYX	0:85b3fd62ea1a	90	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	91	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/128\|
NYX	0:85b3fd62ea1a	92	+----------------------------------------------------------------------------------------------+
NYX	0:85b3fd62ea1a	93
NYX	0:85b3fd62ea1a	94	DataSize = SPI_DATASIZE_16BIT:
NYX	0:85b3fd62ea1a	95	+----------------------------------------------------------------------------------------------+
NYX	0:85b3fd62ea1a	96	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
NYX	0:85b3fd62ea1a	97	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
NYX	0:85b3fd62ea1a	98	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
NYX	0:85b3fd62ea1a	99	\|==============================================================================================\|
NYX	0:85b3fd62ea1a	100	\| T \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
NYX	0:85b3fd62ea1a	101	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	102	\| / \| Interrupt \| Fpclk/4 \| Fpclk/4 \| NA \| NA \| NA \| NA \|
NYX	0:85b3fd62ea1a	103	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	104	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
NYX	0:85b3fd62ea1a	105	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
NYX	0:85b3fd62ea1a	106	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/32 \| Fpclk/2 \|
NYX	0:85b3fd62ea1a	107	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	108	\| R \| Interrupt \| Fpclk/4 \| Fpclk/4 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
NYX	0:85b3fd62ea1a	109	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	110	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/128 \| Fpclk/2 \|
NYX	0:85b3fd62ea1a	111	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
NYX	0:85b3fd62ea1a	112	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/32 \|
NYX	0:85b3fd62ea1a	113	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	114	\| T \| Interrupt \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
NYX	0:85b3fd62ea1a	115	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
NYX	0:85b3fd62ea1a	116	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/128\|
NYX	0:85b3fd62ea1a	117	+----------------------------------------------------------------------------------------------+
NYX	0:85b3fd62ea1a	118	[..]
NYX	0:85b3fd62ea1a	119	(@) The max SPI frequency depend on SPI data size (8bits, 16bits),
NYX	0:85b3fd62ea1a	120	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
NYX	0:85b3fd62ea1a	121	(@)
NYX	0:85b3fd62ea1a	122	(+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
NYX	0:85b3fd62ea1a	123	(+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
NYX	0:85b3fd62ea1a	124	(+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
NYX	0:85b3fd62ea1a	125	******************************************************************************
NYX	0:85b3fd62ea1a	126	* @attention
NYX	0:85b3fd62ea1a	127	*
NYX	0:85b3fd62ea1a	128	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX	0:85b3fd62ea1a	129	*
NYX	0:85b3fd62ea1a	130	* Redistribution and use in source and binary forms, with or without modification,
NYX	0:85b3fd62ea1a	131	* are permitted provided that the following conditions are met:
NYX	0:85b3fd62ea1a	132	* 1. Redistributions of source code must retain the above copyright notice,
NYX	0:85b3fd62ea1a	133	* this list of conditions and the following disclaimer.
NYX	0:85b3fd62ea1a	134	* 2. Redistributions in binary form must reproduce the above copyright notice,
NYX	0:85b3fd62ea1a	135	* this list of conditions and the following disclaimer in the documentation
NYX	0:85b3fd62ea1a	136	* and/or other materials provided with the distribution.
NYX	0:85b3fd62ea1a	137	* 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX	0:85b3fd62ea1a	138	* may be used to endorse or promote products derived from this software
NYX	0:85b3fd62ea1a	139	* without specific prior written permission.
NYX	0:85b3fd62ea1a	140	*
NYX	0:85b3fd62ea1a	141	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX	0:85b3fd62ea1a	142	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX	0:85b3fd62ea1a	143	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX	0:85b3fd62ea1a	144	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX	0:85b3fd62ea1a	145	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX	0:85b3fd62ea1a	146	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX	0:85b3fd62ea1a	147	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX	0:85b3fd62ea1a	148	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX	0:85b3fd62ea1a	149	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX	0:85b3fd62ea1a	150	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX	0:85b3fd62ea1a	151	*
NYX	0:85b3fd62ea1a	152	******************************************************************************
NYX	0:85b3fd62ea1a	153	*/
NYX	0:85b3fd62ea1a	154
NYX	0:85b3fd62ea1a	155	/* Includes ------------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	156	#include "stm32f4xx_hal.h"
NYX	0:85b3fd62ea1a	157
NYX	0:85b3fd62ea1a	158	/** @addtogroup STM32F4xx_HAL_Driver
NYX	0:85b3fd62ea1a	159	* @{
NYX	0:85b3fd62ea1a	160	*/
NYX	0:85b3fd62ea1a	161	/** @defgroup SPI SPI
NYX	0:85b3fd62ea1a	162	* @brief SPI HAL module driver
NYX	0:85b3fd62ea1a	163	* @{
NYX	0:85b3fd62ea1a	164	*/
NYX	0:85b3fd62ea1a	165	#ifdef HAL_SPI_MODULE_ENABLED
NYX	0:85b3fd62ea1a	166
NYX	0:85b3fd62ea1a	167	/* Private typedef -----------------------------------------------------------*/
NYX	0:85b3fd62ea1a	168	/* Private defines -----------------------------------------------------------*/
NYX	0:85b3fd62ea1a	169	/** @defgroup SPI_Private_Constants SPI Private Constants
NYX	0:85b3fd62ea1a	170	* @{
NYX	0:85b3fd62ea1a	171	*/
NYX	0:85b3fd62ea1a	172	#define SPI_DEFAULT_TIMEOUT 100U
NYX	0:85b3fd62ea1a	173	/**
NYX	0:85b3fd62ea1a	174	* @}
NYX	0:85b3fd62ea1a	175	*/
NYX	0:85b3fd62ea1a	176
NYX	0:85b3fd62ea1a	177	/* Private macros ------------------------------------------------------------*/
NYX	0:85b3fd62ea1a	178	/* Private variables ---------------------------------------------------------*/
NYX	0:85b3fd62ea1a	179	/* Private function prototypes -----------------------------------------------*/
NYX	0:85b3fd62ea1a	180	/** @addtogroup SPI_Private_Functions
NYX	0:85b3fd62ea1a	181	* @{
NYX	0:85b3fd62ea1a	182	*/
NYX	0:85b3fd62ea1a	183	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	184	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	185	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	186	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	187	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	188	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	189	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	190	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	191	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	192	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
NYX	0:85b3fd62ea1a	193	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
NYX	0:85b3fd62ea1a	194	static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
NYX	0:85b3fd62ea1a	195	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	196	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	197	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	198	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	199	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	200	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	201	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	202	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	203	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	204	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	205	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	206	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	207	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	208	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	209	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	210	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	211	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	212	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	213	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
NYX	0:85b3fd62ea1a	214	static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
NYX	0:85b3fd62ea1a	215	/**
NYX	0:85b3fd62ea1a	216	* @}
NYX	0:85b3fd62ea1a	217	*/
NYX	0:85b3fd62ea1a	218
NYX	0:85b3fd62ea1a	219	/* Exported functions --------------------------------------------------------*/
NYX	0:85b3fd62ea1a	220	/** @defgroup SPI_Exported_Functions SPI Exported Functions
NYX	0:85b3fd62ea1a	221	* @{
NYX	0:85b3fd62ea1a	222	*/
NYX	0:85b3fd62ea1a	223
NYX	0:85b3fd62ea1a	224	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
NYX	0:85b3fd62ea1a	225	* @brief Initialization and Configuration functions
NYX	0:85b3fd62ea1a	226	*
NYX	0:85b3fd62ea1a	227	@verbatim
NYX	0:85b3fd62ea1a	228	===============================================================================
NYX	0:85b3fd62ea1a	229	##### Initialization and de-initialization functions #####
NYX	0:85b3fd62ea1a	230	===============================================================================
NYX	0:85b3fd62ea1a	231	[..] This subsection provides a set of functions allowing to initialize and
NYX	0:85b3fd62ea1a	232	de-initialize the SPIx peripheral:
NYX	0:85b3fd62ea1a	233
NYX	0:85b3fd62ea1a	234	(+) User must implement HAL_SPI_MspInit() function in which he configures
NYX	0:85b3fd62ea1a	235	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
NYX	0:85b3fd62ea1a	236
NYX	0:85b3fd62ea1a	237	(+) Call the function HAL_SPI_Init() to configure the selected device with
NYX	0:85b3fd62ea1a	238	the selected configuration:
NYX	0:85b3fd62ea1a	239	(++) Mode
NYX	0:85b3fd62ea1a	240	(++) Direction
NYX	0:85b3fd62ea1a	241	(++) Data Size
NYX	0:85b3fd62ea1a	242	(++) Clock Polarity and Phase
NYX	0:85b3fd62ea1a	243	(++) NSS Management
NYX	0:85b3fd62ea1a	244	(++) BaudRate Prescaler
NYX	0:85b3fd62ea1a	245	(++) FirstBit
NYX	0:85b3fd62ea1a	246	(++) TIMode
NYX	0:85b3fd62ea1a	247	(++) CRC Calculation
NYX	0:85b3fd62ea1a	248	(++) CRC Polynomial if CRC enabled
NYX	0:85b3fd62ea1a	249
NYX	0:85b3fd62ea1a	250	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
NYX	0:85b3fd62ea1a	251	of the selected SPIx peripheral.
NYX	0:85b3fd62ea1a	252
NYX	0:85b3fd62ea1a	253	@endverbatim
NYX	0:85b3fd62ea1a	254	* @{
NYX	0:85b3fd62ea1a	255	*/
NYX	0:85b3fd62ea1a	256
NYX	0:85b3fd62ea1a	257	/**
NYX	0:85b3fd62ea1a	258	* @brief Initialize the SPI according to the specified parameters
NYX	0:85b3fd62ea1a	259	* in the SPI_InitTypeDef and initialize the associated handle.
NYX	0:85b3fd62ea1a	260	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	261	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	262	* @retval HAL status
NYX	0:85b3fd62ea1a	263	*/
NYX	0:85b3fd62ea1a	264	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	265	{
NYX	0:85b3fd62ea1a	266	/* Check the SPI handle allocation */
NYX	0:85b3fd62ea1a	267	if(hspi == NULL)
NYX	0:85b3fd62ea1a	268	{
NYX	0:85b3fd62ea1a	269	return HAL_ERROR;
NYX	0:85b3fd62ea1a	270	}
NYX	0:85b3fd62ea1a	271
NYX	0:85b3fd62ea1a	272	/* Check the parameters */
NYX	0:85b3fd62ea1a	273	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
NYX	0:85b3fd62ea1a	274	assert_param(IS_SPI_MODE(hspi->Init.Mode));
NYX	0:85b3fd62ea1a	275	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
NYX	0:85b3fd62ea1a	276	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
NYX	0:85b3fd62ea1a	277	assert_param(IS_SPI_NSS(hspi->Init.NSS));
NYX	0:85b3fd62ea1a	278	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
NYX	0:85b3fd62ea1a	279	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
NYX	0:85b3fd62ea1a	280	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
NYX	0:85b3fd62ea1a	281	if(hspi->Init.TIMode == SPI_TIMODE_DISABLE)
NYX	0:85b3fd62ea1a	282	{
NYX	0:85b3fd62ea1a	283	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
NYX	0:85b3fd62ea1a	284	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
NYX	0:85b3fd62ea1a	285	}
NYX	0:85b3fd62ea1a	286	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	287	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
NYX	0:85b3fd62ea1a	288	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	289	{
NYX	0:85b3fd62ea1a	290	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
NYX	0:85b3fd62ea1a	291	}
NYX	0:85b3fd62ea1a	292	#else
NYX	0:85b3fd62ea1a	293	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
NYX	0:85b3fd62ea1a	294	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	295
NYX	0:85b3fd62ea1a	296	if(hspi->State == HAL_SPI_STATE_RESET)
NYX	0:85b3fd62ea1a	297	{
NYX	0:85b3fd62ea1a	298	/* Allocate lock resource and initialize it */
NYX	0:85b3fd62ea1a	299	hspi->Lock = HAL_UNLOCKED;
NYX	0:85b3fd62ea1a	300
NYX	0:85b3fd62ea1a	301	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
NYX	0:85b3fd62ea1a	302	HAL_SPI_MspInit(hspi);
NYX	0:85b3fd62ea1a	303	}
NYX	0:85b3fd62ea1a	304
NYX	0:85b3fd62ea1a	305	hspi->State = HAL_SPI_STATE_BUSY;
NYX	0:85b3fd62ea1a	306
NYX	0:85b3fd62ea1a	307	/* Disable the selected SPI peripheral */
NYX	0:85b3fd62ea1a	308	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	309
NYX	0:85b3fd62ea1a	310	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
NYX	0:85b3fd62ea1a	311	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
NYX	0:85b3fd62ea1a	312	Communication speed, First bit and CRC calculation state */
NYX	0:85b3fd62ea1a	313	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
NYX	0:85b3fd62ea1a	314	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
NYX	0:85b3fd62ea1a	315	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
NYX	0:85b3fd62ea1a	316
NYX	0:85b3fd62ea1a	317	/* Configure : NSS management */
NYX	0:85b3fd62ea1a	318	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
NYX	0:85b3fd62ea1a	319
NYX	0:85b3fd62ea1a	320	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	321	/---------------------------- SPIx CRCPOLY Configuration ------------------/
NYX	0:85b3fd62ea1a	322	/* Configure : CRC Polynomial */
NYX	0:85b3fd62ea1a	323	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	324	{
NYX	0:85b3fd62ea1a	325	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
NYX	0:85b3fd62ea1a	326	}
NYX	0:85b3fd62ea1a	327	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	328
NYX	0:85b3fd62ea1a	329	#if defined(SPI_I2SCFGR_I2SMOD)
NYX	0:85b3fd62ea1a	330	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
NYX	0:85b3fd62ea1a	331	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
NYX	0:85b3fd62ea1a	332	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	333
NYX	0:85b3fd62ea1a	334	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	335	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	336
NYX	0:85b3fd62ea1a	337	return HAL_OK;
NYX	0:85b3fd62ea1a	338	}
NYX	0:85b3fd62ea1a	339
NYX	0:85b3fd62ea1a	340	/**
NYX	0:85b3fd62ea1a	341	* @brief De Initialize the SPI peripheral.
NYX	0:85b3fd62ea1a	342	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	343	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	344	* @retval HAL status
NYX	0:85b3fd62ea1a	345	*/
NYX	0:85b3fd62ea1a	346	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	347	{
NYX	0:85b3fd62ea1a	348	/* Check the SPI handle allocation */
NYX	0:85b3fd62ea1a	349	if(hspi == NULL)
NYX	0:85b3fd62ea1a	350	{
NYX	0:85b3fd62ea1a	351	return HAL_ERROR;
NYX	0:85b3fd62ea1a	352	}
NYX	0:85b3fd62ea1a	353
NYX	0:85b3fd62ea1a	354	/* Check SPI Instance parameter */
NYX	0:85b3fd62ea1a	355	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
NYX	0:85b3fd62ea1a	356
NYX	0:85b3fd62ea1a	357	hspi->State = HAL_SPI_STATE_BUSY;
NYX	0:85b3fd62ea1a	358
NYX	0:85b3fd62ea1a	359	/* Disable the SPI Peripheral Clock */
NYX	0:85b3fd62ea1a	360	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	361
NYX	0:85b3fd62ea1a	362	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
NYX	0:85b3fd62ea1a	363	HAL_SPI_MspDeInit(hspi);
NYX	0:85b3fd62ea1a	364
NYX	0:85b3fd62ea1a	365	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	366	hspi->State = HAL_SPI_STATE_RESET;
NYX	0:85b3fd62ea1a	367
NYX	0:85b3fd62ea1a	368	/* Release Lock */
NYX	0:85b3fd62ea1a	369	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	370
NYX	0:85b3fd62ea1a	371	return HAL_OK;
NYX	0:85b3fd62ea1a	372	}
NYX	0:85b3fd62ea1a	373
NYX	0:85b3fd62ea1a	374	/**
NYX	0:85b3fd62ea1a	375	* @brief Initialize the SPI MSP.
NYX	0:85b3fd62ea1a	376	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	377	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	378	* @retval None
NYX	0:85b3fd62ea1a	379	*/
NYX	0:85b3fd62ea1a	380	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	381	{
NYX	0:85b3fd62ea1a	382	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	383	UNUSED(hspi);
NYX	0:85b3fd62ea1a	384	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	385	the HAL_SPI_MspInit should be implemented in the user file
NYX	0:85b3fd62ea1a	386	*/
NYX	0:85b3fd62ea1a	387	}
NYX	0:85b3fd62ea1a	388
NYX	0:85b3fd62ea1a	389	/**
NYX	0:85b3fd62ea1a	390	* @brief De-Initialize the SPI MSP.
NYX	0:85b3fd62ea1a	391	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	392	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	393	* @retval None
NYX	0:85b3fd62ea1a	394	*/
NYX	0:85b3fd62ea1a	395	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	396	{
NYX	0:85b3fd62ea1a	397	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	398	UNUSED(hspi);
NYX	0:85b3fd62ea1a	399	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	400	the HAL_SPI_MspDeInit should be implemented in the user file
NYX	0:85b3fd62ea1a	401	*/
NYX	0:85b3fd62ea1a	402	}
NYX	0:85b3fd62ea1a	403
NYX	0:85b3fd62ea1a	404	/**
NYX	0:85b3fd62ea1a	405	* @}
NYX	0:85b3fd62ea1a	406	*/
NYX	0:85b3fd62ea1a	407
NYX	0:85b3fd62ea1a	408	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
NYX	0:85b3fd62ea1a	409	* @brief Data transfers functions
NYX	0:85b3fd62ea1a	410	*
NYX	0:85b3fd62ea1a	411	@verbatim
NYX	0:85b3fd62ea1a	412	==============================================================================
NYX	0:85b3fd62ea1a	413	##### IO operation functions #####
NYX	0:85b3fd62ea1a	414	===============================================================================
NYX	0:85b3fd62ea1a	415	[..]
NYX	0:85b3fd62ea1a	416	This subsection provides a set of functions allowing to manage the SPI
NYX	0:85b3fd62ea1a	417	data transfers.
NYX	0:85b3fd62ea1a	418
NYX	0:85b3fd62ea1a	419	[..] The SPI supports master and slave mode :
NYX	0:85b3fd62ea1a	420
NYX	0:85b3fd62ea1a	421	(#) There are two modes of transfer:
NYX	0:85b3fd62ea1a	422	(++) Blocking mode: The communication is performed in polling mode.
NYX	0:85b3fd62ea1a	423	The HAL status of all data processing is returned by the same function
NYX	0:85b3fd62ea1a	424	after finishing transfer.
NYX	0:85b3fd62ea1a	425	(++) No-Blocking mode: The communication is performed using Interrupts
NYX	0:85b3fd62ea1a	426	or DMA, These APIs return the HAL status.
NYX	0:85b3fd62ea1a	427	The end of the data processing will be indicated through the
NYX	0:85b3fd62ea1a	428	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
NYX	0:85b3fd62ea1a	429	using DMA mode.
NYX	0:85b3fd62ea1a	430	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
NYX	0:85b3fd62ea1a	431	will be executed respectively at the end of the transmit or Receive process
NYX	0:85b3fd62ea1a	432	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
NYX	0:85b3fd62ea1a	433
NYX	0:85b3fd62ea1a	434	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
NYX	0:85b3fd62ea1a	435	exist for 1Line (simplex) and 2Lines (full duplex) modes.
NYX	0:85b3fd62ea1a	436
NYX	0:85b3fd62ea1a	437	@endverbatim
NYX	0:85b3fd62ea1a	438	* @{
NYX	0:85b3fd62ea1a	439	*/
NYX	0:85b3fd62ea1a	440
NYX	0:85b3fd62ea1a	441	/**
NYX	0:85b3fd62ea1a	442	* @brief Transmit an amount of data in blocking mode.
NYX	0:85b3fd62ea1a	443	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	444	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	445	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	446	* @param Size: amount of data to be sent
NYX	0:85b3fd62ea1a	447	* @param Timeout: Timeout duration
NYX	0:85b3fd62ea1a	448	* @retval HAL status
NYX	0:85b3fd62ea1a	449	*/
NYX	0:85b3fd62ea1a	450	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
NYX	0:85b3fd62ea1a	451	{
NYX	0:85b3fd62ea1a	452	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	453	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	454
NYX	0:85b3fd62ea1a	455	/* Check Direction parameter */
NYX	0:85b3fd62ea1a	456	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
NYX	0:85b3fd62ea1a	457
NYX	0:85b3fd62ea1a	458	/* Process Locked */
NYX	0:85b3fd62ea1a	459	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	460
NYX	0:85b3fd62ea1a	461	/* Init tickstart for timeout management*/
NYX	0:85b3fd62ea1a	462	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	463
NYX	0:85b3fd62ea1a	464	if(hspi->State != HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	465	{
NYX	0:85b3fd62ea1a	466	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	467	goto error;
NYX	0:85b3fd62ea1a	468	}
NYX	0:85b3fd62ea1a	469
NYX	0:85b3fd62ea1a	470	if((pData == NULL ) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	471	{
NYX	0:85b3fd62ea1a	472	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	473	goto error;
NYX	0:85b3fd62ea1a	474	}
NYX	0:85b3fd62ea1a	475
NYX	0:85b3fd62ea1a	476	/* Set the transaction information */
NYX	0:85b3fd62ea1a	477	hspi->State = HAL_SPI_STATE_BUSY_TX;
NYX	0:85b3fd62ea1a	478	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	479	hspi->pTxBuffPtr = (uint8_t *)pData;
NYX	0:85b3fd62ea1a	480	hspi->TxXferSize = Size;
NYX	0:85b3fd62ea1a	481	hspi->TxXferCount = Size;
NYX	0:85b3fd62ea1a	482
NYX	0:85b3fd62ea1a	483	/Init field not used in handle to zero /
NYX	0:85b3fd62ea1a	484	hspi->pRxBuffPtr = (uint8_t *)NULL;
NYX	0:85b3fd62ea1a	485	hspi->RxXferSize = 0U;
NYX	0:85b3fd62ea1a	486	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	487	hspi->TxISR = NULL;
NYX	0:85b3fd62ea1a	488	hspi->RxISR = NULL;
NYX	0:85b3fd62ea1a	489
NYX	0:85b3fd62ea1a	490	/* Configure communication direction : 1Line */
NYX	0:85b3fd62ea1a	491	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
NYX	0:85b3fd62ea1a	492	{
NYX	0:85b3fd62ea1a	493	SPI_1LINE_TX(hspi);
NYX	0:85b3fd62ea1a	494	}
NYX	0:85b3fd62ea1a	495
NYX	0:85b3fd62ea1a	496	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	497	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	498	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	499	{
NYX	0:85b3fd62ea1a	500	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	501	}
NYX	0:85b3fd62ea1a	502	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	503
NYX	0:85b3fd62ea1a	504	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	505	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	506	{
NYX	0:85b3fd62ea1a	507	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	508	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	509	}
NYX	0:85b3fd62ea1a	510
NYX	0:85b3fd62ea1a	511	/* Transmit data in 16 Bit mode */
NYX	0:85b3fd62ea1a	512	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
NYX	0:85b3fd62ea1a	513	{
NYX	0:85b3fd62ea1a	514	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
NYX	0:85b3fd62ea1a	515	{
NYX	0:85b3fd62ea1a	516	hspi->Instance->DR = ((uint16_t )pData);
NYX	0:85b3fd62ea1a	517	pData += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	518	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	519	}
NYX	0:85b3fd62ea1a	520	/* Transmit data in 16 Bit mode */
NYX	0:85b3fd62ea1a	521	while (hspi->TxXferCount > 0U)
NYX	0:85b3fd62ea1a	522	{
NYX	0:85b3fd62ea1a	523	/* Wait until TXE flag is set to send data */
NYX	0:85b3fd62ea1a	524	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
NYX	0:85b3fd62ea1a	525	{
NYX	0:85b3fd62ea1a	526	hspi->Instance->DR = ((uint16_t )pData);
NYX	0:85b3fd62ea1a	527	pData += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	528	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	529	}
NYX	0:85b3fd62ea1a	530	else
NYX	0:85b3fd62ea1a	531	{
NYX	0:85b3fd62ea1a	532	/* Timeout management */
NYX	0:85b3fd62ea1a	533	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
NYX	0:85b3fd62ea1a	534	{
NYX	0:85b3fd62ea1a	535	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	536	goto error;
NYX	0:85b3fd62ea1a	537	}
NYX	0:85b3fd62ea1a	538	}
NYX	0:85b3fd62ea1a	539	}
NYX	0:85b3fd62ea1a	540	}
NYX	0:85b3fd62ea1a	541	/* Transmit data in 8 Bit mode */
NYX	0:85b3fd62ea1a	542	else
NYX	0:85b3fd62ea1a	543	{
NYX	0:85b3fd62ea1a	544	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
NYX	0:85b3fd62ea1a	545	{
NYX	0:85b3fd62ea1a	546	((__IO uint8_t)&hspi->Instance->DR) = (*pData);
NYX	0:85b3fd62ea1a	547	pData += sizeof(uint8_t);
NYX	0:85b3fd62ea1a	548	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	549	}
NYX	0:85b3fd62ea1a	550	while (hspi->TxXferCount > 0U)
NYX	0:85b3fd62ea1a	551	{
NYX	0:85b3fd62ea1a	552	/* Wait until TXE flag is set to send data */
NYX	0:85b3fd62ea1a	553	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
NYX	0:85b3fd62ea1a	554	{
NYX	0:85b3fd62ea1a	555	((__IO uint8_t)&hspi->Instance->DR) = (*pData);
NYX	0:85b3fd62ea1a	556	pData += sizeof(uint8_t);
NYX	0:85b3fd62ea1a	557	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	558	}
NYX	0:85b3fd62ea1a	559	else
NYX	0:85b3fd62ea1a	560	{
NYX	0:85b3fd62ea1a	561	/* Timeout management */
NYX	0:85b3fd62ea1a	562	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
NYX	0:85b3fd62ea1a	563	{
NYX	0:85b3fd62ea1a	564	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	565	goto error;
NYX	0:85b3fd62ea1a	566	}
NYX	0:85b3fd62ea1a	567	}
NYX	0:85b3fd62ea1a	568	}
NYX	0:85b3fd62ea1a	569	}
NYX	0:85b3fd62ea1a	570
NYX	0:85b3fd62ea1a	571	/* Wait until TXE flag */
NYX	0:85b3fd62ea1a	572	if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	573	{
NYX	0:85b3fd62ea1a	574	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	575	goto error;
NYX	0:85b3fd62ea1a	576	}
NYX	0:85b3fd62ea1a	577
NYX	0:85b3fd62ea1a	578	/* Check Busy flag */
NYX	0:85b3fd62ea1a	579	if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	580	{
NYX	0:85b3fd62ea1a	581	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	582	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
NYX	0:85b3fd62ea1a	583	goto error;
NYX	0:85b3fd62ea1a	584	}
NYX	0:85b3fd62ea1a	585
NYX	0:85b3fd62ea1a	586	/* Clear overrun flag in 2 Lines communication mode because received is not read */
NYX	0:85b3fd62ea1a	587	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
NYX	0:85b3fd62ea1a	588	{
NYX	0:85b3fd62ea1a	589	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	590	}
NYX	0:85b3fd62ea1a	591	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	592	/* Enable CRC Transmission */
NYX	0:85b3fd62ea1a	593	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	594	{
NYX	0:85b3fd62ea1a	595	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	596	}
NYX	0:85b3fd62ea1a	597	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	598
NYX	0:85b3fd62ea1a	599	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	600	{
NYX	0:85b3fd62ea1a	601	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	602	}
NYX	0:85b3fd62ea1a	603
NYX	0:85b3fd62ea1a	604	error:
NYX	0:85b3fd62ea1a	605	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	606	/* Process Unlocked */
NYX	0:85b3fd62ea1a	607	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	608	return errorcode;
NYX	0:85b3fd62ea1a	609	}
NYX	0:85b3fd62ea1a	610
NYX	0:85b3fd62ea1a	611	/**
NYX	0:85b3fd62ea1a	612	* @brief Receive an amount of data in blocking mode.
NYX	0:85b3fd62ea1a	613	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	614	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	615	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	616	* @param Size: amount of data to be received
NYX	0:85b3fd62ea1a	617	* @param Timeout: Timeout duration
NYX	0:85b3fd62ea1a	618	* @retval HAL status
NYX	0:85b3fd62ea1a	619	*/
NYX	0:85b3fd62ea1a	620	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
NYX	0:85b3fd62ea1a	621	{
NYX	0:85b3fd62ea1a	622	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	623	__IO uint16_t tmpreg = 0U;
NYX	0:85b3fd62ea1a	624	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	625	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	626	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	627
NYX	0:85b3fd62ea1a	628	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
NYX	0:85b3fd62ea1a	629	{
NYX	0:85b3fd62ea1a	630	hspi->State = HAL_SPI_STATE_BUSY_RX;
NYX	0:85b3fd62ea1a	631	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
NYX	0:85b3fd62ea1a	632	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
NYX	0:85b3fd62ea1a	633	}
NYX	0:85b3fd62ea1a	634
NYX	0:85b3fd62ea1a	635	/* Process Locked */
NYX	0:85b3fd62ea1a	636	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	637
NYX	0:85b3fd62ea1a	638	/* Init tickstart for timeout management*/
NYX	0:85b3fd62ea1a	639	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	640
NYX	0:85b3fd62ea1a	641	if(hspi->State != HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	642	{
NYX	0:85b3fd62ea1a	643	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	644	goto error;
NYX	0:85b3fd62ea1a	645	}
NYX	0:85b3fd62ea1a	646
NYX	0:85b3fd62ea1a	647	if((pData == NULL ) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	648	{
NYX	0:85b3fd62ea1a	649	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	650	goto error;
NYX	0:85b3fd62ea1a	651	}
NYX	0:85b3fd62ea1a	652
NYX	0:85b3fd62ea1a	653	/* Set the transaction information */
NYX	0:85b3fd62ea1a	654	hspi->State = HAL_SPI_STATE_BUSY_RX;
NYX	0:85b3fd62ea1a	655	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	656	hspi->pRxBuffPtr = (uint8_t *)pData;
NYX	0:85b3fd62ea1a	657	hspi->RxXferSize = Size;
NYX	0:85b3fd62ea1a	658	hspi->RxXferCount = Size;
NYX	0:85b3fd62ea1a	659
NYX	0:85b3fd62ea1a	660	/Init field not used in handle to zero /
NYX	0:85b3fd62ea1a	661	hspi->pTxBuffPtr = (uint8_t *)NULL;
NYX	0:85b3fd62ea1a	662	hspi->TxXferSize = 0U;
NYX	0:85b3fd62ea1a	663	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	664	hspi->RxISR = NULL;
NYX	0:85b3fd62ea1a	665	hspi->TxISR = NULL;
NYX	0:85b3fd62ea1a	666
NYX	0:85b3fd62ea1a	667	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	668	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	669	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	670	{
NYX	0:85b3fd62ea1a	671	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	672	/* this is done to handle the CRCNEXT before the latest data */
NYX	0:85b3fd62ea1a	673	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	674	}
NYX	0:85b3fd62ea1a	675	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	676
NYX	0:85b3fd62ea1a	677	/* Configure communication direction: 1Line */
NYX	0:85b3fd62ea1a	678	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
NYX	0:85b3fd62ea1a	679	{
NYX	0:85b3fd62ea1a	680	SPI_1LINE_RX(hspi);
NYX	0:85b3fd62ea1a	681	}
NYX	0:85b3fd62ea1a	682
NYX	0:85b3fd62ea1a	683	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	684	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	685	{
NYX	0:85b3fd62ea1a	686	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	687	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	688	}
NYX	0:85b3fd62ea1a	689
NYX	0:85b3fd62ea1a	690	/* Receive data in 8 Bit mode */
NYX	0:85b3fd62ea1a	691	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
NYX	0:85b3fd62ea1a	692	{
NYX	0:85b3fd62ea1a	693	/* Transfer loop */
NYX	0:85b3fd62ea1a	694	while(hspi->RxXferCount > 0U)
NYX	0:85b3fd62ea1a	695	{
NYX	0:85b3fd62ea1a	696	/* Check the RXNE flag */
NYX	0:85b3fd62ea1a	697	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
NYX	0:85b3fd62ea1a	698	{
NYX	0:85b3fd62ea1a	699	/* read the received data */
NYX	0:85b3fd62ea1a	700	(* (uint8_t )pData)= (__IO uint8_t *)&hspi->Instance->DR;
NYX	0:85b3fd62ea1a	701	pData += sizeof(uint8_t);
NYX	0:85b3fd62ea1a	702	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	703	}
NYX	0:85b3fd62ea1a	704	else
NYX	0:85b3fd62ea1a	705	{
NYX	0:85b3fd62ea1a	706	/* Timeout management */
NYX	0:85b3fd62ea1a	707	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
NYX	0:85b3fd62ea1a	708	{
NYX	0:85b3fd62ea1a	709	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	710	goto error;
NYX	0:85b3fd62ea1a	711	}
NYX	0:85b3fd62ea1a	712	}
NYX	0:85b3fd62ea1a	713	}
NYX	0:85b3fd62ea1a	714	}
NYX	0:85b3fd62ea1a	715	else
NYX	0:85b3fd62ea1a	716	{
NYX	0:85b3fd62ea1a	717	/* Transfer loop */
NYX	0:85b3fd62ea1a	718	while(hspi->RxXferCount > 0U)
NYX	0:85b3fd62ea1a	719	{
NYX	0:85b3fd62ea1a	720	/* Check the RXNE flag */
NYX	0:85b3fd62ea1a	721	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
NYX	0:85b3fd62ea1a	722	{
NYX	0:85b3fd62ea1a	723	((uint16_t)pData) = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	724	pData += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	725	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	726	}
NYX	0:85b3fd62ea1a	727	else
NYX	0:85b3fd62ea1a	728	{
NYX	0:85b3fd62ea1a	729	/* Timeout management */
NYX	0:85b3fd62ea1a	730	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
NYX	0:85b3fd62ea1a	731	{
NYX	0:85b3fd62ea1a	732	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	733	goto error;
NYX	0:85b3fd62ea1a	734	}
NYX	0:85b3fd62ea1a	735	}
NYX	0:85b3fd62ea1a	736	}
NYX	0:85b3fd62ea1a	737	}
NYX	0:85b3fd62ea1a	738
NYX	0:85b3fd62ea1a	739	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	740	/* Handle the CRC Transmission */
NYX	0:85b3fd62ea1a	741	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	742	{
NYX	0:85b3fd62ea1a	743	/* freeze the CRC before the latest data */
NYX	0:85b3fd62ea1a	744	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	745
NYX	0:85b3fd62ea1a	746	/* Read the latest data */
NYX	0:85b3fd62ea1a	747	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	748	{
NYX	0:85b3fd62ea1a	749	/* the latest data has not been received */
NYX	0:85b3fd62ea1a	750	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	751	goto error;
NYX	0:85b3fd62ea1a	752	}
NYX	0:85b3fd62ea1a	753
NYX	0:85b3fd62ea1a	754	/* Receive last data in 16 Bit mode */
NYX	0:85b3fd62ea1a	755	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
NYX	0:85b3fd62ea1a	756	{
NYX	0:85b3fd62ea1a	757	((uint16_t)pData) = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	758	}
NYX	0:85b3fd62ea1a	759	/* Receive last data in 8 Bit mode */
NYX	0:85b3fd62ea1a	760	else
NYX	0:85b3fd62ea1a	761	{
NYX	0:85b3fd62ea1a	762	((uint8_t )pData) = (__IO uint8_t )&hspi->Instance->DR;
NYX	0:85b3fd62ea1a	763	}
NYX	0:85b3fd62ea1a	764
NYX	0:85b3fd62ea1a	765	/* Wait the CRC data */
NYX	0:85b3fd62ea1a	766	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	767	{
NYX	0:85b3fd62ea1a	768	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	769	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	770	goto error;
NYX	0:85b3fd62ea1a	771	}
NYX	0:85b3fd62ea1a	772
NYX	0:85b3fd62ea1a	773	/* Read CRC to Flush DR and RXNE flag */
NYX	0:85b3fd62ea1a	774	tmpreg = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	775	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	776	UNUSED(tmpreg);
NYX	0:85b3fd62ea1a	777	}
NYX	0:85b3fd62ea1a	778	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	779
NYX	0:85b3fd62ea1a	780	/* Check the end of the transaction */
NYX	0:85b3fd62ea1a	781	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
NYX	0:85b3fd62ea1a	782	{
NYX	0:85b3fd62ea1a	783	/* Disable SPI peripheral */
NYX	0:85b3fd62ea1a	784	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	785	}
NYX	0:85b3fd62ea1a	786
NYX	0:85b3fd62ea1a	787	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	788	/* Check if CRC error occurred */
NYX	0:85b3fd62ea1a	789	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
NYX	0:85b3fd62ea1a	790	{
NYX	0:85b3fd62ea1a	791	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	792	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
NYX	0:85b3fd62ea1a	793	}
NYX	0:85b3fd62ea1a	794	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	795
NYX	0:85b3fd62ea1a	796	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	797	{
NYX	0:85b3fd62ea1a	798	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	799	}
NYX	0:85b3fd62ea1a	800
NYX	0:85b3fd62ea1a	801	error :
NYX	0:85b3fd62ea1a	802	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	803	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	804	return errorcode;
NYX	0:85b3fd62ea1a	805	}
NYX	0:85b3fd62ea1a	806
NYX	0:85b3fd62ea1a	807	/**
NYX	0:85b3fd62ea1a	808	* @brief Transmit and Receive an amount of data in blocking mode.
NYX	0:85b3fd62ea1a	809	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	810	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	811	* @param pTxData: pointer to transmission data buffer
NYX	0:85b3fd62ea1a	812	* @param pRxData: pointer to reception data buffer
NYX	0:85b3fd62ea1a	813	* @param Size: amount of data to be sent and received
NYX	0:85b3fd62ea1a	814	* @param Timeout: Timeout duration
NYX	0:85b3fd62ea1a	815	* @retval HAL status
NYX	0:85b3fd62ea1a	816	*/
NYX	0:85b3fd62ea1a	817	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
NYX	0:85b3fd62ea1a	818	{
NYX	0:85b3fd62ea1a	819	uint32_t tmp = 0U, tmp1 = 0U;
NYX	0:85b3fd62ea1a	820	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	821	__IO uint16_t tmpreg1 = 0U;
NYX	0:85b3fd62ea1a	822	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	823	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	824	/* Variable used to alternate Rx and Tx during transfer */
NYX	0:85b3fd62ea1a	825	uint32_t txallowed = 1U;
NYX	0:85b3fd62ea1a	826	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	827
NYX	0:85b3fd62ea1a	828	/* Check Direction parameter */
NYX	0:85b3fd62ea1a	829	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
NYX	0:85b3fd62ea1a	830
NYX	0:85b3fd62ea1a	831	/* Process Locked */
NYX	0:85b3fd62ea1a	832	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	833
NYX	0:85b3fd62ea1a	834	/* Init tickstart for timeout management*/
NYX	0:85b3fd62ea1a	835	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	836
NYX	0:85b3fd62ea1a	837	tmp = hspi->State;
NYX	0:85b3fd62ea1a	838	tmp1 = hspi->Init.Mode;
NYX	0:85b3fd62ea1a	839
NYX	0:85b3fd62ea1a	840	if(!((tmp == HAL_SPI_STATE_READY) \|\| \
NYX	0:85b3fd62ea1a	841	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
NYX	0:85b3fd62ea1a	842	{
NYX	0:85b3fd62ea1a	843	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	844	goto error;
NYX	0:85b3fd62ea1a	845	}
NYX	0:85b3fd62ea1a	846
NYX	0:85b3fd62ea1a	847	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	848	{
NYX	0:85b3fd62ea1a	849	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	850	goto error;
NYX	0:85b3fd62ea1a	851	}
NYX	0:85b3fd62ea1a	852
NYX	0:85b3fd62ea1a	853	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
NYX	0:85b3fd62ea1a	854	if(hspi->State == HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	855	{
NYX	0:85b3fd62ea1a	856	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
NYX	0:85b3fd62ea1a	857	}
NYX	0:85b3fd62ea1a	858
NYX	0:85b3fd62ea1a	859	/* Set the transaction information */
NYX	0:85b3fd62ea1a	860	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	861	hspi->pRxBuffPtr = (uint8_t *)pRxData;
NYX	0:85b3fd62ea1a	862	hspi->RxXferCount = Size;
NYX	0:85b3fd62ea1a	863	hspi->RxXferSize = Size;
NYX	0:85b3fd62ea1a	864	hspi->pTxBuffPtr = (uint8_t *)pTxData;
NYX	0:85b3fd62ea1a	865	hspi->TxXferCount = Size;
NYX	0:85b3fd62ea1a	866	hspi->TxXferSize = Size;
NYX	0:85b3fd62ea1a	867
NYX	0:85b3fd62ea1a	868	/Init field not used in handle to zero /
NYX	0:85b3fd62ea1a	869	hspi->RxISR = NULL;
NYX	0:85b3fd62ea1a	870	hspi->TxISR = NULL;
NYX	0:85b3fd62ea1a	871
NYX	0:85b3fd62ea1a	872	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	873	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	874	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	875	{
NYX	0:85b3fd62ea1a	876	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	877	}
NYX	0:85b3fd62ea1a	878	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	879
NYX	0:85b3fd62ea1a	880	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	881	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	882	{
NYX	0:85b3fd62ea1a	883	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	884	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	885	}
NYX	0:85b3fd62ea1a	886
NYX	0:85b3fd62ea1a	887	/* Transmit and Receive data in 16 Bit mode */
NYX	0:85b3fd62ea1a	888	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
NYX	0:85b3fd62ea1a	889	{
NYX	0:85b3fd62ea1a	890	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
NYX	0:85b3fd62ea1a	891	{
NYX	0:85b3fd62ea1a	892	hspi->Instance->DR = ((uint16_t )pTxData);
NYX	0:85b3fd62ea1a	893	pTxData += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	894	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	895	}
NYX	0:85b3fd62ea1a	896	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
NYX	0:85b3fd62ea1a	897	{
NYX	0:85b3fd62ea1a	898	/* Check TXE flag */
NYX	0:85b3fd62ea1a	899	if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
NYX	0:85b3fd62ea1a	900	{
NYX	0:85b3fd62ea1a	901	hspi->Instance->DR = ((uint16_t )pTxData);
NYX	0:85b3fd62ea1a	902	pTxData += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	903	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	904	/* Next Data is a reception (Rx). Tx not allowed */
NYX	0:85b3fd62ea1a	905	txallowed = 0U;
NYX	0:85b3fd62ea1a	906
NYX	0:85b3fd62ea1a	907	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	908	/* Enable CRC Transmission */
NYX	0:85b3fd62ea1a	909	if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
NYX	0:85b3fd62ea1a	910	{
NYX	0:85b3fd62ea1a	911	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	912	}
NYX	0:85b3fd62ea1a	913	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	914	}
NYX	0:85b3fd62ea1a	915
NYX	0:85b3fd62ea1a	916	/* Check RXNE flag */
NYX	0:85b3fd62ea1a	917	if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
NYX	0:85b3fd62ea1a	918	{
NYX	0:85b3fd62ea1a	919	((uint16_t )pRxData) = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	920	pRxData += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	921	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	922	/* Next Data is a Transmission (Tx). Tx is allowed */
NYX	0:85b3fd62ea1a	923	txallowed = 1U;
NYX	0:85b3fd62ea1a	924	}
NYX	0:85b3fd62ea1a	925	if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
NYX	0:85b3fd62ea1a	926	{
NYX	0:85b3fd62ea1a	927	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	928	goto error;
NYX	0:85b3fd62ea1a	929	}
NYX	0:85b3fd62ea1a	930	}
NYX	0:85b3fd62ea1a	931	}
NYX	0:85b3fd62ea1a	932	/* Transmit and Receive data in 8 Bit mode */
NYX	0:85b3fd62ea1a	933	else
NYX	0:85b3fd62ea1a	934	{
NYX	0:85b3fd62ea1a	935	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01U))
NYX	0:85b3fd62ea1a	936	{
NYX	0:85b3fd62ea1a	937	((__IO uint8_t)&hspi->Instance->DR) = (*pTxData);
NYX	0:85b3fd62ea1a	938	pTxData += sizeof(uint8_t);
NYX	0:85b3fd62ea1a	939	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	940	}
NYX	0:85b3fd62ea1a	941	while((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
NYX	0:85b3fd62ea1a	942	{
NYX	0:85b3fd62ea1a	943	/* check TXE flag */
NYX	0:85b3fd62ea1a	944	if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
NYX	0:85b3fd62ea1a	945	{
NYX	0:85b3fd62ea1a	946	(__IO uint8_t )&hspi->Instance->DR = (*pTxData++);
NYX	0:85b3fd62ea1a	947	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	948	/* Next Data is a reception (Rx). Tx not allowed */
NYX	0:85b3fd62ea1a	949	txallowed = 0U;
NYX	0:85b3fd62ea1a	950
NYX	0:85b3fd62ea1a	951	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	952	/* Enable CRC Transmission */
NYX	0:85b3fd62ea1a	953	if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
NYX	0:85b3fd62ea1a	954	{
NYX	0:85b3fd62ea1a	955	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	956	}
NYX	0:85b3fd62ea1a	957	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	958	}
NYX	0:85b3fd62ea1a	959
NYX	0:85b3fd62ea1a	960	/* Wait until RXNE flag is reset */
NYX	0:85b3fd62ea1a	961	if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
NYX	0:85b3fd62ea1a	962	{
NYX	0:85b3fd62ea1a	963	((uint8_t )pRxData++) = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	964	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	965	/* Next Data is a Transmission (Tx). Tx is allowed */
NYX	0:85b3fd62ea1a	966	txallowed = 1U;
NYX	0:85b3fd62ea1a	967	}
NYX	0:85b3fd62ea1a	968	if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
NYX	0:85b3fd62ea1a	969	{
NYX	0:85b3fd62ea1a	970	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	971	goto error;
NYX	0:85b3fd62ea1a	972	}
NYX	0:85b3fd62ea1a	973	}
NYX	0:85b3fd62ea1a	974	}
NYX	0:85b3fd62ea1a	975
NYX	0:85b3fd62ea1a	976	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	977	/* Read CRC from DR to close CRC calculation process */
NYX	0:85b3fd62ea1a	978	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	979	{
NYX	0:85b3fd62ea1a	980	/* Wait until TXE flag */
NYX	0:85b3fd62ea1a	981	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	982	{
NYX	0:85b3fd62ea1a	983	/* Error on the CRC reception */
NYX	0:85b3fd62ea1a	984	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	985	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	986	goto error;
NYX	0:85b3fd62ea1a	987	}
NYX	0:85b3fd62ea1a	988	/* Read CRC */
NYX	0:85b3fd62ea1a	989	tmpreg1 = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	990	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	991	UNUSED(tmpreg1);
NYX	0:85b3fd62ea1a	992	}
NYX	0:85b3fd62ea1a	993
NYX	0:85b3fd62ea1a	994	/* Check if CRC error occurred */
NYX	0:85b3fd62ea1a	995	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
NYX	0:85b3fd62ea1a	996	{
NYX	0:85b3fd62ea1a	997	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	998	/* Clear CRC Flag */
NYX	0:85b3fd62ea1a	999	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
NYX	0:85b3fd62ea1a	1000
NYX	0:85b3fd62ea1a	1001	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	1002	}
NYX	0:85b3fd62ea1a	1003	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	1004
NYX	0:85b3fd62ea1a	1005	/* Wait until TXE flag */
NYX	0:85b3fd62ea1a	1006	if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	1007	{
NYX	0:85b3fd62ea1a	1008	errorcode = HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	1009	goto error;
NYX	0:85b3fd62ea1a	1010	}
NYX	0:85b3fd62ea1a	1011
NYX	0:85b3fd62ea1a	1012	/* Check Busy flag */
NYX	0:85b3fd62ea1a	1013	if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	1014	{
NYX	0:85b3fd62ea1a	1015	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	1016	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
NYX	0:85b3fd62ea1a	1017	goto error;
NYX	0:85b3fd62ea1a	1018	}
NYX	0:85b3fd62ea1a	1019
NYX	0:85b3fd62ea1a	1020	/* Clear overrun flag in 2 Lines communication mode because received is not read */
NYX	0:85b3fd62ea1a	1021	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
NYX	0:85b3fd62ea1a	1022	{
NYX	0:85b3fd62ea1a	1023	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	1024	}
NYX	0:85b3fd62ea1a	1025
NYX	0:85b3fd62ea1a	1026	error :
NYX	0:85b3fd62ea1a	1027	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	1028	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1029	return errorcode;
NYX	0:85b3fd62ea1a	1030	}
NYX	0:85b3fd62ea1a	1031
NYX	0:85b3fd62ea1a	1032	/**
NYX	0:85b3fd62ea1a	1033	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
NYX	0:85b3fd62ea1a	1034	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1035	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	1036	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	1037	* @param Size: amount of data to be sent
NYX	0:85b3fd62ea1a	1038	* @retval HAL status
NYX	0:85b3fd62ea1a	1039	*/
NYX	0:85b3fd62ea1a	1040	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
NYX	0:85b3fd62ea1a	1041	{
NYX	0:85b3fd62ea1a	1042	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	1043
NYX	0:85b3fd62ea1a	1044	/* Check Direction parameter */
NYX	0:85b3fd62ea1a	1045	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
NYX	0:85b3fd62ea1a	1046
NYX	0:85b3fd62ea1a	1047	/* Process Locked */
NYX	0:85b3fd62ea1a	1048	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	1049
NYX	0:85b3fd62ea1a	1050	if((pData == NULL) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	1051	{
NYX	0:85b3fd62ea1a	1052	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	1053	goto error;
NYX	0:85b3fd62ea1a	1054	}
NYX	0:85b3fd62ea1a	1055
NYX	0:85b3fd62ea1a	1056	if(hspi->State != HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	1057	{
NYX	0:85b3fd62ea1a	1058	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	1059	goto error;
NYX	0:85b3fd62ea1a	1060	}
NYX	0:85b3fd62ea1a	1061
NYX	0:85b3fd62ea1a	1062	/* Set the transaction information */
NYX	0:85b3fd62ea1a	1063	hspi->State = HAL_SPI_STATE_BUSY_TX;
NYX	0:85b3fd62ea1a	1064	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1065	hspi->pTxBuffPtr = (uint8_t *)pData;
NYX	0:85b3fd62ea1a	1066	hspi->TxXferSize = Size;
NYX	0:85b3fd62ea1a	1067	hspi->TxXferCount = Size;
NYX	0:85b3fd62ea1a	1068
NYX	0:85b3fd62ea1a	1069	/* Init field not used in handle to zero */
NYX	0:85b3fd62ea1a	1070	hspi->pRxBuffPtr = (uint8_t *)NULL;
NYX	0:85b3fd62ea1a	1071	hspi->RxXferSize = 0U;
NYX	0:85b3fd62ea1a	1072	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	1073	hspi->RxISR = NULL;
NYX	0:85b3fd62ea1a	1074
NYX	0:85b3fd62ea1a	1075	/* Set the function for IT treatment */
NYX	0:85b3fd62ea1a	1076	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
NYX	0:85b3fd62ea1a	1077	{
NYX	0:85b3fd62ea1a	1078	hspi->TxISR = SPI_TxISR_16BIT;
NYX	0:85b3fd62ea1a	1079	}
NYX	0:85b3fd62ea1a	1080	else
NYX	0:85b3fd62ea1a	1081	{
NYX	0:85b3fd62ea1a	1082	hspi->TxISR = SPI_TxISR_8BIT;
NYX	0:85b3fd62ea1a	1083	}
NYX	0:85b3fd62ea1a	1084
NYX	0:85b3fd62ea1a	1085	/* Configure communication direction : 1Line */
NYX	0:85b3fd62ea1a	1086	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
NYX	0:85b3fd62ea1a	1087	{
NYX	0:85b3fd62ea1a	1088	SPI_1LINE_TX(hspi);
NYX	0:85b3fd62ea1a	1089	}
NYX	0:85b3fd62ea1a	1090
NYX	0:85b3fd62ea1a	1091	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	1092	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	1093	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	1094	{
NYX	0:85b3fd62ea1a	1095	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	1096	}
NYX	0:85b3fd62ea1a	1097	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	1098
NYX	0:85b3fd62ea1a	1099	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
NYX	0:85b3fd62ea1a	1100	{
NYX	0:85b3fd62ea1a	1101	/* Enable TXE interrupt */
NYX	0:85b3fd62ea1a	1102	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
NYX	0:85b3fd62ea1a	1103	}
NYX	0:85b3fd62ea1a	1104	else
NYX	0:85b3fd62ea1a	1105	{
NYX	0:85b3fd62ea1a	1106	/* Enable TXE and ERR interrupt */
NYX	0:85b3fd62ea1a	1107	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	1108	}
NYX	0:85b3fd62ea1a	1109
NYX	0:85b3fd62ea1a	1110	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	1111	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	1112	{
NYX	0:85b3fd62ea1a	1113	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	1114	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	1115	}
NYX	0:85b3fd62ea1a	1116
NYX	0:85b3fd62ea1a	1117	error :
NYX	0:85b3fd62ea1a	1118	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1119	return errorcode;
NYX	0:85b3fd62ea1a	1120	}
NYX	0:85b3fd62ea1a	1121
NYX	0:85b3fd62ea1a	1122	/**
NYX	0:85b3fd62ea1a	1123	* @brief Receive an amount of data in non-blocking mode with Interrupt.
NYX	0:85b3fd62ea1a	1124	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1125	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	1126	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	1127	* @param Size: amount of data to be sent
NYX	0:85b3fd62ea1a	1128	* @retval HAL status
NYX	0:85b3fd62ea1a	1129	*/
NYX	0:85b3fd62ea1a	1130	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
NYX	0:85b3fd62ea1a	1131	{
NYX	0:85b3fd62ea1a	1132	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	1133
NYX	0:85b3fd62ea1a	1134	if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
NYX	0:85b3fd62ea1a	1135	{
NYX	0:85b3fd62ea1a	1136	hspi->State = HAL_SPI_STATE_BUSY_RX;
NYX	0:85b3fd62ea1a	1137	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
NYX	0:85b3fd62ea1a	1138	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
NYX	0:85b3fd62ea1a	1139	}
NYX	0:85b3fd62ea1a	1140
NYX	0:85b3fd62ea1a	1141	/* Process Locked */
NYX	0:85b3fd62ea1a	1142	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	1143
NYX	0:85b3fd62ea1a	1144	if(hspi->State != HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	1145	{
NYX	0:85b3fd62ea1a	1146	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	1147	goto error;
NYX	0:85b3fd62ea1a	1148	}
NYX	0:85b3fd62ea1a	1149
NYX	0:85b3fd62ea1a	1150	if((pData == NULL) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	1151	{
NYX	0:85b3fd62ea1a	1152	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	1153	goto error;
NYX	0:85b3fd62ea1a	1154	}
NYX	0:85b3fd62ea1a	1155
NYX	0:85b3fd62ea1a	1156	/* Set the transaction information */
NYX	0:85b3fd62ea1a	1157	hspi->State = HAL_SPI_STATE_BUSY_RX;
NYX	0:85b3fd62ea1a	1158	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1159	hspi->pRxBuffPtr = (uint8_t *)pData;
NYX	0:85b3fd62ea1a	1160	hspi->RxXferSize = Size;
NYX	0:85b3fd62ea1a	1161	hspi->RxXferCount = Size;
NYX	0:85b3fd62ea1a	1162
NYX	0:85b3fd62ea1a	1163	/* Init field not used in handle to zero */
NYX	0:85b3fd62ea1a	1164	hspi->pTxBuffPtr = (uint8_t *)NULL;
NYX	0:85b3fd62ea1a	1165	hspi->TxXferSize = 0U;
NYX	0:85b3fd62ea1a	1166	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	1167	hspi->TxISR = NULL;
NYX	0:85b3fd62ea1a	1168
NYX	0:85b3fd62ea1a	1169	/* Set the function for IT treatment */
NYX	0:85b3fd62ea1a	1170	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
NYX	0:85b3fd62ea1a	1171	{
NYX	0:85b3fd62ea1a	1172	hspi->RxISR = SPI_RxISR_16BIT;
NYX	0:85b3fd62ea1a	1173	}
NYX	0:85b3fd62ea1a	1174	else
NYX	0:85b3fd62ea1a	1175	{
NYX	0:85b3fd62ea1a	1176	hspi->RxISR = SPI_RxISR_8BIT;
NYX	0:85b3fd62ea1a	1177	}
NYX	0:85b3fd62ea1a	1178
NYX	0:85b3fd62ea1a	1179	/* Configure communication direction : 1Line */
NYX	0:85b3fd62ea1a	1180	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
NYX	0:85b3fd62ea1a	1181	{
NYX	0:85b3fd62ea1a	1182	SPI_1LINE_RX(hspi);
NYX	0:85b3fd62ea1a	1183	}
NYX	0:85b3fd62ea1a	1184
NYX	0:85b3fd62ea1a	1185	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	1186	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	1187	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	1188	{
NYX	0:85b3fd62ea1a	1189	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	1190	}
NYX	0:85b3fd62ea1a	1191	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	1192
NYX	0:85b3fd62ea1a	1193	/* Enable TXE and ERR interrupt */
NYX	0:85b3fd62ea1a	1194	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	1195
NYX	0:85b3fd62ea1a	1196	/* Note : The SPI must be enabled after unlocking current process
NYX	0:85b3fd62ea1a	1197	to avoid the risk of SPI interrupt handle execution before current
NYX	0:85b3fd62ea1a	1198	process unlock */
NYX	0:85b3fd62ea1a	1199
NYX	0:85b3fd62ea1a	1200	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	1201	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	1202	{
NYX	0:85b3fd62ea1a	1203	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	1204	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	1205	}
NYX	0:85b3fd62ea1a	1206
NYX	0:85b3fd62ea1a	1207	error :
NYX	0:85b3fd62ea1a	1208	/* Process Unlocked */
NYX	0:85b3fd62ea1a	1209	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1210	return errorcode;
NYX	0:85b3fd62ea1a	1211	}
NYX	0:85b3fd62ea1a	1212
NYX	0:85b3fd62ea1a	1213	/**
NYX	0:85b3fd62ea1a	1214	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
NYX	0:85b3fd62ea1a	1215	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1216	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	1217	* @param pTxData: pointer to transmission data buffer
NYX	0:85b3fd62ea1a	1218	* @param pRxData: pointer to reception data buffer
NYX	0:85b3fd62ea1a	1219	* @param Size: amount of data to be sent and received
NYX	0:85b3fd62ea1a	1220	* @retval HAL status
NYX	0:85b3fd62ea1a	1221	*/
NYX	0:85b3fd62ea1a	1222	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
NYX	0:85b3fd62ea1a	1223	{
NYX	0:85b3fd62ea1a	1224	uint32_t tmp = 0U, tmp1 = 0U;
NYX	0:85b3fd62ea1a	1225	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	1226
NYX	0:85b3fd62ea1a	1227	/* Check Direction parameter */
NYX	0:85b3fd62ea1a	1228	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
NYX	0:85b3fd62ea1a	1229
NYX	0:85b3fd62ea1a	1230	/* Process locked */
NYX	0:85b3fd62ea1a	1231	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	1232
NYX	0:85b3fd62ea1a	1233	tmp = hspi->State;
NYX	0:85b3fd62ea1a	1234	tmp1 = hspi->Init.Mode;
NYX	0:85b3fd62ea1a	1235
NYX	0:85b3fd62ea1a	1236	if(!((tmp == HAL_SPI_STATE_READY) \|\| \
NYX	0:85b3fd62ea1a	1237	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
NYX	0:85b3fd62ea1a	1238	{
NYX	0:85b3fd62ea1a	1239	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	1240	goto error;
NYX	0:85b3fd62ea1a	1241	}
NYX	0:85b3fd62ea1a	1242
NYX	0:85b3fd62ea1a	1243	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	1244	{
NYX	0:85b3fd62ea1a	1245	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	1246	goto error;
NYX	0:85b3fd62ea1a	1247	}
NYX	0:85b3fd62ea1a	1248
NYX	0:85b3fd62ea1a	1249	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
NYX	0:85b3fd62ea1a	1250	if(hspi->State == HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	1251	{
NYX	0:85b3fd62ea1a	1252	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
NYX	0:85b3fd62ea1a	1253	}
NYX	0:85b3fd62ea1a	1254
NYX	0:85b3fd62ea1a	1255	/* Set the transaction information */
NYX	0:85b3fd62ea1a	1256	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1257	hspi->pTxBuffPtr = (uint8_t *)pTxData;
NYX	0:85b3fd62ea1a	1258	hspi->TxXferSize = Size;
NYX	0:85b3fd62ea1a	1259	hspi->TxXferCount = Size;
NYX	0:85b3fd62ea1a	1260	hspi->pRxBuffPtr = (uint8_t *)pRxData;
NYX	0:85b3fd62ea1a	1261	hspi->RxXferSize = Size;
NYX	0:85b3fd62ea1a	1262	hspi->RxXferCount = Size;
NYX	0:85b3fd62ea1a	1263
NYX	0:85b3fd62ea1a	1264	/* Set the function for IT treatment */
NYX	0:85b3fd62ea1a	1265	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
NYX	0:85b3fd62ea1a	1266	{
NYX	0:85b3fd62ea1a	1267	hspi->RxISR = SPI_2linesRxISR_16BIT;
NYX	0:85b3fd62ea1a	1268	hspi->TxISR = SPI_2linesTxISR_16BIT;
NYX	0:85b3fd62ea1a	1269	}
NYX	0:85b3fd62ea1a	1270	else
NYX	0:85b3fd62ea1a	1271	{
NYX	0:85b3fd62ea1a	1272	hspi->RxISR = SPI_2linesRxISR_8BIT;
NYX	0:85b3fd62ea1a	1273	hspi->TxISR = SPI_2linesTxISR_8BIT;
NYX	0:85b3fd62ea1a	1274	}
NYX	0:85b3fd62ea1a	1275
NYX	0:85b3fd62ea1a	1276	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	1277	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	1278	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	1279	{
NYX	0:85b3fd62ea1a	1280	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	1281	}
NYX	0:85b3fd62ea1a	1282	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	1283
NYX	0:85b3fd62ea1a	1284	/* Enable TXE, RXNE and ERR interrupt */
NYX	0:85b3fd62ea1a	1285	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	1286
NYX	0:85b3fd62ea1a	1287	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	1288	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	1289	{
NYX	0:85b3fd62ea1a	1290	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	1291	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	1292	}
NYX	0:85b3fd62ea1a	1293
NYX	0:85b3fd62ea1a	1294	error :
NYX	0:85b3fd62ea1a	1295	/* Process Unlocked */
NYX	0:85b3fd62ea1a	1296	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1297	return errorcode;
NYX	0:85b3fd62ea1a	1298	}
NYX	0:85b3fd62ea1a	1299
NYX	0:85b3fd62ea1a	1300	/**
NYX	0:85b3fd62ea1a	1301	* @brief Transmit an amount of data in non-blocking mode with DMA.
NYX	0:85b3fd62ea1a	1302	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1303	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	1304	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	1305	* @param Size: amount of data to be sent
NYX	0:85b3fd62ea1a	1306	* @retval HAL status
NYX	0:85b3fd62ea1a	1307	*/
NYX	0:85b3fd62ea1a	1308	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
NYX	0:85b3fd62ea1a	1309	{
NYX	0:85b3fd62ea1a	1310	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	1311
NYX	0:85b3fd62ea1a	1312	/* Check Direction parameter */
NYX	0:85b3fd62ea1a	1313	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
NYX	0:85b3fd62ea1a	1314
NYX	0:85b3fd62ea1a	1315	/* Process Locked */
NYX	0:85b3fd62ea1a	1316	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	1317
NYX	0:85b3fd62ea1a	1318	if(hspi->State != HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	1319	{
NYX	0:85b3fd62ea1a	1320	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	1321	goto error;
NYX	0:85b3fd62ea1a	1322	}
NYX	0:85b3fd62ea1a	1323
NYX	0:85b3fd62ea1a	1324	if((pData == NULL) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	1325	{
NYX	0:85b3fd62ea1a	1326	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	1327	goto error;
NYX	0:85b3fd62ea1a	1328	}
NYX	0:85b3fd62ea1a	1329
NYX	0:85b3fd62ea1a	1330	/* Set the transaction information */
NYX	0:85b3fd62ea1a	1331	hspi->State = HAL_SPI_STATE_BUSY_TX;
NYX	0:85b3fd62ea1a	1332	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1333	hspi->pTxBuffPtr = (uint8_t *)pData;
NYX	0:85b3fd62ea1a	1334	hspi->TxXferSize = Size;
NYX	0:85b3fd62ea1a	1335	hspi->TxXferCount = Size;
NYX	0:85b3fd62ea1a	1336
NYX	0:85b3fd62ea1a	1337	/* Init field not used in handle to zero */
NYX	0:85b3fd62ea1a	1338	hspi->pRxBuffPtr = (uint8_t *)NULL;
NYX	0:85b3fd62ea1a	1339	hspi->TxISR = NULL;
NYX	0:85b3fd62ea1a	1340	hspi->RxISR = NULL;
NYX	0:85b3fd62ea1a	1341	hspi->RxXferSize = 0U;
NYX	0:85b3fd62ea1a	1342	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	1343
NYX	0:85b3fd62ea1a	1344	/* Configure communication direction : 1Line */
NYX	0:85b3fd62ea1a	1345	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
NYX	0:85b3fd62ea1a	1346	{
NYX	0:85b3fd62ea1a	1347	SPI_1LINE_TX(hspi);
NYX	0:85b3fd62ea1a	1348	}
NYX	0:85b3fd62ea1a	1349
NYX	0:85b3fd62ea1a	1350	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	1351	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	1352	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	1353	{
NYX	0:85b3fd62ea1a	1354	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	1355	}
NYX	0:85b3fd62ea1a	1356	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	1357
NYX	0:85b3fd62ea1a	1358	/* Set the SPI TxDMA Half transfer complete callback */
NYX	0:85b3fd62ea1a	1359	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
NYX	0:85b3fd62ea1a	1360
NYX	0:85b3fd62ea1a	1361	/* Set the SPI TxDMA transfer complete callback */
NYX	0:85b3fd62ea1a	1362	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
NYX	0:85b3fd62ea1a	1363
NYX	0:85b3fd62ea1a	1364	/* Set the DMA error callback */
NYX	0:85b3fd62ea1a	1365	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
NYX	0:85b3fd62ea1a	1366
NYX	0:85b3fd62ea1a	1367	/* Set the DMA AbortCpltCallback */
NYX	0:85b3fd62ea1a	1368	hspi->hdmatx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1369
NYX	0:85b3fd62ea1a	1370	/* Enable the Tx DMA Stream */
NYX	0:85b3fd62ea1a	1371	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
NYX	0:85b3fd62ea1a	1372
NYX	0:85b3fd62ea1a	1373	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	1374	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	1375	{
NYX	0:85b3fd62ea1a	1376	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	1377	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	1378	}
NYX	0:85b3fd62ea1a	1379
NYX	0:85b3fd62ea1a	1380	/* Enable the SPI Error Interrupt Bit */
NYX	0:85b3fd62ea1a	1381	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
NYX	0:85b3fd62ea1a	1382
NYX	0:85b3fd62ea1a	1383	/* Enable Tx DMA Request */
NYX	0:85b3fd62ea1a	1384	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
NYX	0:85b3fd62ea1a	1385
NYX	0:85b3fd62ea1a	1386	error :
NYX	0:85b3fd62ea1a	1387	/* Process Unlocked */
NYX	0:85b3fd62ea1a	1388	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1389	return errorcode;
NYX	0:85b3fd62ea1a	1390	}
NYX	0:85b3fd62ea1a	1391
NYX	0:85b3fd62ea1a	1392	/**
NYX	0:85b3fd62ea1a	1393	* @brief Receive an amount of data in non-blocking mode with DMA.
NYX	0:85b3fd62ea1a	1394	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1395	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	1396	* @param pData: pointer to data buffer
NYX	0:85b3fd62ea1a	1397	* @note When the CRC feature is enabled the pData Length must be Size + 1.
NYX	0:85b3fd62ea1a	1398	* @param Size: amount of data to be sent
NYX	0:85b3fd62ea1a	1399	* @retval HAL status
NYX	0:85b3fd62ea1a	1400	*/
NYX	0:85b3fd62ea1a	1401	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
NYX	0:85b3fd62ea1a	1402	{
NYX	0:85b3fd62ea1a	1403	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	1404
NYX	0:85b3fd62ea1a	1405	if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
NYX	0:85b3fd62ea1a	1406	{
NYX	0:85b3fd62ea1a	1407	hspi->State = HAL_SPI_STATE_BUSY_RX;
NYX	0:85b3fd62ea1a	1408	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
NYX	0:85b3fd62ea1a	1409	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
NYX	0:85b3fd62ea1a	1410	}
NYX	0:85b3fd62ea1a	1411
NYX	0:85b3fd62ea1a	1412	/* Process Locked */
NYX	0:85b3fd62ea1a	1413	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	1414
NYX	0:85b3fd62ea1a	1415	if(hspi->State != HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	1416	{
NYX	0:85b3fd62ea1a	1417	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	1418	goto error;
NYX	0:85b3fd62ea1a	1419	}
NYX	0:85b3fd62ea1a	1420
NYX	0:85b3fd62ea1a	1421	if((pData == NULL) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	1422	{
NYX	0:85b3fd62ea1a	1423	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	1424	goto error;
NYX	0:85b3fd62ea1a	1425	}
NYX	0:85b3fd62ea1a	1426
NYX	0:85b3fd62ea1a	1427	/* Set the transaction information */
NYX	0:85b3fd62ea1a	1428	hspi->State = HAL_SPI_STATE_BUSY_RX;
NYX	0:85b3fd62ea1a	1429	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1430	hspi->pRxBuffPtr = (uint8_t *)pData;
NYX	0:85b3fd62ea1a	1431	hspi->RxXferSize = Size;
NYX	0:85b3fd62ea1a	1432	hspi->RxXferCount = Size;
NYX	0:85b3fd62ea1a	1433
NYX	0:85b3fd62ea1a	1434	/Init field not used in handle to zero /
NYX	0:85b3fd62ea1a	1435	hspi->RxISR = NULL;
NYX	0:85b3fd62ea1a	1436	hspi->TxISR = NULL;
NYX	0:85b3fd62ea1a	1437	hspi->TxXferSize = 0U;
NYX	0:85b3fd62ea1a	1438	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	1439
NYX	0:85b3fd62ea1a	1440	/* Configure communication direction : 1Line */
NYX	0:85b3fd62ea1a	1441	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
NYX	0:85b3fd62ea1a	1442	{
NYX	0:85b3fd62ea1a	1443	SPI_1LINE_RX(hspi);
NYX	0:85b3fd62ea1a	1444	}
NYX	0:85b3fd62ea1a	1445
NYX	0:85b3fd62ea1a	1446	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	1447	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	1448	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	1449	{
NYX	0:85b3fd62ea1a	1450	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	1451	}
NYX	0:85b3fd62ea1a	1452	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	1453
NYX	0:85b3fd62ea1a	1454	/* Set the SPI RxDMA Half transfer complete callback */
NYX	0:85b3fd62ea1a	1455	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
NYX	0:85b3fd62ea1a	1456
NYX	0:85b3fd62ea1a	1457	/* Set the SPI Rx DMA transfer complete callback */
NYX	0:85b3fd62ea1a	1458	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
NYX	0:85b3fd62ea1a	1459
NYX	0:85b3fd62ea1a	1460	/* Set the DMA error callback */
NYX	0:85b3fd62ea1a	1461	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
NYX	0:85b3fd62ea1a	1462
NYX	0:85b3fd62ea1a	1463	/* Set the DMA AbortCpltCallback */
NYX	0:85b3fd62ea1a	1464	hspi->hdmarx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1465
NYX	0:85b3fd62ea1a	1466	/* Enable the Rx DMA Stream */
NYX	0:85b3fd62ea1a	1467	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
NYX	0:85b3fd62ea1a	1468
NYX	0:85b3fd62ea1a	1469	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	1470	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	1471	{
NYX	0:85b3fd62ea1a	1472	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	1473	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	1474	}
NYX	0:85b3fd62ea1a	1475
NYX	0:85b3fd62ea1a	1476	/* Enable the SPI Error Interrupt Bit */
NYX	0:85b3fd62ea1a	1477	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
NYX	0:85b3fd62ea1a	1478
NYX	0:85b3fd62ea1a	1479	/* Enable Rx DMA Request */
NYX	0:85b3fd62ea1a	1480	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	1481
NYX	0:85b3fd62ea1a	1482	error:
NYX	0:85b3fd62ea1a	1483	/* Process Unlocked */
NYX	0:85b3fd62ea1a	1484	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1485	return errorcode;
NYX	0:85b3fd62ea1a	1486	}
NYX	0:85b3fd62ea1a	1487
NYX	0:85b3fd62ea1a	1488	/**
NYX	0:85b3fd62ea1a	1489	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
NYX	0:85b3fd62ea1a	1490	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1491	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	1492	* @param pTxData: pointer to transmission data buffer
NYX	0:85b3fd62ea1a	1493	* @param pRxData: pointer to reception data buffer
NYX	0:85b3fd62ea1a	1494	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
NYX	0:85b3fd62ea1a	1495	* @param Size: amount of data to be sent
NYX	0:85b3fd62ea1a	1496	* @retval HAL status
NYX	0:85b3fd62ea1a	1497	*/
NYX	0:85b3fd62ea1a	1498	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
NYX	0:85b3fd62ea1a	1499	{
NYX	0:85b3fd62ea1a	1500	uint32_t tmp = 0U, tmp1 = 0U;
NYX	0:85b3fd62ea1a	1501	HAL_StatusTypeDef errorcode = HAL_OK;
NYX	0:85b3fd62ea1a	1502
NYX	0:85b3fd62ea1a	1503	/* Check Direction parameter */
NYX	0:85b3fd62ea1a	1504	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
NYX	0:85b3fd62ea1a	1505
NYX	0:85b3fd62ea1a	1506	/* Process locked */
NYX	0:85b3fd62ea1a	1507	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	1508
NYX	0:85b3fd62ea1a	1509	tmp = hspi->State;
NYX	0:85b3fd62ea1a	1510	tmp1 = hspi->Init.Mode;
NYX	0:85b3fd62ea1a	1511	if(!((tmp == HAL_SPI_STATE_READY) \|\|
NYX	0:85b3fd62ea1a	1512	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
NYX	0:85b3fd62ea1a	1513	{
NYX	0:85b3fd62ea1a	1514	errorcode = HAL_BUSY;
NYX	0:85b3fd62ea1a	1515	goto error;
NYX	0:85b3fd62ea1a	1516	}
NYX	0:85b3fd62ea1a	1517
NYX	0:85b3fd62ea1a	1518	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
NYX	0:85b3fd62ea1a	1519	{
NYX	0:85b3fd62ea1a	1520	errorcode = HAL_ERROR;
NYX	0:85b3fd62ea1a	1521	goto error;
NYX	0:85b3fd62ea1a	1522	}
NYX	0:85b3fd62ea1a	1523
NYX	0:85b3fd62ea1a	1524	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
NYX	0:85b3fd62ea1a	1525	if(hspi->State == HAL_SPI_STATE_READY)
NYX	0:85b3fd62ea1a	1526	{
NYX	0:85b3fd62ea1a	1527	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
NYX	0:85b3fd62ea1a	1528	}
NYX	0:85b3fd62ea1a	1529
NYX	0:85b3fd62ea1a	1530	/* Set the transaction information */
NYX	0:85b3fd62ea1a	1531	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1532	hspi->pTxBuffPtr = (uint8_t*)pTxData;
NYX	0:85b3fd62ea1a	1533	hspi->TxXferSize = Size;
NYX	0:85b3fd62ea1a	1534	hspi->TxXferCount = Size;
NYX	0:85b3fd62ea1a	1535	hspi->pRxBuffPtr = (uint8_t*)pRxData;
NYX	0:85b3fd62ea1a	1536	hspi->RxXferSize = Size;
NYX	0:85b3fd62ea1a	1537	hspi->RxXferCount = Size;
NYX	0:85b3fd62ea1a	1538
NYX	0:85b3fd62ea1a	1539	/* Init field not used in handle to zero */
NYX	0:85b3fd62ea1a	1540	hspi->RxISR = NULL;
NYX	0:85b3fd62ea1a	1541	hspi->TxISR = NULL;
NYX	0:85b3fd62ea1a	1542
NYX	0:85b3fd62ea1a	1543	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	1544	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	1545	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	1546	{
NYX	0:85b3fd62ea1a	1547	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	1548	}
NYX	0:85b3fd62ea1a	1549	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	1550
NYX	0:85b3fd62ea1a	1551	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
NYX	0:85b3fd62ea1a	1552	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
NYX	0:85b3fd62ea1a	1553	{
NYX	0:85b3fd62ea1a	1554	/* Set the SPI Rx DMA Half transfer complete callback */
NYX	0:85b3fd62ea1a	1555	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
NYX	0:85b3fd62ea1a	1556	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
NYX	0:85b3fd62ea1a	1557	}
NYX	0:85b3fd62ea1a	1558	else
NYX	0:85b3fd62ea1a	1559	{
NYX	0:85b3fd62ea1a	1560	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
NYX	0:85b3fd62ea1a	1561	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
NYX	0:85b3fd62ea1a	1562	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
NYX	0:85b3fd62ea1a	1563	}
NYX	0:85b3fd62ea1a	1564
NYX	0:85b3fd62ea1a	1565	/* Set the DMA error callback */
NYX	0:85b3fd62ea1a	1566	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
NYX	0:85b3fd62ea1a	1567
NYX	0:85b3fd62ea1a	1568	/* Set the DMA AbortCpltCallback */
NYX	0:85b3fd62ea1a	1569	hspi->hdmarx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1570
NYX	0:85b3fd62ea1a	1571	/* Enable the Rx DMA Stream */
NYX	0:85b3fd62ea1a	1572	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
NYX	0:85b3fd62ea1a	1573
NYX	0:85b3fd62ea1a	1574	/* Enable Rx DMA Request */
NYX	0:85b3fd62ea1a	1575	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	1576
NYX	0:85b3fd62ea1a	1577	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
NYX	0:85b3fd62ea1a	1578	is performed in DMA reception complete callback */
NYX	0:85b3fd62ea1a	1579	hspi->hdmatx->XferHalfCpltCallback = NULL;
NYX	0:85b3fd62ea1a	1580	hspi->hdmatx->XferCpltCallback = NULL;
NYX	0:85b3fd62ea1a	1581	hspi->hdmatx->XferErrorCallback = NULL;
NYX	0:85b3fd62ea1a	1582	hspi->hdmatx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1583
NYX	0:85b3fd62ea1a	1584	/* Enable the Tx DMA Stream */
NYX	0:85b3fd62ea1a	1585	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
NYX	0:85b3fd62ea1a	1586
NYX	0:85b3fd62ea1a	1587	/* Check if the SPI is already enabled */
NYX	0:85b3fd62ea1a	1588	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
NYX	0:85b3fd62ea1a	1589	{
NYX	0:85b3fd62ea1a	1590	/* Enable SPI peripheral */
NYX	0:85b3fd62ea1a	1591	__HAL_SPI_ENABLE(hspi);
NYX	0:85b3fd62ea1a	1592	}
NYX	0:85b3fd62ea1a	1593	/* Enable the SPI Error Interrupt Bit */
NYX	0:85b3fd62ea1a	1594	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
NYX	0:85b3fd62ea1a	1595
NYX	0:85b3fd62ea1a	1596	/* Enable Tx DMA Request */
NYX	0:85b3fd62ea1a	1597	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
NYX	0:85b3fd62ea1a	1598
NYX	0:85b3fd62ea1a	1599	error :
NYX	0:85b3fd62ea1a	1600	/* Process Unlocked */
NYX	0:85b3fd62ea1a	1601	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1602	return errorcode;
NYX	0:85b3fd62ea1a	1603	}
NYX	0:85b3fd62ea1a	1604
NYX	0:85b3fd62ea1a	1605	/**
NYX	0:85b3fd62ea1a	1606	* @brief Abort ongoing transfer (blocking mode).
NYX	0:85b3fd62ea1a	1607	* @param hspi SPI handle.
NYX	0:85b3fd62ea1a	1608	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
NYX	0:85b3fd62ea1a	1609	* started in Interrupt or DMA mode.
NYX	0:85b3fd62ea1a	1610	* This procedure performs following operations :
NYX	0:85b3fd62ea1a	1611	* - Disable SPI Interrupts (depending of transfer direction)
NYX	0:85b3fd62ea1a	1612	* - Disable the DMA transfer in the peripheral register (if enabled)
NYX	0:85b3fd62ea1a	1613	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
NYX	0:85b3fd62ea1a	1614	* - Set handle State to READY
NYX	0:85b3fd62ea1a	1615	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
NYX	0:85b3fd62ea1a	1616	* @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
NYX	0:85b3fd62ea1a	1617	* before starting new SPI receive process.
NYX	0:85b3fd62ea1a	1618	* @retval HAL status
NYX	0:85b3fd62ea1a	1619	*/
NYX	0:85b3fd62ea1a	1620	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	1621	{
NYX	0:85b3fd62ea1a	1622	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
NYX	0:85b3fd62ea1a	1623
NYX	0:85b3fd62ea1a	1624	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
NYX	0:85b3fd62ea1a	1625	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
NYX	0:85b3fd62ea1a	1626	{
NYX	0:85b3fd62ea1a	1627	hspi->TxISR = SPI_AbortTx_ISR;
NYX	0:85b3fd62ea1a	1628	}
NYX	0:85b3fd62ea1a	1629
NYX	0:85b3fd62ea1a	1630	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
NYX	0:85b3fd62ea1a	1631	{
NYX	0:85b3fd62ea1a	1632	hspi->RxISR = SPI_AbortRx_ISR;
NYX	0:85b3fd62ea1a	1633	}
NYX	0:85b3fd62ea1a	1634
NYX	0:85b3fd62ea1a	1635	/* Clear ERRIE interrupts in case of DMA Mode */
NYX	0:85b3fd62ea1a	1636	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
NYX	0:85b3fd62ea1a	1637
NYX	0:85b3fd62ea1a	1638	/* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
NYX	0:85b3fd62ea1a	1639	if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
NYX	0:85b3fd62ea1a	1640	{
NYX	0:85b3fd62ea1a	1641	/* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */
NYX	0:85b3fd62ea1a	1642	if(hspi->hdmatx != NULL)
NYX	0:85b3fd62ea1a	1643	{
NYX	0:85b3fd62ea1a	1644	/* Set the SPI DMA Abort callback :
NYX	0:85b3fd62ea1a	1645	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
NYX	0:85b3fd62ea1a	1646	hspi->hdmatx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1647
NYX	0:85b3fd62ea1a	1648	/* Abort DMA Tx Handle linked to SPI Peripheral */
NYX	0:85b3fd62ea1a	1649	HAL_DMA_Abort(hspi->hdmatx);
NYX	0:85b3fd62ea1a	1650
NYX	0:85b3fd62ea1a	1651	/* Disable Tx DMA Request */
NYX	0:85b3fd62ea1a	1652	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
NYX	0:85b3fd62ea1a	1653
NYX	0:85b3fd62ea1a	1654	/* Wait until TXE flag is set */
NYX	0:85b3fd62ea1a	1655	do
NYX	0:85b3fd62ea1a	1656	{
NYX	0:85b3fd62ea1a	1657	if(count-- == 0U)
NYX	0:85b3fd62ea1a	1658	{
NYX	0:85b3fd62ea1a	1659	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	1660	break;
NYX	0:85b3fd62ea1a	1661	}
NYX	0:85b3fd62ea1a	1662	}
NYX	0:85b3fd62ea1a	1663	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
NYX	0:85b3fd62ea1a	1664	}
NYX	0:85b3fd62ea1a	1665	/* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */
NYX	0:85b3fd62ea1a	1666	if(hspi->hdmarx != NULL)
NYX	0:85b3fd62ea1a	1667	{
NYX	0:85b3fd62ea1a	1668	/* Set the SPI DMA Abort callback :
NYX	0:85b3fd62ea1a	1669	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
NYX	0:85b3fd62ea1a	1670	hspi->hdmarx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1671
NYX	0:85b3fd62ea1a	1672	/* Abort DMA Rx Handle linked to SPI Peripheral */
NYX	0:85b3fd62ea1a	1673	HAL_DMA_Abort(hspi->hdmarx);
NYX	0:85b3fd62ea1a	1674
NYX	0:85b3fd62ea1a	1675	/* Disable peripheral */
NYX	0:85b3fd62ea1a	1676	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	1677
NYX	0:85b3fd62ea1a	1678	/* Disable Rx DMA Request */
NYX	0:85b3fd62ea1a	1679	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
NYX	0:85b3fd62ea1a	1680
NYX	0:85b3fd62ea1a	1681	}
NYX	0:85b3fd62ea1a	1682	}
NYX	0:85b3fd62ea1a	1683	/* Reset Tx and Rx transfer counters */
NYX	0:85b3fd62ea1a	1684	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	1685	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	1686
NYX	0:85b3fd62ea1a	1687	/* Reset errorCode */
NYX	0:85b3fd62ea1a	1688	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1689
NYX	0:85b3fd62ea1a	1690	/* Clear the Error flags in the SR register */
NYX	0:85b3fd62ea1a	1691	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	1692	__HAL_SPI_CLEAR_FREFLAG(hspi);
NYX	0:85b3fd62ea1a	1693
NYX	0:85b3fd62ea1a	1694	/* Restore hspi->state to ready */
NYX	0:85b3fd62ea1a	1695	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	1696
NYX	0:85b3fd62ea1a	1697	return HAL_OK;
NYX	0:85b3fd62ea1a	1698	}
NYX	0:85b3fd62ea1a	1699
NYX	0:85b3fd62ea1a	1700	/**
NYX	0:85b3fd62ea1a	1701	* @brief Abort ongoing transfer (Interrupt mode).
NYX	0:85b3fd62ea1a	1702	* @param hspi SPI handle.
NYX	0:85b3fd62ea1a	1703	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
NYX	0:85b3fd62ea1a	1704	* started in Interrupt or DMA mode.
NYX	0:85b3fd62ea1a	1705	* This procedure performs following operations :
NYX	0:85b3fd62ea1a	1706	* - Disable SPI Interrupts (depending of transfer direction)
NYX	0:85b3fd62ea1a	1707	* - Disable the DMA transfer in the peripheral register (if enabled)
NYX	0:85b3fd62ea1a	1708	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
NYX	0:85b3fd62ea1a	1709	* - Set handle State to READY
NYX	0:85b3fd62ea1a	1710	* - At abort completion, call user abort complete callback
NYX	0:85b3fd62ea1a	1711	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
NYX	0:85b3fd62ea1a	1712	* considered as completed only when user abort complete callback is executed (not when exiting function).
NYX	0:85b3fd62ea1a	1713	* @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
NYX	0:85b3fd62ea1a	1714	* before starting new SPI receive process.
NYX	0:85b3fd62ea1a	1715	* @retval HAL status
NYX	0:85b3fd62ea1a	1716	*/
NYX	0:85b3fd62ea1a	1717	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	1718	{
NYX	0:85b3fd62ea1a	1719	uint32_t abortcplt;
NYX	0:85b3fd62ea1a	1720
NYX	0:85b3fd62ea1a	1721	/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
NYX	0:85b3fd62ea1a	1722	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
NYX	0:85b3fd62ea1a	1723	{
NYX	0:85b3fd62ea1a	1724	hspi->TxISR = SPI_AbortTx_ISR;
NYX	0:85b3fd62ea1a	1725	}
NYX	0:85b3fd62ea1a	1726
NYX	0:85b3fd62ea1a	1727	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
NYX	0:85b3fd62ea1a	1728	{
NYX	0:85b3fd62ea1a	1729	hspi->RxISR = SPI_AbortRx_ISR;
NYX	0:85b3fd62ea1a	1730	}
NYX	0:85b3fd62ea1a	1731
NYX	0:85b3fd62ea1a	1732	/* Clear ERRIE interrupts in case of DMA Mode */
NYX	0:85b3fd62ea1a	1733	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
NYX	0:85b3fd62ea1a	1734
NYX	0:85b3fd62ea1a	1735	abortcplt = 1U;
NYX	0:85b3fd62ea1a	1736
NYX	0:85b3fd62ea1a	1737	/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
NYX	0:85b3fd62ea1a	1738	before any call to DMA Abort functions */
NYX	0:85b3fd62ea1a	1739	/* DMA Tx Handle is valid */
NYX	0:85b3fd62ea1a	1740	if(hspi->hdmatx != NULL)
NYX	0:85b3fd62ea1a	1741	{
NYX	0:85b3fd62ea1a	1742	/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
NYX	0:85b3fd62ea1a	1743	Otherwise, set it to NULL */
NYX	0:85b3fd62ea1a	1744	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
NYX	0:85b3fd62ea1a	1745	{
NYX	0:85b3fd62ea1a	1746	hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
NYX	0:85b3fd62ea1a	1747	}
NYX	0:85b3fd62ea1a	1748	else
NYX	0:85b3fd62ea1a	1749	{
NYX	0:85b3fd62ea1a	1750	hspi->hdmatx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1751	}
NYX	0:85b3fd62ea1a	1752	}
NYX	0:85b3fd62ea1a	1753	/* DMA Rx Handle is valid */
NYX	0:85b3fd62ea1a	1754	if(hspi->hdmarx != NULL)
NYX	0:85b3fd62ea1a	1755	{
NYX	0:85b3fd62ea1a	1756	/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
NYX	0:85b3fd62ea1a	1757	Otherwise, set it to NULL */
NYX	0:85b3fd62ea1a	1758	if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
NYX	0:85b3fd62ea1a	1759	{
NYX	0:85b3fd62ea1a	1760	hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
NYX	0:85b3fd62ea1a	1761	}
NYX	0:85b3fd62ea1a	1762	else
NYX	0:85b3fd62ea1a	1763	{
NYX	0:85b3fd62ea1a	1764	hspi->hdmarx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1765	}
NYX	0:85b3fd62ea1a	1766	}
NYX	0:85b3fd62ea1a	1767
NYX	0:85b3fd62ea1a	1768	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
NYX	0:85b3fd62ea1a	1769	if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
NYX	0:85b3fd62ea1a	1770	{
NYX	0:85b3fd62ea1a	1771	/* Abort the SPI DMA Tx channel */
NYX	0:85b3fd62ea1a	1772	if(hspi->hdmatx != NULL)
NYX	0:85b3fd62ea1a	1773	{
NYX	0:85b3fd62ea1a	1774	/* Abort DMA Tx Handle linked to SPI Peripheral */
NYX	0:85b3fd62ea1a	1775	if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
NYX	0:85b3fd62ea1a	1776	{
NYX	0:85b3fd62ea1a	1777	hspi->hdmatx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1778	}
NYX	0:85b3fd62ea1a	1779	else
NYX	0:85b3fd62ea1a	1780	{
NYX	0:85b3fd62ea1a	1781	abortcplt = 0U;
NYX	0:85b3fd62ea1a	1782	}
NYX	0:85b3fd62ea1a	1783	}
NYX	0:85b3fd62ea1a	1784	/* Abort the SPI DMA Rx channel */
NYX	0:85b3fd62ea1a	1785	if(hspi->hdmarx != NULL)
NYX	0:85b3fd62ea1a	1786	{
NYX	0:85b3fd62ea1a	1787	/* Abort DMA Rx Handle linked to SPI Peripheral */
NYX	0:85b3fd62ea1a	1788	if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
NYX	0:85b3fd62ea1a	1789	{
NYX	0:85b3fd62ea1a	1790	hspi->hdmarx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1791	abortcplt = 1U;
NYX	0:85b3fd62ea1a	1792	}
NYX	0:85b3fd62ea1a	1793	else
NYX	0:85b3fd62ea1a	1794	{
NYX	0:85b3fd62ea1a	1795	abortcplt = 0U;
NYX	0:85b3fd62ea1a	1796	}
NYX	0:85b3fd62ea1a	1797	}
NYX	0:85b3fd62ea1a	1798	}
NYX	0:85b3fd62ea1a	1799
NYX	0:85b3fd62ea1a	1800	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
NYX	0:85b3fd62ea1a	1801	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
NYX	0:85b3fd62ea1a	1802	{
NYX	0:85b3fd62ea1a	1803	/* Abort the SPI DMA Tx channel */
NYX	0:85b3fd62ea1a	1804	if(hspi->hdmatx != NULL)
NYX	0:85b3fd62ea1a	1805	{
NYX	0:85b3fd62ea1a	1806	/* Abort DMA Tx Handle linked to SPI Peripheral */
NYX	0:85b3fd62ea1a	1807	if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
NYX	0:85b3fd62ea1a	1808	{
NYX	0:85b3fd62ea1a	1809	hspi->hdmatx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1810	}
NYX	0:85b3fd62ea1a	1811	else
NYX	0:85b3fd62ea1a	1812	{
NYX	0:85b3fd62ea1a	1813	abortcplt = 0U;
NYX	0:85b3fd62ea1a	1814	}
NYX	0:85b3fd62ea1a	1815	}
NYX	0:85b3fd62ea1a	1816	}
NYX	0:85b3fd62ea1a	1817	/* Disable the SPI DMA Tx or the SPI Rx request if enabled */
NYX	0:85b3fd62ea1a	1818	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
NYX	0:85b3fd62ea1a	1819	{
NYX	0:85b3fd62ea1a	1820	/* Abort the SPI DMA Rx channel */
NYX	0:85b3fd62ea1a	1821	if(hspi->hdmarx != NULL)
NYX	0:85b3fd62ea1a	1822	{
NYX	0:85b3fd62ea1a	1823	/* Abort DMA Rx Handle linked to SPI Peripheral */
NYX	0:85b3fd62ea1a	1824	if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
NYX	0:85b3fd62ea1a	1825	{
NYX	0:85b3fd62ea1a	1826	hspi->hdmarx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	1827	}
NYX	0:85b3fd62ea1a	1828	else
NYX	0:85b3fd62ea1a	1829	{
NYX	0:85b3fd62ea1a	1830	abortcplt = 0U;
NYX	0:85b3fd62ea1a	1831	}
NYX	0:85b3fd62ea1a	1832	}
NYX	0:85b3fd62ea1a	1833	}
NYX	0:85b3fd62ea1a	1834
NYX	0:85b3fd62ea1a	1835	if(abortcplt == 1U)
NYX	0:85b3fd62ea1a	1836	{
NYX	0:85b3fd62ea1a	1837	/* Reset Tx and Rx transfer counters */
NYX	0:85b3fd62ea1a	1838	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	1839	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	1840
NYX	0:85b3fd62ea1a	1841	/* Reset errorCode */
NYX	0:85b3fd62ea1a	1842	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	1843
NYX	0:85b3fd62ea1a	1844	/* Clear the Error flags in the SR register */
NYX	0:85b3fd62ea1a	1845	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	1846	__HAL_SPI_CLEAR_FREFLAG(hspi);
NYX	0:85b3fd62ea1a	1847
NYX	0:85b3fd62ea1a	1848	/* Restore hspi->State to Ready */
NYX	0:85b3fd62ea1a	1849	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	1850
NYX	0:85b3fd62ea1a	1851	/* As no DMA to be aborted, call directly user Abort complete callback */
NYX	0:85b3fd62ea1a	1852	HAL_SPI_AbortCpltCallback(hspi);
NYX	0:85b3fd62ea1a	1853	}
NYX	0:85b3fd62ea1a	1854	return HAL_OK;
NYX	0:85b3fd62ea1a	1855	}
NYX	0:85b3fd62ea1a	1856
NYX	0:85b3fd62ea1a	1857	/**
NYX	0:85b3fd62ea1a	1858	* @brief Pause the DMA Transfer.
NYX	0:85b3fd62ea1a	1859	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1860	* the configuration information for the specified SPI module.
NYX	0:85b3fd62ea1a	1861	* @retval HAL status
NYX	0:85b3fd62ea1a	1862	*/
NYX	0:85b3fd62ea1a	1863	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	1864	{
NYX	0:85b3fd62ea1a	1865	/* Process Locked */
NYX	0:85b3fd62ea1a	1866	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	1867
NYX	0:85b3fd62ea1a	1868	/* Disable the SPI DMA Tx & Rx requests */
NYX	0:85b3fd62ea1a	1869	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	1870
NYX	0:85b3fd62ea1a	1871	/* Process Unlocked */
NYX	0:85b3fd62ea1a	1872	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1873
NYX	0:85b3fd62ea1a	1874	return HAL_OK;
NYX	0:85b3fd62ea1a	1875	}
NYX	0:85b3fd62ea1a	1876
NYX	0:85b3fd62ea1a	1877	/**
NYX	0:85b3fd62ea1a	1878	* @brief Resume the DMA Transfer.
NYX	0:85b3fd62ea1a	1879	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1880	* the configuration information for the specified SPI module.
NYX	0:85b3fd62ea1a	1881	* @retval HAL status
NYX	0:85b3fd62ea1a	1882	*/
NYX	0:85b3fd62ea1a	1883	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	1884	{
NYX	0:85b3fd62ea1a	1885	/* Process Locked */
NYX	0:85b3fd62ea1a	1886	__HAL_LOCK(hspi);
NYX	0:85b3fd62ea1a	1887
NYX	0:85b3fd62ea1a	1888	/* Enable the SPI DMA Tx & Rx requests */
NYX	0:85b3fd62ea1a	1889	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	1890
NYX	0:85b3fd62ea1a	1891	/* Process Unlocked */
NYX	0:85b3fd62ea1a	1892	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	1893
NYX	0:85b3fd62ea1a	1894	return HAL_OK;
NYX	0:85b3fd62ea1a	1895	}
NYX	0:85b3fd62ea1a	1896
NYX	0:85b3fd62ea1a	1897	/**
NYX	0:85b3fd62ea1a	1898	* @brief Stop the DMA Transfer.
NYX	0:85b3fd62ea1a	1899	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1900	* the configuration information for the specified SPI module.
NYX	0:85b3fd62ea1a	1901	* @retval HAL status
NYX	0:85b3fd62ea1a	1902	*/
NYX	0:85b3fd62ea1a	1903	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	1904	{
NYX	0:85b3fd62ea1a	1905	/* The Lock is not implemented on this API to allow the user application
NYX	0:85b3fd62ea1a	1906	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
NYX	0:85b3fd62ea1a	1907	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
NYX	0:85b3fd62ea1a	1908	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
NYX	0:85b3fd62ea1a	1909	*/
NYX	0:85b3fd62ea1a	1910
NYX	0:85b3fd62ea1a	1911	/* Abort the SPI DMA tx Stream */
NYX	0:85b3fd62ea1a	1912	if(hspi->hdmatx != NULL)
NYX	0:85b3fd62ea1a	1913	{
NYX	0:85b3fd62ea1a	1914	HAL_DMA_Abort(hspi->hdmatx);
NYX	0:85b3fd62ea1a	1915	}
NYX	0:85b3fd62ea1a	1916	/* Abort the SPI DMA rx Stream */
NYX	0:85b3fd62ea1a	1917	if(hspi->hdmarx != NULL)
NYX	0:85b3fd62ea1a	1918	{
NYX	0:85b3fd62ea1a	1919	HAL_DMA_Abort(hspi->hdmarx);
NYX	0:85b3fd62ea1a	1920	}
NYX	0:85b3fd62ea1a	1921
NYX	0:85b3fd62ea1a	1922	/* Disable the SPI DMA Tx & Rx requests */
NYX	0:85b3fd62ea1a	1923	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	1924	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	1925	return HAL_OK;
NYX	0:85b3fd62ea1a	1926	}
NYX	0:85b3fd62ea1a	1927
NYX	0:85b3fd62ea1a	1928	/**
NYX	0:85b3fd62ea1a	1929	* @brief Handle SPI interrupt request.
NYX	0:85b3fd62ea1a	1930	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	1931	* the configuration information for the specified SPI module.
NYX	0:85b3fd62ea1a	1932	* @retval None
NYX	0:85b3fd62ea1a	1933	*/
NYX	0:85b3fd62ea1a	1934	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	1935	{
NYX	0:85b3fd62ea1a	1936	uint32_t itsource = hspi->Instance->CR2;
NYX	0:85b3fd62ea1a	1937	uint32_t itflag = hspi->Instance->SR;
NYX	0:85b3fd62ea1a	1938
NYX	0:85b3fd62ea1a	1939	/* SPI in mode Receiver ----------------------------------------------------*/
NYX	0:85b3fd62ea1a	1940	if(((itflag & SPI_FLAG_OVR) == RESET) &&
NYX	0:85b3fd62ea1a	1941	((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
NYX	0:85b3fd62ea1a	1942	{
NYX	0:85b3fd62ea1a	1943	hspi->RxISR(hspi);
NYX	0:85b3fd62ea1a	1944	return;
NYX	0:85b3fd62ea1a	1945	}
NYX	0:85b3fd62ea1a	1946
NYX	0:85b3fd62ea1a	1947	/* SPI in mode Transmitter -------------------------------------------------*/
NYX	0:85b3fd62ea1a	1948	if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
NYX	0:85b3fd62ea1a	1949	{
NYX	0:85b3fd62ea1a	1950	hspi->TxISR(hspi);
NYX	0:85b3fd62ea1a	1951	return;
NYX	0:85b3fd62ea1a	1952	}
NYX	0:85b3fd62ea1a	1953
NYX	0:85b3fd62ea1a	1954	/* SPI in Error Treatment --------------------------------------------------*/
NYX	0:85b3fd62ea1a	1955	if(((itflag & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
NYX	0:85b3fd62ea1a	1956	{
NYX	0:85b3fd62ea1a	1957	/* SPI Overrun error interrupt occurred ----------------------------------*/
NYX	0:85b3fd62ea1a	1958	if((itflag & SPI_FLAG_OVR) != RESET)
NYX	0:85b3fd62ea1a	1959	{
NYX	0:85b3fd62ea1a	1960	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
NYX	0:85b3fd62ea1a	1961	{
NYX	0:85b3fd62ea1a	1962	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
NYX	0:85b3fd62ea1a	1963	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	1964	}
NYX	0:85b3fd62ea1a	1965	else
NYX	0:85b3fd62ea1a	1966	{
NYX	0:85b3fd62ea1a	1967	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	1968	return;
NYX	0:85b3fd62ea1a	1969	}
NYX	0:85b3fd62ea1a	1970	}
NYX	0:85b3fd62ea1a	1971
NYX	0:85b3fd62ea1a	1972	/* SPI Mode Fault error interrupt occurred -------------------------------*/
NYX	0:85b3fd62ea1a	1973	if((itflag & SPI_FLAG_MODF) != RESET)
NYX	0:85b3fd62ea1a	1974	{
NYX	0:85b3fd62ea1a	1975	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
NYX	0:85b3fd62ea1a	1976	__HAL_SPI_CLEAR_MODFFLAG(hspi);
NYX	0:85b3fd62ea1a	1977	}
NYX	0:85b3fd62ea1a	1978
NYX	0:85b3fd62ea1a	1979	/* SPI Frame error interrupt occurred ------------------------------------*/
NYX	0:85b3fd62ea1a	1980	if((itflag & SPI_FLAG_FRE) != RESET)
NYX	0:85b3fd62ea1a	1981	{
NYX	0:85b3fd62ea1a	1982	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
NYX	0:85b3fd62ea1a	1983	__HAL_SPI_CLEAR_FREFLAG(hspi);
NYX	0:85b3fd62ea1a	1984	}
NYX	0:85b3fd62ea1a	1985
NYX	0:85b3fd62ea1a	1986	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	1987	{
NYX	0:85b3fd62ea1a	1988	/* Disable all interrupts */
NYX	0:85b3fd62ea1a	1989	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
NYX	0:85b3fd62ea1a	1990
NYX	0:85b3fd62ea1a	1991	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	1992	/* Disable the SPI DMA requests if enabled */
NYX	0:85b3fd62ea1a	1993	if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))\|\|(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
NYX	0:85b3fd62ea1a	1994	{
NYX	0:85b3fd62ea1a	1995	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN));
NYX	0:85b3fd62ea1a	1996
NYX	0:85b3fd62ea1a	1997	/* Abort the SPI DMA Rx channel */
NYX	0:85b3fd62ea1a	1998	if(hspi->hdmarx != NULL)
NYX	0:85b3fd62ea1a	1999	{
NYX	0:85b3fd62ea1a	2000	/* Set the SPI DMA Abort callback :
NYX	0:85b3fd62ea1a	2001	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
NYX	0:85b3fd62ea1a	2002	hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
NYX	0:85b3fd62ea1a	2003	HAL_DMA_Abort_IT(hspi->hdmarx);
NYX	0:85b3fd62ea1a	2004	}
NYX	0:85b3fd62ea1a	2005	/* Abort the SPI DMA Tx channel */
NYX	0:85b3fd62ea1a	2006	if(hspi->hdmatx != NULL)
NYX	0:85b3fd62ea1a	2007	{
NYX	0:85b3fd62ea1a	2008	/* Set the SPI DMA Abort callback :
NYX	0:85b3fd62ea1a	2009	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
NYX	0:85b3fd62ea1a	2010	hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
NYX	0:85b3fd62ea1a	2011	HAL_DMA_Abort_IT(hspi->hdmatx);
NYX	0:85b3fd62ea1a	2012	}
NYX	0:85b3fd62ea1a	2013	}
NYX	0:85b3fd62ea1a	2014	else
NYX	0:85b3fd62ea1a	2015	{
NYX	0:85b3fd62ea1a	2016	/* Call user error callback */
NYX	0:85b3fd62ea1a	2017	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	2018	}
NYX	0:85b3fd62ea1a	2019	}
NYX	0:85b3fd62ea1a	2020	return;
NYX	0:85b3fd62ea1a	2021	}
NYX	0:85b3fd62ea1a	2022	}
NYX	0:85b3fd62ea1a	2023
NYX	0:85b3fd62ea1a	2024	/**
NYX	0:85b3fd62ea1a	2025	* @brief Tx Transfer completed callback.
NYX	0:85b3fd62ea1a	2026	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2027	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2028	* @retval None
NYX	0:85b3fd62ea1a	2029	*/
NYX	0:85b3fd62ea1a	2030	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2031	{
NYX	0:85b3fd62ea1a	2032	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	2033	UNUSED(hspi);
NYX	0:85b3fd62ea1a	2034	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	2035	the HAL_SPI_TxCpltCallback should be implemented in the user file
NYX	0:85b3fd62ea1a	2036	*/
NYX	0:85b3fd62ea1a	2037	}
NYX	0:85b3fd62ea1a	2038
NYX	0:85b3fd62ea1a	2039	/**
NYX	0:85b3fd62ea1a	2040	* @brief Rx Transfer completed callback.
NYX	0:85b3fd62ea1a	2041	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2042	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2043	* @retval None
NYX	0:85b3fd62ea1a	2044	*/
NYX	0:85b3fd62ea1a	2045	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2046	{
NYX	0:85b3fd62ea1a	2047	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	2048	UNUSED(hspi);
NYX	0:85b3fd62ea1a	2049	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	2050	the HAL_SPI_RxCpltCallback should be implemented in the user file
NYX	0:85b3fd62ea1a	2051	*/
NYX	0:85b3fd62ea1a	2052	}
NYX	0:85b3fd62ea1a	2053
NYX	0:85b3fd62ea1a	2054	/**
NYX	0:85b3fd62ea1a	2055	* @brief Tx and Rx Transfer completed callback.
NYX	0:85b3fd62ea1a	2056	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2057	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2058	* @retval None
NYX	0:85b3fd62ea1a	2059	*/
NYX	0:85b3fd62ea1a	2060	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2061	{
NYX	0:85b3fd62ea1a	2062	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	2063	UNUSED(hspi);
NYX	0:85b3fd62ea1a	2064	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	2065	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
NYX	0:85b3fd62ea1a	2066	*/
NYX	0:85b3fd62ea1a	2067	}
NYX	0:85b3fd62ea1a	2068
NYX	0:85b3fd62ea1a	2069	/**
NYX	0:85b3fd62ea1a	2070	* @brief Tx Half Transfer completed callback.
NYX	0:85b3fd62ea1a	2071	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2072	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2073	* @retval None
NYX	0:85b3fd62ea1a	2074	*/
NYX	0:85b3fd62ea1a	2075	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2076	{
NYX	0:85b3fd62ea1a	2077	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	2078	UNUSED(hspi);
NYX	0:85b3fd62ea1a	2079	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	2080	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
NYX	0:85b3fd62ea1a	2081	*/
NYX	0:85b3fd62ea1a	2082	}
NYX	0:85b3fd62ea1a	2083
NYX	0:85b3fd62ea1a	2084	/**
NYX	0:85b3fd62ea1a	2085	* @brief Rx Half Transfer completed callback.
NYX	0:85b3fd62ea1a	2086	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2087	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2088	* @retval None
NYX	0:85b3fd62ea1a	2089	*/
NYX	0:85b3fd62ea1a	2090	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2091	{
NYX	0:85b3fd62ea1a	2092	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	2093	UNUSED(hspi);
NYX	0:85b3fd62ea1a	2094	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	2095	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
NYX	0:85b3fd62ea1a	2096	*/
NYX	0:85b3fd62ea1a	2097	}
NYX	0:85b3fd62ea1a	2098
NYX	0:85b3fd62ea1a	2099	/**
NYX	0:85b3fd62ea1a	2100	* @brief Tx and Rx Half Transfer callback.
NYX	0:85b3fd62ea1a	2101	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2102	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2103	* @retval None
NYX	0:85b3fd62ea1a	2104	*/
NYX	0:85b3fd62ea1a	2105	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2106	{
NYX	0:85b3fd62ea1a	2107	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	2108	UNUSED(hspi);
NYX	0:85b3fd62ea1a	2109	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	2110	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
NYX	0:85b3fd62ea1a	2111	*/
NYX	0:85b3fd62ea1a	2112	}
NYX	0:85b3fd62ea1a	2113
NYX	0:85b3fd62ea1a	2114	/**
NYX	0:85b3fd62ea1a	2115	* @brief SPI error callback.
NYX	0:85b3fd62ea1a	2116	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2117	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2118	* @retval None
NYX	0:85b3fd62ea1a	2119	*/
NYX	0:85b3fd62ea1a	2120	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2121	{
NYX	0:85b3fd62ea1a	2122	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	2123	UNUSED(hspi);
NYX	0:85b3fd62ea1a	2124	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	2125	the HAL_SPI_ErrorCallback should be implemented in the user file
NYX	0:85b3fd62ea1a	2126	*/
NYX	0:85b3fd62ea1a	2127	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
NYX	0:85b3fd62ea1a	2128	and user can use HAL_SPI_GetError() API to check the latest error occurred
NYX	0:85b3fd62ea1a	2129	*/
NYX	0:85b3fd62ea1a	2130	}
NYX	0:85b3fd62ea1a	2131
NYX	0:85b3fd62ea1a	2132	/**
NYX	0:85b3fd62ea1a	2133	* @brief SPI Abort Complete callback.
NYX	0:85b3fd62ea1a	2134	* @param hspi SPI handle.
NYX	0:85b3fd62ea1a	2135	* @retval None
NYX	0:85b3fd62ea1a	2136	*/
NYX	0:85b3fd62ea1a	2137	__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2138	{
NYX	0:85b3fd62ea1a	2139	/* Prevent unused argument(s) compilation warning */
NYX	0:85b3fd62ea1a	2140	UNUSED(hspi);
NYX	0:85b3fd62ea1a	2141
NYX	0:85b3fd62ea1a	2142	/* NOTE : This function should not be modified, when the callback is needed,
NYX	0:85b3fd62ea1a	2143	the HAL_SPI_AbortCpltCallback can be implemented in the user file.
NYX	0:85b3fd62ea1a	2144	*/
NYX	0:85b3fd62ea1a	2145	}
NYX	0:85b3fd62ea1a	2146
NYX	0:85b3fd62ea1a	2147	/**
NYX	0:85b3fd62ea1a	2148	* @}
NYX	0:85b3fd62ea1a	2149	*/
NYX	0:85b3fd62ea1a	2150
NYX	0:85b3fd62ea1a	2151	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
NYX	0:85b3fd62ea1a	2152	* @brief SPI control functions
NYX	0:85b3fd62ea1a	2153	*
NYX	0:85b3fd62ea1a	2154	@verbatim
NYX	0:85b3fd62ea1a	2155	===============================================================================
NYX	0:85b3fd62ea1a	2156	##### Peripheral State and Errors functions #####
NYX	0:85b3fd62ea1a	2157	===============================================================================
NYX	0:85b3fd62ea1a	2158	[..]
NYX	0:85b3fd62ea1a	2159	This subsection provides a set of functions allowing to control the SPI.
NYX	0:85b3fd62ea1a	2160	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
NYX	0:85b3fd62ea1a	2161	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
NYX	0:85b3fd62ea1a	2162	@endverbatim
NYX	0:85b3fd62ea1a	2163	* @{
NYX	0:85b3fd62ea1a	2164	*/
NYX	0:85b3fd62ea1a	2165
NYX	0:85b3fd62ea1a	2166	/**
NYX	0:85b3fd62ea1a	2167	* @brief Return the SPI handle state.
NYX	0:85b3fd62ea1a	2168	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2169	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2170	* @retval SPI state
NYX	0:85b3fd62ea1a	2171	*/
NYX	0:85b3fd62ea1a	2172	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2173	{
NYX	0:85b3fd62ea1a	2174	/* Return SPI handle state */
NYX	0:85b3fd62ea1a	2175	return hspi->State;
NYX	0:85b3fd62ea1a	2176	}
NYX	0:85b3fd62ea1a	2177
NYX	0:85b3fd62ea1a	2178	/**
NYX	0:85b3fd62ea1a	2179	* @brief Return the SPI error code.
NYX	0:85b3fd62ea1a	2180	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2181	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2182	* @retval SPI error code in bitmap format
NYX	0:85b3fd62ea1a	2183	*/
NYX	0:85b3fd62ea1a	2184	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2185	{
NYX	0:85b3fd62ea1a	2186	/* Return SPI ErrorCode */
NYX	0:85b3fd62ea1a	2187	return hspi->ErrorCode;
NYX	0:85b3fd62ea1a	2188	}
NYX	0:85b3fd62ea1a	2189
NYX	0:85b3fd62ea1a	2190	/**
NYX	0:85b3fd62ea1a	2191	* @}
NYX	0:85b3fd62ea1a	2192	*/
NYX	0:85b3fd62ea1a	2193
NYX	0:85b3fd62ea1a	2194	/**
NYX	0:85b3fd62ea1a	2195	* @}
NYX	0:85b3fd62ea1a	2196	*/
NYX	0:85b3fd62ea1a	2197
NYX	0:85b3fd62ea1a	2198	/** @addtogroup SPI_Private_Functions
NYX	0:85b3fd62ea1a	2199	* @brief Private functions
NYX	0:85b3fd62ea1a	2200	* @{
NYX	0:85b3fd62ea1a	2201	*/
NYX	0:85b3fd62ea1a	2202
NYX	0:85b3fd62ea1a	2203	/**
NYX	0:85b3fd62ea1a	2204	* @brief DMA SPI transmit process complete callback.
NYX	0:85b3fd62ea1a	2205	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2206	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	2207	* @retval None
NYX	0:85b3fd62ea1a	2208	*/
NYX	0:85b3fd62ea1a	2209	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2210	{
NYX	0:85b3fd62ea1a	2211	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2212	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	2213
NYX	0:85b3fd62ea1a	2214	/* Init tickstart for timeout managment*/
NYX	0:85b3fd62ea1a	2215	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2216
NYX	0:85b3fd62ea1a	2217	/* DMA Normal Mode */
NYX	0:85b3fd62ea1a	2218	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
NYX	0:85b3fd62ea1a	2219	{
NYX	0:85b3fd62ea1a	2220	/* Disable Tx DMA Request */
NYX	0:85b3fd62ea1a	2221	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
NYX	0:85b3fd62ea1a	2222
NYX	0:85b3fd62ea1a	2223	/* Check the end of the transaction */
NYX	0:85b3fd62ea1a	2224	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	2225	{
NYX	0:85b3fd62ea1a	2226	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	2227	}
NYX	0:85b3fd62ea1a	2228
NYX	0:85b3fd62ea1a	2229	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
NYX	0:85b3fd62ea1a	2230	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
NYX	0:85b3fd62ea1a	2231	{
NYX	0:85b3fd62ea1a	2232	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	2233	}
NYX	0:85b3fd62ea1a	2234
NYX	0:85b3fd62ea1a	2235	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	2236	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	2237
NYX	0:85b3fd62ea1a	2238	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	2239	{
NYX	0:85b3fd62ea1a	2240	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	2241	return;
NYX	0:85b3fd62ea1a	2242	}
NYX	0:85b3fd62ea1a	2243	}
NYX	0:85b3fd62ea1a	2244	HAL_SPI_TxCpltCallback(hspi);
NYX	0:85b3fd62ea1a	2245	}
NYX	0:85b3fd62ea1a	2246
NYX	0:85b3fd62ea1a	2247	/**
NYX	0:85b3fd62ea1a	2248	* @brief DMA SPI receive process complete callback.
NYX	0:85b3fd62ea1a	2249	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2250	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	2251	* @retval None
NYX	0:85b3fd62ea1a	2252	*/
NYX	0:85b3fd62ea1a	2253	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2254	{
NYX	0:85b3fd62ea1a	2255	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2256	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2257	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	2258	__IO uint16_t tmpreg = 0U;
NYX	0:85b3fd62ea1a	2259
NYX	0:85b3fd62ea1a	2260	/* Init tickstart for timeout management*/
NYX	0:85b3fd62ea1a	2261	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2262	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2263
NYX	0:85b3fd62ea1a	2264	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
NYX	0:85b3fd62ea1a	2265	{
NYX	0:85b3fd62ea1a	2266	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2267	/* CRC handling */
NYX	0:85b3fd62ea1a	2268	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2269	{
NYX	0:85b3fd62ea1a	2270	/* Wait until RXNE flag */
NYX	0:85b3fd62ea1a	2271	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	2272	{
NYX	0:85b3fd62ea1a	2273	/* Error on the CRC reception */
NYX	0:85b3fd62ea1a	2274	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	2275	}
NYX	0:85b3fd62ea1a	2276	/* Read CRC */
NYX	0:85b3fd62ea1a	2277	tmpreg = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	2278	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	2279	UNUSED(tmpreg);
NYX	0:85b3fd62ea1a	2280	}
NYX	0:85b3fd62ea1a	2281	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2282
NYX	0:85b3fd62ea1a	2283	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
NYX	0:85b3fd62ea1a	2284	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	2285
NYX	0:85b3fd62ea1a	2286	/* Check the end of the transaction */
NYX	0:85b3fd62ea1a	2287	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
NYX	0:85b3fd62ea1a	2288	{
NYX	0:85b3fd62ea1a	2289	/* Disable SPI peripheral */
NYX	0:85b3fd62ea1a	2290	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	2291	}
NYX	0:85b3fd62ea1a	2292
NYX	0:85b3fd62ea1a	2293	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	2294	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	2295
NYX	0:85b3fd62ea1a	2296	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2297	/* Check if CRC error occurred */
NYX	0:85b3fd62ea1a	2298	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
NYX	0:85b3fd62ea1a	2299	{
NYX	0:85b3fd62ea1a	2300	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	2301	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
NYX	0:85b3fd62ea1a	2302	}
NYX	0:85b3fd62ea1a	2303	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2304
NYX	0:85b3fd62ea1a	2305	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	2306	{
NYX	0:85b3fd62ea1a	2307	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	2308	return;
NYX	0:85b3fd62ea1a	2309	}
NYX	0:85b3fd62ea1a	2310	}
NYX	0:85b3fd62ea1a	2311	HAL_SPI_RxCpltCallback(hspi);
NYX	0:85b3fd62ea1a	2312	}
NYX	0:85b3fd62ea1a	2313
NYX	0:85b3fd62ea1a	2314	/**
NYX	0:85b3fd62ea1a	2315	* @brief DMA SPI transmit receive process complete callback.
NYX	0:85b3fd62ea1a	2316	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2317	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	2318	* @retval None
NYX	0:85b3fd62ea1a	2319	*/
NYX	0:85b3fd62ea1a	2320	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2321	{
NYX	0:85b3fd62ea1a	2322	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2323	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	2324	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2325	__IO int16_t tmpreg = 0U;
NYX	0:85b3fd62ea1a	2326	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2327	/* Init tickstart for timeout management*/
NYX	0:85b3fd62ea1a	2328	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	2329
NYX	0:85b3fd62ea1a	2330	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
NYX	0:85b3fd62ea1a	2331	{
NYX	0:85b3fd62ea1a	2332	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2333	/* CRC handling */
NYX	0:85b3fd62ea1a	2334	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2335	{
NYX	0:85b3fd62ea1a	2336	/* Wait the CRC data */
NYX	0:85b3fd62ea1a	2337	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	2338	{
NYX	0:85b3fd62ea1a	2339	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	2340	}
NYX	0:85b3fd62ea1a	2341	/* Read CRC to Flush DR and RXNE flag */
NYX	0:85b3fd62ea1a	2342	tmpreg = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	2343	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	2344	UNUSED(tmpreg);
NYX	0:85b3fd62ea1a	2345	}
NYX	0:85b3fd62ea1a	2346	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2347	/* Check the end of the transaction */
NYX	0:85b3fd62ea1a	2348	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	2349	{
NYX	0:85b3fd62ea1a	2350	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	2351	}
NYX	0:85b3fd62ea1a	2352
NYX	0:85b3fd62ea1a	2353	/* Disable Rx/Tx DMA Request */
NYX	0:85b3fd62ea1a	2354	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	2355
NYX	0:85b3fd62ea1a	2356	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	2357	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	2358	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	2359
NYX	0:85b3fd62ea1a	2360	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2361	/* Check if CRC error occurred */
NYX	0:85b3fd62ea1a	2362	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
NYX	0:85b3fd62ea1a	2363	{
NYX	0:85b3fd62ea1a	2364	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	2365	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
NYX	0:85b3fd62ea1a	2366	}
NYX	0:85b3fd62ea1a	2367	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2368
NYX	0:85b3fd62ea1a	2369	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	2370	{
NYX	0:85b3fd62ea1a	2371	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	2372	return;
NYX	0:85b3fd62ea1a	2373	}
NYX	0:85b3fd62ea1a	2374	}
NYX	0:85b3fd62ea1a	2375	HAL_SPI_TxRxCpltCallback(hspi);
NYX	0:85b3fd62ea1a	2376	}
NYX	0:85b3fd62ea1a	2377
NYX	0:85b3fd62ea1a	2378	/**
NYX	0:85b3fd62ea1a	2379	* @brief DMA SPI half transmit process complete callback.
NYX	0:85b3fd62ea1a	2380	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2381	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	2382	* @retval None
NYX	0:85b3fd62ea1a	2383	*/
NYX	0:85b3fd62ea1a	2384	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2385	{
NYX	0:85b3fd62ea1a	2386	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2387
NYX	0:85b3fd62ea1a	2388	HAL_SPI_TxHalfCpltCallback(hspi);
NYX	0:85b3fd62ea1a	2389	}
NYX	0:85b3fd62ea1a	2390
NYX	0:85b3fd62ea1a	2391	/**
NYX	0:85b3fd62ea1a	2392	* @brief DMA SPI half receive process complete callback
NYX	0:85b3fd62ea1a	2393	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2394	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	2395	* @retval None
NYX	0:85b3fd62ea1a	2396	*/
NYX	0:85b3fd62ea1a	2397	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2398	{
NYX	0:85b3fd62ea1a	2399	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2400
NYX	0:85b3fd62ea1a	2401	HAL_SPI_RxHalfCpltCallback(hspi);
NYX	0:85b3fd62ea1a	2402	}
NYX	0:85b3fd62ea1a	2403
NYX	0:85b3fd62ea1a	2404	/**
NYX	0:85b3fd62ea1a	2405	* @brief DMA SPI half transmit receive process complete callback.
NYX	0:85b3fd62ea1a	2406	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2407	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	2408	* @retval None
NYX	0:85b3fd62ea1a	2409	*/
NYX	0:85b3fd62ea1a	2410	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2411	{
NYX	0:85b3fd62ea1a	2412	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2413
NYX	0:85b3fd62ea1a	2414	HAL_SPI_TxRxHalfCpltCallback(hspi);
NYX	0:85b3fd62ea1a	2415	}
NYX	0:85b3fd62ea1a	2416
NYX	0:85b3fd62ea1a	2417	/**
NYX	0:85b3fd62ea1a	2418	* @brief DMA SPI communication error callback.
NYX	0:85b3fd62ea1a	2419	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2420	* the configuration information for the specified DMA module.
NYX	0:85b3fd62ea1a	2421	* @retval None
NYX	0:85b3fd62ea1a	2422	*/
NYX	0:85b3fd62ea1a	2423	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2424	{
NYX	0:85b3fd62ea1a	2425	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2426
NYX	0:85b3fd62ea1a	2427	/* Stop the disable DMA transfer on SPI side */
NYX	0:85b3fd62ea1a	2428	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	2429
NYX	0:85b3fd62ea1a	2430	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
NYX	0:85b3fd62ea1a	2431	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	2432	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	2433	}
NYX	0:85b3fd62ea1a	2434
NYX	0:85b3fd62ea1a	2435	/**
NYX	0:85b3fd62ea1a	2436	* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
NYX	0:85b3fd62ea1a	2437	* (To be called at end of DMA Abort procedure following error occurrence).
NYX	0:85b3fd62ea1a	2438	* @param hdma DMA handle.
NYX	0:85b3fd62ea1a	2439	* @retval None
NYX	0:85b3fd62ea1a	2440	*/
NYX	0:85b3fd62ea1a	2441	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2442	{
NYX	0:85b3fd62ea1a	2443	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2444	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	2445	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	2446
NYX	0:85b3fd62ea1a	2447	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	2448	}
NYX	0:85b3fd62ea1a	2449
NYX	0:85b3fd62ea1a	2450	/**
NYX	0:85b3fd62ea1a	2451	* @brief DMA SPI Tx communication abort callback, when initiated by user
NYX	0:85b3fd62ea1a	2452	* (To be called at end of DMA Tx Abort procedure following user abort request).
NYX	0:85b3fd62ea1a	2453	* @note When this callback is executed, User Abort complete call back is called only if no
NYX	0:85b3fd62ea1a	2454	* Abort still ongoing for Rx DMA Handle.
NYX	0:85b3fd62ea1a	2455	* @param hdma DMA handle.
NYX	0:85b3fd62ea1a	2456	* @retval None
NYX	0:85b3fd62ea1a	2457	*/
NYX	0:85b3fd62ea1a	2458	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2459	{
NYX	0:85b3fd62ea1a	2460	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
NYX	0:85b3fd62ea1a	2461	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2462
NYX	0:85b3fd62ea1a	2463	hspi->hdmatx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	2464
NYX	0:85b3fd62ea1a	2465	/* Disable Tx DMA Request */
NYX	0:85b3fd62ea1a	2466	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );
NYX	0:85b3fd62ea1a	2467
NYX	0:85b3fd62ea1a	2468	/* Wait until TXE flag is set */
NYX	0:85b3fd62ea1a	2469	do
NYX	0:85b3fd62ea1a	2470	{
NYX	0:85b3fd62ea1a	2471	if(count-- == 0U)
NYX	0:85b3fd62ea1a	2472	{
NYX	0:85b3fd62ea1a	2473	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	2474	break;
NYX	0:85b3fd62ea1a	2475	}
NYX	0:85b3fd62ea1a	2476	}
NYX	0:85b3fd62ea1a	2477	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
NYX	0:85b3fd62ea1a	2478
NYX	0:85b3fd62ea1a	2479	/* Check if an Abort process is still ongoing */
NYX	0:85b3fd62ea1a	2480	if(hspi->hdmarx != NULL)
NYX	0:85b3fd62ea1a	2481	{
NYX	0:85b3fd62ea1a	2482	if(hspi->hdmarx->XferAbortCallback != NULL)
NYX	0:85b3fd62ea1a	2483	{
NYX	0:85b3fd62ea1a	2484	return;
NYX	0:85b3fd62ea1a	2485	}
NYX	0:85b3fd62ea1a	2486	}
NYX	0:85b3fd62ea1a	2487
NYX	0:85b3fd62ea1a	2488	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
NYX	0:85b3fd62ea1a	2489	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	2490	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	2491
NYX	0:85b3fd62ea1a	2492	/* Reset errorCode */
NYX	0:85b3fd62ea1a	2493	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	2494
NYX	0:85b3fd62ea1a	2495	/* Clear the Error flags in the SR register */
NYX	0:85b3fd62ea1a	2496	__HAL_SPI_CLEAR_FREFLAG(hspi);
NYX	0:85b3fd62ea1a	2497
NYX	0:85b3fd62ea1a	2498	/* Restore hspi->State to Ready */
NYX	0:85b3fd62ea1a	2499	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	2500
NYX	0:85b3fd62ea1a	2501	/* Call user Abort complete callback */
NYX	0:85b3fd62ea1a	2502	HAL_SPI_AbortCpltCallback(hspi);
NYX	0:85b3fd62ea1a	2503	}
NYX	0:85b3fd62ea1a	2504
NYX	0:85b3fd62ea1a	2505	/**
NYX	0:85b3fd62ea1a	2506	* @brief DMA SPI Rx communication abort callback, when initiated by user
NYX	0:85b3fd62ea1a	2507	* (To be called at end of DMA Rx Abort procedure following user abort request).
NYX	0:85b3fd62ea1a	2508	* @note When this callback is executed, User Abort complete call back is called only if no
NYX	0:85b3fd62ea1a	2509	* Abort still ongoing for Tx DMA Handle.
NYX	0:85b3fd62ea1a	2510	* @param hdma DMA handle.
NYX	0:85b3fd62ea1a	2511	* @retval None
NYX	0:85b3fd62ea1a	2512	*/
NYX	0:85b3fd62ea1a	2513	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
NYX	0:85b3fd62ea1a	2514	{
NYX	0:85b3fd62ea1a	2515	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
NYX	0:85b3fd62ea1a	2516
NYX	0:85b3fd62ea1a	2517	/* Disable SPI Peripheral */
NYX	0:85b3fd62ea1a	2518	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	2519
NYX	0:85b3fd62ea1a	2520	hspi->hdmarx->XferAbortCallback = NULL;
NYX	0:85b3fd62ea1a	2521
NYX	0:85b3fd62ea1a	2522	/* Disable Rx DMA Request */
NYX	0:85b3fd62ea1a	2523	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
NYX	0:85b3fd62ea1a	2524
NYX	0:85b3fd62ea1a	2525	/* Check if an Abort process is still ongoing */
NYX	0:85b3fd62ea1a	2526	if(hspi->hdmatx != NULL)
NYX	0:85b3fd62ea1a	2527	{
NYX	0:85b3fd62ea1a	2528	if(hspi->hdmatx->XferAbortCallback != NULL)
NYX	0:85b3fd62ea1a	2529	{
NYX	0:85b3fd62ea1a	2530	return;
NYX	0:85b3fd62ea1a	2531	}
NYX	0:85b3fd62ea1a	2532	}
NYX	0:85b3fd62ea1a	2533
NYX	0:85b3fd62ea1a	2534	/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
NYX	0:85b3fd62ea1a	2535	hspi->RxXferCount = 0U;
NYX	0:85b3fd62ea1a	2536	hspi->TxXferCount = 0U;
NYX	0:85b3fd62ea1a	2537
NYX	0:85b3fd62ea1a	2538	/* Reset errorCode */
NYX	0:85b3fd62ea1a	2539	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
NYX	0:85b3fd62ea1a	2540
NYX	0:85b3fd62ea1a	2541	/* Clear the Error flags in the SR register */
NYX	0:85b3fd62ea1a	2542	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	2543	__HAL_SPI_CLEAR_FREFLAG(hspi);
NYX	0:85b3fd62ea1a	2544
NYX	0:85b3fd62ea1a	2545	/* Restore hspi->State to Ready */
NYX	0:85b3fd62ea1a	2546	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	2547
NYX	0:85b3fd62ea1a	2548	/* Call user Abort complete callback */
NYX	0:85b3fd62ea1a	2549	HAL_SPI_AbortCpltCallback(hspi);
NYX	0:85b3fd62ea1a	2550	}
NYX	0:85b3fd62ea1a	2551
NYX	0:85b3fd62ea1a	2552	/**
NYX	0:85b3fd62ea1a	2553	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
NYX	0:85b3fd62ea1a	2554	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2555	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2556	* @retval None
NYX	0:85b3fd62ea1a	2557	*/
NYX	0:85b3fd62ea1a	2558	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2559	{
NYX	0:85b3fd62ea1a	2560	/* Receive data in 8bit mode */
NYX	0:85b3fd62ea1a	2561	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
NYX	0:85b3fd62ea1a	2562	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	2563
NYX	0:85b3fd62ea1a	2564	/* check end of the reception */
NYX	0:85b3fd62ea1a	2565	if(hspi->RxXferCount == 0U)
NYX	0:85b3fd62ea1a	2566	{
NYX	0:85b3fd62ea1a	2567	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2568	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2569	{
NYX	0:85b3fd62ea1a	2570	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
NYX	0:85b3fd62ea1a	2571	return;
NYX	0:85b3fd62ea1a	2572	}
NYX	0:85b3fd62ea1a	2573	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2574
NYX	0:85b3fd62ea1a	2575	/* Disable RXNE interrupt */
NYX	0:85b3fd62ea1a	2576	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	2577
NYX	0:85b3fd62ea1a	2578	if(hspi->TxXferCount == 0U)
NYX	0:85b3fd62ea1a	2579	{
NYX	0:85b3fd62ea1a	2580	SPI_CloseRxTx_ISR(hspi);
NYX	0:85b3fd62ea1a	2581	}
NYX	0:85b3fd62ea1a	2582	}
NYX	0:85b3fd62ea1a	2583	}
NYX	0:85b3fd62ea1a	2584
NYX	0:85b3fd62ea1a	2585	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2586	/**
NYX	0:85b3fd62ea1a	2587	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
NYX	0:85b3fd62ea1a	2588	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2589	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2590	* @retval None
NYX	0:85b3fd62ea1a	2591	*/
NYX	0:85b3fd62ea1a	2592	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2593	{
NYX	0:85b3fd62ea1a	2594	__IO uint8_t tmpreg = 0U;
NYX	0:85b3fd62ea1a	2595
NYX	0:85b3fd62ea1a	2596	/* Read data register to flush CRC */
NYX	0:85b3fd62ea1a	2597	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
NYX	0:85b3fd62ea1a	2598
NYX	0:85b3fd62ea1a	2599	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	2600
NYX	0:85b3fd62ea1a	2601	UNUSED(tmpreg);
NYX	0:85b3fd62ea1a	2602
NYX	0:85b3fd62ea1a	2603	/* Disable RXNE interrupt */
NYX	0:85b3fd62ea1a	2604	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	2605
NYX	0:85b3fd62ea1a	2606	if(hspi->TxXferCount == 0U)
NYX	0:85b3fd62ea1a	2607	{
NYX	0:85b3fd62ea1a	2608	SPI_CloseRxTx_ISR(hspi);
NYX	0:85b3fd62ea1a	2609	}
NYX	0:85b3fd62ea1a	2610	}
NYX	0:85b3fd62ea1a	2611	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2612
NYX	0:85b3fd62ea1a	2613	/**
NYX	0:85b3fd62ea1a	2614	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
NYX	0:85b3fd62ea1a	2615	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2616	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2617	* @retval None
NYX	0:85b3fd62ea1a	2618	*/
NYX	0:85b3fd62ea1a	2619	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2620	{
NYX	0:85b3fd62ea1a	2621	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
NYX	0:85b3fd62ea1a	2622	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	2623
NYX	0:85b3fd62ea1a	2624	/* check the end of the transmission */
NYX	0:85b3fd62ea1a	2625	if(hspi->TxXferCount == 0U)
NYX	0:85b3fd62ea1a	2626	{
NYX	0:85b3fd62ea1a	2627	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2628	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2629	{
NYX	0:85b3fd62ea1a	2630	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	2631	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
NYX	0:85b3fd62ea1a	2632	return;
NYX	0:85b3fd62ea1a	2633	}
NYX	0:85b3fd62ea1a	2634	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2635
NYX	0:85b3fd62ea1a	2636	/* Disable TXE interrupt */
NYX	0:85b3fd62ea1a	2637	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
NYX	0:85b3fd62ea1a	2638
NYX	0:85b3fd62ea1a	2639	if(hspi->RxXferCount == 0U)
NYX	0:85b3fd62ea1a	2640	{
NYX	0:85b3fd62ea1a	2641	SPI_CloseRxTx_ISR(hspi);
NYX	0:85b3fd62ea1a	2642	}
NYX	0:85b3fd62ea1a	2643	}
NYX	0:85b3fd62ea1a	2644	}
NYX	0:85b3fd62ea1a	2645
NYX	0:85b3fd62ea1a	2646	/**
NYX	0:85b3fd62ea1a	2647	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
NYX	0:85b3fd62ea1a	2648	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2649	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2650	* @retval None
NYX	0:85b3fd62ea1a	2651	*/
NYX	0:85b3fd62ea1a	2652	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2653	{
NYX	0:85b3fd62ea1a	2654	/* Receive data in 16 Bit mode */
NYX	0:85b3fd62ea1a	2655	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	2656	hspi->pRxBuffPtr += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	2657	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	2658
NYX	0:85b3fd62ea1a	2659	if(hspi->RxXferCount == 0U)
NYX	0:85b3fd62ea1a	2660	{
NYX	0:85b3fd62ea1a	2661	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2662	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2663	{
NYX	0:85b3fd62ea1a	2664	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
NYX	0:85b3fd62ea1a	2665	return;
NYX	0:85b3fd62ea1a	2666	}
NYX	0:85b3fd62ea1a	2667	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2668
NYX	0:85b3fd62ea1a	2669	/* Disable RXNE interrupt */
NYX	0:85b3fd62ea1a	2670	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
NYX	0:85b3fd62ea1a	2671
NYX	0:85b3fd62ea1a	2672	if(hspi->TxXferCount == 0U)
NYX	0:85b3fd62ea1a	2673	{
NYX	0:85b3fd62ea1a	2674	SPI_CloseRxTx_ISR(hspi);
NYX	0:85b3fd62ea1a	2675	}
NYX	0:85b3fd62ea1a	2676	}
NYX	0:85b3fd62ea1a	2677	}
NYX	0:85b3fd62ea1a	2678
NYX	0:85b3fd62ea1a	2679	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2680	/**
NYX	0:85b3fd62ea1a	2681	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
NYX	0:85b3fd62ea1a	2682	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2683	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2684	* @retval None
NYX	0:85b3fd62ea1a	2685	*/
NYX	0:85b3fd62ea1a	2686	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2687	{
NYX	0:85b3fd62ea1a	2688	/* Receive data in 16 Bit mode */
NYX	0:85b3fd62ea1a	2689	__IO uint16_t tmpreg = 0U;
NYX	0:85b3fd62ea1a	2690
NYX	0:85b3fd62ea1a	2691	/* Read data register to flush CRC */
NYX	0:85b3fd62ea1a	2692	tmpreg = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	2693
NYX	0:85b3fd62ea1a	2694	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	2695	UNUSED(tmpreg);
NYX	0:85b3fd62ea1a	2696
NYX	0:85b3fd62ea1a	2697	/* Disable RXNE interrupt */
NYX	0:85b3fd62ea1a	2698	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
NYX	0:85b3fd62ea1a	2699
NYX	0:85b3fd62ea1a	2700	SPI_CloseRxTx_ISR(hspi);
NYX	0:85b3fd62ea1a	2701	}
NYX	0:85b3fd62ea1a	2702	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2703
NYX	0:85b3fd62ea1a	2704	/**
NYX	0:85b3fd62ea1a	2705	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
NYX	0:85b3fd62ea1a	2706	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2707	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2708	* @retval None
NYX	0:85b3fd62ea1a	2709	*/
NYX	0:85b3fd62ea1a	2710	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2711	{
NYX	0:85b3fd62ea1a	2712	/* Transmit data in 16 Bit mode */
NYX	0:85b3fd62ea1a	2713	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
NYX	0:85b3fd62ea1a	2714	hspi->pTxBuffPtr += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	2715	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	2716
NYX	0:85b3fd62ea1a	2717	/* Enable CRC Transmission */
NYX	0:85b3fd62ea1a	2718	if(hspi->TxXferCount == 0U)
NYX	0:85b3fd62ea1a	2719	{
NYX	0:85b3fd62ea1a	2720	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2721	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2722	{
NYX	0:85b3fd62ea1a	2723	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	2724	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
NYX	0:85b3fd62ea1a	2725	return;
NYX	0:85b3fd62ea1a	2726	}
NYX	0:85b3fd62ea1a	2727	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2728
NYX	0:85b3fd62ea1a	2729	/* Disable TXE interrupt */
NYX	0:85b3fd62ea1a	2730	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
NYX	0:85b3fd62ea1a	2731
NYX	0:85b3fd62ea1a	2732	if(hspi->RxXferCount == 0U)
NYX	0:85b3fd62ea1a	2733	{
NYX	0:85b3fd62ea1a	2734	SPI_CloseRxTx_ISR(hspi);
NYX	0:85b3fd62ea1a	2735	}
NYX	0:85b3fd62ea1a	2736	}
NYX	0:85b3fd62ea1a	2737	}
NYX	0:85b3fd62ea1a	2738
NYX	0:85b3fd62ea1a	2739	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2740	/**
NYX	0:85b3fd62ea1a	2741	* @brief Manage the CRC 8-bit receive in Interrupt context.
NYX	0:85b3fd62ea1a	2742	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2743	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2744	* @retval None
NYX	0:85b3fd62ea1a	2745	*/
NYX	0:85b3fd62ea1a	2746	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2747	{
NYX	0:85b3fd62ea1a	2748	__IO uint8_t tmpreg = 0U;
NYX	0:85b3fd62ea1a	2749
NYX	0:85b3fd62ea1a	2750	/* Read data register to flush CRC */
NYX	0:85b3fd62ea1a	2751	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
NYX	0:85b3fd62ea1a	2752
NYX	0:85b3fd62ea1a	2753	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	2754	UNUSED(tmpreg);
NYX	0:85b3fd62ea1a	2755
NYX	0:85b3fd62ea1a	2756	SPI_CloseRx_ISR(hspi);
NYX	0:85b3fd62ea1a	2757	}
NYX	0:85b3fd62ea1a	2758	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2759
NYX	0:85b3fd62ea1a	2760	/**
NYX	0:85b3fd62ea1a	2761	* @brief Manage the receive 8-bit in Interrupt context.
NYX	0:85b3fd62ea1a	2762	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2763	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2764	* @retval None
NYX	0:85b3fd62ea1a	2765	*/
NYX	0:85b3fd62ea1a	2766	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2767	{
NYX	0:85b3fd62ea1a	2768	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
NYX	0:85b3fd62ea1a	2769	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	2770
NYX	0:85b3fd62ea1a	2771	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2772	/* Enable CRC Transmission */
NYX	0:85b3fd62ea1a	2773	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
NYX	0:85b3fd62ea1a	2774	{
NYX	0:85b3fd62ea1a	2775	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	2776	}
NYX	0:85b3fd62ea1a	2777	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2778
NYX	0:85b3fd62ea1a	2779	if(hspi->RxXferCount == 0U)
NYX	0:85b3fd62ea1a	2780	{
NYX	0:85b3fd62ea1a	2781	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2782	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2783	{
NYX	0:85b3fd62ea1a	2784	hspi->RxISR = SPI_RxISR_8BITCRC;
NYX	0:85b3fd62ea1a	2785	return;
NYX	0:85b3fd62ea1a	2786	}
NYX	0:85b3fd62ea1a	2787	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2788	SPI_CloseRx_ISR(hspi);
NYX	0:85b3fd62ea1a	2789	}
NYX	0:85b3fd62ea1a	2790	}
NYX	0:85b3fd62ea1a	2791
NYX	0:85b3fd62ea1a	2792	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2793	/**
NYX	0:85b3fd62ea1a	2794	* @brief Manage the CRC 16-bit receive in Interrupt context.
NYX	0:85b3fd62ea1a	2795	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2796	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2797	* @retval None
NYX	0:85b3fd62ea1a	2798	*/
NYX	0:85b3fd62ea1a	2799	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2800	{
NYX	0:85b3fd62ea1a	2801	__IO uint16_t tmpreg = 0U;
NYX	0:85b3fd62ea1a	2802
NYX	0:85b3fd62ea1a	2803	/* Read data register to flush CRC */
NYX	0:85b3fd62ea1a	2804	tmpreg = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	2805
NYX	0:85b3fd62ea1a	2806	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	2807	UNUSED(tmpreg);
NYX	0:85b3fd62ea1a	2808
NYX	0:85b3fd62ea1a	2809	/* Disable RXNE and ERR interrupt */
NYX	0:85b3fd62ea1a	2810	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	2811
NYX	0:85b3fd62ea1a	2812	SPI_CloseRx_ISR(hspi);
NYX	0:85b3fd62ea1a	2813	}
NYX	0:85b3fd62ea1a	2814	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2815
NYX	0:85b3fd62ea1a	2816	/**
NYX	0:85b3fd62ea1a	2817	* @brief Manage the 16-bit receive in Interrupt context.
NYX	0:85b3fd62ea1a	2818	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2819	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2820	* @retval None
NYX	0:85b3fd62ea1a	2821	*/
NYX	0:85b3fd62ea1a	2822	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2823	{
NYX	0:85b3fd62ea1a	2824	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
NYX	0:85b3fd62ea1a	2825	hspi->pRxBuffPtr += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	2826	hspi->RxXferCount--;
NYX	0:85b3fd62ea1a	2827
NYX	0:85b3fd62ea1a	2828	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2829	/* Enable CRC Transmission */
NYX	0:85b3fd62ea1a	2830	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
NYX	0:85b3fd62ea1a	2831	{
NYX	0:85b3fd62ea1a	2832	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	2833	}
NYX	0:85b3fd62ea1a	2834	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2835
NYX	0:85b3fd62ea1a	2836	if(hspi->RxXferCount == 0U)
NYX	0:85b3fd62ea1a	2837	{
NYX	0:85b3fd62ea1a	2838	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2839	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2840	{
NYX	0:85b3fd62ea1a	2841	hspi->RxISR = SPI_RxISR_16BITCRC;
NYX	0:85b3fd62ea1a	2842	return;
NYX	0:85b3fd62ea1a	2843	}
NYX	0:85b3fd62ea1a	2844	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2845	SPI_CloseRx_ISR(hspi);
NYX	0:85b3fd62ea1a	2846	}
NYX	0:85b3fd62ea1a	2847	}
NYX	0:85b3fd62ea1a	2848
NYX	0:85b3fd62ea1a	2849	/**
NYX	0:85b3fd62ea1a	2850	* @brief Handle the data 8-bit transmit in Interrupt mode.
NYX	0:85b3fd62ea1a	2851	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2852	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2853	* @retval None
NYX	0:85b3fd62ea1a	2854	*/
NYX	0:85b3fd62ea1a	2855	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2856	{
NYX	0:85b3fd62ea1a	2857	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
NYX	0:85b3fd62ea1a	2858	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	2859
NYX	0:85b3fd62ea1a	2860	if(hspi->TxXferCount == 0U)
NYX	0:85b3fd62ea1a	2861	{
NYX	0:85b3fd62ea1a	2862	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2863	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2864	{
NYX	0:85b3fd62ea1a	2865	/* Enable CRC Transmission */
NYX	0:85b3fd62ea1a	2866	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	2867	}
NYX	0:85b3fd62ea1a	2868	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2869	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
NYX	0:85b3fd62ea1a	2870	SPI_CloseTx_ISR(hspi);
NYX	0:85b3fd62ea1a	2871	}
NYX	0:85b3fd62ea1a	2872	}
NYX	0:85b3fd62ea1a	2873
NYX	0:85b3fd62ea1a	2874	/**
NYX	0:85b3fd62ea1a	2875	* @brief Handle the data 16-bit transmit in Interrupt mode.
NYX	0:85b3fd62ea1a	2876	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2877	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2878	* @retval None
NYX	0:85b3fd62ea1a	2879	*/
NYX	0:85b3fd62ea1a	2880	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	2881	{
NYX	0:85b3fd62ea1a	2882	/* Transmit data in 16 Bit mode */
NYX	0:85b3fd62ea1a	2883	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
NYX	0:85b3fd62ea1a	2884	hspi->pTxBuffPtr += sizeof(uint16_t);
NYX	0:85b3fd62ea1a	2885	hspi->TxXferCount--;
NYX	0:85b3fd62ea1a	2886
NYX	0:85b3fd62ea1a	2887	if(hspi->TxXferCount == 0U)
NYX	0:85b3fd62ea1a	2888	{
NYX	0:85b3fd62ea1a	2889	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	2890	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2891	{
NYX	0:85b3fd62ea1a	2892	/* Enable CRC Transmission */
NYX	0:85b3fd62ea1a	2893	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
NYX	0:85b3fd62ea1a	2894	}
NYX	0:85b3fd62ea1a	2895	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	2896	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
NYX	0:85b3fd62ea1a	2897	SPI_CloseTx_ISR(hspi);
NYX	0:85b3fd62ea1a	2898	}
NYX	0:85b3fd62ea1a	2899	}
NYX	0:85b3fd62ea1a	2900
NYX	0:85b3fd62ea1a	2901	/**
NYX	0:85b3fd62ea1a	2902	* @brief Handle SPI Communication Timeout.
NYX	0:85b3fd62ea1a	2903	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2904	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2905	* @param Flag: SPI flag to check
NYX	0:85b3fd62ea1a	2906	* @param State: flag state to check
NYX	0:85b3fd62ea1a	2907	* @param Timeout: Timeout duration
NYX	0:85b3fd62ea1a	2908	* @param Tickstart: tick start value
NYX	0:85b3fd62ea1a	2909	* @retval HAL status
NYX	0:85b3fd62ea1a	2910	*/
NYX	0:85b3fd62ea1a	2911	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
NYX	0:85b3fd62ea1a	2912	{
NYX	0:85b3fd62ea1a	2913	while((hspi->Instance->SR & Flag) != State)
NYX	0:85b3fd62ea1a	2914	{
NYX	0:85b3fd62ea1a	2915	if(Timeout != HAL_MAX_DELAY)
NYX	0:85b3fd62ea1a	2916	{
NYX	0:85b3fd62ea1a	2917	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) >= Timeout))
NYX	0:85b3fd62ea1a	2918	{
NYX	0:85b3fd62ea1a	2919	/* Disable the SPI and reset the CRC: the CRC value should be cleared
NYX	0:85b3fd62ea1a	2920	on both master and slave sides in order to resynchronize the master
NYX	0:85b3fd62ea1a	2921	and slave for their respective CRC calculation */
NYX	0:85b3fd62ea1a	2922
NYX	0:85b3fd62ea1a	2923	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
NYX	0:85b3fd62ea1a	2924	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	2925
NYX	0:85b3fd62ea1a	2926	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
NYX	0:85b3fd62ea1a	2927	{
NYX	0:85b3fd62ea1a	2928	/* Disable SPI peripheral */
NYX	0:85b3fd62ea1a	2929	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	2930	}
NYX	0:85b3fd62ea1a	2931
NYX	0:85b3fd62ea1a	2932	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	2933	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2934	{
NYX	0:85b3fd62ea1a	2935	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	2936	}
NYX	0:85b3fd62ea1a	2937
NYX	0:85b3fd62ea1a	2938	hspi->State= HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	2939
NYX	0:85b3fd62ea1a	2940	/* Process Unlocked */
NYX	0:85b3fd62ea1a	2941	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	2942
NYX	0:85b3fd62ea1a	2943	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2944	}
NYX	0:85b3fd62ea1a	2945	}
NYX	0:85b3fd62ea1a	2946	}
NYX	0:85b3fd62ea1a	2947
NYX	0:85b3fd62ea1a	2948	return HAL_OK;
NYX	0:85b3fd62ea1a	2949	}
NYX	0:85b3fd62ea1a	2950
NYX	0:85b3fd62ea1a	2951	/**
NYX	0:85b3fd62ea1a	2952	* @brief Handle SPI Communication Timeout.
NYX	0:85b3fd62ea1a	2953	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	2954	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	2955	* @param Flag: SPI TXE flag to check
NYX	0:85b3fd62ea1a	2956	* @param State: flag state to check
NYX	0:85b3fd62ea1a	2957	* @param Timeout: Timeout duration
NYX	0:85b3fd62ea1a	2958	* @param Tickstart: tick start value
NYX	0:85b3fd62ea1a	2959	* @retval HAL status
NYX	0:85b3fd62ea1a	2960	*/
NYX	0:85b3fd62ea1a	2961	static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
NYX	0:85b3fd62ea1a	2962	{
NYX	0:85b3fd62ea1a	2963	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET)
NYX	0:85b3fd62ea1a	2964	{
NYX	0:85b3fd62ea1a	2965	if(Timeout != HAL_MAX_DELAY)
NYX	0:85b3fd62ea1a	2966	{
NYX	0:85b3fd62ea1a	2967	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) >= Timeout))
NYX	0:85b3fd62ea1a	2968	{
NYX	0:85b3fd62ea1a	2969	/* Disable the SPI and reset the CRC: the CRC value should be cleared
NYX	0:85b3fd62ea1a	2970	on both master and slave sides in order to resynchronize the master
NYX	0:85b3fd62ea1a	2971	and slave for their respective CRC calculation */
NYX	0:85b3fd62ea1a	2972
NYX	0:85b3fd62ea1a	2973	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
NYX	0:85b3fd62ea1a	2974	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	2975
NYX	0:85b3fd62ea1a	2976	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
NYX	0:85b3fd62ea1a	2977	{
NYX	0:85b3fd62ea1a	2978	/* Disable SPI peripheral */
NYX	0:85b3fd62ea1a	2979	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	2980	}
NYX	0:85b3fd62ea1a	2981
NYX	0:85b3fd62ea1a	2982	/* Reset CRC Calculation */
NYX	0:85b3fd62ea1a	2983	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
NYX	0:85b3fd62ea1a	2984	{
NYX	0:85b3fd62ea1a	2985	SPI_RESET_CRC(hspi);
NYX	0:85b3fd62ea1a	2986	}
NYX	0:85b3fd62ea1a	2987
NYX	0:85b3fd62ea1a	2988	hspi->State= HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	2989
NYX	0:85b3fd62ea1a	2990	/* Process Unlocked */
NYX	0:85b3fd62ea1a	2991	__HAL_UNLOCK(hspi);
NYX	0:85b3fd62ea1a	2992
NYX	0:85b3fd62ea1a	2993	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	2994	}
NYX	0:85b3fd62ea1a	2995	}
NYX	0:85b3fd62ea1a	2996	}
NYX	0:85b3fd62ea1a	2997
NYX	0:85b3fd62ea1a	2998	return HAL_OK;
NYX	0:85b3fd62ea1a	2999	}
NYX	0:85b3fd62ea1a	3000
NYX	0:85b3fd62ea1a	3001	/**
NYX	0:85b3fd62ea1a	3002	* @brief Handle to check BSY flag before start a new transaction.
NYX	0:85b3fd62ea1a	3003	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	3004	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	3005	* @param Timeout: Timeout duration
NYX	0:85b3fd62ea1a	3006	* @param Tickstart: tick start value
NYX	0:85b3fd62ea1a	3007	* @retval HAL status
NYX	0:85b3fd62ea1a	3008	*/
NYX	0:85b3fd62ea1a	3009	static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
NYX	0:85b3fd62ea1a	3010	{
NYX	0:85b3fd62ea1a	3011	/* Control the BSY flag */
NYX	0:85b3fd62ea1a	3012	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	3013	{
NYX	0:85b3fd62ea1a	3014	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	3015	return HAL_TIMEOUT;
NYX	0:85b3fd62ea1a	3016	}
NYX	0:85b3fd62ea1a	3017	return HAL_OK;
NYX	0:85b3fd62ea1a	3018	}
NYX	0:85b3fd62ea1a	3019
NYX	0:85b3fd62ea1a	3020	/**
NYX	0:85b3fd62ea1a	3021	* @brief Handle the end of the RXTX transaction.
NYX	0:85b3fd62ea1a	3022	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	3023	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	3024	* @retval None
NYX	0:85b3fd62ea1a	3025	*/
NYX	0:85b3fd62ea1a	3026	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	3027	{
NYX	0:85b3fd62ea1a	3028	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	3029	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
NYX	0:85b3fd62ea1a	3030	/* Init tickstart for timeout managment*/
NYX	0:85b3fd62ea1a	3031	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3032
NYX	0:85b3fd62ea1a	3033	/* Disable ERR interrupt */
NYX	0:85b3fd62ea1a	3034	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
NYX	0:85b3fd62ea1a	3035
NYX	0:85b3fd62ea1a	3036	/* Wait until TXE flag is set */
NYX	0:85b3fd62ea1a	3037	do
NYX	0:85b3fd62ea1a	3038	{
NYX	0:85b3fd62ea1a	3039	if(count-- == 0U)
NYX	0:85b3fd62ea1a	3040	{
NYX	0:85b3fd62ea1a	3041	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	3042	break;
NYX	0:85b3fd62ea1a	3043	}
NYX	0:85b3fd62ea1a	3044	}
NYX	0:85b3fd62ea1a	3045	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
NYX	0:85b3fd62ea1a	3046
NYX	0:85b3fd62ea1a	3047	/* Check the end of the transaction */
NYX	0:85b3fd62ea1a	3048	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
NYX	0:85b3fd62ea1a	3049	{
NYX	0:85b3fd62ea1a	3050	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	3051	}
NYX	0:85b3fd62ea1a	3052
NYX	0:85b3fd62ea1a	3053	/* Clear overrun flag in 2 Lines communication mode because received is not read */
NYX	0:85b3fd62ea1a	3054	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
NYX	0:85b3fd62ea1a	3055	{
NYX	0:85b3fd62ea1a	3056	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	3057	}
NYX	0:85b3fd62ea1a	3058
NYX	0:85b3fd62ea1a	3059	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	3060	/* Check if CRC error occurred */
NYX	0:85b3fd62ea1a	3061	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
NYX	0:85b3fd62ea1a	3062	{
NYX	0:85b3fd62ea1a	3063	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	3064	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	3065	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
NYX	0:85b3fd62ea1a	3066	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	3067	}
NYX	0:85b3fd62ea1a	3068	else
NYX	0:85b3fd62ea1a	3069	{
NYX	0:85b3fd62ea1a	3070	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	3071	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	3072	{
NYX	0:85b3fd62ea1a	3073	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
NYX	0:85b3fd62ea1a	3074	{
NYX	0:85b3fd62ea1a	3075	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	3076	HAL_SPI_RxCpltCallback(hspi);
NYX	0:85b3fd62ea1a	3077	}
NYX	0:85b3fd62ea1a	3078	else
NYX	0:85b3fd62ea1a	3079	{
NYX	0:85b3fd62ea1a	3080	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	3081	HAL_SPI_TxRxCpltCallback(hspi);
NYX	0:85b3fd62ea1a	3082	}
NYX	0:85b3fd62ea1a	3083	}
NYX	0:85b3fd62ea1a	3084	else
NYX	0:85b3fd62ea1a	3085	{
NYX	0:85b3fd62ea1a	3086	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	3087	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	3088	}
NYX	0:85b3fd62ea1a	3089	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	3090	}
NYX	0:85b3fd62ea1a	3091	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	3092	}
NYX	0:85b3fd62ea1a	3093
NYX	0:85b3fd62ea1a	3094	/**
NYX	0:85b3fd62ea1a	3095	* @brief Handle the end of the RX transaction.
NYX	0:85b3fd62ea1a	3096	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	3097	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	3098	* @retval None
NYX	0:85b3fd62ea1a	3099	*/
NYX	0:85b3fd62ea1a	3100	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	3101	{
NYX	0:85b3fd62ea1a	3102	/* Disable RXNE and ERR interrupt */
NYX	0:85b3fd62ea1a	3103	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	3104
NYX	0:85b3fd62ea1a	3105	/* Check the end of the transaction */
NYX	0:85b3fd62ea1a	3106	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
NYX	0:85b3fd62ea1a	3107	{
NYX	0:85b3fd62ea1a	3108	/* Disable SPI peripheral */
NYX	0:85b3fd62ea1a	3109	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	3110	}
NYX	0:85b3fd62ea1a	3111
NYX	0:85b3fd62ea1a	3112	/* Clear overrun flag in 2 Lines communication mode because received is not read */
NYX	0:85b3fd62ea1a	3113	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
NYX	0:85b3fd62ea1a	3114	{
NYX	0:85b3fd62ea1a	3115	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	3116	}
NYX	0:85b3fd62ea1a	3117	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	3118
NYX	0:85b3fd62ea1a	3119	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	3120	/* Check if CRC error occurred */
NYX	0:85b3fd62ea1a	3121	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
NYX	0:85b3fd62ea1a	3122	{
NYX	0:85b3fd62ea1a	3123	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
NYX	0:85b3fd62ea1a	3124	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
NYX	0:85b3fd62ea1a	3125	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	3126	}
NYX	0:85b3fd62ea1a	3127	else
NYX	0:85b3fd62ea1a	3128	{
NYX	0:85b3fd62ea1a	3129	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	3130	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	3131	{
NYX	0:85b3fd62ea1a	3132	HAL_SPI_RxCpltCallback(hspi);
NYX	0:85b3fd62ea1a	3133	}
NYX	0:85b3fd62ea1a	3134	else
NYX	0:85b3fd62ea1a	3135	{
NYX	0:85b3fd62ea1a	3136	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	3137	}
NYX	0:85b3fd62ea1a	3138	#if (USE_SPI_CRC != 0U)
NYX	0:85b3fd62ea1a	3139	}
NYX	0:85b3fd62ea1a	3140	#endif /* USE_SPI_CRC */
NYX	0:85b3fd62ea1a	3141	}
NYX	0:85b3fd62ea1a	3142
NYX	0:85b3fd62ea1a	3143	/**
NYX	0:85b3fd62ea1a	3144	* @brief Handle the end of the TX transaction.
NYX	0:85b3fd62ea1a	3145	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	3146	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	3147	* @retval None
NYX	0:85b3fd62ea1a	3148	*/
NYX	0:85b3fd62ea1a	3149	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	3150	{
NYX	0:85b3fd62ea1a	3151	uint32_t tickstart = 0U;
NYX	0:85b3fd62ea1a	3152	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
NYX	0:85b3fd62ea1a	3153
NYX	0:85b3fd62ea1a	3154	/* Init tickstart for timeout management*/
NYX	0:85b3fd62ea1a	3155	tickstart = HAL_GetTick();
NYX	0:85b3fd62ea1a	3156
NYX	0:85b3fd62ea1a	3157	/* Wait until TXE flag is set */
NYX	0:85b3fd62ea1a	3158	do
NYX	0:85b3fd62ea1a	3159	{
NYX	0:85b3fd62ea1a	3160	if(count-- == 0U)
NYX	0:85b3fd62ea1a	3161	{
NYX	0:85b3fd62ea1a	3162	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	3163	break;
NYX	0:85b3fd62ea1a	3164	}
NYX	0:85b3fd62ea1a	3165	}
NYX	0:85b3fd62ea1a	3166	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
NYX	0:85b3fd62ea1a	3167
NYX	0:85b3fd62ea1a	3168	/* Disable TXE and ERR interrupt */
NYX	0:85b3fd62ea1a	3169	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
NYX	0:85b3fd62ea1a	3170
NYX	0:85b3fd62ea1a	3171	/* Check Busy flag */
NYX	0:85b3fd62ea1a	3172	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
NYX	0:85b3fd62ea1a	3173	{
NYX	0:85b3fd62ea1a	3174	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	3175	}
NYX	0:85b3fd62ea1a	3176
NYX	0:85b3fd62ea1a	3177	/* Clear overrun flag in 2 Lines communication mode because received is not read */
NYX	0:85b3fd62ea1a	3178	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
NYX	0:85b3fd62ea1a	3179	{
NYX	0:85b3fd62ea1a	3180	__HAL_SPI_CLEAR_OVRFLAG(hspi);
NYX	0:85b3fd62ea1a	3181	}
NYX	0:85b3fd62ea1a	3182
NYX	0:85b3fd62ea1a	3183	hspi->State = HAL_SPI_STATE_READY;
NYX	0:85b3fd62ea1a	3184	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
NYX	0:85b3fd62ea1a	3185	{
NYX	0:85b3fd62ea1a	3186	HAL_SPI_ErrorCallback(hspi);
NYX	0:85b3fd62ea1a	3187	}
NYX	0:85b3fd62ea1a	3188	else
NYX	0:85b3fd62ea1a	3189	{
NYX	0:85b3fd62ea1a	3190	HAL_SPI_TxCpltCallback(hspi);
NYX	0:85b3fd62ea1a	3191	}
NYX	0:85b3fd62ea1a	3192	}
NYX	0:85b3fd62ea1a	3193
NYX	0:85b3fd62ea1a	3194	/**
NYX	0:85b3fd62ea1a	3195	* @}
NYX	0:85b3fd62ea1a	3196	*/
NYX	0:85b3fd62ea1a	3197
NYX	0:85b3fd62ea1a	3198	/**
NYX	0:85b3fd62ea1a	3199	* @brief Handle abort a Tx or Rx transaction.
NYX	0:85b3fd62ea1a	3200	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	3201	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	3202	* @retval None
NYX	0:85b3fd62ea1a	3203	*/
NYX	0:85b3fd62ea1a	3204	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	3205	{
NYX	0:85b3fd62ea1a	3206	__IO uint32_t tmpreg = 0U;
NYX	0:85b3fd62ea1a	3207	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
NYX	0:85b3fd62ea1a	3208
NYX	0:85b3fd62ea1a	3209	/* Wait until TXE flag is set */
NYX	0:85b3fd62ea1a	3210	do
NYX	0:85b3fd62ea1a	3211	{
NYX	0:85b3fd62ea1a	3212	if(count-- == 0U)
NYX	0:85b3fd62ea1a	3213	{
NYX	0:85b3fd62ea1a	3214	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
NYX	0:85b3fd62ea1a	3215	break;
NYX	0:85b3fd62ea1a	3216	}
NYX	0:85b3fd62ea1a	3217	}
NYX	0:85b3fd62ea1a	3218	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
NYX	0:85b3fd62ea1a	3219
NYX	0:85b3fd62ea1a	3220	/* Disable SPI Peripheral */
NYX	0:85b3fd62ea1a	3221	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	3222
NYX	0:85b3fd62ea1a	3223	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
NYX	0:85b3fd62ea1a	3224	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
NYX	0:85b3fd62ea1a	3225
NYX	0:85b3fd62ea1a	3226	/* Flush DR Register */
NYX	0:85b3fd62ea1a	3227	tmpreg = ((__IO uint32_t )&hspi->Instance->DR);
NYX	0:85b3fd62ea1a	3228
NYX	0:85b3fd62ea1a	3229	/* To avoid GCC warning */
NYX	0:85b3fd62ea1a	3230	UNUSED(tmpreg);
NYX	0:85b3fd62ea1a	3231	}
NYX	0:85b3fd62ea1a	3232
NYX	0:85b3fd62ea1a	3233	/**
NYX	0:85b3fd62ea1a	3234	* @brief Handle abort a Tx or Rx transaction.
NYX	0:85b3fd62ea1a	3235	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
NYX	0:85b3fd62ea1a	3236	* the configuration information for SPI module.
NYX	0:85b3fd62ea1a	3237	* @retval None
NYX	0:85b3fd62ea1a	3238	*/
NYX	0:85b3fd62ea1a	3239	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
NYX	0:85b3fd62ea1a	3240	{
NYX	0:85b3fd62ea1a	3241	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
NYX	0:85b3fd62ea1a	3242	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE \| SPI_CR2_RXNEIE \| SPI_CR2_ERRIE));
NYX	0:85b3fd62ea1a	3243
NYX	0:85b3fd62ea1a	3244	/* Disable SPI Peripheral */
NYX	0:85b3fd62ea1a	3245	__HAL_SPI_DISABLE(hspi);
NYX	0:85b3fd62ea1a	3246	}
NYX	0:85b3fd62ea1a	3247	/**
NYX	0:85b3fd62ea1a	3248	* @}
NYX	0:85b3fd62ea1a	3249	*/
NYX	0:85b3fd62ea1a	3250	#endif /* HAL_SPI_MODULE_ENABLED */
NYX	0:85b3fd62ea1a	3251
NYX	0:85b3fd62ea1a	3252	/**
NYX	0:85b3fd62ea1a	3253	* @}
NYX	0:85b3fd62ea1a	3254	*/
NYX	0:85b3fd62ea1a	3255
NYX	0:85b3fd62ea1a	3256	/**
NYX	0:85b3fd62ea1a	3257	* @}
NYX	0:85b3fd62ea1a	3258	*/
NYX	0:85b3fd62ea1a	3259
NYX	0:85b3fd62ea1a	3260	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

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