Takaaki Numai / mbed-dev

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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NYX 0:85b3fd62ea1a 1 /**
NYX 0:85b3fd62ea1a 2 ******************************************************************************
NYX 0:85b3fd62ea1a 3 * @file stm32f4xx_hal_sdram.c
NYX 0:85b3fd62ea1a 4 * @author MCD Application Team
NYX 0:85b3fd62ea1a 5 * @version V1.7.1
NYX 0:85b3fd62ea1a 6 * @date 14-April-2017
NYX 0:85b3fd62ea1a 7 * @brief SDRAM HAL module driver.
NYX 0:85b3fd62ea1a 8 * This file provides a generic firmware to drive SDRAM memories mounted
NYX 0:85b3fd62ea1a 9 * as external device.
NYX 0:85b3fd62ea1a 10 *
NYX 0:85b3fd62ea1a 11 @verbatim
NYX 0:85b3fd62ea1a 12 ==============================================================================
NYX 0:85b3fd62ea1a 13 ##### How to use this driver #####
NYX 0:85b3fd62ea1a 14 ==============================================================================
NYX 0:85b3fd62ea1a 15 [..]
NYX 0:85b3fd62ea1a 16 This driver is a generic layered driver which contains a set of APIs used to
NYX 0:85b3fd62ea1a 17 control SDRAM memories. It uses the FMC layer functions to interface
NYX 0:85b3fd62ea1a 18 with SDRAM devices.
NYX 0:85b3fd62ea1a 19 The following sequence should be followed to configure the FMC to interface
NYX 0:85b3fd62ea1a 20 with SDRAM memories:
NYX 0:85b3fd62ea1a 21
NYX 0:85b3fd62ea1a 22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
NYX 0:85b3fd62ea1a 23 SDRAM_HandleTypeDef hdsram
NYX 0:85b3fd62ea1a 24
NYX 0:85b3fd62ea1a 25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
NYX 0:85b3fd62ea1a 26 values of the structure member.
NYX 0:85b3fd62ea1a 27
NYX 0:85b3fd62ea1a 28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
NYX 0:85b3fd62ea1a 29 base register instance for NOR or SDRAM device
NYX 0:85b3fd62ea1a 30
NYX 0:85b3fd62ea1a 31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
NYX 0:85b3fd62ea1a 32 FMC_SDRAM_TimingTypeDef Timing;
NYX 0:85b3fd62ea1a 33 and fill its fields with the allowed values of the structure member.
NYX 0:85b3fd62ea1a 34
NYX 0:85b3fd62ea1a 35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
NYX 0:85b3fd62ea1a 36 performs the following sequence:
NYX 0:85b3fd62ea1a 37
NYX 0:85b3fd62ea1a 38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
NYX 0:85b3fd62ea1a 39 (##) Control register configuration using the FMC SDRAM interface function
NYX 0:85b3fd62ea1a 40 FMC_SDRAM_Init()
NYX 0:85b3fd62ea1a 41 (##) Timing register configuration using the FMC SDRAM interface function
NYX 0:85b3fd62ea1a 42 FMC_SDRAM_Timing_Init()
NYX 0:85b3fd62ea1a 43 (##) Program the SDRAM external device by applying its initialization sequence
NYX 0:85b3fd62ea1a 44 according to the device plugged in your hardware. This step is mandatory
NYX 0:85b3fd62ea1a 45 for accessing the SDRAM device.
NYX 0:85b3fd62ea1a 46
NYX 0:85b3fd62ea1a 47 (#) At this stage you can perform read/write accesses from/to the memory connected
NYX 0:85b3fd62ea1a 48 to the SDRAM Bank. You can perform either polling or DMA transfer using the
NYX 0:85b3fd62ea1a 49 following APIs:
NYX 0:85b3fd62ea1a 50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
NYX 0:85b3fd62ea1a 51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
NYX 0:85b3fd62ea1a 52
NYX 0:85b3fd62ea1a 53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
NYX 0:85b3fd62ea1a 54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
NYX 0:85b3fd62ea1a 55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
NYX 0:85b3fd62ea1a 56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
NYX 0:85b3fd62ea1a 57 structure.
NYX 0:85b3fd62ea1a 58
NYX 0:85b3fd62ea1a 59 (#) You can continuously monitor the SDRAM device HAL state by calling the function
NYX 0:85b3fd62ea1a 60 HAL_SDRAM_GetState()
NYX 0:85b3fd62ea1a 61
NYX 0:85b3fd62ea1a 62 @endverbatim
NYX 0:85b3fd62ea1a 63 ******************************************************************************
NYX 0:85b3fd62ea1a 64 * @attention
NYX 0:85b3fd62ea1a 65 *
NYX 0:85b3fd62ea1a 66 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
NYX 0:85b3fd62ea1a 67 *
NYX 0:85b3fd62ea1a 68 * Redistribution and use in source and binary forms, with or without modification,
NYX 0:85b3fd62ea1a 69 * are permitted provided that the following conditions are met:
NYX 0:85b3fd62ea1a 70 * 1. Redistributions of source code must retain the above copyright notice,
NYX 0:85b3fd62ea1a 71 * this list of conditions and the following disclaimer.
NYX 0:85b3fd62ea1a 72 * 2. Redistributions in binary form must reproduce the above copyright notice,
NYX 0:85b3fd62ea1a 73 * this list of conditions and the following disclaimer in the documentation
NYX 0:85b3fd62ea1a 74 * and/or other materials provided with the distribution.
NYX 0:85b3fd62ea1a 75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NYX 0:85b3fd62ea1a 76 * may be used to endorse or promote products derived from this software
NYX 0:85b3fd62ea1a 77 * without specific prior written permission.
NYX 0:85b3fd62ea1a 78 *
NYX 0:85b3fd62ea1a 79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NYX 0:85b3fd62ea1a 80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NYX 0:85b3fd62ea1a 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NYX 0:85b3fd62ea1a 82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NYX 0:85b3fd62ea1a 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NYX 0:85b3fd62ea1a 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NYX 0:85b3fd62ea1a 85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NYX 0:85b3fd62ea1a 86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NYX 0:85b3fd62ea1a 87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NYX 0:85b3fd62ea1a 88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NYX 0:85b3fd62ea1a 89 *
NYX 0:85b3fd62ea1a 90 ******************************************************************************
NYX 0:85b3fd62ea1a 91 */
NYX 0:85b3fd62ea1a 92
NYX 0:85b3fd62ea1a 93 /* Includes ------------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 94 #include "stm32f4xx_hal.h"
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 /** @addtogroup STM32F4xx_HAL_Driver
NYX 0:85b3fd62ea1a 97 * @{
NYX 0:85b3fd62ea1a 98 */
NYX 0:85b3fd62ea1a 99
NYX 0:85b3fd62ea1a 100 /** @defgroup SDRAM SDRAM
NYX 0:85b3fd62ea1a 101 * @brief SDRAM driver modules
NYX 0:85b3fd62ea1a 102 * @{
NYX 0:85b3fd62ea1a 103 */
NYX 0:85b3fd62ea1a 104 #ifdef HAL_SDRAM_MODULE_ENABLED
NYX 0:85b3fd62ea1a 105 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
NYX 0:85b3fd62ea1a 106 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
NYX 0:85b3fd62ea1a 107
NYX 0:85b3fd62ea1a 108 /* Private typedef -----------------------------------------------------------*/
NYX 0:85b3fd62ea1a 109 /* Private define ------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 110 /* Private macro -------------------------------------------------------------*/
NYX 0:85b3fd62ea1a 111 /* Private variables ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 112 /* Private functions ---------------------------------------------------------*/
NYX 0:85b3fd62ea1a 113 /* Exported functions --------------------------------------------------------*/
NYX 0:85b3fd62ea1a 114 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
NYX 0:85b3fd62ea1a 115 * @{
NYX 0:85b3fd62ea1a 116 */
NYX 0:85b3fd62ea1a 117
NYX 0:85b3fd62ea1a 118 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
NYX 0:85b3fd62ea1a 119 * @brief Initialization and Configuration functions
NYX 0:85b3fd62ea1a 120 *
NYX 0:85b3fd62ea1a 121 @verbatim
NYX 0:85b3fd62ea1a 122 ==============================================================================
NYX 0:85b3fd62ea1a 123 ##### SDRAM Initialization and de_initialization functions #####
NYX 0:85b3fd62ea1a 124 ==============================================================================
NYX 0:85b3fd62ea1a 125 [..]
NYX 0:85b3fd62ea1a 126 This section provides functions allowing to initialize/de-initialize
NYX 0:85b3fd62ea1a 127 the SDRAM memory
NYX 0:85b3fd62ea1a 128
NYX 0:85b3fd62ea1a 129 @endverbatim
NYX 0:85b3fd62ea1a 130 * @{
NYX 0:85b3fd62ea1a 131 */
NYX 0:85b3fd62ea1a 132
NYX 0:85b3fd62ea1a 133 /**
NYX 0:85b3fd62ea1a 134 * @brief Performs the SDRAM device initialization sequence.
NYX 0:85b3fd62ea1a 135 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 136 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 137 * @param Timing: Pointer to SDRAM control timing structure
NYX 0:85b3fd62ea1a 138 * @retval HAL status
NYX 0:85b3fd62ea1a 139 */
NYX 0:85b3fd62ea1a 140 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
NYX 0:85b3fd62ea1a 141 {
NYX 0:85b3fd62ea1a 142 /* Check the SDRAM handle parameter */
NYX 0:85b3fd62ea1a 143 if(hsdram == NULL)
NYX 0:85b3fd62ea1a 144 {
NYX 0:85b3fd62ea1a 145 return HAL_ERROR;
NYX 0:85b3fd62ea1a 146 }
NYX 0:85b3fd62ea1a 147
NYX 0:85b3fd62ea1a 148 if(hsdram->State == HAL_SDRAM_STATE_RESET)
NYX 0:85b3fd62ea1a 149 {
NYX 0:85b3fd62ea1a 150 /* Allocate lock resource and initialize it */
NYX 0:85b3fd62ea1a 151 hsdram->Lock = HAL_UNLOCKED;
NYX 0:85b3fd62ea1a 152 /* Initialize the low level hardware (MSP) */
NYX 0:85b3fd62ea1a 153 HAL_SDRAM_MspInit(hsdram);
NYX 0:85b3fd62ea1a 154 }
NYX 0:85b3fd62ea1a 155
NYX 0:85b3fd62ea1a 156 /* Initialize the SDRAM controller state */
NYX 0:85b3fd62ea1a 157 hsdram->State = HAL_SDRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 158
NYX 0:85b3fd62ea1a 159 /* Initialize SDRAM control Interface */
NYX 0:85b3fd62ea1a 160 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
NYX 0:85b3fd62ea1a 161
NYX 0:85b3fd62ea1a 162 /* Initialize SDRAM timing Interface */
NYX 0:85b3fd62ea1a 163 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
NYX 0:85b3fd62ea1a 164
NYX 0:85b3fd62ea1a 165 /* Update the SDRAM controller state */
NYX 0:85b3fd62ea1a 166 hsdram->State = HAL_SDRAM_STATE_READY;
NYX 0:85b3fd62ea1a 167
NYX 0:85b3fd62ea1a 168 return HAL_OK;
NYX 0:85b3fd62ea1a 169 }
NYX 0:85b3fd62ea1a 170
NYX 0:85b3fd62ea1a 171 /**
NYX 0:85b3fd62ea1a 172 * @brief Perform the SDRAM device initialization sequence.
NYX 0:85b3fd62ea1a 173 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 174 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 175 * @retval HAL status
NYX 0:85b3fd62ea1a 176 */
NYX 0:85b3fd62ea1a 177 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 178 {
NYX 0:85b3fd62ea1a 179 /* Initialize the low level hardware (MSP) */
NYX 0:85b3fd62ea1a 180 HAL_SDRAM_MspDeInit(hsdram);
NYX 0:85b3fd62ea1a 181
NYX 0:85b3fd62ea1a 182 /* Configure the SDRAM registers with their reset values */
NYX 0:85b3fd62ea1a 183 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
NYX 0:85b3fd62ea1a 184
NYX 0:85b3fd62ea1a 185 /* Reset the SDRAM controller state */
NYX 0:85b3fd62ea1a 186 hsdram->State = HAL_SDRAM_STATE_RESET;
NYX 0:85b3fd62ea1a 187
NYX 0:85b3fd62ea1a 188 /* Release Lock */
NYX 0:85b3fd62ea1a 189 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 190
NYX 0:85b3fd62ea1a 191 return HAL_OK;
NYX 0:85b3fd62ea1a 192 }
NYX 0:85b3fd62ea1a 193
NYX 0:85b3fd62ea1a 194 /**
NYX 0:85b3fd62ea1a 195 * @brief SDRAM MSP Init.
NYX 0:85b3fd62ea1a 196 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 197 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 198 * @retval None
NYX 0:85b3fd62ea1a 199 */
NYX 0:85b3fd62ea1a 200 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 201 {
NYX 0:85b3fd62ea1a 202 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 203 UNUSED(hsdram);
NYX 0:85b3fd62ea1a 204 /* NOTE: This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 205 the HAL_SDRAM_MspInit could be implemented in the user file
NYX 0:85b3fd62ea1a 206 */
NYX 0:85b3fd62ea1a 207 }
NYX 0:85b3fd62ea1a 208
NYX 0:85b3fd62ea1a 209 /**
NYX 0:85b3fd62ea1a 210 * @brief SDRAM MSP DeInit.
NYX 0:85b3fd62ea1a 211 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 212 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 213 * @retval None
NYX 0:85b3fd62ea1a 214 */
NYX 0:85b3fd62ea1a 215 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 216 {
NYX 0:85b3fd62ea1a 217 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 218 UNUSED(hsdram);
NYX 0:85b3fd62ea1a 219 /* NOTE: This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 220 the HAL_SDRAM_MspDeInit could be implemented in the user file
NYX 0:85b3fd62ea1a 221 */
NYX 0:85b3fd62ea1a 222 }
NYX 0:85b3fd62ea1a 223
NYX 0:85b3fd62ea1a 224 /**
NYX 0:85b3fd62ea1a 225 * @brief This function handles SDRAM refresh error interrupt request.
NYX 0:85b3fd62ea1a 226 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 227 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 228 * @retval HAL status
NYX 0:85b3fd62ea1a 229 */
NYX 0:85b3fd62ea1a 230 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 231 {
NYX 0:85b3fd62ea1a 232 /* Check SDRAM interrupt Rising edge flag */
NYX 0:85b3fd62ea1a 233 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
NYX 0:85b3fd62ea1a 234 {
NYX 0:85b3fd62ea1a 235 /* SDRAM refresh error interrupt callback */
NYX 0:85b3fd62ea1a 236 HAL_SDRAM_RefreshErrorCallback(hsdram);
NYX 0:85b3fd62ea1a 237
NYX 0:85b3fd62ea1a 238 /* Clear SDRAM refresh error interrupt pending bit */
NYX 0:85b3fd62ea1a 239 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
NYX 0:85b3fd62ea1a 240 }
NYX 0:85b3fd62ea1a 241 }
NYX 0:85b3fd62ea1a 242
NYX 0:85b3fd62ea1a 243 /**
NYX 0:85b3fd62ea1a 244 * @brief SDRAM Refresh error callback.
NYX 0:85b3fd62ea1a 245 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 246 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 247 * @retval None
NYX 0:85b3fd62ea1a 248 */
NYX 0:85b3fd62ea1a 249 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 250 {
NYX 0:85b3fd62ea1a 251 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 252 UNUSED(hsdram);
NYX 0:85b3fd62ea1a 253 /* NOTE: This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 254 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 255 */
NYX 0:85b3fd62ea1a 256 }
NYX 0:85b3fd62ea1a 257
NYX 0:85b3fd62ea1a 258 /**
NYX 0:85b3fd62ea1a 259 * @brief DMA transfer complete callback.
NYX 0:85b3fd62ea1a 260 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 261 * the configuration information for the specified DMA module.
NYX 0:85b3fd62ea1a 262 * @retval None
NYX 0:85b3fd62ea1a 263 */
NYX 0:85b3fd62ea1a 264 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 265 {
NYX 0:85b3fd62ea1a 266 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 267 UNUSED(hdma);
NYX 0:85b3fd62ea1a 268 /* NOTE: This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 269 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 270 */
NYX 0:85b3fd62ea1a 271 }
NYX 0:85b3fd62ea1a 272
NYX 0:85b3fd62ea1a 273 /**
NYX 0:85b3fd62ea1a 274 * @brief DMA transfer complete error callback.
NYX 0:85b3fd62ea1a 275 * @param hdma: DMA handle
NYX 0:85b3fd62ea1a 276 * @retval None
NYX 0:85b3fd62ea1a 277 */
NYX 0:85b3fd62ea1a 278 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
NYX 0:85b3fd62ea1a 279 {
NYX 0:85b3fd62ea1a 280 /* Prevent unused argument(s) compilation warning */
NYX 0:85b3fd62ea1a 281 UNUSED(hdma);
NYX 0:85b3fd62ea1a 282 /* NOTE: This function Should not be modified, when the callback is needed,
NYX 0:85b3fd62ea1a 283 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
NYX 0:85b3fd62ea1a 284 */
NYX 0:85b3fd62ea1a 285 }
NYX 0:85b3fd62ea1a 286 /**
NYX 0:85b3fd62ea1a 287 * @}
NYX 0:85b3fd62ea1a 288 */
NYX 0:85b3fd62ea1a 289
NYX 0:85b3fd62ea1a 290 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
NYX 0:85b3fd62ea1a 291 * @brief Input Output and memory control functions
NYX 0:85b3fd62ea1a 292 *
NYX 0:85b3fd62ea1a 293 @verbatim
NYX 0:85b3fd62ea1a 294 ==============================================================================
NYX 0:85b3fd62ea1a 295 ##### SDRAM Input and Output functions #####
NYX 0:85b3fd62ea1a 296 ==============================================================================
NYX 0:85b3fd62ea1a 297 [..]
NYX 0:85b3fd62ea1a 298 This section provides functions allowing to use and control the SDRAM memory
NYX 0:85b3fd62ea1a 299
NYX 0:85b3fd62ea1a 300 @endverbatim
NYX 0:85b3fd62ea1a 301 * @{
NYX 0:85b3fd62ea1a 302 */
NYX 0:85b3fd62ea1a 303
NYX 0:85b3fd62ea1a 304 /**
NYX 0:85b3fd62ea1a 305 * @brief Reads 8-bit data buffer from the SDRAM memory.
NYX 0:85b3fd62ea1a 306 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 307 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 308 * @param pAddress: Pointer to read start address
NYX 0:85b3fd62ea1a 309 * @param pDstBuffer: Pointer to destination buffer
NYX 0:85b3fd62ea1a 310 * @param BufferSize: Size of the buffer to read from memory
NYX 0:85b3fd62ea1a 311 * @retval HAL status
NYX 0:85b3fd62ea1a 312 */
NYX 0:85b3fd62ea1a 313 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 314 {
NYX 0:85b3fd62ea1a 315 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
NYX 0:85b3fd62ea1a 316
NYX 0:85b3fd62ea1a 317 /* Process Locked */
NYX 0:85b3fd62ea1a 318 __HAL_LOCK(hsdram);
NYX 0:85b3fd62ea1a 319
NYX 0:85b3fd62ea1a 320 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 321 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 322 {
NYX 0:85b3fd62ea1a 323 return HAL_BUSY;
NYX 0:85b3fd62ea1a 324 }
NYX 0:85b3fd62ea1a 325 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
NYX 0:85b3fd62ea1a 326 {
NYX 0:85b3fd62ea1a 327 return HAL_ERROR;
NYX 0:85b3fd62ea1a 328 }
NYX 0:85b3fd62ea1a 329
NYX 0:85b3fd62ea1a 330 /* Read data from source */
NYX 0:85b3fd62ea1a 331 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 332 {
NYX 0:85b3fd62ea1a 333 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
NYX 0:85b3fd62ea1a 334 pDstBuffer++;
NYX 0:85b3fd62ea1a 335 pSdramAddress++;
NYX 0:85b3fd62ea1a 336 }
NYX 0:85b3fd62ea1a 337
NYX 0:85b3fd62ea1a 338 /* Process Unlocked */
NYX 0:85b3fd62ea1a 339 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 340
NYX 0:85b3fd62ea1a 341 return HAL_OK;
NYX 0:85b3fd62ea1a 342 }
NYX 0:85b3fd62ea1a 343
NYX 0:85b3fd62ea1a 344 /**
NYX 0:85b3fd62ea1a 345 * @brief Writes 8-bit data buffer to SDRAM memory.
NYX 0:85b3fd62ea1a 346 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 347 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 348 * @param pAddress: Pointer to write start address
NYX 0:85b3fd62ea1a 349 * @param pSrcBuffer: Pointer to source buffer to write
NYX 0:85b3fd62ea1a 350 * @param BufferSize: Size of the buffer to write to memory
NYX 0:85b3fd62ea1a 351 * @retval HAL status
NYX 0:85b3fd62ea1a 352 */
NYX 0:85b3fd62ea1a 353 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 354 {
NYX 0:85b3fd62ea1a 355 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
NYX 0:85b3fd62ea1a 356 uint32_t tmp = 0U;
NYX 0:85b3fd62ea1a 357
NYX 0:85b3fd62ea1a 358 /* Process Locked */
NYX 0:85b3fd62ea1a 359 __HAL_LOCK(hsdram);
NYX 0:85b3fd62ea1a 360
NYX 0:85b3fd62ea1a 361 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 362 tmp = hsdram->State;
NYX 0:85b3fd62ea1a 363
NYX 0:85b3fd62ea1a 364 if(tmp == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 365 {
NYX 0:85b3fd62ea1a 366 return HAL_BUSY;
NYX 0:85b3fd62ea1a 367 }
NYX 0:85b3fd62ea1a 368 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
NYX 0:85b3fd62ea1a 369 {
NYX 0:85b3fd62ea1a 370 return HAL_ERROR;
NYX 0:85b3fd62ea1a 371 }
NYX 0:85b3fd62ea1a 372
NYX 0:85b3fd62ea1a 373 /* Write data to memory */
NYX 0:85b3fd62ea1a 374 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 375 {
NYX 0:85b3fd62ea1a 376 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
NYX 0:85b3fd62ea1a 377 pSrcBuffer++;
NYX 0:85b3fd62ea1a 378 pSdramAddress++;
NYX 0:85b3fd62ea1a 379 }
NYX 0:85b3fd62ea1a 380
NYX 0:85b3fd62ea1a 381 /* Process Unlocked */
NYX 0:85b3fd62ea1a 382 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 383
NYX 0:85b3fd62ea1a 384 return HAL_OK;
NYX 0:85b3fd62ea1a 385 }
NYX 0:85b3fd62ea1a 386
NYX 0:85b3fd62ea1a 387 /**
NYX 0:85b3fd62ea1a 388 * @brief Reads 16-bit data buffer from the SDRAM memory.
NYX 0:85b3fd62ea1a 389 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 390 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 391 * @param pAddress: Pointer to read start address
NYX 0:85b3fd62ea1a 392 * @param pDstBuffer: Pointer to destination buffer
NYX 0:85b3fd62ea1a 393 * @param BufferSize: Size of the buffer to read from memory
NYX 0:85b3fd62ea1a 394 * @retval HAL status
NYX 0:85b3fd62ea1a 395 */
NYX 0:85b3fd62ea1a 396 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 397 {
NYX 0:85b3fd62ea1a 398 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
NYX 0:85b3fd62ea1a 399
NYX 0:85b3fd62ea1a 400 /* Process Locked */
NYX 0:85b3fd62ea1a 401 __HAL_LOCK(hsdram);
NYX 0:85b3fd62ea1a 402
NYX 0:85b3fd62ea1a 403 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 404 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 405 {
NYX 0:85b3fd62ea1a 406 return HAL_BUSY;
NYX 0:85b3fd62ea1a 407 }
NYX 0:85b3fd62ea1a 408 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
NYX 0:85b3fd62ea1a 409 {
NYX 0:85b3fd62ea1a 410 return HAL_ERROR;
NYX 0:85b3fd62ea1a 411 }
NYX 0:85b3fd62ea1a 412
NYX 0:85b3fd62ea1a 413 /* Read data from source */
NYX 0:85b3fd62ea1a 414 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 415 {
NYX 0:85b3fd62ea1a 416 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
NYX 0:85b3fd62ea1a 417 pDstBuffer++;
NYX 0:85b3fd62ea1a 418 pSdramAddress++;
NYX 0:85b3fd62ea1a 419 }
NYX 0:85b3fd62ea1a 420
NYX 0:85b3fd62ea1a 421 /* Process Unlocked */
NYX 0:85b3fd62ea1a 422 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 423
NYX 0:85b3fd62ea1a 424 return HAL_OK;
NYX 0:85b3fd62ea1a 425 }
NYX 0:85b3fd62ea1a 426
NYX 0:85b3fd62ea1a 427 /**
NYX 0:85b3fd62ea1a 428 * @brief Writes 16-bit data buffer to SDRAM memory.
NYX 0:85b3fd62ea1a 429 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 430 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 431 * @param pAddress: Pointer to write start address
NYX 0:85b3fd62ea1a 432 * @param pSrcBuffer: Pointer to source buffer to write
NYX 0:85b3fd62ea1a 433 * @param BufferSize: Size of the buffer to write to memory
NYX 0:85b3fd62ea1a 434 * @retval HAL status
NYX 0:85b3fd62ea1a 435 */
NYX 0:85b3fd62ea1a 436 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 437 {
NYX 0:85b3fd62ea1a 438 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
NYX 0:85b3fd62ea1a 439 uint32_t tmp = 0U;
NYX 0:85b3fd62ea1a 440
NYX 0:85b3fd62ea1a 441 /* Process Locked */
NYX 0:85b3fd62ea1a 442 __HAL_LOCK(hsdram);
NYX 0:85b3fd62ea1a 443
NYX 0:85b3fd62ea1a 444 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 445 tmp = hsdram->State;
NYX 0:85b3fd62ea1a 446
NYX 0:85b3fd62ea1a 447 if(tmp == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 448 {
NYX 0:85b3fd62ea1a 449 return HAL_BUSY;
NYX 0:85b3fd62ea1a 450 }
NYX 0:85b3fd62ea1a 451 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
NYX 0:85b3fd62ea1a 452 {
NYX 0:85b3fd62ea1a 453 return HAL_ERROR;
NYX 0:85b3fd62ea1a 454 }
NYX 0:85b3fd62ea1a 455
NYX 0:85b3fd62ea1a 456 /* Write data to memory */
NYX 0:85b3fd62ea1a 457 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 458 {
NYX 0:85b3fd62ea1a 459 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
NYX 0:85b3fd62ea1a 460 pSrcBuffer++;
NYX 0:85b3fd62ea1a 461 pSdramAddress++;
NYX 0:85b3fd62ea1a 462 }
NYX 0:85b3fd62ea1a 463
NYX 0:85b3fd62ea1a 464 /* Process Unlocked */
NYX 0:85b3fd62ea1a 465 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 466
NYX 0:85b3fd62ea1a 467 return HAL_OK;
NYX 0:85b3fd62ea1a 468 }
NYX 0:85b3fd62ea1a 469
NYX 0:85b3fd62ea1a 470 /**
NYX 0:85b3fd62ea1a 471 * @brief Reads 32-bit data buffer from the SDRAM memory.
NYX 0:85b3fd62ea1a 472 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 473 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 474 * @param pAddress: Pointer to read start address
NYX 0:85b3fd62ea1a 475 * @param pDstBuffer: Pointer to destination buffer
NYX 0:85b3fd62ea1a 476 * @param BufferSize: Size of the buffer to read from memory
NYX 0:85b3fd62ea1a 477 * @retval HAL status
NYX 0:85b3fd62ea1a 478 */
NYX 0:85b3fd62ea1a 479 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 480 {
NYX 0:85b3fd62ea1a 481 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
NYX 0:85b3fd62ea1a 482
NYX 0:85b3fd62ea1a 483 /* Process Locked */
NYX 0:85b3fd62ea1a 484 __HAL_LOCK(hsdram);
NYX 0:85b3fd62ea1a 485
NYX 0:85b3fd62ea1a 486 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 487 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 488 {
NYX 0:85b3fd62ea1a 489 return HAL_BUSY;
NYX 0:85b3fd62ea1a 490 }
NYX 0:85b3fd62ea1a 491 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
NYX 0:85b3fd62ea1a 492 {
NYX 0:85b3fd62ea1a 493 return HAL_ERROR;
NYX 0:85b3fd62ea1a 494 }
NYX 0:85b3fd62ea1a 495
NYX 0:85b3fd62ea1a 496 /* Read data from source */
NYX 0:85b3fd62ea1a 497 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 498 {
NYX 0:85b3fd62ea1a 499 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
NYX 0:85b3fd62ea1a 500 pDstBuffer++;
NYX 0:85b3fd62ea1a 501 pSdramAddress++;
NYX 0:85b3fd62ea1a 502 }
NYX 0:85b3fd62ea1a 503
NYX 0:85b3fd62ea1a 504 /* Process Unlocked */
NYX 0:85b3fd62ea1a 505 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 506
NYX 0:85b3fd62ea1a 507 return HAL_OK;
NYX 0:85b3fd62ea1a 508 }
NYX 0:85b3fd62ea1a 509
NYX 0:85b3fd62ea1a 510 /**
NYX 0:85b3fd62ea1a 511 * @brief Writes 32-bit data buffer to SDRAM memory.
NYX 0:85b3fd62ea1a 512 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 513 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 514 * @param pAddress: Pointer to write start address
NYX 0:85b3fd62ea1a 515 * @param pSrcBuffer: Pointer to source buffer to write
NYX 0:85b3fd62ea1a 516 * @param BufferSize: Size of the buffer to write to memory
NYX 0:85b3fd62ea1a 517 * @retval HAL status
NYX 0:85b3fd62ea1a 518 */
NYX 0:85b3fd62ea1a 519 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 520 {
NYX 0:85b3fd62ea1a 521 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
NYX 0:85b3fd62ea1a 522 uint32_t tmp = 0U;
NYX 0:85b3fd62ea1a 523
NYX 0:85b3fd62ea1a 524 /* Process Locked */
NYX 0:85b3fd62ea1a 525 __HAL_LOCK(hsdram);
NYX 0:85b3fd62ea1a 526
NYX 0:85b3fd62ea1a 527 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 528 tmp = hsdram->State;
NYX 0:85b3fd62ea1a 529
NYX 0:85b3fd62ea1a 530 if(tmp == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 531 {
NYX 0:85b3fd62ea1a 532 return HAL_BUSY;
NYX 0:85b3fd62ea1a 533 }
NYX 0:85b3fd62ea1a 534 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
NYX 0:85b3fd62ea1a 535 {
NYX 0:85b3fd62ea1a 536 return HAL_ERROR;
NYX 0:85b3fd62ea1a 537 }
NYX 0:85b3fd62ea1a 538
NYX 0:85b3fd62ea1a 539 /* Write data to memory */
NYX 0:85b3fd62ea1a 540 for(; BufferSize != 0U; BufferSize--)
NYX 0:85b3fd62ea1a 541 {
NYX 0:85b3fd62ea1a 542 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
NYX 0:85b3fd62ea1a 543 pSrcBuffer++;
NYX 0:85b3fd62ea1a 544 pSdramAddress++;
NYX 0:85b3fd62ea1a 545 }
NYX 0:85b3fd62ea1a 546
NYX 0:85b3fd62ea1a 547 /* Process Unlocked */
NYX 0:85b3fd62ea1a 548 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 549
NYX 0:85b3fd62ea1a 550 return HAL_OK;
NYX 0:85b3fd62ea1a 551 }
NYX 0:85b3fd62ea1a 552
NYX 0:85b3fd62ea1a 553 /**
NYX 0:85b3fd62ea1a 554 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
NYX 0:85b3fd62ea1a 555 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 556 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 557 * @param pAddress: Pointer to read start address
NYX 0:85b3fd62ea1a 558 * @param pDstBuffer: Pointer to destination buffer
NYX 0:85b3fd62ea1a 559 * @param BufferSize: Size of the buffer to read from memory
NYX 0:85b3fd62ea1a 560 * @retval HAL status
NYX 0:85b3fd62ea1a 561 */
NYX 0:85b3fd62ea1a 562 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 563 {
NYX 0:85b3fd62ea1a 564 uint32_t tmp = 0U;
NYX 0:85b3fd62ea1a 565
NYX 0:85b3fd62ea1a 566 /* Process Locked */
NYX 0:85b3fd62ea1a 567 __HAL_LOCK(hsdram);
NYX 0:85b3fd62ea1a 568
NYX 0:85b3fd62ea1a 569 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 570 tmp = hsdram->State;
NYX 0:85b3fd62ea1a 571
NYX 0:85b3fd62ea1a 572 if(tmp == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 573 {
NYX 0:85b3fd62ea1a 574 return HAL_BUSY;
NYX 0:85b3fd62ea1a 575 }
NYX 0:85b3fd62ea1a 576 else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
NYX 0:85b3fd62ea1a 577 {
NYX 0:85b3fd62ea1a 578 return HAL_ERROR;
NYX 0:85b3fd62ea1a 579 }
NYX 0:85b3fd62ea1a 580
NYX 0:85b3fd62ea1a 581 /* Configure DMA user callbacks */
NYX 0:85b3fd62ea1a 582 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
NYX 0:85b3fd62ea1a 583 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
NYX 0:85b3fd62ea1a 584
NYX 0:85b3fd62ea1a 585 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 586 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
NYX 0:85b3fd62ea1a 587
NYX 0:85b3fd62ea1a 588 /* Process Unlocked */
NYX 0:85b3fd62ea1a 589 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 590
NYX 0:85b3fd62ea1a 591 return HAL_OK;
NYX 0:85b3fd62ea1a 592 }
NYX 0:85b3fd62ea1a 593
NYX 0:85b3fd62ea1a 594 /**
NYX 0:85b3fd62ea1a 595 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
NYX 0:85b3fd62ea1a 596 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 597 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 598 * @param pAddress: Pointer to write start address
NYX 0:85b3fd62ea1a 599 * @param pSrcBuffer: Pointer to source buffer to write
NYX 0:85b3fd62ea1a 600 * @param BufferSize: Size of the buffer to write to memory
NYX 0:85b3fd62ea1a 601 * @retval HAL status
NYX 0:85b3fd62ea1a 602 */
NYX 0:85b3fd62ea1a 603 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
NYX 0:85b3fd62ea1a 604 {
NYX 0:85b3fd62ea1a 605 uint32_t tmp = 0U;
NYX 0:85b3fd62ea1a 606
NYX 0:85b3fd62ea1a 607 /* Process Locked */
NYX 0:85b3fd62ea1a 608 __HAL_LOCK(hsdram);
NYX 0:85b3fd62ea1a 609
NYX 0:85b3fd62ea1a 610 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 611 tmp = hsdram->State;
NYX 0:85b3fd62ea1a 612
NYX 0:85b3fd62ea1a 613 if(tmp == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 614 {
NYX 0:85b3fd62ea1a 615 return HAL_BUSY;
NYX 0:85b3fd62ea1a 616 }
NYX 0:85b3fd62ea1a 617 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
NYX 0:85b3fd62ea1a 618 {
NYX 0:85b3fd62ea1a 619 return HAL_ERROR;
NYX 0:85b3fd62ea1a 620 }
NYX 0:85b3fd62ea1a 621
NYX 0:85b3fd62ea1a 622 /* Configure DMA user callbacks */
NYX 0:85b3fd62ea1a 623 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
NYX 0:85b3fd62ea1a 624 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
NYX 0:85b3fd62ea1a 625
NYX 0:85b3fd62ea1a 626 /* Enable the DMA Stream */
NYX 0:85b3fd62ea1a 627 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
NYX 0:85b3fd62ea1a 628
NYX 0:85b3fd62ea1a 629 /* Process Unlocked */
NYX 0:85b3fd62ea1a 630 __HAL_UNLOCK(hsdram);
NYX 0:85b3fd62ea1a 631
NYX 0:85b3fd62ea1a 632 return HAL_OK;
NYX 0:85b3fd62ea1a 633 }
NYX 0:85b3fd62ea1a 634 /**
NYX 0:85b3fd62ea1a 635 * @}
NYX 0:85b3fd62ea1a 636 */
NYX 0:85b3fd62ea1a 637
NYX 0:85b3fd62ea1a 638 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
NYX 0:85b3fd62ea1a 639 * @brief management functions
NYX 0:85b3fd62ea1a 640 *
NYX 0:85b3fd62ea1a 641 @verbatim
NYX 0:85b3fd62ea1a 642 ==============================================================================
NYX 0:85b3fd62ea1a 643 ##### SDRAM Control functions #####
NYX 0:85b3fd62ea1a 644 ==============================================================================
NYX 0:85b3fd62ea1a 645 [..]
NYX 0:85b3fd62ea1a 646 This subsection provides a set of functions allowing to control dynamically
NYX 0:85b3fd62ea1a 647 the SDRAM interface.
NYX 0:85b3fd62ea1a 648
NYX 0:85b3fd62ea1a 649 @endverbatim
NYX 0:85b3fd62ea1a 650 * @{
NYX 0:85b3fd62ea1a 651 */
NYX 0:85b3fd62ea1a 652
NYX 0:85b3fd62ea1a 653 /**
NYX 0:85b3fd62ea1a 654 * @brief Enables dynamically SDRAM write protection.
NYX 0:85b3fd62ea1a 655 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 656 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 657 * @retval HAL status
NYX 0:85b3fd62ea1a 658 */
NYX 0:85b3fd62ea1a 659 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 660 {
NYX 0:85b3fd62ea1a 661 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 662 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 663 {
NYX 0:85b3fd62ea1a 664 return HAL_BUSY;
NYX 0:85b3fd62ea1a 665 }
NYX 0:85b3fd62ea1a 666
NYX 0:85b3fd62ea1a 667 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 668 hsdram->State = HAL_SDRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 669
NYX 0:85b3fd62ea1a 670 /* Enable write protection */
NYX 0:85b3fd62ea1a 671 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
NYX 0:85b3fd62ea1a 672
NYX 0:85b3fd62ea1a 673 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 674 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
NYX 0:85b3fd62ea1a 675
NYX 0:85b3fd62ea1a 676 return HAL_OK;
NYX 0:85b3fd62ea1a 677 }
NYX 0:85b3fd62ea1a 678
NYX 0:85b3fd62ea1a 679 /**
NYX 0:85b3fd62ea1a 680 * @brief Disables dynamically SDRAM write protection.
NYX 0:85b3fd62ea1a 681 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 682 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 683 * @retval HAL status
NYX 0:85b3fd62ea1a 684 */
NYX 0:85b3fd62ea1a 685 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 686 {
NYX 0:85b3fd62ea1a 687 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 688 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 689 {
NYX 0:85b3fd62ea1a 690 return HAL_BUSY;
NYX 0:85b3fd62ea1a 691 }
NYX 0:85b3fd62ea1a 692
NYX 0:85b3fd62ea1a 693 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 694 hsdram->State = HAL_SDRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 695
NYX 0:85b3fd62ea1a 696 /* Disable write protection */
NYX 0:85b3fd62ea1a 697 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
NYX 0:85b3fd62ea1a 698
NYX 0:85b3fd62ea1a 699 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 700 hsdram->State = HAL_SDRAM_STATE_READY;
NYX 0:85b3fd62ea1a 701
NYX 0:85b3fd62ea1a 702 return HAL_OK;
NYX 0:85b3fd62ea1a 703 }
NYX 0:85b3fd62ea1a 704
NYX 0:85b3fd62ea1a 705 /**
NYX 0:85b3fd62ea1a 706 * @brief Sends Command to the SDRAM bank.
NYX 0:85b3fd62ea1a 707 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 708 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 709 * @param Command: SDRAM command structure
NYX 0:85b3fd62ea1a 710 * @param Timeout: Timeout duration
NYX 0:85b3fd62ea1a 711 * @retval HAL status
NYX 0:85b3fd62ea1a 712 */
NYX 0:85b3fd62ea1a 713 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
NYX 0:85b3fd62ea1a 714 {
NYX 0:85b3fd62ea1a 715 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 716 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 717 {
NYX 0:85b3fd62ea1a 718 return HAL_BUSY;
NYX 0:85b3fd62ea1a 719 }
NYX 0:85b3fd62ea1a 720
NYX 0:85b3fd62ea1a 721 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 722 hsdram->State = HAL_SDRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 723
NYX 0:85b3fd62ea1a 724 /* Send SDRAM command */
NYX 0:85b3fd62ea1a 725 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
NYX 0:85b3fd62ea1a 726
NYX 0:85b3fd62ea1a 727 /* Update the SDRAM controller state */
NYX 0:85b3fd62ea1a 728 if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
NYX 0:85b3fd62ea1a 729 {
NYX 0:85b3fd62ea1a 730 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
NYX 0:85b3fd62ea1a 731 }
NYX 0:85b3fd62ea1a 732 else
NYX 0:85b3fd62ea1a 733 {
NYX 0:85b3fd62ea1a 734 hsdram->State = HAL_SDRAM_STATE_READY;
NYX 0:85b3fd62ea1a 735 }
NYX 0:85b3fd62ea1a 736
NYX 0:85b3fd62ea1a 737 return HAL_OK;
NYX 0:85b3fd62ea1a 738 }
NYX 0:85b3fd62ea1a 739
NYX 0:85b3fd62ea1a 740 /**
NYX 0:85b3fd62ea1a 741 * @brief Programs the SDRAM Memory Refresh rate.
NYX 0:85b3fd62ea1a 742 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 743 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 744 * @param RefreshRate: The SDRAM refresh rate value
NYX 0:85b3fd62ea1a 745 * @retval HAL status
NYX 0:85b3fd62ea1a 746 */
NYX 0:85b3fd62ea1a 747 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
NYX 0:85b3fd62ea1a 748 {
NYX 0:85b3fd62ea1a 749 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 750 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 751 {
NYX 0:85b3fd62ea1a 752 return HAL_BUSY;
NYX 0:85b3fd62ea1a 753 }
NYX 0:85b3fd62ea1a 754
NYX 0:85b3fd62ea1a 755 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 756 hsdram->State = HAL_SDRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 757
NYX 0:85b3fd62ea1a 758 /* Program the refresh rate */
NYX 0:85b3fd62ea1a 759 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
NYX 0:85b3fd62ea1a 760
NYX 0:85b3fd62ea1a 761 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 762 hsdram->State = HAL_SDRAM_STATE_READY;
NYX 0:85b3fd62ea1a 763
NYX 0:85b3fd62ea1a 764 return HAL_OK;
NYX 0:85b3fd62ea1a 765 }
NYX 0:85b3fd62ea1a 766
NYX 0:85b3fd62ea1a 767 /**
NYX 0:85b3fd62ea1a 768 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
NYX 0:85b3fd62ea1a 769 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 770 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 771 * @param AutoRefreshNumber: The SDRAM auto Refresh number
NYX 0:85b3fd62ea1a 772 * @retval HAL status
NYX 0:85b3fd62ea1a 773 */
NYX 0:85b3fd62ea1a 774 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
NYX 0:85b3fd62ea1a 775 {
NYX 0:85b3fd62ea1a 776 /* Check the SDRAM controller state */
NYX 0:85b3fd62ea1a 777 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
NYX 0:85b3fd62ea1a 778 {
NYX 0:85b3fd62ea1a 779 return HAL_BUSY;
NYX 0:85b3fd62ea1a 780 }
NYX 0:85b3fd62ea1a 781
NYX 0:85b3fd62ea1a 782 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 783 hsdram->State = HAL_SDRAM_STATE_BUSY;
NYX 0:85b3fd62ea1a 784
NYX 0:85b3fd62ea1a 785 /* Set the Auto-Refresh number */
NYX 0:85b3fd62ea1a 786 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
NYX 0:85b3fd62ea1a 787
NYX 0:85b3fd62ea1a 788 /* Update the SDRAM state */
NYX 0:85b3fd62ea1a 789 hsdram->State = HAL_SDRAM_STATE_READY;
NYX 0:85b3fd62ea1a 790
NYX 0:85b3fd62ea1a 791 return HAL_OK;
NYX 0:85b3fd62ea1a 792 }
NYX 0:85b3fd62ea1a 793
NYX 0:85b3fd62ea1a 794 /**
NYX 0:85b3fd62ea1a 795 * @brief Returns the SDRAM memory current mode.
NYX 0:85b3fd62ea1a 796 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 797 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 798 * @retval The SDRAM memory mode.
NYX 0:85b3fd62ea1a 799 */
NYX 0:85b3fd62ea1a 800 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 801 {
NYX 0:85b3fd62ea1a 802 /* Return the SDRAM memory current mode */
NYX 0:85b3fd62ea1a 803 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
NYX 0:85b3fd62ea1a 804 }
NYX 0:85b3fd62ea1a 805
NYX 0:85b3fd62ea1a 806 /**
NYX 0:85b3fd62ea1a 807 * @}
NYX 0:85b3fd62ea1a 808 */
NYX 0:85b3fd62ea1a 809
NYX 0:85b3fd62ea1a 810 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
NYX 0:85b3fd62ea1a 811 * @brief Peripheral State functions
NYX 0:85b3fd62ea1a 812 *
NYX 0:85b3fd62ea1a 813 @verbatim
NYX 0:85b3fd62ea1a 814 ==============================================================================
NYX 0:85b3fd62ea1a 815 ##### SDRAM State functions #####
NYX 0:85b3fd62ea1a 816 ==============================================================================
NYX 0:85b3fd62ea1a 817 [..]
NYX 0:85b3fd62ea1a 818 This subsection permits to get in run-time the status of the SDRAM controller
NYX 0:85b3fd62ea1a 819 and the data flow.
NYX 0:85b3fd62ea1a 820
NYX 0:85b3fd62ea1a 821 @endverbatim
NYX 0:85b3fd62ea1a 822 * @{
NYX 0:85b3fd62ea1a 823 */
NYX 0:85b3fd62ea1a 824
NYX 0:85b3fd62ea1a 825 /**
NYX 0:85b3fd62ea1a 826 * @brief Returns the SDRAM state.
NYX 0:85b3fd62ea1a 827 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
NYX 0:85b3fd62ea1a 828 * the configuration information for SDRAM module.
NYX 0:85b3fd62ea1a 829 * @retval HAL state
NYX 0:85b3fd62ea1a 830 */
NYX 0:85b3fd62ea1a 831 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
NYX 0:85b3fd62ea1a 832 {
NYX 0:85b3fd62ea1a 833 return hsdram->State;
NYX 0:85b3fd62ea1a 834 }
NYX 0:85b3fd62ea1a 835
NYX 0:85b3fd62ea1a 836 /**
NYX 0:85b3fd62ea1a 837 * @}
NYX 0:85b3fd62ea1a 838 */
NYX 0:85b3fd62ea1a 839
NYX 0:85b3fd62ea1a 840 /**
NYX 0:85b3fd62ea1a 841 * @}
NYX 0:85b3fd62ea1a 842 */
NYX 0:85b3fd62ea1a 843 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
NYX 0:85b3fd62ea1a 844 #endif /* HAL_SDRAM_MODULE_ENABLED */
NYX 0:85b3fd62ea1a 845 /**
NYX 0:85b3fd62ea1a 846 * @}
NYX 0:85b3fd62ea1a 847 */
NYX 0:85b3fd62ea1a 848
NYX 0:85b3fd62ea1a 849 /**
NYX 0:85b3fd62ea1a 850 * @}
NYX 0:85b3fd62ea1a 851 */
NYX 0:85b3fd62ea1a 852
NYX 0:85b3fd62ea1a 853 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/